From 0ccf6a2be256c623d2315a065ee581311c4337f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Duda?= Date: Tue, 27 Mar 2018 18:32:38 +0200 Subject: [PATCH] [nrf52840] update nrfx to version 1.0.0 (#2639) Signed-off-by: Duda, Lukasz --- .../NordicSemiconductor/nrfx/CHANGELOG.md | 33 +- third_party/NordicSemiconductor/nrfx/LICENSE | 68 +- .../nrfx/drivers/include/nrf_bitmask.h | 41 +- .../nrfx/drivers/include/nrfx_adc.h | 41 +- .../nrfx/drivers/include/nrfx_clock.h | 41 +- .../nrfx/drivers/include/nrfx_comp.h | 41 +- .../nrfx/drivers/include/nrfx_gpiote.h | 41 +- .../nrfx/drivers/include/nrfx_i2s.h | 41 +- .../nrfx/drivers/include/nrfx_lpcomp.h | 41 +- .../nrfx/drivers/include/nrfx_pdm.h | 41 +- .../nrfx/drivers/include/nrfx_power.h | 41 +- .../nrfx/drivers/include/nrfx_power_clock.h | 41 +- .../nrfx/drivers/include/nrfx_ppi.h | 41 +- .../nrfx/drivers/include/nrfx_pwm.h | 41 +- .../nrfx/drivers/include/nrfx_qdec.h | 41 +- .../nrfx/drivers/include/nrfx_qspi.h | 41 +- .../nrfx/drivers/include/nrfx_rng.h | 41 +- .../nrfx/drivers/include/nrfx_rtc.h | 41 +- .../nrfx/drivers/include/nrfx_saadc.h | 41 +- .../nrfx/drivers/include/nrfx_spi.h | 89 +- .../nrfx/drivers/include/nrfx_spim.h | 41 +- .../nrfx/drivers/include/nrfx_spis.h | 213 +- .../nrfx/drivers/include/nrfx_swi.h | 41 +- .../nrfx/drivers/include/nrfx_systick.h | 41 +- .../nrfx/drivers/include/nrfx_timer.h | 41 +- .../nrfx/drivers/include/nrfx_twi.h | 41 +- .../nrfx/drivers/include/nrfx_twim.h | 41 +- .../nrfx/drivers/include/nrfx_twis.h | 41 +- .../nrfx/drivers/include/nrfx_uart.h | 41 +- .../nrfx/drivers/include/nrfx_uarte.h | 41 +- .../nrfx/drivers/include/nrfx_wdt.h | 41 +- .../nrfx/drivers/nrfx_common.h | 41 +- .../nrfx/drivers/nrfx_errors.h | 41 +- .../nrfx/drivers/src/nrfx_adc.c | 41 +- .../nrfx/drivers/src/nrfx_clock.c | 82 +- .../nrfx/drivers/src/nrfx_comp.c | 41 +- .../nrfx/drivers/src/nrfx_gpiote.c | 51 +- .../nrfx/drivers/src/nrfx_i2s.c | 41 +- .../nrfx/drivers/src/nrfx_lpcomp.c | 41 +- .../nrfx/drivers/src/nrfx_pdm.c | 41 +- .../nrfx/drivers/src/nrfx_power.c | 45 +- .../nrfx/drivers/src/nrfx_power_clock.c | 41 +- .../nrfx/drivers/src/nrfx_ppi.c | 41 +- .../nrfx/drivers/src/nrfx_pwm.c | 41 +- .../nrfx/drivers/src/nrfx_qdec.c | 41 +- .../nrfx/drivers/src/nrfx_qspi.c | 46 +- .../nrfx/drivers/src/nrfx_rng.c | 41 +- .../nrfx/drivers/src/nrfx_rtc.c | 41 +- .../nrfx/drivers/src/nrfx_saadc.c | 43 +- .../nrfx/drivers/src/nrfx_spi.c | 57 +- .../nrfx/drivers/src/nrfx_spim.c | 118 +- .../nrfx/drivers/src/nrfx_spis.c | 78 +- .../nrfx/drivers/src/nrfx_swi.c | 41 +- .../nrfx/drivers/src/nrfx_systick.c | 43 +- .../nrfx/drivers/src/nrfx_timer.c | 41 +- .../nrfx/drivers/src/nrfx_twi.c | 41 +- .../nrfx/drivers/src/nrfx_twim.c | 41 +- .../nrfx/drivers/src/nrfx_twis.c | 41 +- .../nrfx/drivers/src/nrfx_uart.c | 41 +- .../nrfx/drivers/src/nrfx_uarte.c | 41 +- .../nrfx/drivers/src/nrfx_wdt.c | 41 +- .../nrfx/drivers/src/prs/nrfx_prs.c | 41 +- .../nrfx/drivers/src/prs/nrfx_prs.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_adc.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_clock.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_comp.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_ecb.c | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_ecb.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_egu.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_gpio.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_gpiote.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_i2s.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_lpcomp.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_nvmc.c | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_nvmc.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_pdm.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_power.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_ppi.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_pwm.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_qdec.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_qspi.h | 42 +- .../NordicSemiconductor/nrfx/hal/nrf_rng.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_rtc.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_saadc.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_spi.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_spim.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_spis.h | 41 +- .../nrfx/hal/nrf_systick.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_temp.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_timer.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_twi.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_twim.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_twis.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_uart.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_uarte.h | 41 +- .../NordicSemiconductor/nrfx/hal/nrf_usbd.h | 45 +- .../NordicSemiconductor/nrfx/hal/nrf_wdt.h | 41 +- .../nrfx/mdk/compiler_abstraction.h | 2 +- .../nrfx/mdk/gcc_startup_nrf52840.S | 2 +- .../NordicSemiconductor/nrfx/mdk/nrf.h | 6 +- .../nrfx/mdk/nrf51_to_nrf52.h | 2 +- .../nrfx/mdk/nrf51_to_nrf52840.h | 2 +- .../NordicSemiconductor/nrfx/mdk/nrf52840.h | 899 +- .../NordicSemiconductor/nrfx/mdk/nrf52840.svd | 8938 +++++++++-------- .../nrfx/mdk/nrf52840_bitfields.h | 1804 ++-- .../nrfx/mdk/nrf52840_peripherals.h | 2 +- .../nrfx/mdk/nrf_peripherals.h | 107 +- .../nrfx/mdk/system_nrf52840.c | 2 +- .../nrfx/mdk/system_nrf52840.h | 2 +- third_party/NordicSemiconductor/nrfx/nrfx.h | 41 +- .../nrfx/soc/nrfx_coredep.h | 43 +- .../NordicSemiconductor/nrfx/soc/nrfx_irqs.h | 41 +- .../nrfx/soc/nrfx_irqs_nrf51.h | 41 +- .../nrfx/soc/nrfx_irqs_nrf52810.h | 41 +- .../nrfx/soc/nrfx_irqs_nrf52832.h | 41 +- .../nrfx/soc/nrfx_irqs_nrf52840.h | 41 +- .../nrfx/templates/nRF51/nrfx_config.h | 20 - .../nrfx/templates/nRF52810/nrfx_config.h | 20 - .../nrfx/templates/nRF52832/nrfx_config.h | 20 - .../nrfx/templates/nRF52840/nrfx_config.h | 32 +- .../nrfx/templates/nrfx_glue.h | 41 +- .../nrfx/templates/nrfx_log.h | 41 +- 122 files changed, 7944 insertions(+), 8702 deletions(-) diff --git a/third_party/NordicSemiconductor/nrfx/CHANGELOG.md b/third_party/NordicSemiconductor/nrfx/CHANGELOG.md index bd75484c1..fe4f2b97a 100644 --- a/third_party/NordicSemiconductor/nrfx/CHANGELOG.md +++ b/third_party/NordicSemiconductor/nrfx/CHANGELOG.md @@ -1,26 +1,29 @@ # Changelog All notable changes to this project are documented in this file. -## [Unreleased] +## [1.0.0] - 2018-03-21 ### Added -- Added wait-for function to improve time-out functionality in QSPI and SAADC drivers. -- Added glue layer for interrupt pending set/clear and is set functions. -- Added new interrupts and events to UARTE HAL. +- Added the NRFX_WAIT_FOR macro to improve the time-out functionality in QSPI and SAADC drivers. +- Added glue layer macros for checking and modifying the pending status of interrupts. +- Added new enumeration values for interrupts and events in the UARTE HAL. +- Implemented workarounds for nRF52 anomalies 192 and 201 in the CLOCK driver. +- Implemented workaround for nRF52840 anomaly 122 in the QSPI driver. +- Implemented workaround for nRF52840 anomaly 198 in the SPIM driver. ### Changed -- Extended input pin configuration in GPIOTE driver. -- Unified the way of checking if required event handler was provided. Now, all drivers do it with assertion. -- Improved condition checking in uninit and init functions in SAADC driver. -- Enabled RNG bias correction by default. -- Updated MDK to 8.15.4. -- Refactored ADC driver and HAL. -- Corrected TIMER asserts to make it usable with PPI in debug. -- Improved buffer handling in I2S driver. The API of the driver has been sligthly modified. +- Updated MDK to 8.16.0. +- Extended input pin configuration in the GPIOTE driver. +- Unified the way of checking if a required event handler was provided. Now, all drivers do it with assertions. +- Changed the RNG bias correction configuration option to be enabled by default. +- Refactored the ADC driver and HAL. +- Corrected assertions in the TIMER driver to make it usable in debug version with PPI. +- Improved buffer handling in the I2S driver. The API of the driver has been sligthly modified. +- Enhanced SPIS driver API: added the "p_context" parameter, allowed NULL pointers for zero-length buffers. ### Fixed -- Fixed result value casting in TEMP HAL. -- Fixed types of conversion result and buffer size in ADC HAL and driver. -- Fixed timeout in SAADC driver in abort function. +- Fixed result value casting in the TEMP HAL. +- Fixed types of conversion result and buffer size in the ADC HAL and driver. +- Fixed time-out in the SAADC driver in abort function. ## [0.8.0] - 2017-12-20 ### Added diff --git a/third_party/NordicSemiconductor/nrfx/LICENSE b/third_party/NordicSemiconductor/nrfx/LICENSE index 1e45b06f4..67c8788b2 100644 --- a/third_party/NordicSemiconductor/nrfx/LICENSE +++ b/third_party/NordicSemiconductor/nrfx/LICENSE @@ -1,39 +1,29 @@ -/** - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +Copyright (c) 2017 - 2018, Nordic Semiconductor ASA +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h index 8f2ac3626..f1f593048 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_BITMASK_H diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h index e28d52aaa..dbb729304 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_ADC_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h index 8a5e184af..27cd4236a 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_CLOCK_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h index 8b4ee4400..e337429df 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_COMP_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h index ee79e6d94..24e9eed90 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_GPIOTE_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h index f64fa210c..f7766a615 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_I2S_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h index f6744a332..6acecc0c8 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_LPCOMP_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h index f2201c97f..a0cdda1a9 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_PDM_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h index c7bac84d3..34f15f332 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_POWER_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h index c63dbcf47..cc3a59432 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_POWER_CLOCK_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h index f7b9b24d4..69b4d7707 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_PPI_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h index c4c15dd49..d65dbb4f6 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_PWM_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h index 9f636d5b9..7d6bdfb9a 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_QDEC_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h index 6f19f105b..9259441b8 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_QSPI_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h index 431f872f1..56ec5f75b 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_RNG_H__ #define NRFX_RNG_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h index aec1b7deb..8e84051c3 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_RTC_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h index 76532d4da..df5f3eaac 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_SAADC_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h index 19af4de0c..cacf1ad69 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_SPI_H__ @@ -93,40 +84,6 @@ enum { */ #define NRFX_SPI_PIN_NOT_USED 0xFF -/** - * @brief SPI data rates. - */ -typedef enum -{ - NRFX_SPI_FREQ_125K = NRF_SPI_FREQ_125K, ///< 125 kbps. - NRFX_SPI_FREQ_250K = NRF_SPI_FREQ_250K, ///< 250 kbps. - NRFX_SPI_FREQ_500K = NRF_SPI_FREQ_500K, ///< 500 kbps. - NRFX_SPI_FREQ_1M = NRF_SPI_FREQ_1M, ///< 1 Mbps. - NRFX_SPI_FREQ_2M = NRF_SPI_FREQ_2M, ///< 2 Mbps. - NRFX_SPI_FREQ_4M = NRF_SPI_FREQ_4M, ///< 4 Mbps. - NRFX_SPI_FREQ_8M = NRF_SPI_FREQ_8M ///< 8 Mbps. -} nrfx_spi_frequency_t; - -/** - * @brief SPI modes. - */ -typedef enum -{ - NRFX_SPI_MODE_0 = NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock. - NRFX_SPI_MODE_1 = NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock. - NRFX_SPI_MODE_2 = NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock. - NRFX_SPI_MODE_3 = NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock. -} nrfx_spi_mode_t; - -/** - * @brief SPI bit orders. - */ -typedef enum -{ - NRFX_SPI_BIT_ORDER_MSB_FIRST = NRF_SPI_BIT_ORDER_MSB_FIRST, ///< Most significant bit shifted out first. - NRFX_SPI_BIT_ORDER_LSB_FIRST = NRF_SPI_BIT_ORDER_LSB_FIRST ///< Least significant bit shifted out first. -} nrfx_spi_bit_order_t; - /** * @brief SPI master driver instance configuration structure. */ @@ -149,9 +106,9 @@ typedef struct uint8_t orc; ///< Over-run character. /**< This character is used when all bytes from the TX buffer are sent, but the transfer continues due to RX. */ - nrfx_spi_frequency_t frequency; ///< SPI frequency. - nrfx_spi_mode_t mode; ///< SPI mode. - nrfx_spi_bit_order_t bit_order; ///< SPI bit order. + nrf_spi_frequency_t frequency; ///< SPI frequency. + nrf_spi_mode_t mode; ///< SPI mode. + nrf_spi_bit_order_t bit_order; ///< SPI bit order. } nrfx_spi_config_t; /** @@ -165,9 +122,9 @@ typedef struct .ss_pin = NRFX_SPI_PIN_NOT_USED, \ .irq_priority = NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY, \ .orc = 0xFF, \ - .frequency = NRFX_SPI_FREQ_4M, \ - .mode = NRFX_SPI_MODE_0, \ - .bit_order = NRFX_SPI_BIT_ORDER_MSB_FIRST, \ + .frequency = NRF_SPI_FREQ_4M, \ + .mode = NRF_SPI_MODE_0, \ + .bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST, \ } /** @@ -179,7 +136,7 @@ typedef struct size_t tx_length; ///< TX buffer length. uint8_t * p_rx_buffer; ///< Pointer to RX buffer. size_t rx_length; ///< RX buffer length. -}nrfx_spi_xfer_desc_t; +} nrfx_spi_xfer_desc_t; /** * @brief Macro for setting up single transfer descriptor. diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h index 3490f1102..f9763dfa9 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_SPIM_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h index 0eb6fa106..5ea069930 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_SPIS_H__ @@ -56,48 +47,6 @@ extern "C" { * @brief SPI Slave peripheral driver. */ -#define NRFX_SPIS_DEFAULT_CSN_PULLUP NRF_GPIO_PIN_NOPULL /**< Default pull-up configuration of the SPI CS. */ -#define NRFX_SPIS_DEFAULT_MISO_DRIVE NRF_GPIO_PIN_S0S1 /**< Default drive configuration of the SPI MISO. */ - -/** -* @brief This value can be provided instead of a pin number for the signals MOSI -* and MISO to specify that the given signal is not used and therefore -* does not need to be connected to a pin. -*/ -#define NRFX_SPIS_PIN_NOT_USED 0xFF - -/** @brief SPIS transaction bit order definitions. */ -typedef enum -{ - NRFX_SPIS_BIT_ORDER_LSB_FIRST = NRF_SPIS_BIT_ORDER_LSB_FIRST, /**< Least significant bit shifted out first. */ - NRFX_SPIS_BIT_ORDER_MSB_FIRST = NRF_SPIS_BIT_ORDER_MSB_FIRST /**< Most significant bit shifted out first. */ -} nrfx_spis_endian_t; - -/** @brief SPIS mode definitions for clock polarity and phase. */ -typedef enum -{ - NRFX_SPIS_MODE_0 = NRF_SPIS_MODE_0, /**< (CPOL = 0, CPHA = 0). */ - NRFX_SPIS_MODE_1 = NRF_SPIS_MODE_1, /**< (CPOL = 0, CPHA = 1). */ - NRFX_SPIS_MODE_2 = NRF_SPIS_MODE_2, /**< (CPOL = 1, CPHA = 0). */ - NRFX_SPIS_MODE_3 = NRF_SPIS_MODE_3 /**< (CPOL = 1, CPHA = 1). */ -} nrfx_spis_mode_t; - -/** @brief Event callback function event definitions. */ -typedef enum -{ - NRFX_SPIS_BUFFERS_SET_DONE, /**< Memory buffer set event. Memory buffers have been set successfully to the SPI slave device, and SPI transactions can be done. */ - NRFX_SPIS_XFER_DONE, /**< SPI transaction event. SPI transaction has been completed. */ - NRFX_SPIS_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} nrfx_spis_event_type_t; - -/** @brief Structure containing the event context from the SPI slave driver. */ -typedef struct -{ - nrfx_spis_event_type_t evt_type; //!< Type of event. - size_t rx_amount; //!< Number of bytes received in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. - size_t tx_amount; //!< Number of bytes transmitted in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. -} nrfx_spis_event_t; - /** @brief SPI slave driver instance data structure. */ typedef struct { @@ -105,13 +54,6 @@ typedef struct uint8_t drv_inst_idx; //!< Driver instance index. } nrfx_spis_t; -/** @brief Macro for creating an SPI slave driver instance. */ -#define NRFX_SPIS_INSTANCE(id) \ -{ \ - .p_reg = NRFX_CONCAT_2(NRF_SPIS, id), \ - .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPIS, id, _INST_IDX), \ -} - enum { #if NRFX_CHECK(NRFX_SPIS0_ENABLED) NRFX_SPIS0_INST_IDX, @@ -125,50 +67,91 @@ enum { NRFX_SPIS_ENABLED_COUNT }; +/** @brief Macro for creating an SPI slave driver instance. */ +#define NRFX_SPIS_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_SPIS, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPIS, id, _INST_IDX), \ +} + +/** + * @brief This value can be provided instead of a pin number for the signals MOSI + * and MISO to specify that the given signal is not used and therefore + * does not need to be connected to a pin. + */ +#define NRFX_SPIS_PIN_NOT_USED 0xFF + +/** @brief Default pull-up configuration of the SPI CS. */ +#define NRFX_SPIS_DEFAULT_CSN_PULLUP NRF_GPIO_PIN_NOPULL +/** @brief Default drive configuration of the SPI MISO. */ +#define NRFX_SPIS_DEFAULT_MISO_DRIVE NRF_GPIO_PIN_S0S1 + +/** @brief SPI slave driver event types. */ +typedef enum +{ + NRFX_SPIS_BUFFERS_SET_DONE, //!< Memory buffer set event. Memory buffers have been set successfully to the SPI slave device, and SPI transaction can be done. + NRFX_SPIS_XFER_DONE, //!< SPI transaction event. SPI transaction has been completed. + NRFX_SPIS_EVT_TYPE_MAX //!< Enumeration upper bound. +} nrfx_spis_evt_type_t; + +/** @brief SPI slave driver event structure. */ +typedef struct +{ + nrfx_spis_evt_type_t evt_type; //!< Type of the event. + size_t rx_amount; //!< Number of bytes received in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. + size_t tx_amount; //!< Number of bytes transmitted in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. +} nrfx_spis_evt_t; + /** @brief SPI slave instance default configuration. */ -#define NRFX_SPIS_DEFAULT_CONFIG \ -{ \ - .sck_pin = NRFX_SPIS_PIN_NOT_USED, \ - .mosi_pin = NRFX_SPIS_PIN_NOT_USED, \ - .miso_pin = NRFX_SPIS_PIN_NOT_USED, \ - .csn_pin = NRFX_SPIS_PIN_NOT_USED, \ - .miso_drive = NRFX_SPIS_DEFAULT_MISO_DRIVE, \ - .csn_pullup = NRFX_SPIS_DEFAULT_CSN_PULLUP, \ - .orc = NRFX_SPIS_DEFAULT_ORC, \ - .def = NRFX_SPIS_DEFAULT_DEF, \ - .mode = (nrfx_spis_mode_t)NRFX_SPIS_DEFAULT_MODE, \ - .bit_order = (nrfx_spis_endian_t)NRFX_SPIS_DEFAULT_BIT_ORDER, \ - .irq_priority = NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY, \ +#define NRFX_SPIS_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRFX_SPIS_PIN_NOT_USED, \ + .mosi_pin = NRFX_SPIS_PIN_NOT_USED, \ + .miso_pin = NRFX_SPIS_PIN_NOT_USED, \ + .csn_pin = NRFX_SPIS_PIN_NOT_USED, \ + .mode = NRF_SPIS_MODE_0, \ + .bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST, \ + .csn_pullup = NRFX_SPIS_DEFAULT_CSN_PULLUP, \ + .miso_drive = NRFX_SPIS_DEFAULT_MISO_DRIVE, \ + .def = NRFX_SPIS_DEFAULT_DEF, \ + .orc = NRFX_SPIS_DEFAULT_ORC, \ + .irq_priority = NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY, \ } /** @brief SPI peripheral device configuration data. */ typedef struct { - uint32_t miso_pin; //!< SPI MISO pin (optional). - /**< Set @ref NRFX_SPIS_PIN_NOT_USED - * if this signal is not needed. */ - uint32_t mosi_pin; //!< SPI MOSI pin (optional). - /**< Set @ref NRFX_SPIS_PIN_NOT_USED - * if this signal is not needed. */ - uint32_t sck_pin; //!< SPI SCK pin. - uint32_t csn_pin; //!< SPI CSN pin. - nrfx_spis_mode_t mode; //!< SPI mode. - nrfx_spis_endian_t bit_order; //!< SPI transaction bit order. - nrf_gpio_pin_pull_t csn_pullup; //!< CSN pin pull-up configuration. - nrf_gpio_pin_drive_t miso_drive; //!< MISO pin drive configuration. - uint8_t def; //!< Character clocked out in case of an ignored transaction. - uint8_t orc; //!< Character clocked out after an over-read of the transmit buffer. - uint8_t irq_priority; //!< Interrupt priority. + uint32_t miso_pin; //!< SPI MISO pin (optional). + /**< Set @ref NRFX_SPIS_PIN_NOT_USED + * if this signal is not needed. */ + uint32_t mosi_pin; //!< SPI MOSI pin (optional). + /**< Set @ref NRFX_SPIS_PIN_NOT_USED + * if this signal is not needed. */ + uint32_t sck_pin; //!< SPI SCK pin. + uint32_t csn_pin; //!< SPI CSN pin. + nrf_spis_mode_t mode; //!< SPI mode. + nrf_spis_bit_order_t bit_order; //!< SPI transaction bit order. + nrf_gpio_pin_pull_t csn_pullup; //!< CSN pin pull-up configuration. + nrf_gpio_pin_drive_t miso_drive; //!< MISO pin drive configuration. + uint8_t def; //!< Character clocked out in case of an ignored transaction. + uint8_t orc; //!< Character clocked out after an over-read of the transmit buffer. + uint8_t irq_priority; //!< Interrupt priority. } nrfx_spis_config_t; -/** @brief SPI slave event callback function type. +/** + * @brief SPI slave driver event handler type. * - * @param[in] event SPI slave driver event. + * @param[in] p_event Pointer to the event structure. The structure is + * allocated on the stack so it is valid only until + * the event handler returns. + * @param[in] p_context Context set on initialization. */ -typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_event_t event); +typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_evt_t const * p_event, + void * p_context); -/** @brief Function for initializing the SPI slave driver instance. +/** + * @brief Function for initializing the SPI slave driver instance. * * @note When the nRF52 Anomaly 109 workaround for SPIS is enabled, this function * initializes the GPIOTE driver as well, and uses one of GPIOTE channels @@ -178,6 +161,7 @@ typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_event_t event); * @param[in] p_config Pointer to the structure with initial configuration. * @param[in] event_handler Function to be called by the SPI slave driver upon event. * Must not be NULL. + * @param[in] p_context Context passed to the event handler. * * @retval NRFX_SUCCESS If the initialization was successful. * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. @@ -192,7 +176,8 @@ typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_event_t event); */ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, nrfx_spis_config_t const * p_config, - nrfx_spis_event_handler_t event_handler); + nrfx_spis_event_handler_t event_handler, + void * p_context); /** * @brief Function for uninitializing the SPI slave driver instance. @@ -201,14 +186,15 @@ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, */ void nrfx_spis_uninit(nrfx_spis_t const * const p_instance); -/** @brief Function for preparing the SPI slave instance for a single SPI transaction. +/** + * @brief Function for preparing the SPI slave instance for a single SPI transaction. * * This function prepares the SPI slave device to be ready for a single SPI transaction. It configures * the SPI slave device to use the memory supplied with the function call in SPI transactions. * * When either the memory buffer configuration or the SPI transaction has been * completed, the event callback function will be called with the appropriate event - * @ref nrfx_spis_event_type_t. Note that the callback function can be called before returning from + * @ref nrfx_spis_evt_type_t. Note that the callback function can be called before returning from * this function, because it is called from the SPI slave interrupt context. * * @note This function can be called from the callback function context. @@ -221,13 +207,12 @@ void nrfx_spis_uninit(nrfx_spis_t const * const p_instance); * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. * * @param[in] p_instance Pointer to the driver instance structure. - * @param[in] p_tx_buffer Pointer to the TX buffer. - * @param[in] p_rx_buffer Pointer to the RX buffer. + * @param[in] p_tx_buffer Pointer to the TX buffer. Can be NULL when the buffer length is zero. + * @param[in] p_rx_buffer Pointer to the RX buffer. Can be NULL when the buffer length is zero. * @param[in] tx_buffer_length Length of the TX buffer in bytes. * @param[in] rx_buffer_length Length of the RX buffer in bytes. * * @retval NRFX_SUCCESS If the operation was successful. - * @retval NRFX_ERROR_NULL If the operation failed because a NULL pointer was supplied. * @retval NRFX_ERROR_INVALID_STATE If the operation failed because the SPI slave device is in an incorrect state. * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data * RAM region. @@ -235,9 +220,9 @@ void nrfx_spis_uninit(nrfx_spis_t const * const p_instance); * @retval NRFX_ERROR_INTERNAL If the operation failed because of an internal error. */ nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance, - uint8_t const * p_tx_buffer, + uint8_t const * p_tx_buffer, size_t tx_buffer_length, - uint8_t * p_rx_buffer, + uint8_t * p_rx_buffer, size_t rx_buffer_length); diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h index 92416aef1..7c297fe42 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_SWI_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h index 162907446..b6c42f6c8 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_SYSTICK_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h index b493f239e..2fbfc569d 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_TIMER_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h index c5b85908d..ab68c6d6a 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_TWI_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h index 0b1be22fe..211a66943 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_TWIM_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h index 56308680f..a424a1e98 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_TWIS_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h index d55beb724..3af649b5f 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_UART_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h index e5deec0b5..4ce3ae7d7 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_UARTE_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h index be98a3853..8f82ebcdc 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_WDT_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h index 3b47ac204..2b17f7d0e 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_COMMON_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h index f900be811..f2fed763b 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_ERRORS_H__ diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_adc.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_adc.c index cbe51facd..96dc9824c 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_adc.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_adc.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c index 6d087cb1e..8bda4a912 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -71,6 +62,17 @@ extern bool nrfx_power_irq_enabled; #define CALIBRATION_SUPPORT 0 #endif +#if defined(NRF52810_XXAA) || \ + defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ + defined(NRF52840_XXAA) +// Enable workaround for nRF52 anomaly 192 (LFRC oscillator frequency is wrong +// after calibration, exceeding 500 ppm). +#define USE_WORKAROUND_FOR_ANOMALY_192 + +// Enable workaround for nRF52 anomaly 201 (EVENTS_HFCLKSTARTED might be generated twice). +#define USE_WORKAROUND_FOR_ANOMALY_201 +#endif + typedef enum { CAL_STATE_IDLE, @@ -82,6 +84,10 @@ typedef struct { nrfx_clock_event_handler_t event_handler; bool module_initialized; /*< Indicate the state of module */ +#if defined(USE_WORKAROUND_FOR_ANOMALY_201) + bool hfclk_started; /*< Anomaly 201 workaround. */ +#endif + #if CALIBRATION_SUPPORT volatile nrfx_clock_cal_state_t cal_state; #endif // CALIBRATION_SUPPORT @@ -97,7 +103,7 @@ static nrfx_clock_cb_t m_clock_cb; bool nrfx_clock_irq_enabled; #endif -#ifdef NRF52832_XXAA +#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) // ANOMALY 132 - LFCLK needs to avoid frame from 66us to 138us after LFCLK stop. This solution // applies delay of 138us before starting LFCLK. @@ -140,7 +146,7 @@ static void nrfx_clock_anomaly_132(void) CoreDebug->DEMCR = core_debug; } -#endif // NRF52832_XXAA +#endif // defined(NRF52832_XXAA) || defined(NRF52832_XXAB) nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler) { @@ -158,6 +164,9 @@ nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler) #endif m_clock_cb.event_handler = event_handler; m_clock_cb.module_initialized = true; +#if defined(USE_WORKAROUND_FOR_ANOMALY_201) + m_clock_cb.hfclk_started = false; +#endif } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); @@ -212,7 +221,7 @@ void nrfx_clock_lfclk_start(void) nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED); nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK); -#ifdef NRF52832_XXAA +#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) nrfx_clock_anomaly_132(); #endif @@ -241,6 +250,9 @@ void nrfx_clock_hfclk_stop(void) nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP); while (nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY)) {} +#if defined(USE_WORKAROUND_FOR_ANOMALY_201) + m_clock_cb.hfclk_started = false; +#endif } nrfx_err_t nrfx_clock_calibration_start(void) @@ -262,6 +274,9 @@ nrfx_err_t nrfx_clock_calibration_start(void) nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE); nrf_clock_int_enable(NRF_CLOCK_INT_DONE_MASK); m_clock_cb.cal_state = CAL_STATE_CAL; +#if defined(USE_WORKAROUND_FOR_ANOMALY_192) + *(volatile uint32_t *)0x40000C34 = 0x00000002; +#endif nrf_clock_task_trigger(NRF_CLOCK_TASK_CAL); } else @@ -308,7 +323,15 @@ void nrfx_clock_irq_handler(void) NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_HFCLKSTARTED)); nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK); +#if defined(USE_WORKAROUND_FOR_ANOMALY_201) + if (!m_clock_cb.hfclk_started) + { + m_clock_cb.hfclk_started = true; + m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED); + } +#else m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED); +#endif } if (nrf_clock_event_check(NRF_CLOCK_EVENT_LFCLKSTARTED)) { @@ -330,6 +353,9 @@ void nrfx_clock_irq_handler(void) if (nrf_clock_event_check(NRF_CLOCK_EVENT_DONE)) { +#if defined(USE_WORKAROUND_FOR_ANOMALY_192) + *(volatile uint32_t *)0x40000C34 = 0x00000000; +#endif nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE); NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_DONE)); nrf_clock_int_disable(NRF_CLOCK_INT_DONE_MASK); diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_comp.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_comp.c index 63572d5ca..618ec7747 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_comp.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_comp.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_gpiote.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_gpiote.c index 61fb15408..b5e18fe5d 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_gpiote.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_gpiote.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -376,7 +367,7 @@ void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(pin < NUMBER_OF_PINS); NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)) + NRFX_ASSERT(!pin_in_use_by_te(pin)); nrf_gpio_pin_set(pin); } @@ -386,7 +377,7 @@ void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(pin < NUMBER_OF_PINS); NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)) + NRFX_ASSERT(!pin_in_use_by_te(pin)); nrf_gpio_pin_clear(pin); } @@ -396,7 +387,7 @@ void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(pin < NUMBER_OF_PINS); NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(!pin_in_use_by_te(pin)) + NRFX_ASSERT(!pin_in_use_by_te(pin)); nrf_gpio_pin_toggle(pin); } @@ -406,7 +397,7 @@ void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(pin < NUMBER_OF_PINS); NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)) + NRFX_ASSERT(pin_in_use_by_te(pin)); nrf_gpiote_task_enable((uint32_t)m_cb.pin_assignments[pin]); } @@ -416,7 +407,7 @@ void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin) { NRFX_ASSERT(pin < NUMBER_OF_PINS); NRFX_ASSERT(pin_in_use(pin)); - NRFX_ASSERT(pin_in_use_by_te(pin)) + NRFX_ASSERT(pin_in_use_by_te(pin)); nrf_gpiote_task_disable((uint32_t)m_cb.pin_assignments[pin]); } diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_i2s.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_i2s.c index 35beaab67..28b412556 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_i2s.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_i2s.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_lpcomp.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_lpcomp.c index 024eda661..d50878902 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_lpcomp.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_lpcomp.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pdm.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pdm.c index db0945e7c..c3eaf1639 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pdm.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pdm.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c index a8d9089b7..c2d7a5d8b 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -304,6 +295,8 @@ void nrfx_power_irq_handler(void) #endif } +#endif // NRFX_CHECK(NRFX_POWER_ENABLED) + #if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) void nrfx_power_clock_irq_handler(void) { @@ -311,5 +304,3 @@ void nrfx_power_clock_irq_handler(void) nrfx_clock_irq_handler(); } #endif - -#endif // NRFX_CHECK(NRFX_POWER_ENABLED) diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power_clock.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power_clock.c index ff69bf714..1be9ade0d 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power_clock.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power_clock.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_ppi.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_ppi.c index 067ba18d6..546aae7cf 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_ppi.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_ppi.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pwm.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pwm.c index 3a6581f57..d00ee5085 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pwm.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_pwm.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qdec.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qdec.c index c7994d13e..e49c94d9f 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qdec.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qdec.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c index 1b64295f4..146cdd034 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -265,6 +256,11 @@ void nrfx_qspi_uninit(void) nrf_qspi_disable(NRF_QSPI); + nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_DEACTIVATE); + + // Workaround for nRF52840 anomaly 122: Current consumption is too high. + *(volatile uint32_t *)0x40029054ul = 1ul; + NRFX_IRQ_DISABLE(QSPI_IRQn); nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rng.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rng.c index a179f7ca8..3b33edaf0 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rng.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rng.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rtc.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rtc.c index 95e860571..5546c10eb 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rtc.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_rtc.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_saadc.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_saadc.c index 2f293dd26..1f6989980 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_saadc.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_saadc.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -342,7 +333,7 @@ nrfx_err_t nrfx_saadc_channel_init(uint8_t chan nrfx_err_t nrfx_saadc_channel_uninit(uint8_t channel) { - NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT) + NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); nrfx_err_t err_code; diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spi.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spi.c index ecf5926f1..99d29f6bb 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spi.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spi.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -66,6 +57,7 @@ typedef struct // [no need for 'volatile' attribute for the following members, as they // are not concurrently used in IRQ handlers and main line code] uint8_t ss_pin; + uint8_t miso_pin; uint8_t orc; size_t bytes_transferred; @@ -125,7 +117,7 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, // 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1); // according to the reference manual guidelines this pin and its input // buffer must always be connected for the SPI to work. - if (p_config->mode <= NRFX_SPI_MODE_1) + if (p_config->mode <= NRF_SPI_MODE_1) { nrf_gpio_pin_clear(p_config->sck_pin); } @@ -160,6 +152,7 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, { miso_pin = NRF_SPI_PIN_NOT_CONNECTED; } + m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin; // - Slave Select (optional) - output with initial value 1 (inactive). if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED) { @@ -170,11 +163,8 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, NRF_SPI_Type * p_spi = p_instance->p_reg; nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin); - nrf_spi_frequency_set(p_spi, - (nrf_spi_frequency_t)p_config->frequency); - nrf_spi_configure(p_spi, - (nrf_spi_mode_t)p_config->mode, - (nrf_spi_bit_order_t)p_config->bit_order); + nrf_spi_frequency_set(p_spi, p_config->frequency); + nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order); m_cb[p_instance->drv_inst_idx].orc = p_config->orc; @@ -215,6 +205,11 @@ void nrfx_spi_uninit(nrfx_spi_t const * const p_instance) { nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK); } + + if (p_cb->miso_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_cfg_default(p_cb->miso_pin); + } nrf_spi_disable(p_spi); #if NRFX_CHECK(NRFX_PRS_ENABLED) diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spim.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spim.c index 6b734f22b..e7fe76151 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spim.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spim.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -110,6 +101,7 @@ typedef struct // are not concurrently used in IRQ handlers and main line code] bool ss_active_high; uint8_t ss_pin; + uint8_t miso_pin; uint8_t orc; #if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) @@ -119,6 +111,47 @@ typedef struct } spim_control_block_t; static spim_control_block_t m_cb[NRFX_SPIM_ENABLED_COUNT]; +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + +// Workaround for nRF52840 anomaly 198: SPIM3 transmit data might be corrupted. + +static uint32_t m_anomaly_198_preserved_value; + +static void anomaly_198_enable(uint8_t const * p_buffer, size_t buf_len) +{ + m_anomaly_198_preserved_value = *((volatile uint32_t *)0x40000E00); + + if (buf_len == 0) + { + return; + } + uint32_t buffer_end_addr = ((uint32_t)p_buffer) + buf_len; + uint32_t block_addr = ((uint32_t)p_buffer) & ~0x1FFF; + uint32_t block_flag = (1UL << ((block_addr >> 13) & 0xFFFF)); + uint32_t occupied_blocks = 0; + + if (block_addr >= 0x20010000) + { + occupied_blocks = (1UL << 8); + } + else + { + do { + occupied_blocks |= block_flag; + block_flag <<= 1; + block_addr += 0x2000; + } while ((block_addr < buffer_end_addr) && (block_addr < 0x20012000)); + } + + *((volatile uint32_t *)0x40000E00) = occupied_blocks; +} + +static void anomaly_198_disable(void) +{ + *((volatile uint32_t *)0x40000E00) = m_anomaly_198_preserved_value; +} +#endif // NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, nrfx_spim_config_t const * p_config, nrfx_spim_evt_handler_t handler, @@ -228,6 +261,7 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, { miso_pin = NRF_SPIM_PIN_NOT_CONNECTED; } + m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin; // - Slave Select (optional) - output with initial value 1 (inactive). if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED) { @@ -270,11 +304,8 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin); - nrf_spim_frequency_set(p_spim, - (nrf_spim_frequency_t)p_config->frequency); - nrf_spim_configure(p_spim, - (nrf_spim_mode_t)p_config->mode, - (nrf_spim_bit_order_t)p_config->bit_order); + nrf_spim_frequency_set(p_spim, p_config->frequency); + nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order); nrf_spim_orc_set(p_spim, p_config->orc); @@ -323,6 +354,11 @@ void nrfx_spim_uninit(nrfx_spim_t const * const p_instance) p_cb->transfer_in_progress = false; } } + + if (p_cb->miso_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_cfg_default(p_cb->miso_pin); + } nrf_spim_disable(p_spim); #if NRFX_CHECK(NRFX_PRS_ENABLED) @@ -338,7 +374,7 @@ nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance, uint32_t flags, uint8_t cmd_length) { - ASSERT(cmd_length <= NRF_SPIM_DCX_CNT_ALL_CMD) + NRFX_ASSERT(cmd_length <= NRF_SPIM_DCX_CNT_ALL_CMD); nrf_spim_dcx_cnt_set((NRF_SPIM_Type *)p_instance->p_reg, cmd_length); return nrfx_spim_xfer(p_instance, p_xfer_desc, 0); } @@ -432,6 +468,13 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length); nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, p_xfer_desc->rx_length); +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + if (p_spim == NRF_SPIM3) + { + anomaly_198_enable(p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length); + } +#endif + nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); spim_list_enable_handle(p_spim, flags); @@ -455,6 +498,13 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, if (!p_cb->handler) { while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)){} + +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + if (p_spim == NRF_SPIM3) + { + anomaly_198_disable(); + } +#endif if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) { #if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) @@ -585,6 +635,12 @@ static void irq_handler(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)) { +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + if (p_spim == NRF_SPIM3) + { + anomaly_198_disable(); + } +#endif nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); NRFX_ASSERT(p_cb->handler); NRFX_LOG_DEBUG("Event: NRF_SPIM_EVENT_END."); diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spis.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spis.c index 06f4b4e17..416135b60 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spis.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_spis.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -118,13 +109,15 @@ typedef struct volatile uint8_t * rx_buffer; //!< SPI slave RX buffer. nrfx_drv_state_t state; //!< driver initialization state. volatile nrfx_spis_state_t spi_state; //!< SPI slave state. + void * p_context; //!< Context set on initialization. } spis_cb_t; static spis_cb_t m_cb[NRFX_SPIS_ENABLED_COUNT]; nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, nrfx_spis_config_t const * p_config, - nrfx_spis_event_handler_t event_handler) + nrfx_spis_event_handler_t event_handler, + void * p_context) { NRFX_ASSERT(p_config); NRFX_ASSERT(event_handler); @@ -142,7 +135,7 @@ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, return err_code; } - if ((uint32_t)p_config->mode > (uint32_t)NRFX_SPIS_MODE_3) + if ((uint32_t)p_config->mode > (uint32_t)NRF_SPIS_MODE_3) { err_code = NRFX_ERROR_INVALID_PARAM; NRFX_LOG_WARNING("Function: %s, error code: %s.", @@ -227,8 +220,7 @@ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, nrf_spis_tx_buffer_set(p_spis, NULL, 0); // Configure SPI mode. - nrf_spis_configure(p_spis, (nrf_spis_mode_t) p_config->mode, - (nrf_spis_bit_order_t) p_config->bit_order); + nrf_spis_configure(p_spis, p_config->mode, p_config->bit_order); // Configure DEF and ORC characters. nrf_spis_def_set(p_spis, p_config->def); @@ -241,8 +233,9 @@ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, // Enable END_ACQUIRE shortcut. nrf_spis_shorts_enable(p_spis, NRF_SPIS_SHORT_END_ACQUIRE); - m_cb[p_instance->drv_inst_idx].spi_state = SPIS_STATE_INIT; - m_cb[p_instance->drv_inst_idx].handler = event_handler; + p_cb->spi_state = SPIS_STATE_INIT; + p_cb->handler = event_handler; + p_cb->p_context = p_context; #if defined(USE_DMA_ISSUE_WORKAROUND) // Configure a GPIOTE channel to generate interrupts on each falling edge @@ -280,11 +273,8 @@ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, // Enable SPI slave device. nrf_spis_enable(p_spis); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; + NRFX_LOG_INFO("Initialized."); + return NRFX_SUCCESS; } @@ -306,7 +296,7 @@ void nrfx_spis_uninit(nrfx_spis_t const * const p_instance) #endif p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; - NRFX_LOG_INFO("Initialized."); + NRFX_LOG_INFO("Uninitialized."); } @@ -314,7 +304,7 @@ void nrfx_spis_uninit(nrfx_spis_t const * const p_instance) static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis, spis_cb_t * p_cb) { - nrfx_spis_event_t event; + nrfx_spis_evt_t event; switch (p_cb->spi_state) { @@ -328,7 +318,7 @@ static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis, event.tx_amount = 0; NRFX_ASSERT(p_cb->handler != NULL); - p_cb->handler(event); + p_cb->handler(&event, p_cb->p_context); break; case SPIS_XFER_COMPLETED: @@ -340,7 +330,7 @@ static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis, NRFX_LOG_HEXDUMP_DEBUG((uint8_t const *)p_cb->rx_buffer, event.rx_amount * sizeof(p_cb->rx_buffer[0])); NRFX_ASSERT(p_cb->handler != NULL); - p_cb->handler(event); + p_cb->handler(&event, p_cb->p_context); break; default: @@ -369,14 +359,12 @@ nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance, uint8_t * p_rx_buffer, size_t rx_buffer_length) { + NRFX_ASSERT(p_tx_buffer != NULL || tx_buffer_length == 0); + NRFX_ASSERT(p_rx_buffer != NULL || rx_buffer_length == 0); + spis_cb_t * p_cb = &m_cb[p_instance->drv_inst_idx]; nrfx_err_t err_code; - if (p_rx_buffer == NULL || p_tx_buffer == NULL) - { - return NRFX_ERROR_NULL; - } - if (!SPIS_LENGTH_VALIDATE(p_instance->drv_inst_idx, rx_buffer_length, tx_buffer_length)) diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_swi.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_swi.c index 4a6dcc4d4..5d8b4d24e 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_swi.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_swi.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_systick.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_systick.c index 1a6151afe..6998182a4 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_systick.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_systick.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -83,7 +74,7 @@ * @param us Time in microseconds to check */ #define NRFX_SYSTICK_ASSERT_TIMEOUT(us) \ - NRFX_ASSERT(us <= (NRFX_SYSTICK_TICKS_MAX / ((SystemCoreClock) / NRFX_SYSTICK_US))) + NRFX_ASSERT(us <= (NRFX_SYSTICK_TICKS_MAX / ((SystemCoreClock) / NRFX_SYSTICK_US))); /** * @brief Function that converts microseconds to ticks diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_timer.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_timer.c index 024958efb..d9d2d569b 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_timer.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_timer.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c index c7492bd4e..d5f0a1c9a 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c index 7d9cb3600..fdfaca6e6 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c index 9fb7a4947..47baa1c89 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c index 8c5f487f8..43a25151c 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c index 1d5bf090a..bc4fcbe97 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c index d4d33b1fa..059804115 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.c b/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.c index e7a105fe3..24cafeb5c 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.c +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h b/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h index f585fa131..2ce29cc70 100644 --- a/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h +++ b/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_PRS_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h index 862e6f1e5..bcc5913bd 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_ADC_H_ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h index 31cfc7a2e..3140f445c 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_CLOCK_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h index 0f8b10816..3c75be6e5 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_COMP_H_ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c index e794a0838..9458f21e6 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ //lint -e438 diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h index 15830b7d9..c0d1b4df3 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_ECB_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h index 083dce279..dc6709f46 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_EGU_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h index 09113205f..94544edce 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_GPIO_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h index 91faf9fcc..0e44941e4 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_GPIOTE_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h index ab698e592..7d77a4d9e 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_I2S_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h index c10a909a0..c1ab7f77f 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_LPCOMP_H_ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.c b/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.c index 99fc64f85..6bb66db6c 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.c +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.c @@ -1,41 +1,32 @@ /** * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ /** *@file diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h index a0d8de8ef..afc928acc 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_NVMC_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h index 5f183140e..39344f9e0 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_PDM_H_ #define NRF_PDM_H_ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h index 9082d82ce..14fd9c1e8 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_POWER_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h index cdface55e..96d9f0612 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_PPI_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h index 6c576126b..88d87ea6e 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_PWM_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h index 537bf78ef..de8138062 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_QDEC_H__ #define NRF_QDEC_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h index 444f4ba0a..d0767d725 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_QSPI_H__ @@ -77,6 +68,7 @@ typedef enum NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */ NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */ NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */ + NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */ /*lint -restore*/ } nrf_qspi_task_t; diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h index 62f60c02b..2d932ba49 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_RNG_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h index d4770d5e4..cb1218c85 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_RTC_H diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h index fe8835683..b72f32081 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_SAADC_H_ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h index 28b8c8026..e672d5420 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_SPI_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h index ede94f3c2..1c93e0302 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_SPIM_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h index d2d56c665..d44d89aff 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_SPIS_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h index 4842fb423..110c49368 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_SYSTICK_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h index 04772a9f4..3d567953c 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_TEMP_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h index 2303478d0..2cf38279a 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_TIMER_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h index e17b7933c..90a621786 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_TWI_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h index a5a8e37a8..a67f0bb20 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_TWIM_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h index 30d501829..8ca0a2894 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_TWIS_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h index 71d772651..863edf708 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_UART_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h index b1e65dca1..0fbef02c1 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_UARTE_H__ diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h index 73610d548..43fc29710 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_USBD_H__ @@ -1189,8 +1180,8 @@ void nrf_usbd_dpdmvalue_set(nrf_usbd_dpdmvalue_t val) void nrf_usbd_dtoggle_set(uint8_t ep, nrf_usbd_dtoggle_t op) { - ASSERT(NRF_USBD_EP_VALIDATE(ep)); - ASSERT(!NRF_USBD_EPISO_CHECK(ep)); + NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); + NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep)); NRF_USBD->DTOGGLE = ep | (NRF_USBD_DTOGGLE_NOP << USBD_DTOGGLE_VALUE_Pos); __DSB(); NRF_USBD->DTOGGLE = ep | (op << USBD_DTOGGLE_VALUE_Pos); diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h index 44157b38d..ab851f2b6 100644 --- a/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h +++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_WDT_H__ diff --git a/third_party/NordicSemiconductor/nrfx/mdk/compiler_abstraction.h b/third_party/NordicSemiconductor/nrfx/mdk/compiler_abstraction.h index 1b07ffa63..f63646959 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/compiler_abstraction.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/compiler_abstraction.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52840.S b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52840.S index ad45d5eed..a8b6e8d6a 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52840.S +++ b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52840.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2017 ARM Limited. All rights reserved. +Copyright (c) 2009-2018 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf.h index 7dc01c1e4..b2447339a 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -35,8 +35,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 15 -#define MDK_MICRO_VERSION 4 +#define MDK_MINOR_VERSION 16 +#define MDK_MICRO_VERSION 0 /* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ #if defined (NRF52) diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52.h index 3c9f8a2d9..9cdae0c7c 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52840.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52840.h index 729e943cf..d0a442162 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52840.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf51_to_nrf52840.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h index 6d33e65c9..b547c2a72 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h @@ -6,12 +6,12 @@ * nrf52840 from Nordic Semiconductor. * * @version V1 - * @date 24. January 2018 + * @date 8. March 2018 * * @note Generated with SVDConv V2.81d * from CMSIS SVD File 'nrf52840.svd' Version 1, * - * @par Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved. + * @par Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -177,7 +177,7 @@ typedef struct { __I uint32_t PACKAGE; /*!< Package option */ __I uint32_t RAM; /*!< RAM variant */ __I uint32_t FLASH; /*!< Flash variant */ - __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ + __IO uint32_t UNUSED8[3]; /*!< Unspecified */ } FICR_INFO_Type; typedef struct { @@ -223,12 +223,19 @@ typedef struct { } FICR_TRNG90B_Type; typedef struct { - __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ - __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ - __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ + __IO uint32_t POWER; /*!< Description cluster[n]: RAMn power control register */ + __O uint32_t POWERSET; /*!< Description cluster[n]: RAMn power control set register */ + __O uint32_t POWERCLR; /*!< Description cluster[n]: RAMn power control clear register */ __I uint32_t RESERVED0; } POWER_RAM_Type; +typedef struct { + __IO uint32_t RTS; /*!< Pin select for RTS */ + __IO uint32_t TXD; /*!< Pin select for TXD */ + __IO uint32_t CTS; /*!< Pin select for CTS */ + __IO uint32_t RXD; /*!< Pin select for RXD */ +} UART_PSEL_Type; + typedef struct { __IO uint32_t RTS; /*!< Pin select for RTS signal */ __IO uint32_t TXD; /*!< Pin select for TXD signal */ @@ -249,11 +256,10 @@ typedef struct { } UARTE_TXD_Type; typedef struct { - __IO uint32_t RTS; /*!< Pin select for RTS */ - __IO uint32_t TXD; /*!< Pin select for TXD */ - __IO uint32_t CTS; /*!< Pin select for CTS */ - __IO uint32_t RXD; /*!< Pin select for RXD */ -} UART_PSEL_Type; + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ +} SPI_PSEL_Type; typedef struct { __IO uint32_t SCK; /*!< Pin select for SCK */ @@ -301,6 +307,11 @@ typedef struct { __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ } SPIS_TXD_Type; +typedef struct { + __IO uint32_t SCL; /*!< Pin select for SCL */ + __IO uint32_t SDA; /*!< Pin select for SDA */ +} TWI_PSEL_Type; + typedef struct { __IO uint32_t SCL; /*!< Pin select for SCL signal */ __IO uint32_t SDA; /*!< Pin select for SDA signal */ @@ -337,17 +348,6 @@ typedef struct { __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ } TWIS_TXD_Type; -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ -} SPI_PSEL_Type; - -typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL */ - __IO uint32_t SDA; /*!< Pin select for SDA */ -} TWI_PSEL_Type; - typedef struct { __IO uint32_t RX; /*!< Result of last incoming frame */ } NFCT_FRAMESTATUS_Type; @@ -363,22 +363,24 @@ typedef struct { } NFCT_RXD_Type; typedef struct { - __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ - __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ + __IO uint32_t LIMITH; /*!< Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */ + __IO uint32_t LIMITL; /*!< Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */ } SAADC_EVENTS_CH_Type; typedef struct { - __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ - __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ - __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ - __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring - a channel */ + __IO uint32_t PSELP; /*!< Description cluster[n]: Input positive pin selection for CH[n] */ + __IO uint32_t PSELN; /*!< Description cluster[n]: Input negative pin selection for CH[n] */ + __IO uint32_t CONFIG; /*!< Description cluster[n]: Input configuration for CH[n] */ + __IO uint32_t LIMIT; /*!< Description cluster[n]: High/low limits for event monitoring + of a channel */ } SAADC_CH_Type; typedef struct { __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ - __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ + __IO uint32_t MAXCNT; /*!< Maximum number of 16-bit samples to be written to output RAM + buffer */ + __I uint32_t AMOUNT; /*!< Number of 16-bit samples written to output RAM buffer since + the previous START task */ } SAADC_RESULT_Type; typedef struct { @@ -388,18 +390,18 @@ typedef struct { } QDEC_PSEL_Type; typedef struct { - __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in RAM of this sequence */ - __IO uint32_t CNT; /*!< Description cluster[0]: Number of values (duty cycles) in this + __IO uint32_t PTR; /*!< Description cluster[n]: Beginning address in RAM of this sequence */ + __IO uint32_t CNT; /*!< Description cluster[n]: Number of values (duty cycles) in this sequence */ - __IO uint32_t REFRESH; /*!< Description cluster[0]: Number of additional PWM periods between + __IO uint32_t REFRESH; /*!< Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ - __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ + __IO uint32_t ENDDELAY; /*!< Description cluster[n]: Time added after the sequence */ __I uint32_t RESERVED1[4]; } PWM_SEQ_Type; typedef struct { - __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel - 0 */ + __IO uint32_t OUT[4]; /*!< Description collection[n]: Output pin select for PWM channel + n */ } PWM_PSEL_Type; typedef struct { @@ -413,59 +415,59 @@ typedef struct { } PDM_SAMPLE_Type; typedef struct { - __IO uint32_t ADDR; /*!< Description cluster[0]: Configure the word-aligned start address - of region 0 to protect */ - __IO uint32_t SIZE; /*!< Description cluster[0]: Size of region to protect counting from - address ACL[0].ADDR. Write '0' as no effect. */ - __IO uint32_t PERM; /*!< Description cluster[0]: Access permissions for region 0 as defined - by start address ACL[0].ADDR and size ACL[0].SIZE */ + __IO uint32_t ADDR; /*!< Description cluster[n]: Configure the word-aligned start address + of region n to protect */ + __IO uint32_t SIZE; /*!< Description cluster[n]: Size of region to protect counting from + address ACL[n].ADDR. Write '0' as no effect. */ + __IO uint32_t PERM; /*!< Description cluster[n]: Access permissions for region n as defined + by start address ACL[n].ADDR and size ACL[n].SIZE */ __IO uint32_t UNUSED0; /*!< Unspecified */ } ACL_ACL_Type; typedef struct { - __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ - __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ + __O uint32_t EN; /*!< Description cluster[n]: Enable channel group n */ + __O uint32_t DIS; /*!< Description cluster[n]: Disable channel group n */ } PPI_TASKS_CHG_Type; typedef struct { - __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ - __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ + __IO uint32_t EEP; /*!< Description cluster[n]: Channel n event end-point */ + __IO uint32_t TEP; /*!< Description cluster[n]: Channel n task end-point */ } PPI_CH_Type; typedef struct { - __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ + __IO uint32_t TEP; /*!< Description cluster[n]: Channel n task end-point */ } PPI_FORK_Type; typedef struct { - __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ - __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ + __IO uint32_t WA; /*!< Description cluster[n]: Write access to region n detected */ + __IO uint32_t RA; /*!< Description cluster[n]: Read access to region n detected */ } MWU_EVENTS_REGION_Type; typedef struct { - __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 + __IO uint32_t WA; /*!< Description cluster[n]: Write access to peripheral region n detected */ - __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ + __IO uint32_t RA; /*!< Description cluster[n]: Read access to peripheral region n detected */ } MWU_EVENTS_PREGION_Type; typedef struct { - __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region - 0, write access detected while corresponding subregion was enabled + __IO uint32_t SUBSTATWA; /*!< Description cluster[n]: Source of event/interrupt in region + n, write access detected while corresponding subregion was enabled for watching */ - __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region - 0, read access detected while corresponding subregion was enabled + __IO uint32_t SUBSTATRA; /*!< Description cluster[n]: Source of event/interrupt in region + n, read access detected while corresponding subregion was enabled for watching */ } MWU_PERREGION_Type; typedef struct { - __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ - __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ + __IO uint32_t START; /*!< Description cluster[n]: Start address for region n */ + __IO uint32_t END; /*!< Description cluster[n]: End address of region n */ __I uint32_t RESERVED2[2]; } MWU_REGION_Type; typedef struct { - __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ - __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ - __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ + __I uint32_t START; /*!< Description cluster[n]: Reserved for future use */ + __I uint32_t END; /*!< Description cluster[n]: Reserved for future use */ + __IO uint32_t SUBS; /*!< Description cluster[n]: Subregions of region n */ __I uint32_t RESERVED3; } MWU_PREGION_Type; @@ -503,23 +505,23 @@ typedef struct { } I2S_PSEL_Type; typedef struct { - __I uint32_t EPIN[8]; /*!< Description collection[0]: IN endpoint halted status. Can be + __I uint32_t EPIN[8]; /*!< Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ __I uint32_t RESERVED4; - __I uint32_t EPOUT[8]; /*!< Description collection[0]: OUT endpoint halted status. Can be + __I uint32_t EPOUT[8]; /*!< Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ } USBD_HALTED_Type; typedef struct { - __IO uint32_t EPOUT[8]; /*!< Description collection[0]: Amount of bytes received last in + __IO uint32_t EPOUT[8]; /*!< Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint */ - __I uint32_t ISOOUT; /*!< Amount of bytes received last on this iso OUT data endpoint */ + __I uint32_t ISOOUT; /*!< Number of bytes received last on this ISO OUT data endpoint */ } USBD_SIZE_Type; typedef struct { - __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */ - __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */ - __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last + __IO uint32_t PTR; /*!< Description cluster[n]: Data pointer */ + __IO uint32_t MAXCNT; /*!< Description cluster[n]: Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Description cluster[n]: Number of bytes transferred in the last transaction */ __I uint32_t RESERVED5[2]; } USBD_EPIN_Type; @@ -531,9 +533,9 @@ typedef struct { } USBD_ISOIN_Type; typedef struct { - __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */ - __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */ - __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last + __IO uint32_t PTR; /*!< Description cluster[n]: Data pointer */ + __IO uint32_t MAXCNT; /*!< Description cluster[n]: Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Description cluster[n]: Number of bytes transferred in the last transaction */ __I uint32_t RESERVED6[2]; } USBD_EPOUT_Type; @@ -586,16 +588,16 @@ typedef struct { /*!< FICR Structure __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ __I uint32_t CODESIZE; /*!< Code memory size */ __I uint32_t RESERVED1[18]; - __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ + __I uint32_t DEVICEID[2]; /*!< Description collection[n]: Device identifier */ __I uint32_t RESERVED2[6]; - __I uint32_t ER[4]; /*!< Description collection[0]: Encryption root, word 0 */ - __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ + __I uint32_t ER[4]; /*!< Description collection[n]: Encryption root, word n */ + __I uint32_t IR[4]; /*!< Description collection[n]: Identity Root, word n */ __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ - __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ + __I uint32_t DEVICEADDR[2]; /*!< Description collection[n]: Device address n */ __I uint32_t RESERVED3[21]; FICR_INFO_Type INFO; /*!< Device info */ __I uint32_t RESERVED4[140]; - __I uint32_t PRODTEST[3]; /*!< Description collection[0]: Production test signature 0 */ + __I uint32_t PRODTEST[3]; /*!< Description collection[n]: Production test signature n */ __I uint32_t RESERVED5[42]; FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ __I uint32_t RESERVED6[2]; @@ -620,23 +622,73 @@ typedef struct { /*!< UICR Structure __IO uint32_t UNUSED2; /*!< Unspecified */ __I uint32_t RESERVED0; __IO uint32_t UNUSED3; /*!< Unspecified */ - __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ - __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ - __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ + __IO uint32_t NRFFW[15]; /*!< Description collection[n]: Reserved for Nordic firmware design */ + __IO uint32_t NRFHW[12]; /*!< Description collection[n]: Reserved for Nordic hardware design */ + __IO uint32_t CUSTOMER[32]; /*!< Description collection[n]: Reserved for customer */ __I uint32_t RESERVED1[64]; - __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function */ + __IO uint32_t PSELRESET[2]; /*!< Description collection[n]: Mapping of the nRESET function */ __IO uint32_t APPROTECT; /*!< Access port protection */ __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ __IO uint32_t DEBUGCTRL; /*!< Processor debug control */ - __I uint32_t RESERVED2[59]; - __IO uint32_t DCDCDRIVE0; /*!< Set drive level for REG0 DCDC mode. Using high drive will slightly - reduce DCDC efficiency. */ + __I uint32_t RESERVED2[60]; __IO uint32_t REGOUT0; /*!< GPIO reference voltage / external output supply voltage in high voltage mode */ } NRF_UICR_Type; +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFXO crystal oscillator */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFXO crystal oscillator */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFXO crystal oscillator started */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFRC completed */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ + __I uint32_t RESERVED2[5]; + __IO uint32_t EVENTS_CTSTARTED; /*!< Calibration timer has been started and is ready to process new + tasks */ + __IO uint32_t EVENTS_CTSTOPPED; /*!< Calibration timer has been stopped and is ready to process new + tasks */ + __I uint32_t RESERVED3[117]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[63]; + __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ + __I uint32_t HFCLKSTAT; /*!< HFCLK status */ + __I uint32_t RESERVED5; + __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ + __I uint32_t LFCLKSTAT; /*!< LFCLK status */ + __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + __I uint32_t RESERVED6[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ + __I uint32_t RESERVED7[3]; + __IO uint32_t HFXODEBOUNCE; /*!< HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART + task. */ + __I uint32_t RESERVED8[3]; + __IO uint32_t CTIV; /*!< Calibration timer interval */ + __I uint32_t RESERVED9[8]; + __IO uint32_t TRACECONFIG; /*!< Clocking options for the trace port debug interface */ + __I uint32_t RESERVED10[21]; + __IO uint32_t LFRCMODE; /*!< LFRC mode configuration */ +} NRF_CLOCK_Type; + + /* ================================================================================ */ /* ================ POWER ================ */ /* ================================================================================ */ @@ -670,7 +722,7 @@ typedef struct { /*!< POWER Structure __I uint32_t RESERVED7[49]; __O uint32_t SYSTEMOFF; /*!< System OFF register */ __I uint32_t RESERVED8[3]; - __IO uint32_t POFCON; /*!< Power failure comparator configuration */ + __IO uint32_t POFCON; /*!< Power-fail comparator configuration */ __I uint32_t RESERVED9[2]; __IO uint32_t GPREGRET; /*!< General purpose retention register */ __IO uint32_t GPREGRET2; /*!< General purpose retention register */ @@ -685,65 +737,13 @@ typedef struct { /*!< POWER Structure } NRF_POWER_Type; -/* ================================================================================ */ -/* ================ CLOCK ================ */ -/* ================================================================================ */ - - -/** - * @brief Clock control (CLOCK) - */ - -typedef struct { /*!< CLOCK Structure */ - __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ - __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ - __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ - __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ - __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC or LFULP oscillator */ - __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ - __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ - __I uint32_t RESERVED0[57]; - __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ - __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ - __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ - __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ - __I uint32_t RESERVED2[5]; - __IO uint32_t EVENTS_CTSTARTED; /*!< Calibration timer has been started and is ready to process new - tasks */ - __IO uint32_t EVENTS_CTSTOPPED; /*!< Calibration timer has been stopped and is ready to process new - tasks */ - __I uint32_t RESERVED3[117]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[63]; - __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ - __I uint32_t HFCLKSTAT; /*!< HFCLK status */ - __I uint32_t RESERVED5; - __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ - __I uint32_t LFCLKSTAT; /*!< LFCLK status */ - __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ - __I uint32_t RESERVED6[62]; - __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ - __I uint32_t RESERVED7[3]; - __IO uint32_t HFXODEBOUNCE; /*!< HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART - task. */ - __I uint32_t RESERVED8[3]; - __IO uint32_t CTIV; /*!< Calibration timer interval */ - __I uint32_t RESERVED9[8]; - __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ - __I uint32_t RESERVED10[21]; - __IO uint32_t LFRCMODE; /*!< LFRC mode configuration */ -} NRF_CLOCK_Type; - - /* ================================================================================ */ /* ================ RADIO ================ */ /* ================================================================================ */ /** - * @brief 2.4 GHz Radio (RADIO) + * @brief 2.4 GHz radio (RADIO) */ typedef struct { /*!< RADIO Structure */ @@ -753,14 +753,14 @@ typedef struct { /*!< RADIO Structure __O uint32_t TASKS_STOP; /*!< Stop RADIO */ __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal - strength. */ + strength */ __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ - __O uint32_t TASKS_EDSTART; /*!< Start the Energy Detect measurement used in IEEE 802.15.4 mode */ - __O uint32_t TASKS_EDSTOP; /*!< Stop the Energy Detect measurement */ - __O uint32_t TASKS_CCASTART; /*!< Start the Clear Channel Assessment used in IEEE 802.15.4 mode */ - __O uint32_t TASKS_CCASTOP; /*!< Stop the Clear Channel Assessment */ + __O uint32_t TASKS_EDSTART; /*!< Start the energy detect measurement used in IEEE 802.15.4 mode */ + __O uint32_t TASKS_EDSTOP; /*!< Stop the energy detect measurement */ + __O uint32_t TASKS_CCASTART; /*!< Start the clear channel assessment used in IEEE 802.15.4 mode */ + __O uint32_t TASKS_CCASTOP; /*!< Stop the clear channel assessment */ __I uint32_t RESERVED0[51]; __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ @@ -769,16 +769,16 @@ typedef struct { /*!< RADIO Structure __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ - __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete */ __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value */ __I uint32_t RESERVED2; __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ __IO uint32_t EVENTS_FRAMESTART; /*!< IEEE 802.15.4 length field received */ - __IO uint32_t EVENTS_EDEND; /*!< Sampling of Energy Detection complete. A new ED sample is ready - for readout from the RADIO.EDSAMPLE register */ - __IO uint32_t EVENTS_EDSTOPPED; /*!< The sampling of Energy Detection has stopped */ + __IO uint32_t EVENTS_EDEND; /*!< Sampling of energy detection complete. A new ED sample is ready + for readout from the RADIO.EDSAMPLE register. */ + __IO uint32_t EVENTS_EDSTOPPED; /*!< The sampling of energy detection has stopped */ __IO uint32_t EVENTS_CCAIDLE; /*!< Wireless medium in idle - clear to send */ __IO uint32_t EVENTS_CCABUSY; /*!< Wireless medium busy - do not send */ __IO uint32_t EVENTS_CCASTOPPED; /*!< The CCA has stopped */ @@ -786,7 +786,7 @@ typedef struct { /*!< RADIO Structure to Ble_LR500Kbit. */ __IO uint32_t EVENTS_TXREADY; /*!< RADIO has ramped up and is ready to be started TX path */ __IO uint32_t EVENTS_RXREADY; /*!< RADIO has ramped up and is ready to be started RX path */ - __IO uint32_t EVENTS_MHRMATCH; /*!< MAC Header match found. */ + __IO uint32_t EVENTS_MHRMATCH; /*!< MAC header match found */ __I uint32_t RESERVED3[3]; __IO uint32_t EVENTS_PHYEND; /*!< Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. */ @@ -819,7 +819,7 @@ typedef struct { /*!< RADIO Structure __IO uint32_t CRCPOLY; /*!< CRC polynomial */ __IO uint32_t CRCINIT; /*!< CRC initial value */ __I uint32_t RESERVED9; - __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ + __IO uint32_t TIFS; /*!< Interframe spacing in us */ __I uint32_t RSSISAMPLE; /*!< RSSI sample */ __I uint32_t RESERVED10; __I uint32_t STATE; /*!< Current radio state */ @@ -827,23 +827,69 @@ typedef struct { /*!< RADIO Structure __I uint32_t RESERVED11[2]; __IO uint32_t BCC; /*!< Bit counter compare */ __I uint32_t RESERVED12[39]; - __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ - __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ + __IO uint32_t DAB[8]; /*!< Description collection[n]: Device address base segment n */ + __IO uint32_t DAP[8]; /*!< Description collection[n]: Device address prefix n */ __IO uint32_t DACNF; /*!< Device address match configuration */ - __IO uint32_t MHRMATCHCONF; /*!< Search Pattern Configuration */ + __IO uint32_t MHRMATCHCONF; /*!< Search pattern configuration */ __IO uint32_t MHRMATCHMAS; /*!< Pattern mask */ __I uint32_t RESERVED13; __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ __I uint32_t RESERVED14[3]; - __IO uint32_t SFD; /*!< IEEE 802.15.4 Start of Frame Delimiter */ - __IO uint32_t EDCNT; /*!< IEEE 802.15.4 Energy Detect Loop Count */ - __IO uint32_t EDSAMPLE; /*!< IEEE 802.15.4 Energy Detect Level */ - __IO uint32_t CCACTRL; /*!< IEEE 802.15.4 Clear Channel Assessment Control */ + __IO uint32_t SFD; /*!< IEEE 802.15.4 start of frame delimiter */ + __IO uint32_t EDCNT; /*!< IEEE 802.15.4 energy detect loop count */ + __IO uint32_t EDSAMPLE; /*!< IEEE 802.15.4 energy detect level */ + __IO uint32_t CCACTRL; /*!< IEEE 802.15.4 clear channel assessment control */ __I uint32_t RESERVED15[611]; __IO uint32_t POWER; /*!< Peripheral power control */ } NRF_RADIO_Type; +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART) + */ + +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED9; + UART_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RXD; /*!< RXD register */ + __O uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UART_Type; + + /* ================================================================================ */ /* ================ UARTE ================ */ /* ================================================================================ */ @@ -902,49 +948,32 @@ typedef struct { /*!< UARTE Structure /* ================================================================================ */ -/* ================ UART ================ */ +/* ================ SPI ================ */ /* ================================================================================ */ /** - * @brief Universal Asynchronous Receiver/Transmitter (UART) + * @brief Serial Peripheral Interface 0 (SPI) */ -typedef struct { /*!< UART Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ - __I uint32_t RESERVED1[56]; - __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ - __I uint32_t RESERVED2[4]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ - __I uint32_t RESERVED3; - __IO uint32_t EVENTS_ERROR; /*!< Error detected */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ - __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED6[64]; +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ + __I uint32_t RESERVED1[126]; __IO uint32_t INTENSET; /*!< Enable interrupt */ __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED7[93]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED8[31]; - __IO uint32_t ENABLE; /*!< Enable UART */ - __I uint32_t RESERVED9; - UART_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI */ + __I uint32_t RESERVED3; + SPI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED4; __I uint32_t RXD; /*!< RXD register */ - __O uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED10; - __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED11[17]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ -} NRF_UART_Type; + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register */ +} NRF_SPI_Type; /* ================================================================================ */ @@ -1049,6 +1078,57 @@ typedef struct { /*!< SPIS Structure } NRF_SPIS_Type; +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI) + */ + +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or + received */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable TWI */ + __I uint32_t RESERVED12; + TWI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWI_Type; + + /* ================================================================================ */ /* ================ TWIM ================ */ /* ================================================================================ */ @@ -1148,7 +1228,7 @@ typedef struct { /*!< TWIS Structure __I uint32_t RESERVED13; TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ __I uint32_t RESERVED14[14]; - __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ + __IO uint32_t ADDRESS[2]; /*!< Description collection[n]: TWI slave address n */ __I uint32_t RESERVED15; __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ __I uint32_t RESERVED16[10]; @@ -1157,86 +1237,6 @@ typedef struct { /*!< TWIS Structure } NRF_TWIS_Type; -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ - - -/** - * @brief Serial Peripheral Interface 0 (SPI) - */ - -typedef struct { /*!< SPI Structure */ - __I uint32_t RESERVED0[66]; - __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ - __I uint32_t RESERVED1[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< Enable SPI */ - __I uint32_t RESERVED3; - SPI_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED4; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED5; - __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CONFIG; /*!< Configuration register */ -} NRF_SPI_Type; - - -/* ================================================================================ */ -/* ================ TWI ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C compatible Two-Wire Interface 0 (TWI) - */ - -typedef struct { /*!< TWI Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ - __I uint32_t RESERVED4[4]; - __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or - received */ - __I uint32_t RESERVED7[3]; - __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ - __I uint32_t RESERVED8[45]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED9[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED10[110]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED11[14]; - __IO uint32_t ENABLE; /*!< Enable TWI */ - __I uint32_t RESERVED12; - TWI_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED13[2]; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED14; - __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ - __I uint32_t RESERVED15[24]; - __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ -} NRF_TWI_Type; - - /* ================================================================================ */ /* ================ NFCT ================ */ /* ================================================================================ */ @@ -1325,17 +1325,17 @@ typedef struct { /*!< NFCT Structure */ typedef struct { /*!< GPIOTE Structure */ - __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ + __O uint32_t TASKS_OUT[8]; /*!< Description collection[n]: Task for writing to pin specified + in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is to set it high. */ + __O uint32_t TASKS_SET[8]; /*!< Description collection[n]: Task for writing to pin specified + in CONFIG[n].PSEL. Action on pin is to set it high. */ __I uint32_t RESERVED1[4]; - __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is to set it low. */ + __O uint32_t TASKS_CLR[8]; /*!< Description collection[n]: Task for writing to pin specified + in CONFIG[n].PSEL. Action on pin is to set it low. */ __I uint32_t RESERVED2[32]; - __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified - in CONFIG[0].PSEL */ + __IO uint32_t EVENTS_IN[8]; /*!< Description collection[n]: Event generated from pin specified + in CONFIG[n].PSEL */ __I uint32_t RESERVED3[23]; __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism enabled */ @@ -1343,7 +1343,7 @@ typedef struct { /*!< GPIOTE Structure __IO uint32_t INTENSET; /*!< Enable interrupt */ __IO uint32_t INTENCLR; /*!< Disable interrupt */ __I uint32_t RESERVED5[129]; - __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] + __IO uint32_t CONFIG[8]; /*!< Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; @@ -1354,23 +1354,23 @@ typedef struct { /*!< GPIOTE Structure /** - * @brief Analog to Digital Converter (SAADC) + * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) */ typedef struct { /*!< SAADC Structure */ - __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ - __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ - __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ + __O uint32_t TASKS_START; /*!< Starts the SAADC and prepares the result buffer in RAM */ + __O uint32_t TASKS_SAMPLE; /*!< Takes one SAADC sample */ + __O uint32_t TASKS_STOP; /*!< Stops the SAADC and terminates all on-going conversions */ __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ - __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ - __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, + __IO uint32_t EVENTS_STARTED; /*!< The SAADC has started */ + __IO uint32_t EVENTS_END; /*!< The SAADC has filled up the result buffer */ + __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ - __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ + __IO uint32_t EVENTS_RESULTDONE; /*!< Result ready for transfer to RAM */ __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ - __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ + __IO uint32_t EVENTS_STOPPED; /*!< The SAADC has stopped */ SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ __I uint32_t RESERVED1[106]; __IO uint32_t INTEN; /*!< Enable or disable interrupt */ @@ -1379,14 +1379,14 @@ typedef struct { /*!< SAADC Structure __I uint32_t RESERVED2[61]; __I uint32_t STATUS; /*!< Status */ __I uint32_t RESERVED3[63]; - __IO uint32_t ENABLE; /*!< Enable or disable ADC */ + __IO uint32_t ENABLE; /*!< Enable or disable SAADC */ __I uint32_t RESERVED4[3]; SAADC_CH_Type CH[8]; /*!< Unspecified */ __I uint32_t RESERVED5[24]; __IO uint32_t RESOLUTION; /*!< Resolution configuration */ - __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined - with SCAN. The RESOLUTION is applied before averaging, thus - for high OVERSAMPLE a higher RESOLUTION should be used. */ + __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. The RESOLUTION is applied before + averaging, thus for high OVERSAMPLE a higher RESOLUTION should + be used. */ __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ __I uint32_t RESERVED6[12]; SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ @@ -1409,9 +1409,9 @@ typedef struct { /*!< TIMER Structure __O uint32_t TASKS_CLEAR; /*!< Clear time */ __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ __I uint32_t RESERVED0[11]; - __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ + __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[n]: Capture Timer value to CC[n] register */ __I uint32_t RESERVED1[58]; - __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ + __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[n]: Compare event on CC[n] match */ __I uint32_t RESERVED2[42]; __IO uint32_t SHORTS; /*!< Shortcut register */ __I uint32_t RESERVED3[64]; @@ -1423,7 +1423,7 @@ typedef struct { /*!< TIMER Structure __I uint32_t RESERVED5; __IO uint32_t PRESCALER; /*!< Timer prescaler register */ __I uint32_t RESERVED6[11]; - __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ + __IO uint32_t CC[6]; /*!< Description collection[n]: Capture/Compare register n */ } NRF_TIMER_Type; @@ -1445,7 +1445,7 @@ typedef struct { /*!< RTC Structure __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ __I uint32_t RESERVED1[14]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ + __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[n]: Compare event on CC[n] match */ __I uint32_t RESERVED2[109]; __IO uint32_t INTENSET; /*!< Enable interrupt */ __IO uint32_t INTENCLR; /*!< Disable interrupt */ @@ -1458,7 +1458,7 @@ typedef struct { /*!< RTC Structure __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ __I uint32_t RESERVED5[13]; - __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ + __IO uint32_t CC[4]; /*!< Description collection[n]: Compare register n */ } NRF_RTC_Type; @@ -1554,6 +1554,39 @@ typedef struct { /*!< ECB Structure } NRF_ECB_Type; +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR */ + __IO uint32_t NIRK; /*!< Number of IRKs */ + __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_AAR_Type; + + /* ================================================================================ */ /* ================ CCM ================ */ /* ================================================================================ */ @@ -1594,39 +1627,6 @@ typedef struct { /*!< CCM Structure } NRF_CCM_Type; -/* ================================================================================ */ -/* ================ AAR ================ */ -/* ================================================================================ */ - - -/** - * @brief Accelerated Address Resolver (AAR) - */ - -typedef struct { /*!< AAR Structure */ - __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK - data structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ - __I uint32_t RESERVED1[61]; - __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ - __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ - __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t STATUS; /*!< Resolution status */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable AAR */ - __IO uint32_t NIRK; /*!< Number of IRKs */ - __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ - __I uint32_t RESERVED5; - __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ -} NRF_AAR_Type; - - /* ================================================================================ */ /* ================ WDT ================ */ /* ================================================================================ */ @@ -1651,7 +1651,7 @@ typedef struct { /*!< WDT Structure __IO uint32_t RREN; /*!< Enable register for reload request registers */ __IO uint32_t CONFIG; /*!< Configuration register */ __I uint32_t RESERVED4[60]; - __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ + __O uint32_t RR[8]; /*!< Description collection[n]: Reload request n */ } NRF_WDT_Type; @@ -1777,6 +1777,28 @@ typedef struct { /*!< LPCOMP Structure } NRF_LPCOMP_Type; +/* ================================================================================ */ +/* ================ EGU ================ */ +/* ================================================================================ */ + + +/** + * @brief Event Generator Unit 0 (EGU) + */ + +typedef struct { /*!< EGU Structure */ + __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[n]: Trigger n for triggering the corresponding + TRIGGERED[n] event */ + __I uint32_t RESERVED0[48]; + __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[n]: Event number n generated by triggering + the corresponding TRIGGER[n] task */ + __I uint32_t RESERVED1[112]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ +} NRF_EGU_Type; + + /* ================================================================================ */ /* ================ SWI ================ */ /* ================================================================================ */ @@ -1791,28 +1813,6 @@ typedef struct { /*!< SWI Structure } NRF_SWI_Type; -/* ================================================================================ */ -/* ================ EGU ================ */ -/* ================================================================================ */ - - -/** - * @brief Event Generator Unit 0 (EGU) - */ - -typedef struct { /*!< EGU Structure */ - __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding - TRIGGERED[0] event */ - __I uint32_t RESERVED0[48]; - __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering - the corresponding TRIGGER[0] task */ - __I uint32_t RESERVED1[112]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ -} NRF_EGU_Type; - - /* ================================================================================ */ /* ================ PWM ================ */ /* ================================================================================ */ @@ -1826,9 +1826,9 @@ typedef struct { /*!< PWM Structure __I uint32_t RESERVED0; __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ - __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all - enabled channels from sequence 0, and starts playing that sequence - at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes + __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[n]: Loads the first PWM value on all + enabled channels from sequence n, and starts playing that sequence + at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start @@ -1836,10 +1836,10 @@ typedef struct { /*!< PWM Structure __I uint32_t RESERVED1[60]; __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer generated */ - __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence - 0 */ - __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence - 0, when last value from RAM has been applied to wave counter */ + __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[n]: First PWM period started on sequence + n */ + __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[n]: Emitted at end of every sequence + n, when last value from RAM has been applied to wave counter */ __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times defined in LOOP.CNT */ @@ -1900,6 +1900,21 @@ typedef struct { /*!< PDM Structure } NRF_PDM_Type; +/* ================================================================================ */ +/* ================ ACL ================ */ +/* ================================================================================ */ + + +/** + * @brief Access control lists (ACL) + */ + +typedef struct { /*!< ACL Structure */ + __I uint32_t RESERVED0[512]; + ACL_ACL_Type ACL[8]; /*!< Unspecified */ +} NRF_ACL_Type; + + /* ================================================================================ */ /* ================ NVMC ================ */ /* ================================================================================ */ @@ -1918,9 +1933,9 @@ typedef struct { /*!< NVMC Structure __IO uint32_t CONFIG; /*!< Configuration register */ union { - __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in code area */ __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in code area */ }; __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in code area. @@ -1936,21 +1951,6 @@ typedef struct { /*!< NVMC Structure } NRF_NVMC_Type; -/* ================================================================================ */ -/* ================ ACL ================ */ -/* ================================================================================ */ - - -/** - * @brief Access control lists (ACL) - */ - -typedef struct { /*!< ACL Structure */ - __I uint32_t RESERVED0[512]; - ACL_ACL_Type ACL[8]; /*!< Unspecified */ -} NRF_ACL_Type; - - /* ================================================================================ */ /* ================ PPI ================ */ /* ================================================================================ */ @@ -1969,7 +1969,7 @@ typedef struct { /*!< PPI Structure __I uint32_t RESERVED1; PPI_CH_Type CH[20]; /*!< PPI Channel */ __I uint32_t RESERVED2[148]; - __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ + __IO uint32_t CHG[6]; /*!< Description collection[n]: Channel group n */ __I uint32_t RESERVED3[62]; PPI_FORK_Type FORK[32]; /*!< Fork */ } NRF_PPI_Type; @@ -2073,48 +2073,48 @@ typedef struct { /*!< FPU Structure /** - * @brief Universal Serial Bus device (USBD) + * @brief Universal serial bus device (USBD) */ typedef struct { /*!< USBD Structure */ __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTEPIN[8]; /*!< Description collection[0]: Captures the EPIN[0].PTR and EPIN[0].MAXCNT - registers values, and enables endpoint IN 0 to respond to traffic + __O uint32_t TASKS_STARTEPIN[8]; /*!< Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT + registers values, and enables endpoint IN n to respond to traffic from host */ __O uint32_t TASKS_STARTISOIN; /*!< Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and - enables sending data on iso endpoint */ - __O uint32_t TASKS_STARTEPOUT[8]; /*!< Description collection[0]: Captures the EPOUT[0].PTR and EPOUT[0].MAXCNT - registers values, and enables endpoint 0 to respond to traffic + enables sending data on ISO endpoint */ + __O uint32_t TASKS_STARTEPOUT[8]; /*!< Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT + registers values, and enables endpoint n to respond to traffic from host */ __O uint32_t TASKS_STARTISOOUT; /*!< Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, - and enables receiving of data on iso endpoint */ + and enables receiving of data on ISO endpoint */ __O uint32_t TASKS_EP0RCVOUT; /*!< Allows OUT data stage on control endpoint 0 */ __O uint32_t TASKS_EP0STATUS; /*!< Allows status stage on control endpoint 0 */ - __O uint32_t TASKS_EP0STALL; /*!< STALLs data and status stage on control endpoint 0 */ - __O uint32_t TASKS_DPDMDRIVE; /*!< Forces D+ and D-lines to the state defined in the DPDMVALUE + __O uint32_t TASKS_EP0STALL; /*!< Stalls data and status stage on control endpoint 0 */ + __O uint32_t TASKS_DPDMDRIVE; /*!< Forces D+ and D- lines into the state defined in the DPDMVALUE register */ - __O uint32_t TASKS_DPDMNODRIVE; /*!< Stops forcing D+ and D- lines to any state (USB engine takes + __O uint32_t TASKS_DPDMNODRIVE; /*!< Stops forcing D+ and D- lines into any state (USB engine takes control) */ __I uint32_t RESERVED1[40]; - __IO uint32_t EVENTS_USBRESET; /*!< Signals that a USB reset condition has been detected on the - USB lines */ + __IO uint32_t EVENTS_USBRESET; /*!< Signals that a USB reset condition has been detected on USB + lines */ __IO uint32_t EVENTS_STARTED; /*!< Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ - __IO uint32_t EVENTS_ENDEPIN[8]; /*!< Description collection[0]: The whole EPIN[0] buffer has been + __IO uint32_t EVENTS_ENDEPIN[8]; /*!< Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ __IO uint32_t EVENTS_EP0DATADONE; /*!< An acknowledged data transfer has taken place on the control endpoint */ __IO uint32_t EVENTS_ENDISOIN; /*!< The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ - __IO uint32_t EVENTS_ENDEPOUT[8]; /*!< Description collection[0]: The whole EPOUT[0] buffer has been + __IO uint32_t EVENTS_ENDEPOUT[8]; /*!< Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ __IO uint32_t EVENTS_ENDISOOUT; /*!< The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ __IO uint32_t EVENTS_SOF; /*!< Signals that a SOF (start of frame) condition has been detected - on the USB lines */ - __IO uint32_t EVENTS_USBEVENT; /*!< An event or an error not covered by specific events has occurred, - check EVENTCAUSE register to find the cause */ + on USB lines */ + __IO uint32_t EVENTS_USBEVENT; /*!< An event or an error not covered by specific events has occurred. + Check EVENTCAUSE register to find the cause. */ __IO uint32_t EVENTS_EP0SETUP; /*!< A valid SETUP token has been received (and acknowledged) on the control endpoint */ __IO uint32_t EVENTS_EPDATA; /*!< A data transfer has occurred on a data endpoint, indicated by @@ -2126,7 +2126,7 @@ typedef struct { /*!< USBD Structure __IO uint32_t INTENSET; /*!< Enable interrupt */ __IO uint32_t INTENCLR; /*!< Disable interrupt */ __I uint32_t RESERVED4[61]; - __IO uint32_t EVENTCAUSE; /*!< Details on event that caused the USBEVENT event */ + __IO uint32_t EVENTCAUSE; /*!< Details on what caused the USBEVENT event */ __I uint32_t RESERVED5[7]; USBD_HALTED_Type HALTED; /*!< Unspecified */ __I uint32_t RESERVED6; @@ -2148,17 +2148,17 @@ typedef struct { /*!< USBD Structure __I uint32_t RESERVED8[15]; __IO uint32_t ENABLE; /*!< Enable USB */ __IO uint32_t USBPULLUP; /*!< Control of the USB pull-up */ - __IO uint32_t DPDMVALUE; /*!< State at which the DPDMDRIVE task will force D+ and D-. The - DPDMNODRIVE task reverts the control of the lines to MAC IP - (no forcing). */ - __IO uint32_t DTOGGLE; /*!< Data toggle control and status. */ + __IO uint32_t DPDMVALUE; /*!< State D+ and D- lines will be forced into by the DPDMDRIVE task. + The DPDMNODRIVE task reverts the control of the lines to MAC + IP (no forcing). */ + __IO uint32_t DTOGGLE; /*!< Data toggle control and status */ __IO uint32_t EPINEN; /*!< Endpoint IN enable */ __IO uint32_t EPOUTEN; /*!< Endpoint OUT enable */ __O uint32_t EPSTALL; /*!< STALL endpoints */ __IO uint32_t ISOSPLIT; /*!< Controls the split of ISO buffers */ __I uint32_t FRAMECNTR; /*!< Returns the current value of the start of frame counter */ __I uint32_t RESERVED9[2]; - __IO uint32_t LOWPOWER; /*!< Controls USBD peripheral low-power mode during USB suspend */ + __IO uint32_t LOWPOWER; /*!< Controls USBD peripheral low power mode during USB suspend */ __IO uint32_t ISOINCONFIG; /*!< Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ __I uint32_t RESERVED10[51]; @@ -2240,10 +2240,41 @@ typedef struct { /*!< GPIO Structure set in the PIN_CNF[n].SENSE registers */ __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ __I uint32_t RESERVED1[118]; - __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ + __IO uint32_t PIN_CNF[32]; /*!< Description collection[n]: Configuration of GPIO pins */ } NRF_GPIO_Type; +/* ================================================================================ */ +/* ================ CC_HOST_RGF ================ */ +/* ================================================================================ */ + + +/** + * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) + */ + +typedef struct { /*!< CC_HOST_RGF Structure */ + __I uint32_t RESERVED0[1678]; + __IO uint32_t HOST_CRYPTOKEY_SEL; /*!< AES hardware key select */ + __I uint32_t RESERVED1[4]; + __IO uint32_t HOST_IOT_KPRTL_LOCK; /*!< This write-once register is the K_PRTL lock register. When this + register is set, K_PRTL can not be used and a zeroed key will + be used instead. The value of this register is saved in the + CRYPTOCELL AO power domain. */ + __IO uint32_t HOST_IOT_KDR0; /*!< This register holds bits 31:0 of K_DR. The value of this register + is saved in the CRYPTOCELL AO power domain. Reading from this + address returns the K_DR valid status indicating if K_DR is + successfully retained. */ + __O uint32_t HOST_IOT_KDR1; /*!< This register holds bits 63:32 of K_DR. The value of this register + is saved in the CRYPTOCELL AO power domain. */ + __O uint32_t HOST_IOT_KDR2; /*!< This register holds bits 95:64 of K_DR. The value of this register + is saved in the CRYPTOCELL AO power domain. */ + __O uint32_t HOST_IOT_KDR3; /*!< This register holds bits 127:96 of K_DR. The value of this register + is saved in the CRYPTOCELL AO power domain. */ + __IO uint32_t HOST_IOT_LCS; /*!< Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ +} NRF_CC_HOST_RGF_Type; + + /* ================================================================================ */ /* ================ CRYPTOCELL ================ */ /* ================================================================================ */ @@ -2255,7 +2286,7 @@ typedef struct { /*!< GPIO Structure typedef struct { /*!< CRYPTOCELL Structure */ __I uint32_t RESERVED0[320]; - __IO uint32_t ENABLE; /*!< Control power and clock for CRYPTOCELL subsystem */ + __IO uint32_t ENABLE; /*!< Enable CRYPTOCELL subsystem */ } NRF_CRYPTOCELL_Type; @@ -2283,23 +2314,23 @@ typedef struct { /*!< CRYPTOCELL Structure #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL -#define NRF_POWER_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL #define NRF_RADIO_BASE 0x40001000UL -#define NRF_UARTE0_BASE 0x40002000UL #define NRF_UART0_BASE 0x40002000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL #define NRF_SPIM0_BASE 0x40003000UL #define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL #define NRF_TWIM0_BASE 0x40003000UL #define NRF_TWIS0_BASE 0x40003000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL #define NRF_SPIM1_BASE 0x40004000UL #define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL #define NRF_TWIM1_BASE 0x40004000UL #define NRF_TWIS1_BASE 0x40004000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL #define NRF_NFCT_BASE 0x40005000UL #define NRF_GPIOTE_BASE 0x40006000UL #define NRF_SAADC_BASE 0x40007000UL @@ -2310,38 +2341,38 @@ typedef struct { /*!< CRYPTOCELL Structure #define NRF_TEMP_BASE 0x4000C000UL #define NRF_RNG_BASE 0x4000D000UL #define NRF_ECB_BASE 0x4000E000UL -#define NRF_CCM_BASE 0x4000F000UL #define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL #define NRF_WDT_BASE 0x40010000UL #define NRF_RTC1_BASE 0x40011000UL #define NRF_QDEC_BASE 0x40012000UL #define NRF_COMP_BASE 0x40013000UL #define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_SWI0_BASE 0x40014000UL #define NRF_EGU0_BASE 0x40014000UL -#define NRF_SWI1_BASE 0x40015000UL +#define NRF_SWI0_BASE 0x40014000UL #define NRF_EGU1_BASE 0x40015000UL -#define NRF_SWI2_BASE 0x40016000UL +#define NRF_SWI1_BASE 0x40015000UL #define NRF_EGU2_BASE 0x40016000UL -#define NRF_SWI3_BASE 0x40017000UL +#define NRF_SWI2_BASE 0x40016000UL #define NRF_EGU3_BASE 0x40017000UL -#define NRF_SWI4_BASE 0x40018000UL +#define NRF_SWI3_BASE 0x40017000UL #define NRF_EGU4_BASE 0x40018000UL -#define NRF_SWI5_BASE 0x40019000UL +#define NRF_SWI4_BASE 0x40018000UL #define NRF_EGU5_BASE 0x40019000UL +#define NRF_SWI5_BASE 0x40019000UL #define NRF_TIMER3_BASE 0x4001A000UL #define NRF_TIMER4_BASE 0x4001B000UL #define NRF_PWM0_BASE 0x4001C000UL #define NRF_PDM_BASE 0x4001D000UL -#define NRF_NVMC_BASE 0x4001E000UL #define NRF_ACL_BASE 0x4001E000UL +#define NRF_NVMC_BASE 0x4001E000UL #define NRF_PPI_BASE 0x4001F000UL #define NRF_MWU_BASE 0x40020000UL #define NRF_PWM1_BASE 0x40021000UL #define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPI2_BASE 0x40023000UL #define NRF_SPIM2_BASE 0x40023000UL #define NRF_SPIS2_BASE 0x40023000UL -#define NRF_SPI2_BASE 0x40023000UL #define NRF_RTC2_BASE 0x40024000UL #define NRF_I2S_BASE 0x40025000UL #define NRF_FPU_BASE 0x40026000UL @@ -2352,6 +2383,7 @@ typedef struct { /*!< CRYPTOCELL Structure #define NRF_SPIM3_BASE 0x4002F000UL #define NRF_P0_BASE 0x50000000UL #define NRF_P1_BASE 0x50000300UL +#define NRF_CC_HOST_RGF_BASE 0x5002A000UL #define NRF_CRYPTOCELL_BASE 0x5002A000UL @@ -2361,23 +2393,23 @@ typedef struct { /*!< CRYPTOCELL Structure #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) -#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) -#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) #define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) #define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) #define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) #define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) #define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) #define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) -#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) #define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) #define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) @@ -2388,38 +2420,38 @@ typedef struct { /*!< CRYPTOCELL Structure #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) -#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) #define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) -#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) +#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) #define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) -#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) +#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) #define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) -#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) +#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) #define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) -#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) +#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) #define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) -#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) +#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) #define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) +#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) #define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) #define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) #define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) #define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) -#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) #define NRF_ACL ((NRF_ACL_Type *) NRF_ACL_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) #define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) #define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) #define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) #define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) #define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) -#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) #define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) #define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) #define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) @@ -2430,6 +2462,7 @@ typedef struct { /*!< CRYPTOCELL Structure #define NRF_SPIM3 ((NRF_SPIM_Type *) NRF_SPIM3_BASE) #define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) #define NRF_P1 ((NRF_GPIO_Type *) NRF_P1_BASE) +#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type *) NRF_CC_HOST_RGF_BASE) #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type *) NRF_CRYPTOCELL_BASE) diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd index 996112f94..1ff982163 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd @@ -8,7 +8,7 @@ 1 nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -61,14 +61,14 @@ POSSIBILITY OF SUCH DAMAGE.\n FICR Factory information configuration registers - FICR 0x10000000 - 32 0 0x1000 registers + FICR + 0x20 CODEPAGESIZE @@ -101,10 +101,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 - 4 + 0x2 + 0x4 DEVICEID[%s] - Description collection[0]: Device identifier + Description collection[n]: Device identifier 0x060 read-only 0xFFFFFFFF @@ -118,34 +118,34 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 - 4 + 0x4 + 0x4 ER[%s] - Description collection[0]: Encryption root, word 0 + Description collection[n]: Encryption root, word n 0x080 read-only 0xFFFFFFFF ER - Encryption root, word 0 + Encryption root, word n 0 31 - 4 - 4 + 0x4 + 0x4 IR[%s] - Description collection[0]: Identity Root, word 0 + Description collection[n]: Identity Root, word n 0x090 read-only 0xFFFFFFFF IR - Identity Root, word 0 + Identity Root, word n 0 31 @@ -179,10 +179,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 - 4 + 0x2 + 0x4 DEVICEADDR[%s] - Description collection[0]: Device address 0 + Description collection[n]: Device address n 0x0A4 read-only 0xFFFFFFFF @@ -406,26 +406,26 @@ POSSIBILITY OF SUCH DAMAGE.\n - 3 - 4 - UNUSED0[%s] - Description collection[0]: Unspecified + 0x3 + 0x4 + UNUSED8[%s] + Unspecified 0x014 read-write - 3 - 4 + 0x3 + 0x4 PRODTEST[%s] - Description collection[0]: Production test signature 0 + Description collection[n]: Production test signature n 0x350 read-only 0xFFFFFFFF PRODTEST - Production test signature 0 + Production test signature n 0 31 @@ -973,14 +973,14 @@ POSSIBILITY OF SUCH DAMAGE.\n UICR User information configuration registers - UICR 0x10001000 - 32 0 0x1000 registers + UICR + 0x20 UNUSED0 @@ -1007,10 +1007,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - 15 - 4 + 0xF + 0x4 NRFFW[%s] - Description collection[0]: Reserved for Nordic firmware design + Description collection[n]: Reserved for Nordic firmware design 0x014 read-write 0xFFFFFFFF @@ -1024,10 +1024,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 12 - 4 + 0xC + 0x4 NRFHW[%s] - Description collection[0]: Reserved for Nordic hardware design + Description collection[n]: Reserved for Nordic hardware design 0x050 read-write 0xFFFFFFFF @@ -1041,10 +1041,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 32 - 4 + 0x20 + 0x4 CUSTOMER[%s] - Description collection[0]: Reserved for customer + Description collection[n]: Reserved for customer 0x080 read-write 0xFFFFFFFF @@ -1058,10 +1058,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 - 4 + 0x2 + 0x4 PSELRESET[%s] - Description collection[0]: Mapping of the nRESET function + Description collection[n]: Mapping of the nRESET function 0x200 read-write 0xFFFFFFFF @@ -1197,33 +1197,6 @@ POSSIBILITY OF SUCH DAMAGE.\n - - DCDCDRIVE0 - Set drive level for REG0 DCDC mode. Using high drive will slightly reduce DCDC efficiency. - 0x300 - read-write - 0xFFFFFFFF - - - DCDCDRIVE0 - Set drive level for REG0 DCDC mode. - 0 - 0 - - - Low - Low drive - 0 - - - High - High drive - 1 - - - - - REGOUT0 GPIO reference voltage / external output supply voltage in high voltage mode @@ -1279,11 +1252,9 @@ POSSIBILITY OF SUCH DAMAGE.\n - POWER - Power control - POWER + CLOCK + Clock control 0x40000000 - 32 0 0x1000 @@ -1293,6 +1264,925 @@ POSSIBILITY OF SUCH DAMAGE.\n POWER_CLOCK 0 + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFXO crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + 0 + 0 + + + + + TASKS_HFCLKSTOP + Stop HFXO crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + 0 + 0 + + + + + TASKS_LFCLKSTART + Start LFCLK + 0x008 + write-only + + + TASKS_LFCLKSTART + 0 + 0 + + + + + TASKS_LFCLKSTOP + Stop LFCLK + 0x00C + write-only + + + TASKS_LFCLKSTOP + 0 + 0 + + + + + TASKS_CAL + Start calibration of LFRC + 0x010 + write-only + + + TASKS_CAL + 0 + 0 + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + 0 + 0 + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + 0 + 0 + + + + + EVENTS_HFCLKSTARTED + HFXO crystal oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + 0 + 0 + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + 0 + 0 + + + + + EVENTS_DONE + Calibration of LFRC completed + 0x10C + read-write + + + EVENTS_DONE + 0 + 0 + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + 0 + 0 + + + + + EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks + 0x128 + read-write + + + EVENTS_CTSTARTED + 0 + 0 + + + + + EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks + 0x12C + read-write + + + EVENTS_CTSTOPPED + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for HFCLKSTARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for LFCLKSTARTED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for DONE event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for CTTO event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTARTED + Write '1' to enable interrupt for CTSTARTED event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTOPPED + Write '1' to enable interrupt for CTSTOPPED event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for HFCLKSTARTED event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for LFCLKSTARTED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for DONE event + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to disable interrupt for CTTO event + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTARTED + Write '1' to disable interrupt for CTSTARTED event + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTSTOPPED + Write '1' to disable interrupt for CTSTOPPED event + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator (LFRC) + 0 + + + Xtal + 32.768 kHz crystal oscillator (LFXO) + 1 + + + Synth + 32.768 kHz synthesized from HFCLK (LFSYNT) + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + HFXODEBOUNCE + HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. + 0x528 + read-write + 0x00000010 + + + HFXODEBOUNCE + HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. + 0 + 7 + + + Db256us + 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. + 0x10 + + + Db1024us + 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. + 0x40 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + TRACECONFIG + Clocking options for the trace port debug interface + 0x55C + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. + 0 + 1 + + + 32MHz + 32 MHz trace port clock (TRACECLK = 16 MHz) + 0 + + + 16MHz + 16 MHz trace port clock (TRACECLK = 8 MHz) + 1 + + + 8MHz + 8 MHz trace port clock (TRACECLK = 4 MHz) + 2 + + + 4MHz + 4 MHz trace port clock (TRACECLK = 2 MHz) + 3 + + + + + TRACEMUX + Pin multiplexing of trace signals. See pin assignment chapter for more details. + 16 + 17 + + + GPIO + No trace signals routed to pins. All pins can be used as regular GPIOs. + 0 + + + Serial + SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. + 1 + + + Parallel + All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. + 2 + + + + + + + LFRCMODE + LFRC mode configuration + 0x5B4 + read-write + 0x00000000 + + + MODE + Set LFRC mode + 0 + 0 + + + Normal + Normal mode + 0 + + + ULP + Ultra-low power mode (ULP) + 1 + + + + + STATUS + Active LFRC mode. This field is read only. + 16 + 16 + + + Normal + Normal mode + 0 + + + ULP + Ultra-low power mode (ULP) + 1 + + + + + + + + + POWER + Power control + 0x40000000 + CLOCK + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + POWER + 0x20 TASKS_CONSTLAT @@ -1406,7 +2296,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POFWARN - Write '1' to Enable interrupt for POFWARN event + Write '1' to enable interrupt for POFWARN event 2 2 @@ -1433,7 +2323,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPENTER - Write '1' to Enable interrupt for SLEEPENTER event + Write '1' to enable interrupt for SLEEPENTER event 5 5 @@ -1460,7 +2350,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPEXIT - Write '1' to Enable interrupt for SLEEPEXIT event + Write '1' to enable interrupt for SLEEPEXIT event 6 6 @@ -1487,7 +2377,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBDETECTED - Write '1' to Enable interrupt for USBDETECTED event + Write '1' to enable interrupt for USBDETECTED event 7 7 @@ -1514,7 +2404,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBREMOVED - Write '1' to Enable interrupt for USBREMOVED event + Write '1' to enable interrupt for USBREMOVED event 8 8 @@ -1541,7 +2431,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBPWRRDY - Write '1' to Enable interrupt for USBPWRRDY event + Write '1' to enable interrupt for USBPWRRDY event 9 9 @@ -1576,7 +2466,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POFWARN - Write '1' to Disable interrupt for POFWARN event + Write '1' to disable interrupt for POFWARN event 2 2 @@ -1603,7 +2493,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPENTER - Write '1' to Disable interrupt for SLEEPENTER event + Write '1' to disable interrupt for SLEEPENTER event 5 5 @@ -1630,7 +2520,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPEXIT - Write '1' to Disable interrupt for SLEEPEXIT event + Write '1' to disable interrupt for SLEEPEXIT event 6 6 @@ -1657,7 +2547,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBDETECTED - Write '1' to Disable interrupt for USBDETECTED event + Write '1' to disable interrupt for USBDETECTED event 7 7 @@ -1684,7 +2574,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBREMOVED - Write '1' to Disable interrupt for USBREMOVED event + Write '1' to disable interrupt for USBREMOVED event 8 8 @@ -1711,7 +2601,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBPWRRDY - Write '1' to Disable interrupt for USBPWRRDY event + Write '1' to disable interrupt for USBPWRRDY event 9 9 @@ -1890,7 +2780,7 @@ POSSIBILITY OF SUCH DAMAGE.\n VBUS - Reset due to wake up from System OFF mode by Vbus rising into valid range + Reset due to wake up from System OFF mode by VBUS rising into valid range 20 20 @@ -1910,7 +2800,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RAMSTATUS - Deprecated register - RAM status register + Deprecated register - RAM status register 0x428 read-only 0x00000000 @@ -2057,13 +2947,13 @@ POSSIBILITY OF SUCH DAMAGE.\n POFCON - Power failure comparator configuration + Power-fail comparator configuration 0x510 read-write POF - Enable or disable power failure comparator + Enable or disable power failure warning 0 0 @@ -2081,7 +2971,7 @@ POSSIBILITY OF SUCH DAMAGE.\n THRESHOLD - Power failure comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). + Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. 1 4 @@ -2149,7 +3039,7 @@ POSSIBILITY OF SUCH DAMAGE.\n THRESHOLDVDDH - Power failure comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). + Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). 8 11 @@ -2346,21 +3236,21 @@ POSSIBILITY OF SUCH DAMAGE.\n 9 - 16 + 0x010 RAM[%s] Unspecified POWER_RAM 0x900 POWER - Description cluster[0]: RAM0 power control register + Description cluster[n]: RAMn power control register 0x000 read-write 0x0000FFFF S0POWER - Keep RAM section S0 ON or OFF in System ON mode. + Keep RAM section S0 on or off in System ON mode. 0 0 @@ -2378,7 +3268,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S1POWER - Keep RAM section S1 ON or OFF in System ON mode. + Keep RAM section S1 on or off in System ON mode. 1 1 @@ -2396,7 +3286,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S2POWER - Keep RAM section S2 ON or OFF in System ON mode. + Keep RAM section S2 on or off in System ON mode. 2 2 @@ -2414,7 +3304,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S3POWER - Keep RAM section S3 ON or OFF in System ON mode. + Keep RAM section S3 on or off in System ON mode. 3 3 @@ -2432,7 +3322,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S4POWER - Keep RAM section S4 ON or OFF in System ON mode. + Keep RAM section S4 on or off in System ON mode. 4 4 @@ -2450,7 +3340,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S5POWER - Keep RAM section S5 ON or OFF in System ON mode. + Keep RAM section S5 on or off in System ON mode. 5 5 @@ -2468,7 +3358,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S6POWER - Keep RAM section S6 ON or OFF in System ON mode. + Keep RAM section S6 on or off in System ON mode. 6 6 @@ -2486,7 +3376,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S7POWER - Keep RAM section S7 ON or OFF in System ON mode. + Keep RAM section S7 on or off in System ON mode. 7 7 @@ -2504,7 +3394,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S8POWER - Keep RAM section S8 ON or OFF in System ON mode. + Keep RAM section S8 on or off in System ON mode. 8 8 @@ -2522,7 +3412,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S9POWER - Keep RAM section S9 ON or OFF in System ON mode. + Keep RAM section S9 on or off in System ON mode. 9 9 @@ -2540,7 +3430,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S10POWER - Keep RAM section S10 ON or OFF in System ON mode. + Keep RAM section S10 on or off in System ON mode. 10 10 @@ -2558,7 +3448,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S11POWER - Keep RAM section S11 ON or OFF in System ON mode. + Keep RAM section S11 on or off in System ON mode. 11 11 @@ -2576,7 +3466,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S12POWER - Keep RAM section S12 ON or OFF in System ON mode. + Keep RAM section S12 on or off in System ON mode. 12 12 @@ -2594,7 +3484,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S13POWER - Keep RAM section S13 ON or OFF in System ON mode. + Keep RAM section S13 on or off in System ON mode. 13 13 @@ -2612,7 +3502,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S14POWER - Keep RAM section S14 ON or OFF in System ON mode. + Keep RAM section S14 on or off in System ON mode. 14 14 @@ -2630,7 +3520,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S15POWER - Keep RAM section S15 ON or OFF in System ON mode. + Keep RAM section S15 on or off in System ON mode. 15 15 @@ -2648,7 +3538,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S0RETENTION - Keep retention on RAM section S0 when RAM section is in OFF + Keep retention on RAM section S0 when RAM section is off 16 16 @@ -2666,7 +3556,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S1RETENTION - Keep retention on RAM section S1 when RAM section is in OFF + Keep retention on RAM section S1 when RAM section is off 17 17 @@ -2684,7 +3574,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S2RETENTION - Keep retention on RAM section S2 when RAM section is in OFF + Keep retention on RAM section S2 when RAM section is off 18 18 @@ -2702,7 +3592,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S3RETENTION - Keep retention on RAM section S3 when RAM section is in OFF + Keep retention on RAM section S3 when RAM section is off 19 19 @@ -2720,7 +3610,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S4RETENTION - Keep retention on RAM section S4 when RAM section is in OFF + Keep retention on RAM section S4 when RAM section is off 20 20 @@ -2738,7 +3628,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S5RETENTION - Keep retention on RAM section S5 when RAM section is in OFF + Keep retention on RAM section S5 when RAM section is off 21 21 @@ -2756,7 +3646,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S6RETENTION - Keep retention on RAM section S6 when RAM section is in OFF + Keep retention on RAM section S6 when RAM section is off 22 22 @@ -2774,7 +3664,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S7RETENTION - Keep retention on RAM section S7 when RAM section is in OFF + Keep retention on RAM section S7 when RAM section is off 23 23 @@ -2792,7 +3682,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S8RETENTION - Keep retention on RAM section S8 when RAM section is in OFF + Keep retention on RAM section S8 when RAM section is off 24 24 @@ -2810,7 +3700,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S9RETENTION - Keep retention on RAM section S9 when RAM section is in OFF + Keep retention on RAM section S9 when RAM section is off 25 25 @@ -2828,7 +3718,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S10RETENTION - Keep retention on RAM section S10 when RAM section is in OFF + Keep retention on RAM section S10 when RAM section is off 26 26 @@ -2846,7 +3736,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S11RETENTION - Keep retention on RAM section S11 when RAM section is in OFF + Keep retention on RAM section S11 when RAM section is off 27 27 @@ -2864,7 +3754,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S12RETENTION - Keep retention on RAM section S12 when RAM section is in OFF + Keep retention on RAM section S12 when RAM section is off 28 28 @@ -2882,7 +3772,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S13RETENTION - Keep retention on RAM section S13 when RAM section is in OFF + Keep retention on RAM section S13 when RAM section is off 29 29 @@ -2900,7 +3790,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S14RETENTION - Keep retention on RAM section S14 when RAM section is in OFF + Keep retention on RAM section S14 when RAM section is off 30 30 @@ -2918,7 +3808,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S15RETENTION - Keep retention on RAM section S15 when RAM section is in OFF + Keep retention on RAM section S15 when RAM section is off 31 31 @@ -2938,14 +3828,14 @@ POSSIBILITY OF SUCH DAMAGE.\n POWERSET - Description cluster[0]: RAM0 power control set register + Description cluster[n]: RAMn power control set register 0x004 write-only 0x0000FFFF S0POWER - Keep RAM section S0 of RAM0 on or off in System ON mode + Keep RAM section S0 of RAMn on or off in System ON mode 0 0 @@ -2958,7 +3848,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S1POWER - Keep RAM section S1 of RAM0 on or off in System ON mode + Keep RAM section S1 of RAMn on or off in System ON mode 1 1 @@ -2971,7 +3861,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S2POWER - Keep RAM section S2 of RAM0 on or off in System ON mode + Keep RAM section S2 of RAMn on or off in System ON mode 2 2 @@ -2984,7 +3874,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S3POWER - Keep RAM section S3 of RAM0 on or off in System ON mode + Keep RAM section S3 of RAMn on or off in System ON mode 3 3 @@ -2997,7 +3887,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S4POWER - Keep RAM section S4 of RAM0 on or off in System ON mode + Keep RAM section S4 of RAMn on or off in System ON mode 4 4 @@ -3010,7 +3900,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S5POWER - Keep RAM section S5 of RAM0 on or off in System ON mode + Keep RAM section S5 of RAMn on or off in System ON mode 5 5 @@ -3023,7 +3913,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S6POWER - Keep RAM section S6 of RAM0 on or off in System ON mode + Keep RAM section S6 of RAMn on or off in System ON mode 6 6 @@ -3036,7 +3926,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S7POWER - Keep RAM section S7 of RAM0 on or off in System ON mode + Keep RAM section S7 of RAMn on or off in System ON mode 7 7 @@ -3049,7 +3939,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S8POWER - Keep RAM section S8 of RAM0 on or off in System ON mode + Keep RAM section S8 of RAMn on or off in System ON mode 8 8 @@ -3062,7 +3952,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S9POWER - Keep RAM section S9 of RAM0 on or off in System ON mode + Keep RAM section S9 of RAMn on or off in System ON mode 9 9 @@ -3075,7 +3965,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S10POWER - Keep RAM section S10 of RAM0 on or off in System ON mode + Keep RAM section S10 of RAMn on or off in System ON mode 10 10 @@ -3088,7 +3978,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S11POWER - Keep RAM section S11 of RAM0 on or off in System ON mode + Keep RAM section S11 of RAMn on or off in System ON mode 11 11 @@ -3101,7 +3991,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S12POWER - Keep RAM section S12 of RAM0 on or off in System ON mode + Keep RAM section S12 of RAMn on or off in System ON mode 12 12 @@ -3114,7 +4004,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S13POWER - Keep RAM section S13 of RAM0 on or off in System ON mode + Keep RAM section S13 of RAMn on or off in System ON mode 13 13 @@ -3127,7 +4017,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S14POWER - Keep RAM section S14 of RAM0 on or off in System ON mode + Keep RAM section S14 of RAMn on or off in System ON mode 14 14 @@ -3140,7 +4030,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S15POWER - Keep RAM section S15 of RAM0 on or off in System ON mode + Keep RAM section S15 of RAMn on or off in System ON mode 15 15 @@ -3363,14 +4253,14 @@ POSSIBILITY OF SUCH DAMAGE.\n POWERCLR - Description cluster[0]: RAM0 power control clear register + Description cluster[n]: RAMn power control clear register 0x008 write-only 0x0000FFFF S0POWER - Keep RAM section S0 of RAM0 on or off in System ON mode + Keep RAM section S0 of RAMn on or off in System ON mode 0 0 @@ -3383,7 +4273,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S1POWER - Keep RAM section S1 of RAM0 on or off in System ON mode + Keep RAM section S1 of RAMn on or off in System ON mode 1 1 @@ -3396,7 +4286,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S2POWER - Keep RAM section S2 of RAM0 on or off in System ON mode + Keep RAM section S2 of RAMn on or off in System ON mode 2 2 @@ -3409,7 +4299,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S3POWER - Keep RAM section S3 of RAM0 on or off in System ON mode + Keep RAM section S3 of RAMn on or off in System ON mode 3 3 @@ -3422,7 +4312,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S4POWER - Keep RAM section S4 of RAM0 on or off in System ON mode + Keep RAM section S4 of RAMn on or off in System ON mode 4 4 @@ -3435,7 +4325,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S5POWER - Keep RAM section S5 of RAM0 on or off in System ON mode + Keep RAM section S5 of RAMn on or off in System ON mode 5 5 @@ -3448,7 +4338,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S6POWER - Keep RAM section S6 of RAM0 on or off in System ON mode + Keep RAM section S6 of RAMn on or off in System ON mode 6 6 @@ -3461,7 +4351,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S7POWER - Keep RAM section S7 of RAM0 on or off in System ON mode + Keep RAM section S7 of RAMn on or off in System ON mode 7 7 @@ -3474,7 +4364,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S8POWER - Keep RAM section S8 of RAM0 on or off in System ON mode + Keep RAM section S8 of RAMn on or off in System ON mode 8 8 @@ -3487,7 +4377,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S9POWER - Keep RAM section S9 of RAM0 on or off in System ON mode + Keep RAM section S9 of RAMn on or off in System ON mode 9 9 @@ -3500,7 +4390,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S10POWER - Keep RAM section S10 of RAM0 on or off in System ON mode + Keep RAM section S10 of RAMn on or off in System ON mode 10 10 @@ -3513,7 +4403,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S11POWER - Keep RAM section S11 of RAM0 on or off in System ON mode + Keep RAM section S11 of RAMn on or off in System ON mode 11 11 @@ -3526,7 +4416,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S12POWER - Keep RAM section S12 of RAM0 on or off in System ON mode + Keep RAM section S12 of RAMn on or off in System ON mode 12 12 @@ -3539,7 +4429,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S13POWER - Keep RAM section S13 of RAM0 on or off in System ON mode + Keep RAM section S13 of RAMn on or off in System ON mode 13 13 @@ -3552,7 +4442,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S14POWER - Keep RAM section S14 of RAM0 on or off in System ON mode + Keep RAM section S14 of RAMn on or off in System ON mode 14 14 @@ -3565,7 +4455,7 @@ POSSIBILITY OF SUCH DAMAGE.\n S15POWER - Keep RAM section S15 of RAM0 on or off in System ON mode + Keep RAM section S15 of RAMn on or off in System ON mode 15 15 @@ -3789,929 +4679,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - - CLOCK - Clock control - CLOCK - 0x40000000 - 32 - POWER - - 0 - 0x1000 - registers - - - POWER_CLOCK - 0 - - - - TASKS_HFCLKSTART - Start HFCLK crystal oscillator - 0x000 - write-only - - - TASKS_HFCLKSTART - 0 - 0 - - - - - TASKS_HFCLKSTOP - Stop HFCLK crystal oscillator - 0x004 - write-only - - - TASKS_HFCLKSTOP - 0 - 0 - - - - - TASKS_LFCLKSTART - Start LFCLK source - 0x008 - write-only - - - TASKS_LFCLKSTART - 0 - 0 - - - - - TASKS_LFCLKSTOP - Stop LFCLK source - 0x00C - write-only - - - TASKS_LFCLKSTOP - 0 - 0 - - - - - TASKS_CAL - Start calibration of LFRC or LFULP oscillator - 0x010 - write-only - - - TASKS_CAL - 0 - 0 - - - - - TASKS_CTSTART - Start calibration timer - 0x014 - write-only - - - TASKS_CTSTART - 0 - 0 - - - - - TASKS_CTSTOP - Stop calibration timer - 0x018 - write-only - - - TASKS_CTSTOP - 0 - 0 - - - - - EVENTS_HFCLKSTARTED - HFCLK oscillator started - 0x100 - read-write - - - EVENTS_HFCLKSTARTED - 0 - 0 - - - - - EVENTS_LFCLKSTARTED - LFCLK started - 0x104 - read-write - - - EVENTS_LFCLKSTARTED - 0 - 0 - - - - - EVENTS_DONE - Calibration of LFCLK RC oscillator complete event - 0x10C - read-write - - - EVENTS_DONE - 0 - 0 - - - - - EVENTS_CTTO - Calibration timer timeout - 0x110 - read-write - - - EVENTS_CTTO - 0 - 0 - - - - - EVENTS_CTSTARTED - Calibration timer has been started and is ready to process new tasks - 0x128 - read-write - - - EVENTS_CTSTARTED - 0 - 0 - - - - - EVENTS_CTSTOPPED - Calibration timer has been stopped and is ready to process new tasks - 0x12C - read-write - - - EVENTS_CTSTOPPED - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - HFCLKSTARTED - Write '1' to Enable interrupt for HFCLKSTARTED event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LFCLKSTARTED - Write '1' to Enable interrupt for LFCLKSTARTED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DONE - Write '1' to Enable interrupt for DONE event - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTTO - Write '1' to Enable interrupt for CTTO event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTSTARTED - Write '1' to Enable interrupt for CTSTARTED event - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTSTOPPED - Write '1' to Enable interrupt for CTSTOPPED event - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - HFCLKSTARTED - Write '1' to Disable interrupt for HFCLKSTARTED event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LFCLKSTARTED - Write '1' to Disable interrupt for LFCLKSTARTED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - DONE - Write '1' to Disable interrupt for DONE event - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CTTO - Write '1' to Disable interrupt for CTTO event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CTSTARTED - Write '1' to Disable interrupt for CTSTARTED event - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - CTSTOPPED - Write '1' to Disable interrupt for CTSTOPPED event - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - HFCLKRUN - Status indicating that HFCLKSTART task has been triggered - 0x408 - read-only - - - STATUS - HFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLKSTAT - HFCLK status - 0x40C - read-only - - - SRC - Source of HFCLK - 0 - 0 - - - RC - 64 MHz internal oscillator (HFINT) - 0 - - - Xtal - 64 MHz crystal oscillator (HFXO) - 1 - - - - - STATE - HFCLK state - 16 - 16 - - - NotRunning - HFCLK not running - 0 - - - Running - HFCLK running - 1 - - - - - - - LFCLKRUN - Status indicating that LFCLKSTART task has been triggered - 0x414 - read-only - - - STATUS - LFCLKSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - LFCLKSTAT - LFCLK status - 0x418 - read-only - - - SRC - Source of LFCLK - 0 - 1 - - - RC - 32.768 kHz RC oscillator - 0 - - - Xtal - 32.768 kHz crystal oscillator - 1 - - - Synth - 32.768 kHz synthesized from HFCLK - 2 - - - - - STATE - LFCLK state - 16 - 16 - - - NotRunning - LFCLK not running - 0 - - - Running - LFCLK running - 1 - - - - - - - LFCLKSRCCOPY - Copy of LFCLKSRC register, set when LFCLKSTART task was triggered - 0x41C - read-only - - - SRC - Clock source - 0 - 1 - - - RC - 32.768 kHz RC oscillator - 0 - - - Xtal - 32.768 kHz crystal oscillator - 1 - - - Synth - 32.768 kHz synthesized from HFCLK - 2 - - - - - - - LFCLKSRC - Clock source for the LFCLK - 0x518 - read-write - - - SRC - Clock source - 0 - 1 - - - RC - 32.768 kHz RC oscillator - 0 - - - Xtal - 32.768 kHz crystal oscillator - 1 - - - Synth - 32.768 kHz synthesized from HFCLK - 2 - - - - - BYPASS - Enable or disable bypass of LFCLK crystal oscillator with external clock source - 16 - 16 - - - Disabled - Disable (use with Xtal or low-swing external source) - 0 - - - Enabled - Enable (use with rail-to-rail external source) - 1 - - - - - EXTERNAL - Enable or disable external source for LFCLK - 17 - 17 - - - Disabled - Disable external source (use with Xtal) - 0 - - - Enabled - Enable use of external source instead of Xtal (SRC needs to be set to Xtal) - 1 - - - - - - - HFXODEBOUNCE - HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. - 0x528 - read-write - 0x00000010 - - - HFXODEBOUNCE - HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. - 0 - 7 - - - Db256us - 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. - 0x10 - - - Db1024us - 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. - 0x40 - - - - - - - CTIV - Calibration timer interval - 0x538 - read-write - - - CTIV - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. - 0 - 6 - - - - - TRACECONFIG - Clocking options for the Trace Port debug interface - 0x55C - read-write - 0x00000000 - - - TRACEPORTSPEED - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. - 0 - 1 - - - 32MHz - 32 MHz Trace Port clock (TRACECLK = 16 MHz) - 0 - - - 16MHz - 16 MHz Trace Port clock (TRACECLK = 8 MHz) - 1 - - - 8MHz - 8 MHz Trace Port clock (TRACECLK = 4 MHz) - 2 - - - 4MHz - 4 MHz Trace Port clock (TRACECLK = 2 MHz) - 3 - - - - - TRACEMUX - Pin multiplexing of trace signals. See pin assignment chapter for more details. - 16 - 17 - - - GPIO - No trace signals routed to pins. All pins can be used as regular GPIOs. - 0 - - - Serial - SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. - 1 - - - Parallel - All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. - 2 - - - - - - - LFRCMODE - LFRC mode configuration - 0x5B4 - read-write - 0x00000000 - - - MODE - Set LFRC mode - 0 - 0 - - - Normal - Normal mode - 0 - - - ULP - Ultra-low power mode (ULP) - 1 - - - - - STATUS - Active LFRC mode. This field is read only. - 16 - 16 - - - Normal - Normal mode - 0 - - - ULP - Ultra-low power mode (ULP) - 1 - - - - - - - RADIO - 2.4 GHz Radio - RADIO + 2.4 GHz radio 0x40001000 - 32 0 0x1000 @@ -4721,6 +4692,8 @@ POSSIBILITY OF SUCH DAMAGE.\n RADIO 1 + RADIO + 0x20 TASKS_TXEN @@ -4789,7 +4762,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength. + Start the RSSI and take one single sample of the receive signal strength 0x014 write-only @@ -4841,7 +4814,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_EDSTART - Start the Energy Detect measurement used in IEEE 802.15.4 mode + Start the energy detect measurement used in IEEE 802.15.4 mode 0x024 write-only @@ -4854,7 +4827,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_EDSTOP - Stop the Energy Detect measurement + Stop the energy detect measurement 0x028 write-only @@ -4867,7 +4840,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CCASTART - Start the Clear Channel Assessment used in IEEE 802.15.4 mode + Start the clear channel assessment used in IEEE 802.15.4 mode 0x02C write-only @@ -4880,7 +4853,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CCASTOP - Stop the Clear Channel Assessment + Stop the clear channel assessment 0x030 write-only @@ -4984,7 +4957,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_RSSIEND - Sampling of receive signal strength complete. + Sampling of receive signal strength complete 0x11C read-write @@ -4997,7 +4970,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_BCMATCH - Bit counter reached bit count value. + Bit counter reached bit count value 0x128 read-write @@ -5049,7 +5022,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_EDEND - Sampling of Energy Detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write @@ -5062,7 +5035,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_EDSTOPPED - The sampling of Energy Detection has stopped + The sampling of energy detection has stopped 0x140 read-write @@ -5153,7 +5126,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_MHRMATCH - MAC Header match found. + MAC header match found 0x15C read-write @@ -5535,7 +5508,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Enable interrupt for READY event + Write '1' to enable interrupt for READY event 0 0 @@ -5562,7 +5535,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ADDRESS - Write '1' to Enable interrupt for ADDRESS event + Write '1' to enable interrupt for ADDRESS event 1 1 @@ -5589,7 +5562,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PAYLOAD - Write '1' to Enable interrupt for PAYLOAD event + Write '1' to enable interrupt for PAYLOAD event 2 2 @@ -5616,7 +5589,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Enable interrupt for END event + Write '1' to enable interrupt for END event 3 3 @@ -5643,7 +5616,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DISABLED - Write '1' to Enable interrupt for DISABLED event + Write '1' to enable interrupt for DISABLED event 4 4 @@ -5670,7 +5643,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DEVMATCH - Write '1' to Enable interrupt for DEVMATCH event + Write '1' to enable interrupt for DEVMATCH event 5 5 @@ -5697,7 +5670,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DEVMISS - Write '1' to Enable interrupt for DEVMISS event + Write '1' to enable interrupt for DEVMISS event 6 6 @@ -5724,7 +5697,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RSSIEND - Write '1' to Enable interrupt for RSSIEND event + Write '1' to enable interrupt for RSSIEND event 7 7 @@ -5751,7 +5724,7 @@ POSSIBILITY OF SUCH DAMAGE.\n BCMATCH - Write '1' to Enable interrupt for BCMATCH event + Write '1' to enable interrupt for BCMATCH event 10 10 @@ -5778,7 +5751,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CRCOK - Write '1' to Enable interrupt for CRCOK event + Write '1' to enable interrupt for CRCOK event 12 12 @@ -5805,7 +5778,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CRCERROR - Write '1' to Enable interrupt for CRCERROR event + Write '1' to enable interrupt for CRCERROR event 13 13 @@ -5832,7 +5805,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FRAMESTART - Write '1' to Enable interrupt for FRAMESTART event + Write '1' to enable interrupt for FRAMESTART event 14 14 @@ -5859,7 +5832,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EDEND - Write '1' to Enable interrupt for EDEND event + Write '1' to enable interrupt for EDEND event 15 15 @@ -5886,7 +5859,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EDSTOPPED - Write '1' to Enable interrupt for EDSTOPPED event + Write '1' to enable interrupt for EDSTOPPED event 16 16 @@ -5913,7 +5886,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCAIDLE - Write '1' to Enable interrupt for CCAIDLE event + Write '1' to enable interrupt for CCAIDLE event 17 17 @@ -5940,7 +5913,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCABUSY - Write '1' to Enable interrupt for CCABUSY event + Write '1' to enable interrupt for CCABUSY event 18 18 @@ -5967,7 +5940,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCASTOPPED - Write '1' to Enable interrupt for CCASTOPPED event + Write '1' to enable interrupt for CCASTOPPED event 19 19 @@ -5994,7 +5967,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEBOOST - Write '1' to Enable interrupt for RATEBOOST event + Write '1' to enable interrupt for RATEBOOST event 20 20 @@ -6021,7 +5994,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXREADY - Write '1' to Enable interrupt for TXREADY event + Write '1' to enable interrupt for TXREADY event 21 21 @@ -6048,7 +6021,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXREADY - Write '1' to Enable interrupt for RXREADY event + Write '1' to enable interrupt for RXREADY event 22 22 @@ -6075,7 +6048,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MHRMATCH - Write '1' to Enable interrupt for MHRMATCH event + Write '1' to enable interrupt for MHRMATCH event 23 23 @@ -6102,7 +6075,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PHYEND - Write '1' to Enable interrupt for PHYEND event + Write '1' to enable interrupt for PHYEND event 27 27 @@ -6137,7 +6110,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Disable interrupt for READY event + Write '1' to disable interrupt for READY event 0 0 @@ -6164,7 +6137,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ADDRESS - Write '1' to Disable interrupt for ADDRESS event + Write '1' to disable interrupt for ADDRESS event 1 1 @@ -6191,7 +6164,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PAYLOAD - Write '1' to Disable interrupt for PAYLOAD event + Write '1' to disable interrupt for PAYLOAD event 2 2 @@ -6218,7 +6191,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Disable interrupt for END event + Write '1' to disable interrupt for END event 3 3 @@ -6245,7 +6218,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DISABLED - Write '1' to Disable interrupt for DISABLED event + Write '1' to disable interrupt for DISABLED event 4 4 @@ -6272,7 +6245,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DEVMATCH - Write '1' to Disable interrupt for DEVMATCH event + Write '1' to disable interrupt for DEVMATCH event 5 5 @@ -6299,7 +6272,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DEVMISS - Write '1' to Disable interrupt for DEVMISS event + Write '1' to disable interrupt for DEVMISS event 6 6 @@ -6326,7 +6299,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RSSIEND - Write '1' to Disable interrupt for RSSIEND event + Write '1' to disable interrupt for RSSIEND event 7 7 @@ -6353,7 +6326,7 @@ POSSIBILITY OF SUCH DAMAGE.\n BCMATCH - Write '1' to Disable interrupt for BCMATCH event + Write '1' to disable interrupt for BCMATCH event 10 10 @@ -6380,7 +6353,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CRCOK - Write '1' to Disable interrupt for CRCOK event + Write '1' to disable interrupt for CRCOK event 12 12 @@ -6407,7 +6380,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CRCERROR - Write '1' to Disable interrupt for CRCERROR event + Write '1' to disable interrupt for CRCERROR event 13 13 @@ -6434,7 +6407,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FRAMESTART - Write '1' to Disable interrupt for FRAMESTART event + Write '1' to disable interrupt for FRAMESTART event 14 14 @@ -6461,7 +6434,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EDEND - Write '1' to Disable interrupt for EDEND event + Write '1' to disable interrupt for EDEND event 15 15 @@ -6488,7 +6461,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EDSTOPPED - Write '1' to Disable interrupt for EDSTOPPED event + Write '1' to disable interrupt for EDSTOPPED event 16 16 @@ -6515,7 +6488,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCAIDLE - Write '1' to Disable interrupt for CCAIDLE event + Write '1' to disable interrupt for CCAIDLE event 17 17 @@ -6542,7 +6515,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCABUSY - Write '1' to Disable interrupt for CCABUSY event + Write '1' to disable interrupt for CCABUSY event 18 18 @@ -6569,7 +6542,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CCASTOPPED - Write '1' to Disable interrupt for CCASTOPPED event + Write '1' to disable interrupt for CCASTOPPED event 19 19 @@ -6596,7 +6569,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RATEBOOST - Write '1' to Disable interrupt for RATEBOOST event + Write '1' to disable interrupt for RATEBOOST event 20 20 @@ -6623,7 +6596,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXREADY - Write '1' to Disable interrupt for TXREADY event + Write '1' to disable interrupt for TXREADY event 21 21 @@ -6650,7 +6623,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXREADY - Write '1' to Disable interrupt for RXREADY event + Write '1' to disable interrupt for RXREADY event 22 22 @@ -6677,7 +6650,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MHRMATCH - Write '1' to Disable interrupt for MHRMATCH event + Write '1' to disable interrupt for MHRMATCH event 23 23 @@ -6704,7 +6677,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PHYEND - Write '1' to Disable interrupt for PHYEND event + Write '1' to disable interrupt for PHYEND event 27 27 @@ -6898,7 +6871,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXPOWER - RADIO output power. + RADIO output power 0 7 @@ -6970,7 +6943,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Neg30dBm Deprecated enumerator - -40 dBm - 0xD8 + 0xFF Neg40dBm @@ -6989,7 +6962,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MODE - Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. 0 3 @@ -7005,22 +6978,22 @@ POSSIBILITY OF SUCH DAMAGE.\n Ble_1Mbit - 1 Mbit/s Bluetooth Low Energy + 1 Mbit/s BLE 3 Ble_2Mbit - 2 Mbit/s Bluetooth Low Energy + 2 Mbit/s BLE 4 Ble_LR125Kbit - Long range 125 kbit/s (TX Only - RX supports both) + Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX 5 Ble_LR500Kbit - Long range 500 kbit/s (TX Only - RX supports both) + Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX 6 @@ -7076,7 +7049,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CILEN - Length of Code Indicator - Long Range + Length of code indicator - long range 22 23 @@ -7103,7 +7076,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LongRange - Preamble - used for BTLE Long Range + Preamble - used for BLE long range 3 @@ -7166,7 +7139,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Little - Least Significant bit on air first + Least significant bit on air first 0 @@ -7544,13 +7517,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TIFS - Inter Frame Spacing in us + Interframe spacing in us 0x544 read-write TIFS - Inter Frame Spacing in us + Interframe spacing in us 0 9 @@ -7661,32 +7634,32 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 DAB[%s] - Description collection[0]: Device address base segment 0 + Description collection[n]: Device address base segment n 0x600 read-write DAB - Device address base segment 0 + Device address base segment n 0 31 - 8 - 4 + 0x8 + 0x4 DAP[%s] - Description collection[0]: Device address prefix 0 + Description collection[n]: Device address prefix n 0x620 read-write DAP - Device address prefix 0 + Device address prefix n 0 15 @@ -7894,7 +7867,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MHRMATCHCONF - Search Pattern Configuration + Search pattern configuration 0x644 read-write @@ -7956,14 +7929,14 @@ POSSIBILITY OF SUCH DAMAGE.\n SFD - IEEE 802.15.4 Start of Frame Delimiter + IEEE 802.15.4 start of frame delimiter 0x660 read-write 0x000000A7 SFD - IEEE 802.15.4 Start of Frame Delimiter. Note, the least significant 4-bits of the SFD cannot all be zeros. + IEEE 802.15.4 start of frame delimiter 0 7 @@ -7971,14 +7944,14 @@ POSSIBILITY OF SUCH DAMAGE.\n EDCNT - IEEE 802.15.4 Energy Detect Loop Count + IEEE 802.15.4 energy detect loop count 0x664 read-write 0x00000000 EDCNT - IEEE 802.15.4 Energy Detect Loop Count + IEEE 802.15.4 energy detect loop count 0 20 @@ -7986,14 +7959,14 @@ POSSIBILITY OF SUCH DAMAGE.\n EDSAMPLE - IEEE 802.15.4 Energy Detect Level + IEEE 802.15.4 energy detect level 0x668 read-write 0x00000000 EDLVL - IEEE 802.15.4 Energy Detect Level + IEEE 802.15.4 energy detect level 0 7 @@ -8001,53 +7974,53 @@ POSSIBILITY OF SUCH DAMAGE.\n CCACTRL - IEEE 802.15.4 Clear Channel Assessment Control + IEEE 802.15.4 clear channel assessment control 0x66C read-write 0x00000000 CCAMODE - CCA Mode Of Operation + CCA mode of operation 0 2 EdMode - Energy Above Threshold + Energy above threshold 0 CarrierMode - Carrier Seen + Carrier seen 1 CarrierAndEdMode - Energy Above Threshold AND Carrier Seen + Energy above threshold AND carrier seen 2 CarrierOrEdMode - Energy Above Threshold OR Carrier Seen + Energy above threshold OR carrier seen 3 EdModeTest1 - Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. 4 CCAEDTHRES - CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode. + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. 8 15 CCACORRTHRES - CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. 16 23 @@ -8088,12 +8061,1010 @@ POSSIBILITY OF SUCH DAMAGE.\n + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + 0 + 0 + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + 0 + 0 + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + 0 + 0 + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + 0 + 0 + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + 0 + 0 + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + 0 + 0 + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + 0 + 0 + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + 0 + 0 + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + 0 + 0 + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + CTS_STARTRX + Shortcut between CTS event and STARTRX task + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between NCTS event and STOPRX task + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for CTS event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for NCTS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for RXDRDY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for TXDRDY event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for RXTO event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for CTS event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for NCTS event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for RXDRDY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for TXDRDY event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for RXTO event + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSEL + Unspecified + UART_PSEL + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + + + UARTE0 UART with EasyDMA 0 - UARTE 0x40002000 - 32 + UART0 UARTE 0 @@ -8104,6 +9075,8 @@ POSSIBILITY OF SUCH DAMAGE.\n UARTE0_UART0 2 + UARTE + 0x20 TASKS_STARTRX @@ -8571,7 +9544,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CTS - Write '1' to Enable interrupt for CTS event + Write '1' to enable interrupt for CTS event 0 0 @@ -8598,7 +9571,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NCTS - Write '1' to Enable interrupt for NCTS event + Write '1' to enable interrupt for NCTS event 1 1 @@ -8625,7 +9598,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXDRDY - Write '1' to Enable interrupt for RXDRDY event + Write '1' to enable interrupt for RXDRDY event 2 2 @@ -8652,7 +9625,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Enable interrupt for ENDRX event + Write '1' to enable interrupt for ENDRX event 4 4 @@ -8679,7 +9652,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXDRDY - Write '1' to Enable interrupt for TXDRDY event + Write '1' to enable interrupt for TXDRDY event 7 7 @@ -8706,7 +9679,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDTX - Write '1' to Enable interrupt for ENDTX event + Write '1' to enable interrupt for ENDTX event 8 8 @@ -8733,7 +9706,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Enable interrupt for ERROR event + Write '1' to enable interrupt for ERROR event 9 9 @@ -8760,7 +9733,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXTO - Write '1' to Enable interrupt for RXTO event + Write '1' to enable interrupt for RXTO event 17 17 @@ -8787,7 +9760,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTARTED - Write '1' to Enable interrupt for RXSTARTED event + Write '1' to enable interrupt for RXSTARTED event 19 19 @@ -8814,7 +9787,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTARTED - Write '1' to Enable interrupt for TXSTARTED event + Write '1' to enable interrupt for TXSTARTED event 20 20 @@ -8841,7 +9814,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTOPPED - Write '1' to Enable interrupt for TXSTOPPED event + Write '1' to enable interrupt for TXSTOPPED event 22 22 @@ -8876,7 +9849,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CTS - Write '1' to Disable interrupt for CTS event + Write '1' to disable interrupt for CTS event 0 0 @@ -8903,7 +9876,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NCTS - Write '1' to Disable interrupt for NCTS event + Write '1' to disable interrupt for NCTS event 1 1 @@ -8930,7 +9903,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXDRDY - Write '1' to Disable interrupt for RXDRDY event + Write '1' to disable interrupt for RXDRDY event 2 2 @@ -8957,7 +9930,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Disable interrupt for ENDRX event + Write '1' to disable interrupt for ENDRX event 4 4 @@ -8984,7 +9957,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXDRDY - Write '1' to Disable interrupt for TXDRDY event + Write '1' to disable interrupt for TXDRDY event 7 7 @@ -9011,7 +9984,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDTX - Write '1' to Disable interrupt for ENDTX event + Write '1' to disable interrupt for ENDTX event 8 8 @@ -9038,7 +10011,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Disable interrupt for ERROR event + Write '1' to disable interrupt for ERROR event 9 9 @@ -9065,7 +10038,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXTO - Write '1' to Disable interrupt for RXTO event + Write '1' to disable interrupt for RXTO event 17 17 @@ -9092,7 +10065,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTARTED - Write '1' to Disable interrupt for RXSTARTED event + Write '1' to disable interrupt for RXSTARTED event 19 19 @@ -9119,7 +10092,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTARTED - Write '1' to Disable interrupt for TXSTARTED event + Write '1' to disable interrupt for TXSTARTED event 20 20 @@ -9146,7 +10119,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTOPPED - Write '1' to Disable interrupt for TXSTOPPED event + Write '1' to disable interrupt for TXSTOPPED event 22 22 @@ -9714,210 +10687,35 @@ POSSIBILITY OF SUCH DAMAGE.\n - UART0 - Universal Asynchronous Receiver/Transmitter - UART - 0x40002000 - 32 - UARTE0 - UART + SPI0 + Serial Peripheral Interface 0 + 0x40003000 + SPI 0 0x1000 registers - UARTE0_UART0 - 2 + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + SPI + 0x20 - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - 0 - 0 - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - 0 - 0 - - - - - TASKS_SUSPEND - Suspend UART - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - 0 - 0 - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - 0 - 0 - - - - - EVENTS_RXDRDY - Data received in RXD + EVENTS_READY + TXD byte sent and RXD byte received 0x108 read-write - EVENTS_RXDRDY + EVENTS_READY 0 0 - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - 0 - 0 - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - CTS_STARTRX - Shortcut between CTS event and STARTRX task - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - NCTS_STOPRX - Shortcut between NCTS event and STOPRX task - 4 - 4 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - INTENSET Enable interrupt @@ -9925,62 +10723,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - CTS - Write '1' to Enable interrupt for CTS event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NCTS - Write '1' to Enable interrupt for NCTS event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXDRDY - Write '1' to Enable interrupt for RXDRDY event + READY + Write '1' to enable interrupt for READY event 2 2 @@ -10005,87 +10749,6 @@ POSSIBILITY OF SUCH DAMAGE.\n - - TXDRDY - Write '1' to Enable interrupt for TXDRDY event - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to Enable interrupt for ERROR event - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXTO - Write '1' to Enable interrupt for RXTO event - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - @@ -10095,62 +10758,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - CTS - Write '1' to Disable interrupt for CTS event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NCTS - Write '1' to Disable interrupt for NCTS event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXDRDY - Write '1' to Disable interrupt for RXDRDY event + READY + Write '1' to disable interrupt for READY event 2 2 @@ -10175,195 +10784,29 @@ POSSIBILITY OF SUCH DAMAGE.\n - - TXDRDY - Write '1' to Disable interrupt for TXDRDY event - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to Disable interrupt for ERROR event - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXTO - Write '1' to Disable interrupt for RXTO event - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x480 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - PARITY - Parity error - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - FRAMING - Framing error occurred - 2 - 2 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - BREAK - Break condition - 3 - 3 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - ENABLE - Enable UART + Enable SPI 0x500 read-write ENABLE - Enable or disable UART + Enable or disable SPI 0 3 Disabled - Disable UART + Disable SPI 0 Enabled - Enable UART - 4 + Enable SPI + 1 @@ -10372,11 +10815,11 @@ POSSIBILITY OF SUCH DAMAGE.\n PSEL Unspecified - UART_PSEL + SPI_PSEL 0x508 - RTS - Pin select for RTS + SCK + Pin select for SCK 0x000 read-write 0xFFFFFFFF @@ -10414,8 +10857,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TXD - Pin select for TXD + MOSI + Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF @@ -10453,8 +10896,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - CTS - Pin select for CTS + MISO + Pin select for MISO signal 0x008 read-write 0xFFFFFFFF @@ -10491,45 +10934,6 @@ POSSIBILITY OF SUCH DAMAGE.\n - - RXD - Pin select for RXD - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - RXD @@ -10540,7 +10944,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXD - RX data received in previous transfers, double buffered + RX data received. Double buffered 0 7 @@ -10550,162 +10954,125 @@ POSSIBILITY OF SUCH DAMAGE.\n TXD TXD register 0x51C - write-only + read-write TXD - TX data to be transferred + TX data to send. Double buffered 0 7 - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 - BAUDRATE - Baud rate + FREQUENCY + SPI master data rate 0 31 - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 + K125 + 125 kbps + 0x02000000 - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 - - - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 - - - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 - - - Baud14400 - 14400 baud (actual rate: 14414) - 0x003B0000 - - - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 - - - Baud28800 - 28800 baud (actual rate: 28829) - 0x0075F000 - - - Baud31250 - 31250 baud - 0x00800000 - - - Baud38400 - 38400 baud (actual rate: 38462) - 0x009D5000 - - - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 - - - Baud57600 - 57600 baud (actual rate: 57762) - 0x00EBF000 - - - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 - - - Baud115200 - 115200 baud (actual rate: 115942) - 0x01D7E000 - - - Baud230400 - 230400 baud (actual rate: 231884) - 0x03AFB000 - - - Baud250000 - 250000 baud + K250 + 250 kbps 0x04000000 - Baud460800 - 460800 baud (actual rate: 470588) - 0x075F7000 + K500 + 500 kbps + 0x08000000 - Baud921600 - 921600 baud (actual rate: 941176) - 0x0EBED000 - - - Baud1M - 1Mega baud + M1 + 1 Mbps 0x10000000 + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + CONFIG - Configuration of parity and hardware flow control - 0x56C + Configuration register + 0x554 read-write - HWFC - Hardware flow control + ORDER + Bit order 0 0 - Disabled - Disabled + MsbFirst + Most significant bit shifted out first 0 - Enabled - Enabled + LsbFirst + Least significant bit shifted out first 1 - PARITY - Parity + CPHA + Serial clock (SCK) phase 1 - 3 + 1 - Excluded - Exclude parity bit - 0x0 + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 - Included - Include parity bit - 0x7 + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 @@ -10716,9 +11083,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIM0 Serial Peripheral Interface Master with EasyDMA 0 - SPIM 0x40003000 - 32 + SPI0 SPIM 0 @@ -10729,6 +11095,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 + SPIM + 0x20 TASKS_START @@ -10881,7 +11249,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 1 1 @@ -10908,7 +11276,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Enable interrupt for ENDRX event + Write '1' to enable interrupt for ENDRX event 4 4 @@ -10935,7 +11303,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Enable interrupt for END event + Write '1' to enable interrupt for END event 6 6 @@ -10962,7 +11330,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDTX - Write '1' to Enable interrupt for ENDTX event + Write '1' to enable interrupt for ENDTX event 8 8 @@ -10989,7 +11357,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Enable interrupt for STARTED event + Write '1' to enable interrupt for STARTED event 19 19 @@ -11024,7 +11392,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 1 1 @@ -11051,7 +11419,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Disable interrupt for ENDRX event + Write '1' to disable interrupt for ENDRX event 4 4 @@ -11078,7 +11446,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Disable interrupt for END event + Write '1' to disable interrupt for END event 6 6 @@ -11105,7 +11473,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDTX - Write '1' to Disable interrupt for ENDTX event + Write '1' to disable interrupt for ENDTX event 8 8 @@ -11132,7 +11500,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Disable interrupt for STARTED event + Write '1' to disable interrupt for STARTED event 19 19 @@ -11674,7 +12042,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Sample delay for input serial data on MISO 0x000 read-write - 0x00000000 + 0x00000002 RXDELAY @@ -11689,7 +12057,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions 0x004 read-write - 0x00000000 + 0x00000002 CSNDUR @@ -11799,10 +12167,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIS0 SPI Slave 0 - SPIS 0x40003000 - 32 - SPIM0 + SPI0 SPIS 0 @@ -11813,6 +12179,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 + SPIS + 0x20 TASKS_ACQUIRE @@ -11913,7 +12281,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Enable interrupt for END event + Write '1' to enable interrupt for END event 1 1 @@ -11940,7 +12308,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Enable interrupt for ENDRX event + Write '1' to enable interrupt for ENDRX event 4 4 @@ -11967,7 +12335,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACQUIRED - Write '1' to Enable interrupt for ACQUIRED event + Write '1' to enable interrupt for ACQUIRED event 10 10 @@ -12002,7 +12370,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Disable interrupt for END event + Write '1' to disable interrupt for END event 1 1 @@ -12029,7 +12397,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Disable interrupt for ENDRX event + Write '1' to disable interrupt for ENDRX event 4 4 @@ -12056,7 +12424,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACQUIRED - Write '1' to Disable interrupt for ACQUIRED event + Write '1' to disable interrupt for ACQUIRED event 10 10 @@ -12558,13 +12926,809 @@ POSSIBILITY OF SUCH DAMAGE.\n + + TWI0 + I2C compatible Two-Wire Interface 0 + 0x40003000 + SPI0 + TWI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + 0 + 0 + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + 0 + 0 + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + 0 + 0 + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + 0 + 0 + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + 0 + 0 + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + 0 + 0 + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + 0 + 0 + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + 0 + 0 + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + 0 + 0 + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + 0 + 0 + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + 0 + 0 + + + + + SHORTS + Shortcut register + 0x200 + read-write + + + BB_SUSPEND + Shortcut between BB event and SUSPEND task + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between BB event and STOP task + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for RXDREADY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for TXDSENT event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for BB event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for SUSPENDED event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for STOPPED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for RXDREADY event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for TXDSENT event + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for ERROR event + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for BB event + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for SUSPENDED event + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSEL + Unspecified + TWI_PSEL + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + TWIM0 I2C compatible Two-Wire Master Interface with EasyDMA 0 - TWIM 0x40003000 - 32 - SPIM0 + SPI0 TWIM 0 @@ -12575,6 +13739,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 + TWIM + 0x20 TASKS_STARTRX @@ -12990,7 +14156,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 1 1 @@ -13017,7 +14183,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Enable interrupt for ERROR event + Write '1' to enable interrupt for ERROR event 9 9 @@ -13044,7 +14210,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SUSPENDED - Write '1' to Enable interrupt for SUSPENDED event + Write '1' to enable interrupt for SUSPENDED event 18 18 @@ -13071,7 +14237,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTARTED - Write '1' to Enable interrupt for RXSTARTED event + Write '1' to enable interrupt for RXSTARTED event 19 19 @@ -13098,7 +14264,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTARTED - Write '1' to Enable interrupt for TXSTARTED event + Write '1' to enable interrupt for TXSTARTED event 20 20 @@ -13125,7 +14291,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LASTRX - Write '1' to Enable interrupt for LASTRX event + Write '1' to enable interrupt for LASTRX event 23 23 @@ -13152,7 +14318,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LASTTX - Write '1' to Enable interrupt for LASTTX event + Write '1' to enable interrupt for LASTTX event 24 24 @@ -13187,7 +14353,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 1 1 @@ -13214,7 +14380,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Disable interrupt for ERROR event + Write '1' to disable interrupt for ERROR event 9 9 @@ -13241,7 +14407,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SUSPENDED - Write '1' to Disable interrupt for SUSPENDED event + Write '1' to disable interrupt for SUSPENDED event 18 18 @@ -13268,7 +14434,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTARTED - Write '1' to Disable interrupt for RXSTARTED event + Write '1' to disable interrupt for RXSTARTED event 19 19 @@ -13295,7 +14461,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTARTED - Write '1' to Disable interrupt for TXSTARTED event + Write '1' to disable interrupt for TXSTARTED event 20 20 @@ -13322,7 +14488,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LASTRX - Write '1' to Disable interrupt for LASTRX event + Write '1' to disable interrupt for LASTRX event 23 23 @@ -13349,7 +14515,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LASTTX - Write '1' to Disable interrupt for LASTTX event + Write '1' to disable interrupt for LASTTX event 24 24 @@ -13748,10 +14914,8 @@ POSSIBILITY OF SUCH DAMAGE.\n TWIS0 I2C compatible Two-Wire Slave Interface with EasyDMA 0 - TWIS 0x40003000 - 32 - SPIM0 + SPI0 TWIS 0 @@ -13762,6 +14926,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 + TWIS + 0x20 TASKS_STOP @@ -14074,7 +15240,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 1 1 @@ -14101,7 +15267,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Enable interrupt for ERROR event + Write '1' to enable interrupt for ERROR event 9 9 @@ -14128,7 +15294,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTARTED - Write '1' to Enable interrupt for RXSTARTED event + Write '1' to enable interrupt for RXSTARTED event 19 19 @@ -14155,7 +15321,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTARTED - Write '1' to Enable interrupt for TXSTARTED event + Write '1' to enable interrupt for TXSTARTED event 20 20 @@ -14182,7 +15348,7 @@ POSSIBILITY OF SUCH DAMAGE.\n WRITE - Write '1' to Enable interrupt for WRITE event + Write '1' to enable interrupt for WRITE event 25 25 @@ -14209,7 +15375,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READ - Write '1' to Enable interrupt for READ event + Write '1' to enable interrupt for READ event 26 26 @@ -14244,7 +15410,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 1 1 @@ -14271,7 +15437,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Disable interrupt for ERROR event + Write '1' to disable interrupt for ERROR event 9 9 @@ -14298,7 +15464,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXSTARTED - Write '1' to Disable interrupt for RXSTARTED event + Write '1' to disable interrupt for RXSTARTED event 19 19 @@ -14325,7 +15491,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXSTARTED - Write '1' to Disable interrupt for TXSTARTED event + Write '1' to disable interrupt for TXSTARTED event 20 20 @@ -14352,7 +15518,7 @@ POSSIBILITY OF SUCH DAMAGE.\n WRITE - Write '1' to Disable interrupt for WRITE event + Write '1' to disable interrupt for WRITE event 25 25 @@ -14379,7 +15545,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READ - Write '1' to Disable interrupt for READ event + Write '1' to disable interrupt for READ event 26 26 @@ -14690,10 +15856,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 - 4 + 0x2 + 0x4 ADDRESS[%s] - Description collection[0]: TWI slave address 0 + Description collection[n]: TWI slave address n 0x588 read-write @@ -14766,1205 +15932,20 @@ POSSIBILITY OF SUCH DAMAGE.\n - - SPI0 - Serial Peripheral Interface 0 - SPI - 0x40003000 - 32 - SPIM0 - SPI - - 0 - 0x1000 - registers - + + SPI1 + Serial Peripheral Interface 1 + 0x40004000 - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 - - - EVENTS_READY - TXD byte sent and RXD byte received - 0x108 - read-write - - - EVENTS_READY - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - READY - Write '1' to Enable interrupt for READY event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - READY - Write '1' to Disable interrupt for READY event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ENABLE - Enable SPI - 0x500 - read-write - - - ENABLE - Enable or disable SPI - 0 - 3 - - - Disabled - Disable SPI - 0 - - - Enabled - Enable SPI - 1 - - - - - - - PSEL - Unspecified - SPI_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RX data received. Double buffered - 0 - 7 - - - - - TXD - TXD register - 0x51C - read-write - - - TXD - TX data to send. Double buffered - 0 - 7 - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - SPI master data rate - 0 - 31 - - - K125 - 125 kbps - 0x02000000 - - - K250 - 250 kbps - 0x04000000 - - - K500 - 500 kbps - 0x08000000 - - - M1 - 1 Mbps - 0x10000000 - - - M2 - 2 Mbps - 0x20000000 - - - M4 - 4 Mbps - 0x40000000 - - - M8 - 8 Mbps - 0x80000000 - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - - ORDER - Bit order - 0 - 0 - - - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first - 1 - - - - - CPHA - Serial clock (SCK) phase - 1 - 1 - - - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge - 1 - - - - - CPOL - Serial clock (SCK) polarity - 2 - 2 - - - ActiveHigh - Active high - 0 - - - ActiveLow - Active low - 1 - - - - - - - - - TWI0 - I2C compatible Two-Wire Interface 0 - TWI - 0x40003000 - 32 - SPIM0 - TWI - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_RXDREADY - TWI RXD byte received - 0x108 - read-write - - - EVENTS_RXDREADY - 0 - 0 - - - - - EVENTS_TXDSENT - TWI TXD byte sent - 0x11C - read-write - - - EVENTS_TXDSENT - 0 - 0 - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_BB - TWI byte boundary, generated before each byte that is sent or received - 0x138 - read-write - - - EVENTS_BB - 0 - 0 - - - - - EVENTS_SUSPENDED - TWI entered the suspended state - 0x148 - read-write - - - EVENTS_SUSPENDED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - BB_SUSPEND - Shortcut between BB event and SUSPEND task - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - BB_STOP - Shortcut between BB event and STOP task - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to Enable interrupt for STOPPED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RXDREADY - Write '1' to Enable interrupt for RXDREADY event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TXDSENT - Write '1' to Enable interrupt for TXDSENT event - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - ERROR - Write '1' to Enable interrupt for ERROR event - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - BB - Write '1' to Enable interrupt for BB event - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SUSPENDED - Write '1' to Enable interrupt for SUSPENDED event - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to Disable interrupt for STOPPED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RXDREADY - Write '1' to Disable interrupt for RXDREADY event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - TXDSENT - Write '1' to Disable interrupt for TXDSENT event - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - ERROR - Write '1' to Disable interrupt for ERROR event - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - BB - Write '1' to Disable interrupt for BB event - 14 - 14 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SUSPENDED - Write '1' to Disable interrupt for SUSPENDED event - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear - - - OVERRUN - Overrun error - 0 - 0 - - read - - NotPresent - Read: no overrun occured - 0 - - - Present - Read: overrun occured - 1 - - - - - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 - 2 - - read - - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 - - - - - - - ENABLE - Enable TWI - 0x500 - read-write - - - ENABLE - Enable or disable TWI - 0 - 3 - - - Disabled - Disable TWI - 0 - - - Enabled - Enable TWI - 5 - - - - - - - PSEL - Unspecified - TWI_PSEL - 0x508 - - SCL - Pin select for SCL - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RXD register - 0 - 7 - - - - - TXD - TXD register - 0x51C - read-write - - - TXD - TXD register - 0 - 7 - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - - FREQUENCY - TWI master clock frequency - 0 - 31 - - - K100 - 100 kbps - 0x01980000 - - - K250 - 250 kbps - 0x04000000 - - - K400 - 400 kbps (actual rate 410.256 kbps) - 0x06680000 - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - SPIM1 Serial Peripheral Interface Master with EasyDMA 1 - SPIM 0x40004000 - 32 + SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 @@ -15973,46 +15954,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIS1 SPI Slave 1 - SPIS 0x40004000 - 32 - SPIM1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWIM1 - I2C compatible Two-Wire Master Interface with EasyDMA 1 - TWIM - 0x40004000 - 32 - SPIM1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWIS1 - I2C compatible Two-Wire Slave Interface with EasyDMA 1 - TWIS - 0x40004000 - 32 - SPIM1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - SPI1 - Serial Peripheral Interface 1 - SPI - 0x40004000 - 32 - SPIM1 + SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 @@ -16021,10 +15964,28 @@ POSSIBILITY OF SUCH DAMAGE.\n TWI1 I2C compatible Two-Wire Interface 1 - TWI 0x40004000 - 32 - SPIM1 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x40004000 + SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 @@ -16033,9 +15994,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NFCT NFC-A compatible radio - NFCT 0x40005000 - 32 0 0x1000 @@ -16045,6 +16004,8 @@ POSSIBILITY OF SUCH DAMAGE.\n NFCT 5 + NFCT + 0x20 TASKS_ACTIVATE @@ -16680,7 +16641,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Enable interrupt for READY event + Write '1' to enable interrupt for READY event 0 0 @@ -16707,7 +16668,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FIELDDETECTED - Write '1' to Enable interrupt for FIELDDETECTED event + Write '1' to enable interrupt for FIELDDETECTED event 1 1 @@ -16734,7 +16695,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FIELDLOST - Write '1' to Enable interrupt for FIELDLOST event + Write '1' to enable interrupt for FIELDLOST event 2 2 @@ -16761,7 +16722,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXFRAMESTART - Write '1' to Enable interrupt for TXFRAMESTART event + Write '1' to enable interrupt for TXFRAMESTART event 3 3 @@ -16788,7 +16749,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXFRAMEEND - Write '1' to Enable interrupt for TXFRAMEEND event + Write '1' to enable interrupt for TXFRAMEEND event 4 4 @@ -16815,7 +16776,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXFRAMESTART - Write '1' to Enable interrupt for RXFRAMESTART event + Write '1' to enable interrupt for RXFRAMESTART event 5 5 @@ -16842,7 +16803,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXFRAMEEND - Write '1' to Enable interrupt for RXFRAMEEND event + Write '1' to enable interrupt for RXFRAMEEND event 6 6 @@ -16869,7 +16830,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Enable interrupt for ERROR event + Write '1' to enable interrupt for ERROR event 7 7 @@ -16896,7 +16857,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXERROR - Write '1' to Enable interrupt for RXERROR event + Write '1' to enable interrupt for RXERROR event 10 10 @@ -16923,7 +16884,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Enable interrupt for ENDRX event + Write '1' to enable interrupt for ENDRX event 11 11 @@ -16950,7 +16911,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDTX - Write '1' to Enable interrupt for ENDTX event + Write '1' to enable interrupt for ENDTX event 12 12 @@ -16977,7 +16938,7 @@ POSSIBILITY OF SUCH DAMAGE.\n AUTOCOLRESSTARTED - Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + Write '1' to enable interrupt for AUTOCOLRESSTARTED event 14 14 @@ -17004,7 +16965,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COLLISION - Write '1' to Enable interrupt for COLLISION event + Write '1' to enable interrupt for COLLISION event 18 18 @@ -17031,7 +16992,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SELECTED - Write '1' to Enable interrupt for SELECTED event + Write '1' to enable interrupt for SELECTED event 19 19 @@ -17058,7 +17019,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Enable interrupt for STARTED event + Write '1' to enable interrupt for STARTED event 20 20 @@ -17093,7 +17054,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Disable interrupt for READY event + Write '1' to disable interrupt for READY event 0 0 @@ -17120,7 +17081,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FIELDDETECTED - Write '1' to Disable interrupt for FIELDDETECTED event + Write '1' to disable interrupt for FIELDDETECTED event 1 1 @@ -17147,7 +17108,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FIELDLOST - Write '1' to Disable interrupt for FIELDLOST event + Write '1' to disable interrupt for FIELDLOST event 2 2 @@ -17174,7 +17135,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXFRAMESTART - Write '1' to Disable interrupt for TXFRAMESTART event + Write '1' to disable interrupt for TXFRAMESTART event 3 3 @@ -17201,7 +17162,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXFRAMEEND - Write '1' to Disable interrupt for TXFRAMEEND event + Write '1' to disable interrupt for TXFRAMEEND event 4 4 @@ -17228,7 +17189,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXFRAMESTART - Write '1' to Disable interrupt for RXFRAMESTART event + Write '1' to disable interrupt for RXFRAMESTART event 5 5 @@ -17255,7 +17216,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXFRAMEEND - Write '1' to Disable interrupt for RXFRAMEEND event + Write '1' to disable interrupt for RXFRAMEEND event 6 6 @@ -17282,7 +17243,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Disable interrupt for ERROR event + Write '1' to disable interrupt for ERROR event 7 7 @@ -17309,7 +17270,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXERROR - Write '1' to Disable interrupt for RXERROR event + Write '1' to disable interrupt for RXERROR event 10 10 @@ -17336,7 +17297,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDRX - Write '1' to Disable interrupt for ENDRX event + Write '1' to disable interrupt for ENDRX event 11 11 @@ -17363,7 +17324,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDTX - Write '1' to Disable interrupt for ENDTX event + Write '1' to disable interrupt for ENDTX event 12 12 @@ -17390,7 +17351,7 @@ POSSIBILITY OF SUCH DAMAGE.\n AUTOCOLRESSTARTED - Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + Write '1' to disable interrupt for AUTOCOLRESSTARTED event 14 14 @@ -17417,7 +17378,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COLLISION - Write '1' to Disable interrupt for COLLISION event + Write '1' to disable interrupt for COLLISION event 18 18 @@ -17444,7 +17405,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SELECTED - Write '1' to Disable interrupt for SELECTED event + Write '1' to disable interrupt for SELECTED event 19 19 @@ -17471,7 +17432,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Disable interrupt for STARTED event + Write '1' to disable interrupt for STARTED event 20 20 @@ -17637,7 +17598,9 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPSTATE - Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. 0 0 @@ -17771,6 +17734,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Packet pointer for TXD and RXD data storage in Data RAM 0x510 read-write + 0x00000000 PTR @@ -18233,9 +18197,7 @@ POSSIBILITY OF SUCH DAMAGE.\n GPIOTE GPIO Tasks and Events - GPIOTE 0x40006000 - 32 0 0x1000 @@ -18245,12 +18207,14 @@ POSSIBILITY OF SUCH DAMAGE.\n GPIOTE 6 + GPIOTE + 0x20 - 8 - 4 + 0x8 + 0x4 TASKS_OUT[%s] - Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only @@ -18262,10 +18226,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 TASKS_SET[%s] - Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. + Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0x030 write-only @@ -18277,10 +18241,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 TASKS_CLR[%s] - Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. + Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0x060 write-only @@ -18292,10 +18256,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 EVENTS_IN[%s] - Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL + Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL 0x100 read-write @@ -18327,7 +18291,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN0 - Write '1' to Enable interrupt for IN[0] event + Write '1' to enable interrupt for IN[0] event 0 0 @@ -18354,7 +18318,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN1 - Write '1' to Enable interrupt for IN[1] event + Write '1' to enable interrupt for IN[1] event 1 1 @@ -18381,7 +18345,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN2 - Write '1' to Enable interrupt for IN[2] event + Write '1' to enable interrupt for IN[2] event 2 2 @@ -18408,7 +18372,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN3 - Write '1' to Enable interrupt for IN[3] event + Write '1' to enable interrupt for IN[3] event 3 3 @@ -18435,7 +18399,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN4 - Write '1' to Enable interrupt for IN[4] event + Write '1' to enable interrupt for IN[4] event 4 4 @@ -18462,7 +18426,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN5 - Write '1' to Enable interrupt for IN[5] event + Write '1' to enable interrupt for IN[5] event 5 5 @@ -18489,7 +18453,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN6 - Write '1' to Enable interrupt for IN[6] event + Write '1' to enable interrupt for IN[6] event 6 6 @@ -18516,7 +18480,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN7 - Write '1' to Enable interrupt for IN[7] event + Write '1' to enable interrupt for IN[7] event 7 7 @@ -18543,7 +18507,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PORT - Write '1' to Enable interrupt for PORT event + Write '1' to enable interrupt for PORT event 31 31 @@ -18578,7 +18542,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN0 - Write '1' to Disable interrupt for IN[0] event + Write '1' to disable interrupt for IN[0] event 0 0 @@ -18605,7 +18569,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN1 - Write '1' to Disable interrupt for IN[1] event + Write '1' to disable interrupt for IN[1] event 1 1 @@ -18632,7 +18596,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN2 - Write '1' to Disable interrupt for IN[2] event + Write '1' to disable interrupt for IN[2] event 2 2 @@ -18659,7 +18623,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN3 - Write '1' to Disable interrupt for IN[3] event + Write '1' to disable interrupt for IN[3] event 3 3 @@ -18686,7 +18650,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN4 - Write '1' to Disable interrupt for IN[4] event + Write '1' to disable interrupt for IN[4] event 4 4 @@ -18713,7 +18677,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN5 - Write '1' to Disable interrupt for IN[5] event + Write '1' to disable interrupt for IN[5] event 5 5 @@ -18740,7 +18704,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN6 - Write '1' to Disable interrupt for IN[6] event + Write '1' to disable interrupt for IN[6] event 6 6 @@ -18767,7 +18731,7 @@ POSSIBILITY OF SUCH DAMAGE.\n IN7 - Write '1' to Disable interrupt for IN[7] event + Write '1' to disable interrupt for IN[7] event 7 7 @@ -18794,7 +18758,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PORT - Write '1' to Disable interrupt for PORT event + Write '1' to disable interrupt for PORT event 31 31 @@ -18822,10 +18786,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 CONFIG[%s] - Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event 0x510 read-write @@ -18916,10 +18880,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SAADC - Analog to Digital Converter - SAADC + Successive approximation register (SAR) analog-to-digital converter 0x40007000 - 32 0 0x1000 @@ -18929,10 +18891,12 @@ POSSIBILITY OF SUCH DAMAGE.\n SAADC 7 + SAADC + 0x20 TASKS_START - Start the ADC and prepare the result buffer in RAM + Starts the SAADC and prepares the result buffer in RAM 0x000 write-only @@ -18945,7 +18909,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Takes one SAADC sample 0x004 write-only @@ -18958,7 +18922,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_STOP - Stop the ADC and terminate any on-going conversion + Stops the SAADC and terminates all on-going conversions 0x008 write-only @@ -18984,7 +18948,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_STARTED - The ADC has started + The SAADC has started 0x100 read-write @@ -18997,7 +18961,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_END - The ADC has filled up the Result buffer + The SAADC has filled up the result buffer 0x104 read-write @@ -19010,7 +18974,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_DONE - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write @@ -19023,7 +18987,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_RESULTDONE - A result is ready to get transferred to RAM. + Result ready for transfer to RAM 0x10C read-write @@ -19049,7 +19013,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_STOPPED - The ADC has stopped + The SAADC has stopped 0x114 read-write @@ -19062,14 +19026,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 8 - 8 + 0x008 EVENTS_CH[%s] Unspecified SAADC_EVENTS_CH 0x118 LIMITH - Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH + Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH 0x000 read-write @@ -19082,7 +19046,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LIMITL - Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW + Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW 0x004 read-write @@ -19506,7 +19470,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Enable interrupt for STARTED event + Write '1' to enable interrupt for STARTED event 0 0 @@ -19533,7 +19497,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Enable interrupt for END event + Write '1' to enable interrupt for END event 1 1 @@ -19560,7 +19524,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DONE - Write '1' to Enable interrupt for DONE event + Write '1' to enable interrupt for DONE event 2 2 @@ -19587,7 +19551,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RESULTDONE - Write '1' to Enable interrupt for RESULTDONE event + Write '1' to enable interrupt for RESULTDONE event 3 3 @@ -19614,7 +19578,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CALIBRATEDONE - Write '1' to Enable interrupt for CALIBRATEDONE event + Write '1' to enable interrupt for CALIBRATEDONE event 4 4 @@ -19641,7 +19605,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 5 5 @@ -19668,7 +19632,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0LIMITH - Write '1' to Enable interrupt for CH[0].LIMITH event + Write '1' to enable interrupt for CH[0].LIMITH event 6 6 @@ -19695,7 +19659,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0LIMITL - Write '1' to Enable interrupt for CH[0].LIMITL event + Write '1' to enable interrupt for CH[0].LIMITL event 7 7 @@ -19722,7 +19686,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1LIMITH - Write '1' to Enable interrupt for CH[1].LIMITH event + Write '1' to enable interrupt for CH[1].LIMITH event 8 8 @@ -19749,7 +19713,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1LIMITL - Write '1' to Enable interrupt for CH[1].LIMITL event + Write '1' to enable interrupt for CH[1].LIMITL event 9 9 @@ -19776,7 +19740,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2LIMITH - Write '1' to Enable interrupt for CH[2].LIMITH event + Write '1' to enable interrupt for CH[2].LIMITH event 10 10 @@ -19803,7 +19767,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2LIMITL - Write '1' to Enable interrupt for CH[2].LIMITL event + Write '1' to enable interrupt for CH[2].LIMITL event 11 11 @@ -19830,7 +19794,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3LIMITH - Write '1' to Enable interrupt for CH[3].LIMITH event + Write '1' to enable interrupt for CH[3].LIMITH event 12 12 @@ -19857,7 +19821,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3LIMITL - Write '1' to Enable interrupt for CH[3].LIMITL event + Write '1' to enable interrupt for CH[3].LIMITL event 13 13 @@ -19884,7 +19848,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4LIMITH - Write '1' to Enable interrupt for CH[4].LIMITH event + Write '1' to enable interrupt for CH[4].LIMITH event 14 14 @@ -19911,7 +19875,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4LIMITL - Write '1' to Enable interrupt for CH[4].LIMITL event + Write '1' to enable interrupt for CH[4].LIMITL event 15 15 @@ -19938,7 +19902,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5LIMITH - Write '1' to Enable interrupt for CH[5].LIMITH event + Write '1' to enable interrupt for CH[5].LIMITH event 16 16 @@ -19965,7 +19929,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5LIMITL - Write '1' to Enable interrupt for CH[5].LIMITL event + Write '1' to enable interrupt for CH[5].LIMITL event 17 17 @@ -19992,7 +19956,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6LIMITH - Write '1' to Enable interrupt for CH[6].LIMITH event + Write '1' to enable interrupt for CH[6].LIMITH event 18 18 @@ -20019,7 +19983,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6LIMITL - Write '1' to Enable interrupt for CH[6].LIMITL event + Write '1' to enable interrupt for CH[6].LIMITL event 19 19 @@ -20046,7 +20010,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7LIMITH - Write '1' to Enable interrupt for CH[7].LIMITH event + Write '1' to enable interrupt for CH[7].LIMITH event 20 20 @@ -20073,7 +20037,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7LIMITL - Write '1' to Enable interrupt for CH[7].LIMITL event + Write '1' to enable interrupt for CH[7].LIMITL event 21 21 @@ -20108,7 +20072,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Disable interrupt for STARTED event + Write '1' to disable interrupt for STARTED event 0 0 @@ -20135,7 +20099,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Disable interrupt for END event + Write '1' to disable interrupt for END event 1 1 @@ -20162,7 +20126,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DONE - Write '1' to Disable interrupt for DONE event + Write '1' to disable interrupt for DONE event 2 2 @@ -20189,7 +20153,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RESULTDONE - Write '1' to Disable interrupt for RESULTDONE event + Write '1' to disable interrupt for RESULTDONE event 3 3 @@ -20216,7 +20180,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CALIBRATEDONE - Write '1' to Disable interrupt for CALIBRATEDONE event + Write '1' to disable interrupt for CALIBRATEDONE event 4 4 @@ -20243,7 +20207,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 5 5 @@ -20270,7 +20234,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0LIMITH - Write '1' to Disable interrupt for CH[0].LIMITH event + Write '1' to disable interrupt for CH[0].LIMITH event 6 6 @@ -20297,7 +20261,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0LIMITL - Write '1' to Disable interrupt for CH[0].LIMITL event + Write '1' to disable interrupt for CH[0].LIMITL event 7 7 @@ -20324,7 +20288,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1LIMITH - Write '1' to Disable interrupt for CH[1].LIMITH event + Write '1' to disable interrupt for CH[1].LIMITH event 8 8 @@ -20351,7 +20315,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1LIMITL - Write '1' to Disable interrupt for CH[1].LIMITL event + Write '1' to disable interrupt for CH[1].LIMITL event 9 9 @@ -20378,7 +20342,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2LIMITH - Write '1' to Disable interrupt for CH[2].LIMITH event + Write '1' to disable interrupt for CH[2].LIMITH event 10 10 @@ -20405,7 +20369,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2LIMITL - Write '1' to Disable interrupt for CH[2].LIMITL event + Write '1' to disable interrupt for CH[2].LIMITL event 11 11 @@ -20432,7 +20396,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3LIMITH - Write '1' to Disable interrupt for CH[3].LIMITH event + Write '1' to disable interrupt for CH[3].LIMITH event 12 12 @@ -20459,7 +20423,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3LIMITL - Write '1' to Disable interrupt for CH[3].LIMITL event + Write '1' to disable interrupt for CH[3].LIMITL event 13 13 @@ -20486,7 +20450,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4LIMITH - Write '1' to Disable interrupt for CH[4].LIMITH event + Write '1' to disable interrupt for CH[4].LIMITH event 14 14 @@ -20513,7 +20477,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4LIMITL - Write '1' to Disable interrupt for CH[4].LIMITL event + Write '1' to disable interrupt for CH[4].LIMITL event 15 15 @@ -20540,7 +20504,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5LIMITH - Write '1' to Disable interrupt for CH[5].LIMITH event + Write '1' to disable interrupt for CH[5].LIMITH event 16 16 @@ -20567,7 +20531,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5LIMITL - Write '1' to Disable interrupt for CH[5].LIMITL event + Write '1' to disable interrupt for CH[5].LIMITL event 17 17 @@ -20594,7 +20558,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6LIMITH - Write '1' to Disable interrupt for CH[6].LIMITH event + Write '1' to disable interrupt for CH[6].LIMITH event 18 18 @@ -20621,7 +20585,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6LIMITL - Write '1' to Disable interrupt for CH[6].LIMITL event + Write '1' to disable interrupt for CH[6].LIMITL event 19 19 @@ -20648,7 +20612,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7LIMITH - Write '1' to Disable interrupt for CH[7].LIMITH event + Write '1' to disable interrupt for CH[7].LIMITH event 20 20 @@ -20675,7 +20639,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7LIMITL - Write '1' to Disable interrupt for CH[7].LIMITL event + Write '1' to disable interrupt for CH[7].LIMITL event 21 21 @@ -20716,12 +20680,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Ready - ADC is ready. No on-going conversion. + SAADC is ready. No on-going conversions. 0 Busy - ADC is busy. Conversion in progress. + SAADC is busy. Conversion in progress. 1 @@ -20730,24 +20694,24 @@ POSSIBILITY OF SUCH DAMAGE.\n ENABLE - Enable or disable ADC + Enable or disable SAADC 0x500 read-write ENABLE - Enable or disable ADC + Enable or disable SAADC 0 0 Disabled - Disable ADC + Disable SAADC 0 Enabled - Enable ADC + Enable SAADC 1 @@ -20756,14 +20720,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 8 - 16 + 0x010 CH[%s] Unspecified SAADC_CH 0x510 PSELP - Description cluster[0]: Input positive pin selection for CH[0] + Description cluster[n]: Input positive pin selection for CH[n] 0x000 read-write 0x00000000 @@ -20835,7 +20799,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PSELN - Description cluster[0]: Input negative pin selection for CH[0] + Description cluster[n]: Input negative pin selection for CH[n] 0x004 read-write 0x00000000 @@ -20907,7 +20871,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CONFIG - Description cluster[0]: Input configuration for CH[0] + Description cluster[n]: Input configuration for CH[n] 0x008 read-write 0x00020000 @@ -21036,7 +21000,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TACQ - Acquisition time, the time the ADC uses to sample the input voltage + Acquisition time, the time the SAADC uses to sample the input voltage 16 18 @@ -21080,7 +21044,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SE - Single ended, PSELN will be ignored, negative input to ADC shorted to GND + Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND 0 @@ -21112,7 +21076,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LIMIT - Description cluster[0]: High/low limits for event monitoring a channel + Description cluster[n]: High/low limits for event monitoring of a channel 0x00C read-write 0x7FFF8000 @@ -21147,22 +21111,22 @@ POSSIBILITY OF SUCH DAMAGE.\n 8bit - 8 bit + 8 bits 0 10bit - 10 bit + 10 bits 1 12bit - 12 bit + 12 bits 2 14bit - 14 bit + 14 bits 3 @@ -21171,7 +21135,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OVERSAMPLE - Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 0x5F4 read-write @@ -21283,13 +21247,13 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXCNT - Maximum number of buffer words to transfer + Maximum number of 16-bit samples to be written to output RAM buffer 0x004 read-write MAXCNT - Maximum number of buffer words to transfer + Maximum number of 16-bit samples to be written to output RAM buffer 0 14 @@ -21297,13 +21261,13 @@ POSSIBILITY OF SUCH DAMAGE.\n AMOUNT - Number of buffer words transferred since last START + Number of 16-bit samples written to output RAM buffer since the previous START task 0x008 read-only AMOUNT - Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. 0 14 @@ -21315,9 +21279,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMER0 Timer/Counter 0 - TIMER 0x40008000 - 32 TIMER 0 @@ -21328,6 +21290,8 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMER0 8 + TIMER + 0x20 TASKS_START @@ -21383,7 +21347,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_SHUTDOWN - Deprecated register - Shut down timer + Deprecated register - Shut down timer 0x010 write-only @@ -21395,10 +21359,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 6 - 4 + 0x6 + 0x4 TASKS_CAPTURE[%s] - Description collection[0]: Capture Timer value to CC[0] register + Description collection[n]: Capture Timer value to CC[n] register 0x040 write-only @@ -21410,10 +21374,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 6 - 4 + 0x6 + 0x4 EVENTS_COMPARE[%s] - Description collection[0]: Compare event on CC[0] match + Description collection[n]: Compare event on CC[n] match 0x140 read-write @@ -21656,7 +21620,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE0 - Write '1' to Enable interrupt for COMPARE[0] event + Write '1' to enable interrupt for COMPARE[0] event 16 16 @@ -21683,7 +21647,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE1 - Write '1' to Enable interrupt for COMPARE[1] event + Write '1' to enable interrupt for COMPARE[1] event 17 17 @@ -21710,7 +21674,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE2 - Write '1' to Enable interrupt for COMPARE[2] event + Write '1' to enable interrupt for COMPARE[2] event 18 18 @@ -21737,7 +21701,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE3 - Write '1' to Enable interrupt for COMPARE[3] event + Write '1' to enable interrupt for COMPARE[3] event 19 19 @@ -21764,7 +21728,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE4 - Write '1' to Enable interrupt for COMPARE[4] event + Write '1' to enable interrupt for COMPARE[4] event 20 20 @@ -21791,7 +21755,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE5 - Write '1' to Enable interrupt for COMPARE[5] event + Write '1' to enable interrupt for COMPARE[5] event 21 21 @@ -21826,7 +21790,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE0 - Write '1' to Disable interrupt for COMPARE[0] event + Write '1' to disable interrupt for COMPARE[0] event 16 16 @@ -21853,7 +21817,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE1 - Write '1' to Disable interrupt for COMPARE[1] event + Write '1' to disable interrupt for COMPARE[1] event 17 17 @@ -21880,7 +21844,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE2 - Write '1' to Disable interrupt for COMPARE[2] event + Write '1' to disable interrupt for COMPARE[2] event 18 18 @@ -21907,7 +21871,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE3 - Write '1' to Disable interrupt for COMPARE[3] event + Write '1' to disable interrupt for COMPARE[3] event 19 19 @@ -21934,7 +21898,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE4 - Write '1' to Disable interrupt for COMPARE[4] event + Write '1' to disable interrupt for COMPARE[4] event 20 20 @@ -21961,7 +21925,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE5 - Write '1' to Disable interrupt for COMPARE[5] event + Write '1' to disable interrupt for COMPARE[5] event 21 21 @@ -22071,10 +22035,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 6 - 4 + 0x6 + 0x4 CC[%s] - Description collection[0]: Capture/Compare register 0 + Description collection[n]: Capture/Compare register n 0x540 read-write @@ -22091,9 +22055,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMER1 Timer/Counter 1 - TIMER 0x40009000 - 32 TIMER1 9 @@ -22102,9 +22064,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMER2 Timer/Counter 2 - TIMER 0x4000A000 - 32 TIMER2 10 @@ -22113,9 +22073,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RTC0 Real time counter 0 - RTC 0x4000B000 - 32 RTC 0 @@ -22126,6 +22084,8 @@ POSSIBILITY OF SUCH DAMAGE.\n RTC0 11 + RTC + 0x20 TASKS_START @@ -22206,10 +22166,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 - 4 + 0x4 + 0x4 EVENTS_COMPARE[%s] - Description collection[0]: Compare event on CC[0] match + Description collection[n]: Compare event on CC[n] match 0x140 read-write @@ -22228,7 +22188,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TICK - Write '1' to Enable interrupt for TICK event + Write '1' to enable interrupt for TICK event 0 0 @@ -22255,7 +22215,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OVRFLW - Write '1' to Enable interrupt for OVRFLW event + Write '1' to enable interrupt for OVRFLW event 1 1 @@ -22282,7 +22242,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE0 - Write '1' to Enable interrupt for COMPARE[0] event + Write '1' to enable interrupt for COMPARE[0] event 16 16 @@ -22309,7 +22269,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE1 - Write '1' to Enable interrupt for COMPARE[1] event + Write '1' to enable interrupt for COMPARE[1] event 17 17 @@ -22336,7 +22296,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE2 - Write '1' to Enable interrupt for COMPARE[2] event + Write '1' to enable interrupt for COMPARE[2] event 18 18 @@ -22363,7 +22323,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE3 - Write '1' to Enable interrupt for COMPARE[3] event + Write '1' to enable interrupt for COMPARE[3] event 19 19 @@ -22398,7 +22358,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TICK - Write '1' to Disable interrupt for TICK event + Write '1' to disable interrupt for TICK event 0 0 @@ -22425,7 +22385,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OVRFLW - Write '1' to Disable interrupt for OVRFLW event + Write '1' to disable interrupt for OVRFLW event 1 1 @@ -22452,7 +22412,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE0 - Write '1' to Disable interrupt for COMPARE[0] event + Write '1' to disable interrupt for COMPARE[0] event 16 16 @@ -22479,7 +22439,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE1 - Write '1' to Disable interrupt for COMPARE[1] event + Write '1' to disable interrupt for COMPARE[1] event 17 17 @@ -22506,7 +22466,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE2 - Write '1' to Disable interrupt for COMPARE[2] event + Write '1' to disable interrupt for COMPARE[2] event 18 18 @@ -22533,7 +22493,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE3 - Write '1' to Disable interrupt for COMPARE[3] event + Write '1' to disable interrupt for COMPARE[3] event 19 19 @@ -22684,7 +22644,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TICK - Write '1' to Enable event routing for TICK event + Write '1' to enable event routing for TICK event 0 0 @@ -22711,7 +22671,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OVRFLW - Write '1' to Enable event routing for OVRFLW event + Write '1' to enable event routing for OVRFLW event 1 1 @@ -22738,7 +22698,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE0 - Write '1' to Enable event routing for COMPARE[0] event + Write '1' to enable event routing for COMPARE[0] event 16 16 @@ -22765,7 +22725,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE1 - Write '1' to Enable event routing for COMPARE[1] event + Write '1' to enable event routing for COMPARE[1] event 17 17 @@ -22792,7 +22752,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE2 - Write '1' to Enable event routing for COMPARE[2] event + Write '1' to enable event routing for COMPARE[2] event 18 18 @@ -22819,7 +22779,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE3 - Write '1' to Enable event routing for COMPARE[3] event + Write '1' to enable event routing for COMPARE[3] event 19 19 @@ -22854,7 +22814,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TICK - Write '1' to Disable event routing for TICK event + Write '1' to disable event routing for TICK event 0 0 @@ -22881,7 +22841,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OVRFLW - Write '1' to Disable event routing for OVRFLW event + Write '1' to disable event routing for OVRFLW event 1 1 @@ -22908,7 +22868,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE0 - Write '1' to Disable event routing for COMPARE[0] event + Write '1' to disable event routing for COMPARE[0] event 16 16 @@ -22935,7 +22895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE1 - Write '1' to Disable event routing for COMPARE[1] event + Write '1' to disable event routing for COMPARE[1] event 17 17 @@ -22962,7 +22922,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE2 - Write '1' to Disable event routing for COMPARE[2] event + Write '1' to disable event routing for COMPARE[2] event 18 18 @@ -22989,7 +22949,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMPARE3 - Write '1' to Disable event routing for COMPARE[3] event + Write '1' to disable event routing for COMPARE[3] event 19 19 @@ -23045,10 +23005,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 4 - 4 + 0x4 + 0x4 CC[%s] - Description collection[0]: Compare register 0 + Description collection[n]: Compare register n 0x540 read-write @@ -23065,9 +23025,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEMP Temperature Sensor - TEMP 0x4000C000 - 32 0 0x1000 @@ -23077,6 +23035,8 @@ POSSIBILITY OF SUCH DAMAGE.\n TEMP 12 + TEMP + 0x20 TASKS_START @@ -23125,7 +23085,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DATARDY - Write '1' to Enable interrupt for DATARDY event + Write '1' to enable interrupt for DATARDY event 0 0 @@ -23160,7 +23120,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DATARDY - Write '1' to Disable interrupt for DATARDY event + Write '1' to disable interrupt for DATARDY event 0 0 @@ -23462,9 +23422,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RNG Random Number Generator - RNG 0x4000D000 - 32 0 0x1000 @@ -23474,6 +23432,8 @@ POSSIBILITY OF SUCH DAMAGE.\n RNG 13 + RNG + 0x20 TASKS_START @@ -23548,7 +23508,7 @@ POSSIBILITY OF SUCH DAMAGE.\n VALRDY - Write '1' to Enable interrupt for VALRDY event + Write '1' to enable interrupt for VALRDY event 0 0 @@ -23583,7 +23543,7 @@ POSSIBILITY OF SUCH DAMAGE.\n VALRDY - Write '1' to Disable interrupt for VALRDY event + Write '1' to disable interrupt for VALRDY event 0 0 @@ -23655,9 +23615,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ECB AES ECB Mode Encryption - ECB 0x4000E000 - 32 0 0x1000 @@ -23667,6 +23625,8 @@ POSSIBILITY OF SUCH DAMAGE.\n ECB 14 + ECB + 0x20 TASKS_STARTECB @@ -23728,7 +23688,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDECB - Write '1' to Enable interrupt for ENDECB event + Write '1' to enable interrupt for ENDECB event 0 0 @@ -23755,7 +23715,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORECB - Write '1' to Enable interrupt for ERRORECB event + Write '1' to enable interrupt for ERRORECB event 1 1 @@ -23790,7 +23750,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDECB - Write '1' to Disable interrupt for ENDECB event + Write '1' to disable interrupt for ENDECB event 0 0 @@ -23817,7 +23777,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORECB - Write '1' to Disable interrupt for ERRORECB event + Write '1' to disable interrupt for ERRORECB event 1 1 @@ -23861,11 +23821,9 @@ POSSIBILITY OF SUCH DAMAGE.\n - CCM - AES CCM Mode Encryption - CCM + AAR + Accelerated Address Resolver 0x4000F000 - 32 0 0x1000 @@ -23875,6 +23833,367 @@ POSSIBILITY OF SUCH DAMAGE.\n CCM_AAR 15 + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + 0 + 0 + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + 0 + 0 + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + 0 + 0 + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + 0 + 0 + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + 0 + 0 + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for END event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for RESOLVED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for NOTRESOLVED event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for END event + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for RESOLVED event + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for NOTRESOLVED event + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity root keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 TASKS_KSGEN @@ -23956,7 +24275,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ERROR - Deprecated register - CCM error event + Deprecated register - CCM error event 0x108 read-write @@ -24001,7 +24320,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDKSGEN - Write '1' to Enable interrupt for ENDKSGEN event + Write '1' to enable interrupt for ENDKSGEN event 0 0 @@ -24028,7 +24347,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDCRYPT - Write '1' to Enable interrupt for ENDCRYPT event + Write '1' to enable interrupt for ENDCRYPT event 1 1 @@ -24055,7 +24374,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Enable interrupt for ERROR event + Write '1' to enable interrupt for ERROR event 2 2 @@ -24090,7 +24409,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDKSGEN - Write '1' to Disable interrupt for ENDKSGEN event + Write '1' to disable interrupt for ENDKSGEN event 0 0 @@ -24117,7 +24436,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDCRYPT - Write '1' to Disable interrupt for ENDCRYPT event + Write '1' to disable interrupt for ENDCRYPT event 1 1 @@ -24144,7 +24463,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERROR - Write '1' to Disable interrupt for ERROR event + Write '1' to disable interrupt for ERROR event 2 2 @@ -24346,7 +24665,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. + Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. 0 31 @@ -24406,371 +24726,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - - AAR - Accelerated Address Resolver - AAR - 0x4000F000 - 32 - CCM - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - - - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop resolving addresses - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - EVENTS_END - Address resolution procedure complete - 0x100 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_RESOLVED - Address resolved - 0x104 - read-write - - - EVENTS_RESOLVED - 0 - 0 - - - - - EVENTS_NOTRESOLVED - Address not resolved - 0x108 - read-write - - - EVENTS_NOTRESOLVED - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - END - Write '1' to Enable interrupt for END event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - RESOLVED - Write '1' to Enable interrupt for RESOLVED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - NOTRESOLVED - Write '1' to Enable interrupt for NOTRESOLVED event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - END - Write '1' to Disable interrupt for END event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - RESOLVED - Write '1' to Disable interrupt for RESOLVED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - NOTRESOLVED - Write '1' to Disable interrupt for NOTRESOLVED event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - - - STATUS - Resolution status - 0x400 - read-only - - - STATUS - The IRK that was used last time an address was resolved - 0 - 3 - - - - - ENABLE - Enable AAR - 0x500 - read-write - - - ENABLE - Enable or disable AAR - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 3 - - - - - - - NIRK - Number of IRKs - 0x504 - read-write - 0x00000001 - - - NIRK - Number of Identity root keys available in the IRK data structure - 0 - 4 - - - - - IRKPTR - Pointer to IRK data structure - 0x508 - read-write - - - IRKPTR - Pointer to the IRK data structure - 0 - 31 - - - - - ADDRPTR - Pointer to the resolvable address - 0x510 - read-write - - - ADDRPTR - Pointer to the resolvable address (6-bytes) - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. - 0 - 31 - - - - - WDT Watchdog Timer - WDT 0x40010000 - 32 0 0x1000 @@ -24780,6 +24739,8 @@ POSSIBILITY OF SUCH DAMAGE.\n WDT 16 + WDT + 0x20 TASKS_START @@ -24815,7 +24776,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMEOUT - Write '1' to Enable interrupt for TIMEOUT event + Write '1' to enable interrupt for TIMEOUT event 0 0 @@ -24850,7 +24811,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMEOUT - Write '1' to Disable interrupt for TIMEOUT event + Write '1' to disable interrupt for TIMEOUT event 0 0 @@ -25270,10 +25231,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 RR[%s] - Description collection[0]: Reload request 0 + Description collection[n]: Reload request n 0x600 write-only @@ -25297,9 +25258,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RTC1 Real time counter 1 - RTC 0x40011000 - 32 RTC1 17 @@ -25308,9 +25267,7 @@ POSSIBILITY OF SUCH DAMAGE.\n QDEC Quadrature Decoder - QDEC 0x40012000 - 32 0 0x1000 @@ -25320,6 +25277,8 @@ POSSIBILITY OF SUCH DAMAGE.\n QDEC 18 + QDEC + 0x20 TASKS_START @@ -25593,7 +25552,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SAMPLERDY - Write '1' to Enable interrupt for SAMPLERDY event + Write '1' to enable interrupt for SAMPLERDY event 0 0 @@ -25620,7 +25579,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REPORTRDY - Write '1' to Enable interrupt for REPORTRDY event + Write '1' to enable interrupt for REPORTRDY event 1 1 @@ -25647,7 +25606,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACCOF - Write '1' to Enable interrupt for ACCOF event + Write '1' to enable interrupt for ACCOF event 2 2 @@ -25674,7 +25633,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DBLRDY - Write '1' to Enable interrupt for DBLRDY event + Write '1' to enable interrupt for DBLRDY event 3 3 @@ -25701,7 +25660,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 4 4 @@ -25736,7 +25695,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SAMPLERDY - Write '1' to Disable interrupt for SAMPLERDY event + Write '1' to disable interrupt for SAMPLERDY event 0 0 @@ -25763,7 +25722,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REPORTRDY - Write '1' to Disable interrupt for REPORTRDY event + Write '1' to disable interrupt for REPORTRDY event 1 1 @@ -25790,7 +25749,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACCOF - Write '1' to Disable interrupt for ACCOF event + Write '1' to disable interrupt for ACCOF event 2 2 @@ -25817,7 +25776,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DBLRDY - Write '1' to Disable interrupt for DBLRDY event + Write '1' to disable interrupt for DBLRDY event 3 3 @@ -25844,7 +25803,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 4 4 @@ -26297,9 +26256,7 @@ POSSIBILITY OF SUCH DAMAGE.\n COMP Comparator - COMP 0x40013000 - 32 0 0x1000 @@ -26309,6 +26266,8 @@ POSSIBILITY OF SUCH DAMAGE.\n COMP_LPCOMP 19 + COMP + 0x20 TASKS_START @@ -26587,7 +26546,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Enable interrupt for READY event + Write '1' to enable interrupt for READY event 0 0 @@ -26614,7 +26573,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DOWN - Write '1' to Enable interrupt for DOWN event + Write '1' to enable interrupt for DOWN event 1 1 @@ -26641,7 +26600,7 @@ POSSIBILITY OF SUCH DAMAGE.\n UP - Write '1' to Enable interrupt for UP event + Write '1' to enable interrupt for UP event 2 2 @@ -26668,7 +26627,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CROSS - Write '1' to Enable interrupt for CROSS event + Write '1' to enable interrupt for CROSS event 3 3 @@ -26703,7 +26662,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Disable interrupt for READY event + Write '1' to disable interrupt for READY event 0 0 @@ -26730,7 +26689,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DOWN - Write '1' to Disable interrupt for DOWN event + Write '1' to disable interrupt for DOWN event 1 1 @@ -26757,7 +26716,7 @@ POSSIBILITY OF SUCH DAMAGE.\n UP - Write '1' to Disable interrupt for UP event + Write '1' to disable interrupt for UP event 2 2 @@ -26784,7 +26743,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CROSS - Write '1' to Disable interrupt for CROSS event + Write '1' to disable interrupt for CROSS event 3 3 @@ -27118,9 +27077,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LPCOMP Low Power Comparator - LPCOMP 0x40013000 - 32 COMP 0 @@ -27131,6 +27088,8 @@ POSSIBILITY OF SUCH DAMAGE.\n COMP_LPCOMP 19 + LPCOMP + 0x20 TASKS_START @@ -27329,7 +27288,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Enable interrupt for READY event + Write '1' to enable interrupt for READY event 0 0 @@ -27356,7 +27315,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DOWN - Write '1' to Enable interrupt for DOWN event + Write '1' to enable interrupt for DOWN event 1 1 @@ -27383,7 +27342,7 @@ POSSIBILITY OF SUCH DAMAGE.\n UP - Write '1' to Enable interrupt for UP event + Write '1' to enable interrupt for UP event 2 2 @@ -27410,7 +27369,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CROSS - Write '1' to Enable interrupt for CROSS event + Write '1' to enable interrupt for CROSS event 3 3 @@ -27445,7 +27404,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Disable interrupt for READY event + Write '1' to disable interrupt for READY event 0 0 @@ -27472,7 +27431,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DOWN - Write '1' to Disable interrupt for DOWN event + Write '1' to disable interrupt for DOWN event 1 1 @@ -27499,7 +27458,7 @@ POSSIBILITY OF SUCH DAMAGE.\n UP - Write '1' to Disable interrupt for UP event + Write '1' to disable interrupt for UP event 2 2 @@ -27526,7 +27485,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CROSS - Write '1' to Disable interrupt for CROSS event + Write '1' to disable interrupt for CROSS event 3 3 @@ -27843,39 +27802,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - - SWI0 - Software interrupt 0 - SWI - 0x40014000 - 32 - SWI - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - - - UNUSED - Unused. - 0x000 - 0x00000000 - read-only - - - EGU0 Event Generator Unit 0 - EGU 0x40014000 - 32 - SWI0 EGU 0 @@ -27886,12 +27816,14 @@ POSSIBILITY OF SUCH DAMAGE.\n SWI0_EGU0 20 + EGU + 0x20 - 16 - 4 + 0x10 + 0x4 TASKS_TRIGGER[%s] - Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event + Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event 0x000 write-only @@ -27903,10 +27835,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 16 - 4 + 0x10 + 0x4 EVENTS_TRIGGERED[%s] - Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task + Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task 0x100 read-write @@ -28221,7 +28153,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED0 - Write '1' to Enable interrupt for TRIGGERED[0] event + Write '1' to enable interrupt for TRIGGERED[0] event 0 0 @@ -28248,7 +28180,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED1 - Write '1' to Enable interrupt for TRIGGERED[1] event + Write '1' to enable interrupt for TRIGGERED[1] event 1 1 @@ -28275,7 +28207,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED2 - Write '1' to Enable interrupt for TRIGGERED[2] event + Write '1' to enable interrupt for TRIGGERED[2] event 2 2 @@ -28302,7 +28234,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED3 - Write '1' to Enable interrupt for TRIGGERED[3] event + Write '1' to enable interrupt for TRIGGERED[3] event 3 3 @@ -28329,7 +28261,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED4 - Write '1' to Enable interrupt for TRIGGERED[4] event + Write '1' to enable interrupt for TRIGGERED[4] event 4 4 @@ -28356,7 +28288,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED5 - Write '1' to Enable interrupt for TRIGGERED[5] event + Write '1' to enable interrupt for TRIGGERED[5] event 5 5 @@ -28383,7 +28315,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED6 - Write '1' to Enable interrupt for TRIGGERED[6] event + Write '1' to enable interrupt for TRIGGERED[6] event 6 6 @@ -28410,7 +28342,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED7 - Write '1' to Enable interrupt for TRIGGERED[7] event + Write '1' to enable interrupt for TRIGGERED[7] event 7 7 @@ -28437,7 +28369,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED8 - Write '1' to Enable interrupt for TRIGGERED[8] event + Write '1' to enable interrupt for TRIGGERED[8] event 8 8 @@ -28464,7 +28396,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED9 - Write '1' to Enable interrupt for TRIGGERED[9] event + Write '1' to enable interrupt for TRIGGERED[9] event 9 9 @@ -28491,7 +28423,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED10 - Write '1' to Enable interrupt for TRIGGERED[10] event + Write '1' to enable interrupt for TRIGGERED[10] event 10 10 @@ -28518,7 +28450,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED11 - Write '1' to Enable interrupt for TRIGGERED[11] event + Write '1' to enable interrupt for TRIGGERED[11] event 11 11 @@ -28545,7 +28477,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED12 - Write '1' to Enable interrupt for TRIGGERED[12] event + Write '1' to enable interrupt for TRIGGERED[12] event 12 12 @@ -28572,7 +28504,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED13 - Write '1' to Enable interrupt for TRIGGERED[13] event + Write '1' to enable interrupt for TRIGGERED[13] event 13 13 @@ -28599,7 +28531,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED14 - Write '1' to Enable interrupt for TRIGGERED[14] event + Write '1' to enable interrupt for TRIGGERED[14] event 14 14 @@ -28626,7 +28558,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED15 - Write '1' to Enable interrupt for TRIGGERED[15] event + Write '1' to enable interrupt for TRIGGERED[15] event 15 15 @@ -28661,7 +28593,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED0 - Write '1' to Disable interrupt for TRIGGERED[0] event + Write '1' to disable interrupt for TRIGGERED[0] event 0 0 @@ -28688,7 +28620,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED1 - Write '1' to Disable interrupt for TRIGGERED[1] event + Write '1' to disable interrupt for TRIGGERED[1] event 1 1 @@ -28715,7 +28647,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED2 - Write '1' to Disable interrupt for TRIGGERED[2] event + Write '1' to disable interrupt for TRIGGERED[2] event 2 2 @@ -28742,7 +28674,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED3 - Write '1' to Disable interrupt for TRIGGERED[3] event + Write '1' to disable interrupt for TRIGGERED[3] event 3 3 @@ -28769,7 +28701,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED4 - Write '1' to Disable interrupt for TRIGGERED[4] event + Write '1' to disable interrupt for TRIGGERED[4] event 4 4 @@ -28796,7 +28728,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED5 - Write '1' to Disable interrupt for TRIGGERED[5] event + Write '1' to disable interrupt for TRIGGERED[5] event 5 5 @@ -28823,7 +28755,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED6 - Write '1' to Disable interrupt for TRIGGERED[6] event + Write '1' to disable interrupt for TRIGGERED[6] event 6 6 @@ -28850,7 +28782,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED7 - Write '1' to Disable interrupt for TRIGGERED[7] event + Write '1' to disable interrupt for TRIGGERED[7] event 7 7 @@ -28877,7 +28809,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED8 - Write '1' to Disable interrupt for TRIGGERED[8] event + Write '1' to disable interrupt for TRIGGERED[8] event 8 8 @@ -28904,7 +28836,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED9 - Write '1' to Disable interrupt for TRIGGERED[9] event + Write '1' to disable interrupt for TRIGGERED[9] event 9 9 @@ -28931,7 +28863,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED10 - Write '1' to Disable interrupt for TRIGGERED[10] event + Write '1' to disable interrupt for TRIGGERED[10] event 10 10 @@ -28958,7 +28890,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED11 - Write '1' to Disable interrupt for TRIGGERED[11] event + Write '1' to disable interrupt for TRIGGERED[11] event 11 11 @@ -28985,7 +28917,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED12 - Write '1' to Disable interrupt for TRIGGERED[12] event + Write '1' to disable interrupt for TRIGGERED[12] event 12 12 @@ -29012,7 +28944,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED13 - Write '1' to Disable interrupt for TRIGGERED[13] event + Write '1' to disable interrupt for TRIGGERED[13] event 13 13 @@ -29039,7 +28971,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED14 - Write '1' to Disable interrupt for TRIGGERED[14] event + Write '1' to disable interrupt for TRIGGERED[14] event 14 14 @@ -29066,7 +28998,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRIGGERED15 - Write '1' to Disable interrupt for TRIGGERED[15] event + Write '1' to disable interrupt for TRIGGERED[15] event 15 15 @@ -29095,116 +29027,123 @@ POSSIBILITY OF SUCH DAMAGE.\n - - SWI1 - Software interrupt 1 - SWI - 0x40015000 - 32 + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + - SWI1_EGU1 - 21 + SWI0_EGU0 + 20 + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + EGU1 Event Generator Unit 1 - EGU 0x40015000 - 32 - SWI1 SWI1_EGU1 21 - SWI2 - Software interrupt 2 - SWI - 0x40016000 - 32 + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 - SWI2_EGU2 - 22 + SWI1_EGU1 + 21 EGU2 Event Generator Unit 2 - EGU 0x40016000 - 32 - SWI2 SWI2_EGU2 22 - SWI3 - Software interrupt 3 - SWI - 0x40017000 - 32 + SWI2 + Software interrupt 2 + 0x40016000 + EGU2 - SWI3_EGU3 - 23 + SWI2_EGU2 + 22 EGU3 Event Generator Unit 3 - EGU 0x40017000 - 32 - SWI3 SWI3_EGU3 23 - SWI4 - Software interrupt 4 - SWI - 0x40018000 - 32 + SWI3 + Software interrupt 3 + 0x40017000 + EGU3 - SWI4_EGU4 - 24 + SWI3_EGU3 + 23 EGU4 Event Generator Unit 4 - EGU 0x40018000 - 32 - SWI4 SWI4_EGU4 24 - SWI5 - Software interrupt 5 - SWI - 0x40019000 - 32 + SWI4 + Software interrupt 4 + 0x40018000 + EGU4 - SWI5_EGU5 - 25 + SWI4_EGU4 + 24 EGU5 Event Generator Unit 5 - EGU 0x40019000 - 32 - SWI5 + + SWI5_EGU5 + 25 + + + + SWI5 + Software interrupt 5 + 0x40019000 + EGU5 SWI5_EGU5 25 @@ -29213,9 +29152,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMER3 Timer/Counter 3 - TIMER 0x4001A000 - 32 TIMER3 26 @@ -29224,9 +29161,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIMER4 Timer/Counter 4 - TIMER 0x4001B000 - 32 TIMER4 27 @@ -29235,9 +29170,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PWM0 Pulse width modulation unit 0 - PWM 0x4001C000 - 32 PWM 0 @@ -29248,6 +29181,8 @@ POSSIBILITY OF SUCH DAMAGE.\n PWM0 28 + PWM + 0x20 TASKS_STOP @@ -29263,10 +29198,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 - 4 + 0x2 + 0x4 TASKS_SEQSTART[%s] - Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0x008 write-only @@ -29304,10 +29239,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 - 4 + 0x2 + 0x4 EVENTS_SEQSTARTED[%s] - Description collection[0]: First PWM period started on sequence 0 + Description collection[n]: First PWM period started on sequence n 0x108 read-write @@ -29319,10 +29254,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 2 - 4 + 0x2 + 0x4 EVENTS_SEQEND[%s] - Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter + Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0x110 read-write @@ -29599,7 +29534,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 1 1 @@ -29626,7 +29561,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQSTARTED0 - Write '1' to Enable interrupt for SEQSTARTED[0] event + Write '1' to enable interrupt for SEQSTARTED[0] event 2 2 @@ -29653,7 +29588,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQSTARTED1 - Write '1' to Enable interrupt for SEQSTARTED[1] event + Write '1' to enable interrupt for SEQSTARTED[1] event 3 3 @@ -29680,7 +29615,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQEND0 - Write '1' to Enable interrupt for SEQEND[0] event + Write '1' to enable interrupt for SEQEND[0] event 4 4 @@ -29707,7 +29642,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQEND1 - Write '1' to Enable interrupt for SEQEND[1] event + Write '1' to enable interrupt for SEQEND[1] event 5 5 @@ -29734,7 +29669,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PWMPERIODEND - Write '1' to Enable interrupt for PWMPERIODEND event + Write '1' to enable interrupt for PWMPERIODEND event 6 6 @@ -29761,7 +29696,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LOOPSDONE - Write '1' to Enable interrupt for LOOPSDONE event + Write '1' to enable interrupt for LOOPSDONE event 7 7 @@ -29796,7 +29731,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 1 1 @@ -29823,7 +29758,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQSTARTED0 - Write '1' to Disable interrupt for SEQSTARTED[0] event + Write '1' to disable interrupt for SEQSTARTED[0] event 2 2 @@ -29850,7 +29785,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQSTARTED1 - Write '1' to Disable interrupt for SEQSTARTED[1] event + Write '1' to disable interrupt for SEQSTARTED[1] event 3 3 @@ -29877,7 +29812,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQEND0 - Write '1' to Disable interrupt for SEQEND[0] event + Write '1' to disable interrupt for SEQEND[0] event 4 4 @@ -29904,7 +29839,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SEQEND1 - Write '1' to Disable interrupt for SEQEND[1] event + Write '1' to disable interrupt for SEQEND[1] event 5 5 @@ -29931,7 +29866,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PWMPERIODEND - Write '1' to Disable interrupt for PWMPERIODEND event + Write '1' to disable interrupt for PWMPERIODEND event 6 6 @@ -29958,7 +29893,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LOOPSDONE - Write '1' to Disable interrupt for LOOPSDONE event + Write '1' to disable interrupt for LOOPSDONE event 7 7 @@ -30190,14 +30125,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 2 - 32 + 0x020 SEQ[%s] Unspecified PWM_SEQ 0x520 PTR - Description cluster[0]: Beginning address in RAM of this sequence + Description cluster[n]: Beginning address in RAM of this sequence 0x000 read-write 0x00000000 @@ -30212,7 +30147,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CNT - Description cluster[0]: Number of values (duty cycles) in this sequence + Description cluster[n]: Number of values (duty cycles) in this sequence 0x004 read-write 0x00000000 @@ -30234,7 +30169,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REFRESH - Description cluster[0]: Number of additional PWM periods between samples loaded into compare register + Description cluster[n]: Number of additional PWM periods between samples loaded into compare register 0x008 read-write 0x00000001 @@ -30256,7 +30191,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDDELAY - Description cluster[0]: Time added after the sequence + Description cluster[n]: Time added after the sequence 0x00C read-write 0x00000000 @@ -30276,10 +30211,10 @@ POSSIBILITY OF SUCH DAMAGE.\n PWM_PSEL 0x560 - 4 - 4 + 0x4 + 0x4 OUT[%s] - Description collection[0]: Output pin select for PWM channel 0 + Description collection[n]: Output pin select for PWM channel n 0x000 read-write 0xFFFFFFFF @@ -30322,9 +30257,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PDM Pulse Density Modulation (Digital Microphone) Interface - PDM 0x4001D000 - 32 0 0x1000 @@ -30334,6 +30267,8 @@ POSSIBILITY OF SUCH DAMAGE.\n PDM 29 + PDM + 0x20 TASKS_START @@ -30470,7 +30405,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Enable interrupt for STARTED event + Write '1' to enable interrupt for STARTED event 0 0 @@ -30497,7 +30432,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 1 1 @@ -30524,7 +30459,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Enable interrupt for END event + Write '1' to enable interrupt for END event 2 2 @@ -30559,7 +30494,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Disable interrupt for STARTED event + Write '1' to disable interrupt for STARTED event 0 0 @@ -30586,7 +30521,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 1 1 @@ -30613,7 +30548,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Write '1' to Disable interrupt for END event + Write '1' to disable interrupt for END event 2 2 @@ -30971,16 +30906,120 @@ POSSIBILITY OF SUCH DAMAGE.\n - NVMC - Non Volatile Memory Controller - NVMC + ACL + Access control lists 0x4001E000 - 32 0 0x1000 registers + ACL + 0x20 + + + 8 + 0x010 + ACL[%s] + Unspecified + ACL_ACL + 0x800 + + ADDR + Description cluster[n]: Configure the word-aligned start address of region n to protect + 0x000 + read-write + 0x00000000 + + + ADDR + Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. + 0 + 31 + + + + + SIZE + Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + 0x004 + read-write + 0x00000000 + + + SIZE + Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. + 0 + 31 + + + + + PERM + Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE + 0x008 + read-write + 0x00000000 + + + WRITE + Configure write and erase permissions for region n. Write '0' has no effect. + 1 + 1 + + + Enable + Allow write and erase instructions to region n + 0 + + + Disable + Block write and erase instructions to region n + 1 + + + + + READ + Configure read permissions for region n. Write '0' has no effect. + 2 + 2 + + + Enable + Allow read instructions to region n + 0 + + + Disable + Block read instructions to region n + 1 + + + + + + + UNUSED0 + Unspecified + 0x00C + read-write + + + + + + NVMC + Non Volatile Memory Controller + 0x4001E000 + ACL + + 0 + 0x1000 + registers + + NVMC + 0x20 READY @@ -31067,29 +31106,29 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERASEPCR1 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + ERASEPAGE + Register for erasing a page in code area 0x508 read-write - ERASEPCR1 - Register for erasing a page in code area. Equivalent to ERASEPAGE. + ERASEPAGE + Register for starting erase of a page in code area 0 31 - ERASEPAGE - Register for erasing a page in code area + ERASEPCR1 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. 0x508 read-write - ERASEPCR1 + ERASEPAGE - ERASEPAGE - Register for starting erase of a page in code area + ERASEPCR1 + Register for erasing a page in code area. Equivalent to ERASEPAGE. 0 31 @@ -31123,7 +31162,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERASEPCR0 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. 0x510 read-write @@ -31265,132 +31304,28 @@ POSSIBILITY OF SUCH DAMAGE.\n - - ACL - Access control lists - ACL - 0x4001E000 - 32 - NVMC - - 0 - 0x1000 - registers - - - - 8 - 16 - ACL[%s] - Unspecified - ACL_ACL - 0x800 - - ADDR - Description cluster[0]: Configure the word-aligned start address of region 0 to protect - 0x000 - read-write - 0x00000000 - - - ADDR - Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary. - 0 - 31 - - - - - SIZE - Description cluster[0]: Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect. - 0x004 - read-write - 0x00000000 - - - SIZE - Size of flash region 0 in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. - 0 - 31 - - - - - PERM - Description cluster[0]: Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE - 0x008 - read-write - 0x00000000 - - - WRITE - Configure write and erase permissions for region 0. Write '0' has no effect. - 1 - 1 - - - Enable - Allow write and erase instructions to region 0 - 0 - - - Disable - Block write and erase instructions to region 0 - 1 - - - - - READ - Configure read permissions for region 0. Write '0' has no effect. - 2 - 2 - - - Enable - Allow read instructions to region 0 - 0 - - - Disable - Block read instructions to region 0 - 1 - - - - - - - UNUSED0 - Unspecified - 0x00C - read-write - - - - PPI Programmable Peripheral Interconnect - PPI 0x4001F000 - 32 0 0x1000 registers + PPI + 0x20 6 - 8 + 0x008 TASKS_CHG[%s] Channel group tasks PPI_TASKS_CHG 0x000 EN - Description cluster[0]: Enable channel group 0 + Description cluster[n]: Enable channel group n 0x000 write-only @@ -31403,7 +31338,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DIS - Description cluster[0]: Disable channel group 0 + Description cluster[n]: Disable channel group n 0x004 write-only @@ -33747,14 +33682,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 20 - 8 + 0x008 CH[%s] PPI Channel PPI_CH 0x510 EEP - Description cluster[0]: Channel 0 event end-point + Description cluster[n]: Channel n event end-point 0x000 read-write @@ -33768,7 +33703,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEP - Description cluster[0]: Channel 0 task end-point + Description cluster[n]: Channel n task end-point 0x004 read-write @@ -33782,10 +33717,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 6 - 4 + 0x6 + 0x4 CHG[%s] - Description collection[0]: Channel group 0 + Description collection[n]: Channel group n 0x800 read-write @@ -34369,14 +34304,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 32 - 4 + 0x004 FORK[%s] Fork PPI_FORK 0x910 TEP - Description cluster[0]: Channel 0 task end-point + Description cluster[n]: Channel n task end-point 0x000 read-write @@ -34394,9 +34329,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MWU Memory Watch Unit - MWU 0x40020000 - 32 0 0x1000 @@ -34406,17 +34339,19 @@ POSSIBILITY OF SUCH DAMAGE.\n MWU 32 + MWU + 0x20 4 - 8 + 0x008 EVENTS_REGION[%s] Unspecified MWU_EVENTS_REGION 0x100 WA - Description cluster[0]: Write access to region 0 detected + Description cluster[n]: Write access to region n detected 0x000 read-write @@ -34429,7 +34364,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RA - Description cluster[0]: Read access to region 0 detected + Description cluster[n]: Read access to region n detected 0x004 read-write @@ -34443,14 +34378,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 2 - 8 + 0x008 EVENTS_PREGION[%s] Unspecified MWU_EVENTS_PREGION 0x160 WA - Description cluster[0]: Write access to peripheral region 0 detected + Description cluster[n]: Write access to peripheral region n detected 0x000 read-write @@ -34463,7 +34398,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RA - Description cluster[0]: Read access to peripheral region 0 detected + Description cluster[n]: Read access to peripheral region n detected 0x004 read-write @@ -34707,7 +34642,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0WA - Write '1' to Enable interrupt for REGION[0].WA event + Write '1' to enable interrupt for REGION[0].WA event 0 0 @@ -34734,7 +34669,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0RA - Write '1' to Enable interrupt for REGION[0].RA event + Write '1' to enable interrupt for REGION[0].RA event 1 1 @@ -34761,7 +34696,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1WA - Write '1' to Enable interrupt for REGION[1].WA event + Write '1' to enable interrupt for REGION[1].WA event 2 2 @@ -34788,7 +34723,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1RA - Write '1' to Enable interrupt for REGION[1].RA event + Write '1' to enable interrupt for REGION[1].RA event 3 3 @@ -34815,7 +34750,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2WA - Write '1' to Enable interrupt for REGION[2].WA event + Write '1' to enable interrupt for REGION[2].WA event 4 4 @@ -34842,7 +34777,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2RA - Write '1' to Enable interrupt for REGION[2].RA event + Write '1' to enable interrupt for REGION[2].RA event 5 5 @@ -34869,7 +34804,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3WA - Write '1' to Enable interrupt for REGION[3].WA event + Write '1' to enable interrupt for REGION[3].WA event 6 6 @@ -34896,7 +34831,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3RA - Write '1' to Enable interrupt for REGION[3].RA event + Write '1' to enable interrupt for REGION[3].RA event 7 7 @@ -34923,7 +34858,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0WA - Write '1' to Enable interrupt for PREGION[0].WA event + Write '1' to enable interrupt for PREGION[0].WA event 24 24 @@ -34950,7 +34885,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0RA - Write '1' to Enable interrupt for PREGION[0].RA event + Write '1' to enable interrupt for PREGION[0].RA event 25 25 @@ -34977,7 +34912,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1WA - Write '1' to Enable interrupt for PREGION[1].WA event + Write '1' to enable interrupt for PREGION[1].WA event 26 26 @@ -35004,7 +34939,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1RA - Write '1' to Enable interrupt for PREGION[1].RA event + Write '1' to enable interrupt for PREGION[1].RA event 27 27 @@ -35039,7 +34974,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0WA - Write '1' to Disable interrupt for REGION[0].WA event + Write '1' to disable interrupt for REGION[0].WA event 0 0 @@ -35066,7 +35001,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0RA - Write '1' to Disable interrupt for REGION[0].RA event + Write '1' to disable interrupt for REGION[0].RA event 1 1 @@ -35093,7 +35028,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1WA - Write '1' to Disable interrupt for REGION[1].WA event + Write '1' to disable interrupt for REGION[1].WA event 2 2 @@ -35120,7 +35055,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1RA - Write '1' to Disable interrupt for REGION[1].RA event + Write '1' to disable interrupt for REGION[1].RA event 3 3 @@ -35147,7 +35082,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2WA - Write '1' to Disable interrupt for REGION[2].WA event + Write '1' to disable interrupt for REGION[2].WA event 4 4 @@ -35174,7 +35109,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2RA - Write '1' to Disable interrupt for REGION[2].RA event + Write '1' to disable interrupt for REGION[2].RA event 5 5 @@ -35201,7 +35136,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3WA - Write '1' to Disable interrupt for REGION[3].WA event + Write '1' to disable interrupt for REGION[3].WA event 6 6 @@ -35228,7 +35163,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3RA - Write '1' to Disable interrupt for REGION[3].RA event + Write '1' to disable interrupt for REGION[3].RA event 7 7 @@ -35255,7 +35190,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0WA - Write '1' to Disable interrupt for PREGION[0].WA event + Write '1' to disable interrupt for PREGION[0].WA event 24 24 @@ -35282,7 +35217,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0RA - Write '1' to Disable interrupt for PREGION[0].RA event + Write '1' to disable interrupt for PREGION[0].RA event 25 25 @@ -35309,7 +35244,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1WA - Write '1' to Disable interrupt for PREGION[1].WA event + Write '1' to disable interrupt for PREGION[1].WA event 26 26 @@ -35336,7 +35271,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1RA - Write '1' to Disable interrupt for PREGION[1].RA event + Write '1' to disable interrupt for PREGION[1].RA event 27 27 @@ -35595,7 +35530,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0WA - Write '1' to Enable non-maskable interrupt for REGION[0].WA event + Write '1' to enable non-maskable interrupt for REGION[0].WA event 0 0 @@ -35622,7 +35557,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0RA - Write '1' to Enable non-maskable interrupt for REGION[0].RA event + Write '1' to enable non-maskable interrupt for REGION[0].RA event 1 1 @@ -35649,7 +35584,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1WA - Write '1' to Enable non-maskable interrupt for REGION[1].WA event + Write '1' to enable non-maskable interrupt for REGION[1].WA event 2 2 @@ -35676,7 +35611,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1RA - Write '1' to Enable non-maskable interrupt for REGION[1].RA event + Write '1' to enable non-maskable interrupt for REGION[1].RA event 3 3 @@ -35703,7 +35638,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2WA - Write '1' to Enable non-maskable interrupt for REGION[2].WA event + Write '1' to enable non-maskable interrupt for REGION[2].WA event 4 4 @@ -35730,7 +35665,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2RA - Write '1' to Enable non-maskable interrupt for REGION[2].RA event + Write '1' to enable non-maskable interrupt for REGION[2].RA event 5 5 @@ -35757,7 +35692,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3WA - Write '1' to Enable non-maskable interrupt for REGION[3].WA event + Write '1' to enable non-maskable interrupt for REGION[3].WA event 6 6 @@ -35784,7 +35719,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3RA - Write '1' to Enable non-maskable interrupt for REGION[3].RA event + Write '1' to enable non-maskable interrupt for REGION[3].RA event 7 7 @@ -35811,7 +35746,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0WA - Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + Write '1' to enable non-maskable interrupt for PREGION[0].WA event 24 24 @@ -35838,7 +35773,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0RA - Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + Write '1' to enable non-maskable interrupt for PREGION[0].RA event 25 25 @@ -35865,7 +35800,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1WA - Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + Write '1' to enable non-maskable interrupt for PREGION[1].WA event 26 26 @@ -35892,7 +35827,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1RA - Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + Write '1' to enable non-maskable interrupt for PREGION[1].RA event 27 27 @@ -35927,7 +35862,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0WA - Write '1' to Disable non-maskable interrupt for REGION[0].WA event + Write '1' to disable non-maskable interrupt for REGION[0].WA event 0 0 @@ -35954,7 +35889,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION0RA - Write '1' to Disable non-maskable interrupt for REGION[0].RA event + Write '1' to disable non-maskable interrupt for REGION[0].RA event 1 1 @@ -35981,7 +35916,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1WA - Write '1' to Disable non-maskable interrupt for REGION[1].WA event + Write '1' to disable non-maskable interrupt for REGION[1].WA event 2 2 @@ -36008,7 +35943,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION1RA - Write '1' to Disable non-maskable interrupt for REGION[1].RA event + Write '1' to disable non-maskable interrupt for REGION[1].RA event 3 3 @@ -36035,7 +35970,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2WA - Write '1' to Disable non-maskable interrupt for REGION[2].WA event + Write '1' to disable non-maskable interrupt for REGION[2].WA event 4 4 @@ -36062,7 +35997,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION2RA - Write '1' to Disable non-maskable interrupt for REGION[2].RA event + Write '1' to disable non-maskable interrupt for REGION[2].RA event 5 5 @@ -36089,7 +36024,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3WA - Write '1' to Disable non-maskable interrupt for REGION[3].WA event + Write '1' to disable non-maskable interrupt for REGION[3].WA event 6 6 @@ -36116,7 +36051,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGION3RA - Write '1' to Disable non-maskable interrupt for REGION[3].RA event + Write '1' to disable non-maskable interrupt for REGION[3].RA event 7 7 @@ -36143,7 +36078,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0WA - Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + Write '1' to disable non-maskable interrupt for PREGION[0].WA event 24 24 @@ -36170,7 +36105,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION0RA - Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + Write '1' to disable non-maskable interrupt for PREGION[0].RA event 25 25 @@ -36197,7 +36132,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1WA - Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + Write '1' to disable non-maskable interrupt for PREGION[1].WA event 26 26 @@ -36224,7 +36159,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PREGION1RA - Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + Write '1' to disable non-maskable interrupt for PREGION[1].RA event 27 27 @@ -36253,21 +36188,21 @@ POSSIBILITY OF SUCH DAMAGE.\n 2 - 8 + 0x008 PERREGION[%s] Unspecified MWU_PERREGION 0x400 SUBSTATWA - Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching + Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching 0x000 read-write oneToClear SR0 - Subregion 0 in region 0 (write '1' to clear) + Subregion 0 in region n (write '1' to clear) 0 0 @@ -36285,7 +36220,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR1 - Subregion 1 in region 0 (write '1' to clear) + Subregion 1 in region n (write '1' to clear) 1 1 @@ -36303,7 +36238,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR2 - Subregion 2 in region 0 (write '1' to clear) + Subregion 2 in region n (write '1' to clear) 2 2 @@ -36321,7 +36256,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR3 - Subregion 3 in region 0 (write '1' to clear) + Subregion 3 in region n (write '1' to clear) 3 3 @@ -36339,7 +36274,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR4 - Subregion 4 in region 0 (write '1' to clear) + Subregion 4 in region n (write '1' to clear) 4 4 @@ -36357,7 +36292,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR5 - Subregion 5 in region 0 (write '1' to clear) + Subregion 5 in region n (write '1' to clear) 5 5 @@ -36375,7 +36310,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR6 - Subregion 6 in region 0 (write '1' to clear) + Subregion 6 in region n (write '1' to clear) 6 6 @@ -36393,7 +36328,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR7 - Subregion 7 in region 0 (write '1' to clear) + Subregion 7 in region n (write '1' to clear) 7 7 @@ -36411,7 +36346,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR8 - Subregion 8 in region 0 (write '1' to clear) + Subregion 8 in region n (write '1' to clear) 8 8 @@ -36429,7 +36364,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR9 - Subregion 9 in region 0 (write '1' to clear) + Subregion 9 in region n (write '1' to clear) 9 9 @@ -36447,7 +36382,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR10 - Subregion 10 in region 0 (write '1' to clear) + Subregion 10 in region n (write '1' to clear) 10 10 @@ -36465,7 +36400,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR11 - Subregion 11 in region 0 (write '1' to clear) + Subregion 11 in region n (write '1' to clear) 11 11 @@ -36483,7 +36418,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR12 - Subregion 12 in region 0 (write '1' to clear) + Subregion 12 in region n (write '1' to clear) 12 12 @@ -36501,7 +36436,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR13 - Subregion 13 in region 0 (write '1' to clear) + Subregion 13 in region n (write '1' to clear) 13 13 @@ -36519,7 +36454,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR14 - Subregion 14 in region 0 (write '1' to clear) + Subregion 14 in region n (write '1' to clear) 14 14 @@ -36537,7 +36472,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR15 - Subregion 15 in region 0 (write '1' to clear) + Subregion 15 in region n (write '1' to clear) 15 15 @@ -36555,7 +36490,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR16 - Subregion 16 in region 0 (write '1' to clear) + Subregion 16 in region n (write '1' to clear) 16 16 @@ -36573,7 +36508,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR17 - Subregion 17 in region 0 (write '1' to clear) + Subregion 17 in region n (write '1' to clear) 17 17 @@ -36591,7 +36526,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR18 - Subregion 18 in region 0 (write '1' to clear) + Subregion 18 in region n (write '1' to clear) 18 18 @@ -36609,7 +36544,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR19 - Subregion 19 in region 0 (write '1' to clear) + Subregion 19 in region n (write '1' to clear) 19 19 @@ -36627,7 +36562,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR20 - Subregion 20 in region 0 (write '1' to clear) + Subregion 20 in region n (write '1' to clear) 20 20 @@ -36645,7 +36580,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR21 - Subregion 21 in region 0 (write '1' to clear) + Subregion 21 in region n (write '1' to clear) 21 21 @@ -36663,7 +36598,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR22 - Subregion 22 in region 0 (write '1' to clear) + Subregion 22 in region n (write '1' to clear) 22 22 @@ -36681,7 +36616,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR23 - Subregion 23 in region 0 (write '1' to clear) + Subregion 23 in region n (write '1' to clear) 23 23 @@ -36699,7 +36634,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR24 - Subregion 24 in region 0 (write '1' to clear) + Subregion 24 in region n (write '1' to clear) 24 24 @@ -36717,7 +36652,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR25 - Subregion 25 in region 0 (write '1' to clear) + Subregion 25 in region n (write '1' to clear) 25 25 @@ -36735,7 +36670,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR26 - Subregion 26 in region 0 (write '1' to clear) + Subregion 26 in region n (write '1' to clear) 26 26 @@ -36753,7 +36688,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR27 - Subregion 27 in region 0 (write '1' to clear) + Subregion 27 in region n (write '1' to clear) 27 27 @@ -36771,7 +36706,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR28 - Subregion 28 in region 0 (write '1' to clear) + Subregion 28 in region n (write '1' to clear) 28 28 @@ -36789,7 +36724,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR29 - Subregion 29 in region 0 (write '1' to clear) + Subregion 29 in region n (write '1' to clear) 29 29 @@ -36807,7 +36742,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR30 - Subregion 30 in region 0 (write '1' to clear) + Subregion 30 in region n (write '1' to clear) 30 30 @@ -36825,7 +36760,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR31 - Subregion 31 in region 0 (write '1' to clear) + Subregion 31 in region n (write '1' to clear) 31 31 @@ -36845,14 +36780,14 @@ POSSIBILITY OF SUCH DAMAGE.\n SUBSTATRA - Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching + Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching 0x004 read-write oneToClear SR0 - Subregion 0 in region 0 (write '1' to clear) + Subregion 0 in region n (write '1' to clear) 0 0 @@ -36870,7 +36805,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR1 - Subregion 1 in region 0 (write '1' to clear) + Subregion 1 in region n (write '1' to clear) 1 1 @@ -36888,7 +36823,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR2 - Subregion 2 in region 0 (write '1' to clear) + Subregion 2 in region n (write '1' to clear) 2 2 @@ -36906,7 +36841,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR3 - Subregion 3 in region 0 (write '1' to clear) + Subregion 3 in region n (write '1' to clear) 3 3 @@ -36924,7 +36859,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR4 - Subregion 4 in region 0 (write '1' to clear) + Subregion 4 in region n (write '1' to clear) 4 4 @@ -36942,7 +36877,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR5 - Subregion 5 in region 0 (write '1' to clear) + Subregion 5 in region n (write '1' to clear) 5 5 @@ -36960,7 +36895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR6 - Subregion 6 in region 0 (write '1' to clear) + Subregion 6 in region n (write '1' to clear) 6 6 @@ -36978,7 +36913,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR7 - Subregion 7 in region 0 (write '1' to clear) + Subregion 7 in region n (write '1' to clear) 7 7 @@ -36996,7 +36931,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR8 - Subregion 8 in region 0 (write '1' to clear) + Subregion 8 in region n (write '1' to clear) 8 8 @@ -37014,7 +36949,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR9 - Subregion 9 in region 0 (write '1' to clear) + Subregion 9 in region n (write '1' to clear) 9 9 @@ -37032,7 +36967,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR10 - Subregion 10 in region 0 (write '1' to clear) + Subregion 10 in region n (write '1' to clear) 10 10 @@ -37050,7 +36985,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR11 - Subregion 11 in region 0 (write '1' to clear) + Subregion 11 in region n (write '1' to clear) 11 11 @@ -37068,7 +37003,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR12 - Subregion 12 in region 0 (write '1' to clear) + Subregion 12 in region n (write '1' to clear) 12 12 @@ -37086,7 +37021,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR13 - Subregion 13 in region 0 (write '1' to clear) + Subregion 13 in region n (write '1' to clear) 13 13 @@ -37104,7 +37039,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR14 - Subregion 14 in region 0 (write '1' to clear) + Subregion 14 in region n (write '1' to clear) 14 14 @@ -37122,7 +37057,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR15 - Subregion 15 in region 0 (write '1' to clear) + Subregion 15 in region n (write '1' to clear) 15 15 @@ -37140,7 +37075,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR16 - Subregion 16 in region 0 (write '1' to clear) + Subregion 16 in region n (write '1' to clear) 16 16 @@ -37158,7 +37093,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR17 - Subregion 17 in region 0 (write '1' to clear) + Subregion 17 in region n (write '1' to clear) 17 17 @@ -37176,7 +37111,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR18 - Subregion 18 in region 0 (write '1' to clear) + Subregion 18 in region n (write '1' to clear) 18 18 @@ -37194,7 +37129,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR19 - Subregion 19 in region 0 (write '1' to clear) + Subregion 19 in region n (write '1' to clear) 19 19 @@ -37212,7 +37147,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR20 - Subregion 20 in region 0 (write '1' to clear) + Subregion 20 in region n (write '1' to clear) 20 20 @@ -37230,7 +37165,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR21 - Subregion 21 in region 0 (write '1' to clear) + Subregion 21 in region n (write '1' to clear) 21 21 @@ -37248,7 +37183,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR22 - Subregion 22 in region 0 (write '1' to clear) + Subregion 22 in region n (write '1' to clear) 22 22 @@ -37266,7 +37201,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR23 - Subregion 23 in region 0 (write '1' to clear) + Subregion 23 in region n (write '1' to clear) 23 23 @@ -37284,7 +37219,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR24 - Subregion 24 in region 0 (write '1' to clear) + Subregion 24 in region n (write '1' to clear) 24 24 @@ -37302,7 +37237,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR25 - Subregion 25 in region 0 (write '1' to clear) + Subregion 25 in region n (write '1' to clear) 25 25 @@ -37320,7 +37255,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR26 - Subregion 26 in region 0 (write '1' to clear) + Subregion 26 in region n (write '1' to clear) 26 26 @@ -37338,7 +37273,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR27 - Subregion 27 in region 0 (write '1' to clear) + Subregion 27 in region n (write '1' to clear) 27 27 @@ -37356,7 +37291,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR28 - Subregion 28 in region 0 (write '1' to clear) + Subregion 28 in region n (write '1' to clear) 28 28 @@ -37374,7 +37309,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR29 - Subregion 29 in region 0 (write '1' to clear) + Subregion 29 in region n (write '1' to clear) 29 29 @@ -37392,7 +37327,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR30 - Subregion 30 in region 0 (write '1' to clear) + Subregion 30 in region n (write '1' to clear) 30 30 @@ -37410,7 +37345,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SR31 - Subregion 31 in region 0 (write '1' to clear) + Subregion 31 in region n (write '1' to clear) 31 31 @@ -38319,14 +38254,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 4 - 16 + 0x010 REGION[%s] Unspecified MWU_REGION 0x600 START - Description cluster[0]: Start address for region 0 + Description cluster[n]: Start address for region n 0x000 read-write 0x00000000 @@ -38341,7 +38276,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Description cluster[0]: End address of region 0 + Description cluster[n]: End address of region n 0x004 read-write @@ -38356,14 +38291,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 2 - 16 + 0x010 PREGION[%s] Unspecified MWU_PREGION 0x6C0 START - Description cluster[0]: Reserved for future use + Description cluster[n]: Reserved for future use 0x000 read-only @@ -38377,7 +38312,7 @@ POSSIBILITY OF SUCH DAMAGE.\n END - Description cluster[0]: Reserved for future use + Description cluster[n]: Reserved for future use 0x004 read-only @@ -38391,7 +38326,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SUBS - Description cluster[0]: Subregions of region 0 + Description cluster[n]: Subregions of region n 0x008 read-write 0x00000000 @@ -38980,9 +38915,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PWM1 Pulse width modulation unit 1 - PWM 0x40021000 - 32 PWM1 33 @@ -38991,20 +38924,26 @@ POSSIBILITY OF SUCH DAMAGE.\n PWM2 Pulse width modulation unit 2 - PWM 0x40022000 - 32 PWM2 34 + + SPI2 + Serial Peripheral Interface 2 + 0x40023000 + + SPIM2_SPIS2_SPI2 + 35 + + SPIM2 Serial Peripheral Interface Master with EasyDMA 2 - SPIM 0x40023000 - 32 + SPI2 SPIM2_SPIS2_SPI2 35 @@ -39013,22 +38952,8 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIS2 SPI Slave 2 - SPIS 0x40023000 - 32 - SPIM2 - - SPIM2_SPIS2_SPI2 - 35 - - - - SPI2 - Serial Peripheral Interface 2 - SPI - 0x40023000 - 32 - SPIM2 + SPI2 SPIM2_SPIS2_SPI2 35 @@ -39037,9 +38962,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RTC2 Real time counter 2 - RTC 0x40024000 - 32 RTC2 36 @@ -39048,9 +38971,7 @@ POSSIBILITY OF SUCH DAMAGE.\n I2S Inter-IC Sound - I2S 0x40025000 - 32 0 0x1000 @@ -39060,6 +38981,8 @@ POSSIBILITY OF SUCH DAMAGE.\n I2S 37 + I2S + 0x20 TASKS_START @@ -39089,7 +39012,8 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_RXPTRUPD - The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0x104 read-write @@ -39115,7 +39039,8 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_TXPTRUPD - The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0x114 read-write @@ -39196,7 +39121,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXPTRUPD - Write '1' to Enable interrupt for RXPTRUPD event + Write '1' to enable interrupt for RXPTRUPD event 1 1 @@ -39223,7 +39148,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Enable interrupt for STOPPED event + Write '1' to enable interrupt for STOPPED event 2 2 @@ -39250,7 +39175,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXPTRUPD - Write '1' to Enable interrupt for TXPTRUPD event + Write '1' to enable interrupt for TXPTRUPD event 5 5 @@ -39285,7 +39210,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RXPTRUPD - Write '1' to Disable interrupt for RXPTRUPD event + Write '1' to disable interrupt for RXPTRUPD event 1 1 @@ -39312,7 +39237,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STOPPED - Write '1' to Disable interrupt for STOPPED event + Write '1' to disable interrupt for STOPPED event 2 2 @@ -39339,7 +39264,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXPTRUPD - Write '1' to Disable interrupt for TXPTRUPD event + Write '1' to disable interrupt for TXPTRUPD event 5 5 @@ -40063,9 +39988,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FPU FPU - FPU 0x40026000 - 32 0 0x1000 @@ -40075,6 +39998,8 @@ POSSIBILITY OF SUCH DAMAGE.\n FPU 38 + FPU + 0x20 UNUSED @@ -40087,10 +40012,8 @@ POSSIBILITY OF SUCH DAMAGE.\n USBD - Universal Serial Bus device - USBD + Universal serial bus device 0x40027000 - 32 0 0x1000 @@ -40100,12 +40023,14 @@ POSSIBILITY OF SUCH DAMAGE.\n USBD 39 + USBD + 0x20 - 8 - 4 + 0x8 + 0x4 TASKS_STARTEPIN[%s] - Description collection[0]: Captures the EPIN[0].PTR and EPIN[0].MAXCNT registers values, and enables endpoint IN 0 to respond to traffic from host + Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host 0x004 write-only @@ -40118,7 +40043,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_STARTISOIN - Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on iso endpoint + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint 0x024 write-only @@ -40130,10 +40055,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 TASKS_STARTEPOUT[%s] - Description collection[0]: Captures the EPOUT[0].PTR and EPOUT[0].MAXCNT registers values, and enables endpoint 0 to respond to traffic from host + Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host 0x028 write-only @@ -40146,7 +40071,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_STARTISOOUT - Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on iso endpoint + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint 0x048 write-only @@ -40185,7 +40110,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_EP0STALL - STALLs data and status stage on control endpoint 0 + Stalls data and status stage on control endpoint 0 0x054 write-only @@ -40198,7 +40123,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_DPDMDRIVE - Forces D+ and D-lines to the state defined in the DPDMVALUE register + Forces D+ and D- lines into the state defined in the DPDMVALUE register 0x058 write-only @@ -40211,7 +40136,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_DPDMNODRIVE - Stops forcing D+ and D- lines to any state (USB engine takes control) + Stops forcing D+ and D- lines into any state (USB engine takes control) 0x05C write-only @@ -40224,7 +40149,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_USBRESET - Signals that a USB reset condition has been detected on the USB lines + Signals that a USB reset condition has been detected on USB lines 0x100 read-write @@ -40249,10 +40174,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 EVENTS_ENDEPIN[%s] - Description collection[0]: The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software. + Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0x108 read-write @@ -40290,10 +40215,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 EVENTS_ENDEPOUT[%s] - Description collection[0]: The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software. + Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0x130 read-write @@ -40319,7 +40244,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SOF - Signals that a SOF (start of frame) condition has been detected on the USB lines + Signals that a SOF (start of frame) condition has been detected on USB lines 0x154 read-write @@ -40332,7 +40257,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_USBEVENT - An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. 0x158 read-write @@ -40933,7 +40858,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBRESET - Write '1' to Enable interrupt for USBRESET event + Write '1' to enable interrupt for USBRESET event 0 0 @@ -40960,7 +40885,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Enable interrupt for STARTED event + Write '1' to enable interrupt for STARTED event 1 1 @@ -40987,7 +40912,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN0 - Write '1' to Enable interrupt for ENDEPIN[0] event + Write '1' to enable interrupt for ENDEPIN[0] event 2 2 @@ -41014,7 +40939,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN1 - Write '1' to Enable interrupt for ENDEPIN[1] event + Write '1' to enable interrupt for ENDEPIN[1] event 3 3 @@ -41041,7 +40966,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN2 - Write '1' to Enable interrupt for ENDEPIN[2] event + Write '1' to enable interrupt for ENDEPIN[2] event 4 4 @@ -41068,7 +40993,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN3 - Write '1' to Enable interrupt for ENDEPIN[3] event + Write '1' to enable interrupt for ENDEPIN[3] event 5 5 @@ -41095,7 +41020,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN4 - Write '1' to Enable interrupt for ENDEPIN[4] event + Write '1' to enable interrupt for ENDEPIN[4] event 6 6 @@ -41122,7 +41047,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN5 - Write '1' to Enable interrupt for ENDEPIN[5] event + Write '1' to enable interrupt for ENDEPIN[5] event 7 7 @@ -41149,7 +41074,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN6 - Write '1' to Enable interrupt for ENDEPIN[6] event + Write '1' to enable interrupt for ENDEPIN[6] event 8 8 @@ -41176,7 +41101,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN7 - Write '1' to Enable interrupt for ENDEPIN[7] event + Write '1' to enable interrupt for ENDEPIN[7] event 9 9 @@ -41203,7 +41128,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EP0DATADONE - Write '1' to Enable interrupt for EP0DATADONE event + Write '1' to enable interrupt for EP0DATADONE event 10 10 @@ -41230,7 +41155,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDISOIN - Write '1' to Enable interrupt for ENDISOIN event + Write '1' to enable interrupt for ENDISOIN event 11 11 @@ -41257,7 +41182,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT0 - Write '1' to Enable interrupt for ENDEPOUT[0] event + Write '1' to enable interrupt for ENDEPOUT[0] event 12 12 @@ -41284,7 +41209,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT1 - Write '1' to Enable interrupt for ENDEPOUT[1] event + Write '1' to enable interrupt for ENDEPOUT[1] event 13 13 @@ -41311,7 +41236,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT2 - Write '1' to Enable interrupt for ENDEPOUT[2] event + Write '1' to enable interrupt for ENDEPOUT[2] event 14 14 @@ -41338,7 +41263,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT3 - Write '1' to Enable interrupt for ENDEPOUT[3] event + Write '1' to enable interrupt for ENDEPOUT[3] event 15 15 @@ -41365,7 +41290,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT4 - Write '1' to Enable interrupt for ENDEPOUT[4] event + Write '1' to enable interrupt for ENDEPOUT[4] event 16 16 @@ -41392,7 +41317,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT5 - Write '1' to Enable interrupt for ENDEPOUT[5] event + Write '1' to enable interrupt for ENDEPOUT[5] event 17 17 @@ -41419,7 +41344,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT6 - Write '1' to Enable interrupt for ENDEPOUT[6] event + Write '1' to enable interrupt for ENDEPOUT[6] event 18 18 @@ -41446,7 +41371,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT7 - Write '1' to Enable interrupt for ENDEPOUT[7] event + Write '1' to enable interrupt for ENDEPOUT[7] event 19 19 @@ -41473,7 +41398,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDISOOUT - Write '1' to Enable interrupt for ENDISOOUT event + Write '1' to enable interrupt for ENDISOOUT event 20 20 @@ -41500,7 +41425,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SOF - Write '1' to Enable interrupt for SOF event + Write '1' to enable interrupt for SOF event 21 21 @@ -41527,7 +41452,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBEVENT - Write '1' to Enable interrupt for USBEVENT event + Write '1' to enable interrupt for USBEVENT event 22 22 @@ -41554,7 +41479,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EP0SETUP - Write '1' to Enable interrupt for EP0SETUP event + Write '1' to enable interrupt for EP0SETUP event 23 23 @@ -41581,7 +41506,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPDATA - Write '1' to Enable interrupt for EPDATA event + Write '1' to enable interrupt for EPDATA event 24 24 @@ -41616,7 +41541,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBRESET - Write '1' to Disable interrupt for USBRESET event + Write '1' to disable interrupt for USBRESET event 0 0 @@ -41643,7 +41568,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STARTED - Write '1' to Disable interrupt for STARTED event + Write '1' to disable interrupt for STARTED event 1 1 @@ -41670,7 +41595,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN0 - Write '1' to Disable interrupt for ENDEPIN[0] event + Write '1' to disable interrupt for ENDEPIN[0] event 2 2 @@ -41697,7 +41622,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN1 - Write '1' to Disable interrupt for ENDEPIN[1] event + Write '1' to disable interrupt for ENDEPIN[1] event 3 3 @@ -41724,7 +41649,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN2 - Write '1' to Disable interrupt for ENDEPIN[2] event + Write '1' to disable interrupt for ENDEPIN[2] event 4 4 @@ -41751,7 +41676,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN3 - Write '1' to Disable interrupt for ENDEPIN[3] event + Write '1' to disable interrupt for ENDEPIN[3] event 5 5 @@ -41778,7 +41703,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN4 - Write '1' to Disable interrupt for ENDEPIN[4] event + Write '1' to disable interrupt for ENDEPIN[4] event 6 6 @@ -41805,7 +41730,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN5 - Write '1' to Disable interrupt for ENDEPIN[5] event + Write '1' to disable interrupt for ENDEPIN[5] event 7 7 @@ -41832,7 +41757,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN6 - Write '1' to Disable interrupt for ENDEPIN[6] event + Write '1' to disable interrupt for ENDEPIN[6] event 8 8 @@ -41859,7 +41784,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPIN7 - Write '1' to Disable interrupt for ENDEPIN[7] event + Write '1' to disable interrupt for ENDEPIN[7] event 9 9 @@ -41886,7 +41811,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EP0DATADONE - Write '1' to Disable interrupt for EP0DATADONE event + Write '1' to disable interrupt for EP0DATADONE event 10 10 @@ -41913,7 +41838,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDISOIN - Write '1' to Disable interrupt for ENDISOIN event + Write '1' to disable interrupt for ENDISOIN event 11 11 @@ -41940,7 +41865,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT0 - Write '1' to Disable interrupt for ENDEPOUT[0] event + Write '1' to disable interrupt for ENDEPOUT[0] event 12 12 @@ -41967,7 +41892,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT1 - Write '1' to Disable interrupt for ENDEPOUT[1] event + Write '1' to disable interrupt for ENDEPOUT[1] event 13 13 @@ -41994,7 +41919,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT2 - Write '1' to Disable interrupt for ENDEPOUT[2] event + Write '1' to disable interrupt for ENDEPOUT[2] event 14 14 @@ -42021,7 +41946,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT3 - Write '1' to Disable interrupt for ENDEPOUT[3] event + Write '1' to disable interrupt for ENDEPOUT[3] event 15 15 @@ -42048,7 +41973,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT4 - Write '1' to Disable interrupt for ENDEPOUT[4] event + Write '1' to disable interrupt for ENDEPOUT[4] event 16 16 @@ -42075,7 +42000,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT5 - Write '1' to Disable interrupt for ENDEPOUT[5] event + Write '1' to disable interrupt for ENDEPOUT[5] event 17 17 @@ -42102,7 +42027,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT6 - Write '1' to Disable interrupt for ENDEPOUT[6] event + Write '1' to disable interrupt for ENDEPOUT[6] event 18 18 @@ -42129,7 +42054,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDEPOUT7 - Write '1' to Disable interrupt for ENDEPOUT[7] event + Write '1' to disable interrupt for ENDEPOUT[7] event 19 19 @@ -42156,7 +42081,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ENDISOOUT - Write '1' to Disable interrupt for ENDISOOUT event + Write '1' to disable interrupt for ENDISOOUT event 20 20 @@ -42183,7 +42108,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SOF - Write '1' to Disable interrupt for SOF event + Write '1' to disable interrupt for SOF event 21 21 @@ -42210,7 +42135,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBEVENT - Write '1' to Disable interrupt for USBEVENT event + Write '1' to disable interrupt for USBEVENT event 22 22 @@ -42237,7 +42162,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EP0SETUP - Write '1' to Disable interrupt for EP0SETUP event + Write '1' to disable interrupt for EP0SETUP event 23 23 @@ -42264,7 +42189,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPDATA - Write '1' to Disable interrupt for EPDATA event + Write '1' to disable interrupt for EPDATA event 24 24 @@ -42293,7 +42218,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTCAUSE - Details on event that caused the USBEVENT event + Details on what caused the USBEVENT event 0x400 read-write oneToClear @@ -42318,7 +42243,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SUSPEND - Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear. + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. 8 8 @@ -42336,7 +42261,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RESUME - Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear. + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. 9 9 @@ -42396,10 +42321,10 @@ POSSIBILITY OF SUCH DAMAGE.\n USBD_HALTED 0x420 - 8 - 4 + 0x8 + 0x4 EPIN[%s] - Description collection[0]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0x000 read-only @@ -42424,10 +42349,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 8 - 4 + 0x8 + 0x4 EPOUT[%s] - Description collection[0]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0x024 read-only @@ -42461,7 +42386,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN0 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 0 0 @@ -42479,7 +42404,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN1 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 1 1 @@ -42497,7 +42422,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN2 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 2 2 @@ -42515,7 +42440,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN3 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 3 3 @@ -42533,7 +42458,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN4 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 4 4 @@ -42551,7 +42476,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN5 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 5 5 @@ -42569,7 +42494,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN6 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 6 6 @@ -42587,7 +42512,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN7 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 7 7 @@ -42605,7 +42530,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPIN8 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 8 8 @@ -42623,7 +42548,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT0 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 16 16 @@ -42641,7 +42566,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT1 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 17 17 @@ -42659,7 +42584,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT2 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 18 18 @@ -42677,7 +42602,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT3 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 19 19 @@ -42695,7 +42620,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT4 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 20 20 @@ -42713,7 +42638,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT5 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 21 21 @@ -42731,7 +42656,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT6 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 22 22 @@ -42749,7 +42674,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT7 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 23 23 @@ -42767,7 +42692,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EPOUT8 - Endpoint's EasyDMA registers captured state. Write '1' to clear. + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 24 24 @@ -43147,7 +43072,7 @@ POSSIBILITY OF SUCH DAMAGE.\n BREQUEST - SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values. + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. 0 7 @@ -43306,16 +43231,16 @@ POSSIBILITY OF SUCH DAMAGE.\n USBD_SIZE 0x4A0 - 8 - 4 + 0x8 + 0x4 EPOUT[%s] - Description collection[0]: Amount of bytes received last in the data stage of this OUT endpoint + Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint 0x000 read-write SIZE - Amount of bytes received last in the data stage of this OUT endpoint + Number of bytes received last in the data stage of this OUT endpoint 0 6 @@ -43323,14 +43248,14 @@ POSSIBILITY OF SUCH DAMAGE.\n ISOOUT - Amount of bytes received last on this iso OUT data endpoint + Number of bytes received last on this ISO OUT data endpoint 0x020 read-only 0x00010000 SIZE - Amount of bytes received last on this iso OUT data endpoint + Number of bytes received last on this ISO OUT data endpoint 0 9 @@ -43409,19 +43334,19 @@ POSSIBILITY OF SUCH DAMAGE.\n DPDMVALUE - State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). 0x508 read-write STATE - State at which the DPDMDRIVE task will force D+ and D- + State D+ and D- lines will be forced into by the DPDMDRIVE task 0 4 Resume - D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state) + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) 1 @@ -43440,7 +43365,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DTOGGLE - Data toggle control and status. + Data toggle control and status 0x50C read-write 0x00000100 @@ -43647,18 +43572,18 @@ POSSIBILITY OF SUCH DAMAGE.\n ISOIN - Enable iso IN endpoint + Enable ISO IN endpoint 8 8 Disable - Disable iso IN endpoint 8 + Disable ISO IN endpoint 8 0 Enable - Enable iso IN endpoint 8 + Enable ISO IN endpoint 8 1 @@ -43818,18 +43743,18 @@ POSSIBILITY OF SUCH DAMAGE.\n ISOOUT - Enable iso OUT endpoint 8 + Enable ISO OUT endpoint 8 8 8 Disable - Disable iso OUT endpoint 8 + Disable ISO OUT endpoint 8 0 Enable - Enable iso OUT endpoint 8 + Enable ISO OUT endpoint 8 1 @@ -43930,7 +43855,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LOWPOWER - Controls USBD peripheral low-power mode during USB suspend + Controls USBD peripheral low power mode during USB suspend 0x52C read-write 0x00000000 @@ -43983,14 +43908,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 8 - 20 + 0x014 EPIN[%s] Unspecified USBD_EPIN 0x600 PTR - Description cluster[0]: Data pointer + Description cluster[n]: Data pointer 0x000 read-write @@ -44004,7 +43929,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXCNT - Description cluster[0]: Maximum number of bytes to transfer + Description cluster[n]: Maximum number of bytes to transfer 0x004 read-write @@ -44018,7 +43943,7 @@ POSSIBILITY OF SUCH DAMAGE.\n AMOUNT - Description cluster[0]: Number of bytes transferred in the last transaction + Description cluster[n]: Number of bytes transferred in the last transaction 0x008 read-only @@ -44081,14 +44006,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 8 - 20 + 0x014 EPOUT[%s] Unspecified USBD_EPOUT 0x700 PTR - Description cluster[0]: Data pointer + Description cluster[n]: Data pointer 0x000 read-write @@ -44102,7 +44027,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXCNT - Description cluster[0]: Maximum number of bytes to transfer + Description cluster[n]: Maximum number of bytes to transfer 0x004 read-write @@ -44116,7 +44041,7 @@ POSSIBILITY OF SUCH DAMAGE.\n AMOUNT - Description cluster[0]: Number of bytes transferred in the last transaction + Description cluster[n]: Number of bytes transferred in the last transaction 0x008 read-only @@ -44182,9 +44107,7 @@ POSSIBILITY OF SUCH DAMAGE.\n UARTE1 UART with EasyDMA 1 - UARTE 0x40028000 - 32 UARTE1 40 @@ -44193,9 +44116,7 @@ POSSIBILITY OF SUCH DAMAGE.\n QSPI External flash interface - QSPI 0x40029000 - 32 0 0x1000 @@ -44205,6 +44126,8 @@ POSSIBILITY OF SUCH DAMAGE.\n QSPI 41 + QSPI + 0x20 TASKS_ACTIVATE @@ -44318,7 +44241,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Enable interrupt for READY event + Write '1' to enable interrupt for READY event 0 0 @@ -44353,7 +44276,7 @@ POSSIBILITY OF SUCH DAMAGE.\n READY - Write '1' to Disable interrupt for READY event + Write '1' to disable interrupt for READY event 0 0 @@ -45380,9 +45303,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PWM3 Pulse width modulation unit 3 - PWM 0x4002D000 - 32 PWM3 45 @@ -45391,9 +45312,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SPIM3 Serial Peripheral Interface Master with EasyDMA 3 - SPIM 0x4002F000 - 32 SPIM3 47 @@ -45402,15 +45321,15 @@ POSSIBILITY OF SUCH DAMAGE.\n P0 GPIO Port 1 - GPIO 0x50000000 - 32 GPIO 0 0x1000 registers + GPIO + 0x20 OUT @@ -51267,10 +51186,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - 32 - 4 + 0x20 + 0x4 PIN_CNF[%s] - Description collection[0]: Configuration of GPIO pins + Description collection[n]: Configuration of GPIO pins 0x700 read-write 0x00000002 @@ -51412,17 +51331,192 @@ POSSIBILITY OF SUCH DAMAGE.\n P1 GPIO Port 2 - GPIO 0x50000300 - 32 P0 + + CC_HOST_RGF + CRYPTOCELL HOST_RGF interface + 0x5002A000 + + 0 + 0x2000 + registers + + CC_HOST_RGF + 0x20 + + + HOST_CRYPTOKEY_SEL + AES hardware key select + 0x1A38 + read-write + 0x00000000 + + + HOST_CRYPTOKEY_SEL + Select the source of the HW key that is used by the AES engine + 0 + 1 + + + K_DR + Use device root key K_DR from CRYPTOCELL AO power domain + 0 + + + K_PRTL + Use hard-coded RTL key K_PRTL + 1 + + + Session + Use provided session key + 2 + + + + + + + HOST_IOT_KPRTL_LOCK + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A4C + read-write + 0x00000000 + + + HOST_IOT_KPRTL_LOCK + This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0 + 0 + + + Disabled + K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + 0 + + + Enabled + K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + 1 + + + + + + + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + 0x1A50 + read-write + 0x00000000 + + + HOST_IOT_KDR0 + Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain + 0 + 31 + + + + + HOST_IOT_KDR1 + This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A54 + write-only + 0x00000000 + + + HOST_IOT_KDR1 + K_DR bits 63:32 + 0 + 31 + + + + + HOST_IOT_KDR2 + This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A58 + write-only + 0x00000000 + + + HOST_IOT_KDR2 + K_DR bits 95:64 + 0 + 31 + + + + + HOST_IOT_KDR3 + This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A5C + write-only + 0x00000000 + + + HOST_IOT_KDR3 + K_DR bits 127:96 + 0 + 31 + + + + + HOST_IOT_LCS + Controls lifecycle state (LCS) for CRYPTOCELL subsystem + 0x1A60 + read-write + 0x00000002 + + + LCS + Lifecycle state value. This field is write-once per reset. + 0 + 2 + + + Debug + CC310 operates in debug mode + 0 + + + Secure + CC310 operates in secure mode + 2 + + + + + LCS_IS_VALID + This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset + 8 + 8 + + + Invalid + A valid LCS is not yet retained in the CRYPTOCELL AO power domain + 0 + + + Valid + A valid LCS is successfully retained in the CRYPTOCELL AO power domain + 1 + + + + + + + CRYPTOCELL ARM TrustZone CryptoCell register interface - CRYPTOCELL 0x5002A000 - 32 + CC_HOST_RGF 0 0x2000 @@ -51432,10 +51526,12 @@ POSSIBILITY OF SUCH DAMAGE.\n CRYPTOCELL 42 + CRYPTOCELL + 0x20 ENABLE - Control power and clock for CRYPTOCELL subsystem + Enable CRYPTOCELL subsystem 0x500 read-write 0x00000000 diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h index 7d85a902d..6d1990bb1 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -76,21 +76,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for END event */ +/* Bit 0 : Write '1' to enable interrupt for END event */ #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -100,21 +100,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for END event */ +/* Bit 0 : Write '1' to disable interrupt for END event */ #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -170,33 +170,33 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access control lists */ /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster[0]: Configure the word-aligned start address of region 0 to protect */ +/* Description: Description cluster[n]: Configure the word-aligned start address of region n to protect */ -/* Bits 31..0 : Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary. */ +/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster[0]: Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect. */ +/* Description: Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ -/* Bits 31..0 : Size of flash region 0 in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ +/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ /* Register: ACL_ACL_PERM */ -/* Description: Description cluster[0]: Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE */ +/* Description: Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ -/* Bit 2 : Configure read permissions for region 0. Write '0' has no effect. */ +/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region 0 */ -#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region 0 */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ -/* Bit 1 : Configure write and erase permissions for region 0. Write '0' has no effect. */ +/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region 0 */ -#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region 0 */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ /* Peripheral: CCM */ @@ -245,7 +245,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ /* Register: CCM_EVENTS_ERROR */ -/* Description: Deprecated register - CCM error event */ +/* Description: Deprecated register - CCM error event */ /* Bit 0 : */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ @@ -263,21 +263,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ +/* Bit 2 : Write '1' to enable interrupt for ERROR event */ #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -287,21 +287,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ +/* Bit 2 : Write '1' to disable interrupt for ERROR event */ #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -373,7 +373,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ @@ -396,39 +397,105 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ +/* Peripheral: CC_HOST_RGF */ +/* Description: CRYPTOCELL HOST_RGF interface */ + +/* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */ +/* Description: AES hardware key select */ + +/* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ + +/* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ +/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ +/* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ + +/* Bits 31..0 : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR1 */ +/* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 63:32 */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR2 */ +/* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 95:64 */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR3 */ +/* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 127:96 */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_LCS */ +/* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ + +/* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< A valid LCS is not yet retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< A valid LCS is successfully retained in the CRYPTOCELL AO power domain */ + +/* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */ + + /* Peripheral: CLOCK */ /* Description: Clock control */ /* Register: CLOCK_TASKS_HFCLKSTART */ -/* Description: Start HFCLK crystal oscillator */ +/* Description: Start HFXO crystal oscillator */ /* Bit 0 : */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ /* Register: CLOCK_TASKS_HFCLKSTOP */ -/* Description: Stop HFCLK crystal oscillator */ +/* Description: Stop HFXO crystal oscillator */ /* Bit 0 : */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ /* Register: CLOCK_TASKS_LFCLKSTART */ -/* Description: Start LFCLK source */ +/* Description: Start LFCLK */ /* Bit 0 : */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ /* Register: CLOCK_TASKS_LFCLKSTOP */ -/* Description: Stop LFCLK source */ +/* Description: Stop LFCLK */ /* Bit 0 : */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ /* Register: CLOCK_TASKS_CAL */ -/* Description: Start calibration of LFRC or LFULP oscillator */ +/* Description: Start calibration of LFRC */ /* Bit 0 : */ #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ @@ -449,7 +516,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ /* Register: CLOCK_EVENTS_HFCLKSTARTED */ -/* Description: HFCLK oscillator started */ +/* Description: HFXO crystal oscillator started */ /* Bit 0 : */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ @@ -463,7 +530,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ /* Register: CLOCK_EVENTS_DONE */ -/* Description: Calibration of LFCLK RC oscillator complete event */ +/* Description: Calibration of LFRC completed */ /* Bit 0 : */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ @@ -493,42 +560,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ -/* Bit 11 : Write '1' to Enable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to enable interrupt for CTSTOPPED event */ #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to Enable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to enable interrupt for CTSTARTED event */ #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ +/* Bit 4 : Write '1' to enable interrupt for CTTO event */ #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for DONE event */ +/* Bit 3 : Write '1' to enable interrupt for DONE event */ #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -538,42 +605,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 11 : Write '1' to Disable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to disable interrupt for CTSTOPPED event */ #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to Disable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to disable interrupt for CTSTARTED event */ #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ +/* Bit 4 : Write '1' to disable interrupt for CTTO event */ #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for DONE event */ +/* Bit 3 : Write '1' to disable interrupt for DONE event */ #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -625,9 +692,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Source of LFCLK */ #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ -#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ /* Register: CLOCK_LFCLKSRCCOPY */ /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ @@ -635,9 +702,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ -#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK */ @@ -657,9 +724,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ -#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ /* Register: CLOCK_HFXODEBOUNCE */ /* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */ @@ -678,7 +745,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ /* Register: CLOCK_TRACECONFIG */ -/* Description: Clocking options for the Trace Port debug interface */ +/* Description: Clocking options for the trace port debug interface */ /* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */ #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ @@ -687,13 +754,13 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */ #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */ -/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ +/* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */ #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */ /* Register: CLOCK_LFRCMODE */ /* Description: LFRC mode configuration */ @@ -826,28 +893,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for CROSS event */ #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for UP event */ #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for DOWN event */ #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for READY event */ #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -857,28 +924,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for CROSS event */ #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for UP event */ #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for DOWN event */ #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for READY event */ #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -986,7 +1053,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: ARM TrustZone CryptoCell register interface */ /* Register: CRYPTOCELL_ENABLE */ -/* Description: Control power and clock for CRYPTOCELL subsystem */ +/* Description: Enable CRYPTOCELL subsystem */ /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */ #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ @@ -1029,14 +1096,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_INTENSET */ /* Description: Enable interrupt */ -/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to enable interrupt for ENDECB event */ #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1046,14 +1113,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to disable interrupt for ENDECB event */ #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1072,14 +1139,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Event Generator Unit 0 */ /* Register: EGU_TASKS_TRIGGER */ -/* Description: Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event */ +/* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ /* Bit 0 : */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ /* Register: EGU_EVENTS_TRIGGERED */ -/* Description: Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task */ +/* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ /* Bit 0 : */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ @@ -1187,112 +1254,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1302,112 +1369,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1433,23 +1500,23 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ /* Register: FICR_DEVICEID */ -/* Description: Description collection[0]: Device identifier */ +/* Description: Description collection[n]: Device identifier */ /* Bits 31..0 : 64 bit unique device identifier */ #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ /* Register: FICR_ER */ -/* Description: Description collection[0]: Encryption root, word 0 */ +/* Description: Description collection[n]: Encryption root, word n */ -/* Bits 31..0 : Encryption root, word 0 */ +/* Bits 31..0 : Encryption root, word n */ #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ /* Register: FICR_IR */ -/* Description: Description collection[0]: Identity Root, word 0 */ +/* Description: Description collection[n]: Identity Root, word n */ -/* Bits 31..0 : Identity Root, word 0 */ +/* Bits 31..0 : Identity Root, word n */ #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ @@ -1463,7 +1530,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ /* Register: FICR_DEVICEADDR */ -/* Description: Description collection[0]: Device address 0 */ +/* Description: Description collection[n]: Device address n */ /* Bits 31..0 : 48 bit device address */ #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ @@ -1529,9 +1596,9 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_PRODTEST */ -/* Description: Description collection[0]: Production test signature 0 */ +/* Description: Description collection[n]: Production test signature n */ -/* Bits 31..0 : Production test signature 0 */ +/* Bits 31..0 : Production test signature n */ #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ #define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */ #define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */ @@ -1793,28 +1860,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: GPIO Tasks and Events */ /* Register: GPIOTE_TASKS_OUT */ -/* Description: Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ /* Bit 0 : */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ /* Register: GPIOTE_TASKS_SET */ -/* Description: Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ /* Bit 0 : */ #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ /* Register: GPIOTE_TASKS_CLR */ -/* Description: Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ /* Bit 0 : */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ /* Register: GPIOTE_EVENTS_IN */ -/* Description: Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL */ +/* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ /* Bit 0 : */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ @@ -1830,63 +1897,63 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIOTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 31 : Write '1' to Enable interrupt for PORT event */ +/* Bit 31 : Write '1' to enable interrupt for PORT event */ #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to enable interrupt for IN[7] event */ #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to enable interrupt for IN[6] event */ #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to enable interrupt for IN[5] event */ #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to enable interrupt for IN[4] event */ #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to enable interrupt for IN[3] event */ #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to enable interrupt for IN[2] event */ #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to enable interrupt for IN[1] event */ #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to enable interrupt for IN[0] event */ #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -1896,63 +1963,63 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIOTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 31 : Write '1' to Disable interrupt for PORT event */ +/* Bit 31 : Write '1' to disable interrupt for PORT event */ #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to disable interrupt for IN[7] event */ #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to disable interrupt for IN[6] event */ #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to disable interrupt for IN[5] event */ #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to disable interrupt for IN[4] event */ #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to disable interrupt for IN[3] event */ #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to disable interrupt for IN[2] event */ #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to disable interrupt for IN[1] event */ #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to disable interrupt for IN[0] event */ #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -1960,7 +2027,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -2010,7 +2077,8 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ /* Register: I2S_EVENTS_RXPTRUPD */ -/* Description: The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ +/* Description: The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ /* Bit 0 : */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ @@ -2024,7 +2092,8 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ /* Register: I2S_EVENTS_TXPTRUPD */ -/* Description: The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ +/* Description: The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ /* Bit 0 : */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ @@ -2054,21 +2123,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENSET */ /* Description: Enable interrupt */ -/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to enable interrupt for TXPTRUPD event */ #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to enable interrupt for STOPPED event */ #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to enable interrupt for RXPTRUPD event */ #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2078,21 +2147,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to disable interrupt for TXPTRUPD event */ #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to disable interrupt for STOPPED event */ #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to disable interrupt for RXPTRUPD event */ #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2418,28 +2487,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for CROSS event */ #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for UP event */ #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for DOWN event */ #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for READY event */ #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2449,28 +2518,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for CROSS event */ #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for UP event */ #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for DOWN event */ #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for READY event */ #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2566,28 +2635,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Memory Watch Unit */ /* Register: MWU_EVENTS_REGION_WA */ -/* Description: Description cluster[0]: Write access to region 0 detected */ +/* Description: Description cluster[n]: Write access to region n detected */ /* Bit 0 : */ #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */ /* Register: MWU_EVENTS_REGION_RA */ -/* Description: Description cluster[0]: Read access to region 0 detected */ +/* Description: Description cluster[n]: Read access to region n detected */ /* Bit 0 : */ #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */ /* Register: MWU_EVENTS_PREGION_WA */ -/* Description: Description cluster[0]: Write access to peripheral region 0 detected */ +/* Description: Description cluster[n]: Write access to peripheral region n detected */ /* Bit 0 : */ #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */ /* Register: MWU_EVENTS_PREGION_RA */ -/* Description: Description cluster[0]: Read access to peripheral region 0 detected */ +/* Description: Description cluster[n]: Read access to peripheral region n detected */ /* Bit 0 : */ #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ @@ -2671,84 +2740,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable interrupt for PREGION[1].RA event */ #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable interrupt for PREGION[1].WA event */ #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable interrupt for PREGION[0].RA event */ #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable interrupt for PREGION[0].WA event */ #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable interrupt for REGION[3].RA event */ #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable interrupt for REGION[3].WA event */ #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */ #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */ #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable interrupt for REGION[1].RA event */ #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */ #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable interrupt for REGION[0].RA event */ #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable interrupt for REGION[0].WA event */ #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2758,84 +2827,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable interrupt for PREGION[1].RA event */ #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable interrupt for PREGION[1].WA event */ #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable interrupt for PREGION[0].RA event */ #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable interrupt for PREGION[0].WA event */ #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable interrupt for REGION[3].RA event */ #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable interrupt for REGION[3].WA event */ #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */ #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */ #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable interrupt for REGION[1].RA event */ #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */ #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable interrupt for REGION[0].RA event */ #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable interrupt for REGION[0].WA event */ #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2920,84 +2989,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_NMIENSET */ /* Description: Enable non-maskable interrupt */ -/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */ #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */ #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */ #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */ #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */ #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */ #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */ #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */ #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */ #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */ #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */ #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */ #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3007,84 +3076,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_NMIENCLR */ /* Description: Disable non-maskable interrupt */ -/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */ #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */ #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */ #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */ #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */ #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */ #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */ #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */ #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */ #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */ #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */ #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */ #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3092,390 +3161,390 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_PERREGION_SUBSTATWA */ -/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ -/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ /* Register: MWU_PERREGION_SUBSTATRA */ -/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ -/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ @@ -3731,35 +3800,35 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ /* Register: MWU_REGION_START */ -/* Description: Description cluster[0]: Start address for region 0 */ +/* Description: Description cluster[n]: Start address for region n */ /* Bits 31..0 : Start address for region */ #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_REGION_END */ -/* Description: Description cluster[0]: End address of region 0 */ +/* Description: Description cluster[n]: End address of region n */ /* Bits 31..0 : End address of region. */ #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_START */ -/* Description: Description cluster[0]: Reserved for future use */ +/* Description: Description cluster[n]: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_PREGION_END */ -/* Description: Description cluster[0]: Reserved for future use */ +/* Description: Description cluster[n]: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_SUBS */ -/* Description: Description cluster[0]: Subregions of region 0 */ +/* Description: Description cluster[n]: Subregions of region n */ /* Bit 31 : Include or exclude subregion 31 in region */ #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -4228,105 +4297,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ +/* Bit 20 : Write '1' to enable interrupt for STARTED event */ #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to enable interrupt for SELECTED event */ #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to enable interrupt for COLLISION event */ #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to enable interrupt for AUTOCOLRESSTARTED event */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to enable interrupt for ENDTX event */ #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to enable interrupt for ENDRX event */ #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to enable interrupt for RXERROR event */ #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ +/* Bit 7 : Write '1' to enable interrupt for ERROR event */ #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to enable interrupt for RXFRAMEEND event */ #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to enable interrupt for RXFRAMESTART event */ #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to enable interrupt for TXFRAMEEND event */ #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to enable interrupt for TXFRAMESTART event */ #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */ #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to enable interrupt for FIELDDETECTED event */ #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for READY event */ #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4336,105 +4405,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ +/* Bit 20 : Write '1' to disable interrupt for STARTED event */ #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to disable interrupt for SELECTED event */ #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to disable interrupt for COLLISION event */ #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to disable interrupt for AUTOCOLRESSTARTED event */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to disable interrupt for ENDTX event */ #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to disable interrupt for ENDRX event */ #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to disable interrupt for RXERROR event */ #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ +/* Bit 7 : Write '1' to disable interrupt for ERROR event */ #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to disable interrupt for RXFRAMEEND event */ #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to disable interrupt for RXFRAMESTART event */ #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to disable interrupt for TXFRAMEEND event */ #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to disable interrupt for TXFRAMESTART event */ #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */ #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to disable interrupt for FIELDDETECTED event */ #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for READY event */ #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4485,7 +4554,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_SLEEPSTATE */ /* Description: Sleep state during automatic collision resolution */ -/* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. */ +/* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. */ #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */ #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */ #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */ @@ -4760,13 +4831,6 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ -/* Register: NVMC_ERASEPCR1 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ - -/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ -#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ -#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ - /* Register: NVMC_ERASEPAGE */ /* Description: Register for erasing a page in code area */ @@ -4774,6 +4838,13 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + /* Register: NVMC_ERASEALL */ /* Description: Register for erasing all non-volatile user memory */ @@ -4784,7 +4855,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ /* Register: NVMC_ERASEPCR0 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ /* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ @@ -6544,7 +6615,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ /* Register: GPIO_PIN_CNF */ -/* Description: Description collection[0]: Configuration of GPIO pins */ +/* Description: Description collection[n]: Configuration of GPIO pins */ /* Bits 17..16 : Pin sensing mechanism */ #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ @@ -6647,21 +6718,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to Enable interrupt for END event */ +/* Bit 2 : Write '1' to enable interrupt for END event */ #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for STARTED event */ #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6671,21 +6742,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to Disable interrupt for END event */ +/* Bit 2 : Write '1' to disable interrupt for END event */ #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for STARTED event */ #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6869,42 +6940,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 9 : Write '1' to Enable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to enable interrupt for USBPWRRDY event */ #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to Enable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to enable interrupt for USBREMOVED event */ #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to enable interrupt for USBDETECTED event */ #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to enable interrupt for POFWARN event */ #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -6914,42 +6985,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 9 : Write '1' to Disable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to disable interrupt for USBPWRRDY event */ #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to Disable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to disable interrupt for USBREMOVED event */ #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to disable interrupt for USBDETECTED event */ #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to disable interrupt for POFWARN event */ #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -6959,7 +7030,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_RESETREAS */ /* Description: Reset reason */ -/* Bit 20 : Reset due to wake up from System OFF mode by Vbus rising into valid range */ +/* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */ #define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */ #define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ #define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */ @@ -7014,7 +7085,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ /* Register: POWER_RAMSTATUS */ -/* Description: Deprecated register - RAM status register */ +/* Description: Deprecated register - RAM status register */ /* Bit 3 : RAM block 3 is on or off/powering up */ #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ @@ -7064,9 +7135,9 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ /* Register: POWER_POFCON */ -/* Description: Power failure comparator configuration */ +/* Description: Power-fail comparator configuration */ -/* Bits 11..8 : Power failure comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */ +/* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */ #define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */ #define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */ #define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */ @@ -7086,7 +7157,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */ #define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */ -/* Bits 4..1 : Power failure comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). */ +/* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */ #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ @@ -7102,7 +7173,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ -/* Bit 0 : Enable or disable power failure comparator */ +/* Bit 0 : Enable or disable power failure warning */ #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ @@ -7150,202 +7221,202 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ /* Register: POWER_RAM_POWER */ -/* Description: Description cluster[0]: RAM0 power control register */ +/* Description: Description cluster[n]: RAMn power control register */ -/* Bit 31 : Keep retention on RAM section S15 when RAM section is in OFF */ +/* Bit 31 : Keep retention on RAM section S15 when RAM section is off */ #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ #define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ #define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */ -/* Bit 30 : Keep retention on RAM section S14 when RAM section is in OFF */ +/* Bit 30 : Keep retention on RAM section S14 when RAM section is off */ #define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ #define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ #define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */ -/* Bit 29 : Keep retention on RAM section S13 when RAM section is in OFF */ +/* Bit 29 : Keep retention on RAM section S13 when RAM section is off */ #define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ #define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ #define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */ -/* Bit 28 : Keep retention on RAM section S12 when RAM section is in OFF */ +/* Bit 28 : Keep retention on RAM section S12 when RAM section is off */ #define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ #define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ #define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */ -/* Bit 27 : Keep retention on RAM section S11 when RAM section is in OFF */ +/* Bit 27 : Keep retention on RAM section S11 when RAM section is off */ #define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ #define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ #define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */ -/* Bit 26 : Keep retention on RAM section S10 when RAM section is in OFF */ +/* Bit 26 : Keep retention on RAM section S10 when RAM section is off */ #define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ #define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ #define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */ -/* Bit 25 : Keep retention on RAM section S9 when RAM section is in OFF */ +/* Bit 25 : Keep retention on RAM section S9 when RAM section is off */ #define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ #define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ #define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */ -/* Bit 24 : Keep retention on RAM section S8 when RAM section is in OFF */ +/* Bit 24 : Keep retention on RAM section S8 when RAM section is off */ #define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ #define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ #define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */ -/* Bit 23 : Keep retention on RAM section S7 when RAM section is in OFF */ +/* Bit 23 : Keep retention on RAM section S7 when RAM section is off */ #define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ #define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ #define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */ -/* Bit 22 : Keep retention on RAM section S6 when RAM section is in OFF */ +/* Bit 22 : Keep retention on RAM section S6 when RAM section is off */ #define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ #define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ #define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */ -/* Bit 21 : Keep retention on RAM section S5 when RAM section is in OFF */ +/* Bit 21 : Keep retention on RAM section S5 when RAM section is off */ #define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ #define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ #define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */ -/* Bit 20 : Keep retention on RAM section S4 when RAM section is in OFF */ +/* Bit 20 : Keep retention on RAM section S4 when RAM section is off */ #define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ #define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ #define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */ -/* Bit 19 : Keep retention on RAM section S3 when RAM section is in OFF */ +/* Bit 19 : Keep retention on RAM section S3 when RAM section is off */ #define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ #define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ #define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ -/* Bit 18 : Keep retention on RAM section S2 when RAM section is in OFF */ +/* Bit 18 : Keep retention on RAM section S2 when RAM section is off */ #define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ #define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ #define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ -/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +/* Bit 17 : Keep retention on RAM section S1 when RAM section is off */ #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ -/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +/* Bit 16 : Keep retention on RAM section S0 when RAM section is off */ #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ -/* Bit 15 : Keep RAM section S15 ON or OFF in System ON mode. */ +/* Bit 15 : Keep RAM section S15 on or off in System ON mode. */ #define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ #define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ #define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */ -/* Bit 14 : Keep RAM section S14 ON or OFF in System ON mode. */ +/* Bit 14 : Keep RAM section S14 on or off in System ON mode. */ #define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ #define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ #define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */ -/* Bit 13 : Keep RAM section S13 ON or OFF in System ON mode. */ +/* Bit 13 : Keep RAM section S13 on or off in System ON mode. */ #define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ #define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ #define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */ -/* Bit 12 : Keep RAM section S12 ON or OFF in System ON mode. */ +/* Bit 12 : Keep RAM section S12 on or off in System ON mode. */ #define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ #define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ #define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */ -/* Bit 11 : Keep RAM section S11 ON or OFF in System ON mode. */ +/* Bit 11 : Keep RAM section S11 on or off in System ON mode. */ #define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ #define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ #define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */ -/* Bit 10 : Keep RAM section S10 ON or OFF in System ON mode. */ +/* Bit 10 : Keep RAM section S10 on or off in System ON mode. */ #define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ #define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ #define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */ -/* Bit 9 : Keep RAM section S9 ON or OFF in System ON mode. */ +/* Bit 9 : Keep RAM section S9 on or off in System ON mode. */ #define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ #define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ #define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */ -/* Bit 8 : Keep RAM section S8 ON or OFF in System ON mode. */ +/* Bit 8 : Keep RAM section S8 on or off in System ON mode. */ #define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ #define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ #define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */ -/* Bit 7 : Keep RAM section S7 ON or OFF in System ON mode. */ +/* Bit 7 : Keep RAM section S7 on or off in System ON mode. */ #define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ #define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ #define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */ -/* Bit 6 : Keep RAM section S6 ON or OFF in System ON mode. */ +/* Bit 6 : Keep RAM section S6 on or off in System ON mode. */ #define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ #define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ #define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */ -/* Bit 5 : Keep RAM section S5 ON or OFF in System ON mode. */ +/* Bit 5 : Keep RAM section S5 on or off in System ON mode. */ #define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ #define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ #define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */ -/* Bit 4 : Keep RAM section S4 ON or OFF in System ON mode. */ +/* Bit 4 : Keep RAM section S4 on or off in System ON mode. */ #define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ #define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ #define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */ -/* Bit 3 : Keep RAM section S3 ON or OFF in System ON mode. */ +/* Bit 3 : Keep RAM section S3 on or off in System ON mode. */ #define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ #define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */ -/* Bit 2 : Keep RAM section S2 ON or OFF in System ON mode. */ +/* Bit 2 : Keep RAM section S2 on or off in System ON mode. */ #define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ #define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */ -/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +/* Bit 1 : Keep RAM section S1 on or off in System ON mode. */ #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ -/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +/* Bit 0 : Keep RAM section S0 on or off in System ON mode. */ #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERSET */ -/* Description: Description cluster[0]: RAM0 power control set register */ +/* Description: Description cluster[n]: RAMn power control set register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7427,88 +7498,88 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ -/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */ +/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ #define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ #define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */ -/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */ +/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ #define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ #define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */ -/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */ +/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ #define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ #define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */ -/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */ +/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ #define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ #define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */ -/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */ +/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ #define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ #define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */ -/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */ +/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ #define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ #define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */ -/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */ +/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ #define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ #define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */ -/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */ +/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ #define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ #define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */ -/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */ +/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ #define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ #define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */ -/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */ +/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ #define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ #define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */ -/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */ +/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ #define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ #define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */ -/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */ +/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ #define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ #define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */ -/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */ +/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ #define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ -/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */ +/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ #define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ -/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ -/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERCLR */ -/* Description: Description cluster[0]: RAM0 power control clear register */ +/* Description: Description cluster[n]: RAMn power control clear register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7590,82 +7661,82 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ -/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */ +/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ #define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ #define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */ -/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */ +/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ #define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ #define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */ -/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */ +/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ #define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ #define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */ -/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */ +/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ #define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ #define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */ -/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */ +/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ #define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ #define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */ -/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */ +/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ #define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ #define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */ -/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */ +/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ #define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ #define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */ -/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */ +/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ #define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ #define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */ -/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */ +/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ #define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ #define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */ -/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */ +/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ #define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ #define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */ -/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */ +/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ #define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ #define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */ -/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */ +/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ #define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ #define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */ -/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */ +/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ #define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ -/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */ +/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ #define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ -/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ -/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ @@ -7675,14 +7746,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Programmable Peripheral Interconnect */ /* Register: PPI_TASKS_CHG_EN */ -/* Description: Description cluster[0]: Enable channel group 0 */ +/* Description: Description cluster[n]: Enable channel group n */ /* Bit 0 : */ #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ /* Register: PPI_TASKS_CHG_DIS */ -/* Description: Description cluster[0]: Disable channel group 0 */ +/* Description: Description cluster[n]: Disable channel group n */ /* Bit 0 : */ #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ @@ -8338,21 +8409,21 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster[0]: Channel 0 event end-point */ +/* Description: Description cluster[n]: Channel n event end-point */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster[0]: Channel 0 task end-point */ +/* Description: Description cluster[n]: Channel n task end-point */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ /* Register: PPI_CHG */ -/* Description: Description collection[0]: Channel group 0 */ +/* Description: Description collection[n]: Channel group n */ /* Bit 31 : Include or exclude channel 31 */ #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ @@ -8547,7 +8618,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster[0]: Channel 0 task end-point */ +/* Description: Description cluster[n]: Channel n task end-point */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -8565,7 +8636,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ /* Register: PWM_TASKS_SEQSTART */ -/* Description: Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +/* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ /* Bit 0 : */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ @@ -8586,14 +8657,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ /* Register: PWM_EVENTS_SEQSTARTED */ -/* Description: Description collection[0]: First PWM period started on sequence 0 */ +/* Description: Description collection[n]: First PWM period started on sequence n */ /* Bit 0 : */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ /* Register: PWM_EVENTS_SEQEND */ -/* Description: Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter */ +/* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ /* Bit 0 : */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ @@ -8694,49 +8765,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8746,49 +8817,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8861,14 +8932,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[0]: Beginning address in RAM of this sequence */ +/* Description: Description cluster[n]: Beginning address in RAM of this sequence */ /* Bits 31..0 : Beginning address in RAM of this sequence */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[0]: Number of values (duty cycles) in this sequence */ +/* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ /* Bits 14..0 : Number of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8876,7 +8947,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[0]: Number of additional PWM periods between samples loaded into compare register */ +/* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8884,14 +8955,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ /* Register: PWM_SEQ_ENDDELAY */ -/* Description: Description cluster[0]: Time added after the sequence */ +/* Description: Description cluster[n]: Time added after the sequence */ /* Bits 23..0 : Time added after the sequence in PWM periods */ #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: PWM_PSEL_OUT */ -/* Description: Description collection[0]: Output pin select for PWM channel 0 */ +/* Description: Description collection[n]: Output pin select for PWM channel n */ /* Bit 31 : Connection */ #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -9029,35 +9100,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to enable interrupt for STOPPED event */ #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to enable interrupt for ACCOF event */ #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9067,35 +9138,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to disable interrupt for STOPPED event */ #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to disable interrupt for ACCOF event */ #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9314,7 +9385,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to Enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for READY event */ #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9324,7 +9395,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to Disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for READY event */ #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9732,7 +9803,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: RADIO */ -/* Description: 2.4 GHz Radio */ +/* Description: 2.4 GHz radio */ /* Register: RADIO_TASKS_TXEN */ /* Description: Enable RADIO in TX mode */ @@ -9770,7 +9841,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ /* Register: RADIO_TASKS_RSSISTART */ -/* Description: Start the RSSI and take one single sample of the receive signal strength. */ +/* Description: Start the RSSI and take one single sample of the receive signal strength */ /* Bit 0 : */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ @@ -9798,28 +9869,28 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ /* Register: RADIO_TASKS_EDSTART */ -/* Description: Start the Energy Detect measurement used in IEEE 802.15.4 mode */ +/* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ /* Bit 0 : */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ /* Register: RADIO_TASKS_EDSTOP */ -/* Description: Stop the Energy Detect measurement */ +/* Description: Stop the energy detect measurement */ /* Bit 0 : */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ /* Register: RADIO_TASKS_CCASTART */ -/* Description: Start the Clear Channel Assessment used in IEEE 802.15.4 mode */ +/* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ /* Bit 0 : */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ /* Register: RADIO_TASKS_CCASTOP */ -/* Description: Stop the Clear Channel Assessment */ +/* Description: Stop the clear channel assessment */ /* Bit 0 : */ #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ @@ -9875,14 +9946,14 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ /* Register: RADIO_EVENTS_RSSIEND */ -/* Description: Sampling of receive signal strength complete. */ +/* Description: Sampling of receive signal strength complete */ /* Bit 0 : */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ /* Register: RADIO_EVENTS_BCMATCH */ -/* Description: Bit counter reached bit count value. */ +/* Description: Bit counter reached bit count value */ /* Bit 0 : */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ @@ -9910,14 +9981,14 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ /* Register: RADIO_EVENTS_EDEND */ -/* Description: Sampling of Energy Detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ /* Bit 0 : */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ /* Register: RADIO_EVENTS_EDSTOPPED */ -/* Description: The sampling of Energy Detection has stopped */ +/* Description: The sampling of energy detection has stopped */ /* Bit 0 : */ #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ @@ -9966,7 +10037,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ /* Register: RADIO_EVENTS_MHRMATCH */ -/* Description: MAC Header match found. */ +/* Description: MAC header match found */ /* Bit 0 : */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ @@ -10099,154 +10170,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to Enable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to enable interrupt for PHYEND event */ #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to Enable interrupt for MHRMATCH event */ +/* Bit 23 : Write '1' to enable interrupt for MHRMATCH event */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to Enable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to enable interrupt for RXREADY event */ #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to Enable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to enable interrupt for TXREADY event */ #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to Enable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to enable interrupt for RATEBOOST event */ #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to enable interrupt for CCASTOPPED event */ #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to enable interrupt for CCABUSY event */ #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to Enable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to enable interrupt for CCAIDLE event */ #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to Enable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to enable interrupt for EDSTOPPED event */ #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to Enable interrupt for EDEND event */ +/* Bit 15 : Write '1' to enable interrupt for EDEND event */ #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to Enable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to enable interrupt for FRAMESTART event */ #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to enable interrupt for CRCOK event */ #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to enable interrupt for DISABLED event */ #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for END event */ +/* Bit 3 : Write '1' to enable interrupt for END event */ #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for READY event */ #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10256,154 +10327,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to Disable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to disable interrupt for PHYEND event */ #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to Disable interrupt for MHRMATCH event */ +/* Bit 23 : Write '1' to disable interrupt for MHRMATCH event */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to Disable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to disable interrupt for RXREADY event */ #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to Disable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to disable interrupt for TXREADY event */ #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to Disable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to disable interrupt for RATEBOOST event */ #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to disable interrupt for CCASTOPPED event */ #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to disable interrupt for CCABUSY event */ #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to Disable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to disable interrupt for CCAIDLE event */ #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to Disable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to disable interrupt for EDSTOPPED event */ #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to Disable interrupt for EDEND event */ +/* Bit 15 : Write '1' to disable interrupt for EDEND event */ #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to Disable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to disable interrupt for FRAMESTART event */ #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to disable interrupt for CRCOK event */ #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to disable interrupt for DISABLED event */ #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for END event */ +/* Bit 3 : Write '1' to disable interrupt for END event */ #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for READY event */ #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10478,7 +10549,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TXPOWER */ /* Description: Output power */ -/* Bits 7..0 : RADIO output power. */ +/* Bits 7..0 : RADIO output power */ #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ @@ -10489,26 +10560,26 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ -/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ -#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ -#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ -#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s (TX Only - RX supports both) */ -#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s (TX Only - RX supports both) */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */ /* Register: RADIO_PCNF0 */ @@ -10530,9 +10601,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ -#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BTLE Long Range */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ -/* Bits 23..22 : Length of Code Indicator - Long Range */ +/* Bits 23..22 : Length of code indicator - long range */ #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ @@ -10566,7 +10637,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ /* Bits 18..16 : Base address length in number of bytes */ @@ -10724,9 +10795,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ /* Register: RADIO_TIFS */ -/* Description: Inter Frame Spacing in us */ +/* Description: Interframe spacing in us */ -/* Bits 9..0 : Inter Frame Spacing in us */ +/* Bits 9..0 : Interframe spacing in us */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ @@ -10768,16 +10839,16 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ /* Register: RADIO_DAB */ -/* Description: Description collection[0]: Device address base segment 0 */ +/* Description: Description collection[n]: Device address base segment n */ -/* Bits 31..0 : Device address base segment 0 */ +/* Bits 31..0 : Device address base segment n */ #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ /* Register: RADIO_DAP */ -/* Description: Description collection[0]: Device address prefix 0 */ +/* Description: Description collection[n]: Device address prefix n */ -/* Bits 15..0 : Device address prefix 0 */ +/* Bits 15..0 : Device address prefix n */ #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ @@ -10881,49 +10952,49 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ /* Register: RADIO_SFD */ -/* Description: IEEE 802.15.4 Start of Frame Delimiter */ +/* Description: IEEE 802.15.4 start of frame delimiter */ -/* Bits 7..0 : IEEE 802.15.4 Start of Frame Delimiter. Note, the least significant 4-bits of the SFD cannot all be zeros. */ +/* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ /* Register: RADIO_EDCNT */ -/* Description: IEEE 802.15.4 Energy Detect Loop Count */ +/* Description: IEEE 802.15.4 energy detect loop count */ -/* Bits 20..0 : IEEE 802.15.4 Energy Detect Loop Count */ +/* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ /* Register: RADIO_EDSAMPLE */ -/* Description: IEEE 802.15.4 Energy Detect Level */ +/* Description: IEEE 802.15.4 energy detect level */ -/* Bits 7..0 : IEEE 802.15.4 Energy Detect Level */ +/* Bits 7..0 : IEEE 802.15.4 energy detect level */ #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ /* Register: RADIO_CCACTRL */ -/* Description: IEEE 802.15.4 Clear Channel Assessment Control */ +/* Description: IEEE 802.15.4 clear channel assessment control */ /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ -/* Bits 23..16 : CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ +/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ -/* Bits 15..8 : CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode. */ +/* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ -/* Bits 2..0 : CCA Mode Of Operation */ +/* Bits 2..0 : CCA mode of operation */ #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ -#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy Above Threshold */ -#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier Seen */ -#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy Above Threshold AND Carrier Seen */ -#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy Above Threshold OR Carrier Seen */ -#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ +#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ +#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ +#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ /* Register: RADIO_POWER */ /* Description: Peripheral power control */ @@ -10971,7 +11042,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to enable interrupt for VALRDY event */ #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -10981,7 +11052,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to disable interrupt for VALRDY event */ #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11051,7 +11122,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ /* Register: RTC_EVENTS_COMPARE */ -/* Description: Description collection[0]: Compare event on CC[0] match */ +/* Description: Description collection[n]: Compare event on CC[n] match */ /* Bit 0 : */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ @@ -11060,42 +11131,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for TICK event */ +/* Bit 0 : Write '1' to enable interrupt for TICK event */ #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11105,42 +11176,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for TICK event */ +/* Bit 0 : Write '1' to disable interrupt for TICK event */ #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11189,42 +11260,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ -/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to enable event routing for OVRFLW event */ #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable event routing for TICK event */ +/* Bit 0 : Write '1' to enable event routing for TICK event */ #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11234,42 +11305,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTENCLR */ /* Description: Disable event routing */ -/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to disable event routing for OVRFLW event */ #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable event routing for TICK event */ +/* Bit 0 : Write '1' to disable event routing for TICK event */ #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11291,7 +11362,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: RTC_CC */ -/* Description: Description collection[0]: Compare register 0 */ +/* Description: Description collection[n]: Compare register n */ /* Bits 23..0 : Compare value */ #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ @@ -11299,24 +11370,24 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: SAADC */ -/* Description: Analog to Digital Converter */ +/* Description: Successive approximation register (SAR) analog-to-digital converter */ /* Register: SAADC_TASKS_START */ -/* Description: Start the ADC and prepare the result buffer in RAM */ +/* Description: Starts the SAADC and prepares the result buffer in RAM */ /* Bit 0 : */ #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ /* Register: SAADC_TASKS_SAMPLE */ -/* Description: Take one ADC sample, if scan is enabled all channels are sampled */ +/* Description: Takes one SAADC sample */ /* Bit 0 : */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ /* Register: SAADC_TASKS_STOP */ -/* Description: Stop the ADC and terminate any on-going conversion */ +/* Description: Stops the SAADC and terminates all on-going conversions */ /* Bit 0 : */ #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ @@ -11330,28 +11401,28 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ /* Register: SAADC_EVENTS_STARTED */ -/* Description: The ADC has started */ +/* Description: The SAADC has started */ /* Bit 0 : */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ /* Register: SAADC_EVENTS_END */ -/* Description: The ADC has filled up the Result buffer */ +/* Description: The SAADC has filled up the result buffer */ /* Bit 0 : */ #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ /* Register: SAADC_EVENTS_DONE */ -/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ +/* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ /* Bit 0 : */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ /* Register: SAADC_EVENTS_RESULTDONE */ -/* Description: A result is ready to get transferred to RAM. */ +/* Description: Result ready for transfer to RAM */ /* Bit 0 : */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ @@ -11365,21 +11436,21 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ /* Register: SAADC_EVENTS_STOPPED */ -/* Description: The ADC has stopped */ +/* Description: The SAADC has stopped */ /* Bit 0 : */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ /* Register: SAADC_EVENTS_CH_LIMITH */ -/* Description: Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ +/* Description: Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */ /* Bit 0 : */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ /* Register: SAADC_EVENTS_CH_LIMITL */ -/* Description: Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ +/* Description: Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */ /* Bit 0 : */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ @@ -11523,154 +11594,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to enable interrupt for STOPPED event */ #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for DONE event */ +/* Bit 2 : Write '1' to enable interrupt for DONE event */ #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for END event */ #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for STARTED event */ #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11680,154 +11751,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to disable interrupt for STOPPED event */ #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for DONE event */ +/* Bit 2 : Write '1' to disable interrupt for DONE event */ #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for END event */ #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for STARTED event */ #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11840,20 +11911,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Status */ #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ -#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< SAADC is busy. Conversion in progress. */ /* Register: SAADC_ENABLE */ -/* Description: Enable or disable ADC */ +/* Description: Enable or disable SAADC */ -/* Bit 0 : Enable or disable ADC */ +/* Bit 0 : Enable or disable SAADC */ #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ -#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */ /* Register: SAADC_CH_PSELP */ -/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ +/* Description: Description cluster[n]: Input positive pin selection for CH[n] */ /* Bits 4..0 : Analog positive input channel */ #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ @@ -11871,7 +11942,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_PSELN */ -/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ +/* Description: Description cluster[n]: Input negative pin selection for CH[n] */ /* Bits 4..0 : Analog negative input, enables differential channel */ #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ @@ -11889,7 +11960,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_CONFIG */ -/* Description: Description cluster[0]: Input configuration for CH[0] */ +/* Description: Description cluster[n]: Input configuration for CH[n] */ /* Bit 24 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ @@ -11900,10 +11971,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 20 : Enable differential mode */ #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */ #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ -/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +/* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */ #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ @@ -11948,7 +12019,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ /* Register: SAADC_CH_LIMIT */ -/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ +/* Description: Description cluster[n]: High/low limits for event monitoring of a channel */ /* Bits 31..16 : High level limit */ #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ @@ -11964,13 +12035,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..0 : Set the resolution */ #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ -#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ -#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ -#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ -#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bits */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bits */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bits */ /* Register: SAADC_OVERSAMPLE */ -/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ +/* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ /* Bits 3..0 : Oversample control */ #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ @@ -12006,16 +12077,16 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: SAADC_RESULT_MAXCNT */ -/* Description: Maximum number of buffer words to transfer */ +/* Description: Maximum number of 16-bit samples to be written to output RAM buffer */ -/* Bits 14..0 : Maximum number of buffer words to transfer */ +/* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */ #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: SAADC_RESULT_AMOUNT */ -/* Description: Number of buffer words transferred since last START */ +/* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */ -/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +/* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */ #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ @@ -12033,7 +12104,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to Enable interrupt for READY event */ +/* Bit 2 : Write '1' to enable interrupt for READY event */ #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12043,7 +12114,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to Disable interrupt for READY event */ +/* Bit 2 : Write '1' to disable interrupt for READY event */ #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12238,35 +12309,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ +/* Bit 19 : Write '1' to enable interrupt for STARTED event */ #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for END event */ +/* Bit 6 : Write '1' to enable interrupt for END event */ #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12276,35 +12347,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ +/* Bit 19 : Write '1' to disable interrupt for STARTED event */ #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for END event */ +/* Bit 6 : Write '1' to disable interrupt for END event */ #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12605,21 +12676,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for END event */ #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12629,21 +12700,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for END event */ #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12860,7 +12931,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to enable interrupt for DATARDY event */ #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -12870,7 +12941,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to disable interrupt for DATARDY event */ #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -13036,21 +13107,21 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ /* Register: TIMER_TASKS_SHUTDOWN */ -/* Description: Deprecated register - Shut down timer */ +/* Description: Deprecated register - Shut down timer */ /* Bit 0 : */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ /* Register: TIMER_TASKS_CAPTURE */ -/* Description: Description collection[0]: Capture Timer value to CC[0] register */ +/* Description: Description collection[n]: Capture Timer value to CC[n] register */ /* Bit 0 : */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ /* Register: TIMER_EVENTS_COMPARE */ -/* Description: Description collection[0]: Compare event on CC[0] match */ +/* Description: Description collection[n]: Compare event on CC[n] match */ /* Bit 0 : */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ @@ -13134,42 +13205,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13179,42 +13250,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13250,7 +13321,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: TIMER_CC */ -/* Description: Description collection[0]: Capture/Compare register 0 */ +/* Description: Description collection[n]: Capture/Compare register n */ /* Bits 31..0 : Capture/Compare value */ #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ @@ -13355,42 +13426,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to Enable interrupt for BB event */ +/* Bit 14 : Write '1' to enable interrupt for BB event */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to enable interrupt for TXDSENT event */ #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to enable interrupt for RXDREADY event */ #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13400,42 +13471,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to Disable interrupt for BB event */ +/* Bit 14 : Write '1' to disable interrupt for BB event */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to disable interrupt for TXDSENT event */ #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to disable interrupt for RXDREADY event */ #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13712,49 +13783,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to enable interrupt for LASTTX event */ #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to enable interrupt for LASTRX event */ #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13764,49 +13835,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to disable interrupt for LASTTX event */ #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to disable interrupt for LASTRX event */ #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14092,42 +14163,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 26 : Write '1' to Enable interrupt for READ event */ +/* Bit 26 : Write '1' to enable interrupt for READ event */ #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ +/* Bit 25 : Write '1' to enable interrupt for WRITE event */ #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14137,42 +14208,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 26 : Write '1' to Disable interrupt for READ event */ +/* Bit 26 : Write '1' to disable interrupt for READ event */ #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ +/* Bit 25 : Write '1' to disable interrupt for WRITE event */ #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14293,7 +14364,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: TWIS_ADDRESS */ -/* Description: Description collection[0]: TWI slave address 0 */ +/* Description: Description collection[n]: TWI slave address n */ /* Bits 6..0 : TWI slave address */ #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ @@ -14420,42 +14491,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENSET */ /* Description: Enable interrupt */ -/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for RXTO event */ #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for NCTS event */ #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for CTS event */ #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14465,42 +14536,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for RXTO event */ #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for NCTS event */ #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for CTS event */ #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14868,77 +14939,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for RXTO event */ #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for NCTS event */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for CTS event */ #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14948,77 +15019,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for RXTO event */ #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for NCTS event */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for CTS event */ #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15222,28 +15293,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: User information configuration registers */ /* Register: UICR_NRFFW */ -/* Description: Description collection[0]: Reserved for Nordic firmware design */ +/* Description: Description collection[n]: Reserved for Nordic firmware design */ /* Bits 31..0 : Reserved for Nordic firmware design */ #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ /* Register: UICR_NRFHW */ -/* Description: Description collection[0]: Reserved for Nordic hardware design */ +/* Description: Description collection[n]: Reserved for Nordic hardware design */ /* Bits 31..0 : Reserved for Nordic hardware design */ #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ /* Register: UICR_CUSTOMER */ -/* Description: Description collection[0]: Reserved for customer */ +/* Description: Description collection[n]: Reserved for customer */ /* Bits 31..0 : Reserved for customer */ #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ /* Register: UICR_PSELRESET */ -/* Description: Description collection[0]: Mapping of the nRESET function */ +/* Description: Description collection[n]: Mapping of the nRESET function */ /* Bit 31 : Connection */ #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -15292,15 +15363,6 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */ #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ -/* Register: UICR_DCDCDRIVE0 */ -/* Description: Set drive level for REG0 DCDC mode. Using high drive will slightly reduce DCDC efficiency. */ - -/* Bit 0 : Set drive level for REG0 DCDC mode. */ -#define UICR_DCDCDRIVE0_DCDCDRIVE0_Pos (0UL) /*!< Position of DCDCDRIVE0 field. */ -#define UICR_DCDCDRIVE0_DCDCDRIVE0_Msk (0x1UL << UICR_DCDCDRIVE0_DCDCDRIVE0_Pos) /*!< Bit mask of DCDCDRIVE0 field. */ -#define UICR_DCDCDRIVE0_DCDCDRIVE0_Low (0UL) /*!< Low drive */ -#define UICR_DCDCDRIVE0_DCDCDRIVE0_High (1UL) /*!< High drive */ - /* Register: UICR_REGOUT0 */ /* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ @@ -15317,31 +15379,31 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: USBD */ -/* Description: Universal Serial Bus device */ +/* Description: Universal serial bus device */ /* Register: USBD_TASKS_STARTEPIN */ -/* Description: Description collection[0]: Captures the EPIN[0].PTR and EPIN[0].MAXCNT registers values, and enables endpoint IN 0 to respond to traffic from host */ +/* Description: Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ /* Bit 0 : */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ /* Register: USBD_TASKS_STARTISOIN */ -/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on iso endpoint */ +/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ /* Bit 0 : */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ /* Register: USBD_TASKS_STARTEPOUT */ -/* Description: Description collection[0]: Captures the EPOUT[0].PTR and EPOUT[0].MAXCNT registers values, and enables endpoint 0 to respond to traffic from host */ +/* Description: Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ /* Bit 0 : */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ /* Register: USBD_TASKS_STARTISOOUT */ -/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on iso endpoint */ +/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ /* Bit 0 : */ #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ @@ -15362,28 +15424,28 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ /* Register: USBD_TASKS_EP0STALL */ -/* Description: STALLs data and status stage on control endpoint 0 */ +/* Description: Stalls data and status stage on control endpoint 0 */ /* Bit 0 : */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ /* Register: USBD_TASKS_DPDMDRIVE */ -/* Description: Forces D+ and D-lines to the state defined in the DPDMVALUE register */ +/* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ /* Bit 0 : */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ /* Register: USBD_TASKS_DPDMNODRIVE */ -/* Description: Stops forcing D+ and D- lines to any state (USB engine takes control) */ +/* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ /* Bit 0 : */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ /* Register: USBD_EVENTS_USBRESET */ -/* Description: Signals that a USB reset condition has been detected on the USB lines */ +/* Description: Signals that a USB reset condition has been detected on USB lines */ /* Bit 0 : */ #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ @@ -15397,7 +15459,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ /* Register: USBD_EVENTS_ENDEPIN */ -/* Description: Description collection[0]: The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ /* Bit 0 : */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ @@ -15418,7 +15480,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ /* Register: USBD_EVENTS_ENDEPOUT */ -/* Description: Description collection[0]: The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ /* Bit 0 : */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ @@ -15432,14 +15494,14 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ /* Register: USBD_EVENTS_SOF */ -/* Description: Signals that a SOF (start of frame) condition has been detected on the USB lines */ +/* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ /* Bit 0 : */ #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ /* Register: USBD_EVENTS_USBEVENT */ -/* Description: An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause */ +/* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ /* Bit 0 : */ #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ @@ -15648,175 +15710,175 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to Enable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to enable interrupt for EPDATA event */ #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to Enable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to enable interrupt for EP0SETUP event */ #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to Enable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to enable interrupt for USBEVENT event */ #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to Enable interrupt for SOF event */ +/* Bit 21 : Write '1' to enable interrupt for SOF event */ #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to Enable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to enable interrupt for ENDISOOUT event */ #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to Enable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to enable interrupt for ENDEPOUT[7] event */ #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to Enable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to enable interrupt for ENDEPOUT[6] event */ #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to Enable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to enable interrupt for ENDEPOUT[5] event */ #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to Enable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to enable interrupt for ENDEPOUT[4] event */ #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to Enable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to enable interrupt for ENDEPOUT[3] event */ #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to Enable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */ #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to Enable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to enable interrupt for ENDEPOUT[1] event */ #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to Enable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to enable interrupt for ENDEPOUT[0] event */ #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to Enable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to enable interrupt for ENDISOIN event */ #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to Enable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to enable interrupt for EP0DATADONE event */ #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to Enable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to enable interrupt for ENDEPIN[7] event */ #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to Enable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to enable interrupt for ENDEPIN[6] event */ #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to enable interrupt for ENDEPIN[5] event */ #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to Enable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to enable interrupt for ENDEPIN[4] event */ #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to Enable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to enable interrupt for ENDEPIN[3] event */ #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to Enable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */ #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to Enable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to enable interrupt for ENDEPIN[1] event */ #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */ #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to Enable interrupt for STARTED event */ +/* Bit 1 : Write '1' to enable interrupt for STARTED event */ #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to Enable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to enable interrupt for USBRESET event */ #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -15826,175 +15888,175 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to Disable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to disable interrupt for EPDATA event */ #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to Disable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to disable interrupt for EP0SETUP event */ #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to Disable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to disable interrupt for USBEVENT event */ #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to Disable interrupt for SOF event */ +/* Bit 21 : Write '1' to disable interrupt for SOF event */ #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to Disable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to disable interrupt for ENDISOOUT event */ #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to Disable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to disable interrupt for ENDEPOUT[7] event */ #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to Disable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to disable interrupt for ENDEPOUT[6] event */ #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to Disable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to disable interrupt for ENDEPOUT[5] event */ #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to Disable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to disable interrupt for ENDEPOUT[4] event */ #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to Disable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to disable interrupt for ENDEPOUT[3] event */ #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to Disable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */ #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to Disable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to disable interrupt for ENDEPOUT[1] event */ #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to Disable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to disable interrupt for ENDEPOUT[0] event */ #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to Disable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to disable interrupt for ENDISOIN event */ #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to Disable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to disable interrupt for EP0DATADONE event */ #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to Disable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to disable interrupt for ENDEPIN[7] event */ #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to Disable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to disable interrupt for ENDEPIN[6] event */ #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to disable interrupt for ENDEPIN[5] event */ #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to Disable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to disable interrupt for ENDEPIN[4] event */ #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to Disable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to disable interrupt for ENDEPIN[3] event */ #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to Disable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */ #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to Disable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to disable interrupt for ENDEPIN[1] event */ #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */ #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to Disable interrupt for STARTED event */ +/* Bit 1 : Write '1' to disable interrupt for STARTED event */ #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to Disable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to disable interrupt for USBRESET event */ #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -16002,7 +16064,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */ /* Register: USBD_EVENTCAUSE */ -/* Description: Details on event that caused the USBEVENT event */ +/* Description: Details on what caused the USBEVENT event */ /* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */ #define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */ @@ -16016,13 +16078,13 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */ #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */ -/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear. */ +/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */ #define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */ #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */ #define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */ #define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */ -/* Bit 8 : Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear. */ +/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */ #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */ #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */ #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */ @@ -16035,7 +16097,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ /* Register: USBD_HALTED_EPIN */ -/* Description: Description collection[0]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16044,7 +16106,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ /* Register: USBD_HALTED_EPOUT */ -/* Description: Description collection[0]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16055,109 +16117,109 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPSTATUS */ /* Description: Provides information on which endpoint's EasyDMA registers have been captured */ -/* Bit 24 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */ #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */ #define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 23 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ #define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 22 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ #define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 21 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ #define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 20 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ #define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 19 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ #define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 18 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ #define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 17 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ #define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 16 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */ #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */ #define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 8 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */ #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */ #define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 7 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ #define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 6 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ #define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 5 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ #define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 4 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ #define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 3 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ #define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 2 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ #define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 1 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ #define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 0 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ +/* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */ #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */ #define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ @@ -16284,7 +16346,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_BREQUEST */ /* Description: SETUP data, byte 1, bRequest */ -/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values. */ +/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */ #define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */ #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */ #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */ @@ -16342,14 +16404,14 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ /* Register: USBD_SIZE_EPOUT */ -/* Description: Description collection[0]: Amount of bytes received last in the data stage of this OUT endpoint */ +/* Description: Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint */ -/* Bits 6..0 : Amount of bytes received last in the data stage of this OUT endpoint */ +/* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ /* Register: USBD_SIZE_ISOOUT */ -/* Description: Amount of bytes received last on this iso OUT data endpoint */ +/* Description: Number of bytes received last on this ISO OUT data endpoint */ /* Bit 16 : Zero-length data packet received */ #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */ @@ -16357,7 +16419,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */ #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */ -/* Bits 9..0 : Amount of bytes received last on this iso OUT data endpoint */ +/* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */ #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ @@ -16380,17 +16442,17 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */ /* Register: USBD_DPDMVALUE */ -/* Description: State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ +/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ -/* Bits 4..0 : State at which the DPDMDRIVE task will force D+ and D- */ +/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */ #define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */ #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */ -#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state) */ +#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */ #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */ #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */ /* Register: USBD_DTOGGLE */ -/* Description: Data toggle control and status. */ +/* Description: Data toggle control and status */ /* Bits 9..8 : Data toggle value */ #define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */ @@ -16412,11 +16474,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPINEN */ /* Description: Endpoint IN enable */ -/* Bit 8 : Enable iso IN endpoint */ +/* Bit 8 : Enable ISO IN endpoint */ #define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */ #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */ -#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable iso IN endpoint 8 */ -#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable iso IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */ /* Bit 7 : Enable IN endpoint 7 */ #define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */ @@ -16469,11 +16531,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPOUTEN */ /* Description: Endpoint OUT enable */ -/* Bit 8 : Enable iso OUT endpoint 8 */ +/* Bit 8 : Enable ISO OUT endpoint 8 */ #define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */ #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */ -#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable iso OUT endpoint 8 */ -#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable iso OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */ /* Bit 7 : Enable OUT endpoint 7 */ #define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ @@ -16559,7 +16621,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */ /* Register: USBD_LOWPOWER */ -/* Description: Controls USBD peripheral low-power mode during USB suspend */ +/* Description: Controls USBD peripheral low power mode during USB suspend */ /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */ #define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */ @@ -16577,21 +16639,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ /* Register: USBD_EPIN_PTR */ -/* Description: Description cluster[0]: Data pointer */ +/* Description: Description cluster[n]: Data pointer */ /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPIN_MAXCNT */ -/* Description: Description cluster[0]: Maximum number of bytes to transfer */ +/* Description: Description cluster[n]: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPIN_AMOUNT */ -/* Description: Description cluster[0]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16619,21 +16681,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: USBD_EPOUT_PTR */ -/* Description: Description cluster[0]: Data pointer */ +/* Description: Description cluster[n]: Data pointer */ /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPOUT_MAXCNT */ -/* Description: Description cluster[0]: Maximum number of bytes to transfer */ +/* Description: Description cluster[n]: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPOUT_AMOUNT */ -/* Description: Description cluster[0]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16681,7 +16743,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16691,7 +16753,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16832,7 +16894,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ /* Register: WDT_RR */ -/* Description: Description collection[0]: Reload request 0 */ +/* Description: Description collection[n]: Reload request n */ /* Bits 31..0 : Reload request register */ #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h index b0319f4c4..99120c016 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h index 197f796dc..352b41c8d 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h @@ -1,64 +1,61 @@ -/** - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ #ifndef NRF_PERIPHERALS_H__ #define NRF_PERIPHERALS_H__ /*lint ++flb "Enter library region */ -#if defined(NRF51422) - #include "nrf51422_peripherals.h" -#elif defined(NRF51801) - #include "nrf51801_peripherals.h" -#elif defined(NRF51802) - #include "nrf51802_peripherals.h" -#elif defined(NRF51822) - #include "nrf51822_peripherals.h" -#elif defined(NRF51824) - #include "nrf51824_peripherals.h" -#elif defined(NRF52810_XXAA) - #include "nrf52810_peripherals.h" -#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) - #include "nrf52832_peripherals.h" -#elif defined(NRF52840_XXAA) - #include "nrf52840_peripherals.h" +#if defined(_WIN32) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf specific files when building for PC host */ +#else + + #if defined(NRF51) + #include "nrf51_peripherals.h" + + #elif defined(NRF52810_XXAA) + #include "nrf52810_peripherals.h" + #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) + #include "nrf52832_peripherals.h" + #elif defined(NRF52840_XXAA) + #include "nrf52840_peripherals.h" + + #else + #error "Device must be defined. See nrf.h." + #endif #endif /*lint --flb "Leave library region" */ diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c index cbdd75d42..12478ba3f 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c +++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2017 ARM Limited. All rights reserved. +Copyright (c) 2009-2018 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h index 5a1e79496..28b3151bf 100644 --- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h +++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2017 ARM Limited. All rights reserved. +Copyright (c) 2009-2018 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/third_party/NordicSemiconductor/nrfx/nrfx.h b/third_party/NordicSemiconductor/nrfx/nrfx.h index 37e3c8de5..5f33a13a6 100644 --- a/third_party/NordicSemiconductor/nrfx/nrfx.h +++ b/third_party/NordicSemiconductor/nrfx/nrfx.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_H__ diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h index fddf05268..3d25aa8f1 100644 --- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h +++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h @@ -1,41 +1,32 @@ /** - * Copyright (c) 2018 - 2018, Nordic Semiconductor ASA - * + * Copyright (c) 2018, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_COREDEP_H__ diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h index 60fd4a25c..656b1a429 100644 --- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h +++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_IRQS_H__ diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h index 0a204533e..e7b78f0f3 100644 --- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h +++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_IRQS_NRF51_H__ diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h index 7934854b7..dd051e518 100644 --- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h +++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_IRQS_NRF52832_H__ diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h index b947bdc2b..bd9997731 100644 --- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h +++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_IRQS_NRF52832_H__ diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h index ecb7e1dc3..a7c44bb2e 100644 --- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h +++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_IRQS_NRF52840_H__ diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h index 4d575a7d2..1d2b6ceed 100644 --- a/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h +++ b/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h @@ -867,26 +867,6 @@ #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 3 #endif -// NRFX_SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 - -#ifndef NRFX_SPIS_DEFAULT_MODE -#define NRFX_SPIS_DEFAULT_MODE 0 -#endif - -// NRFX_SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first - -#ifndef NRFX_SPIS_DEFAULT_BIT_ORDER -#define NRFX_SPIS_DEFAULT_BIT_ORDER 0 -#endif - // NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h index 742ad9e79..b2f39c91a 100644 --- a/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h +++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h @@ -1316,26 +1316,6 @@ #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif -// NRFX_SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 - -#ifndef NRFX_SPIS_DEFAULT_MODE -#define NRFX_SPIS_DEFAULT_MODE 0 -#endif - -// NRFX_SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first - -#ifndef NRFX_SPIS_DEFAULT_BIT_ORDER -#define NRFX_SPIS_DEFAULT_BIT_ORDER 0 -#endif - // NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h index 6ba3ac23c..20f3c16de 100644 --- a/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h +++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h @@ -1731,26 +1731,6 @@ #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif -// NRFX_SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 - -#ifndef NRFX_SPIS_DEFAULT_MODE -#define NRFX_SPIS_DEFAULT_MODE 0 -#endif - -// NRFX_SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first - -#ifndef NRFX_SPIS_DEFAULT_BIT_ORDER -#define NRFX_SPIS_DEFAULT_BIT_ORDER 0 -#endif - // NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h index e473ddd5e..786cb4280 100644 --- a/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h +++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h @@ -1709,7 +1709,7 @@ #ifndef NRFX_SPIM3_ENABLED -#define NRFX_SPIM3_ENABLED 0 +#define NRFX_SPIM3_ENABLED 1 #endif // NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features @@ -1795,6 +1795,16 @@ // +// NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED - Enables nRF52840 anomaly 198 workaround for SPIM3. + + +// See more in the Errata document located at +// https://infocenter.nordicsemi.com/ + +#ifndef NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED +#define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 0 +#endif + // // NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver @@ -1838,26 +1848,6 @@ #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif -// NRFX_SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 - -#ifndef NRFX_SPIS_DEFAULT_MODE -#define NRFX_SPIS_DEFAULT_MODE 0 -#endif - -// NRFX_SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first - -#ifndef NRFX_SPIS_DEFAULT_BIT_ORDER -#define NRFX_SPIS_DEFAULT_BIT_ORDER 0 -#endif - // NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> diff --git a/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h b/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h index e29e50a0c..f5ed984dc 100644 --- a/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h +++ b/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_GLUE_H__ diff --git a/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h b/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h index bceab07bc..8f3fc6851 100644 --- a/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h +++ b/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h @@ -1,41 +1,32 @@ /** * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA - * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_LOG_H__