diff --git a/examples/platforms/da15000/Makefile.am b/examples/platforms/da15000/Makefile.am index ff4c79138..02f329e6d 100755 --- a/examples/platforms/da15000/Makefile.am +++ b/examples/platforms/da15000/Makefile.am @@ -36,21 +36,17 @@ libopenthread_da15000_a_CPPFLAGS -I$(top_srcdir)/examples/platforms/da15000 \ -I$(top_srcdir)/examples/platforms/da15000/crypto \ -I$(top_srcdir)/src/core \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/peripherals/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/adapters/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/memory/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/include \ -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/config \ - -I$(top_srcdir)/third_party/dialog/DialogSDK \ + -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/include \ + -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/memory/include \ + -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/osal \ + -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/peripherals/include \ + -I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/include \ -I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/src \ -I$(top_srcdir)/third_party/mbedtls/repo.patched/include \ -include$(top_srcdir)/examples/platforms/da15000/custom_config_qspi.h \ - -Wno-unknown-pragmas \ -Wno-sign-compare \ - -Wno-unused-function \ -Wno-unused-parameter \ - -Wno-shadow \ -Wno-type-limits \ -Wno-unused-variable \ -Wno-missing-field-initializers \ @@ -62,42 +58,41 @@ PLATFORM_SOURCES alarm.c \ flash.c \ logging.c \ + misc.c \ platform.c \ radio.c \ random.c \ uart.c \ - misc.c \ crypto/aes_alt.c \ $(NULL) DIALOG_SOURCES = \ @top_builddir@/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c \ + @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/config.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S \ @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c \ @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/vector_table.S \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c \ @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c \ + @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c \ + @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c \ + @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c \ @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c \ + @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c \ $(NULL) libopenthread_da15000_a_SOURCES = \ diff --git a/examples/platforms/da15000/README.md b/examples/platforms/da15000/README.md index b301fc62c..b2bf70919 100755 --- a/examples/platforms/da15000/README.md +++ b/examples/platforms/da15000/README.md @@ -7,7 +7,7 @@ This directory contains example platform drivers for the [Dialog Semiconductor D **NOTE:** Each Thread node requires a unique EUI-64. Please make sure all Thread nodes in your network have a unique EUI-64 by setting HARDCODED_NODE_ID in radio.c to a unique value. -**NOTE:** Current version works only with DA15000 rev. BA +**NOTE:** Current version works only with DA15000 ## Toolchain @@ -130,7 +130,7 @@ Board will indicate state of device according to LED blink speed. ## Remarks * Validation - The DA15000 example has been validated by Dialog Semiconductor with commit d250105 included. + The DA15000 example has been validated by Dialog Semiconductor with commit 1f6528e included. * Build environment diff --git a/examples/platforms/da15000/alarm.c b/examples/platforms/da15000/alarm.c index 1bb2ede60..bdc578096 100644 --- a/examples/platforms/da15000/alarm.c +++ b/examples/platforms/da15000/alarm.c @@ -31,17 +31,12 @@ * Platform abstraction for the alarm */ -#include - -#include -#include - #include -#include "hw_timer0.h" -#include "hw_gpio.h" #include "platform-da15000.h" +#include "hw_timer0.h" + static bool sIsRunning = false; static uint32_t sAlarm = 0; static uint32_t sCounter; @@ -88,12 +83,6 @@ void otPlatAlarmMilliStartAt(otInstance *aInstance, uint32_t t0, uint32_t dt) hw_timer0_enable(); } - - if (sIsRunning == false) - { - sIsRunning = true; - } - hw_timer0_unfreeze(); } @@ -103,6 +92,3 @@ void otPlatAlarmMilliStop(otInstance *aInstance) sIsRunning = false; hw_timer0_freeze(); } - - - diff --git a/examples/platforms/da15000/custom_config_qspi.h b/examples/platforms/da15000/custom_config_qspi.h index cdfee700c..614e92ddb 100755 --- a/examples/platforms/da15000/custom_config_qspi.h +++ b/examples/platforms/da15000/custom_config_qspi.h @@ -28,7 +28,7 @@ /** * @file custom_config_qspi.h - * Custom configuration file for FreeRTOS applications executing from QSPI. + * Board Support Package. User Configuration file for cached QSPI mode. */ #ifndef CUSTOM_CONFIG_QSPI_H_ @@ -37,7 +37,7 @@ #include "bsp_definitions.h" #define dg_configBLACK_ORCA_IC_REV BLACK_ORCA_IC_REV_B -#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_A +#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_B #undef CONFIG_USE_BLE #define CONFIG_USE_FTDF @@ -45,9 +45,6 @@ #define __HEAP_SIZE 0x0600 #define __STACK_SIZE 0x0100 -#define CONFIG_RETARGET -#define CONFIG_RETARGET_UART HW_UART1 - #define dg_configUSE_LP_CLK LP_CLK_32768 #define dg_configEXEC_MODE MODE_IS_CACHED #define dg_configCODE_LOCATION NON_VOLATILE_IS_FLASH @@ -58,9 +55,6 @@ #define dg_configUSER_CAN_USE_TIMER1 (0) -#define dg_configMEM_RETENTION_MODE (0x1F) -#define dg_configSHUFFLING_MODE (0x3) - #define dg_configUSE_WDOG (0) #define dg_configFLASH_CONNECTED_TO (FLASH_CONNECTED_TO_1V8) @@ -82,36 +76,45 @@ #define dg_configUSE_SW_CURSOR (1) -#define dg_configFEM_DLG_REF_BOARD (1) -#define dg_configPOWER_1V8P (1) +#define dg_configDISABLE_BACKGROUND_FLASH_OPS (1) -#define dg_configUSE_HW_TRNG (1) +/*************************************************************************************************\ + * Memory layout specific config + */ +#define dg_configQSPI_CODE_SIZE (512 * 1024) -#define dg_configUSE_HW_TIMER0 (1) +/*************************************************************************************************\ + * FTDF specific config + */ +#define FTDF_NO_CSL /* Define this to disable CSL mode */ +#define FTDF_NO_TSCH /* Define this to disable TSCH mode */ +#define FTDF_LITE /* Define this to enable LITE mode (only transparent mode enabled) */ +#define FTDF_PHY_API /* Define this to enable PHY API mode (no FTDF adapter; + implies FTDF_LITE) */ +#define FTDF_PASS_ACK_FRAME /* Define this to pass ACK frame */ -#define dg_configUSE_HW_AES_HASH (1) /*************************************************************************************************\ * OS specific config */ #define OS_BAREMETAL -#define CPU_DA15000 (1) /*************************************************************************************************\ * Peripheral specific config */ -#define FTDF_PHY_API -#define dg_configUSE_HW_RF (1) #define dg_configRF_ENABLE_RECALIBRATION (0) -#define FTDF_NO_CSL -#define FTDF_NO_TSCH -#define FTDF_LITE + +#define dg_configUSE_HW_AES_HASH (1) +#define dg_configUSE_HW_TIMER0 (1) +#define dg_configUSE_HW_TRNG (1) #define dg_configFLASH_ADAPTER (0) +#define dg_configRF_ADAPTER (0) #define dg_configUART_SOFTWARE_FIFO (1) #define dg_configUART2_SOFTWARE_FIFO_SIZE (256) + #define dg_configNVMS_ADAPTER (0) #define dg_configNVMS_VES (0) -#define dg_configUSE_WDOG (0) + /* Include bsp default values */ #include "bsp_defaults.h" diff --git a/examples/platforms/da15000/flash.c b/examples/platforms/da15000/flash.c index 2bc1ffa93..1b1635218 100644 --- a/examples/platforms/da15000/flash.c +++ b/examples/platforms/da15000/flash.c @@ -26,8 +26,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include -#include +#include "platform-da15000.h" #include "qspi_automode.h" @@ -144,4 +143,3 @@ uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize) { return qspi_automode_read(aAddress, aData, aSize);; } - diff --git a/examples/platforms/da15000/logging.c b/examples/platforms/da15000/logging.c index 5a282d335..a1dfbedff 100644 --- a/examples/platforms/da15000/logging.c +++ b/examples/platforms/da15000/logging.c @@ -31,11 +31,10 @@ * Platform abstraction for the logging * */ -#include -#include + #include -#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED) +#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED) void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, ...) { (void)aLogLevel; @@ -43,4 +42,3 @@ void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat (void)aFormat; } #endif - diff --git a/examples/platforms/da15000/misc.c b/examples/platforms/da15000/misc.c index ae9b53caf..64c9ba531 100644 --- a/examples/platforms/da15000/misc.c +++ b/examples/platforms/da15000/misc.c @@ -26,11 +26,10 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include - -#include #include +#include "platform-da15000.h" + #include "hw_cpm.h" #include "sdk_defs.h" diff --git a/examples/platforms/da15000/openthread-core-da15000-config.h b/examples/platforms/da15000/openthread-core-da15000-config.h index a22fcc8f1..a965d95b3 100644 --- a/examples/platforms/da15000/openthread-core-da15000-config.h +++ b/examples/platforms/da15000/openthread-core-da15000-config.h @@ -47,7 +47,7 @@ * * The base address of the pages to be used for non-volatile-settings storage. */ -#define SETTINGS_CONFIG_BASE_ADDRESS 0x7B000 +#define SETTINGS_CONFIG_BASE_ADDRESS 0x7B000 /** * @def SETTINGS_CONFIG_PAGE_SIZE @@ -81,6 +81,14 @@ */ #define OPENTHREAD_CONFIG_ENABLE_SOFTWARE_ENERGY_SCAN 1 +/** + * @def OPENTHREAD_CONFIG_ADDRESS_CACHE_ENTRIES + * + * The number of EID-to-RLOC cache entries. + * + */ +#define OPENTHREAD_CONFIG_ADDRESS_CACHE_ENTRIES 20 + /** * @def OPENTHREAD_CONFIG_LOG_OUTPUT * diff --git a/examples/platforms/da15000/platform.c b/examples/platforms/da15000/platform.c index 8688700de..ca67125db 100644 --- a/examples/platforms/da15000/platform.c +++ b/examples/platforms/da15000/platform.c @@ -31,23 +31,18 @@ * This file includes the platform-specific initializers. */ -#include - #include #include #include #include -#include #include "platform-da15000.h" -#include "sdk_defs.h" -#include "ftdf.h" #include "hw_cpm.h" #include "hw_gpio.h" #include "hw_qspi.h" -#include "hw_otpc.h" #include "hw_watchdog.h" +#include "sdk_defs.h" static bool sBlink = false; static int sMsCounterInit; @@ -67,7 +62,7 @@ static otInstance *sInstance = NULL; * Router - 2Hz * Child - 0.5Hz */ -void ExampleProcess(otInstance *aInstance) +static void ExampleProcess(otInstance *aInstance) { static int aliveLEDcounter = 0; otDeviceRole devRole; @@ -136,8 +131,6 @@ void PlatformInit(int argc, char *argv[]) da15000AlarmInit(); // Initialize Radio da15000RadioInit(); - // enable interrupts - portENABLE_INTERRUPTS(); (void)argc; (void)argv; @@ -214,9 +207,7 @@ static void ClkSet(sys_clk_t clock) case sysclk_PLL48: if (hw_cpm_is_pll_locked() == 0) { - hw_watchdog_unfreeze(); // Start watchdog hw_cpm_pll_sys_on(); // Turn on PLL - hw_watchdog_freeze(); // Stop watchdog } hw_cpm_enable_pll_divider(); // Enable divider (div by 2) @@ -229,9 +220,7 @@ static void ClkSet(sys_clk_t clock) case sysclk_PLL96: if (hw_cpm_is_pll_locked() == 0) { - hw_watchdog_unfreeze(); // Start watchdog hw_cpm_pll_sys_on(); // Turn on PLL - hw_watchdog_freeze(); // Stop watchdog } hw_cpm_disable_pll_divider(); // Disable divider (div by 1) @@ -254,7 +243,7 @@ static void ClkChange(sys_clk_t lastClock, sys_clk_t newClock) } } -void StateChangedCallback(uint32_t aFlags, void *aContext) +static void StateChangedCallback(uint32_t aFlags, void *aContext) { if ((aFlags & OT_CHANGED_COMMISSIONER_STATE) != 0) { diff --git a/examples/platforms/da15000/radio.c b/examples/platforms/da15000/radio.c index 9bb42c6e4..20e70b423 100644 --- a/examples/platforms/da15000/radio.c +++ b/examples/platforms/da15000/radio.c @@ -31,8 +31,6 @@ * Platform abstraction for radio communication. */ -#include -#include #include #include @@ -47,27 +45,20 @@ #include "hw_otpc.h" #include "hw_rf.h" #include "internal.h" -#include "regmap.h" #define FACTORY_TEST_TIMESTAMP (0x7F8EA08) // Register holds a timestamp of facotry test of a chip #define FACTORY_TESTER_ID (0x7F8EA0C) // Register holds test machine ID used for factory test -#define DEFAULT_CHANNEL (11) - -#define PRIVILEGED_DATA __attribute__((section("privileged_data_zi"))) - -#define RSSI_TABLE_SIZE 8 -#define EUI64_TABLE_SIZE 8 -#define RADIO_FRAMES_BUFFER_SIZE 8 +#define RADIO_DEFAULT_CHANNEL (11) +#define RADIO_EUI64_TABLE_SIZE (8) +#define RADIO_FRAMES_BUFFER_SIZE (32) enum { DA15000_RECEIVE_SENSITIVITY = -100, // dBm }; -static void da15000OtpRead(void); -static uint8_t eui64[EUI64_TABLE_SIZE] = {0}; - +static ftdf_dbm sRssiReal = -100; // Initialize with the worst power static otInstance *sThreadInstance; static otRadioState sRadioState = OT_RADIO_STATE_DISABLED; static otRadioFrame sReceiveFrame[RADIO_FRAMES_BUFFER_SIZE]; @@ -75,22 +66,19 @@ static otRadioFrame *sReceiveFrameAck; static otRadioFrame sTransmitFrame; static otError sTransmitStatus; static bool sAckFrame = false; -static bool sRadioPromiscuous = false; -static bool sRssiInit = true; -static bool sTransmitDoneFrame = false; static bool sDropFrame = false; -static uint8_t sChannel = DEFAULT_CHANNEL; -static uint8_t sRssiCtr = 0; +static bool sRadioPromiscuous = false; +static bool sTransmitDoneFrame = false; +static uint8_t sChannel = RADIO_DEFAULT_CHANNEL; +static uint8_t sEnableRX = 0; static uint8_t sReadFrame = 0; static uint8_t sWriteFrame = 0; static uint32_t sSleepInitDelay = 0; +static uint8_t sEui64[RADIO_EUI64_TABLE_SIZE]; static uint8_t sReceivePsdu[RADIO_FRAMES_BUFFER_SIZE][OT_RADIO_FRAME_MAX_SIZE]; -static uint8_t sRssiTable[RSSI_TABLE_SIZE]; static uint8_t sTransmitPsdu[OT_RADIO_FRAME_MAX_SIZE]; -PRIVILEGED_DATA static uint8_t sEnableRX; - static void da15000OtpRead(void) { hw_otpc_init(); // Start clock. @@ -103,14 +91,14 @@ static void da15000OtpRead(void) uint32_t *factoryTestId = (uint32_t *) FACTORY_TESTER_ID; __DMB(); - eui64[0] = 0x80; //80-EA-CA is for Dialog Semiconductor - eui64[1] = 0xEA; - eui64[2] = 0xCA; - eui64[3] = (*factoryTestId >> 8) & 0xff; - eui64[4] = (*factoryTestTimeStamp >> 24) & 0xff; - eui64[5] = (*factoryTestTimeStamp >> 16) & 0xff; - eui64[6] = (*factoryTestTimeStamp >> 8) & 0xff; - eui64[7] = *factoryTestTimeStamp & 0xff; + sEui64[0] = 0x80; //80-EA-CA is for Dialog Semiconductor + sEui64[1] = 0xEA; + sEui64[2] = 0xCA; + sEui64[3] = (*factoryTestId >> 8) & 0xff; + sEui64[4] = (*factoryTestTimeStamp >> 24) & 0xff; + sEui64[5] = (*factoryTestTimeStamp >> 16) & 0xff; + sEui64[6] = (*factoryTestTimeStamp >> 8) & 0xff; + sEui64[7] = *factoryTestTimeStamp & 0xff; hw_otpc_manual_read_off(); hw_otpc_disable(); @@ -119,6 +107,7 @@ static void da15000OtpRead(void) void da15000RadioInit(void) { uint16_t ptr; + /* Wake up power domains */ REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); @@ -138,7 +127,7 @@ void da15000RadioInit(void) da15000OtpRead(); - sChannel = DEFAULT_CHANNEL; + sChannel = RADIO_DEFAULT_CHANNEL; sTransmitFrame.mPsdu = sTransmitPsdu; for (ptr = 0; ptr != RADIO_FRAMES_BUFFER_SIZE; ptr++) @@ -152,61 +141,59 @@ void da15000RadioInit(void) void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) { (void)aInstance; - memcpy(aIeeeEui64, eui64, EUI64_TABLE_SIZE); + + memcpy(aIeeeEui64, sEui64, RADIO_EUI64_TABLE_SIZE); } void otPlatRadioSetPanId(otInstance *aInstance, uint16_t aPanid) { - (void)aInstance; + otLogInfoPlat(aInstance, "Set PanId: %X", aPanid); - otLogInfoPlat(sInstance, "Set PanId: %X", aPanid); - - FTDF_setValue(FTDF_PIB_PAN_ID, &aPanid); + ftdf_set_value(FTDF_PIB_PAN_ID, &aPanid); } void otPlatRadioSetExtendedAddress(otInstance *aInstance, const otExtAddress *aAddress) { - (void)aInstance; - - otLogInfoPlat(sInstance, "Set Extended Address: %X%X%X%X%X%X%X%X", + otLogInfoPlat(aInstance, "Set Extended Address: %X%X%X%X%X%X%X%X", aAddress->m8[7], aAddress->m8[6], aAddress->m8[5], aAddress->m8[4], aAddress->m8[3], aAddress->m8[2], aAddress->m8[1], aAddress->m8[0]); - FTDF_setValue(FTDF_PIB_EXTENDED_ADDRESS, aAddress->m8); + ftdf_set_value(FTDF_PIB_EXTENDED_ADDRESS, aAddress->m8); } void otPlatRadioSetShortAddress(otInstance *aInstance, uint16_t aAddress) { - (void)aInstance; + otLogInfoPlat(aInstance, "Set Short Address: %X", aAddress); - otLogInfoPlat(sInstance, "Set Short Address: %X", aAddress); - - FTDF_setValue(FTDF_PIB_SHORT_ADDRESS, &aAddress); + ftdf_set_value(FTDF_PIB_SHORT_ADDRESS, &aAddress); } otError otPlatRadioEnable(otInstance *aInstance) { + ftdf_bitmap32_t options; + otError error = OT_ERROR_NONE; uint8_t modeCCA; - otError error = OT_ERROR_NONE; otEXPECT_ACTION(sRadioState == OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE); sThreadInstance = aInstance; sEnableRX = 1; - FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - FTDF_setValue(FTDF_PIB_CURRENT_CHANNEL, &sChannel); - modeCCA = FTDF_CCA_MODE_2; - FTDF_setValue(FTDF_PIB_CCA_MODE, &modeCCA); + ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - FTDF_Bitmap32 options = FTDF_TRANSPARENT_ENABLE_FCS_GENERATION; + ftdf_set_value(FTDF_PIB_CURRENT_CHANNEL, &sChannel); + + modeCCA = FTDF_CCA_MODE_2; + ftdf_set_value(FTDF_PIB_CCA_MODE, &modeCCA); + + options = FTDF_TRANSPARENT_ENABLE_FCS_GENERATION; options |= FTDF_TRANSPARENT_WAIT_FOR_ACK; options |= FTDF_TRANSPARENT_AUTO_ACK; - FTDF_enableTransparentMode(FTDF_TRUE, options); + ftdf_enable_transparent_mode(FTDF_TRUE, options); otPlatRadioSetPromiscuous(aInstance, false); - otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL); + otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL); sRadioState = OT_RADIO_STATE_SLEEP; exit: @@ -215,14 +202,13 @@ exit: otError otPlatRadioDisable(otInstance *aInstance) { - (void)aInstance; sEnableRX = 0; - FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); + ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); ad_ftdf_sleep_when_possible(FTDF_TRUE); - FTDF_fpprReset(); + ftdf_fppr_reset(); - otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_DISABLED", NULL); + otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_DISABLED", NULL); sRadioState = OT_RADIO_STATE_DISABLED; return OT_ERROR_NONE; @@ -237,7 +223,7 @@ bool otPlatRadioIsEnabled(otInstance *aInstance) otError otPlatRadioSleep(otInstance *aInstance) { - (void)aInstance; + otError error = OT_ERROR_NONE; if (sRadioState == OT_RADIO_STATE_RECEIVE && sSleepInitDelay == 0) { @@ -249,14 +235,13 @@ otError otPlatRadioSleep(otInstance *aInstance) return OT_ERROR_NONE; } - otError error = OT_ERROR_NONE; otEXPECT_ACTION(sRadioState == OT_RADIO_STATE_RECEIVE, error = OT_ERROR_INVALID_STATE); - otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL); + otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL); sRadioState = OT_RADIO_STATE_SLEEP; sEnableRX = 0; - FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); + ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); ad_ftdf_sleep_when_possible(FTDF_TRUE); exit: @@ -265,7 +250,6 @@ exit: otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel) { - (void)aInstance; otError error = OT_ERROR_NONE; otEXPECT_ACTION(sRadioState != OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE); @@ -273,15 +257,15 @@ otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel) ad_ftdf_wake_up(); sEnableRX = 0; - FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); + ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); sChannel = aChannel; - FTDF_setValue(FTDF_PIB_CURRENT_CHANNEL, &aChannel); + ftdf_set_value(FTDF_PIB_CURRENT_CHANNEL, &aChannel); sEnableRX = 1; - FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); + ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL); + otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL); sRadioState = OT_RADIO_STATE_RECEIVE; exit: @@ -296,21 +280,19 @@ void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable) otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress) { - (void)aInstance; otError error = OT_ERROR_NONE; uint8_t entry; uint8_t entryIdx; // check if address already stored + otEXPECT(!ftdf_fppr_lookup_short_address(aShortAddress, &entry, &entryIdx)); - otEXPECT(!FTDF_fpprLookupShortAddress(aShortAddress, &entry, &entryIdx)); + otEXPECT_ACTION(ftdf_fppr_get_free_short_address(&entry, &entryIdx), error = OT_ERROR_NO_BUFS); - otEXPECT_ACTION(FTDF_fpprGetFreeShortAddress(&entry, &entryIdx), error = OT_ERROR_NO_BUFS); + otLogDebgPlat(aInstance, "Add ShortAddress entry: %d", entry); - otLogDebgPlat(sInstance, "Add ShortAddress entry: %d", entry); - - FTDF_fpprSetShortAddress(entry, entryIdx, aShortAddress); - FTDF_fpprSetShortAddressValid(entry, entryIdx, FTDF_TRUE); + ftdf_fppr_set_short_address(entry, entryIdx, aShortAddress); + ftdf_fppr_set_short_address_valid(entry, entryIdx, FTDF_TRUE); exit: return error; @@ -319,10 +301,9 @@ exit: otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) { - (void)aInstance; - + otError error = OT_ERROR_NONE; uint8_t entry; - FTDF_ExtAddress addr; + ftdf_ext_address_t addr; uint32_t addrL; uint64_t addrH; @@ -333,15 +314,14 @@ otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress addr = addrL | (addrH << 32); // check if address already stored - otError error = OT_ERROR_NONE; - otEXPECT(!FTDF_fpprLookupExtAddress(addr, &entry)); + otEXPECT(!ftdf_fppr_lookup_ext_address(addr, &entry)); - otEXPECT_ACTION(FTDF_fpprGetFreeExtAddress(&entry), error = OT_ERROR_NO_BUFS); + otEXPECT_ACTION(ftdf_fppr_get_free_ext_address(&entry), error = OT_ERROR_NO_BUFS); - otLogDebgPlat(sInstance, "Add ExtAddress entry: %d", entry); + otLogDebgPlat(aInstance, "Add ExtAddress entry: %d", entry); - FTDF_fpprSetExtAddress(entry, addr); - FTDF_fpprSetExtAddressValid(entry, FTDF_TRUE); + ftdf_fppr_set_ext_address(entry, addr); + ftdf_fppr_set_ext_address_valid(entry, FTDF_TRUE); exit: return error; @@ -349,17 +329,16 @@ exit: otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress) { - (void)aInstance; otError error = OT_ERROR_NONE; uint8_t entry; uint8_t entryIdx; - otEXPECT_ACTION(FTDF_fpprLookupShortAddress(aShortAddress, &entry, &entryIdx), error = OT_ERROR_NO_ADDRESS); + otEXPECT_ACTION(ftdf_fppr_lookup_short_address(aShortAddress, &entry, &entryIdx), error = OT_ERROR_NO_ADDRESS); - otLogDebgPlat(sInstance, "Clear ShortAddress entry: %d", entry); + otLogDebgPlat(aInstance, "Clear ShortAddress entry: %d", entry); - FTDF_fpprSetShortAddress(entry, entryIdx, 0); - FTDF_fpprSetShortAddressValid(entry, entryIdx, FTDF_FALSE); + ftdf_fppr_set_short_address(entry, entryIdx, 0); + ftdf_fppr_set_short_address_valid(entry, entryIdx, FTDF_FALSE); exit: return error; @@ -367,10 +346,9 @@ exit: otError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) { - (void)aInstance; - + otError error = OT_ERROR_NONE; uint8_t entry; - FTDF_ExtAddress addr; + ftdf_ext_address_t addr; uint32_t addrL; uint64_t addrH; @@ -380,13 +358,12 @@ otError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const otExtAddre (aExtAddress->m8[5] << 8) | (aExtAddress->m8[4] << 0); addr = addrL | (addrH << 32); - otError error = OT_ERROR_NONE; - otEXPECT_ACTION(FTDF_fpprLookupExtAddress(addr, &entry), error = OT_ERROR_NO_ADDRESS); + otEXPECT_ACTION(ftdf_fppr_lookup_ext_address(addr, &entry), error = OT_ERROR_NO_ADDRESS); - otLogDebgPlat(sInstance, "Clear ExtAddress entry: %d", entry); + otLogDebgPlat(aInstance, "Clear ExtAddress entry: %d", entry); - FTDF_fpprSetExtAddress(entry, 0); - FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); + ftdf_fppr_set_ext_address(entry, 0); + ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); exit: return error; @@ -394,19 +371,17 @@ exit: void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance) { - (void)aInstance; - uint8_t i, j; - otLogDebgPlat(sInstance, "Clear ShortAddress entries", NULL); + otLogDebgPlat(aInstance, "Clear ShortAddress entries", NULL); for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { for (j = 0; j < 4; j++) { - if (FTDF_fpprGetShortAddressValid(i, j)) + if (ftdf_fppr_get_short_address_valid(i, j)) { - FTDF_fpprSetShortAddressValid(i, j, FTDF_FALSE); + ftdf_fppr_set_short_address_valid(i, j, FTDF_FALSE); } } } @@ -414,17 +389,15 @@ void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance) void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance) { - (void)aInstance; - uint8_t i; - otLogDebgPlat(sInstance, "Clear ExtAddress entries", NULL); + otLogDebgPlat(aInstance, "Clear ExtAddress entries", NULL); for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { - if (FTDF_fpprGetExtAddressValid(i)) + if (ftdf_fppr_get_ext_address_valid(i)) { - FTDF_fpprSetExtAddressValid(i, FTDF_FALSE); + ftdf_fppr_set_ext_address_valid(i, FTDF_FALSE); } } } @@ -438,19 +411,15 @@ otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance) otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) { - (void)aInstance; - - uint8_t csmaSuppress; - otError error = OT_ERROR_NONE; + otEXPECT_ACTION(sRadioState != OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE); - otLogDebgPlat(sInstance, "Radio start transmit: %d bytes on channel: %d", aFrame->mLength, aFrame->mChannel); + otLogDebgPlat(aInstance, "Radio start transmit: %d bytes on channel: %d", aFrame->mLength, aFrame->mChannel); - csmaSuppress = 0; - ad_ftdf_send_frame_simple(aFrame->mLength, aFrame->mPsdu, aFrame->mChannel, 0, csmaSuppress); //Prio 0 for all. + ad_ftdf_send_frame_simple(aFrame->mLength, aFrame->mPsdu, aFrame->mChannel, 0, FTDF_TRUE); - otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_TRANSMIT", NULL); + otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_TRANSMIT", NULL); sRadioState = OT_RADIO_STATE_TRANSMIT; otPlatRadioTxStarted(aInstance, aFrame); @@ -462,47 +431,15 @@ exit: int8_t otPlatRadioGetRssi(otInstance *aInstance) { (void)aInstance; - uint16_t result = 0; - // fill table with same value for init - if (sRssiInit) - { - for (uint8_t i = 0; i < RSSI_TABLE_SIZE; i++) - { - sRssiTable[i] = sReceiveFrame[sWriteFrame].mLqi; - } - - sRssiInit = false; - } - else - { - ASSERT_ERROR(sRssiCtr < RSSI_TABLE_SIZE); - sRssiTable[sRssiCtr] = sReceiveFrame[sWriteFrame].mLqi; - sRssiCtr++; - - if (sRssiCtr >= RSSI_TABLE_SIZE) - { - sRssiCtr = 0; - } - } - - // average of 8 last lqi - for (uint8_t i = 0; i < RSSI_TABLE_SIZE; i++) - { - result += sRssiTable[i]; - } - - result = result / RSSI_TABLE_SIZE; - - // Approximation to dB scale by divide by 9 - return result / 9; + return sRssiReal; } otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) { (void)aInstance; - return OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_TRANSMIT_RETRIES; + return OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_TRANSMIT_RETRIES | OT_RADIO_CAPS_CSMA_BACKOFF; } bool otPlatRadioGetPromiscuous(otInstance *aInstance) @@ -514,11 +451,9 @@ bool otPlatRadioGetPromiscuous(otInstance *aInstance) void otPlatRadioSetPromiscuous(otInstance *aInstance, bool aEnable) { - (void)aInstance; + otLogInfoPlat(aInstance, "Set Promiscuous: %d", aEnable ? 1 : 0); - otLogInfoPlat(sInstance, "Set Promiscuous: %d", aEnable ? 1 : 0); - - FTDF_setValue(FTDF_PIB_PROMISCUOUS_MODE, &aEnable); + ftdf_set_value(FTDF_PIB_PROMISCUOUS_MODE, &aEnable); sRadioPromiscuous = aEnable; } @@ -533,26 +468,22 @@ otError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint1 void otPlatRadioSetDefaultTxPower(otInstance *aInstance, int8_t aPower) { - (void)aInstance; + otLogInfoPlat(aInstance, "Set DefaultTxPower: %d", aPower); - otLogInfoPlat(sInstance, "Set DefaultTxPower: %d", aPower); - - FTDF_setValue(FTDF_PIB_TX_POWER, &aPower); + ftdf_set_value(FTDF_PIB_TX_POWER, &aPower); } void da15000RadioProcess(otInstance *aInstance) { - (void)aInstance; - - FTDF_FrameHeader frameHeader; + ftdf_frame_header_t frameHeader; if (sReadFrame != sWriteFrame) { - FTDF_getFrameHeader(sReceiveFrame[sReadFrame].mPsdu, &frameHeader); + ftdf_get_frame_header(sReceiveFrame[sReadFrame].mPsdu, &frameHeader); - otLogDebgPlat(sInstance, "Radio received: %d bytes", sReceiveFrame[sReadFrame].mLength); + otLogDebgPlat(aInstance, "Radio received: %d bytes", sReceiveFrame[sReadFrame].mLength); - if (frameHeader.frameType == FTDF_ACKNOWLEDGEMENT_FRAME) + if (frameHeader.frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) { sReceiveFrameAck = &sReceiveFrame[sReadFrame]; sAckFrame = true; @@ -566,26 +497,9 @@ void da15000RadioProcess(otInstance *aInstance) if (sTransmitDoneFrame) { - switch (sTransmitStatus) - { - case OT_ERROR_NONE: - otLogDebgPlat(sInstance, "Radio transmit SUCCESSFUL", NULL); - break; + otLogDebgPlat(aInstance, "Radio transmit status: %s", otThreadErrorToString(sTransmitStatus)); - case OT_ERROR_CHANNEL_ACCESS_FAILURE: - otLogDebgPlat(sInstance, "Radio transmit CHANNEL_ACCESS_FAILURE", NULL); - break; - - case OT_ERROR_NO_ACK: - otLogDebgPlat(sInstance, "Radio transmit NO_ACK", NULL); - break; - - default: - otLogDebgPlat(sInstance, "Radio transmit ABORT", NULL); - break; - } - - FTDF_getFrameHeader(sTransmitFrame.mPsdu, &frameHeader); + ftdf_get_frame_header(sTransmitFrame.mPsdu, &frameHeader); if ((frameHeader.options & FTDF_OPT_ACK_REQUESTED) == 0 || sTransmitStatus != OT_ERROR_NONE) { @@ -602,14 +516,14 @@ void da15000RadioProcess(otInstance *aInstance) sTransmitDoneFrame = false; - otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL); + otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL); } exit: return; } -void FTDF_sendFrameTransparentConfirm(void *handle, FTDF_Bitmap32 status) +void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status) { (void)handle; @@ -635,12 +549,17 @@ void FTDF_sendFrameTransparentConfirm(void *handle, FTDF_Bitmap32 status) sTransmitDoneFrame = true; } -void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength, - FTDF_Octet *frame, - FTDF_Bitmap32 status, - FTDF_LinkQuality lqi) +static void radioRssiCalc(ftdf_link_quality_t link_quality) { - otEXPECT(frameLength <= OT_RADIO_FRAME_MAX_SIZE); + sRssiReal = (ftdf_dbm)((0.5239 * (float)link_quality) - 114.8604); +} + +void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length, + ftdf_octet_t *frame, + ftdf_bitmap32_t status, + ftdf_link_quality_t link_quality) +{ + otEXPECT(frame_length <= OT_RADIO_FRAME_MAX_SIZE); otEXPECT(sRadioState != OT_RADIO_STATE_DISABLED); @@ -648,16 +567,18 @@ void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength, if (status == FTDF_TRANSPARENT_RCV_SUCCESSFUL) { + radioRssiCalc(link_quality); + #if OPENTHREAD_ENABLE_RAW_LINK_API // Timestamp - sReceiveFrameAck.mMsec = otPlatAlarmMilliGetNow(); - sReceiveFrameAck.mUsec = 0; // Don't support microsecond timer for now. + sReceiveFrame[sWriteFrame].mMsec = otPlatAlarmMilliGetNow(); + sReceiveFrame[sWriteFrame].mUsec = 0; // Don't support microsecond timer for now. #endif sReceiveFrame[sWriteFrame].mChannel = sChannel; - sReceiveFrame[sWriteFrame].mLength = frameLength; - sReceiveFrame[sWriteFrame].mLqi = lqi; + sReceiveFrame[sWriteFrame].mLength = frame_length; + sReceiveFrame[sWriteFrame].mLqi = OT_RADIO_LQI_NONE; sReceiveFrame[sWriteFrame].mPower = otPlatRadioGetRssi(sThreadInstance); - memcpy(sReceiveFrame[sWriteFrame].mPsdu, frame, frameLength); + memcpy(sReceiveFrame[sWriteFrame].mPsdu, frame, frame_length); sWriteFrame = (sWriteFrame + 1) % RADIO_FRAMES_BUFFER_SIZE; @@ -676,4 +597,3 @@ int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance) (void)aInstance; return DA15000_RECEIVE_SENSITIVITY; } - diff --git a/examples/platforms/da15000/random.c b/examples/platforms/da15000/random.c index bc51c4a9e..b011c6112 100644 --- a/examples/platforms/da15000/random.c +++ b/examples/platforms/da15000/random.c @@ -36,6 +36,7 @@ #include #include "platform-da15000.h" + #include "hw_trng.h" #include "sdk_defs.h" @@ -125,4 +126,3 @@ otError otPlatRandomGetTrue(uint8_t *aOutput, uint16_t aOutputLength) return OT_ERROR_NONE; } - diff --git a/examples/platforms/da15000/startup_ARMCM0.S b/examples/platforms/da15000/startup_ARMCM0.S deleted file mode 100644 index cb76fa973..000000000 --- a/examples/platforms/da15000/startup_ARMCM0.S +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file startup_ARMCM0.S - * Startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V2.0 - * Date: 16 August 2013 - */ - - .syntax unified - .arch armv6-m - .section text_reset - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -#if (dg_configSKIP_MAGIC_CHECK_AT_START == 0) -/* If the Magic Word {0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEAD10CC} is found at 0x7fd0000 then the - * execution will block for a while in order to give time to a debugger to attach. */ - ldr r4, =0x7fd0000 - ldmia r4!, {r0-r3} - ldr r4, =0xDEADBEEF - cmp r0, r4 - bne .code_starts - cmp r1, r4 - bne .code_starts - cmp r2, r4 - bne .code_starts - ldr r4, =0xDEAD10CC - cmp r3, r4 - bne .code_starts - /* Enable debugger */ - ldr r4, =0x50000012 - ldrh r5, [r4] - mov r6, r5 - movs r1, #128 - orrs r5, r5, r1 - strh r5, [r4] - /* Block for 2'' */ - ldr r0, =0x150000 -.delay_loop: - subs r0, #1 - bgt .delay_loop - /* Make sure that this will happen only once! */ - ldr r4, =0x7fd0000 - movs r0, #0 - str r0, [r4] - /* Restore debugger setting */ - ldr r4, =0x50000012 - strh r6, [r4] - -.code_starts: -#endif - -/* RAM shuffling configuration should be determined from the image in the QSPI Flash or OTP - * and must be applied at the beginning of the Reset Vector. The interrupt vector table must - * be copied to the RAM base after the shuffling is done. - * NOTE: Even though there is an OTP field specifically for the shuffling configuration - * we must bypass it here since the shuffling might change between different - * QSPI FLASH image versions. For OTP images RAM shuffling configuration will never change, - * but we also apply it to ignore the OTP field in any case. */ - ldr r4, =0x50000012 - movs r0, #0 - ldrh r0, [r4] - movs r1, #0x18 - bics r0, r0, r1 - movs r1, #dg_configSHUFFLING_MODE<<3 - orrs r0, r0, r1 - /* Update SYS_CTRL_REG. */ - strh r0, [r4] - - /* Copy ISR VT from from QSPI Flash/OTP to RAM. This must be done - * after applying shuffling mode. */ -# if (dg_configIMAGE_FLASH_OFFSET == 0) - ldr r1, =0x8000008 -# else - ldr r1, =(0x8000000 + dg_configIMAGE_FLASH_OFFSET) -# endif - ldr r2, =0x7FC0000 - ldr r3, =0x7FC00C0 - /* Block should be a multiple of 16 to traverse correctly L_loopIV */ - subs r3, r2 - ble .L_loopIV_done - -.L_loopIV: - ldmia r1!, {r4-r7} - stmia r2!, {r4-r7} - subs r3, #16 - bgt .L_loopIV - -.L_loopIV_done: - - bl SystemInitPre - bl SystemInit - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ -#define __STARTUP_COPY_MULTIPLE - -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r0, =__copy_table_end__ - -.L_loop0: - cmp r4, r0 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - push {r4} - -.L_loop0_0: - subs r3, #16 - blt .L_loop0_0_done - ldmia r1!, {r4-r7} - stmia r2!, {r4-r7} - b .L_loop0_0 - -.L_loop0_0_done: - pop {r4} - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#define __STARTUP_CLEAR_BSS_MULTIPLE - -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r0, =__zero_table_end__ - movs r4, 0 - movs r5, r4 - mov r6, r4 - mov r7, r4 - -.L_loop2: - cmp r3, r0 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - -.L_loop2_0: - subs r2, #32 // Requires 32-byte alignment! - blt .L_loop2_0_done - stmia r1!, {r4-r7} - stmia r1!, {r4-r7} - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - /* Copy the address of the retained NMI and HardFault handlers to the vector table. */ - ldr r0, =0x7FC0008 - ldr r1, =NMI_Handler - str r1, [r0, #0] - ldr r1, =HardFault_Handler - str r1, [r0, #4] - - bl SystemInitPost - - bl main - - .pool - .size Reset_Handler, . - Reset_Handler - - .text - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* - * enable debugger: - * CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 1; - */ - movs r1, #0x50 - lsls r1, #24 - ldrh r2, [r1, #0x12] - movs r3, #0x80 - orrs r2, r2, r3 - strh r2, [r1, #0x12] - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - .thumb - .thumb_func - .align 1 - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - def_irq_handler BLE_WAKEUP_LP_Handler - def_irq_handler BLE_GEN_Handler - def_irq_handler FTDF_WAKEUP_Handler - def_irq_handler FTDF_GEN_Handler - def_irq_handler RFCAL_Handler - def_irq_handler COEX_Handler - def_irq_handler CRYPTO_Handler - def_irq_handler MRM_Handler - def_irq_handler UART_Handler - def_irq_handler UART2_Handler - def_irq_handler I2C_Handler - def_irq_handler I2C2_Handler - def_irq_handler SPI_Handler - def_irq_handler SPI2_Handler - def_irq_handler ADC_Handler - def_irq_handler KEYBRD_Handler - def_irq_handler IRGEN_Handler - def_irq_handler WKUP_GPIO_Handler - def_irq_handler SWTIM0_Handler - def_irq_handler SWTIM1_Handler - def_irq_handler QUADEC_Handler - def_irq_handler USB_Handler - def_irq_handler PCM_Handler - def_irq_handler SRC_IN_Handler - def_irq_handler SRC_OUT_Handler - def_irq_handler VBUS_Handler - def_irq_handler DMA_Handler - def_irq_handler RF_DIAG_Handler - def_irq_handler TRNG_Handler - def_irq_handler DCDC_Handler - def_irq_handler XTAL16RDY_Handler - def_irq_handler RESERVED31_Handler - - .section text_retained - .align 1 - .thumb - .thumb_func - .globl NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r1, =NMI_HandlerC - movs r0, #4 - mov r2, lr - tst r0, r2 - beq NMI_stacking_using_MSP - mrs r0, psp - b stack_check -NMI_stacking_using_MSP: - mrs r0, msp - b stack_check - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb - .thumb_func - .globl HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r1, =HardFault_HandlerC - movs r0, #4 - mov r2, lr - tst r0, r2 - beq HF_stacking_using_MSP - mrs r0, psp - b stack_check -HF_stacking_using_MSP: - mrs r0, msp -stack_check: - /* 0x7FC0000 is start of RAM */ - ldr r2, =0x7FC0000 - cmp r0, r2 - blt Wrong_SP - /* Check SYS_CTRL_REG:CACHERAM_MUX */ - ldr r2, =0x50000012 - ldrh r2, [r2] - movs r3, #1 - lsls r3, r3, #10 - ands r2, r2, r3 - bne cache_is_on - /* 0x7FE4000 marks end of RAM (assuming that the CACHE is used as RAM) */ - ldr r2, =0x7FE4000-32 - b check_end_of_ram -cache_is_on: - /* 0x7FE0000 marks end of RAM */ - ldr r2, =0x7FE0000-32 -check_end_of_ram: - cmp r0, r2 - bgt Wrong_SP - bx r1 -Wrong_SP: - /* Freeze WDog at all times */ - ldr r0, =0x50003300 - ldr r1, =8 - strh r1, [r0, #0] - /* Enable debugger at all times */ - ldr r4, =0x50000012 - ldrh r0, [r4, #0] - movs r1, #0x80 - orrs r0, r0, r1 - /* Update SYS_CTRL_REG */ - strh r0, [r4, #0] - - /* Wait for the WDog to hit or a debug session to start */ - b . - .size HardFault_Handler, . - HardFault_Handler - - .end - diff --git a/examples/platforms/da15000/system_ARMCM0.c b/examples/platforms/da15000/system_ARMCM0.c deleted file mode 100644 index 4e907b04b..000000000 --- a/examples/platforms/da15000/system_ARMCM0.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file system_ARMCM0.c - * CMSIS Device System Source File for ARMCM0 Device Series. - */ - -#include -#include -#include -#include -#include "sdk_defs.h" -#include "interrupts.h" -#include "hw_cpm.h" -#include "hw_otpc.h" -#include "hw_qspi.h" -#include "hw_watchdog.h" -#include "sys_tcs.h" -#include "qspi_automode.h" - -/* - * This is just so that compilation doesn't break for RAM builds. - * The code that uses it is optimized out in RAM builds. - */ -extern uint32_t NVMS_PARAM_PART_end; - -/* - * TCS Offsets - */ -#define OTP_HEADER_BASE_ADDR_IN_OTP (0x7F8E9C0) - -#define TCS_SECTION_OFFSET (184) /* 0x7F8EA78 - 0x7F8E9C0 */ -#define TCS_SECTION_LENGTH (24) /* 24 entries, 16 bytes each for OTP */ - -#ifndef __SYSTEM_CLOCK -# define __SYSTEM_CLOCK (16000000UL) /* 16 MHz */ -#endif - -#if (dg_configUSE_LP_CLK == LP_CLK_32000) -# define LP_CLK_FREQ (32000) - -#elif (dg_configUSE_LP_CLK == LP_CLK_32768) -# define LP_CLK_FREQ (32768) - -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) -# define LP_CLK_FREQ (0) - -#else -# error "dg_configUSE_LP_CLK is not defined or has an unknown value!" -#endif - -/* - * Linker symbols - * - * Note: if any of them is missing, please correct your linker script. Please refer to the linker - * script of pxp_reporter. - */ -extern uint32_t __copy_table_start__; -extern uint32_t __copy_table_end__; -extern uint32_t __zero_table_start__; -extern uint32_t __zero_table_end__; -extern uint8_t end; -extern uint8_t __HeapLimit; - -/* - * Global variables - */ -__RETAINED_RW static uint8_t *heapend = &end; -__RETAINED_UNINIT __attribute__((unused)) uint32_t black_orca_chip_version; -uint32_t SystemCoreClock __RETAINED = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemLPClock __RETAINED = LP_CLK_FREQ; /*!< System Low Power Clock Frequency (LP Clock)*/ - -/** - * @brief Memory safe implementation of newlib's _sbrk(). - * - */ -__LTO_EXT -void *_sbrk(int incr) -{ - uint8_t *newheapstart; - - if (heapend + incr > &__HeapLimit) - { - /* Hitting this, means that the value of _HEAP_SIZE is too small. - * The value of incr is in stored_incr at this point. By checking the equation - * above, it is straightforward to determine the missing space. - */ - volatile int stored_incr __attribute__((unused)); - - stored_incr = incr; - ASSERT_ERROR(0); - - errno = ENOMEM; - return (void *) - 1; - } - - newheapstart = heapend; - heapend += incr; - - return newheapstart; -} - -/** - * Apply trim values from OTP. - * - * @brief Writes the trim values located in the OTP to the corresponding system registers. - * - * @param[out] tcs_array The valid pairs are placed in this buffer. - * @param[out] valid_entries The number of valid pairs. - * - * @return True if at least one trim value has been applied, else false. - * - */ -static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entries) -{ - uint32_t address; - uint32_t inverted_address; - uint32_t value; - uint32_t inverted_value; - uint32_t *p; - int i; - int index = 0; - int vdd = 0; - int retries = 0; - bool forward_reading = true; - bool res = false; - - p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET); - - for (i = 0; i < TCS_SECTION_LENGTH; i++) - { - do - { - address = *p; - p++; - inverted_address = *p; - p++; - value = *p; - p++; - inverted_value = *p; - p++; - - if ((address == 0) && (value == 0)) - { - break; - } - - // Check validity - if ((address != ~inverted_address) || (value != ~inverted_value)) - { - // Change LDO core voltage level and retry - vdd++; - vdd &= 0x3; - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, vdd); - - // Wait for the voltage to settle... - SysTick->CTRL = 0; - SysTick->LOAD = 500; // 500 * (62.5 * 4) = 125usec - SysTick->VAL = 0; - SysTick->CTRL = 0x5; // Start using system clock - - while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {} - - // Adjust the read pointer - p -= 4; - } - - retries++; - - if (retries == 32) - { - // Unrecoverable problem! Assert in development mode - ASSERT_WARNING(0); - - // Unrecoverable problem! Issue a HW reset. - hw_cpm_reset_system(); - } - } - while ((address != ~inverted_address) || (value != ~inverted_value)); - - retries = 0; - - // Read the complete TCS area but skip empty entries. - if ((address == 0) && (value == 0)) - { - if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E)) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) - && (CHIP_IS_AE || CHIP_IS_BA))) - { - if (!forward_reading) - { - break; - } - - forward_reading = false; - p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET); - p += (TCS_SECTION_LENGTH - 1) * 4; - } - else - { - (void)forward_reading; - } - - continue; - } - - if (!forward_reading) - { - p -= 8; - } - - sys_tcs_store_pair(address, value); - - tcs_array[(index * 2) + 0] = address; - tcs_array[(index * 2) + 1] = value; - - *valid_entries = index + 1; - index++; - - res = true; - } - - return res; -} - -/** - * Check whether the code has been compiled for a chip version that is compatible with the chip - * it runs on. - */ -static bool is_compatible_chip_version(void) -{ - const uint32_t ver = black_orca_get_chip_version(); - - /* Oldest supported version is AE. */ - if ((ver < BLACK_ORCA_IC_VERSION(A, E)) && (dg_configUSE_AUTO_CHIP_DETECTION == 0)) - { - return false; - } - - if ((ver == BLACK_ORCA_TARGET_IC) || (dg_configUSE_AUTO_CHIP_DETECTION == 1)) - { - return true; - } - - return false; -} - -#ifdef OS_BAREMETAL - -static volatile bool nortos_xtal16m_settled = false; - -void XTAL16RDY_Handler(void) -{ - nortos_xtal16m_settled = true; -} - -/* carry out clock initialization sequence */ -static void nortos_clk_setup(void) -{ - // Setup DIVN - if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M) - { - hw_cpm_set_divn(false); // External crystal is 16MHz - } - else - { - hw_cpm_set_divn(true); // External crystal is 32MHz - } - - hw_cpm_enable_rc32k(); - hw_cpm_lp_set_rc32k(); - - NVIC_ClearPendingIRQ(XTAL16RDY_IRQn); - nortos_xtal16m_settled = false; - NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ - - hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K); - hw_cpm_enable_xtal16m(); // Enable XTAL16M - hw_watchdog_unfreeze(); // Start watchdog - - while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts - - /* Wait for XTAL16M to settle */ - while (!nortos_xtal16m_settled); - - hw_watchdog_freeze(); // Stop watchdog - hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M); -} - -#endif /* OS_BAREMETAL */ - -static __RETAINED_CODE void configure_cache(void) -{ - bool flush = false; - - GLOBAL_INT_DISABLE(); - - if (dg_configCACHEABLE_QSPI_AREA_LEN != -1) - { - uint32_t cache_len; - - /* dg_configCACHEABLE_QSPI_AREA_LEN must be 64KB-aligned */ - ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0xFFFF) == 0); - /* - * dg_configCACHEABLE_QSPI_AREA_LEN shouldn't set any bits that do not fit in - * CACHE_CTRL2_REG.CACHE_LEN (9 bits wide) after shifting out the lower 16 bits - */ - ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0x1FF0000) - == dg_configCACHEABLE_QSPI_AREA_LEN); - /* - * set cacheable area - * - * setting CACHE_CTRL2_REG.CACHE_LEN to N, actually sets the size of the cacheable - * area to (N + 1) * 64KB - * special cases: - * N == 0 --> no caching - * N == 1 --> 128KB are cached, i.e. no way to cache only 64KB - */ - cache_len = dg_configCACHEABLE_QSPI_AREA_LEN >> 16; - /* cannot cache only 64KB! */ - ASSERT_WARNING(cache_len != 1); - - if (cache_len > 1) - { - cache_len--; - } - - REG_SETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN, cache_len); - } - - if (dg_configCACHE_ASSOCIATIVITY != CACHE_ASSOC_AS_IS) - { - if (CACHE->CACHE_ASSOCCFG_REG != dg_configCACHE_ASSOCIATIVITY) - { - /* override the set associativity setting */ - CACHE->CACHE_ASSOCCFG_REG = dg_configCACHE_ASSOCIATIVITY; - flush = true; - } - } - - if (dg_configCACHE_LINESZ != CACHE_LINESZ_AS_IS) - { - if (CACHE->CACHE_LNSIZECFG_REG != dg_configCACHE_LINESZ) - { - /* override the cache line setting */ - CACHE->CACHE_LNSIZECFG_REG = dg_configCACHE_LINESZ; - flush = true; - } - } - - if (flush && (REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN) > 0)) - { - /* flush cache */ - REG_SET_BIT(CACHE, CACHE_CTRL1_REG, CACHE_FLUSH); - } - - GLOBAL_INT_RESTORE(); -} - -/** - * Basic system setup - * - * @brief Setup the AMBA clocks. Ensure proper alignment of copy and zero table entries. - */ -void SystemInitPre(void) __attribute__((section("text_reset"))); - -void SystemInitPre(void) -{ - /* - * Enable debugger. - */ - if (dg_configENABLE_DEBUGGER) - { - ENABLE_DEBUGGER; - } - - /* - * Bandgap has already been set by the bootloader. - * Use fast clocks from now on. - */ - hw_cpm_set_hclk_div(0); - hw_cpm_set_pclk_div(0); - - /* - * Ensure 16-byte alignment for all elements of each entry in the Copy Table. This is - * a requirement imposed by the fast start-up code! If any of the assertions below hits, - * please correct your linker script file accordingly! - */ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) - { - uint32_t *p; - - for (p = &__copy_table_start__; p < &__copy_table_end__; p += 3) - { - ASSERT_WARNING_UNINIT((p[0] & 0xF) == 0); // from - ASSERT_WARNING_UNINIT((p[1] & 0xF) == 0); // to - ASSERT_WARNING_UNINIT((p[2] & 0xF) == 0); // size - } - } - - /* - * Ensure 32-byte alignment for all elements of each entry in the Data Table. This is - * a requirement imposed by the fast start-up code! If any of the assertions below hits, - * please correct your linker script file accordingly! - */ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) - { - uint32_t *p; - - for (p = &__zero_table_start__; p < &__zero_table_end__; p += 2) - { - ASSERT_WARNING_UNINIT((p[0] & 0x1F) == 0); // start at - ASSERT_WARNING_UNINIT((p[1] & 0x1F) == 0); // size - } - } -} - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ - /* - * Make sure we are running on a chip version that the code has been built for. - */ - ASSERT_WARNING_UNINIT(is_compatible_chip_version()); - - /* - * Detect chip version (optionally). - */ - if (dg_configUSE_AUTO_CHIP_DETECTION == 1) - { - black_orca_chip_version = black_orca_get_chip_version(); - - if (!CHIP_IS_AE && !CHIP_IS_BA) - { - // Oldest supported version is AE. - ASSERT_WARNING_UNINIT(0); - } - } - - /* - * Initialize UNINIT variables. - */ - sys_tcs_init(); - - /* - * BOD protection - */ - if (dg_configUSE_BOD == 1) - { - /* BOD has already been enabled at this point but it must be reconfigured */ - hw_cpm_configure_bod_protection(); - } - else - { - hw_cpm_deactivate_bod_protection(); - } - - /* - * Apply default priorities to interrupts. - */ - set_interrupt_priorities(__dialog_interrupt_priorities); - - /* - * If we are executing from RAM, make sure that code written in Flash won't have left the - * system in "unknown" state. - */ - if (dg_configCODE_LOCATION == NON_VOLATILE_IS_NONE) - { - GLOBAL_INT_DISABLE(); - CRG_TOP->PMU_CTRL_REG |= 0xE; - CRG_TOP->PMU_CTRL_REG &= ~1; - GLOBAL_INT_RESTORE(); - } - - /* - * Switch to RC16. - */ - hw_cpm_set_sysclk(SYS_CLK_IS_RC16); // Use RC16 - hw_cpm_disable_xtal16m(); // Disable XTAL16M - - /* - * Set highest access speed for QSPI Flash. - */ - if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) - { - hw_qspi_set_div(HW_QSPI_DIV_1); - } -} - -/** - * Process the TCS - * - * @brief Process the TCS section. - */ -void SystemInitPost(void) -{ - SystemCoreClock = __SYSTEM_CLOCK; - SystemLPClock = LP_CLK_FREQ; - - uint32_t tcs_pairs[TCS_SECTION_LENGTH * 2]; - uint32_t valid_tcs_pairs = 0; - - hw_cpm_start_ldos(); // Make sure all LDOs are as expected - hw_cpm_reset_radio_vdd(); // Set Radio voltage to 1.40V - - /* - * Initialize Flash - */ - if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) - { - qspi_automode_init(); // The bootloader may have left the Flash in wrong mode... - } - - /* - * Retrieve trim values from OTP. - */ - hw_otpc_init(); // Start clock. - hw_otpc_disable(); // Make sure it is in standby mode. - hw_otpc_init(); // Restart clock. - hw_otpc_manual_read_on(false); - - /* - * Apply trim values from OTP. - */ - apply_trim_values_from_otp(tcs_pairs, &valid_tcs_pairs); - - if (dg_configIMAGE_SETUP == PRODUCTION_MODE) - { - ASSERT_ERROR(sys_tcs_is_calibrated_chip); // Uncalibrated chip!!! - } - - hw_otpc_manual_read_off(); - hw_otpc_disable(); - - if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) - { - hw_cpm_enable_qspi_init(); // Enable QSPI init after wakeup - - hw_qspi_set_read_pipe_clock_delay(6); // Set read pipe clock delay to 6 (Last review date: Feb 15, 2016 - 12:25:47) - } - - /* - * All trim values have been loaded from TCS or defaults are used. - */ - sys_tcs_sort_array(); - sys_tcs_apply(tcs_system); - hw_cpm_set_preferred_values(); - -#ifdef OS_BAREMETAL - /* perform clock initialization here, as there is no CPM to do it later for us */ - nortos_clk_setup(); -#endif - - configure_cache(); -} - -uint32_t DA15000_phy_addr(uint32_t addr) -{ - static const uint32 remap[] = - { - MEMORY_ROM_BASE, - MEMORY_OTP_BASE, - MEMORY_QSPIF_BASE, - MEMORY_SYSRAM_BASE, - MEMORY_QSPIF_BASE, - MEMORY_OTP_BASE, - MEMORY_CACHERAM_BASE, - 0 - }; - - if (addr >= MEMORY_REMAPPED_END) - { - return addr; - } - - return addr + remap[REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0)]; -} - diff --git a/examples/platforms/da15000/uart.c b/examples/platforms/da15000/uart.c index 4bd15ccc0..a3e40f11e 100644 --- a/examples/platforms/da15000/uart.c +++ b/examples/platforms/da15000/uart.c @@ -26,16 +26,16 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include - #include +#include "platform-da15000.h" + #include "hw_gpio.h" #include "hw_uart.h" -#include "platform-da15000.h" static bool sUartWriteDone = false; static bool sUartReadDone = false; +static char *sInitBuf = NULL; static uint8_t sUartBuf; static void UartSignalWrite(void *p, uint16_t transferred) @@ -104,6 +104,12 @@ void da15000UartProcess(void) sUartWriteDone = false; otPlatUartSendDone(); } + + if (sInitBuf == NULL) + { + sInitBuf = "\n"; + otPlatUartReceived((uint8_t *)sInitBuf, 1); + } } otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength) @@ -112,4 +118,3 @@ otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength) return OT_ERROR_NONE; } - diff --git a/examples/platforms/da15000/vector_table.S b/examples/platforms/da15000/vector_table.S deleted file mode 100644 index a11fe06fb..000000000 --- a/examples/platforms/da15000/vector_table.S +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file vector_table.S - * Interrupt Vector Table and Patch Table. - */ -.syntax unified -.arch armv6 - m - -.section .stack -.align 3 -.equ Stack_Size, __STACK_SIZE -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -.section .heap -.align 3 -.equ Heap_Size, __HEAP_SIZE -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.if Heap_Size -.space Heap_Size -.endif -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - -.section .isr_vector, "a" -.align 2 -.globl __isr_vector -__isr_vector: -.long __StackTop /* Top of Stack */ -.long Reset_Handler /* Reset Handler */ -.long Default_Handler /* replaced by NMI_Handler after the ISR is copied to retRAM*/ -.long Default_Handler /* replaced by HardFault_Handler after the ISR is copied to retRAM */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long SVC_Handler /* SVCall Handler */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long PendSV_Handler /* PendSV Handler */ -.long SysTick_Handler /* SysTick Handler */ - -/* External interrupts */ -.long BLE_WAKEUP_LP_Handler /* 0 */ -.long BLE_GEN_Handler /* 1 */ -.long FTDF_WAKEUP_Handler /* 2 */ -.long FTDF_GEN_Handler /* 3 */ -.long RFCAL_Handler /* 4 */ -.long COEX_Handler /* 5 */ -.long CRYPTO_Handler /* 6 */ -.long MRM_Handler /* 7 */ -.long UART_Handler /* 8 */ -.long UART2_Handler /* 9 */ -.long I2C_Handler /* 10 */ -.long I2C2_Handler /* 11 */ -.long SPI_Handler /* 12 */ -.long SPI2_Handler /* 13 */ -.long ADC_Handler /* 14 */ -.long KEYBRD_Handler /* 15 */ -.long IRGEN_Handler /* 16 */ -.long WKUP_GPIO_Handler /* 17 */ -.long SWTIM0_Handler /* 18 */ -.long SWTIM1_Handler /* 19 */ -.long QUADEC_Handler /* 20 */ -.long USB_Handler /* 21 */ -.long PCM_Handler /* 22 */ -.long SRC_IN_Handler /* 23 */ -.long SRC_OUT_Handler /* 24 */ -.long VBUS_Handler /* 25 */ -.long DMA_Handler /* 26 */ -.long RF_DIAG_Handler /* 27 */ -.long TRNG_Handler /* 28 */ -.long DCDC_Handler /* 29 */ -.long XTAL16RDY_Handler /* 30 */ -.long RESERVED31_Handler /* 31 */ - -.size __isr_vector, . - __isr_vector - -/* - * Patch Table - * Notice: it crosses the 0x100 boundary - * in cached mode, the first entries will be copied to - * (and accessed from) RAM and others will only lie on - * QSPI flash or OTP. - * - * In C declare: extern uint32_t __patch_table_start[]; - */ -.section .patch_table, "a" -.align 4 -.globl __patch_table_start -__patch_table_start: -/* - * 28 32-bit entries, initialized to "pointer to Default_Patch_Code" - * - * NOTE: we assume that SYS_CTRL_REG.REMAP_INTVECT == 1 - */ -.long Default_Patch_Code_Handler /* 0, in RAM */ -.long Default_Patch_Code_Handler /* 1, in RAM */ -.long Default_Patch_Code_Handler /* 2, in RAM */ -.long Default_Patch_Code_Handler /* 3, in RAM */ -.long Default_Patch_Code_Handler /* 4, in RAM */ -.long Default_Patch_Code_Handler /* 5, in RAM */ -.long Default_Patch_Code_Handler /* 6, in RAM */ -.long Default_Patch_Code_Handler /* 7, in RAM */ -.long Default_Patch_Code_Handler /* 8, in RAM */ -.long Default_Patch_Code_Handler /* 9, in RAM */ -.long Default_Patch_Code_Handler /* 10, in RAM */ -.long Default_Patch_Code_Handler /* 11, in RAM */ -/* - * Chip version: AD - * Entries 12, 13, 14 and 15 are unusable and skipped in the QSPI image, - * to account for the overhead of the QSPI header (16 bytes). - * - * Chip version: AA, AC, AE - * Entries 14 and 15 are unusable and skipped in the QSPI image, - * to account for the overhead of the QSPI header (8 bytes). - * - * The mkimage tool is responsible for stripping the proper entries from the QSPI image. - */ -.long Default_Patch_Code_Handler /* 12 */ -.long Default_Patch_Code_Handler /* 13 */ -.long 0xDEADBEEF /* 14 */ -.long 0xDEADBEEF /* 15 */ -.size __patch_table_start, . - __patch_table_start - -__patch_table_end: - -.section .default_patch_code_handler_section, "a" -.globl Default_Patch_Code_Handler -.align 1 -.thumb -.thumb_func -.type Default_Patch_Code_Handler, % function -Default_Patch_Code_Handler: -bkpt #0 -bkpt #0 - diff --git a/third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h b/third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h deleted file mode 100644 index 187bde671..000000000 --- a/third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup ADAPTERS - * \{ - * \addtogroup RF_ADAPTER - * - * \brief RF adapter - * - * \{ - */ - -/** - ***************************************************************************************** - * - * @file - * - * @brief Radio module access API. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - - - - -#ifndef AD_RF_H_ -#define AD_RF_H_ - -#if dg_configRF_ADAPTER - -#include -#include - -#include "hw_rf.h" - -/** - * @brief Performs RF adapter initialization - */ -void ad_rf_init(void); - -/** - * \brief Retry a failed calibration - * - * This will power-cycle RF, reapply tcs and recommended settings, and - * retry calibration. If calibration fails again, it will reset the system - * (using the wdog) - */ -void ad_rf_retry_calibration(); - -/** - * \brief Start Calibration procedure and check if it succeeds - * - * This will start the calibration procedure, and check if the calibration initial - * part (the iff calibration) succeeds. If not, it will reset the RF block and retry. - * If the calibration still fails after the second attempt, it will trigger a - * watchdog reset - * - */ -static inline void ad_rf_start_and_check_calibration() -{ - if (!hw_rf_start_calibration()) - ad_rf_retry_calibration(); -} - -/** - * \brief Perform RF system initialization. - * - * This will preform a full RF system init, and check if the - * calibration initial part (the iff calibration) succeeds. If not, it will - * reset the RF block and retry. - * If the calibration still fails after the second attempt, it will trigger a - * watchdog reset - * - */ -static inline void ad_rf_system_init() -{ - if (!hw_rf_system_init()) - ad_rf_retry_calibration(); -} - -/** - * \brief Start Calibration procedure and return. - * - * This will block for some time (with interrupts disabled) in order to perform - * The first part of calibration (IFF, DC offset and the start of gain calib). - * - */ -static inline void ad_rf_start_calibration() -{ - ad_rf_start_and_check_calibration(); -} - -/** - * \brief Sets parameters according to their recommended values, taking RF state into account. - * - * Acts like \ref hw_rf_set_recommended_settings but makes sure that the RF power domain is on and - * unconfigured. Disables interrupts. - * - */ -static inline void ad_rf_request_recommended_settings(void) -{ - hw_rf_request_recommended_settings(); -} - -/** - * \brief Requests that the RF is turned on - * - * Requests that the RF is turned on, if not already on. Disables interrupts. - * - * \param [in] mode_ble True, if the rf is needed for ble - * - */ -static inline void ad_rf_request_on(bool mode_ble) -{ - hw_rf_request_on(mode_ble); -} - -/** - * \brief Requests that the RF is turned off - * - * Requests that the RF is turned off, if not already off. - * The RF will be turned off only if there are no more - * requests (ie. all requesters have called ad_rf_request_off()) - * Disables interrupts - * - * \param [in] mode_ble True, if the rf was needed for ble - */ -static inline void ad_rf_request_off(bool mode_ble) -{ - hw_rf_request_off(mode_ble); -} - -#endif /* dg_configRF_ADAPTER */ - -#endif /* AD_RF_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h b/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h index d22e149cc..edc26449a 100644 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h @@ -597,9 +597,10 @@ /** * \brief Enables BLE diagnostic signals. * - * There are 4 diagnostic signal configurations that user can choose from. To enable a specific - * configuration, simply define dg_configBLE_DIAGN_CONFIG with the perspective configuration ID. - * Configuration ID 0 disables BLE diagnostics. + * There are 5 (4 plus the COEX mode, see next table) diagnostic signal configurations that + * user can choose from. To enable a specific configuration, simply define + * dg_configBLE_DIAGN_CONFIG with the perspective configuration ID. Configuration ID 0 disables + * BLE diagnostics. * * ------------------------------------------------------------------------------------------------------ * | Signal | Pin | Config 1 | Config 2 | Config 3 | Config 4 | @@ -620,6 +621,21 @@ * ------------------------------------------------------------------------------------------------------ * | ble_diag7 | P2_3 | ble_event_irq | rf_rx_data | rf_tx_data_valid | ble_event_irq | * ------------------------------------------------------------------------------------------------------ + * + * Coex Mode Diagnostics: The COEX interface multiplexes its diagnostic pins on top of BLE + * diagnostics when option dg_configCOEX_ENABLE_DIAGS is set to 1. However, diagnostic signals + * ble_diag0 and ble_diag1 are unused by the COEX diagnostics and can be used for BLE. More + * specifically, Config 5 enables the following configuration, that can be used simultaneously + * with COEX diagnostics (dg_configCOEX_ENABLE_DIAGS == 1): + * + * ---------------------------------------------- + * | Signal | Pin | Config 5 | + * ---------------------------------------------- + * | ble_diag0 | P3_0 | radcntl_txen | + * ---------------------------------------------- + * | ble_diag1 | P3_1 | radcntl_rxen | + * ---------------------------------------------- + * */ #ifndef dg_configBLE_DIAGN_CONFIG #define dg_configBLE_DIAGN_CONFIG (0) diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h b/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h index b58268a56..0ac9c45f9 100644 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h @@ -174,7 +174,7 @@ #endif /** - * \brief When set to 1, the chip version (DA14680/1-01 or DA14682/3-BA ) will be detected\n + * \brief When set to 1, the chip version (DA14680/1-01 or DA14682/3-00, DA15XXX-00 ) will be detected\n * automatically. * \note It cannot be used in BLE applications because of the different linker scripts\n * that are used. @@ -617,7 +617,7 @@ #endif /** - * \brief Watchdog Service + * \brief Watchdog Service * * - 1: enabled * - 0: disabled @@ -782,7 +782,7 @@ #endif /** - * \brief When set to 1, the USB interface is used. + * \brief When set to 1, the USB interface is used for data transfers. * * \bsp_default_note{\bsp_config_option_app,} */ @@ -1056,7 +1056,7 @@ * This is a deprecated configuration hence not to be defined by an application. * When entering hibernation mode then: * A DA14680/1-01 system reboots only via an interrupt from the WKUP Ctrl or VBUS. - * A DA14682/3-BA system reboots only via an interrupt from the WKUP Ctrl. + * A DA14682/3-00, DA15XXX-00 system reboots only via an interrupt from the WKUP Ctrl. */ #ifdef dg_configLOW_VBAT_HANDLING #error "Configuration option dg_configLOW_VBAT_HANDLING is no longer supported." @@ -1471,6 +1471,16 @@ (SW_CURSOR_PORT == 2 ? &(GPIO->P2_RESET_DATA_REG) : \ (SW_CURSOR_PORT == 3 ? &(GPIO->P3_RESET_DATA_REG) : \ &(GPIO->P4_RESET_DATA_REG))))) +/** + * \brief Enable task monitoring. + * + * \note Task monitoring can only be enabled if RTT or RETARGET is enabled + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configENABLE_TASK_MONITORING +#define dg_configENABLE_TASK_MONITORING (0) +#endif + /* ---------------------------------------------------------------------------------------------- */ /** @@ -1548,7 +1558,13 @@ /* ------------------------------- Arbiter configuration settings ------------------------------- */ /** - * \brief Custom arbiter configuration support. + * \brief Custom arbiter configuration support + * When defined, coex is configurable and priorities can be set: + * -either manually, per mac, using coex api + * -or automatically, by the PTIs provided by each mac + * + * When not defined, coex operates with the default/fixed priority scheme: + * BLE traffic has always higher priority than FTDF. * * \bsp_default_note{\bsp_config_option_app,} */ @@ -1564,6 +1580,32 @@ #ifndef dg_configCOEX_ENABLE_STATS #define dg_configCOEX_ENABLE_STATS (0) #endif + +/** + * \brief Arbiter diagnostics enable + * + * This automatically enables arbiter diagnostic signals (when RF PD is on) + * + * See hw_coex.h for more information. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configCOEX_ENABLE_DIAGS +#define dg_configCOEX_ENABLE_DIAGS (0) +#endif + +/** + * \brief Arbiter diagnostics mode + * + * This is the default mode for arbiter diagnostics. + * + * See hw_coex.h for more information. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configCOEX_DIAGS_MODE +#define dg_configCOEX_DIAGS_MODE (HW_COEX_DIAG_MODE_3) +#endif /* ---------------------------------------------------------------------------------------------- */ /** @@ -1716,12 +1758,85 @@ #ifndef dg_configUSE_IF_PDM #define dg_configUSE_IF_PDM (0) #endif + +/* ---------------------------------------------------------------------------------------------- */ + + /* ---------------------------------------------------------------------------------------------- */ /** * \} */ +/* ------------------------------- USB settings ------------------------------------------------ */ + +/** + * \addtogroup USB_SETTINGS + * + * \brief USB DMA enable configuration settings + * + * The macros in this section are used to enable the DMA with USB and to define the two possible end point to use the DMA for data transfers. + * \{ + */ + +/** + * \brief Enable the DMA for reading/writing data to USB EP.\n + * By default the USB DMA is not enabled.\n + * To enable the DMA for the USB, set this the macro to value (1) in the custom_config_xxx.h file.\n + * When the USB DMA is enabled, the default end points with DMA are EP1 and EP2. \n + * It is possible only one TX and one RX end point to use DMA.\n + * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n + * To change the end points using DMA, set in the the custom_config_xxx.h file the desired values for the macros: + * \par \c dg_configUSB_TX_DMA_EP + * valid values: 1,3,5\n + * default value: 1 + * \par \c dg_configUSB_RX_DMA_EP + * valid values: 2,4,6\n + * default value: 2 + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUSB_DMA_SUPPORT +#define dg_configUSB_DMA_SUPPORT (0) +#endif + + +/** + * \brief The USB TX end point (D-->H) to enable the DMA.\n + * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n + * To change the TX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros. + * \par \c dg_configUSB_TX_DMA_EP + * valid values: 1,3,5\n + * default value: 1 + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUSB_TX_DMA_EP +#define dg_configUSB_TX_DMA_EP (1) +#endif + +/** + * \brief The USB RX end point (D-->H) to enable the DMA.\n + * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n + * To change the RX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros. + * \par \c dg_configUSB_RX_DMA_EP + * valid values: 2,4,6\n + * default value: 2 + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUSB_RX_DMA_EP +#define dg_configUSB_RX_DMA_EP (2) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + + + /* ------------------------------- WKUP settings ------------------------------------------------ */ /** @@ -1744,7 +1859,7 @@ * \brief WKUP latch wakeup (io) source support * * \note In chip revision DA14680/1-01, this feature is implemented in s/w - * \note In chip revision DA14682/3-BA, this feature is implemented in h/w + * \note In chip revision DA14682/3-00, DA15XXX-00, this feature is implemented in h/w * * \bsp_default_note{\bsp_config_option_app,} */ @@ -2464,7 +2579,573 @@ /* ---------------------------------------------------------------------------------------------- */ +/* ---------------------------------- MEMORY LAYOUT CONFIGURATION ------------------------------- */ +/** + * \addtogroup MEMORY_LAYOUT_SETTINGS + * + * \brief Memory layout configuration settings. + * \{ + */ + +/** + * \brief Controls the retention RAM optimization. + * + * - 0 : All RAM is retained. + * - 1 : Retention memory size is optimal. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configOPTIMAL_RETRAM +#define dg_configOPTIMAL_RETRAM (0) +#endif +/** + * \addtogroup OTP_PROJECT_MEMORY_LAYOUT_SETTINGS + * + * \brief Memory layout configuration settings for a OTP project. + * \{ + */ + +/** + * \brief Code size in OTP projects, no product specific. + * + * \note Code size cannot be more than 58K. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CODE_SIZE +#define dg_configOTP_CODE_SIZE ( 58 * 1024) +#endif + +/** + * \brief RAM-block size in cached mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RAM_SIZE +#define dg_configOTP_CACHED_RAM_SIZE (64 * 1024) +#endif + +/** + * \brief Retained-RAM-0-block size in cached mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE +#define dg_configOTP_CACHED_RETRAM_0_SIZE ( 64 * 1024) +#endif + +/** + * \brief Retained-RAM-1-block size in cached mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE +#define dg_configOTP_CACHED_RETRAM_1_SIZE ( 0 * 1024) +#endif + +/** + * \brief Retained-RAM-0-block size in mirror mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RETRAM_0_SIZE +#define dg_configOTP_MIRROR_RETRAM_0_SIZE ( 48 * 1024) +#endif + +/** + * \brief Retained-RAM-1-block size in mirror mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE +#define dg_configOTP_MIRROR_RETRAM_1_SIZE ( 0 * 1024) +#endif + + + +/** + * \brief Retained-RAM-0-block size for optimal retention memory in cached mode, no product specific. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE +#define dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE ( 32 * 1024) +#endif + +/** + * \brief Retained-RAM-1-block size for optimal retention memory in cached mode, no product specific. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE +#define dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE ( 32 * 1024) +#endif + +/** + * \brief RAM-block size in mirror mode, no product specific. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RAM_SIZE +#define dg_configOTP_MIRROR_RAM_SIZE ( 16 * 1024) +#endif + +/** + * \brief Code size in OTP projects for DA14680/1-01. + * + * \note Code size cannot be more than 58K. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CODE_SIZE_AE +#define dg_configOTP_CODE_SIZE_AE dg_configOTP_CODE_SIZE +#endif + +/** + * \brief Code size in OTP projects for DA14682/3-00, DA15XXX-00. + * + * \note Code size cannot be more than 58K. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CODE_SIZE_BB +#define dg_configOTP_CODE_SIZE_BB dg_configOTP_CODE_SIZE +#endif + +/** + * \brief RAM-block size in cached mode for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RAM_SIZE_AE +#define dg_configOTP_CACHED_RAM_SIZE_AE dg_configOTP_CACHED_RAM_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size in cached mode for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE_AE +#define dg_configOTP_CACHED_RETRAM_0_SIZE_AE dg_configOTP_CACHED_RETRAM_0_SIZE +#endif + +/** + * \brief Retained-RAM-1-block size in cached mode for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE_AE +#define dg_configOTP_CACHED_RETRAM_1_SIZE_AE dg_configOTP_CACHED_RETRAM_1_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size for optimal retention memory in cached mode for DA14680/1-01. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE_AE +#define dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE_AE dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE +#endif + +/** + * \brief Retained-RAM-1-block size for optimal retention memory in cached mode for DA14680/1-01. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE_AE +#define dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE_AE dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE +#endif + +/** + * \brief RAM-block size in cached mode for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RAM_SIZE_BB +#define dg_configOTP_CACHED_RAM_SIZE_BB dg_configOTP_CACHED_RAM_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size in cached mode for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE_BB +#define dg_configOTP_CACHED_RETRAM_0_SIZE_BB dg_configOTP_CACHED_RETRAM_0_SIZE +#endif + +/** + * \brief Retained-RAM-1-block size in cached mode for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE_BB +#define dg_configOTP_CACHED_RETRAM_1_SIZE_BB dg_configOTP_CACHED_RETRAM_1_SIZE +#endif + +/** + * \brief RAM-block size in mirror mode for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RAM_SIZE_AE +#define dg_configOTP_MIRROR_RAM_SIZE_AE dg_configOTP_MIRROR_RAM_SIZE +#endif + +/** + * \brief Retained-RAM-1-block size in mirror mode for DA14680/1-01 + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE_AE +#define dg_configOTP_MIRROR_RETRAM_1_SIZE_AE dg_configOTP_MIRROR_RETRAM_1_SIZE +#endif + +/** + * \brief RAM-block size in mirror mode for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RAM_SIZE_BB +#define dg_configOTP_MIRROR_RAM_SIZE_BB dg_configOTP_MIRROR_RAM_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size in mirror mode for DA14682/3-00, DA15XXX-00 + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RETRAM_0_SIZE_BB +#define dg_configOTP_MIRROR_RETRAM_0_SIZE_BB dg_configOTP_MIRROR_RETRAM_0_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size in mirror mode for DA14682/3-00, DA15XXX-00 + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE_BB +#define dg_configOTP_MIRROR_RETRAM_1_SIZE_BB dg_configOTP_MIRROR_RETRAM_1_SIZE +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup QSPI_PROJECT_MEMORY_LAYOUT_SETTINGS + * + * \brief Memory layout configuration settings for a QSPI project + * \{ + */ + +/** + * \brief Code size in QSPI projects, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CODE_SIZE +#define dg_configQSPI_CODE_SIZE (128 * 1024) +#endif + +/** + * \brief RAM-block size in cached mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RAM_SIZE +#define dg_configQSPI_CACHED_RAM_SIZE ( 64 * 1024) +#endif + +/** + * \brief Retained-RAM-0-block size in cached mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE +#define dg_configQSPI_CACHED_RETRAM_0_SIZE ( 64 * 1024) +#endif + +/** + * \brief Retained-RAM-1-block size in cached mode, no product specific. + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE +#define dg_configQSPI_CACHED_RETRAM_1_SIZE ( 0 * 1024) +#endif + +/** + * \brief Retained-RAM-0-block size for optimal retention memory in cached mode, no product specific. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE +#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE ( 32 * 1024) +#endif + +/** + * \brief Retained-RAM-1-block size for optimal retention memory in cached mode, no product specific. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \note Defining the corresponding product-specific configuration macro will override + * this one. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE +#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE ( 32 * 1024) +#endif + +/** + * \brief Code size in QSPI projects for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CODE_SIZE_AE +#define dg_configQSPI_CODE_SIZE_AE dg_configQSPI_CODE_SIZE +#endif + +/** + * \brief Code size in QSPI projects for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CODE_SIZE_BB +#define dg_configQSPI_CODE_SIZE_BB dg_configQSPI_CODE_SIZE +#endif + +/** + * \brief RAM-block size in cached mode for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RAM_SIZE_AE +#define dg_configQSPI_CACHED_RAM_SIZE_AE dg_configQSPI_CACHED_RAM_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size in cached mode for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE_AE +#define dg_configQSPI_CACHED_RETRAM_0_SIZE_AE dg_configQSPI_CACHED_RETRAM_0_SIZE +#endif + +/** + * \brief Retained-RAM-1-block size in cached mode for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE_AE +#define dg_configQSPI_CACHED_RETRAM_1_SIZE_AE dg_configQSPI_CACHED_RETRAM_1_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size for optimal retention memory in cached mode for DA14680/1-01. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE_AE +#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE_AE dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE +#endif + +/** + * \brief Retained-RAM-1-block size for optimal retention memory in cached mode for DA14680/1-01. + * + * \see dg_configOPTIMAL_RETRAM option + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE_AE +#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE_AE dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE +#endif + +/** + * \brief RAM-block size in cached mode for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RAM_SIZE_BB +#define dg_configQSPI_CACHED_RAM_SIZE_BB dg_configQSPI_CACHED_RAM_SIZE +#endif + +/** + * \brief Retained-RAM-0-block size in cached mode for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE_BB +#define dg_configQSPI_CACHED_RETRAM_0_SIZE_BB dg_configQSPI_CACHED_RETRAM_0_SIZE +#endif + +/** + * \brief Retained-RAM-1-block size in cached mode for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE_BB +#define dg_configQSPI_CACHED_RETRAM_1_SIZE_BB dg_configQSPI_CACHED_RETRAM_1_SIZE +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup RAM_PROJECT_MEMORY_LAYOUT_SETTINGS + * + * \brief Memory layout configuration settings for a RAM project + * \{ + */ + +/** + * \brief Code size in RAM projects for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_CODE_SIZE_AE +#define dg_configRAM_CODE_SIZE_AE ( 79 * 1024) +#endif + +/** + * \brief RAM-block size for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_RAM_SIZE_AE +#define dg_configRAM_RAM_SIZE_AE ( 16 * 1024) +#endif + +/** + * \brief Retained-RAM-0-block size for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_RETRAM_0_SIZE_AE +#define dg_configRAM_RETRAM_0_SIZE_AE (128 * 1024 - dg_configRAM_CODE_SIZE_AE) +#endif + +/** + * \brief Retained-RAM-1-block size for DA14680/1-01. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_RETRAM_1_SIZE_AE +#define dg_configRAM_RETRAM_1_SIZE_AE ( 0 * 1024) +#endif + +/** + * \brief Code size in RAM projects for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_CODE_SIZE_BB +#define dg_configRAM_CODE_SIZE_BB (144 * 1024) +#endif + +/** + * \brief RAM-block size for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_RAM_SIZE_BB +#define dg_configRAM_RAM_SIZE_BB ( 15 * 1024) +#endif + +/** + * \brief Retained-RAM-0-block size for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_RETRAM_0_SIZE_BB +#define dg_configRAM_RETRAM_0_SIZE_BB ( 49 * 1024) +#endif + +/** + * \brief Retained-RAM-0-block size for DA14682/3-00, DA15XXX-00. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configRAM_RETRAM_1_SIZE_BB +#define dg_configRAM_RETRAM_1_SIZE_BB ( 0 * 1024) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + + +/** + * \} + */ #endif /* BSP_DEFAULTS_H_ */ diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h b/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h index e64160c3b..63dd13ce1 100644 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h @@ -126,7 +126,7 @@ #define BLACK_ORCA_MB_REV_D 2 /* - * The cache associtivity options. + * The cache associativity options. */ #define CACHE_ASSOC_AS_IS (-1) /// leave as set by the ROM booter #define CACHE_ASSOC_DIRECT_MAP 0 /// direct-mapped diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h b/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h index 3ce3c0c5b..1a9b24033 100644 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h @@ -43,7 +43,7 @@ * * *************************************************************************************** -*/ + */ #ifndef BSP_FEM_H_ #define BSP_FEM_H_ diff --git a/third_party/dialog/DialogSDK/bsp/include/DA14680BA.h b/third_party/dialog/DialogSDK/bsp/include/DA14680BB.h old mode 100644 new mode 100755 similarity index 99% rename from third_party/dialog/DialogSDK/bsp/include/DA14680BA.h rename to third_party/dialog/DialogSDK/bsp/include/DA14680BB.h index 66febdf9e..801e5161a --- a/third_party/dialog/DialogSDK/bsp/include/DA14680BA.h +++ b/third_party/dialog/DialogSDK/bsp/include/DA14680BB.h @@ -1,4 +1,6 @@ -/* + /** + **************************************************************************************** + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -23,13 +25,18 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * - * @file DA14680BA.h - * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for DA14680BA from Dialog. + * @file DA14680BB.h + * + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * DA14680BB from Dialog. + * * @version V1.2 - * @date 9. August 2016 - * @note Generated with SVDConv V2.87g - * from CMSIS SVD File 'DA14680BA.xml' - * Version 1.2 + * @date 14. June 2017 + * + * @note Generated with SVDConv V2.87l + * from CMSIS SVD File 'DA14680BB.xml' Version 1.2, + * + ***************************************************************************************** */ @@ -38,13 +45,12 @@ * @{ */ - -/** @addtogroup DA14680BA +/** @addtogroup DA14680BB * @{ */ -#ifndef DA14680BA_H -#define DA14680BA_H +#ifndef DA14680BB_H +#define DA14680BB_H #ifdef __cplusplus extern "C" { @@ -65,7 +71,7 @@ typedef enum { SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* -------------------- DA14680BA Specific Interrupt Numbers -------------------- */ +/* -------------------- DA14680BB Specific Interrupt Numbers -------------------- */ BLE_WAKEUP_LP_IRQn = 0, /*!< 0 BLE_WAKEUP_LP */ BLE_GEN_IRQn = 1, /*!< 1 BLE_GEN */ FTDF_WAKEUP_IRQn = 2, /*!< 2 FTDF_WAKEUP */ @@ -101,7 +107,7 @@ typedef enum { } IRQn_Type; -/** @addtogroup Configuration_of_CMSIS_DA14680BA +/** @addtogroup Configuration_of_CMSIS_DA14680BB * @{ */ @@ -118,7 +124,7 @@ typedef enum { /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_DA14680.h" /*!< DA14680BA System */ +#include "system_DA14680.h" /*!< DA14680BB System */ /* ================================================================================ */ @@ -126,7 +132,7 @@ typedef enum { /* ================================================================================ */ -/** @addtogroup Device_Peripheral_Registers_DA14680BA +/** @addtogroup Device_Peripheral_Registers_DA14680BB * @{ */ @@ -469,7 +475,7 @@ typedef struct { /*!< (@ 0x50000000) CRG_TOP __I uint32_t RESERVED2[2]; __IO uint16_t CLK_32K_REG; /*!< (@ 0x50000020) 32 kHz oscillator register */ __IO uint16_t CLK_16M_REG; /*!< (@ 0x50000022) 16 MHz RC and xtal oscillator register */ - __IO uint16_t CLK_RCX20K_REG; /*!< (@ 0x50000024) 20KHz RXC-oscillator control register */ + __IO uint16_t CLK_RCX20K_REG; /*!< (@ 0x50000024) RCX-oscillator control register */ __I uint16_t RESERVED3; __IO uint16_t BANDGAP_REG; /*!< (@ 0x50000028) bandgap trimming */ __IO uint16_t ANA_STATUS_REG; /*!< (@ 0x5000002A) status bit of analog (power management) circuits */ @@ -490,7 +496,7 @@ typedef struct { /*!< (@ 0x50000000) CRG_TOP __IO uint16_t XTALRDY_STAT_REG; /*!< (@ 0x50000052) Difference between XTAL_OK and XTALRDY_IRQ in LP clock cycles */ __IO uint16_t LDO_CTRL3_REG; /*!< (@ 0x50000054) Retention LDO control register */ - __I uint16_t RESERVED6; + __IO uint16_t XTAL16M_CTRL_REG; /*!< (@ 0x50000056) Control register for XTAL16M */ __IO uint16_t XTAL16M_START_REG; /*!< (@ 0x50000058) Xtal frequency trimming register during startup */ __IO uint16_t XTAL16M_RAMP_REG; /*!< (@ 0x5000005A) Xtal frequency trimming register during ramping */ __IO uint16_t XTAL16M_TRSTAT_REG; /*!< (@ 0x5000005C) Read back value of current XTAL trimming */ @@ -1901,11 +1907,13 @@ typedef struct { /*!< (@ 0x50005000) TRNG Str */ typedef struct { /*!< (@ 0x50001000) UART Structure */ - __IO uint16_t UART_RBR_THR_DLL_REG; /*!< (@ 0x50001000) Receive Buffer Register */ + __IO uint16_t UART_RBR_THR_DLL_REG; /*!< (@ 0x50001000) Receive Buffer Register/Transmit Holding Register/Divisor + Latch Low */ __I uint16_t RESERVED; - __IO uint16_t UART_IER_DLH_REG; /*!< (@ 0x50001004) Interrupt Enable Register */ + __IO uint16_t UART_IER_DLH_REG; /*!< (@ 0x50001004) Interrupt Enable Register/Divisor Latch High */ __I uint16_t RESERVED1; - __IO uint16_t UART_IIR_FCR_REG; /*!< (@ 0x50001008) Interrupt Identification Register */ + __IO uint16_t UART_IIR_FCR_REG; /*!< (@ 0x50001008) Interrupt Identification Register/FIFO Control + Register */ __I uint16_t RESERVED2; __IO uint16_t UART_LCR_REG; /*!< (@ 0x5000100C) Line Control Register */ __I uint16_t RESERVED3; @@ -1943,9 +1951,10 @@ typedef struct { /*!< (@ 0x50001000) UART Str */ typedef struct { /*!< (@ 0x50001100) UART2 Structure */ - __IO uint16_t UART2_RBR_THR_DLL_REG; /*!< (@ 0x50001100) Receive Buffer Register */ + __IO uint16_t UART2_RBR_THR_DLL_REG; /*!< (@ 0x50001100) Receive Buffer Register/Transmit Holding Register/Divisor + Latch Low */ __I uint16_t RESERVED; - __IO uint16_t UART2_IER_DLH_REG; /*!< (@ 0x50001104) Interrupt Enable Register */ + __IO uint16_t UART2_IER_DLH_REG; /*!< (@ 0x50001104) Interrupt Enable Register/Divisor Latch High */ __I uint16_t RESERVED1; __IO uint16_t UART2_IIR_FCR_REG; /*!< (@ 0x50001108) Interrupt Identification Register/FIFO Control Register */ @@ -1994,11 +2003,11 @@ typedef struct { /*!< (@ 0x50001100) UART2 St __I uint16_t RESERVED23; __IO uint16_t UART2_FAR_REG; /*!< (@ 0x50001170) FIFO Access Register */ __I uint16_t RESERVED24[5]; - __IO uint16_t UART2_USR_REG; /*!< (@ 0x5000117C) UART Status register. */ + __IO uint16_t UART2_USR_REG; /*!< (@ 0x5000117C) UART Status Register */ __I uint16_t RESERVED25; __IO uint16_t UART2_TFL_REG; /*!< (@ 0x50001180) Transmit FIFO Level */ __I uint16_t RESERVED26; - __IO uint16_t UART2_RFL_REG; /*!< (@ 0x50001184) Receive FIFO Level. */ + __IO uint16_t UART2_RFL_REG; /*!< (@ 0x50001184) Receive FIFO Level */ __I uint16_t RESERVED27; __IO uint16_t UART2_SRR_REG; /*!< (@ 0x50001188) Software Reset Register. */ __I uint16_t RESERVED28; @@ -4329,6 +4338,18 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos (5UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bit 5) */ #define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk (0x20UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bitfield-Mask: 0x01) */ +/* -------------------------- CRG_TOP_XTAL16M_CTRL_REG -------------------------- */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_FREQ_TRIM_SW2_AMP_Pos (0UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_FREQ_TRIM_SW2_AMP (Bit 0) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_FREQ_TRIM_SW2_AMP_Msk (0x7UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_FREQ_TRIM_SW2_AMP (Bitfield-Mask: 0x07) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_AMP_REG_SIG_SEL_Pos (3UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_AMP_REG_SIG_SEL (Bit 3) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_AMP_REG_SIG_SEL_Msk (0x8UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_AMP_REG_SIG_SEL (Bitfield-Mask: 0x01) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_TST_AON_Pos (4UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_TST_AON (Bit 4) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_TST_AON_Msk (0x30UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_TST_AON (Bitfield-Mask: 0x03) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_SH_OVERRULE_Pos (6UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_SH_OVERRULE (Bit 6) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_SH_OVERRULE_Msk (0xc0UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_SH_OVERRULE (Bitfield-Mask: 0x03) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_ENABLE_ZERO_Pos (8UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_ENABLE_ZERO (Bit 8) */ +#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_ENABLE_ZERO_Msk (0x100UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_ENABLE_ZERO (Bitfield-Mask: 0x01) */ + /* -------------------------- CRG_TOP_XTAL16M_START_REG ------------------------- */ #define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos (0UL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bit 0) */ #define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk (0xffUL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bitfield-Mask: 0xff) */ @@ -11048,6 +11069,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define UART_UART_IER_DLH_REG_ETBEI_dlh1_Msk (0x2UL) /*!< UART UART_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01) */ #define UART_UART_IER_DLH_REG_ELSI_dhl2_Pos (2UL) /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bit 2) */ #define UART_UART_IER_DLH_REG_ELSI_dhl2_Msk (0x4UL) /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01) */ +#define UART_UART_IER_DLH_REG_EDSSI_dlh3_Pos (3UL) /*!< UART UART_IER_DLH_REG: EDSSI_dlh3 (Bit 3) */ +#define UART_UART_IER_DLH_REG_EDSSI_dlh3_Msk (0x8UL) /*!< UART UART_IER_DLH_REG: EDSSI_dlh3 (Bitfield-Mask: 0x01) */ +#define UART_UART_IER_DLH_REG_dlh6_4_Pos (4UL) /*!< UART UART_IER_DLH_REG: dlh6_4 (Bit 4) */ +#define UART_UART_IER_DLH_REG_dlh6_4_Msk (0x70UL) /*!< UART UART_IER_DLH_REG: dlh6_4 (Bitfield-Mask: 0x07) */ #define UART_UART_IER_DLH_REG_PTIME_dlh7_Pos (7UL) /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bit 7) */ #define UART_UART_IER_DLH_REG_PTIME_dlh7_Msk (0x80UL) /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01) */ @@ -11148,6 +11173,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Msk (0x2UL) /*!< UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01) */ #define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Pos (2UL) /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bit 2) */ #define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Msk (0x4UL) /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01) */ +#define UART2_UART2_IER_DLH_REG_EDSSI_dlh3_Pos (3UL) /*!< UART2 UART2_IER_DLH_REG: EDSSI_dlh3 (Bit 3) */ +#define UART2_UART2_IER_DLH_REG_EDSSI_dlh3_Msk (0x8UL) /*!< UART2 UART2_IER_DLH_REG: EDSSI_dlh3 (Bitfield-Mask: 0x01) */ +#define UART2_UART2_IER_DLH_REG_dlh6_4_Pos (4UL) /*!< UART2 UART2_IER_DLH_REG: dlh6_4 (Bit 4) */ +#define UART2_UART2_IER_DLH_REG_dlh6_4_Msk (0x70UL) /*!< UART2 UART2_IER_DLH_REG: dlh6_4 (Bitfield-Mask: 0x07) */ #define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Pos (7UL) /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bit 7) */ #define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Msk (0x80UL) /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01) */ @@ -12112,7 +12141,7 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group DA14680BA */ +/** @} */ /* End of group DA14680BB */ /** @} */ /* End of group Dialog */ #ifdef __cplusplus @@ -12120,5 +12149,5 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #endif -#endif /* DA14680BA_H */ +#endif /* DA14680BB_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h b/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h index abc162bc2..587ed989b 100644 --- a/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h +++ b/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h @@ -78,8 +78,8 @@ # error "Unknown chip stepping for revision A -- check the value of dg_configBLACK_ORCA_IC_STEP" # endif #elif dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B -# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_A -# include "DA14680BA.h" +# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_B +# include "DA14680BB.h" # else # error "Unknown chip stepping for revision B -- check the value of dg_configBLACK_ORCA_IC_STEP" # endif @@ -287,7 +287,7 @@ extern uint32_t black_orca_chip_version; #define CHIP_IS_AE (black_orca_chip_version == BLACK_ORCA_IC_VERSION(A, E)) -#define CHIP_IS_BA (black_orca_chip_version == BLACK_ORCA_IC_VERSION(B, A)) +#define CHIP_IS_BB (black_orca_chip_version == BLACK_ORCA_IC_VERSION(B, B)) /** * \brief Get the chip version of the system, at runtime. @@ -310,8 +310,8 @@ __RETAINED_CODE void hw_cpm_assert_trigger_gpio(void); */ #define ASSERT_WARNING(a) \ { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - if (!(a)) { \ + if (!(a)) { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ __asm volatile ( " cpsid i " ); \ GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ hw_cpm_assert_trigger_gpio(); \ @@ -349,8 +349,8 @@ __RETAINED_CODE void hw_cpm_assert_trigger_gpio(void); */ #define ASSERT_WARNING_UNINIT(a) \ { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - if (!(a)) { \ + if (!(a)) { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ __asm volatile ( " cpsid i " ); \ GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ do {} while(1); \ @@ -583,6 +583,41 @@ void __aeabi_memset(void *dest, size_t n, int c); #define REG_CLR_FIELD(base, reg, field, var) \ var &= ~(base ## _ ## reg ## _ ## field ## _Msk) +/** + * \brief Get the address of a register value by index (provided a register interval) + * + * \note The register interval should be an exact multiple of the register's base size. For example, + * if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result + * will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by + * the interval value (in bytes) to find the actual offset of the register. + * + * Returns a register address value by index + */ +#define REG_GET_ADDR_INDEXED(base, reg, interval, index) \ + ((&base->reg) + (((intptr_t) index) * ((interval) / sizeof(base->reg)))) + +/** + * \brief Return the value of a register field by index (provided a register interval). + * + * e.g. + * \code + * uint16_t val; + * uint16_t index = 2 + * + * val = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, REG_EXP_SA_L, 0x10, index) + * + * ... + * \endcode + * + * \note The register interval should be an exact multiple of the register's base size. For example, + * if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result + * will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by + * the interval value (in bytes) to find the actual offset of the register. + * + */ +#define REG_GETF_INDEXED(base, reg, field, interval, index) \ + (((*REG_GET_ADDR_INDEXED(base, reg, interval, index)) & \ + (base ## _ ## reg ## _ ## field ## _Msk)) >> (base ## _ ## reg ## _ ## field ## _Pos)) /** * \brief Return the value of a register field. diff --git a/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld b/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld index ec6567c75..a8105d7c1 100755 --- a/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld +++ b/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld @@ -1,29 +1,32 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. +/** + **************************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** */ MEMORY diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h index 179089588..c6d21aaf1 100644 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h @@ -15,14 +15,6 @@ * * @brief Access QSPI flash when running in auto mode * - * The QSPI controller allows to execute code directly from QSPI flash. - * When code is executing from flash, it is not possible to reprogram the flash. - * To be able to modify the flash when it is used for code execution, it must me assured that - * for the time needed to erase/write, no code is running from flash. - * To achieve this, the code in this module is executed from the RAM. - * Code in this module will not access any other functions or constant variables that could reside - * in flash. - * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -70,15 +62,11 @@ #define __DBG_QSPI_VOLATILE__ #endif - /* * Defines (generic) */ /* Macros to put functions that need to be copied to ram in one section (retained) */ -#define QSPI_SECTION __attribute__((section ("text_retained"), optimize ("no-tree-switch-conversion"))) -#define QSPI_SECTION_NO_INLINE __attribute__ ((section ("text_retained"))) __attribute__ ((noinline)) - typedef struct qspi_ucode_s { const uint32_t *code; uint8_t size; @@ -182,12 +170,12 @@ static inline const void *qspi_automode_addr(uint32_t addr) /** * \brief Power up flash */ -QSPI_SECTION void qspi_automode_flash_power_up(void); +__RETAINED_CODE void qspi_automode_flash_power_up(void); /** * \brief Set QSPI Flash into power down mode */ -QSPI_SECTION void qspi_automode_flash_power_down(void); +__RETAINED_CODE void qspi_automode_flash_power_down(void); /** * \brief Init QSPI controller diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h index 8b11078f2..e964e5027 100644 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h @@ -43,6 +43,7 @@ * **************************************************************************************** */ + #ifndef _QSPI_COMMON_H_ #define _QSPI_COMMON_H_ @@ -162,8 +163,8 @@ static uint8_t flash_read_status_register(void); static void flash_write_status_register(uint8_t value); static void flash_write_enable(void); static void qspi_automode_set_dummy_bytes_count(uint8_t count); -static bool flash_is_busy(void); -static inline bool flash_erase_program_in_progress(void); +static inline bool flash_erase_program_in_progress(void) __attribute__((always_inline)); +static inline bool flash_is_busy(void) __attribute__((always_inline)); #endif /* _QSPI_COMMON_H_ */ /** diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h index eb37fd3bb..774da1618 100644 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h @@ -41,6 +41,7 @@ * **************************************************************************************** */ + #ifndef _QSPI_W32Q80EW_H_ #define _QSPI_W32Q80EW_H_ @@ -95,12 +96,12 @@ static const qspi_flash_config_t flash_w25q80ew_config = { const qspi_flash_config_t* const flash_config = &flash_w25q80ew_config; #endif -QSPI_SECTION static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk) +__RETAINED_CODE static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk) { } -QSPI_SECTION static uint8_t flash_w25q80ew_get_dummy_bytes(void) +__RETAINED_CODE static uint8_t flash_w25q80ew_get_dummy_bytes(void) { return 2; } diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h index 38e6eb07d..0c183ac75 100644 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h @@ -42,6 +42,7 @@ * **************************************************************************************** */ + #ifndef _QSPI_WINBOND_H_ #define _QSPI_WINBOND_H_ @@ -155,7 +156,8 @@ static void flash_w25q_deactivate_command_entry_mode(void); * * \note This function blocks until the Flash has processed the command. */ -QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_wre_volatile(void) +static inline void flash_w25q_wre_volatile(void) __attribute__((always_inline)) __attribute__((unused)); +static inline void flash_w25q_wre_volatile(void) { uint8_t cmd[] = { W25Q_WRITE_ENABLE_NON_VOL }; @@ -165,7 +167,8 @@ QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_wre_volatile( while (flash_is_busy()); } -QSPI_SECTION __attribute__((unused)) static inline uint8_t flash_w25q_read_status_register_2(void) +static inline uint8_t flash_w25q_read_status_register_2(void) __attribute__((always_inline)); +static inline uint8_t flash_w25q_read_status_register_2(void) { __DBG_QSPI_VOLATILE__ uint8_t status; uint8_t cmd[] = { W25Q_READ_STATUS_REGISTER2 }; @@ -184,7 +187,8 @@ QSPI_SECTION __attribute__((unused)) static inline uint8_t flash_w25q_read_statu * value has been actually written is done though. It is up to the caller to decide whether * such verification is needed or not and execute it on its own. */ -QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_write_status_register_2(uint8_t value) +static inline void flash_w25q_write_status_register_2(uint8_t value) __attribute__((always_inline)); +static inline void flash_w25q_write_status_register_2(uint8_t value) { uint8_t cmd[] = { W25Q_WRITE_STATUS_REGISTER2, value }; @@ -194,7 +198,8 @@ QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_write_status_ while (flash_is_busy()); } -QSPI_SECTION static inline void flash_w25q_enable_quad_mode(void) +static inline void flash_w25q_enable_quad_mode(void) __attribute__((always_inline)); +static inline void flash_w25q_enable_quad_mode(void) { uint8_t status; @@ -205,7 +210,7 @@ QSPI_SECTION static inline void flash_w25q_enable_quad_mode(void) } } -QSPI_SECTION static bool flash_w25q_is_suspended(void) +__RETAINED_CODE static bool flash_w25q_is_suspended(void) { __DBG_QSPI_VOLATILE__ uint8_t status; @@ -213,7 +218,7 @@ QSPI_SECTION static bool flash_w25q_is_suspended(void) return (status & W25Q_STATUS2_SUS_MASK) != 0; } -QSPI_SECTION static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density) +__RETAINED_CODE static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density) { flash_activate_command_entry_mode(); @@ -222,7 +227,7 @@ QSPI_SECTION static void flash_w25q_initialize(uint8_t device_type, uint8_t devi flash_deactivate_command_entry_mode(); } -QSPI_SECTION static void flash_w25q_deactivate_command_entry_mode(void) +__RETAINED_CODE static void flash_w25q_deactivate_command_entry_mode(void) { } diff --git a/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c b/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c index 7fe7ab474..b0f2f2c8c 100644 --- a/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c +++ b/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c @@ -38,6 +38,11 @@ #include #include "sdk_defs.h" +#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) +#include "osal.h" +#include "sys_power_mgr.h" +#endif + #include "hw_cpm.h" #include "hw_qspi.h" @@ -83,18 +88,18 @@ * Use with extreme caution!! */ #if dg_configFLASH_AUTODETECT == 1 -#define FLASH_AUTODETECT 1 // Enable Flash auto-detection + #define FLASH_AUTODETECT 1 // Enable Flash auto-detection #else -#if !defined(dg_configFLASH_MANUFACTURER_ID) -#error Please define dg_configFLASH_MANUFACTURER_ID !!! -#endif -#if !defined(dg_configFLASH_DEVICE_TYPE) -#error Please define dg_configFLASH_DEVICE_TYPE !!! -#endif -#if !defined(dg_configFLASH_DENSITY) -#error Please define dg_configFLASH_DENSITY !!! -#endif -#define FLASH_AUTODETECT 0 + #if !defined(dg_configFLASH_MANUFACTURER_ID) + #error Please define dg_configFLASH_MANUFACTURER_ID !!! + #endif + #if !defined(dg_configFLASH_DEVICE_TYPE) + #error Please define dg_configFLASH_DEVICE_TYPE !!! + #endif + #if !defined(dg_configFLASH_DENSITY) + #error Please define dg_configFLASH_DENSITY !!! + #endif + #define FLASH_AUTODETECT 0 #endif #if FLASH_AUTODETECT == 1 @@ -110,16 +115,15 @@ #if (FLASH_AUTODETECT == 1) -static const qspi_flash_config_t *flash_config_table[] = -{ - &flash_w25q80ew_config, // This is the default one - &flash_mx25u51245_config, - &flash_gd25lq80b_config, +static const qspi_flash_config_t* flash_config_table[] = { + &flash_w25q80ew_config, // This is the default one + &flash_mx25u51245_config, + &flash_gd25lq80b_config, }; __RETAINED static qspi_flash_config_t flash_autodetect_config; -__RETAINED qspi_flash_config_t *flash_config; +__RETAINED qspi_flash_config_t * flash_config; #endif @@ -140,24 +144,21 @@ static inline void qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) __attribute__((alway static inline void qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) { - if (mode == HW_QSPI_BUS_MODE_SINGLE) - { - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE); - QSPIC->QSPIC_CTRLMODE_REG |= - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_DAT, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_DAT, 1); - } - else - { + if (mode == HW_QSPI_BUS_MODE_SINGLE) { + QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE); + QSPIC->QSPIC_CTRLMODE_REG |= + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_DAT, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_DAT, 1); + } else { #if QUAD_MODE - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD); - QSPIC->QSPIC_CTRLMODE_REG &= - ~(BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1)); + QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD); + QSPIC->QSPIC_CTRLMODE_REG &= + ~(BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1)); #endif - } + } } /** @@ -169,7 +170,7 @@ static inline void qspi_set_automode(bool automode) __attribute__((always_inline static inline void qspi_set_automode(bool automode) { - REG_SETF(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_AUTO_MD, automode); + REG_SETF(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_AUTO_MD, automode); } /** @@ -181,18 +182,17 @@ static inline void qspi_set_automode(bool automode) * \note The data are transferred as bytes (8 bits wide). No optimization is done in trying to use * faster access methods (i.e. transfer words instead of bytes whenever it is possible). */ -QSPI_SECTION static void qspi_write(const uint8_t *wbuf, size_t wlen) +__RETAINED_CODE static void qspi_write(const uint8_t *wbuf, size_t wlen) { - size_t i; + size_t i; - hw_qspi_cs_enable(); + hw_qspi_cs_enable(); - for (i = 0; i < wlen; ++i) - { - hw_qspi_write8(wbuf[i]); - } + for (i = 0; i < wlen; ++i) { + hw_qspi_write8(wbuf[i]); + } - hw_qspi_cs_disable(); + hw_qspi_cs_disable(); } /** @@ -207,63 +207,53 @@ QSPI_SECTION static void qspi_write(const uint8_t *wbuf, size_t wlen) * \note The data are transferred as bytes (8 bits wide). No optimization is done in trying to use * faster access methods (i.e. transfer words instead of bytes whenever it is possible). */ -QSPI_SECTION static void qspi_transact(const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, size_t rlen) +__RETAINED_CODE static void qspi_transact(const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, size_t rlen) { - size_t i; + size_t i; - hw_qspi_cs_enable(); + hw_qspi_cs_enable(); - for (i = 0; i < wlen; ++i) - { - hw_qspi_write8(wbuf[i]); - } + for (i = 0; i < wlen; ++i) { + hw_qspi_write8(wbuf[i]); + } - for (i = 0; i < rlen; ++i) - { - rbuf[i] = hw_qspi_read8(); - } + for (i = 0; i < rlen; ++i) { + rbuf[i] = hw_qspi_read8(); + } - hw_qspi_cs_disable(); + hw_qspi_cs_disable(); } -QSPI_SECTION static inline bool flash_erase_program_in_progress(void) __attribute__((always_inline)); -QSPI_SECTION static inline bool flash_erase_program_in_progress(void) +static inline bool flash_erase_program_in_progress(void) { - __DBG_QSPI_VOLATILE__ uint8_t status; - uint8_t cmd[] = { flash_config->read_erase_progress_opcode }; + __DBG_QSPI_VOLATILE__ uint8_t status; + uint8_t cmd[] = { flash_config->read_erase_progress_opcode }; - qspi_transact(cmd, 1, &status, 1); + qspi_transact(cmd, 1, &status, 1); - return ((status & (1 << flash_config->erase_in_progress_bit)) != 0) == flash_config->erase_in_progress_bit_high_level; + return ((status & (1 << flash_config->erase_in_progress_bit)) != 0) == flash_config->erase_in_progress_bit_high_level; } -QSPI_SECTION static inline bool flash_is_busy(void) __attribute__((always_inline)); -QSPI_SECTION static inline bool flash_is_busy(void) +static inline bool flash_is_busy(void) { - return (flash_read_status_register() & FLASH_STATUS_BUSY_MASK) != 0; + return (flash_read_status_register() & FLASH_STATUS_BUSY_MASK) != 0; } /** * \brief Exit from continuous mode. */ -QSPI_SECTION static inline void flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE break_seq_size) __attribute__(( - always_inline)); - -QSPI_SECTION static inline void flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE break_seq_size) +__RETAINED_CODE static void flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE break_seq_size) { - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_EXIT_CONTINUOUS_MODE); - - if (break_seq_size == HW_QSPI_BREAK_SEQ_SIZE_2B) - { + hw_qspi_cs_enable(); hw_qspi_write8(CMD_EXIT_CONTINUOUS_MODE); - } + if (break_seq_size == HW_QSPI_BREAK_SEQ_SIZE_2B) { + hw_qspi_write8(CMD_EXIT_CONTINUOUS_MODE); + } + hw_qspi_cs_disable(); - hw_qspi_cs_disable(); - - while (flash_is_busy()); + while (flash_is_busy()); } /** @@ -273,18 +263,18 @@ QSPI_SECTION static inline void flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SI * * \note The function blocks until the Flash executes the command. */ -QSPI_SECTION __attribute__((unused)) static uint8_t flash_get_id(void) +__RETAINED_CODE __attribute__((unused)) static uint8_t flash_get_id(void) { - uint8_t id; + uint8_t id; - hw_qspi_cs_enable(); - hw_qspi_write32(CMD_RELEASE_POWER_DOWN); - id = hw_qspi_read8(); - hw_qspi_cs_disable(); + hw_qspi_cs_enable(); + hw_qspi_write32(CMD_RELEASE_POWER_DOWN); + id = hw_qspi_read8(); + hw_qspi_cs_disable(); - while (flash_is_busy()); + while (flash_is_busy()); - return id; + return id; } /** @@ -297,23 +287,18 @@ QSPI_SECTION __attribute__((unused)) static uint8_t flash_get_id(void) * \note This function blocks until the Flash has processed the command and it will be repeated if, * for any reason, the command was not successfully executed by the Flash. */ -QSPI_SECTION static void flash_write_enable(void) +__RETAINED_CODE static void flash_write_enable(void) { - __DBG_QSPI_VOLATILE__ uint8_t status; - uint8_t cmd[] = { CMD_WRITE_ENABLE }; + __DBG_QSPI_VOLATILE__ uint8_t status; + uint8_t cmd[] = { CMD_WRITE_ENABLE }; - do - { - qspi_write(cmd, 1); - - /* Verify */ - do - { - status = flash_read_status_register(); - } - while (status & FLASH_STATUS_BUSY_MASK); - } - while (!(status & FLASH_STATUS_WEL_MASK)); + do { + qspi_write(cmd, 1); + /* Verify */ + do { + status = flash_read_status_register(); + } while (status & FLASH_STATUS_BUSY_MASK); + } while (!(status & FLASH_STATUS_WEL_MASK)); } /** @@ -321,14 +306,14 @@ QSPI_SECTION static void flash_write_enable(void) * * \return uint8_t The value of the Status Register 1 of the Flash. */ -QSPI_SECTION static uint8_t flash_read_status_register(void) +__RETAINED_CODE static uint8_t flash_read_status_register(void) { - __DBG_QSPI_VOLATILE__ uint8_t status; - uint8_t cmd[] = { CMD_READ_STATUS_REGISTER }; + __DBG_QSPI_VOLATILE__ uint8_t status; + uint8_t cmd[] = { CMD_READ_STATUS_REGISTER }; - qspi_transact(cmd, 1, &status, 1); + qspi_transact(cmd, 1, &status, 1); - return status; + return status; } /** @@ -340,14 +325,14 @@ QSPI_SECTION static uint8_t flash_read_status_register(void) * value has been actually written is done though. It is up to the caller to decide whether * such verification is needed or not and execute it on its own. */ -QSPI_SECTION __attribute__((unused)) static void flash_write_status_register(uint8_t value) +__RETAINED_CODE __attribute__((unused)) static void flash_write_status_register(uint8_t value) { - uint8_t cmd[2] = { CMD_WRITE_STATUS_REGISTER, value }; + uint8_t cmd[2] = { CMD_WRITE_STATUS_REGISTER, value }; - qspi_write(cmd, 2); + qspi_write(cmd, 2); - /* Wait for the Flash to process the command */ - while (flash_is_busy()); + /* Wait for the Flash to process the command */ + while (flash_is_busy()); } /** @@ -367,15 +352,15 @@ void fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t dest) __attribu static inline void fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t dest) { - __asm volatile("copy: \n" - " ldmia %[start]!, {r3} \n" - " str r3, [%[dest]] \n" - " cmp %[start], %[end] \n" - " blt copy \n" - : - : /* output */ - [start] "l"(start), [end] "r"(end), [dest] "l"(dest) : /* inputs (%0, %1, %2) */ - "r3"); /* registers that are destroyed */ + __asm volatile( "copy: \n" + " ldmia %[start]!, {r3} \n" + " str r3, [%[dest]] \n" + " cmp %[start], %[end] \n" + " blt copy \n" + : + : /* output */ + [start] "l" (start), [end] "r" (end), [dest] "l" (dest) : /* inputs (%0, %1, %2) */ + "r3"); /* registers that are destroyed */ } /** @@ -392,107 +377,89 @@ static inline void fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t d * issue another flash_write_page() call in order to write the remaining data to the next * page. */ -QSPI_SECTION static size_t flash_write_page(uint32_t addr, const uint8_t *buf, uint16_t size) +__RETAINED_CODE static size_t flash_write_page(uint32_t addr, const uint8_t *buf, uint16_t size) { - size_t i = 0; - size_t odd = ((uint32_t) buf) & 3; - size_t size_aligned32; - size_t tmp; + size_t i = 0; + size_t odd = ((uint32_t) buf) & 3; + size_t size_aligned32; + size_t tmp; - DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_PAGE_PROG); + DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_PAGE_PROG); - flash_write_enable(); + flash_write_enable(); - /* Reduce max write size, that can reduce interrupt latency time */ - if (size > FLASH_MAX_WRITE_SIZE) - { - size = FLASH_MAX_WRITE_SIZE; - } - - /* Make sure write will not cross page boundary */ - tmp = 256 - (addr & 0xFF); - - if (size > tmp) - { - size = tmp; - } - - hw_qspi_cs_enable(); - - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) - { - hw_qspi_write8(flash_config->page_program_opcode); -#if QUAD_MODE - - if (flash_config->quad_page_program_address == true) - { - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + /* Reduce max write size, that can reduce interrupt latency time */ + if (size > FLASH_MAX_WRITE_SIZE) { + size = FLASH_MAX_WRITE_SIZE; } -#endif - hw_qspi_write32((addr >> 24) | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); -#if QUAD_MODE - - if (flash_config->quad_page_program_address == false) - { - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + /* Make sure write will not cross page boundary */ + tmp = 256 - (addr & 0xFF); + if (size > tmp) { + size = tmp; } -#endif - } - else - { - if (flash_config->quad_page_program_address == true) - { - hw_qspi_write8(flash_config->page_program_opcode); + hw_qspi_cs_enable(); + + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { + hw_qspi_write8(flash_config->page_program_opcode); #if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + if (flash_config->quad_page_program_address == true) { + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + } #endif - hw_qspi_write16(((addr >> 16) & 0xFF) | (addr & 0xFF00)); - hw_qspi_write8(addr & 0xFF); - } - else - { - hw_qspi_write32(CMD_QUAD_PAGE_PROGRAM | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); + hw_qspi_write32((addr >> 24) | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); #if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + if (flash_config->quad_page_program_address == false) { + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + } #endif } - } - - if (odd) - { - odd = 4 - odd; - - for (i = 0; i < odd && i < size; ++i) - { - hw_qspi_write8(buf[i]); + else { + if (flash_config->quad_page_program_address == true) { + hw_qspi_write8(flash_config->page_program_opcode); +#if QUAD_MODE + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); +#endif + hw_qspi_write16(((addr >> 16) & 0xFF) | (addr & 0xFF00)); + hw_qspi_write8(addr & 0xFF); + } + else { + hw_qspi_write32(CMD_QUAD_PAGE_PROGRAM | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); +#if QUAD_MODE + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); +#endif + } } - } - size_aligned32 = ((size - i) & ~0x3); + if (odd) { + odd = 4 - odd; + for (i = 0; i < odd && i < size; ++i) { + hw_qspi_write8(buf[i]); + } + } - if (size_aligned32) - { - fast_write_to_fifo32((uint32_t)(buf + i), (uint32_t)(buf + i + size_aligned32), - (uint32_t) & (QSPIC->QSPIC_WRITEDATA_REG)); - i += size_aligned32; - } + size_aligned32 = ((size - i) & ~0x3); - for (; i < size; i++) - { - hw_qspi_write8(buf[i]); - } + if (size_aligned32) { + fast_write_to_fifo32((uint32_t)(buf + i), (uint32_t)(buf + i + size_aligned32), + (uint32_t)&(QSPIC->QSPIC_WRITEDATA_REG)); + i += size_aligned32; + } - hw_qspi_cs_disable(); + for (; i < size; i++) { + hw_qspi_write8(buf[i]); + } - DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_PAGE_PROG); + hw_qspi_cs_disable(); + + DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_PAGE_PROG); #if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); #endif - return i; + return i; } /** @@ -502,24 +469,22 @@ QSPI_SECTION static size_t flash_write_page(uint32_t addr, const uint8_t *buf, u * * \note This function blocks until the Flash has processed the command. */ -QSPI_SECTION __attribute__((unused)) static void flash_erase_sector(uint32_t addr) +__RETAINED_CODE __attribute__((unused)) static void flash_erase_sector(uint32_t addr) { - flash_write_enable(); + flash_write_enable(); - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) - { - uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 5); - } - else - { - uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 4); - } + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { + uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 5); + } + else { + uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 4); + } - /* Wait for the Flash to process the command */ - while (flash_erase_program_in_progress()); + /* Wait for the Flash to process the command */ + while (flash_erase_program_in_progress()); } /** @@ -528,36 +493,36 @@ QSPI_SECTION __attribute__((unused)) static void flash_erase_sector(uint32_t add * \return bool True if the Flash is not busy else false. * */ -QSPI_SECTION_NO_INLINE static bool qspi_writable(void) +__RETAINED_CODE static bool qspi_writable(void) { - bool writable; + bool writable; - /* - * From now on QSPI may not be available, turn off interrupts. - */ - GLOBAL_INT_DISABLE(); + /* + * From now on QSPI may not be available, turn off interrupts. + */ + GLOBAL_INT_DISABLE(); - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); - /* - * Check if flash is ready. - */ - writable = !(flash_is_busy()); + /* + * Check if flash is ready. + */ + writable = !(flash_is_busy()); - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); + /* + * Restore auto mode. + */ + flash_deactivate_command_entry_mode(); - /* - * Let other code to be executed including QSPI one. - */ - GLOBAL_INT_RESTORE(); + /* + * Let other code to be executed including QSPI one. + */ + GLOBAL_INT_RESTORE(); - return writable; + return writable; } /** @@ -570,11 +535,11 @@ QSPI_SECTION_NO_INLINE static bool qspi_writable(void) * 3: Suspended Erase procedure * 4: Finishing the Erase procedure */ -QSPI_SECTION static uint8_t qspi_get_erase_status(void) +__RETAINED_CODE __attribute__((unused)) static uint8_t qspi_get_erase_status(void) { - QSPIC->QSPIC_CHCKERASE_REG = 0; + QSPIC->QSPIC_CHCKERASE_REG = 0; - return HW_QSPIC_REG_GETF(ERASECTRL, ERS_STATE); + return HW_QSPIC_REG_GETF(ERASECTRL, ERS_STATE); } /** @@ -586,173 +551,163 @@ static inline HW_QSPI_ADDR_SIZE qspi_get_address_size(void) __attribute__((alway static inline HW_QSPI_ADDR_SIZE qspi_get_address_size(void) { - return (HW_QSPI_ADDR_SIZE)HW_QSPIC_REG_GETF(CTRLMODE, USE_32BA); + return (HW_QSPI_ADDR_SIZE)HW_QSPIC_REG_GETF(CTRLMODE, USE_32BA); } __RETAINED_CODE void flash_activate_command_entry_mode(void) { - /* - * Turn off auto mode to allow write. - */ - qspi_set_automode(false); + /* + * Turn off auto mode to allow write. + */ + qspi_set_automode(false); - /* - * Switch to single mode for command entry. - */ - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + /* + * Switch to single mode for command entry. + */ + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - /* - * Exit continuous mode (QPI mode), after this the flash will interpret commands again. - */ - if (flash_config->send_once != 0) - { - flash_reset_continuous_mode(flash_config->break_seq_size); - } + /* + * Exit continuous mode (QPI mode), after this the flash will interpret commands again. + */ + if (flash_config->send_once != 0) { + flash_reset_continuous_mode(flash_config->break_seq_size); + } } __RETAINED_CODE void flash_deactivate_command_entry_mode(void) { - flash_config->deactivate_command_entry_mode(); + flash_config->deactivate_command_entry_mode(); #if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); #endif - qspi_set_automode(true); + qspi_set_automode(true); } #if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) __RETAINED_CODE void flash_erase_sector_manual_mode(uint32_t addr) { - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); - /* - * Issue the erase sector command. - */ - flash_write_enable(); + /* + * Issue the erase sector command. + */ + flash_write_enable(); - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) - { - uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 5); - } - else - { - uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 4); - } + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { + uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 5); + } + else { + uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 4); + } - /* - * Flash stays in manual mode. - */ + /* + * Flash stays in manual mode. + */ } __RETAINED_CODE size_t flash_program_page_manual_mode(uint32_t addr, const uint8_t *buf, uint16_t size) { - size_t written = flash_write_page(addr, buf, size); + size_t written = flash_write_page(addr, buf, size); - /* - * Flash stays in manual mode. - */ + /* + * Flash stays in manual mode. + */ - return written; + return written; } __RETAINED_CODE bool qspi_check_program_erase_in_progress(void) { - return flash_is_busy(); + return flash_is_busy(); } __RETAINED_CODE bool qspi_check_and_suspend(void) { - uint8_t cmd[] = { flash_config->erase_suspend_opcode }; - bool am = hw_qspi_get_automode(); - bool ret = true; + uint8_t cmd[] = { flash_config->erase_suspend_opcode }; + bool am = hw_qspi_get_automode(); + bool ret = true; + + if (am) { + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); + } - if (am) - { /* - * Turn on command entry mode. + * Suspend action. */ - flash_activate_command_entry_mode(); - } + DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); - /* - * Suspend action. - */ - DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); + /* + * Check if an operation is ongoing. + */ + while (flash_erase_program_in_progress()) { + qspi_write(cmd, 1); + } - /* - * Check if an operation is ongoing. - */ - while (flash_erase_program_in_progress()) - { - qspi_write(cmd, 1); - } + hw_cpm_delay_usec(FLASH_SUS_DELAY); // Wait for SUS bit to be updated - hw_cpm_delay_usec(FLASH_SUS_DELAY); // Wait for SUS bit to be updated + DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); - DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); + if (flash_config->is_suspended() == false) { + ret = false; + } - if (flash_config->is_suspended() == false) - { - ret = false; - } + /* + * Restore auto mode. + */ + flash_deactivate_command_entry_mode(); - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); - - return ret; + return ret; } __RETAINED_CODE void qspi_resume(void) { - uint8_t cmd[] = { flash_config->erase_resume_opcode }; + uint8_t cmd[] = { flash_config->erase_resume_opcode }; - do - { - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); + do { + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); + + /* + * Check if suspended. + */ + if (flash_config->is_suspended() == false) { + break; + } + + /* + * Wait for flash to become ready again. + */ + do { + /* + * Resume action. + */ + qspi_write(cmd, 1); + + /* + * Check if SUS bit is cleared. + */ + } while (flash_config->is_suspended()); + } while (0); /* - * Check if suspended. + * Flash stays in manual mode. */ - if (flash_config->is_suspended() == false) - { - break; - } - - /* - * Wait for flash to become ready again. - */ - do - { - /* - * Resume action. - */ - qspi_write(cmd, 1); - - /* - * Check if SUS bit is cleared. - */ - } - while (flash_config->is_suspended()); - } - while (0); - - /* - * Flash stays in manual mode. - */ } #endif +#if (ERASE_IN_AUTOMODE == 1) /** * \brief Erase sector (via CPM background processing or using the QSPI controller) * @@ -764,28 +719,44 @@ __RETAINED_CODE void qspi_resume(void) * * \param[in] addr The address of the sector to be erased. */ -QSPI_SECTION_NO_INLINE static void qspi_erase_sector(uint32_t addr) +__RETAINED_CODE static void qspi_erase_sector(uint32_t addr) { - /* Wait for previous erase to end */ - while (qspi_get_erase_status() != 0) - { - } +#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) + OS_TASK handle; + void *op; - if (qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32) - { - addr >>= 12; - } - else - { - addr >>= 4; - } + handle = OS_GET_CURRENT_TASK(); - /* Setup erase block page */ - HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr); + /* Instruct CPM to erase this sector */ + if (pm_register_qspi_operation(handle, addr, NULL, 0, &op)) { + /* Block until erase is completed */ + OS_TASK_SUSPEND(handle); + OS_FREE(op); + } + else { + /* The PM has not started yet... */ - /* Fire erase */ - HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); +#endif + /* Wait for previous erase to end */ + while (qspi_get_erase_status() != 0) { + } + + if (qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32) { + addr >>= 12; + } else { + addr >>= 4; + } + + /* Setup erase block page */ + HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr); + + /* Fire erase */ + HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); +#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) + } +#endif } +#endif /* (ERASE_IN_AUTOMODE == 1) */ /** * \brief Write data to a page in the Flash (via CPM background processing or using the QSPI @@ -806,39 +777,57 @@ QSPI_SECTION_NO_INLINE static void qspi_erase_sector(uint32_t addr) * * \warning The caller should ensure that buf does not point to QSPI mapped memory. */ -QSPI_SECTION_NO_INLINE static size_t write_page(uint32_t addr, const uint8_t *buf, uint16_t size) +__RETAINED_CODE static size_t write_page(uint32_t addr, const uint8_t *buf, uint16_t size) { - size_t written; + size_t written; - /* - * From now on QSPI may not be available, turn of interrupts. - */ - GLOBAL_INT_DISABLE(); +#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) + OS_TASK handle; + void *op; - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); + handle = OS_GET_CURRENT_TASK(); - /* - * Write data into the page of the Flash. - */ - written = flash_write_page(addr, buf, size); + /* Instruct CPM to program this sector */ + if (pm_register_qspi_operation(handle, addr, buf, &size, &op)) { + /* Block until program is completed */ + OS_TASK_SUSPEND(handle); + OS_FREE(op); + written = size; + } + else { +#endif + /* + * From now on QSPI may not be available, turn of interrupts. + */ + GLOBAL_INT_DISABLE(); - /* Wait for the Flash to process the command */ - while (flash_erase_program_in_progress()); + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); + /* + * Write data into the page of the Flash. + */ + written = flash_write_page(addr, buf, size); - /* - * Let other code to be executed including QSPI one. - */ - GLOBAL_INT_RESTORE(); + /* Wait for the Flash to process the command */ + while (flash_erase_program_in_progress()); - return written; + /* + * Restore auto mode. + */ + flash_deactivate_command_entry_mode(); + + /* + * Let other code to be executed including QSPI one. + */ + GLOBAL_INT_RESTORE(); +#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) + } +#endif + + return written; } /** @@ -855,160 +844,149 @@ QSPI_SECTION_NO_INLINE static size_t write_page(uint32_t addr, const uint8_t *bu * * \param[in] addr The address of the sector to be erased. */ -QSPI_SECTION_NO_INLINE static void erase_sector(uint32_t addr) +__RETAINED_CODE static void erase_sector(uint32_t addr) { #if ERASE_IN_AUTOMODE - /* - * Erase sector in automode - */ - qspi_erase_sector(addr); - - /* - * Wait for erase to finish - */ - while (qspi_get_erase_status()) - { - } + /* + * Erase sector in automode + */ + qspi_erase_sector(addr); + /* + * Wait for erase to finish + */ + while (qspi_get_erase_status()) { + } #else - /* - * From now on QSPI may not be available, turn of interrupts. - */ - GLOBAL_INT_DISABLE(); + /* + * From now on QSPI may not be available, turn of interrupts. + */ + GLOBAL_INT_DISABLE(); - /* - * Turn off auto mode to allow write. - */ - qspi_set_automode(false); + /* + * Turn off auto mode to allow write. + */ + qspi_set_automode(false); - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - /* - * Get the Flash out of Power Down mode. - */ - flash_release_power_down(); + /* + * Exit continuous mode, after this the flash will interpret commands again. + */ + flash_reset_continuous_mode(flash_config->break_seq_size); - /* - * Exit continuous mode, after this the flash will interpret commands again. - */ - flash_reset_continuous_mode(flash_config->break_seq_size); + /* + * Execute erase command. + */ + flash_erase_sector(addr); - /* - * Execute erase command. - */ - flash_erase_sector(addr); + /* + * Restore auto mode. + */ + flash_deactivate_command_entry_mode(); - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); - - /* - * Let other code to be executed including QSPI one. - */ - GLOBAL_INT_RESTORE(); + /* + * Let other code to be executed including QSPI one. + */ + GLOBAL_INT_RESTORE(); #endif } uint32_t qspi_automode_get_code_buffer_size(void) { - /* Return 1 in case some code will pass this value to memory allocation function */ - return 1; + /* Return 1 in case some code will pass this value to memory allocation function */ + return 1; } void qspi_automode_set_code_buffer(void *ram) { - (void) ram; /* Unused */ + (void) ram; /* Unused */ } bool qspi_automode_writable(void) { - return qspi_writable(); + return qspi_writable(); } size_t qspi_automode_write_flash_page(uint32_t addr, const uint8_t *buf, size_t size) { - while (!qspi_automode_writable()) - { - } + while (!qspi_automode_writable()) { + } - return write_page(addr, buf, size); + return write_page(addr, buf, size); } void qspi_automode_erase_flash_sector(uint32_t addr) { - while (!qspi_automode_writable()) - { - } + while (!qspi_automode_writable()) { + } - erase_sector(addr); + erase_sector(addr); } void qspi_automode_erase_chip(void) { - flash_activate_command_entry_mode(); + flash_activate_command_entry_mode(); - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_WRITE_ENABLE); - hw_qspi_cs_disable(); + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_WRITE_ENABLE); + hw_qspi_cs_disable(); - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_CHIP_ERASE); - hw_qspi_cs_disable(); + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_CHIP_ERASE); + hw_qspi_cs_disable(); - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_READ_STATUS_REGISTER); + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_READ_STATUS_REGISTER); + while (hw_qspi_read8() & FLASH_STATUS_BUSY_MASK); + hw_qspi_cs_disable(); - while (hw_qspi_read8() & FLASH_STATUS_BUSY_MASK); - - hw_qspi_cs_disable(); - - flash_deactivate_command_entry_mode(); + flash_deactivate_command_entry_mode(); } size_t qspi_automode_read(uint32_t addr, uint8_t *buf, size_t len) { - memcpy(buf, (void *)(MEMORY_QSPIF_BASE + addr), len); + memcpy(buf, (void *)(MEMORY_QSPIF_BASE + addr), len); - return len; + return len; } -QSPI_SECTION void qspi_automode_flash_power_up(void) +__RETAINED_CODE void qspi_automode_flash_power_up(void) { - hw_cpm_delay_usec(flash_config->power_down_delay); + hw_cpm_delay_usec(flash_config->power_down_delay); - /* Interrupts must be turned off since the flash goes in manual mode, and - * code (e.g. for an ISR) cannot be fetched from flash during this time - */ - GLOBAL_INT_DISABLE(); + /* Interrupts must be turned off since the flash goes in manual mode, and + * code (e.g. for an ISR) cannot be fetched from flash during this time + */ + GLOBAL_INT_DISABLE(); - // Do not call flash_activate_command_entry_mode(). This function will call - // flash_reset_continuous_mode which will try to send break sequence to the QSPI Flash - // which is in power-down mode. - qspi_set_automode(false); - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + // Do not call flash_activate_command_entry_mode(). This function will call + // flash_reset_continuous_mode which will try to send break sequence to the QSPI Flash + // which is in power-down mode. + qspi_set_automode(false); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_RELEASE_POWER_DOWN); - hw_qspi_cs_disable(); + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_RELEASE_POWER_DOWN); + hw_qspi_cs_disable(); - flash_deactivate_command_entry_mode(); + flash_deactivate_command_entry_mode(); - /* - * The flash is in auto mode again. Re-enable the interrupts - */ - GLOBAL_INT_RESTORE(); + /* + * The flash is in auto mode again. Re-enable the interrupts + */ + GLOBAL_INT_RESTORE(); - hw_cpm_delay_usec(flash_config->release_power_down_delay); + hw_cpm_delay_usec(flash_config->release_power_down_delay); } -QSPI_SECTION void qspi_automode_flash_power_down(void) +__RETAINED_CODE void qspi_automode_flash_power_down(void) { - flash_activate_command_entry_mode(); + flash_activate_command_entry_mode(); - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_ENTER_POWER_DOWN); - hw_qspi_cs_disable(); + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_ENTER_POWER_DOWN); + hw_qspi_cs_disable(); // Do not call flash_deactivate_command_entry_mode(). This function will call // flash_config->deactivate_command_entry_mode() which will try to send commands to the QSPI Flash @@ -1017,14 +995,13 @@ QSPI_SECTION void qspi_automode_flash_power_down(void) // flash_deactivate_command_entry_mode(); #if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); #endif - qspi_set_automode(true); + qspi_set_automode(true); } -static qspi_config qspi_cfg = -{ - HW_QSPI_ADDR_SIZE_24, HW_QSPI_POL_HIGH, HW_QSPI_SAMPLING_EDGE_NEGATIVE +static qspi_config qspi_cfg = { + HW_QSPI_ADDR_SIZE_24, HW_QSPI_POL_HIGH, HW_QSPI_SAMPLING_EDGE_NEGATIVE }; /** @@ -1035,27 +1012,27 @@ static qspi_config qspi_cfg = * \param[in] density Pointer to the variable where the device density will be returned */ #if FLASH_AUTODETECT -QSPI_SECTION static void flash_read_jedec_id(uint8_t *manufacturer_id, uint8_t *device_type, uint8_t *density) +__RETAINED_CODE static void flash_read_jedec_id(uint8_t *manufacturer_id, uint8_t *device_type, uint8_t *density) { - uint8_t cmd[] = { CMD_READ_JEDEC_ID }; - uint8_t buffer[3]; + uint8_t cmd[] = { CMD_READ_JEDEC_ID }; + uint8_t buffer[3]; - qspi_set_automode(false); - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + qspi_set_automode(false); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - // reset continuous mode using both one and two break bytes to cover all cases - flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_2B); - flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_1B); + // reset continuous mode using both one and two break bytes to cover all cases + flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_2B); + flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_1B); - qspi_transact(cmd, 1, buffer, 3); - *manufacturer_id = buffer[0]; - *device_type = buffer[1]; - *density = buffer[2]; + qspi_transact(cmd, 1, buffer, 3); + *manufacturer_id = buffer[0]; + *device_type = buffer[1]; + *density = buffer[2]; #if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); #endif - qspi_set_automode(true); + qspi_set_automode(true); } #endif @@ -1064,157 +1041,139 @@ QSPI_SECTION static void flash_read_jedec_id(uint8_t *manufacturer_id, uint8_t * * * \param[in] count Number of dummy bytes (not including extra byte) */ -QSPI_SECTION __attribute__((unused)) static void qspi_automode_set_dummy_bytes_count(uint8_t count) +__RETAINED_CODE __attribute__((unused)) static void qspi_automode_set_dummy_bytes_count(uint8_t count) { - if (count == 3) - { - HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1); - } - else - { - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, - dummy_num[count]); - } + if (count == 3) { + HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1); + } else { + QSPIC->QSPIC_BURSTCMDB_REG = + (QSPIC->QSPIC_BURSTCMDB_REG & + ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) | + REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, + dummy_num[count]); + } } __RETAINED_CODE bool qspi_automode_init(void) { - uint8_t device_type; - uint8_t device_density; + uint8_t device_type; + uint8_t device_density; - hw_qspi_enable_clock(); + hw_qspi_enable_clock(); #if __DBG_QSPI_ENABLED - REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, 3); + REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, 3); #endif #if FLASH_AUTODETECT - uint8_t manufacturer_id; - uint8_t i; + uint8_t manufacturer_id; + uint8_t i; - flash_read_jedec_id(&manufacturer_id, &device_type, &device_density); + flash_read_jedec_id(&manufacturer_id, &device_type, &device_density); - const qspi_flash_config_t *flash_config_init = flash_config_table[0]; // default to first entry. + const qspi_flash_config_t* flash_config_init = flash_config_table[0]; // default to first entry. - for (i = 0; i < sizeof(flash_config_table) / sizeof(qspi_flash_config_t *); i++) - { - if ((flash_config_table[i]->manufacturer_id == manufacturer_id) && - (flash_config_table[i]->device_type == device_type) && - (flash_config_table[i]->device_density == device_density)) - { - flash_config_init = flash_config_table[i]; - break; + for (i=0; i< sizeof(flash_config_table)/sizeof(qspi_flash_config_t*); i++) { + if ( (flash_config_table[i]->manufacturer_id == manufacturer_id) && + (flash_config_table[i]->device_type == device_type) && + (flash_config_table[i]->device_density == device_density)) { + flash_config_init = flash_config_table[i]; + break; + } } - } - - flash_autodetect_config = *flash_config_init; - flash_config = &flash_autodetect_config; + flash_autodetect_config = *flash_config_init; + flash_config = &flash_autodetect_config; #else - device_type = dg_configFLASH_DEVICE_TYPE; - device_density = dg_configFLASH_DENSITY; + device_type = dg_configFLASH_DEVICE_TYPE; + device_density = dg_configFLASH_DENSITY; #endif - /* - * Copy the selected flash struct from flash into retram - */ - flash_config->initialize(device_type, device_density); + /* + * Copy the selected flash struct from flash into retram + */ + flash_config->initialize(device_type, device_density); - uint8_t read_opcode; + uint8_t read_opcode; - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) - { - read_opcode = CMD_FAST_READ_QUAD_4B; - qspi_cfg.address_size = HW_QSPI_ADDR_SIZE_32; // It will be set when hw_qspi_init() is called - } - else - { - read_opcode = CMD_FAST_READ_QUAD; - } + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { + read_opcode = CMD_FAST_READ_QUAD_4B; + qspi_cfg.address_size = HW_QSPI_ADDR_SIZE_32; // It will be set when hw_qspi_init() is called + } + else { + read_opcode = CMD_FAST_READ_QUAD; + } + /* + * Setup erase instruction that will be sent by QSPI controller to erase sector in automode. + */ + hw_qspi_set_erase_instruction(flash_config->erase_opcode, HW_QSPI_BUS_MODE_SINGLE, + HW_QSPI_BUS_MODE_SINGLE, 15, 5); + /* + * Setup instruction pair that will temporarily suspend erase operation to allow read. + */ + hw_qspi_set_suspend_resume_instructions(flash_config->erase_suspend_opcode, HW_QSPI_BUS_MODE_SINGLE, + flash_config->erase_resume_opcode, HW_QSPI_BUS_MODE_SINGLE, 7); - /* - * Setup erase instruction that will be sent by QSPI controller to erase sector in automode. - */ - hw_qspi_set_erase_instruction(flash_config->erase_opcode, HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_SINGLE, 15, 5); - /* - * Setup instruction pair that will temporarily suspend erase operation to allow read. - */ - hw_qspi_set_suspend_resume_instructions(flash_config->erase_suspend_opcode, HW_QSPI_BUS_MODE_SINGLE, - flash_config->erase_resume_opcode, HW_QSPI_BUS_MODE_SINGLE, 7); + /* + * QSPI controller must send write enable before erase, this sets it up. + */ + hw_qspi_set_write_enable_instruction(CMD_WRITE_ENABLE, HW_QSPI_BUS_MODE_SINGLE); - /* - * QSPI controller must send write enable before erase, this sets it up. - */ - hw_qspi_set_write_enable_instruction(CMD_WRITE_ENABLE, HW_QSPI_BUS_MODE_SINGLE); + /* + * Setup instruction that will be used to periodically check erase operation status. + * Check LSB which is 1 when erase is in progress. + */ + hw_qspi_set_read_status_instruction(flash_config->read_erase_progress_opcode, HW_QSPI_BUS_MODE_SINGLE, + HW_QSPI_BUS_MODE_SINGLE, flash_config->erase_in_progress_bit, flash_config->erase_in_progress_bit_high_level?1:0, 20, 0); - /* - * Setup instruction that will be used to periodically check erase operation status. - * Check LSB which is 1 when erase is in progress. - */ - hw_qspi_set_read_status_instruction(flash_config->read_erase_progress_opcode, HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_SINGLE, flash_config->erase_in_progress_bit, flash_config->erase_in_progress_bit_high_level ? 1 : 0, - 20, 0); + /* + * This sequence is necessary if flash is working in continuous read mode, when instruction + * is not sent on every read access just address. Sending 0xFFFF will exit this mode. + * This sequence is sent only when QSPI is working in automode and decides to send one of + * instructions above. + * If flash is working in DUAL bus mode sequence should be 0xFFFF and size should be + * HW_QSPI_BREAK_SEQ_SIZE_2B. + */ + hw_qspi_set_break_sequence(0xFFFF, HW_QSPI_BUS_MODE_SINGLE, flash_config->break_seq_size, 0); - /* - * This sequence is necessary if flash is working in continuous read mode, when instruction - * is not sent on every read access just address. Sending 0xFFFF will exit this mode. - * This sequence is sent only when QSPI is working in automode and decides to send one of - * instructions above. - * If flash is working in DUAL bus mode sequence should be 0xFFFF and size should be - * HW_QSPI_BREAK_SEQ_SIZE_2B. - */ - hw_qspi_set_break_sequence(0xFFFF, HW_QSPI_BUS_MODE_SINGLE, flash_config->break_seq_size, 0); + /* + * If application starts from FLASH then bootloader must have set read instruction. + */ + if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) { + hw_qspi_init(&qspi_cfg); + hw_qspi_set_div(HW_QSPI_DIV_1); + } + flash_activate_command_entry_mode(); - /* - * If application starts from FLASH then bootloader must have set read instruction. - */ - if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - { - hw_qspi_init(&qspi_cfg); - hw_qspi_set_div(HW_QSPI_DIV_1); - } + hw_qspi_set_read_instruction(read_opcode, flash_config->send_once, flash_config->get_dummy_bytes(), HW_QSPI_BUS_MODE_SINGLE, + HW_QSPI_BUS_MODE_QUAD, HW_QSPI_BUS_MODE_QUAD, + HW_QSPI_BUS_MODE_QUAD); + hw_qspi_set_extra_byte(flash_config->extra_byte, HW_QSPI_BUS_MODE_QUAD, 0); + hw_qspi_set_address_size(flash_config->address_size); -#ifdef ENABLE_AUTOMODE_CONFIGURATION_FOR_READ + flash_deactivate_command_entry_mode(); - flash_activate_command_entry_mode(); + HW_QSPIC_REG_SETF(BURSTCMDB, CS_HIGH_MIN, 0); - hw_qspi_set_read_instruction(read_opcode, flash_config->send_once, flash_config->get_dummy_bytes(), - HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_QUAD, HW_QSPI_BUS_MODE_QUAD, - HW_QSPI_BUS_MODE_QUAD); - hw_qspi_set_extra_byte(flash_config->extra_byte, HW_QSPI_BUS_MODE_QUAD, 0); - hw_qspi_set_address_size(flash_config->address_size); - - flash_deactivate_command_entry_mode(); - - HW_QSPIC_REG_SETF(BURSTCMDB, CS_HIGH_MIN, 0); -#else - (void) read_opcode; -#endif - return true; + return true; } -QSPI_SECTION void qspi_automode_sys_clock_cfg(sys_clk_t sys_clk) +__RETAINED_CODE void qspi_automode_sys_clock_cfg(sys_clk_t sys_clk) { - if ((CRG_TOP->CLK_AMBA_REG & (1 << REG_POS(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE))) != 0) // If clock is enabled - { - /* Some of the sys_clk_cfg() implementations put the flash in command entry mode, where the flash is - * not available for code execution. We must make sure that no interrupt (that may cause a cache miss) - * hits during this time. - */ - GLOBAL_INT_DISABLE(); - flash_config->sys_clk_cfg(sys_clk); - GLOBAL_INT_RESTORE(); - } + if ((CRG_TOP->CLK_AMBA_REG & (1 << REG_POS(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE))) != 0) { // If clock is enabled + /* Some of the sys_clk_cfg() implementations put the flash in command entry mode, where the flash is + * not available for code execution. We must make sure that no interrupt (that may cause a cache miss) + * hits during this time. + */ + GLOBAL_INT_DISABLE(); + flash_config->sys_clk_cfg(sys_clk); + GLOBAL_INT_RESTORE(); + } } const qspi_ucode_t *qspi_automode_get_ucode(void) { - return &flash_config->ucode_wakeup; + return &flash_config->ucode_wakeup; } diff --git a/third_party/dialog/DialogSDK/bsp/osal/osal.h b/third_party/dialog/DialogSDK/bsp/osal/osal.h new file mode 100644 index 000000000..5a88a8ea1 --- /dev/null +++ b/third_party/dialog/DialogSDK/bsp/osal/osal.h @@ -0,0 +1,95 @@ +/** + * \addtogroup BSP + * \{ + * \addtogroup OSAL + * + * \brief OS Abstraction Layer + * + * \{ + */ + +/** + **************************************************************************************** + * + * @file osal.h + * + * @brief OS abstraction layer API + * + * @brief Access QSPI flash when running in auto mode + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ + +#ifndef OSAL_H_ +#define OSAL_H_ + +#if defined OS_BAREMETAL + +#include + +/* + * Basic set of macros that can be used in non OS environment. + */ +# define PRIVILEGED_DATA +# define OS_MALLOC malloc +# define OS_FREE free +# ifndef RELEASE_BUILD +# define OS_ASSERT(a) do { if (!(a)) {__BKPT(0);} } while (0) +# else +# define OS_ASSERT(a) ((void) (a)) +# endif + +#endif + +/** + * \brief Cast any pointer to unsigned int value + */ +#define OS_PTR_TO_UINT(p) ((unsigned) (void *) (p)) + +/** + * \brief Cast any pointer to signed int value + */ +#define OS_PTR_TO_INT(p) ((int) (void *) (p)) + +/** + * \brief Cast any unsigned int value to pointer + */ +#define OS_UINT_TO_PTR(u) ((void *) (unsigned) (u)) + +/** + * \brief Cast any signed int value to pointer + */ +#define OS_INT_TO_PTR(i) ((void *) (int) (i)) + +#endif /* OSAL_H_ */ + +/** + * \} + * \} + * \} + */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h index 8c917c2f8..e98faa2a2 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h @@ -9,39 +9,39 @@ */ /** -**************************************************************************************** -* -* @file hw_cpm.c -* -* @brief Clock and Power Manager Driver -* -* Copyright (c) 2016, Dialog Semiconductor -* All rights reserved. -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -* OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -**************************************************************************************** -*/ + **************************************************************************************** + * + * @file hw_aes_hash.h + * + * @brief Definition of API for the AES/HASH Engine Low Level Driver. + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ #ifndef HW_AES_HASH_H_ #define HW_AES_HASH_H_ @@ -49,8 +49,7 @@ #if dg_configUSE_HW_AES_HASH #include -#include -#include +#include "sdk_defs.h" /** * \brief AES/Hash callback diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h index 835820d1d..b99d16825 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h @@ -9,7 +9,7 @@ */ /** -**************************************************************************************** + **************************************************************************************** * * @file hw_cpm.h * @@ -40,8 +40,8 @@ * OF THE POSSIBILITY OF SUCH DAMAGE. * * -**************************************************************************************** -*/ + **************************************************************************************** + */ #ifndef CPM_H_ #define CPM_H_ @@ -50,15 +50,49 @@ #include "sdk_defs.h" -#define SYS_CLK_IS_XTAL16M (0) -#define SYS_CLK_IS_RC16 (1) -#define SYS_CLK_IS_LP (2) -#define SYS_CLK_IS_PLL (3) +/** + * \addtogroup CLOCK_TYPES + * \brief Clock types + * \note These macros must only be used with hw_cpm_set_sysclk(). + * \{ + */ + +/** + * \brief System crystal oscillator 16 MHz + */ +#define SYS_CLK_IS_XTAL16M (0) +/** + * \brief System RC oscillator 16 MHz + */ +#define SYS_CLK_IS_RC16 (1) +/** + * \brief System Low Power clock + */ +#define SYS_CLK_IS_LP (2) +/** + * \brief System PLL + */ +#define SYS_CLK_IS_PLL (3) +/** + * \brief Low Power RC oscillator 32 kHz + */ #define LP_CLK_IS_RC32K (0) +/** + * \brief Low Power RC oscillator 11.7 kHz + */ #define LP_CLK_IS_RCX (1) +/** + * \brief Low Power crystal oscillator 32 kHz + */ #define LP_CLK_IS_XTAL32K (2) +/** + * \brief Low Power external clock + */ #define LP_CLK_IS_EXTERNAL (3) +/** + * \} + */ #define DCDC_IS_READY \ (REG_MSK(DCDC, DCDC_STATUS_1_REG, DCDC_VDD_AVAILABLE)) @@ -75,6 +109,7 @@ typedef enum cal_clk_cel_type { /** * \brief The system clock type + * \note Must only be used with functions cm_sys_clk_init/set() * */ typedef enum sysclk_type { @@ -282,7 +317,7 @@ __STATIC_INLINE void hw_cpm_deactivate_bod_protection(void) } /** - * \brief Activate BOD protection for 1V4 rail (only for DA14682/3-BA chips!). + * \brief Activate BOD protection for 1V4 rail (only for DA14682/3-00, DA15XXX-00 chips!). * */ __STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void) __attribute__((always_inline)); @@ -295,7 +330,7 @@ __STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void) } /** - * \brief Deactivate BOD protection for 1V4 rail (only for DA14682/3-BA chips!). + * \brief Deactivate BOD protection for 1V4 rail (only for DA14682/3-00, DA15XXX-00 chips!). * */ __STATIC_INLINE void hw_cpm_deactivate_1v4_bod_protection(void) __attribute__((always_inline)); diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h index e8924e8ce..ef05b5991 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h @@ -9,43 +9,43 @@ */ /** -**************************************************************************************** -* -* @file hw_cpm.c -* -* @brief Clock and Power Manager Driver -* -* Copyright (c) 2016, Dialog Semiconductor -* All rights reserved. -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -* OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -**************************************************************************************** -*/ + **************************************************************************************** + * + * @file hw_crypto.h + * + * @brief Interrupt handling API for the AES/Hash and ECC Engines. + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ #if (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC) -#include +#include "sdk_defs.h" /** * \brief Crypto engines callback @@ -65,7 +65,7 @@ typedef void (*hw_crypto_cb)(unsigned int status); * * \note AES/HASH engine and ECC engine are common sources of CRYPTO system interrupt. This * function only enables CRYPTO interrupt itself and registers a callback for AES/HASH - * related CRYPTO interrupts. In order to fully enable AES/HASH interrupts + * related CRYPTO interrupts. In order to fully enable AES/HASH interrupts * hw_aes_hash_enable_interrupt_source() must also be called */ void hw_crypto_enable_aes_hash_interrupt(hw_crypto_cb cb); diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h deleted file mode 100644 index cb9209282..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h +++ /dev/null @@ -1,374 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup FEM - * \{ - * \brief Front End Module for SKYWORKS SKY66112-11 - */ - -/** - ***************************************************************************************** - * - * @file - * - * @brief FEM Driver for SKYWORKS SKY66112-11 Low Level Driver API. - * - * GPIOs used for controlling the FEM are configured using the following macros, that should be placed - * in custom_config.h: - * - * CSD : dg_configFEM_SKY66112_11_CSD_PORT/PIN - * CPS : dg_configFEM_SKY66112_11_CPS_PORT/PIN - * CRX : dg_configFEM_SKY66112_11_CRX_PORT/PIN - * CTX : dg_configFEM_SKY66112_11_CTX_PORT/PIN - * CHL : dg_configFEM_SKY66112_11_CHL_PORT/PIN - * ANTSEL: dg_configFEM_SKY66112_11_ANTSEL_PORT/PIN - * - * In order to control an external PA, three GPIOs can be used. These are called RF_ANT_TRIMx, x=0,1,2. Each one of - * these bits is enabled if the corresponding PORT/PIN macros are set: - * - * RF_ANT_TRIM0 : dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT/PIN - * RF_ANT_TRIM1 : dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT/PIN - * RF_ANT_TRIM2 : dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT/PIN - * - * The actual GPIO values for RF_ANT_TRIMx are set by the corresponding MAC, whenever it gains access by the arbiter - * to the RF. This driver only handles the GPIO initialization. - * - * FEM BIAS Voltage control is enabled by the following macros: - * - * V18 : dg_configFEM_SKY66112_11_FEM_BIAS_V18 - * V18P : dg_configFEM_SKY66112_11_FEM_BIAS_V18P - * - * If none of them is set, FEM BIAS will not be controlled by this driver. - * - *************************************************************************************** - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_FEM_H_ -#define HW_FEM_H_ - -#if dg_configFEM == FEM_SKY66112_11 -#include - -#if defined(dg_configFEM_SKY66112_11_FEM_BIAS_V18) && defined(dg_configFEM_SKY66112_11_FEM_BIAS_V18P) -#error Only one of dg_configFEM_SKY66112_11_FEM_BIAS_V18 and dg_configFEM_SKY66112_11_FEM_BIAS_V18P can be set at a time -#endif - -/* Configuration/state structure (actually just a byte) */ -typedef struct __attribute__ ((__packed__)) { -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - uint8_t tx_power: 1; - uint8_t tx_bypass: 1; - uint8_t rx_bypass: 1; -#else - uint8_t tx_power_ble: 1; - uint8_t tx_bypass_ble: 1; - uint8_t rx_bypass_ble: 1; - uint8_t tx_power_ftdf: 1; - uint8_t tx_bypass_ftdf: 1; - uint8_t rx_bypass_ftdf: 1; -#endif - uint8_t antsel: 1; - uint8_t started: 1; -} hw_fem_config; - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -/** - * \brief Configures FEM TX Power - * - * \param [in] high Set true to enable high TX power - * - */ -void hw_fem_set_txpower(bool high); - -/** - * \brief Configures FEM TX bypass mode - * - * \param [in] enable false: Use PA, true: bypass - * - */ -void hw_fem_set_tx_bypass(bool enable); - -/** - * \brief Configures FEM RX bypass mode - * - * \param [in] enable false: Use LNA, true: bypass - * - */ -void hw_fem_set_rx_bypass(bool enable); - -/** - * \brief Gets the TX Power setting - * - * \return true, if TX Power is high, false if low - * - */ -bool hw_fem_get_txpower(void); - -/** - * \brief Gets the TX bypass mode - * - * \return false: No TX bypass, true: TX bypass - * - */ -bool hw_fem_get_tx_bypass(void); - -/** - * \brief Gets the RX bypass mode - * - * \return false: No RX bypass, true: RX bypass - * - */ -bool hw_fem_get_rx_bypass(void); - -#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ -#ifdef CONFIG_USE_BLE -/** - * \brief Configures FEM TX Power for BLE - * - * \param [in] high Set true to enable high TX power - * - */ -void hw_fem_set_txpower_ble(bool high); - -/** - * \brief Configures FEM TX bypass mode for BLE - * - * \param [in] enable false: Use PA, true: bypass - * - */ -void hw_fem_set_tx_bypass_ble(bool enable); - -/** - * \brief Configures FEM RX bypass mode for BLE - * - * \param [in] enable false: Use LNA, true: bypass - * - */ -void hw_fem_set_rx_bypass_ble(bool enable); - -/** - * \brief Gets the TX Power setting for BLE - * - * \return true, if TX Power is high, false if low - * - */ -bool hw_fem_get_txpower_ble(void); - -/** - * \brief Gets the TX bypass mode for BLE - * - * \return false: No TX bypass, true: TX bypass - * - */ -bool hw_fem_get_tx_bypass_ble(void); - -/** - * \brief Gets the RX bypass mode for BLE - * - * \return false: No RX bypass, true: RX bypass - * - */ -bool hw_fem_get_rx_bypass_ble(void); -#endif /* CONFIG_USE_BLE */ - -#ifdef CONFIG_USE_FTDF -/** - * \brief Configures FEM TX Power for FTDF - * - * \param [in] high Set true to enable high TX power - * - */ -void hw_fem_set_txpower_ftdf(bool high); - -/** - * \brief Configures FEM TX bypass mode for FTDF - * - * \param [in] enable false: Use PA, true: bypass - * - */ -void hw_fem_set_tx_bypass_ftdf(bool enable); - -/** - * \brief Configures FEM RX bypass mode for FTDF - * - * \param [in] enable false: Use LNA, true: bypass - * - */ -void hw_fem_set_rx_bypass_ftdf(bool enable); - -/** - * \brief Gets the TX Power setting for FTDF - * - * \return true, if TX Power is high, false if low - * - */ -bool hw_fem_get_txpower_ftdf(void); - -/** - * \brief Gets the TX bypass mode for FTDF - * - * \return false: No TX bypass, true: TX bypass - * - */ -bool hw_fem_get_tx_bypass_ftdf(void); - -/** - * \brief Gets the RX bypass mode for FTDF - * - * \return false: No RX bypass, true: RX bypass - * - */ -bool hw_fem_get_rx_bypass_ftdf(void); -#endif /* CONFIG_USE_FTDF */ - -/** - * \brief Configures FEM TX Power - * - * \param [in] high Set true to enable high TX power - * - * \deprecated Use the BLE/FTDF specific functions instead - */ -void hw_fem_set_txpower(bool high) DEPRECATED; - -/** - * \brief Configures FEM TX bypass mode - * - * \param [in] enable false: Use PA, true: bypass - * - * \deprecated Use the BLE/FTDF specific functions instead - */ -void hw_fem_set_tx_bypass(bool enable) DEPRECATED; - -/** - * \brief Configures FEM RX bypass mode - * - * \param [in] enable false: Use LNA, true: bypass - * - * \deprecated Use the BLE/FTDF specific functions instead - */ -void hw_fem_set_rx_bypass(bool enable) DEPRECATED; - -/** - * \brief Gets the TX Power setting - * - * \return true, if TX Power is high, false if low - * - * \deprecated Use the BLE/FTDF specific functions instead - */ -bool hw_fem_get_txpower(void) DEPRECATED; - -/** - * \brief Gets the TX bypass mode - * - * \return false: No TX bypass, true: TX bypass - * - * \deprecated Use the BLE/FTDF specific functions instead - */ -bool hw_fem_get_tx_bypass(void) DEPRECATED; - -/** - * \brief Gets the RX bypass mode - * - * \return false: No RX bypass, true: RX bypass - * - * \deprecated Use the BLE/FTDF specific functions instead - */ -bool hw_fem_get_rx_bypass(void) DEPRECATED; -#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ - - -/** - * \brief Configures FEM Antenna to use - * - * \param [in] one false: antenna 0, true: antenna 1 - * - */ -void hw_fem_set_antenna(bool one); - -/** - * \brief Gets the selected antenna - * - * \return false: antenna 1, true: antenna 2 - * - */ -bool hw_fem_get_antenna(void); - -/** - * \brief Sets the FEM Bias - * - * \param [in] voltage The voltage to set the FEM Bias to (mV) - * - * \return 0: success, -1: Out of range value entered, -2: FEM BIAS not supported on this board - * - */ -int hw_fem_set_bias(uint16_t voltage); - -/** - * \brief Sets the 2nd FEM Bias - * - * \param [in] voltage The voltage to set the 2nd FEM Bias to (mV) - * - * \return 0: success, -1: Out of range value entered, -2: 2nd FEM BIAS not supported on this board - * - */ -int hw_fem_set_bias2(uint16_t voltage); - -/** - * \brief Starts and configures FEM. - * - * Configures and sets GPIOs according to configuration set by hw_fem_set_config(). Also configures - * DCF Timers. - * - * - * \note To be called by the RF driver when RF is powered on - * - */ -void hw_fem_start(void); - -/** - * \brief Stops FEM. - * - * Stops DCF timers and sets all FEM control signals to 0 to achieve the lowest possible power - * - * \note To be called by the RF driver when RF is powered off - * - */ -void hw_fem_stop(void); - -#endif /* dg_configFEM == FEM_SKY66112_11 */ -#endif /* HW_FEM_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h index 928f4a2e0..7a6a64e85 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h @@ -15,66 +15,6 @@ * * @brief Radio module (RF) Low Level Driver API. * - * @note The following recalibration-related weak functions can be overridden, if needed, - * to provide additional functionality - * - * @note - * ~~~{.c} - * bool hw_rf_preoff_cb(void) - * ~~~ - * - * @note Called before actually shutting down the RF PD. If this returns true, the PD - * will NOT be shutdown, but will stay on. This function can be used to decide - * whether an RF recalibration is needed and to start the respective operation. - * The default implementation (if an explicit implementation is omitted) returns - * false (i.e. the RF PD shuts off immediately). - * - * @note - * ~~~{.c} - * void hw_rf_postconf_cb(void) - * ~~~ - * - * @note Called after the RF recommended settings are applied, or after the - * recalibration procedure is completed. Can be used to start/reset a - * recalibration timer, in case periodic recalibration is enabled using - * dg_configRF_RECALIBRATION_TIMER_TIMEOUT - * - * @note - * ~~~{.c} - * void hw_rf_precalib_cb(void) - * void hw_rf_postcalib_cb(void): - * ~~~ - * - * @note Called when the re-calibration (not the initial calibration) procedure - * starts/ends. Can be used to instruct the system not to go to sleep during - * this time. - * - * @note - * ~~~{.c} - * void hw_rf_apply_tcs_cb(void) - * ~~~ - * - * @note Called before applying the rf recommended settings. The implementation should - * apply the TCS values - * - * @note - * ~~~{.c} - * uint64_t hw_rf_get_start_iff_time(void) - * ~~~ - * - * @note Called to get the time when IFF calibration starts - * - * @note - * ~~~{.c} - * bool hw_rf_check_iff_timeout(uint64_t start_time) - * ~~~ - * - * @note Called to check if IFF calibration has timed-out (i.e. took too long). It takes argument the - * IFF calib start_time, as return by hw_rf_get_start_iff_time(). It should normally check against - * config macro dg_configRF_IFF_CALIBRATION_TIMEOUT. - * - * @warning All the above functions are called in a critical section. They should not block. - * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -102,6 +42,7 @@ * ***************************************************************************************** */ + #ifndef HW_RF_H_ #define HW_RF_H_ @@ -360,6 +301,19 @@ void hw_rf_request_off(bool mode_ble); */ void hw_rf_start_continuous_wave(uint8_t mode, uint8_t ch); +/** + * \brief Start reception of a continuous wave (unmodulated reception) + * + * \param [in] mode is the mode to use. 1: BLE, 2 or 3: FTDF (0: Normal, use hw_rf_stop_*) + * + * \param [in] ch is the Channel to receive on, calculated as: + * (mode is BLE) ch = (F – 2402) / 2, where F ranges from 2402 MHz to 2480 MHz. + * Range: 0x00 – 0x27. + * (mode is FTDF) ch = (F – 2405) / 5, where F ranges from 2405 MHz to 2480 MHz. + * Range: 0x00 – 0xf. + */ +void hw_rf_start_continuous_wave_rx(uint8_t mode, uint8_t ch); + /** * \brief Stop transmitting a continuous wave (unmodulated transmission) * diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h index 62ec2d8a5..ea91523ee 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h @@ -11,39 +11,39 @@ */ /** -**************************************************************************************** -* -* @file sys_tcs.h -* -* @brief TCS Handler header file. -* -* Copyright (c) 2016, Dialog Semiconductor -* All rights reserved. -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -* OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -**************************************************************************************** -*/ + **************************************************************************************** + * + * @file sys_tcs.h + * + * @brief TCS Handler header file. + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ #ifndef SYS_TCS_H_ #define SYS_TCS_H_ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c index cd4b16c4c..16e7ec8bb 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c @@ -8,44 +8,44 @@ */ /** -**************************************************************************************** -* -* @file hw_cpm.c -* -* @brief Clock and Power Manager Driver -* -* Copyright (c) 2016, Dialog Semiconductor -* All rights reserved. -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -* OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -**************************************************************************************** -*/ + **************************************************************************************** + * + * @file hw_aes_hash.c + * + * @brief Implementation of the AES/Hash Engine Low Level Driver. + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ #if dg_configUSE_HW_AES_HASH -#include "hw_aes_hash.h" -#include "hw_crypto.h" +#include +#include #define MODE_IS_AES(m) (m <= HW_AES_CTR) diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c index 0d2d466a6..a375f69fd 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c @@ -8,39 +8,39 @@ */ /** -**************************************************************************************** -* -* @file hw_cpm.c -* -* @brief Clock and Power Manager Driver -* -* Copyright (c) 2016, Dialog Semiconductor -* All rights reserved. -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -* OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -**************************************************************************************** -*/ + **************************************************************************************** + * + * @file hw_cpm.c + * + * @brief Clock and Power Manager Driver + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ #if dg_configUSE_HW_CPM @@ -88,481 +88,463 @@ static const bool cpm_1v8_state = false; uint32_t hw_cpm_sysclk_is_rc16(void) { - uint32_t ret = 0; + uint32_t ret = 0; - if (REG_GETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL) == SYS_CLK_IS_RC16) - { - ret = 1; - } + if (REG_GETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL) == SYS_CLK_IS_RC16) { + ret = 1; + } - return ret; + return ret; } uint32_t hw_cpm_sysclk_is_xtal16m(void) { - uint32_t ret = 0; + uint32_t ret = 0; - if (REG_GETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL) == SYS_CLK_IS_XTAL16M) - { - ret = 1; - } + if (REG_GETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL) == SYS_CLK_IS_XTAL16M) { + ret = 1; + } - return ret; + return ret; } void hw_cpm_set_divn(bool freq) { - uint32_t regval; - int val; + uint32_t regval; + int val; - if (freq) - { - val = 1; - } - else - { - val = 0; - } + if (freq) { + val = 1; + } + else { + val = 0; + } - regval = CRG_TOP->CLK_CTRL_REG; - REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, DIVN_XTAL32M_MODE, regval, val); - REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, XTAL32M_MODE, regval, val); - CRG_TOP->CLK_CTRL_REG = regval; + regval = CRG_TOP->CLK_CTRL_REG; + REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, DIVN_XTAL32M_MODE, regval, val); + REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, XTAL32M_MODE, regval, val); + CRG_TOP->CLK_CTRL_REG = regval; #if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - CRG_TOP->DIVN_SYNC_REG = val; + CRG_TOP->DIVN_SYNC_REG = val; #endif } bool hw_cpm_is_rc16_allowed(void) { - bool ret = false; - uint32_t tmp; + bool ret = false; + uint32_t tmp; - do - { - tmp = CRG_TOP->SYS_STAT_REG; + do { + tmp = CRG_TOP->SYS_STAT_REG; #ifdef CONFIG_USE_FTDF - - // Check FTDF - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP)) - { - break; - } - + // Check FTDF + if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP)) { + break; + } #endif #ifdef CONFIG_USE_BLE - - // Check BLE - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, BLE_IS_UP)) - { - break; - } - + // Check BLE + if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, BLE_IS_UP)) { + break; + } #endif - // Check APHY/DPHY & COEX - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, RAD_IS_UP)) - { - break; - } + // Check APHY/DPHY & COEX + if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, RAD_IS_UP)) { + break; + } - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, PER_IS_UP)) - { - // Check SRC - if (REG_GETF(APU, SRC1_CTRL_REG, SRC_EN) == 1) - { - break; - } + if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, PER_IS_UP)) { + // Check SRC + if (REG_GETF(APU, SRC1_CTRL_REG, SRC_EN) == 1) { + break; + } - // Check PDM - if (REG_GETF(CRG_PER, PDM_DIV_REG, CLK_PDM_EN) == 1) - { - break; - } + // Check PDM + if (REG_GETF(CRG_PER, PDM_DIV_REG, CLK_PDM_EN) == 1) { + break; + } - // Check USB - if (REG_GETF(USB, USB_MCTRL_REG, USBEN) == 1) - { - break; - } + // Check USB + if (REG_GETF(USB, USB_MCTRL_REG, USBEN) == 1) { + break; + } - tmp = CRG_PER->CLK_PER_REG; + tmp = CRG_PER->CLK_PER_REG; + // Check UART1/2 + if (tmp & REG_MSK(CRG_PER, CLK_PER_REG, UART_ENABLE)) { + break; + } - // Check UART1/2 - if (tmp & REG_MSK(CRG_PER, CLK_PER_REG, UART_ENABLE)) - { - break; - } + /* -------------------------------------------------------------------------------*/ - /* -------------------------------------------------------------------------------*/ + // Check ADC clock + if (REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_EN) && + (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, ADC_CLK_SEL)))) { + break; + } - // Check ADC clock - if (REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_EN) && - (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, ADC_CLK_SEL)))) - { - break; - } + // Check I2C clock + if ((tmp & REG_MSK(CRG_PER, CLK_PER_REG, I2C_ENABLE)) && + (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, I2C_CLK_SEL)))) { + break; + } - // Check I2C clock - if ((tmp & REG_MSK(CRG_PER, CLK_PER_REG, I2C_ENABLE)) && - (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, I2C_CLK_SEL)))) - { - break; - } + // Check SPI clock + if ((tmp & REG_MSK(CRG_PER, CLK_PER_REG, SPI_ENABLE)) && + (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, SPI_CLK_SEL)))) { + break; + } - // Check SPI clock - if ((tmp & REG_MSK(CRG_PER, CLK_PER_REG, SPI_ENABLE)) && - (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, SPI_CLK_SEL)))) - { - break; - } + // Check PCM clock + tmp = CRG_PER->PCM_DIV_REG; + if ((tmp & REG_MSK(CRG_PER, PCM_DIV_REG, CLK_PCM_EN)) && + (!(tmp & REG_MSK(CRG_PER, PCM_DIV_REG, PCM_SRC_SEL)))) { + break; + } - // Check PCM clock - tmp = CRG_PER->PCM_DIV_REG; + /* KBSCN and QUAD are not seriously affected by the clock switch and, thus, + * they cannot block it! + */ + } - if ((tmp & REG_MSK(CRG_PER, PCM_DIV_REG, CLK_PCM_EN)) && - (!(tmp & REG_MSK(CRG_PER, PCM_DIV_REG, PCM_SRC_SEL)))) - { - break; - } + tmp = CRG_TOP->CLK_TMR_REG; + // Check Timer0 clock + if ((tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_ENABLE)) && + (!(tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_CLK_SEL)))) { + break; + } - /* KBSCN and QUAD are not seriously affected by the clock switch and, thus, - * they cannot block it! - */ - } + // Check Timer2 clock + if ((tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_ENABLE)) && + (!(tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_CLK_SEL)))) { + break; + } - tmp = CRG_TOP->CLK_TMR_REG; + /* Breathe, SOC and WDOG are not seriously affected by the clock switch and, thus, + * they cannot block it! + */ - // Check Timer0 clock - if ((tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_ENABLE)) && - (!(tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_CLK_SEL)))) - { - break; - } + ret = true; + } while (0); - // Check Timer2 clock - if ((tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_ENABLE)) && - (!(tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_CLK_SEL)))) - { - break; - } - - /* Breathe, SOC and WDOG are not seriously affected by the clock switch and, thus, - * they cannot block it! - */ - - ret = true; - } - while (0); - - return ret; + return ret; } void hw_cpm_set_sysclk(uint32_t mode) { - /* Make sure a valid sys clock is requested */ - ASSERT_WARNING(mode <= SYS_CLK_IS_PLL); + /* Make sure a valid sys clock is requested */ + ASSERT_WARNING(mode <= SYS_CLK_IS_PLL); - REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, mode); + REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, mode); - // Wait until the switch is done! - switch (mode) - { - case SYS_CLK_IS_XTAL16M: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL16M) == 0) {} + // Wait until the switch is done! + switch (mode) { + case SYS_CLK_IS_XTAL16M: + while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL16M) == 0) {} + break; - break; + case SYS_CLK_IS_RC16: + while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_RC16M) == 0) {} + break; - case SYS_CLK_IS_RC16: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_RC16M) == 0) {} + case SYS_CLK_IS_LP: + while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_32K) == 0) {} + break; - break; + case SYS_CLK_IS_PLL: + while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M) == 0) {} + break; - case SYS_CLK_IS_LP: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_32K) == 0) {} - - break; - - case SYS_CLK_IS_PLL: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M) == 0) {} - - break; - - default: - ASSERT_WARNING(0); - break; - } + default: + ASSERT_WARNING(0); + break; + } } void hw_cpm_short_delay(void) { - volatile int i; + volatile int i; - for (i = 0; i < 20; i++); + for (i = 0; i < 20; i++); } void hw_cpm_pll_sys_on(void) { - /* Before enabling the PLL LDO, the 1.4V voltage needs to be present; in real-life this - * is achieved by first turning on the 1.4V ACORE LDO, then the DCDC converter to take over - * the generation of 1.4V and finally turning off the ACORE LDO. - */ + /* Before enabling the PLL LDO, the 1.4V voltage needs to be present; in real-life this + * is achieved by first turning on the 1.4V ACORE LDO, then the DCDC converter to take over + * the generation of 1.4V and finally turning off the ACORE LDO. + */ - /* LDO PLL enable. */ - REG_SET_BIT(GPREG, PLL_SYS_CTRL1_REG, LDO_PLL_ENABLE); + /* LDO PLL enable. */ + REG_SET_BIT(GPREG, PLL_SYS_CTRL1_REG, LDO_PLL_ENABLE); - /* Configure system PLL. */ - REG_SETF(GPREG, PLL_SYS_CTRL1_REG, PLL_R_DIV, 1); /* Default/reset value. */ + /* Configure system PLL. */ + REG_SETF(GPREG, PLL_SYS_CTRL1_REG, PLL_R_DIV, 1); /* Default/reset value. */ - /* Program N-divider and DEL_SEL. */ - REG_SET_BIT(GPREG, PLL_SYS_CTRL2_REG, PLL_SEL_MIN_CUR_INT); // Last review date: Feb 15, 2016 - 12:25:47 + /* Program N-divider and DEL_SEL. */ + REG_SET_BIT(GPREG, PLL_SYS_CTRL2_REG, PLL_SEL_MIN_CUR_INT); // Last review date: Feb 15, 2016 - 12:25:47 - /* Now turn on PLL. */ - REG_SET_BIT(GPREG, PLL_SYS_CTRL1_REG, PLL_EN); + /* Now turn on PLL. */ + REG_SET_BIT(GPREG, PLL_SYS_CTRL1_REG, PLL_EN); - while ((GPREG->PLL_SYS_STATUS_REG & REG_MSK(GPREG, PLL_SYS_STATUS_REG, LDO_PLL_OK)) == 0) {} + while ((GPREG->PLL_SYS_STATUS_REG & REG_MSK(GPREG, PLL_SYS_STATUS_REG, LDO_PLL_OK)) == 0) {} - /* And wait until lock. */ - while ((GPREG->PLL_SYS_STATUS_REG & REG_MSK(GPREG, PLL_SYS_STATUS_REG, PLL_LOCK_FINE)) == 0) {} + /* And wait until lock. */ + while ((GPREG->PLL_SYS_STATUS_REG & REG_MSK(GPREG, PLL_SYS_STATUS_REG, PLL_LOCK_FINE)) == 0) {} } void hw_cpm_pll_sys_off(void) { - // The PLL is not the system clk. - while ((CRG_TOP->CLK_CTRL_REG & REG_MSK(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M)) != 0); - - GPREG->PLL_SYS_CTRL1_REG = 0x0000; // Switch off the PLL. + // The PLL is not the system clk. + while ((CRG_TOP->CLK_CTRL_REG & REG_MSK(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M)) != 0); + GPREG->PLL_SYS_CTRL1_REG = 0x0000; // Switch off the PLL. } __RETAINED_CODE void hw_cpm_start_calibration(cal_clk_t clk_type, uint32_t cycles) { - ASSERT_WARNING(REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 0); // Must be disabled + ASSERT_WARNING(REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 0); // Must be disabled - ANAMISC->CLK_REF_CNT_REG = cycles; // # of cal clock cycles - REG_SETF(ANAMISC, CLK_REF_SEL_REG, REF_CLK_SEL, clk_type); - REG_SET_BIT(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START); + ANAMISC->CLK_REF_CNT_REG = cycles; // # of cal clock cycles + REG_SETF(ANAMISC, CLK_REF_SEL_REG, REF_CLK_SEL, clk_type); + REG_SET_BIT(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START); } uint32_t hw_cpm_get_calibration_data(void) { - uint32_t high; - uint32_t low; - uint32_t value; + uint32_t high; + uint32_t low; + uint32_t value; - while (REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 1); // Wait until it's finished + while (REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 1); // Wait until it's finished - high = ANAMISC->CLK_REF_VAL_H_REG; - low = ANAMISC->CLK_REF_VAL_L_REG; - value = (high << 16) + low; + high = ANAMISC->CLK_REF_VAL_H_REG; + low = ANAMISC->CLK_REF_VAL_L_REG; + value = ( high << 16 ) + low; - return value; + return value; } void hw_cpm_dcdc_config(void) { - uint32_t reg; + uint32_t reg; - /* - * Preferred settings section - * Last review date: Feb 15, 2016 - 12:25:47 - */ - REG_CLR_BIT(DCDC, DCDC_CTRL_0_REG, DCDC_FW_ENABLE); + /* + * Preferred settings section + * Last review date: January 03, 2017 - 16:26:35 + */ + REG_CLR_BIT(DCDC, DCDC_CTRL_0_REG, DCDC_FW_ENABLE); - reg = DCDC->DCDC_IRQ_MASK_REG; - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V18P_TIMEOUT_IRQ_MASK, reg, 1); - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_VDD_TIMEOUT_IRQ_MASK, reg, 1); - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V18_TIMEOUT_IRQ_MASK, reg, 1); - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V14_TIMEOUT_IRQ_MASK, reg, 1); - DCDC->DCDC_IRQ_MASK_REG = reg; + reg = DCDC->DCDC_IRQ_MASK_REG; + REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V18P_TIMEOUT_IRQ_MASK, reg, 1); + REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_VDD_TIMEOUT_IRQ_MASK, reg, 1); + REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V18_TIMEOUT_IRQ_MASK, reg, 1); + REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V14_TIMEOUT_IRQ_MASK, reg, 1); + DCDC->DCDC_IRQ_MASK_REG = reg; - REG_SET_BIT(DCDC, DCDC_TRIM_REG, DCDC_P_COMP_MAN_TRIM); + REG_SET_BIT(DCDC, DCDC_TRIM_REG, DCDC_P_COMP_MAN_TRIM); - DCDC->DCDC_V14_0_REG &= ~(REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_FAST_RAMPING)); +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + DCDC->DCDC_V14_0_REG &= ~(REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_CUR_LIM_MIN) | + REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_FAST_RAMPING)); - DCDC->DCDC_V18_0_REG &= ~(REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_FAST_RAMPING)); + DCDC->DCDC_V18_0_REG &= ~(REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_CUR_LIM_MIN) | + REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_FAST_RAMPING)); - DCDC->DCDC_V18P_0_REG &= ~(REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_FAST_RAMPING)); + DCDC->DCDC_V18P_0_REG &= ~(REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_CUR_LIM_MIN) | + REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_FAST_RAMPING)); - DCDC->DCDC_VDD_0_REG &= ~(REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_FAST_RAMPING)); + DCDC->DCDC_VDD_0_REG &= ~(REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_CUR_LIM_MIN) | + REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_FAST_RAMPING)); +#else + DCDC->DCDC_V14_0_REG &= ~REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_FAST_RAMPING); - REG_SETF(DCDC, DCDC_VDD_1_REG, DCDC_VDD_CUR_LIM_MAX_LV, 0xD); + DCDC->DCDC_V18_0_REG &= ~REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_FAST_RAMPING); - REG_SETF(DCDC, DCDC_V14_0_REG, DCDC_V14_VOLTAGE, 0x7); + DCDC->DCDC_V18P_0_REG &= ~REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_FAST_RAMPING); - if (dg_configPOWER_1V8_ACTIVE == 1) - { - REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, 0x16); - } + DCDC->DCDC_VDD_0_REG &= ~REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_FAST_RAMPING); - if (dg_configPOWER_1V8P == 1) - { - REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, 0x16); - } + reg = DCDC->DCDC_CTRL_2_REG; + REG_SET_FIELD(DCDC, DCDC_CTRL_2_REG, DCDC_LSSUP_TRIM, reg, 0); + REG_SET_FIELD(DCDC, DCDC_CTRL_2_REG, DCDC_HSGND_TRIM, reg, 0); + DCDC->DCDC_CTRL_2_REG = reg; +#endif - // End of preferred settings + REG_SETF(DCDC, DCDC_VDD_1_REG, DCDC_VDD_CUR_LIM_MAX_LV, 0xD); - DCDC->DCDC_VDD_1_REG |= ((1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_HV)) | - (1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_LV))); + REG_SETF(DCDC, DCDC_V14_0_REG, DCDC_V14_VOLTAGE, 0x8); - if ((dg_configPOWER_1V8_ACTIVE == 1) && cpm_1v8_state) - { - DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV)); - DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV); - } - else - { - DCDC->DCDC_V18_1_REG &= ~(REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV) | - REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); - } + if (dg_configPOWER_1V8_ACTIVE == 1) { + REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, 0x16); + } - if (dg_configPOWER_1V8P == 1) - { - DCDC->DCDC_V18P_1_REG |= (1 << REG_POS(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_HV)); - DCDC->DCDC_V18P_1_REG &= ~REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_LV); - } - else - { - DCDC->DCDC_V18P_1_REG &= ~(REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_HV) | - REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_LV)); - } + if (dg_configPOWER_1V8P == 1) { + REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, 0x16); + } + // End of preferred settings + + DCDC->DCDC_VDD_1_REG |= ((1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_HV)) | + (1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_LV))); + + if ((dg_configPOWER_1V8_ACTIVE == 1) && cpm_1v8_state) { + DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV)); + DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV); + } + else { + DCDC->DCDC_V18_1_REG &= ~(REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV) | + REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); + } + + if (dg_configPOWER_1V8P == 1) { + DCDC->DCDC_V18P_1_REG |= (1 << REG_POS(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_HV)); + DCDC->DCDC_V18P_1_REG &= ~REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_LV); + } + else { + DCDC->DCDC_V18P_1_REG &= ~(REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_HV) | + REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_LV)); + } } void hw_cpm_dcdc_on(void) { - DCDC->DCDC_V14_1_REG |= ((1 << REG_POS(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_HV)) | - (1 << REG_POS(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_LV))); + DCDC->DCDC_V14_1_REG |= ((1 << REG_POS(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_HV)) | + (1 << REG_POS(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_LV))); - REG_SETF(DCDC, DCDC_VDD_0_REG, DCDC_VDD_VOLTAGE, 0x10); // 1.2 V + REG_SETF(DCDC, DCDC_VDD_0_REG, DCDC_VDD_VOLTAGE, 0x10); // 1.2 V - REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 1); + REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 1); - // Trim the LDOs down to lowest possible voltage so DCDC can take over - CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_SETVDD); - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, 0x2); + // Trim the LDOs down to lowest possible voltage so DCDC can take over + CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_SETVDD); + REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, 0x2); - // Turn off LDOs - CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_ENABLE); - CRG_TOP->LDO_CTRL2_REG &= ~(REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V2_ON) | - REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON) | - REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_ON)); + // Turn off LDOs + CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_ENABLE); + CRG_TOP->LDO_CTRL2_REG &= ~(REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V2_ON) | + REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON) | + REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_ON)); - // Trim the LDOs back to normal levels - hw_cpm_reset_radio_vdd(); - CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD); + // Trim the LDOs back to normal levels + hw_cpm_reset_radio_vdd(); + CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD); } void hw_cpm_set_preferred_values(void) { - uint32_t reg; + uint32_t reg; - reg = CRG_TOP->CLK_16M_REG; + reg = CRG_TOP->CLK_16M_REG; - REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_HPASS_FLT_EN, reg, 1); // Last review date: Feb 15, 2016 - 12:25:47 - REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_AMP_TRIM, reg, 5); - REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_CUR_SET, reg, 5); + REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_HPASS_FLT_EN, reg, 1); // Last review date: Feb 15, 2016 - 12:25:47 + REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_AMP_TRIM, reg, 5); + REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_CUR_SET, reg, 5); - CRG_TOP->CLK_16M_REG = reg; + CRG_TOP->CLK_16M_REG = reg; - REG_SETF(CRG_TOP, BANDGAP_REG, LDO_SLEEP_TRIM, 0x8); + REG_SETF(CRG_TOP, BANDGAP_REG, LDO_SLEEP_TRIM, 0x8); #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - REG_SETF(CRG_TOP, BANDGAP_REG, BYPASS_COLD_BOOT_DISABLE, 1); // Last review date: Feb 15, 2016 - 12:25:47 + REG_SETF(CRG_TOP, BANDGAP_REG, BYPASS_COLD_BOOT_DISABLE, 1); // Last review date: Feb 15, 2016 - 12:25:47 +#else + /* Hardcoding this since this will be used in AUTO mode as well (uartboot), where + * the AE datasheet is included (it doesn't contain this reg) + */ + volatile uint16_t *xtal16m_ctrl_reg = (volatile uint16_t *)0x50000056; + + /* The following code corresponds to (in BB): + REG_SET_FIELD(CRG_TOP, XTAL16M_CTRL_REG, XTAL16M_ENABLE_ZERO, reg, 1); + REG_SET_FIELD(CRG_TOP, XTAL16M_CTRL_REG, XTAL16M_AMP_REG_SIG_SEL, reg, 1); + */ + *xtal16m_ctrl_reg |= 0x100UL | 0x8UL; + + /* The following corresponds to + REG_SETF(CRG_TOP, BANDGAP_REG, LDO_SUPPLY_USE_BGREF, 1); + */ + CRG_TOP->BANDGAP_REG |= 0x4000UL; #endif } void hw_cpm_configure_xtal32k_pins(void) { - GPIO->P20_MODE_REG = 0x26; - GPIO->P21_MODE_REG = 0x26; + GPIO->P20_MODE_REG = 0x26; + GPIO->P21_MODE_REG = 0x26; } void hw_cpm_configure_ext32k_pins(void) { - GPIO->P20_MODE_REG = 0x0; + GPIO->P20_MODE_REG = 0x0; } void hw_cpm_trigger_sw_cursor(void) { - if (dg_configUSE_SW_CURSOR == 1) - { - if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) - { - SW_CURSOR_SET = 1 << SW_CURSOR_PIN; + if (dg_configUSE_SW_CURSOR == 1) { + if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) { + SW_CURSOR_SET = 1 << SW_CURSOR_PIN; + } + else { + SW_CURSOR_RESET = 1 << SW_CURSOR_PIN; + } + + SW_CURSOR_GPIO = 0x300; + + hw_cpm_delay_usec(50); + + if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) { + SW_CURSOR_RESET = 1 << SW_CURSOR_PIN; + } + + hw_cpm_setup_sw_cursor(); } - else - { - SW_CURSOR_RESET = 1 << SW_CURSOR_PIN; - } - - SW_CURSOR_GPIO = 0x300; - - hw_cpm_delay_usec(50); - - if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) - { - SW_CURSOR_RESET = 1 << SW_CURSOR_PIN; - } - - hw_cpm_setup_sw_cursor(); - } } void hw_cpm_reset_system(void) { - __asm volatile(" cpsid i "); + __asm volatile ( " cpsid i " ); - hw_watchdog_unregister_int(); - hw_watchdog_set_pos_val(1); - hw_watchdog_unfreeze(); + hw_watchdog_unregister_int(); + hw_watchdog_set_pos_val(1); + hw_watchdog_unfreeze(); - while (1); + while (1); } void hw_cpm_reboot_system(void) { - __asm volatile(" cpsid i "); + __asm volatile ( " cpsid i " ); - hw_watchdog_gen_RST(); - hw_watchdog_set_pos_val(1); - hw_watchdog_unfreeze(); + hw_watchdog_gen_RST(); + hw_watchdog_set_pos_val(1); + hw_watchdog_unfreeze(); - while (1); + while (1); } void hw_cpm_assert_trigger_gpio(void) { - if (EXCEPTION_DEBUG == 1) - { - if (dg_configLP_CLK_SOURCE == LP_CLK_IS_DIGITAL) - { - hw_cpm_configure_ext32k_pins(); - } - else if ((dg_configUSE_LP_CLK == LP_CLK_32000) - || (dg_configUSE_LP_CLK == LP_CLK_32768)) - { - hw_cpm_configure_xtal32k_pins(); - } + if (EXCEPTION_DEBUG == 1) { + if (dg_configLP_CLK_SOURCE == LP_CLK_IS_DIGITAL) { + hw_cpm_configure_ext32k_pins(); + } else if ((dg_configUSE_LP_CLK == LP_CLK_32000) + || (dg_configUSE_LP_CLK == LP_CLK_32768)) { + hw_cpm_configure_xtal32k_pins(); + } + hw_cpm_power_up_per_pd(); + hw_cpm_deactivate_pad_latches(); - hw_cpm_power_up_per_pd(); - hw_cpm_deactivate_pad_latches(); - - DBG_SET_HIGH(EXCEPTION_DEBUG, EXCEPTIONDBG); - } + DBG_SET_HIGH(EXCEPTION_DEBUG, EXCEPTIONDBG); + } } #define HW_CPM_ACTIVATE_BOD_PROTECTION \ @@ -594,296 +576,276 @@ do { void hw_cpm_activate_bod_protection(void) { - HW_CPM_ACTIVATE_BOD_PROTECTION + HW_CPM_ACTIVATE_BOD_PROTECTION } void hw_cpm_activate_bod_protection_at_init(void) { - HW_CPM_ACTIVATE_BOD_PROTECTION + HW_CPM_ACTIVATE_BOD_PROTECTION } void hw_cpm_configure_bod_protection(void) { - REG_SETF(CRG_TOP, BOD_CTRL_REG, BOD_VDD_LVL, 1); /* VDD Level (700mV) */ + REG_SETF(CRG_TOP, BOD_CTRL_REG, BOD_VDD_LVL, 1); /* VDD Level (700mV) */ - if (hw_cpm_bod_enabled_in_tcs == 0) - { - /* VBAT enable */ - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_VBAT_EN); + if (hw_cpm_bod_enabled_in_tcs == 0) { + /* VBAT enable */ + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_VBAT_EN); - /* 1V8 Flash enable */ - if ((dg_configPOWER_1V8_ACTIVE == 1) && (dg_configPOWER_1V8_SLEEP == 1)) - { - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); - } - else - { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); - } + /* 1V8 Flash enable */ + if ((dg_configPOWER_1V8_ACTIVE == 1) && (dg_configPOWER_1V8_SLEEP == 1)) { + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); + } else { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); + } - /* 1V8P enable */ - if (dg_configPOWER_1V8P == 1) - { - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); + /* 1V8P enable */ + if (dg_configPOWER_1V8P == 1) { + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); + } else { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); + } + /* Generate Reset on a BOD event */ + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_RESET_EN); } - else - { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); + else { + CRG_TOP->BOD_CTRL2_REG = hw_cpm_bod_enabled_in_tcs; } - - /* Generate Reset on a BOD event */ - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_RESET_EN); - } - else - { - CRG_TOP->BOD_CTRL2_REG = hw_cpm_bod_enabled_in_tcs; - } } void hw_cpm_set_1v8_state(bool state) { - if ((dg_configPOWER_1V8_ACTIVE == 1) && (cpm_1v8_state != state)) - { - uint32_t reg; - uint32_t dcdc_state; + if ((dg_configPOWER_1V8_ACTIVE == 1) && (cpm_1v8_state != state)) { + uint32_t reg; + uint32_t dcdc_state; - GLOBAL_INT_DISABLE(); + GLOBAL_INT_DISABLE(); - reg = CRG_TOP->LDO_CTRL2_REG; - dcdc_state = (uint32_t)REG_GETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE); + reg = CRG_TOP->LDO_CTRL2_REG; + dcdc_state = (uint32_t)REG_GETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE); #if (dg_configPOWER_1V8_ACTIVE == 1) - cpm_1v8_state = state; + cpm_1v8_state = state; #endif - if (!cpm_1v8_state) - { - // Disable BOD for the 1V8 rail - if (dg_configUSE_BOD == 1) - { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); - } + if (!cpm_1v8_state) { + // Disable BOD for the 1V8 rail + if (dg_configUSE_BOD == 1) { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); + } - // Deactivate 1V8 rail in LDOs - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, reg); + // Deactivate 1V8 rail in LDOs + REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, reg); - if (dg_configPOWER_1V8_SLEEP == 1) - { - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, - reg, 1); - } + if (dg_configPOWER_1V8_SLEEP == 1) { + REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, + reg, 1); + } - CRG_TOP->LDO_CTRL2_REG = reg; + CRG_TOP->LDO_CTRL2_REG = reg; - // Deactivate 1V8 rail in DCDC - if (dg_configUSE_DCDC == 1) - { - // Disable DCDC to apply change - REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 0); + // Deactivate 1V8 rail in DCDC + if (dg_configUSE_DCDC == 1) { + // Disable DCDC to apply change + REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 0); - DCDC->DCDC_V18_1_REG &= - ~(REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV) | - REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); + DCDC->DCDC_V18_1_REG &= + ~(REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV) | + REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); - // Restore DCDC - REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, dcdc_state); - } + // Restore DCDC + REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, dcdc_state); + } + } else { + // Restore 1V8 rail in LDOs + /* But not when DCDC is running... */ + if (dcdc_state != 1) { + REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, + reg, 1); + } + + if (dg_configPOWER_1V8_SLEEP == 1) { + REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, + reg); + } + + CRG_TOP->LDO_CTRL2_REG = reg; + + // Restore 1V8 rail in DCDC + if (dg_configUSE_DCDC == 1) { + DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, + DCDC_V18_ENABLE_HV)); + DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, + DCDC_V18_ENABLE_LV); + } + + // Restore BOD setup + if (dg_configUSE_BOD == 1) { + hw_cpm_delay_usec(200); + hw_cpm_configure_bod_protection(); + } + } + + GLOBAL_INT_RESTORE(); } - else - { - // Restore 1V8 rail in LDOs - /* But not when DCDC is running... */ - if (dcdc_state != 1) - { - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, - reg, 1); - } - - if (dg_configPOWER_1V8_SLEEP == 1) - { - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, - reg); - } - - CRG_TOP->LDO_CTRL2_REG = reg; - - // Restore 1V8 rail in DCDC - if (dg_configUSE_DCDC == 1) - { - DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, - DCDC_V18_ENABLE_HV)); - DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, - DCDC_V18_ENABLE_LV); - } - - // Restore BOD setup - if (dg_configUSE_BOD == 1) - { - hw_cpm_delay_usec(200); - hw_cpm_configure_bod_protection(); - } - } - - GLOBAL_INT_RESTORE(); - } } bool hw_cpm_get_1v8_state(void) { - return cpm_1v8_state; + return cpm_1v8_state; } void hw_cpm_delay_usec(uint32_t usec) { - sys_clk_t sclk; - ahb_div_t hclk; - uint8_t freq; + sys_clk_t sclk; + ahb_div_t hclk; + uint8_t freq; - sclk = cm_sysclk; - hclk = cm_ahbclk; - freq = 16 >> hclk; + sclk = cm_sysclk; + hclk = cm_ahbclk; + freq = 16 >> hclk; - /* Requested delay time must be > 0 usec */ - ASSERT_WARNING(usec != 0); + /* Requested delay time must be > 0 usec */ + ASSERT_WARNING(usec != 0); - /* - * ldr r3, [pc, #148] 2 cycles - * push {r4, lr} 2 cycles - * ldrb r1, [r3, #17] 2 cycles - * ldrb r2, [r3, #8] 2 cycles - * movs r3, #16 1 cycle - * asrs r3, r2 1 cycle - * uxtb r3, r2 1 cycle - * ---------- - * cmp r0, #0 4 cycles overhead in total - * bne.n 0x8003106 - * cpsid i - * bkpt 0x0002 - * - * Total: 11 cycles - */ + /* + * ldr r3, [pc, #148] 2 cycles + * push {r4, lr} 2 cycles + * ldrb r1, [r3, #17] 2 cycles + * ldrb r2, [r3, #8] 2 cycles + * movs r3, #16 1 cycle + * asrs r3, r2 1 cycle + * uxtb r3, r2 1 cycle + * ---------- + * cmp r0, #0 4 cycles overhead in total + * bne.n 0x8003106 + * cpsid i + * bkpt 0x0002 + * + * Total: 11 cycles + */ - __asm volatile(" cmp %[sclk], #1 \n" // 1 cycle : 1 (sysclk_RC16, sysclk_XTAL16M) - " ble start \n" // 1 or 3 cycles: 2/4 - " cmp %[sclk], #3 \n" // 1 cycle : 3 (sysclk_PLL48) - " bgt s96M \n" // 1 or 3 cycles: 4/6 - " blt s32M \n" // 1 or 3 cycles: 5/7 - "s48M: add r4, %[freq], %[freq] \n" // 1 cycle : 6 - " add %[freq], r4, %[freq] \n" // 1 cycle : 7 - " b start \n" // 3 cycles : 10 - "s96M: add r4, %[freq], %[freq] \n" // 1 cycle : 7 - " add %[freq], r4, %[freq] \n" // 1 cycle : 8 - " lsl %[freq], %[freq], #1 \n" // 1 cycle : 9 - " b start \n" // 3 cycles : 12 - "s32M: lsl %[freq], %[freq], #1 \n" // 1 cycle : 8 - /* -----------------------------------------------------*/ - /* Overhead up to this point: - * sysclk_RC16 : 15 cycles (error: 15/16 - 15 usec) - * sysclk_XTAL16M : 15 cycles (error: 15/16 - 15 usec) - * sysclk_XTAL32M : 19 cycles (error: 19/32 - 19/2 usec) - * sysclk_PLL48 : 21 cycles (error: 21/48 - 21/3 usec) - * sysclk_PLL96 : 23 cycles (error: 23/96 - 23/6 usec) - */ - "start: cmp %[freq], #16 \n" // 1 cycle : 1 - " bgt high \n" // 1 or 3 cycles: 2/4 - " blt low \n" // 1 or 3 cycles: 3/5 - " mov %[sclk], #4 \n" // 1 cycle : 4 - " b calc \n" // 3 cycles : 7 - "high: cmp %[freq], #24 \n" // 1 cycle : 5 - " bne c32M \n" // 1 or 3 cycles: 6/8 - " mov %[sclk], #6 \n" // 1 cycle : 7 - " b calc \n" // 3 cycles : 10 - "c32M: cmp %[freq], #32 \n" // 1 cycle : 9 - " bne c48M \n" // 1 or 3 cycles: 10/12 - " mov %[sclk], #8 \n" // 1 cycle : 11 - " b calc \n" // 3 cycles : 12 - "c48M: cmp %[freq], #48 \n" // 1 cycle : 13 - " bne c96M \n" // 1 or 3 cycles: 14/16 - " mov %[sclk], #12 \n" // 1 cycle : 15 - " b calc \n" // 3 cycles : 18 - "c96M: mov %[sclk], #24 \n" // 1 cycle : 17 - " b calc \n" // 3 cycles : 20 - "low: cmp %[freq], #1 \n" // 1 cycle : 6 - " bgt c2M \n" // 1 or 3 cycles: 7/9 - " lsr %[usec], %[usec], #2 \n" // 1 cycle : 8 - " b loop \n" // 3 cycles : 11 - "c2M: cmp %[freq], #2 \n" // 1 cycle : 10 - " bgt c3M \n" // 1 or 3 cycles: 11/13 - " lsr %[usec], %[usec], #1 \n" // 1 cycle : 12 - " b loop \n" // 3 cycles : 15 - "c3M: cmp %[freq], #3 \n" // 1 cycle : 14 - " bgt c4M \n" // 1 or 3 cycles: 15/17 - " lsr %[usec], %[usec], #1 \n" // 1 cycle : 16 - " b loop1 \n" // 3 cycles : 19 - "c4M: cmp %[freq], #4 \n" // 1 cycle : 18 - " bgt c6M \n" // 1 or 3 cycles: 19/21 - " b loop \n" // 3 cycles : 22 - "c6M: cmp %[freq],#6 \n" // 1 cycle : 22 - " bgt c8M \n" // 1 or 3 cycles: 23/25 - " b loop1 \n" // 3 cycles : 26 - "c8M: cmp %[freq], #8 \n" // 1 cycle : 26 - " bgt c12M \n" // 1 or 3 cycles: 27/29 - " mov %[sclk], #2 \n" // 1 cycle : 28 - " b calc \n" // 3 cycles : 31 - "c12M: mov %[sclk], #2 \n" // 1 cycle : 30 - " mul %[usec], %[sclk], %[usec] \n" // 1 cycle : 31 - /* Error: - * 1MHz: 11 cycles, 11usec - * 2MHz: 15 cycles, 7.5usec - * 3MHz: 19 cycles, 6.33usec - * 4MHz: 22 cycles, 5.5usec - * 6MHz: 26 cycles, 4.33usec - * 8MHz: 31 cycles, 3.875usec - * 12MHz: 31 cycles, 2.584usec - * 16MHz: 8 cycles, 0.5usec - * 24MHz: 11 cycles, 0.459usec - * 32MHz: 13 cycles, 0.406usec - * 48MHz: 19 cycles, 0.396usec - * 96MHz: 21 cycles, 0.219usec - * - * 1 loop of 4 cycles is --- 1 usec is # loops - * 1MHz: 4usec --- divide (usec) by 4 (up to 5usec error) - * 2MHz: 2usec --- divide (usec) by 2 (up to 2usec error) - * 4MHz: 1usec --- 1 loop ( 0*4 + 1*2, 0.5000usec error) - * 8MHz: 500nsec --- 2 loops ( 1*4 + 1*2, 0.2500usec error) - * 16MHz: 250nsec --- 4 loops ( 3*4 + 1*2, 0.5000usec error) - * 24MHz: 167nsec --- 6 loops ( 5*4 + 1*2, 0.0830usec error) - * 32MHz: 125nsec --- 8 loops ( 7*4 + 1*2, 0.0625usec error) - * 48MHz: 84nsec --- 12 loops (11*4 + 1*2, 0.0420usec error) - * 96MHz: 42nsec --- 24 loops (23*4 + 1*2, 0.0210usec error) - * - * 1 loop of 6 cycles is --- 1 usec is # loops - * 3MHz: 2usec --- divide (usec) by 2 (up to 3usec error) - * 6MHz: 1usec --- 1 loop ( 0*6 + 1*7, 0.1670usec error) - * 12MHz: 0.5usec --- 2 loops ( 1*6 + 1*7, 0.0830usec error) - * - * Cumulative error is: - * 1MHz: 11 + 5 = 16usec - * 2MHz: 7.5 + 2 = 9.5usec - * 3MHz: 6.33 + 3 = 9.33usec - * 4MHz: 5.5 + 0.5 = 6usec - * 6MHz: 4.33 + 0.167 = 4.5usec - * 8MHz: 3.875 + 0.25 = 4.125usec - * 12MHz: 2.584 + 0.083 = 2.67usec - * 16MHz: 0.5 + 0.5 = 1usec - * 24MHz: 0.459 + 0.083 = 0.541usec - * 32MHz: 0.406 + 0.0625 = 0.469usec - * 48MHz: 0.396 + 0.042 = 0.438usec - * 96MHz: 0.219 + 0.021 = 0.429usec - */ - "loop1: sub %[usec], %[usec], #1 \n" // 1 cycle - " nop \n" // 1 cycle - " nop \n" // 1 cycle - " bne loop1 \n" // 3 cycles except for the last one which is 1 - " b exit \n" // 3 cycles - "calc: mul %[usec], %[sclk], %[usec] \n" // 1 cycle - "loop: sub %[usec], %[usec], #1 \n" // 1 cycle - " bne loop \n" // 3 cycles except for the last one which is 1 - "exit: \n" - : - : /* output */ - [usec] "r"(usec), [freq] "r"(freq), [sclk] "r"(sclk) : /* inputs (%0, %1, %2) */ - "r4"); /* registers that are destroyed */ + __asm volatile( " cmp %[sclk], #1 \n" // 1 cycle : 1 (sysclk_RC16, sysclk_XTAL16M) + " ble start \n" // 1 or 3 cycles: 2/4 + " cmp %[sclk], #3 \n" // 1 cycle : 3 (sysclk_PLL48) + " bgt s96M \n" // 1 or 3 cycles: 4/6 + " blt s32M \n" // 1 or 3 cycles: 5/7 + "s48M: add r4, %[freq], %[freq] \n" // 1 cycle : 6 + " add %[freq], r4, %[freq] \n" // 1 cycle : 7 + " b start \n" // 3 cycles : 10 + "s96M: add r4, %[freq], %[freq] \n" // 1 cycle : 7 + " add %[freq], r4, %[freq] \n" // 1 cycle : 8 + " lsl %[freq], %[freq], #1 \n" // 1 cycle : 9 + " b start \n" // 3 cycles : 12 + "s32M: lsl %[freq], %[freq], #1 \n" // 1 cycle : 8 + /* -----------------------------------------------------*/ + /* Overhead up to this point: + * sysclk_RC16 : 15 cycles (error: 15/16 - 15 usec) + * sysclk_XTAL16M : 15 cycles (error: 15/16 - 15 usec) + * sysclk_XTAL32M : 19 cycles (error: 19/32 - 19/2 usec) + * sysclk_PLL48 : 21 cycles (error: 21/48 - 21/3 usec) + * sysclk_PLL96 : 23 cycles (error: 23/96 - 23/6 usec) + */ + "start: cmp %[freq], #16 \n" // 1 cycle : 1 + " bgt high \n" // 1 or 3 cycles: 2/4 + " blt low \n" // 1 or 3 cycles: 3/5 + " mov %[sclk], #4 \n" // 1 cycle : 4 + " b calc \n" // 3 cycles : 7 + "high: cmp %[freq], #24 \n" // 1 cycle : 5 + " bne c32M \n" // 1 or 3 cycles: 6/8 + " mov %[sclk], #6 \n" // 1 cycle : 7 + " b calc \n" // 3 cycles : 10 + "c32M: cmp %[freq], #32 \n" // 1 cycle : 9 + " bne c48M \n" // 1 or 3 cycles: 10/12 + " mov %[sclk], #8 \n" // 1 cycle : 11 + " b calc \n" // 3 cycles : 12 + "c48M: cmp %[freq], #48 \n" // 1 cycle : 13 + " bne c96M \n" // 1 or 3 cycles: 14/16 + " mov %[sclk], #12 \n" // 1 cycle : 15 + " b calc \n" // 3 cycles : 18 + "c96M: mov %[sclk], #24 \n" // 1 cycle : 17 + " b calc \n" // 3 cycles : 20 + "low: cmp %[freq], #1 \n" // 1 cycle : 6 + " bgt c2M \n" // 1 or 3 cycles: 7/9 + " lsr %[usec], %[usec], #2 \n" // 1 cycle : 8 + " b loop \n" // 3 cycles : 11 + "c2M: cmp %[freq], #2 \n" // 1 cycle : 10 + " bgt c3M \n" // 1 or 3 cycles: 11/13 + " lsr %[usec], %[usec], #1 \n" // 1 cycle : 12 + " b loop \n" // 3 cycles : 15 + "c3M: cmp %[freq], #3 \n" // 1 cycle : 14 + " bgt c4M \n" // 1 or 3 cycles: 15/17 + " lsr %[usec], %[usec], #1 \n" // 1 cycle : 16 + " b loop1 \n" // 3 cycles : 19 + "c4M: cmp %[freq], #4 \n" // 1 cycle : 18 + " bgt c6M \n" // 1 or 3 cycles: 19/21 + " b loop \n" // 3 cycles : 22 + "c6M: cmp %[freq],#6 \n" // 1 cycle : 22 + " bgt c8M \n" // 1 or 3 cycles: 23/25 + " b loop1 \n" // 3 cycles : 26 + "c8M: cmp %[freq], #8 \n" // 1 cycle : 26 + " bgt c12M \n" // 1 or 3 cycles: 27/29 + " mov %[sclk], #2 \n" // 1 cycle : 28 + " b calc \n" // 3 cycles : 31 + "c12M: mov %[sclk], #2 \n" // 1 cycle : 30 + " mul %[usec], %[sclk], %[usec] \n" // 1 cycle : 31 + /* Error: + * 1MHz: 11 cycles, 11usec + * 2MHz: 15 cycles, 7.5usec + * 3MHz: 19 cycles, 6.33usec + * 4MHz: 22 cycles, 5.5usec + * 6MHz: 26 cycles, 4.33usec + * 8MHz: 31 cycles, 3.875usec + * 12MHz: 31 cycles, 2.584usec + * 16MHz: 8 cycles, 0.5usec + * 24MHz: 11 cycles, 0.459usec + * 32MHz: 13 cycles, 0.406usec + * 48MHz: 19 cycles, 0.396usec + * 96MHz: 21 cycles, 0.219usec + * + * 1 loop of 4 cycles is --- 1 usec is # loops + * 1MHz: 4usec --- divide (usec) by 4 (up to 5usec error) + * 2MHz: 2usec --- divide (usec) by 2 (up to 2usec error) + * 4MHz: 1usec --- 1 loop ( 0*4 + 1*2, 0.5000usec error) + * 8MHz: 500nsec --- 2 loops ( 1*4 + 1*2, 0.2500usec error) + * 16MHz: 250nsec --- 4 loops ( 3*4 + 1*2, 0.5000usec error) + * 24MHz: 167nsec --- 6 loops ( 5*4 + 1*2, 0.0830usec error) + * 32MHz: 125nsec --- 8 loops ( 7*4 + 1*2, 0.0625usec error) + * 48MHz: 84nsec --- 12 loops (11*4 + 1*2, 0.0420usec error) + * 96MHz: 42nsec --- 24 loops (23*4 + 1*2, 0.0210usec error) + * + * 1 loop of 6 cycles is --- 1 usec is # loops + * 3MHz: 2usec --- divide (usec) by 2 (up to 3usec error) + * 6MHz: 1usec --- 1 loop ( 0*6 + 1*7, 0.1670usec error) + * 12MHz: 0.5usec --- 2 loops ( 1*6 + 1*7, 0.0830usec error) + * + * Cumulative error is: + * 1MHz: 11 + 5 = 16usec + * 2MHz: 7.5 + 2 = 9.5usec + * 3MHz: 6.33 + 3 = 9.33usec + * 4MHz: 5.5 + 0.5 = 6usec + * 6MHz: 4.33 + 0.167 = 4.5usec + * 8MHz: 3.875 + 0.25 = 4.125usec + * 12MHz: 2.584 + 0.083 = 2.67usec + * 16MHz: 0.5 + 0.5 = 1usec + * 24MHz: 0.459 + 0.083 = 0.541usec + * 32MHz: 0.406 + 0.0625 = 0.469usec + * 48MHz: 0.396 + 0.042 = 0.438usec + * 96MHz: 0.219 + 0.021 = 0.429usec + */ + "loop1: sub %[usec], %[usec], #1 \n" // 1 cycle + " nop \n" // 1 cycle + " nop \n" // 1 cycle + " bne loop1 \n" // 3 cycles except for the last one which is 1 + " b exit \n" // 3 cycles + "calc: mul %[usec], %[sclk], %[usec] \n" // 1 cycle + "loop: sub %[usec], %[usec], #1 \n" // 1 cycle + " bne loop \n" // 3 cycles except for the last one which is 1 + "exit: \n" + : + : /* output */ + [usec] "r" (usec), [freq] "r" (freq), [sclk] "r" (sclk) : /* inputs (%0, %1, %2) */ + "r4"); /* registers that are destroyed */ } #endif /* dg_configUSE_HW_CPM */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c index 0100a16c0..b43a393b0 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c @@ -8,39 +8,39 @@ */ /** -**************************************************************************************** -* -* @file hw_cpm.c -* -* @brief Clock and Power Manager Driver -* -* Copyright (c) 2016, Dialog Semiconductor -* All rights reserved. -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -* OF THE POSSIBILITY OF SUCH DAMAGE. -* -* -**************************************************************************************** -*/ + **************************************************************************************** + * + * @file hw_crypto.c + * + * @brief Implementation of interrupt handling for the AES/Hash and ECC Engines. + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ #if (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC) diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c index 0dcfb90d4..a90e4460a 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c @@ -54,10 +54,9 @@ # define SEGGER_SYSTEMVIEW_ISR_EXIT() #endif -static struct hw_dma_callback_data -{ - hw_dma_transfer_cb callback; - void *user_data; +static struct hw_dma_callback_data { + hw_dma_transfer_cb callback; + void *user_data; } dma_callbacks_user_data[8]; #define DMA_CHN_REG(reg, chan) ((volatile uint16 *)(&(reg)) + ((chan) * 8)) @@ -70,251 +69,224 @@ static struct hw_dma_callback_data */ void hw_dma_channel_initialization(DMA_setup *channel_setup) { - volatile uint16 *dma_x_ctrl_reg; - volatile uint16 *dma_x_a_start_low_reg; - volatile uint16 *dma_x_a_start_high_reg; - volatile uint16 *dma_x_b_start_low_reg; - volatile uint16 *dma_x_b_start_high_reg; - volatile uint16 *dma_x_len_reg; - volatile uint16 *dma_x_int_reg; - uint32 src_address; - uint32 dest_address; + volatile uint16 *dma_x_ctrl_reg; + volatile uint16 *dma_x_a_start_low_reg; + volatile uint16 *dma_x_a_start_high_reg; + volatile uint16 *dma_x_b_start_low_reg; + volatile uint16 *dma_x_b_start_high_reg; + volatile uint16 *dma_x_len_reg; + volatile uint16 *dma_x_int_reg; + uint32 src_address; + uint32 dest_address; - /* Make sure the DMA channel length is not zero */ - ASSERT_WARNING(channel_setup->length > 0); + /* Make sure the DMA channel length is not zero */ + ASSERT_WARNING(channel_setup->length > 0); - // Look up DMAx_CTRL_REG address - dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_setup->channel_number); + // Look up DMAx_CTRL_REG address + dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_setup->channel_number); - // Look up DMAx_A_STARTL_REG address - dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel_setup->channel_number); + // Look up DMAx_A_STARTL_REG address + dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel_setup->channel_number); - // Look up DMAx_A_STARTH_REG address - dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel_setup->channel_number); + // Look up DMAx_A_STARTH_REG address + dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel_setup->channel_number); - // Look up DMAx_B_STARTL_REG address - dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel_setup->channel_number); + // Look up DMAx_B_STARTL_REG address + dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel_setup->channel_number); - // Look up DMAx_B_STARTH_REG address - dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel_setup->channel_number); + // Look up DMAx_B_STARTH_REG address + dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel_setup->channel_number); - // Look up DMAX_LEN_REG address - dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel_setup->channel_number); + // Look up DMAX_LEN_REG address + dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel_setup->channel_number); - // Look up DMAX_INT - dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel_setup->channel_number); + // Look up DMAX_INT + dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel_setup->channel_number); - // Make sure DMA channel is disabled first - REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, HW_DMA_STATE_DISABLED); + // Make sure DMA channel is disabled first + REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, HW_DMA_STATE_DISABLED); - // Set DMAx_CTRL_REG width provided settings, but do not start the channel. - // Start the channel with the "dma_channel_enable" function separately. - *dma_x_ctrl_reg = - channel_setup->bus_width | - channel_setup->irq_enable | - channel_setup->dreq_mode | - channel_setup->b_inc | - channel_setup->a_inc | - channel_setup->circular | - channel_setup->dma_prio | - channel_setup->dma_idle | - channel_setup->dma_init; - - // Set DMA_REQ_MUX_REG for the requested channel / trigger combination - if (channel_setup->dma_req_mux != HW_DMA_TRIG_NONE) - { - switch (channel_setup->channel_number) - { - case HW_DMA_CHANNEL_0: - case HW_DMA_CHANNEL_1: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - - case HW_DMA_CHANNEL_2: - case HW_DMA_CHANNEL_3: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - - case HW_DMA_CHANNEL_4: - case HW_DMA_CHANNEL_5: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - - case HW_DMA_CHANNEL_6: - case HW_DMA_CHANNEL_7: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA67_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - - default: - break; - } + // Set DMAx_CTRL_REG width provided settings, but do not start the channel. + // Start the channel with the "dma_channel_enable" function separately. + *dma_x_ctrl_reg = + channel_setup->bus_width | + channel_setup->irq_enable | + channel_setup->dreq_mode | + channel_setup->b_inc | + channel_setup->a_inc | + channel_setup->circular | + channel_setup->dma_prio | + channel_setup->dma_idle | + channel_setup->dma_init; + // Set DMA_REQ_MUX_REG for the requested channel / trigger combination + if (channel_setup->dma_req_mux != HW_DMA_TRIG_NONE) { + switch (channel_setup->channel_number) { + case HW_DMA_CHANNEL_0: + case HW_DMA_CHANNEL_1: + GLOBAL_INT_DISABLE(); + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); + break; + case HW_DMA_CHANNEL_2: + case HW_DMA_CHANNEL_3: + GLOBAL_INT_DISABLE(); + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); + break; + case HW_DMA_CHANNEL_4: + case HW_DMA_CHANNEL_5: + GLOBAL_INT_DISABLE(); + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); + break; + case HW_DMA_CHANNEL_6: + case HW_DMA_CHANNEL_7: + GLOBAL_INT_DISABLE(); + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA67_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); + break; + default: + break; + } #if dg_configDMA_DYNAMIC_MUX || (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - /* - * When different DMA channels are used for same device it is important - * that only one trigger is set for specific device at a time. - * Having same trigger for different channels can cause unpredictable results. - * Following code also should help when SPI1 is assigned to non 0 channel. - */ - GLOBAL_INT_DISABLE(); - - switch (channel_setup->channel_number) - { - case HW_DMA_CHANNEL_6: - case HW_DMA_CHANNEL_7: - if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL) == channel_setup->dma_req_mux) - { - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, HW_DMA_TRIG_NONE); - } - - /* no break */ - case HW_DMA_CHANNEL_4: - case HW_DMA_CHANNEL_5: - if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL) == channel_setup->dma_req_mux) - { - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, HW_DMA_TRIG_NONE); - } - - /* no break */ - case HW_DMA_CHANNEL_2: - case HW_DMA_CHANNEL_3: - if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL) == channel_setup->dma_req_mux) - { - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, HW_DMA_TRIG_NONE); - } - - break; - - case HW_DMA_CHANNEL_0: - case HW_DMA_CHANNEL_1: - default: - break; - } - - GLOBAL_INT_RESTORE(); + /* + * When different DMA channels are used for same device it is important + * that only one trigger is set for specific device at a time. + * Having same trigger for different channels can cause unpredictable results. + * Following code also should help when SPI1 is assigned to non 0 channel. + */ + GLOBAL_INT_DISABLE(); + switch (channel_setup->channel_number) { + case HW_DMA_CHANNEL_6: + case HW_DMA_CHANNEL_7: + if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL) == channel_setup->dma_req_mux) { + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, HW_DMA_TRIG_NONE); + } + /* no break */ + case HW_DMA_CHANNEL_4: + case HW_DMA_CHANNEL_5: + if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL) == channel_setup->dma_req_mux) { + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, HW_DMA_TRIG_NONE); + } + /* no break */ + case HW_DMA_CHANNEL_2: + case HW_DMA_CHANNEL_3: + if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL) == channel_setup->dma_req_mux) { + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, HW_DMA_TRIG_NONE); + } + break; + case HW_DMA_CHANNEL_0: + case HW_DMA_CHANNEL_1: + default: + break; + } + GLOBAL_INT_RESTORE(); #endif - } + } #if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) - - //Set REQ_SENSE bit of i2c and Uart peripherals TX path - if (((channel_setup->dma_req_mux == HW_DMA_TRIG_UART_RXTX) || - (channel_setup->dma_req_mux == HW_DMA_TRIG_UART2_RXTX) || - (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C_RXTX) || - (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C2_RXTX)) && - (channel_setup->channel_number & 1)) //odd channels used for TX - { - REG_SET_FIELD(DMA, DMA0_CTRL_REG, REQ_SENSE, *dma_x_ctrl_reg, 1); - } - + //Set REQ_SENSE bit of i2c, USB and Uart peripherals TX path + if (((channel_setup->dma_req_mux == HW_DMA_TRIG_UART_RXTX) || + (channel_setup->dma_req_mux == HW_DMA_TRIG_UART2_RXTX) || + (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C_RXTX) || + (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C2_RXTX) || + (channel_setup->dma_req_mux == HW_DMA_TRIG_USB_RXTX)) && + (channel_setup->channel_number & 1)) {//odd channels used for TX + REG_SET_FIELD(DMA, DMA0_CTRL_REG, REQ_SENSE, *dma_x_ctrl_reg, 1); + } #endif - src_address = DA15000_phy_addr(channel_setup->src_address); - dest_address = DA15000_phy_addr(channel_setup->dest_address); + src_address = DA15000_phy_addr(channel_setup->src_address); + dest_address = DA15000_phy_addr(channel_setup->dest_address); - // Set source address registers - *dma_x_a_start_low_reg = (src_address & 0xffff); - *dma_x_a_start_high_reg = (src_address >> 16); + // Set source address registers + *dma_x_a_start_low_reg = (src_address & 0xffff); + *dma_x_a_start_high_reg = (src_address >> 16); - // Set destination address registers - *dma_x_b_start_low_reg = (dest_address & 0xffff); - *dma_x_b_start_high_reg = (dest_address >> 16); + // Set destination address registers + *dma_x_b_start_low_reg = (dest_address & 0xffff); + *dma_x_b_start_high_reg = (dest_address >> 16); - // Set IRQ number of transfers - if (channel_setup->irq_nr_of_trans > 0) - { - // If user explicitly set this number use it - *dma_x_int_reg = channel_setup->irq_nr_of_trans - 1; - } - else - { - // If user passed 0, use transfer length to fire interrupt after transfer ends - *dma_x_int_reg = channel_setup->length - 1; - } + // Set IRQ number of transfers + if (channel_setup->irq_nr_of_trans > 0) { + // If user explicitly set this number use it + *dma_x_int_reg = channel_setup->irq_nr_of_trans - 1; + } else { + // If user passed 0, use transfer length to fire interrupt after transfer ends + *dma_x_int_reg = channel_setup->length - 1; + } - // Set the transfer length - *dma_x_len_reg = (channel_setup->length) - 1; + // Set the transfer length + *dma_x_len_reg = (channel_setup->length) - 1; - if (channel_setup->irq_enable) - { - dma_callbacks_user_data[channel_setup->channel_number].callback = channel_setup->callback; - } - else - { - dma_callbacks_user_data[channel_setup->channel_number].callback = NULL; - } - - dma_callbacks_user_data[channel_setup->channel_number].user_data = channel_setup->user_data; + if (channel_setup->irq_enable) + dma_callbacks_user_data[channel_setup->channel_number].callback = channel_setup->callback; + else + dma_callbacks_user_data[channel_setup->channel_number].callback = NULL; + dma_callbacks_user_data[channel_setup->channel_number].user_data = channel_setup->user_data; } void hw_dma_channel_update_source(HW_DMA_CHANNEL channel, void *addr, uint16_t length, - hw_dma_transfer_cb cb) + hw_dma_transfer_cb cb) { - uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr); + uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr); - dma_callbacks_user_data[channel].callback = cb; + dma_callbacks_user_data[channel].callback = cb; - // Look up DMAx_A_STARTL_REG address - volatile uint16 *dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel); + // Look up DMAx_A_STARTL_REG address + volatile uint16 *dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel); - // Look up DMAx_A_STARTH_REG address - volatile uint16 *dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel); + // Look up DMAx_A_STARTH_REG address + volatile uint16 *dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel); - // Look up DMAX_LEN_REG address - volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); + // Look up DMAX_LEN_REG address + volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); - volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); + volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); - // Set source address registers - *dma_x_a_start_low_reg = (phy_addr & 0xffff); - *dma_x_a_start_high_reg = (phy_addr >> 16); + // Set source address registers + *dma_x_a_start_low_reg = (phy_addr & 0xffff); + *dma_x_a_start_high_reg = (phy_addr >> 16); - *dma_x_int_reg = length - 1; + *dma_x_int_reg = length - 1; - // Set the transfer length - *dma_x_len_reg = length - 1; + // Set the transfer length + *dma_x_len_reg = length - 1; } void hw_dma_channel_update_destination(HW_DMA_CHANNEL channel, void *addr, uint16_t length, - hw_dma_transfer_cb cb) + hw_dma_transfer_cb cb) { - uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr); + uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr); - dma_callbacks_user_data[channel].callback = cb; + dma_callbacks_user_data[channel].callback = cb; - // Look up DMAx_B_STARTL_REG address - volatile uint16 *dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel); + // Look up DMAx_B_STARTL_REG address + volatile uint16 *dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel); - // Look up DMAx_B_STARTH_REG address - volatile uint16 *dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel); + // Look up DMAx_B_STARTH_REG address + volatile uint16 *dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel); - // Look up DMAX_LEN_REG address - volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); - volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); + // Look up DMAX_LEN_REG address + volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); + volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); - // Set destination address registers - *dma_x_b_start_low_reg = (phy_addr & 0xffff); - *dma_x_b_start_high_reg = (phy_addr >> 16); + // Set destination address registers + *dma_x_b_start_low_reg = (phy_addr & 0xffff); + *dma_x_b_start_high_reg = (phy_addr >> 16); - *dma_x_int_reg = length - 1; + *dma_x_int_reg = length - 1; - // Set the transfer length - *dma_x_len_reg = length - 1; + // Set the transfer length + *dma_x_len_reg = length - 1; } void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix) { - volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); + volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); - *dma_x_int_reg = int_ix; + *dma_x_int_reg = int_ix; } /** @@ -326,70 +298,59 @@ void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix) */ void hw_dma_channel_enable(HW_DMA_CHANNEL channel_number, HW_DMA_STATE dma_on) { - volatile uint16 *dma_x_ctrl_reg; + volatile uint16 *dma_x_ctrl_reg; - // Look up DMAx_CTRL_REG address - dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_number); + // Look up DMAx_CTRL_REG address + dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_number); - if (dma_on == HW_DMA_STATE_ENABLED) - { - uint16_t dma_ctrl = *dma_x_ctrl_reg; + if (dma_on == HW_DMA_STATE_ENABLED) { + uint16_t dma_ctrl = *dma_x_ctrl_reg; - REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, dma_ctrl, 1); - - if (dma_callbacks_user_data[channel_number].callback) - { - REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, dma_ctrl, 1); + REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, dma_ctrl, 1); + if (dma_callbacks_user_data[channel_number].callback) { + REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, dma_ctrl, 1); + } + // Start the chosen DMA channel + *dma_x_ctrl_reg = dma_ctrl; + NVIC_EnableIRQ(DMA_IRQn); + } else { + // Stop the chosen DMA channel + REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, 0); + REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, *dma_x_ctrl_reg, 0); } - - // Start the chosen DMA channel - *dma_x_ctrl_reg = dma_ctrl; - NVIC_EnableIRQ(DMA_IRQn); - } - else - { - // Stop the chosen DMA channel - REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, 0); - REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, *dma_x_ctrl_reg, 0); - } } static inline void dma_helper(HW_DMA_CHANNEL channel_number, uint16_t len, bool stop_dma) { - hw_dma_transfer_cb cb; + hw_dma_transfer_cb cb; - NVIC_DisableIRQ(DMA_IRQn); - cb = dma_callbacks_user_data[channel_number].callback; - - if (stop_dma) - { - dma_callbacks_user_data[channel_number].callback = NULL; - hw_dma_channel_enable(channel_number, HW_DMA_STATE_DISABLED); - } - - if (cb) - { - cb(dma_callbacks_user_data[channel_number].user_data, len); - } - - NVIC_EnableIRQ(DMA_IRQn); + NVIC_DisableIRQ(DMA_IRQn); + cb = dma_callbacks_user_data[channel_number].callback; + if (stop_dma) { + dma_callbacks_user_data[channel_number].callback = NULL; + hw_dma_channel_enable(channel_number, HW_DMA_STATE_DISABLED); + } + if (cb) { + cb(dma_callbacks_user_data[channel_number].user_data, len); + } + NVIC_EnableIRQ(DMA_IRQn); } bool hw_dma_channel_active(void) { - int dma_on; + int dma_on; - dma_on = REG_GETF(DMA, DMA0_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA1_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA2_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA3_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA4_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA5_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA6_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA7_CTRL_REG, DMA_ON); + dma_on = REG_GETF(DMA, DMA0_CTRL_REG, DMA_ON); + dma_on |= REG_GETF(DMA, DMA1_CTRL_REG, DMA_ON); + dma_on |= REG_GETF(DMA, DMA2_CTRL_REG, DMA_ON); + dma_on |= REG_GETF(DMA, DMA3_CTRL_REG, DMA_ON); + dma_on |= REG_GETF(DMA, DMA4_CTRL_REG, DMA_ON); + dma_on |= REG_GETF(DMA, DMA5_CTRL_REG, DMA_ON); + dma_on |= REG_GETF(DMA, DMA6_CTRL_REG, DMA_ON); + dma_on |= REG_GETF(DMA, DMA7_CTRL_REG, DMA_ON); - return (dma_on == 1); + return (dma_on == 1); } /** @@ -400,62 +361,60 @@ bool hw_dma_channel_active(void) */ void DMA_Handler(void) { - SEGGER_SYSTEMVIEW_ISR_ENTER(); + SEGGER_SYSTEMVIEW_ISR_ENTER(); - uint16_t risen; - uint16_t i; - volatile uint16 *dma_x_len_reg; - volatile uint16 *dma_x_int_reg; - volatile uint16 *dma_x_ctrl_reg; + uint16_t risen; + uint16_t i; + volatile uint16 *dma_x_len_reg; + volatile uint16 *dma_x_int_reg; + volatile uint16 *dma_x_ctrl_reg; - risen = DMA->DMA_INT_STATUS_REG; + risen = DMA->DMA_INT_STATUS_REG; - for (i = 0; risen != 0 && i < 8; ++i, risen >>= 1) - { - if (risen & 1) - { - bool stop; + for (i = 0; risen != 0 && i < 8; ++i, risen >>= 1) { + if (risen & 1) { + bool stop; - /* - * DMAx_INT_REG shows after how many transfers the interrupt - * is generated - */ - dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, i); + /* + * DMAx_INT_REG shows after how many transfers the interrupt + * is generated + */ + dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, i); - /* - * DMAx_LEN_REG shows the length of the DMA transfer - */ - dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, i); + /* + * DMAx_LEN_REG shows the length of the DMA transfer + */ + dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, i); - dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, i); + dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, i); - /* - * Stop DMA if: - * - transfer is completed - * - mode is not circular - */ - stop = (*dma_x_int_reg == *dma_x_len_reg) - && (!REG_GET_FIELD(DMA, DMA0_CTRL_REG, CIRCULAR, *dma_x_ctrl_reg)); - DMA->DMA_CLEAR_INT_REG = 1 << i; - dma_helper(i, *dma_x_int_reg + 1, stop); + /* + * Stop DMA if: + * - transfer is completed + * - mode is not circular + */ + stop = (*dma_x_int_reg == *dma_x_len_reg) + && (!REG_GET_FIELD(DMA, DMA0_CTRL_REG, CIRCULAR, *dma_x_ctrl_reg)); + DMA->DMA_CLEAR_INT_REG = 1 << i; + dma_helper(i, *dma_x_int_reg + 1, stop); + } } - } - SEGGER_SYSTEMVIEW_ISR_EXIT(); + SEGGER_SYSTEMVIEW_ISR_EXIT(); } void hw_dma_channel_stop(HW_DMA_CHANNEL channel_number) { - // Stopping DMA will clear DMAx_IDX_REG so read it before - volatile uint16 *dma_x_idx_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); - dma_helper(channel_number, *dma_x_idx_reg, true); + // Stopping DMA will clear DMAx_IDX_REG so read it before + volatile uint16 *dma_x_idx_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); + dma_helper(channel_number, *dma_x_idx_reg, true); } uint16_t hw_dma_transfered_bytes(HW_DMA_CHANNEL channel_number) { - volatile uint16 *dma_x_int_reg = dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); + volatile uint16 *dma_x_int_reg = dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); - return *dma_x_int_reg; + return *dma_x_int_reg; } #endif /* dg_configUSE_HW_DMA */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c deleted file mode 100644 index 1a606356c..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c +++ /dev/null @@ -1,680 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup FEM - * \{ - */ - -/** - ***************************************************************************************** - * - * @file - * - * @brief FEM Driver for SKYWORKS SKY66112-11 Radio module - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#if dg_configFEM == FEM_SKY66112_11 -#include "stdint.h" - -#include "sdk_defs.h" -#include "hw_gpio.h" -#include "hw_fem_sky66112-11.h" - -static hw_fem_config fem_config __RETAINED; - -#if !defined(dg_configFEM_SKY66112_11_CTX_PORT) || !defined(dg_configFEM_SKY66112_11_CTX_PIN) -#error FEM CTX GPIO must be defined!! -#endif - -#if !defined(dg_configFEM_SKY66112_11_CRX_PORT) || !defined(dg_configFEM_SKY66112_11_CRX_PIN) -#error FEM CRX GPIO must be defined!! -#endif - - -int hw_fem_set_bias(uint16_t voltage) -{ - uint16_t value; - - if (voltage < 1200 || voltage > 1975) - { - return -1; - } - - value = (voltage - 1200) / 27.5; - -#ifdef dg_configFEM_SKY66112_11_FEM_BIAS_V18P - REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, value); - return 0; -#elif defined(dg_configFEM_SKY66112_11_FEM_BIAS_V18) - REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, value); - return 0; -#else - return -2; -#endif - -} - -int hw_fem_set_bias2(uint16_t voltage) -{ - uint16_t value; - - if (voltage < 1200 || voltage > 1975) - { - return -1; - } - - value = (voltage - 1200) / 27.5; - -// /* Value is actually one lower than computed */ -// if (value > 0) -// value--; - -#ifdef dg_configFEM_SKY66112_11_FEM_BIAS2_V18P - REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, value); -#elif defined(dg_configFEM_SKY66112_11_FEM_BIAS2_V18) - REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, value); -#else - return -2; -#endif - return 0; -} - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -void hw_fem_set_txpower(bool high) -{ -#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN) - GLOBAL_INT_DISABLE(); - fem_config.tx_power = high; - - if (fem_config.started) - { - if (high == false) - { - /* TX Power low. Stop DCF, set GPIO to low */ - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT, - dg_configFEM_SKY66112_11_CHL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); - REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG, - RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Msk | - RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk, 0); - - } - else - { - /* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */ - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT, - dg_configFEM_SKY66112_11_CHL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF); - REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG, - RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Msk | - RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk, - RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk); - - } - } - - GLOBAL_INT_RESTORE(); -#endif -} - -static void set_bypass(void) -{ - uint16_t m = 0; - - if (fem_config.tx_bypass) - { - m = RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Msk; - } - - if (fem_config.rx_bypass) - { - m |= RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Msk; - } - - REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG, - RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Msk | - RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Msk, m); - - if (m == 0) - { - /* No RX/TX bypass. Drive the interface line to low */ - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT, - dg_configFEM_SKY66112_11_CPS_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); - } - else - { - /* At least one of TX/RX needs bypass */ - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CPS_PORT, - dg_configFEM_SKY66112_11_CPS_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT3_DCF); - } -} - - -void hw_fem_set_tx_bypass(bool enable) -{ -#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) - GLOBAL_INT_DISABLE(); - fem_config.tx_bypass = enable; - - if (fem_config.started) - { - set_bypass(); - } - - GLOBAL_INT_RESTORE(); -#endif -} - -void hw_fem_set_rx_bypass(bool enable) -{ -#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) - GLOBAL_INT_DISABLE(); - fem_config.rx_bypass = enable; - - if (fem_config.started) - { - set_bypass(); - } - - GLOBAL_INT_RESTORE(); -#endif -} - -bool hw_fem_get_txpower(void) -{ - return fem_config.tx_power; -} - -bool hw_fem_get_tx_bypass(void) -{ - return fem_config.tx_bypass; -} - -bool hw_fem_get_rx_bypass(void) -{ - return fem_config.rx_bypass; -} - -#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ - -#ifdef CONFIG_USE_BLE -bool hw_fem_get_txpower_ble(void) -{ - return fem_config.tx_power_ble; -} - -bool hw_fem_get_tx_bypass_ble(void) -{ - return fem_config.tx_bypass_ble; -} - -bool hw_fem_get_rx_bypass_ble(void) -{ - return fem_config.rx_bypass_ble; -} -#endif /* CONFIG_USE_BLE */ - -#ifdef CONFIG_USE_FTDF -bool hw_fem_get_txpower_ftdf(void) -{ - return fem_config.tx_power_ftdf; -} - -bool hw_fem_get_tx_bypass_ftdf(void) -{ - return fem_config.tx_bypass_ftdf; -} - -bool hw_fem_get_rx_bypass_ftdf(void) -{ - return fem_config.rx_bypass_ftdf; -} -#endif /* CONFIG_USE_FTDF */ - -bool hw_fem_get_txpower(void) -{ - return fem_config.tx_power_ble; -} - -bool hw_fem_get_tx_bypass(void) -{ - return fem_config.tx_bypass_ble; -} - -bool hw_fem_get_rx_bypass(void) -{ - return fem_config.rx_bypass_ble; -} - -static void set_txpower(void) -{ - if (!fem_config.started) - { - return; - } - - /* CHL is always 0 on RX */ - REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_RX); - REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_RX); - - if (fem_config.tx_power_ble) - { - REG_SET_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_TX); - } - - if (fem_config.tx_power_ftdf) - { - REG_SET_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_TX); - } - - if (fem_config.tx_power_ble || fem_config.tx_power_ftdf) - { - /* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */ - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT, - dg_configFEM_SKY66112_11_CHL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF); - } - else - { - /* TX Power low. Stop DCF, set GPIO to low */ - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT, - dg_configFEM_SKY66112_11_CHL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); - } -} - - -void hw_fem_set_txpower_ble(bool high) -{ -#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN) - GLOBAL_INT_DISABLE(); - fem_config.tx_power_ble = high; - set_txpower(); - GLOBAL_INT_RESTORE(); -#endif -} - -void hw_fem_set_txpower_ftdf(bool high) -{ -#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN) - GLOBAL_INT_DISABLE(); - fem_config.tx_power_ftdf = high; - set_txpower(); - GLOBAL_INT_RESTORE(); -#endif -} - -void hw_fem_set_txpower(bool high) -{ - hw_fem_set_txpower_ble(high); -} - - - -static void set_bypass(void) -{ - uint16_t m_ble = 0; - uint16_t m_ftdf = 0; - - if (fem_config.tx_bypass_ble) - { - m_ble = RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk; - } - - if (fem_config.rx_bypass_ble) - { - m_ble |= RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk; - } - - if (fem_config.tx_bypass_ftdf) - { - m_ftdf = RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk; - } - - if (fem_config.rx_bypass_ftdf) - { - m_ftdf |= RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk; - } - - REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_BLE_REG, - RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk | - RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk, m_ble); - REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_FTDF_REG, - RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk | - RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk, m_ftdf); - - if (m_ble == 0 && m_ftdf == 0) - { - /* No RX/TX bypass. Drive the interface line to low */ - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT, - dg_configFEM_SKY66112_11_CPS_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); - } - else - { - /* At least one of TX/RX needs bypass */ - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CPS_PORT, - dg_configFEM_SKY66112_11_CPS_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT3_DCF); - } -} - -#ifdef CONFIG_USE_BLE -void hw_fem_set_tx_bypass_ble(bool enable) -{ -#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) - GLOBAL_INT_DISABLE(); - fem_config.tx_bypass_ble = enable; - - if (fem_config.started) - { - set_bypass(); - } - - GLOBAL_INT_RESTORE(); -#endif -} - -void hw_fem_set_rx_bypass_ble(bool enable) -{ -#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) - GLOBAL_INT_DISABLE(); - fem_config.rx_bypass_ble = enable; - - if (fem_config.started) - { - set_bypass(); - } - - GLOBAL_INT_RESTORE(); -#endif -} -#endif /* CONFIG_USE_BLE */ - -#ifdef CONFIG_USE_FTDF -void hw_fem_set_tx_bypass_ftdf(bool enable) -{ -#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) - GLOBAL_INT_DISABLE(); - fem_config.tx_bypass_ftdf = enable; - - if (fem_config.started) - { - set_bypass(); - } - - GLOBAL_INT_RESTORE(); -#endif -} - -void hw_fem_set_rx_bypass_ftdf(bool enable) -{ -#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) - GLOBAL_INT_DISABLE(); - fem_config.rx_bypass_ftdf = enable; - - if (fem_config.started) - { - set_bypass(); - } - - GLOBAL_INT_RESTORE(); -#endif -} -#endif /* CONFIG_USE_FTDF */ - -void hw_fem_set_tx_bypass(bool enable) -{ - hw_fem_set_tx_bypass_ftdf(enable); -} - -void hw_fem_set_rx_bypass(bool enable) -{ - hw_fem_set_rx_bypass_ftdf(enable); -} -#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ - -void hw_fem_set_antenna(bool one) -{ -#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN) - GLOBAL_INT_DISABLE(); - fem_config.antsel = one; - - if (fem_config.started) - { - /* Antenna selection */ - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT, - dg_configFEM_SKY66112_11_ANTSEL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, fem_config.antsel); - } - - GLOBAL_INT_RESTORE(); -#endif -} - -bool hw_fem_get_antenna(void) -{ - return fem_config.antsel; -} - -void hw_fem_start(void) -{ - GLOBAL_INT_DISABLE(); - fem_config.started = true; - - uint8_t set_delay; - uint8_t reset_delay; - uint16_t rf_port_en; - - /****************************************************** - * Setup GPIOs - */ - - /* CSD GPIO Config */ -#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN) -# if dg_configFEM_SKY66112_11_CSD_USE_DCF == 0 - /* Manually set CSD (Enable FEM) */ - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); -# else - /* Use DCF for CSD */ - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT2_DCF); -# endif -#endif - - /* Timer 27 GPIO (DCF Port 0). Used for TX EN */ - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CTX_PORT, dg_configFEM_SKY66112_11_CTX_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT0_DCF); - - /* Timer 28 (DCF Port 1). Used for RX EN */ - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CRX_PORT, dg_configFEM_SKY66112_11_CRX_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT1_DCF); - - /* Antenna selection */ -#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT, dg_configFEM_SKY66112_11_ANTSEL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, fem_config.antsel); -#endif - - /****************************************************** - * Setup RF_ANT_TRIM GPIOs - */ - - /* RF_ANT_TRIM_0 Config */ -#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN) - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM0); -#endif - - /* RF_ANT_TRIM_1 Config */ -#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN) - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM1); -#endif - - /* RF_ANT_TRIM_2 Config */ -#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN) - hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM2); -#endif - - /****************************************************** - * Setup DCFs - */ - - /* assign values to the timer registers for CTX/CRX (in usec) */ - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF); - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF); - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, SET_OFFSET, dg_configFEM_SKY66112_11_RXSET_DCF); - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_RXRESET_DCF); - - rf_port_en = 0x6; /* Start with Port 0: TX, Port 1: RX */ - - /* Compute set/reset delays to use for CSD, CPS, CHL DCFs: For setting delay, - * smaller of TXSET, RXSET, and for resetting delay, larger of TXSET, RXSET - */ -#if dg_configFEM_SKY66112_11_RXSET_DCF > dg_configFEM_SKY66112_11_TXSET_DCF - set_delay = dg_configFEM_SKY66112_11_TXSET_DCF; -#else - set_delay = dg_configFEM_SKY66112_11_RXSET_DCF; -#endif - -#if dg_configFEM_SKY66112_11_RXRESET_DCF > dg_configFEM_SKY66112_11_TXRESET_DCF - reset_delay = dg_configFEM_SKY66112_11_RXRESET_DCF; -#else - reset_delay = dg_configFEM_SKY66112_11_TXRESET_DCF; -#endif - - /* CSD DCF (if enabled) configuration */ -#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN) -# if dg_configFEM_SKY66112_11_CSD_USE_DCF != 0 - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, SET_OFFSET, set_delay); - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, RESET_OFFSET, reset_delay); - - /* enable DCF Signals for Port 2 (CSD) for both rx/tx */ - rf_port_en |= 0x30; - -# endif /* dg_configFEM_SKY66112_11_CSD_USE_DCF != 0 */ -#endif - - /* Set bypass (CPS) DCF timers (but don't enable yet) */ - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, SET_OFFSET, set_delay); - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, RESET_OFFSET, reset_delay); - - /* Set TX Power (CHL) DCF timers (but don't enable yet) */ - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF); - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF); - - /* Enable DCFs */ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - RFCU_POWER->RF_PORT_EN_REG = rf_port_en; - hw_fem_set_txpower(fem_config.tx_power); -#else - RFCU_POWER->RF_PORT_EN_BLE_REG = rf_port_en; - RFCU_POWER->RF_PORT_EN_FTDF_REG = rf_port_en; - - set_txpower(); -#endif - set_bypass(); - - GLOBAL_INT_RESTORE(); -} - -void hw_fem_stop(void) -{ - GLOBAL_INT_DISABLE(); - fem_config.started = false; - - /* Stop DCF Timers */ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - RFCU_POWER->RF_PORT_EN_REG = 0x0; -#else - RFCU_POWER->RF_PORT_EN_BLE_REG = 0x0; - RFCU_POWER->RF_PORT_EN_FTDF_REG = 0x0; -#endif - - /* Set all FEM interface outputs to GPIO mode, and value 0, in order to get the minimum - * possible power consumption from FEM - */ -#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); -#endif - - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CTX_PORT, dg_configFEM_SKY66112_11_CTX_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); - -#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT, dg_configFEM_SKY66112_11_CHL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); -#endif - - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CRX_PORT, dg_configFEM_SKY66112_11_CRX_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); - -#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT, dg_configFEM_SKY66112_11_CPS_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); -#endif - -#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT, dg_configFEM_SKY66112_11_ANTSEL_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); -#endif - -#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); -#endif - -#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); -#endif - -#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN) - hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); -#endif - - GLOBAL_INT_RESTORE(); -} -#endif /* dg_configFEM == FEM_SKY66112_11 */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c index 3304c3d40..299d4fe53 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c @@ -14,12 +14,30 @@ * * @brief Implementation of the GPADC Low Level Driver. * - * Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer - * program includes Confidential, Proprietary Information and is a Trade Secret of - * Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited - * unless authorized in writing. All Rights Reserved. + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. * - * and contributors. * **************************************************************************************** */ @@ -238,33 +256,41 @@ void hw_gpadc_test_measurements(void) uint16_t hw_gpadc_get_raw_value(void) { - int32_t adc_raw_res = GPADC->GP_ADC_RESULT_REG; - int16_t gain_error = 0; - uint16_t offset_trim = 0; + uint16_t adc_raw_res = GPADC->GP_ADC_RESULT_REG; + int32_t res = adc_raw_res; if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) { if (hw_gpadc_pre_check_for_gain_error()) { + int16_t gain_trim; const HW_GPADC_INPUT_MODE input_mode = hw_gpadc_get_input_mode(); - if (input_mode == HW_GPADC_INPUT_MODE_DIFFERENTIAL) { - gain_error = hw_gpadc_differential_gain_error; - offset_trim = 0x8000; - } else if (input_mode == HW_GPADC_INPUT_MODE_SINGLE_ENDED) { - gain_error = hw_gpadc_single_ended_gain_error; - offset_trim = 0; - } - adc_raw_res = adc_raw_res - - ((adc_raw_res - offset_trim ) * gain_error ) / 0x10000; - /* Adjust value for edge cases */ - if (adc_raw_res & 0x80000000) { /* negative overflow */ - return 0; - } - if (adc_raw_res & 0x7FFF0000) { /* positive overflow */ - return UINT16_MAX; + + if (input_mode == HW_GPADC_INPUT_MODE_SINGLE_ENDED) { + gain_trim = hw_gpadc_single_ended_gain_error; + /* Gain correction */ + res = 0xFFFFU * adc_raw_res / (0xFFFFU + gain_trim); + /* Boundary check */ + if ((uint32_t)res > UINT16_MAX) { + return UINT16_MAX; + } + } else if (input_mode == HW_GPADC_INPUT_MODE_DIFFERENTIAL) { + gain_trim = hw_gpadc_differential_gain_error; + res = (int16_t)(adc_raw_res ^ 0x8000); + /* Gain correction */ + res = 0xFFFF * res / (0xFFFF + gain_trim); + /* Boundary check for lower limit */ + if (res < INT16_MIN) { + return 0; /* INT16_MIN ^ 0x8000 */ + } + /* Boundary check for upper limit */ + if (res > INT16_MAX) { + return UINT16_MAX; /* INT16_MAX ^ 0x8000 */ + } + res ^= 0x8000; } } } - return adc_raw_res; + return res; } #endif /* dg_configUSE_HW_GPADC */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c index 9bbde9fc7..ca5ab57db 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c @@ -67,17 +67,15 @@ static uint16_t Px_DATA_REG_cache[5]; #endif #if (dg_configIMAGE_SETUP == PRODUCTION_MODE) && (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) -#warning "GPIO assignment monitoring is active in PRODUCTION build!" + #warning "GPIO assignment monitoring is active in PRODUCTION build!" #endif static volatile uint8_t GPIO_status[HW_GPIO_NUM_PORTS] = { 0 }; -const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS] = -{ - HW_GPIO_PORT_0_NUM_PINS, HW_GPIO_PORT_1_NUM_PINS, - HW_GPIO_PORT_2_NUM_PINS, HW_GPIO_PORT_3_NUM_PINS, - HW_GPIO_PORT_4_NUM_PINS -}; +const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS] = { + HW_GPIO_PORT_0_NUM_PINS, HW_GPIO_PORT_1_NUM_PINS, + HW_GPIO_PORT_2_NUM_PINS, HW_GPIO_PORT_3_NUM_PINS, + HW_GPIO_PORT_4_NUM_PINS }; /* * Global Functions @@ -87,252 +85,213 @@ const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS] = void hw_gpio_configure(const gpio_config cfg[]) { #if dg_configIMAGE_SETUP == DEVELOPMENT_MODE - int num_pins = 0; - uint8_t set_mask[HW_GPIO_NUM_PORTS]; + int num_pins = 0; + uint8_t set_mask[HW_GPIO_NUM_PORTS] = { 0 }; #endif - if (!cfg) - { - return; - } + if (!cfg) { + return; + } - while (cfg->pin != 0xFF) - { - uint8_t port = cfg->pin >> 4; - uint8_t pin = cfg->pin & 0x0F; + while (cfg->pin != 0xFF) { + uint8_t port = cfg->pin >> 4; + uint8_t pin = cfg->pin & 0x0F; #if dg_configIMAGE_SETUP == DEVELOPMENT_MODE + if (port >= HW_GPIO_NUM_PORTS || pin >= hw_gpio_port_num_pins[port]) { + /* + * invalid port or pin number specified, it was either incorrectly specified + * of cfg was not terminated properly using HW_GPIO_PINCONFIG_END so we're + * reading garbage + */ + __BKPT(0); + } - if (port >= HW_GPIO_NUM_PORTS || pin >= hw_gpio_port_num_pins[port]) - { - /* - * invalid port or pin number specified, it was either incorrectly specified - * of cfg was not terminated properly using HW_GPIO_PINCONFIG_END so we're - * reading garbage - */ - __BKPT(0); - } + if (++num_pins > HW_GPIO_NUM_PINS) { + /* + * trying to set more pins than available, perhaps cfg was not terminated + * properly using HW_GPIO_PINCONFIG_END? + */ + __BKPT(0); + } - if (++num_pins > HW_GPIO_NUM_PINS) - { - /* - * trying to set more pins than available, perhaps cfg was not terminated - * properly using HW_GPIO_PINCONFIG_END? - */ - __BKPT(0); - } + if (set_mask[port] & (1 << pin)) { + /* + * trying to set pin which has been already set by this call which means + * there is duplicated pin in configuration - does not make sense + */ + __BKPT(0); + } - if (set_mask[port] & (1 << pin)) - { - /* - * trying to set pin which has been already set by this call which means - * there is duplicated pin in configuration - does not make sense - */ - __BKPT(0); - } - - set_mask[port] |= (1 << pin); + set_mask[port] |= (1 << pin); #endif - if (cfg->reserve) - { - hw_gpio_reserve_and_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high); - } - else - { - hw_gpio_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high); - } + if (cfg->reserve) { + hw_gpio_reserve_and_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high); + } else { + hw_gpio_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high); + } - cfg++; - } + cfg++; + } } bool hw_gpio_reserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin) { - if ((GPIO_status[port] & (1 << pin))) - { - return false; - } + if ((GPIO_status[port] & (1 << pin))) { + return false; + } - GPIO_status[port] |= (1 << pin); + GPIO_status[port] |= (1 << pin); - return true; + return true; } bool hw_gpio_reserve_and_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function, bool high) + HW_GPIO_FUNC function, bool high) { - if (!hw_gpio_reserve_pin(port, pin)) - { - return false; - } + if (!hw_gpio_reserve_pin(port, pin)) { + return false; + } - hw_gpio_configure_pin(port, pin, mode, function, high); + hw_gpio_configure_pin(port, pin, mode, function, high); - return true; + return true; } void hw_gpio_unreserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin) { - GPIO_status[port] &= ~(1 << pin); + GPIO_status[port] &= ~(1 << pin); } static void hw_gpio_verify_reserved(HW_GPIO_PORT port, HW_GPIO_PIN pin) { #if (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) - - if (!(GPIO_status[port] & (1 << pin))) - { - // If debugger stops at this line, there is configuration problem - // pin is used without being reserved first - __BKPT(0); /* this pin has not been previously reserved! */ - } - + if (!(GPIO_status[port] & (1 << pin))) { + // If debugger stops at this line, there is configuration problem + // pin is used without being reserved first + __BKPT(0); /* this pin has not been previously reserved! */ + } #endif // (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) } void hw_gpio_set_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function) + HW_GPIO_FUNC function) { - hw_gpio_verify_reserved(port, pin); + hw_gpio_verify_reserved(port, pin); - PXX_MODE_REG(port, pin) = mode | function; + PXX_MODE_REG(port, pin) = mode | function; } -void hw_gpio_get_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE *mode, - HW_GPIO_FUNC *function) +void hw_gpio_get_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE* mode, + HW_GPIO_FUNC* function) { - uint16_t val; + uint16_t val; - hw_gpio_verify_reserved(port, pin); + hw_gpio_verify_reserved(port, pin); - val = PXX_MODE_REG(port, pin); - *mode = val & 0x0700; - *function = val & 0x00ff; + val = PXX_MODE_REG(port, pin); + *mode = val & 0x0700; + *function = val & 0x00ff; } void hw_gpio_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function, const bool high) + HW_GPIO_FUNC function, const bool high) { - hw_gpio_verify_reserved(port, pin); + hw_gpio_verify_reserved(port, pin); - if (high) - { - hw_gpio_set_active(port, pin); - } - else - { - hw_gpio_set_inactive(port, pin); - } + if (high) + hw_gpio_set_active(port, pin); + else + hw_gpio_set_inactive(port, pin); - hw_gpio_set_pin_function(port, pin, mode, function); + hw_gpio_set_pin_function(port, pin, mode, function); } void hw_gpio_configure_pin_power(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_POWER power) { - uint16_t padpwr; + uint16_t padpwr; - padpwr = PX_PADPWR_CTRL_REG(port); - padpwr &= ~(1 << pin); - - if (power == HW_GPIO_POWER_VDD1V8P) - { - padpwr |= (1 << pin); - } - - PX_PADPWR_CTRL_REG(port) = padpwr; + padpwr = PX_PADPWR_CTRL_REG(port); + padpwr &= ~(1 << pin); + if (power == HW_GPIO_POWER_VDD1V8P) { + padpwr |= (1 << pin); + } + PX_PADPWR_CTRL_REG(port) = padpwr; } void hw_gpio_set_active(HW_GPIO_PORT port, HW_GPIO_PIN pin) { - hw_gpio_verify_reserved(port, pin); + hw_gpio_verify_reserved(port, pin); - PX_SET_DATA_REG(port) = 1 << pin; + PX_SET_DATA_REG(port) = 1 << pin; #ifdef FPGA_PAD_LOOPBACK_BROKEN - Px_DATA_REG_cache[port] |= 1 << pin; + Px_DATA_REG_cache[port] |= 1 << pin; #endif } void hw_gpio_set_inactive(HW_GPIO_PORT port, HW_GPIO_PIN pin) { - hw_gpio_verify_reserved(port, pin); + hw_gpio_verify_reserved(port, pin); - PX_RESET_DATA_REG(port) = 1 << pin; + PX_RESET_DATA_REG(port) = 1 << pin; #ifdef FPGA_PAD_LOOPBACK_BROKEN - Px_DATA_REG_cache[port] &= ~(1 << pin); + Px_DATA_REG_cache[port] &= ~(1 << pin); #endif } bool hw_gpio_get_pin_status(HW_GPIO_PORT port, HW_GPIO_PIN pin) { #ifdef FPGA_PAD_LOOPBACK_BROKEN - HW_GPIO_MODE mode; - HW_GPIO_FUNC function; + HW_GPIO_MODE mode; + HW_GPIO_FUNC function; #endif - hw_gpio_verify_reserved(port, pin); + hw_gpio_verify_reserved(port, pin); #ifdef FPGA_PAD_LOOPBACK_BROKEN - hw_gpio_get_pin_function(port, pin, &mode, &function); - - if (mode != HW_GPIO_MODE_OUTPUT) - { - return !!(PX_DATA_REG(port) & (1 << pin)); - } - else - { - return !!(Px_DATA_REG_cache[port] & (1 << pin)); - } - + hw_gpio_get_pin_function(port, pin, &mode, &function); + if (mode != HW_GPIO_MODE_OUTPUT) + return !!(PX_DATA_REG(port) & (1 << pin)); + else + return !!(Px_DATA_REG_cache[port] & (1 << pin)); #else - return ((PX_DATA_REG(port) & (1 << pin)) != 0); + return ( (PX_DATA_REG(port) & (1 << pin)) != 0 ); #endif } void hw_gpio_toggle(HW_GPIO_PORT port, HW_GPIO_PIN pin) { - hw_gpio_verify_reserved(port, pin); + hw_gpio_verify_reserved(port, pin); - if (hw_gpio_get_pin_status(port, pin)) - { - hw_gpio_set_inactive(port, pin); - } - else - { - hw_gpio_set_active(port, pin); - } + if (hw_gpio_get_pin_status(port, pin)) + hw_gpio_set_inactive(port, pin); + else + hw_gpio_set_active(port, pin); } int hw_gpio_get_pins_with_function(HW_GPIO_FUNC func, uint8_t *buf, int buf_size) { - int count = 0; - int port; - int pin; - HW_GPIO_MODE mode; - HW_GPIO_FUNC pin_func; + int count = 0; + int port; + int pin; + HW_GPIO_MODE mode; + HW_GPIO_FUNC pin_func; - for (port = 0; port < HW_GPIO_NUM_PORTS; ++port) - { - for (pin = 0; pin < hw_gpio_port_num_pins[port]; ++pin) - { - hw_gpio_get_pin_function(port, pin, &mode, &pin_func); - - if (pin_func != func) - { - continue; - } - - if (count < buf_size && buf != NULL) - { - buf[count] = (uint8_t)((port << 4) | pin); - } - - count++; + for (port = 0; port < HW_GPIO_NUM_PORTS; ++port) { + for (pin = 0; pin < hw_gpio_port_num_pins[port]; ++pin) { + hw_gpio_get_pin_function(port, pin, &mode, &pin_func); + if (pin_func != func) { + continue; + } + if (count < buf_size && buf != NULL) { + buf[count] = (uint8_t) ((port << 4) | pin); + } + count++; + } } - } - - return count; + return count; } #endif /* dg_configUSE_HW_GPIO */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c index d40d28b6a..53dd3203c 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c @@ -41,6 +41,7 @@ * **************************************************************************************** */ + #include #include #include "sdk_defs.h" @@ -91,80 +92,77 @@ __attribute__((section("text_retained"))) #endif void HardFault_HandlerC(unsigned long *hardfault_args) { - // Stack frame contains: - // r0, r1, r2, r3, r12, r14, the return address and xPSR - // - Stacked R0 = hf_args[0] - // - Stacked R1 = hf_args[1] - // - Stacked R2 = hf_args[2] - // - Stacked R3 = hf_args[3] - // - Stacked R12 = hf_args[4] - // - Stacked LR = hf_args[5] - // - Stacked PC = hf_args[6] - // - Stacked xPSR= hf_args[7] - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) - { - hw_watchdog_freeze(); // Stop WDOG + // Stack frame contains: + // r0, r1, r2, r3, r12, r14, the return address and xPSR + // - Stacked R0 = hf_args[0] + // - Stacked R1 = hf_args[1] + // - Stacked R2 = hf_args[2] + // - Stacked R3 = hf_args[3] + // - Stacked R12 = hf_args[4] + // - Stacked LR = hf_args[5] + // - Stacked PC = hf_args[6] + // - Stacked xPSR= hf_args[7] + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { + hw_watchdog_freeze(); // Stop WDOG - ENABLE_DEBUGGER; + ENABLE_DEBUGGER; - *(volatile unsigned long *)(STATUS_BASE) = hardfault_args[0]; // R0 - *(volatile unsigned long *)(STATUS_BASE + 0x04) = hardfault_args[1]; // R1 - *(volatile unsigned long *)(STATUS_BASE + 0x08) = hardfault_args[2]; // R2 - *(volatile unsigned long *)(STATUS_BASE + 0x0C) = hardfault_args[3]; // R3 - *(volatile unsigned long *)(STATUS_BASE + 0x10) = hardfault_args[4]; // R12 - *(volatile unsigned long *)(STATUS_BASE + 0x14) = hardfault_args[5]; // LR - *(volatile unsigned long *)(STATUS_BASE + 0x18) = hardfault_args[6]; // PC - *(volatile unsigned long *)(STATUS_BASE + 0x1C) = hardfault_args[7]; // PSR - *(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)hardfault_args; // Stack Pointer + *(volatile unsigned long *)(STATUS_BASE ) = hardfault_args[0]; // R0 + *(volatile unsigned long *)(STATUS_BASE + 0x04) = hardfault_args[1]; // R1 + *(volatile unsigned long *)(STATUS_BASE + 0x08) = hardfault_args[2]; // R2 + *(volatile unsigned long *)(STATUS_BASE + 0x0C) = hardfault_args[3]; // R3 + *(volatile unsigned long *)(STATUS_BASE + 0x10) = hardfault_args[4]; // R12 + *(volatile unsigned long *)(STATUS_BASE + 0x14) = hardfault_args[5]; // LR + *(volatile unsigned long *)(STATUS_BASE + 0x18) = hardfault_args[6]; // PC + *(volatile unsigned long *)(STATUS_BASE + 0x1C) = hardfault_args[7]; // PSR + *(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)hardfault_args; // Stack Pointer - *(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR - *(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR - *(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR - *(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR - *(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR - *(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR + *(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR + *(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR + *(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR + *(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR + *(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR + *(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR - if (VERBOSE_HARDFAULT) - { - printf("HardFault Handler:\r\n"); - printf("- R0 = 0x%08lx\r\n", hardfault_args[0]); - printf("- R1 = 0x%08lx\r\n", hardfault_args[1]); - printf("- R2 = 0x%08lx\r\n", hardfault_args[2]); - printf("- R3 = 0x%08lx\r\n", hardfault_args[3]); - printf("- R12 = 0x%08lx\r\n", hardfault_args[4]); - printf("- LR = 0x%08lx\r\n", hardfault_args[5]); - printf("- PC = 0x%08lx\r\n", hardfault_args[6]); - printf("- xPSR= 0x%08lx\r\n", hardfault_args[7]); + if (VERBOSE_HARDFAULT) { + printf("HardFault Handler:\r\n"); + printf("- R0 = 0x%08lx\r\n", hardfault_args[0]); + printf("- R1 = 0x%08lx\r\n", hardfault_args[1]); + printf("- R2 = 0x%08lx\r\n", hardfault_args[2]); + printf("- R3 = 0x%08lx\r\n", hardfault_args[3]); + printf("- R12 = 0x%08lx\r\n", hardfault_args[4]); + printf("- LR = 0x%08lx\r\n", hardfault_args[5]); + printf("- PC = 0x%08lx\r\n", hardfault_args[6]); + printf("- xPSR= 0x%08lx\r\n", hardfault_args[7]); + } + + hw_cpm_assert_trigger_gpio(); + + while (1); } - - hw_cpm_assert_trigger_gpio(); - - while (1); - } - else - { + else { # ifdef PRODUCTION_DEBUG_OUTPUT # if (USE_WDOG) - WDOG->WATCHDOG_REG = 0xC8; // Reset WDOG! 200 * 10.24ms active time for UART to finish printing! + WDOG->WATCHDOG_REG = 0xC8; // Reset WDOG! 200 * 10.24ms active time for UART to finish printing! # endif - dbg_prod_output(1, hardfault_args); + dbg_prod_output(1, hardfault_args); # endif // PRODUCTION_DEBUG_OUTPUT - hardfault_event_data[0] = HARDFAULT_MAGIC_NUMBER; - hardfault_event_data[1] = hardfault_args[0]; // R0 - hardfault_event_data[2] = hardfault_args[1]; // R1 - hardfault_event_data[3] = hardfault_args[2]; // R2 - hardfault_event_data[4] = hardfault_args[3]; // R3 - hardfault_event_data[5] = hardfault_args[4]; // R12 - hardfault_event_data[6] = hardfault_args[5]; // LR - hardfault_event_data[7] = hardfault_args[6]; // PC - hardfault_event_data[8] = hardfault_args[7]; // PSR + hardfault_event_data[0] = HARDFAULT_MAGIC_NUMBER; + hardfault_event_data[1] = hardfault_args[0]; // R0 + hardfault_event_data[2] = hardfault_args[1]; // R1 + hardfault_event_data[3] = hardfault_args[2]; // R2 + hardfault_event_data[4] = hardfault_args[3]; // R3 + hardfault_event_data[5] = hardfault_args[4]; // R12 + hardfault_event_data[6] = hardfault_args[5]; // LR + hardfault_event_data[7] = hardfault_args[6]; // PC + hardfault_event_data[8] = hardfault_args[7]; // PSR - hw_cpm_reboot_system(); // Force reset + hw_cpm_reboot_system(); // Force reset - while (1); - } + while (1); + } } /** diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c index 14f6e9a7a..f9bc9efd2 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c @@ -89,89 +89,88 @@ * 25ns : 41ns, 200ns : 208ns, 500ns : 521ns, 1us : 1.021ns, 5us : 5us, 2us : 2.021ns, blanc : 125ns * */ -const uint32_t tim1[11] = -{ - /* 1 MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 2MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (9 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 3MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (14 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 4MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (19 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 6MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (29 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 8MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (39 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 12MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (59 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 16MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (79 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (32 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 24MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (119 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (48 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 32MHz */ - (0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (32 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (159 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (64 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 48MHz */ - (1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - (9 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - (24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - (48 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (239 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - (96 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos) +const uint32_t tim1[11] = { + /* 1 MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 2MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 9 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 3MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 14 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 4MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 19 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 6MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 29 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 8MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 39 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 12MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 59 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 16MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + ( 79 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 32 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 24MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + (119 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 48 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 32MHz */ + ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 32 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + (159 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 64 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), + /* 48MHz */ + ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | + ( 9 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | + ( 24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | + ( 48 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | + (239 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | + ( 96 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos) }; static const uint8_t tim2[HW_OTPC_SYS_CLK_FREQ_48 + 1] = -{ 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 5 }; + { 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 5 }; /* @@ -189,8 +188,8 @@ static const uint8_t tim2[HW_OTPC_SYS_CLK_FREQ_48 + 1] = */ __STATIC_INLINE void wait_for_prog_done(void) { - while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PRDY))) - ; + while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PRDY))) + ; } /** @@ -198,8 +197,8 @@ __STATIC_INLINE void wait_for_prog_done(void) */ __STATIC_INLINE void wait_for_auto_done(void) { - while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, ARDY))) - ; + while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, ARDY))) + ; } /** @@ -207,8 +206,8 @@ __STATIC_INLINE void wait_for_auto_done(void) */ __STATIC_INLINE bool have_prog_error(void) { - return OTPC->OTPC_STAT_REG & - (HW_OTPC_FIELD_VAL(STAT, PERR_UNC, 1) | HW_OTPC_FIELD_VAL(STAT, PERR_COR, 1)); + return OTPC->OTPC_STAT_REG & + (HW_OTPC_FIELD_VAL(STAT, PERR_UNC, 1) | HW_OTPC_FIELD_VAL(STAT, PERR_COR, 1)); } /* @@ -250,224 +249,195 @@ __STATIC_INLINE bool have_prog_error(void) __RETAINED_CODE HW_OTPC_SYS_CLK_FREQ hw_otpc_convert_sys_clk_mhz(uint32_t clk_freq) { - HW_OTPC_SYS_CLK_FREQ f; + HW_OTPC_SYS_CLK_FREQ f; - /* Value to convert must be at most 48 MHz */ - ASSERT_WARNING(clk_freq <= 48); + /* Value to convert must be at most 48 MHz */ + ASSERT_WARNING(clk_freq <= 48); - if (--clk_freq < 4) - { - /* - * cover 1, 2, 3, 4 - */ - f = (HW_OTPC_SYS_CLK_FREQ)clk_freq; - } - else - { - clk_freq -= 5; - /* - * remaining valid values: - * - 0 (initially 6) - * - 2 (initially 8) - * - 6 (initially 12) - * - 10 (initially 16) - * - 18 (initially 24) - * - 26 (initially 32) - * - 42 (initially 48) - */ - - /* no odd valid values any more */ - ASSERT_WARNING(!(clk_freq & 1)); - - clk_freq >>= 1; - - /* - * remaining valid values: - * - 0 (initially 6) - * - 1 (initially 8) - * - 3 (initially 12) - * - 5 (initially 16) - * - 9 (initially 24) - * - 13 (initially 32) - * - 21 (initially 48) - */ - if (clk_freq > 8) - { - /* - * remaining valid values: - * - 9 (initially 24) - * - 13 (initially 32) - * - 21 (initially 48) - */ - if (clk_freq > 16) - { - ASSERT_WARNING(clk_freq == 21); - - f = HW_OTPC_SYS_CLK_FREQ_48; - } - else - { - clk_freq -= 8; + if (--clk_freq < 4) { + /* + * cover 1, 2, 3, 4 + */ + f = (HW_OTPC_SYS_CLK_FREQ)clk_freq; + } else { + clk_freq -= 5; /* * remaining valid values: - * - 1 (initially 24) - * - 5 (initially 32) + * - 0 (initially 6) + * - 2 (initially 8) + * - 6 (initially 12) + * - 10 (initially 16) + * - 18 (initially 24) + * - 26 (initially 32) + * - 42 (initially 48) */ - ASSERT_WARNING((clk_freq == 1) || (clk_freq == 5)); - if (clk_freq < 4) - { - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_24; + /* no odd valid values any more */ + ASSERT_WARNING(!(clk_freq & 1)); + + clk_freq >>= 1; + /* + * remaining valid values: + * - 0 (initially 6) + * - 1 (initially 8) + * - 3 (initially 12) + * - 5 (initially 16) + * - 9 (initially 24) + * - 13 (initially 32) + * - 21 (initially 48) + */ + if (clk_freq > 8) { + /* + * remaining valid values: + * - 9 (initially 24) + * - 13 (initially 32) + * - 21 (initially 48) + */ + if (clk_freq > 16) { + ASSERT_WARNING(clk_freq == 21); + + f = HW_OTPC_SYS_CLK_FREQ_48; + } else { + clk_freq -= 8; + /* + * remaining valid values: + * - 1 (initially 24) + * - 5 (initially 32) + */ + ASSERT_WARNING((clk_freq == 1) || (clk_freq == 5)); + + if (clk_freq < 4) + f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_24; + else + f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_32; + } + } else { + /* + * remaining valid values: + * - 0 (initially 6) + * - 1 (initially 8) + * - 3 (initially 12) + * - 5 (initially 16) + */ + if (clk_freq > 2) { + ASSERT_WARNING((clk_freq == 3) || (clk_freq == 5)); + + if (clk_freq > 4) + f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_16; + else + f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_12; + } else { + f = (HW_OTPC_SYS_CLK_FREQ)(HW_OTPC_SYS_CLK_FREQ_6 + clk_freq); + } } - else - { - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_32; - } - } } - else - { - /* - * remaining valid values: - * - 0 (initially 6) - * - 1 (initially 8) - * - 3 (initially 12) - * - 5 (initially 16) - */ - if (clk_freq > 2) - { - ASSERT_WARNING((clk_freq == 3) || (clk_freq == 5)); - if (clk_freq > 4) - { - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_16; - } - else - { - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_12; - } - } - else - { - f = (HW_OTPC_SYS_CLK_FREQ)(HW_OTPC_SYS_CLK_FREQ_6 + clk_freq); - } - } - } - - return f; + return f; } void hw_otpc_disable(void) { - /* - * Enable OTPC clock - */ - hw_otpc_init(); + /* + * Enable OTPC clock + */ + hw_otpc_init(); - /* - * set OTPC to stand-by mode - */ - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + /* + * set OTPC to stand-by mode + */ + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - /* - * Disable OTPC clock - */ - hw_otpc_close(); + /* + * Disable OTPC clock + */ + hw_otpc_close(); } __RETAINED_CODE void hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ clk_speed) { - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - /* - * Set access speed - */ - ASSERT_WARNING(clk_speed <= HW_OTPC_SYS_CLK_FREQ_48); + /* + * Set access speed + */ + ASSERT_WARNING(clk_speed <= HW_OTPC_SYS_CLK_FREQ_48); - OTPC->OTPC_TIM1_REG = tim1[clk_speed]; - HW_OTPC_REG_SETF(TIM2, CC_T_BCHK, tim2[clk_speed]); + OTPC->OTPC_TIM1_REG = tim1[clk_speed]; + HW_OTPC_REG_SETF(TIM2, CC_T_BCHK, tim2[clk_speed]); } void hw_otpc_power_save(uint32_t inactivity_period) { - /* Only go to power save for an inactivity_period < 1024 */ - ASSERT_WARNING(inactivity_period < 1024); + /* Only go to power save for an inactivity_period < 1024 */ + ASSERT_WARNING(inactivity_period < 1024); - HW_OTPC_REG_SETF(TIM2, CC_STBY_THR, inactivity_period); + HW_OTPC_REG_SETF(TIM2, CC_STBY_THR, inactivity_period); } uint32_t hw_otpc_num_of_rr(void) { - unsigned int i; + unsigned int i; - volatile uint32_t *ptr = (volatile uint32_t *)MEMORY_OTP_BASE; + volatile uint32_t *ptr = (volatile uint32_t *)MEMORY_OTP_BASE; - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - // STBY mode - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + // STBY mode + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - // The access will be performed in the spare rows - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 1); + // The access will be performed in the spare rows + HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 1); - // MREAD mode - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); + // MREAD mode + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); - // Read Records - i = 0; + // Read Records + i = 0; + while ((i < MAX_RR_AVAIL) && (ptr[0x9e - 4 * i] & 0x1)) { + i++; + } - while ((i < MAX_RR_AVAIL) && (ptr[0x9e - 4 * i] & 0x1)) - { - i++; - } + // STBY mode + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - // STBY mode - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + // Select the normal memory array + HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 0); - // Select the normal memory array - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 0); - - return i; + return i; } static bool manual_prog_verify(uint32_t cell_offset, uint32_t pword_l, uint32_t pword_h) { - uint32_t val_l, val_h, old_mode = OTPC->OTPC_MODE_REG; - uint32_t *addr = hw_otpc_cell_to_mem(cell_offset); + uint32_t val_l, val_h, old_mode = OTPC->OTPC_MODE_REG; + uint32_t *addr = hw_otpc_cell_to_mem(cell_offset); - /* we have to go through standby mode first */ - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - __DMB(); - HW_OTPC_REG_SETF(MODE, ERR_RESP_DIS, 1); - __DMB(); - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); + /* we have to go through standby mode first */ + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + __DMB(); + HW_OTPC_REG_SETF(MODE, ERR_RESP_DIS, 1); + __DMB(); + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) - { - HW_OTPC_REG_SETF(STAT, RERROR, - 1); //This bit need to be cleared manually (can only happen if a previous read has not checked/cleared it) - } - - /* - * Read cell in manual mode, as 2 32-bit values (little-endian) - */ - val_l = addr[0]; - val_h = addr[1]; - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - __DMB(); - OTPC->OTPC_MODE_REG = old_mode; - - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) - { - HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually - return false; - } - - return (pword_h == val_h) && (pword_l == val_l); + if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { + HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually (can only happen if a previous read has not checked/cleared it) + } + /* + * Read cell in manual mode, as 2 32-bit values (little-endian) + */ + val_l = addr[0]; + val_h = addr[1]; + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + __DMB(); + OTPC->OTPC_MODE_REG = old_mode; + if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { + HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually + return false; + } + return (pword_h == val_h) && (pword_l == val_l); } /* @@ -477,554 +447,496 @@ static bool manual_prog_verify(uint32_t cell_offset, uint32_t pword_l, uint32_t bool hw_otpc_manual_word_prog(uint32_t cell_offset, uint32_t pword_l, uint32_t pword_h, bool use_rr) { - int i; - bool ret = true; + int i; + bool ret = true; - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - ASSERT_CELL_OFFSET_VALID(cell_offset); + ASSERT_CELL_OFFSET_VALID(cell_offset); - /* - * Program the data regs - */ - OTPC->OTPC_PWORDL_REG = pword_l; - OTPC->OTPC_PWORDH_REG = pword_h; - - /* - * Start programming - */ - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MPROG); - OTPC->OTPC_PCTRL_REG = - HW_OTPC_FIELD_VAL(PCTRL, WADDR, cell_offset) | - HW_OTPC_FIELD_VAL(PCTRL, PSTART, 1); - wait_for_prog_done(); - - /* - * Check and retry up to 10 times - */ - i = 0; - - while (have_prog_error()) - { - if (i == 10) - { - break; - } - - i = i + 1; + /* + * Program the data regs + */ + OTPC->OTPC_PWORDL_REG = pword_l; + OTPC->OTPC_PWORDH_REG = pword_h; + /* + * Start programming + */ + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MPROG); OTPC->OTPC_PCTRL_REG = - HW_OTPC_FIELD_VAL(PCTRL, WADDR, cell_offset) | - HW_OTPC_FIELD_VAL(PCTRL, PSTART, 1) | - HW_OTPC_FIELD_VAL(PCTRL, PRETRY, 1); - + HW_OTPC_FIELD_VAL(PCTRL, WADDR, cell_offset) | + HW_OTPC_FIELD_VAL(PCTRL, PSTART, 1); wait_for_prog_done(); - } - if (i == 10) - { - ret = false; + /* + * Check and retry up to 10 times + */ + i = 0; + while (have_prog_error()) { + if (i == 10) { + break; + } + i = i + 1; - if (MANUAL_PROG_VERIFICATION) - { - ret = manual_prog_verify(cell_offset, pword_l, pword_h); + OTPC->OTPC_PCTRL_REG = + HW_OTPC_FIELD_VAL(PCTRL, WADDR, cell_offset) | + HW_OTPC_FIELD_VAL(PCTRL, PSTART, 1) | + HW_OTPC_FIELD_VAL(PCTRL, PRETRY, 1); + + wait_for_prog_done(); } - if (use_rr && !ret) - { - do - { - // Reset state - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + if (i == 10) { + ret = false; + if (MANUAL_PROG_VERIFICATION) + ret = manual_prog_verify(cell_offset, pword_l, pword_h); - // Abort if the writing was done in the spare area - if (OTPC->OTPC_MODE_REG & HW_OTPC_REG_FIELD_MASK(MODE, USE_SP_ROWS)) - { - break; + if (use_rr && !ret) { + do { + // Reset state + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + + // Abort if the writing was done in the spare area + if (OTPC->OTPC_MODE_REG & HW_OTPC_REG_FIELD_MASK(MODE, USE_SP_ROWS)) { + break; + } + + // Write the repair record to the spare area + if (!hw_otpc_write_rr(cell_offset, pword_l, pword_h)) { + break; + } + + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + // force reloading + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); + + ret = true; + break; + } while (0); } - - // Write the repair record to the spare area - if (!hw_otpc_write_rr(cell_offset, pword_l, pword_h)) - { - break; - } - - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - // force reloading - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); - - ret = true; - break; - } - while (0); } - } - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); + HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - return ret; + return ret; } bool hw_otpc_manual_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool use_rr) + uint32_t num_of_words, bool use_rr) { - uint32_t w, c, ncells, off, val; - bool ret = true; - const uint32_t *addr; + uint32_t w, c, ncells, off, val; + bool ret = true; + const uint32_t* addr; - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - ASSERT_CELL_OFFSET_VALID(cell_offset); + ASSERT_CELL_OFFSET_VALID(cell_offset); - if (num_of_words == 0) - { - return true; // early exit - } + if (num_of_words == 0) + return true; // early exit - /* index in p_data[] */ - w = 0; - off = cell_offset; + /* index in p_data[] */ + w = 0; + off = cell_offset; + if (cell_word == HW_OTPC_WORD_HIGH) { + /* + * read low 32-bit word so that we program the same value + */ + addr = hw_otpc_cell_to_mem(cell_offset); - if (cell_word == HW_OTPC_WORD_HIGH) - { - /* - * read low 32-bit word so that we program the same value - */ - addr = hw_otpc_cell_to_mem(cell_offset); + hw_otpc_manual_read_on(use_rr); + /* little-endian */ + val = addr[0]; + hw_otpc_manual_read_off(); - hw_otpc_manual_read_on(use_rr); - /* little-endian */ - val = addr[0]; - hw_otpc_manual_read_off(); + if (!hw_otpc_manual_word_prog(off++, val, p_data[w++], use_rr)) + return false; - if (!hw_otpc_manual_word_prog(off++, val, p_data[w++], use_rr)) - { - return false; + ncells = (num_of_words - 1) >> 1; + } else { + ncells = num_of_words >> 1; } - ncells = (num_of_words - 1) >> 1; - } - else - { - ncells = num_of_words >> 1; - } - - for (c = 0; c < ncells; c++, off++, w += 2) - { - if (!hw_otpc_manual_word_prog(off, p_data[w], p_data[w + 1], use_rr)) - { - return false; + for (c = 0; c < ncells; c++, off++, w += 2) { + if (!hw_otpc_manual_word_prog(off, p_data[w], p_data[w + 1], use_rr)) + return false; } - } - if (w < num_of_words) - { - /* - * read high 32-bit word so that we program the same value - */ - addr = hw_otpc_cell_to_mem(off); + if (w < num_of_words) { + /* + * read high 32-bit word so that we program the same value + */ + addr = hw_otpc_cell_to_mem(off); - hw_otpc_manual_read_on(use_rr); - /* little-endian */ - val = addr[1]; - hw_otpc_manual_read_off(); + hw_otpc_manual_read_on(use_rr); + /* little-endian */ + val = addr[1]; + hw_otpc_manual_read_off(); - if (!hw_otpc_manual_word_prog(off, p_data[w++], val, use_rr)) - { - return false; + if (!hw_otpc_manual_word_prog(off, p_data[w++], val, use_rr)) + return false; } - } - ASSERT_WARNING(w == num_of_words); + ASSERT_WARNING(w == num_of_words); - return ret; + return ret; } bool hw_otpc_write_rr(uint32_t cell_addr, uint32_t pword_l, uint32_t pword_h) { - uint32_t repair_cnt; - bool ret = false; + uint32_t repair_cnt; + bool ret = false; - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - // Get the number of used Repair Records - repair_cnt = hw_otpc_num_of_rr(); + // Get the number of used Repair Records + repair_cnt = hw_otpc_num_of_rr(); - // Abort if all repair records are being used - if (repair_cnt < MAX_RR_AVAIL) - { - do - { - // The access will be performed in the spare rows - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 1); + // Abort if all repair records are being used + if (repair_cnt < MAX_RR_AVAIL) { + do { + // The access will be performed in the spare rows + HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 1); - // Write the data to the spare area - if (!hw_otpc_manual_word_prog(0x4F - repair_cnt - 1, - pword_l, pword_h, false)) - { - break; - } + // Write the data to the spare area + if (!hw_otpc_manual_word_prog(0x4F - repair_cnt - 1, + pword_l, pword_h, false)) { + break; + } - // Write the header of the repair record to the spare area - if (!hw_otpc_manual_word_prog(0x4F - repair_cnt, - 1 | (cell_addr << 1), 0x00000000, false)) - { - break; - } + // Write the header of the repair record to the spare area + if (!hw_otpc_manual_word_prog(0x4F - repair_cnt, + 1 | (cell_addr << 1), 0x00000000, false)) { + break; + } - ret = true; + ret = true; + } while (0); + + // Return to the normal memory array + HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 0); + + if (ret) { + /* + * Request the reloading of the repair records at the next + * enabling of the OTP cell + */ + HW_OTPC_REG_SETF(MODE, RLD_RR_REQ, 1); + } } - while (0); - // Return to the normal memory array - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 0); - - if (ret) - { - /* - * Request the reloading of the repair records at the next - * enabling of the OTP cell - */ - HW_OTPC_REG_SETF(MODE, RLD_RR_REQ, 1); - } - } - - return ret; + return ret; } void hw_otpc_manual_read_on(bool spare_rows) { - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - /* - * Place the OTPC in manual read mode - */ - if (spare_rows) - { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_MREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else - { - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_MREAD; - } + /* + * Place the OTPC in manual read mode + */ + if (spare_rows) { + OTPC->OTPC_MODE_REG = + HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_MREAD) | + HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); + } + else { + OTPC->OTPC_MODE_REG = HW_OTPC_MODE_MREAD; + } } void hw_otpc_manual_read_off(void) { - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_MREAD); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_MREAD); - /* - * Place the OTPC in STBY mode - */ - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_STBY; + /* + * Place the OTPC in STBY mode + */ + OTPC->OTPC_MODE_REG = HW_OTPC_MODE_STBY; } bool hw_otpc_dma_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) + uint32_t num_of_words, bool spare_rows) { - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - ASSERT_CELL_OFFSET_VALID(cell_offset); + ASSERT_CELL_OFFSET_VALID(cell_offset); - /* - * Make sure that the size is valid - */ - ASSERT_WARNING(num_of_words); - ASSERT_WARNING(num_of_words < 16384); - - /* - * Set up DMA - */ - unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); - - if (IS_SYSRAM_ADDRESS(p_data) || - (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) - { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#if dg_configEXEC_MODE != MODE_IS_CACHED - } - else if (IS_CACHERAM_ADDRESS(p_data)) - { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#endif - } - else - { /* - * Destination address can only reside in RAM or Cache RAM, but in case of remapped - * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) + * Make sure that the size is valid */ - ASSERT_WARNING(0); - } + ASSERT_WARNING(num_of_words); + ASSERT_WARNING(num_of_words < 16384); - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words - 1; + /* + * Set up DMA + */ + unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); - /* - * Start DMA programming - */ - if (spare_rows) - { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else - { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1); - } + if (IS_SYSRAM_ADDRESS(p_data) || + (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) { + OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); +#if dg_configEXEC_MODE != MODE_IS_CACHED + } else if (IS_CACHERAM_ADDRESS(p_data)) { + OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); +#endif + } else { + /* + * Destination address can only reside in RAM or Cache RAM, but in case of remapped + * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) + */ + ASSERT_WARNING(0); + } - wait_for_auto_done(); + OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); + OTPC->OTPC_NWORDS_REG = num_of_words-1; - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PERR_UNC)) - { - return false; - } + /* + * Start DMA programming + */ + if (spare_rows) { + OTPC->OTPC_MODE_REG = + HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | + HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1) | + HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); + } + else { + OTPC->OTPC_MODE_REG = + HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | + HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1); + } - return true; + wait_for_auto_done(); + + /* + * Check result + */ + if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PERR_UNC)) { + return false; + } + + return true; } void hw_otpc_dma_read(uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) + uint32_t num_of_words, bool spare_rows) { - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - ASSERT_CELL_OFFSET_VALID(cell_offset); + ASSERT_CELL_OFFSET_VALID(cell_offset); - /* - * Make sure that the size is valid - */ - ASSERT_WARNING(num_of_words); - ASSERT_WARNING(num_of_words < 16384); - - /* - * Set up DMA - */ - unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); - - if (IS_SYSRAM_ADDRESS(p_data) || - (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) - { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#if dg_configEXEC_MODE != MODE_IS_CACHED - } - else if (IS_CACHERAM_ADDRESS(p_data)) - { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#endif - } - else - { /* - * Destination address can only reside in RAM or Cache RAM, but in case of remapped - * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) + * Make sure that the size is valid */ - ASSERT_WARNING(0); - } + ASSERT_WARNING(num_of_words); + ASSERT_WARNING(num_of_words < 16384); - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words - 1; + /* + * Set up DMA + */ + unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); - /* - * Start DMA programming - */ - if (spare_rows) - { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else - { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1); - } + if (IS_SYSRAM_ADDRESS(p_data) || + (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) { + OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); +#if dg_configEXEC_MODE != MODE_IS_CACHED + } else if (IS_CACHERAM_ADDRESS(p_data)) { + OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); +#endif + } else { + /* + * Destination address can only reside in RAM or Cache RAM, but in case of remapped + * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) + */ + ASSERT_WARNING(0); + } - wait_for_auto_done(); + OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); + OTPC->OTPC_NWORDS_REG = num_of_words-1; + + /* + * Start DMA programming + */ + if (spare_rows) { + OTPC->OTPC_MODE_REG = + HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | + HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1) | + HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); + } + else { + OTPC->OTPC_MODE_REG = + HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | + HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1); + } + + wait_for_auto_done(); } bool hw_otpc_fifo_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) + uint32_t num_of_words, bool spare_rows) { - unsigned int i; + unsigned int i; - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - ASSERT_CELL_OFFSET_VALID(cell_offset); + ASSERT_CELL_OFFSET_VALID(cell_offset); - ASSERT_WARNING_NONZERO_RANGE(num_of_words, 16384); + ASSERT_WARNING_NONZERO_RANGE(num_of_words, 16384); - /* - * Set up FIFO - */ - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words - 1; + /* + * Set up FIFO + */ + OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); + OTPC->OTPC_NWORDS_REG = num_of_words-1; - /* - * Perform programming via FIFO - */ - if (spare_rows) - { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else - { - OTPC->OTPC_MODE_REG = HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG); - } + /* + * Perform programming via FIFO + */ + if (spare_rows) { + OTPC->OTPC_MODE_REG = + HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | + HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); + } + else { + OTPC->OTPC_MODE_REG = HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG); + } - for (i = 0; i < num_of_words; i++) - { - while (HW_OTPC_REG_GETF(STAT, FWORDS) == 8) - ; + for (i = 0; i < num_of_words; i++) { + while (HW_OTPC_REG_GETF(STAT, FWORDS) == 8) + ; + OTPC->OTPC_FFPRT_REG = p_data[i]; // Write FIFO data + } - OTPC->OTPC_FFPRT_REG = p_data[i]; // Write FIFO data - } + /* + * Wait for completion + */ + wait_for_auto_done(); - /* - * Wait for completion - */ - wait_for_auto_done(); + /* + * Check result + */ + if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PERR_UNC)) { + return false; + } - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PERR_UNC)) - { - return false; - } - - return true; + return true; } bool hw_otpc_fifo_read(uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) + uint32_t num_of_words, bool spare_rows) { - unsigned int i; + unsigned int i; - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - ASSERT_CELL_OFFSET_VALID(cell_offset); + ASSERT_CELL_OFFSET_VALID(cell_offset); - ASSERT_WARNING_NONZERO_RANGE(num_of_words, 16384); + ASSERT_WARNING_NONZERO_RANGE(num_of_words, 16384); - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) - { - HW_OTPC_REG_SETF(STAT, RERROR, - 1); //This bit need to be cleared manually (can only happen if a previous read has not checked/cleared it) - } + if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { + HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually (can only happen if a previous read has not checked/cleared it) + } - /* - * Set up FIFO - */ - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words - 1; + /* + * Set up FIFO + */ + OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); + OTPC->OTPC_NWORDS_REG = num_of_words-1; - /* - * Perform reading via FIFO - */ - if (spare_rows) - { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else - { - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_AREAD; - } + /* + * Perform reading via FIFO + */ + if (spare_rows) { + OTPC->OTPC_MODE_REG = + HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | + HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); + } + else { + OTPC->OTPC_MODE_REG = HW_OTPC_MODE_AREAD; + } - for (i = 0; i < num_of_words; i++) - { - while (HW_OTPC_REG_GETF(STAT, FWORDS) == 0) - ; + for (i = 0; i < num_of_words; i++) { + while (HW_OTPC_REG_GETF(STAT, FWORDS) == 0) + ; + p_data[i] = OTPC->OTPC_FFPRT_REG; + } - p_data[i] = OTPC->OTPC_FFPRT_REG; - } + /* + * Wait for completion + */ + wait_for_auto_done(); - /* - * Wait for completion - */ - wait_for_auto_done(); + /* + * Check result + */ + if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { + HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually + return false; + } - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) - { - HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually - return false; - } - - return true; + return true; } void hw_otpc_prepare(uint32_t num_of_bytes) { - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - ASSERT_WARNING_NONZERO_RANGE(num_of_bytes, 65536); + ASSERT_WARNING_NONZERO_RANGE(num_of_bytes, 65536); - /* - * Set up image size - */ - OTPC->OTPC_NWORDS_REG = ((num_of_bytes + 3) >> 2) - 1; + /* + * Set up image size + */ + OTPC->OTPC_NWORDS_REG = ((num_of_bytes + 3) >> 2) - 1; - /* - * Enable OTP_COPY - */ - CRG_TOP->SYS_CTRL_REG |= 1 << REG_POS(CRG_TOP, SYS_CTRL_REG, OTP_COPY); + /* + * Enable OTP_COPY + */ + GLOBAL_INT_DISABLE(); + CRG_TOP->SYS_CTRL_REG |= 1 << REG_POS(CRG_TOP, SYS_CTRL_REG, OTP_COPY); + GLOBAL_INT_RESTORE(); } void hw_otpc_cancel_prepare(void) { - ASSERT_WARNING_OTP_CLK_ENABLED; + ASSERT_WARNING_OTP_CLK_ENABLED; - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - /* - * Disable OTP_COPY - */ - CRG_TOP->SYS_CTRL_REG &= ~REG_MSK(CRG_TOP, SYS_CTRL_REG, OTP_COPY); + /* + * Disable OTP_COPY + */ + GLOBAL_INT_DISABLE(); + CRG_TOP->SYS_CTRL_REG &= ~REG_MSK(CRG_TOP, SYS_CTRL_REG, OTP_COPY); + GLOBAL_INT_RESTORE(); } @@ -1045,47 +957,46 @@ void hw_otpc_cancel_prepare(void) */ static int hw_otpc_core_test(int mode) { - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); + ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - /* - * Put OTPC in the proper test mode - */ - HW_OTPC_REG_SETF(MODE, MODE, mode); + /* + * Put OTPC in the proper test mode + */ + HW_OTPC_REG_SETF(MODE, MODE, mode); - /* - * Wait end of test - */ - while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, TRDY))) - ; + /* + * Wait end of test + */ + while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, TRDY))) + ; - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, TERROR)) - { - return 1; - } + /* + * Check result + */ + if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, TERROR)) { + return 1; + } - return 0; + return 0; } int hw_otpc_blank(void) { - return hw_otpc_core_test(HW_OTPC_MODE_TBLANK); + return hw_otpc_core_test(HW_OTPC_MODE_TBLANK); } int hw_otpc_tdec(void) { - return hw_otpc_core_test(HW_OTPC_MODE_TDEC); + return hw_otpc_core_test(HW_OTPC_MODE_TDEC); } int hw_otpc_twr(void) { - return hw_otpc_core_test(HW_OTPC_MODE_TWR); + return hw_otpc_core_test(HW_OTPC_MODE_TWR); } diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c index acef29507..862367c1c 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c @@ -54,137 +54,119 @@ __attribute__((section("text_retained"))) #endif void hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) { - switch (mode) - { - case HW_QSPI_BUS_MODE_SINGLE: - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE); - break; - - case HW_QSPI_BUS_MODE_DUAL: - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_DUAL); - break; - - case HW_QSPI_BUS_MODE_QUAD: - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD); - hw_qspi_set_io2_output(false); - hw_qspi_set_io3_output(false); - break; - } + switch (mode) { + case HW_QSPI_BUS_MODE_SINGLE: + QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE); + break; + case HW_QSPI_BUS_MODE_DUAL: + QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_DUAL); + break; + case HW_QSPI_BUS_MODE_QUAD: + QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD); + hw_qspi_set_io2_output(false); + hw_qspi_set_io3_output(false); + break; + } } __attribute__((section("text_retained"))) void hw_qspi_set_automode(bool automode) { - if (automode) - { - const uint32_t burst_cmd_a = QSPIC->QSPIC_BURSTCMDA_REG; - const uint32_t burst_cmd_b = QSPIC->QSPIC_BURSTCMDB_REG; - const uint32_t status_cmd = QSPIC->QSPIC_STATUSCMD_REG; - const uint32_t erase_cmd_b = QSPIC->QSPIC_ERASECMDB_REG; - const uint32_t burstbrk = QSPIC->QSPIC_BURSTBRK_REG; - - if (GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_INST_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_ADR_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_DMY_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_EXT_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_ERS_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_WEN_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_SUS_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_RES_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_EAD_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTBRK_REG, burstbrk, QSPIC_BRK_TX_MD) == HW_QSPI_BUS_MODE_QUAD) - { - hw_qspi_set_io2_output(false); - hw_qspi_set_io3_output(false); + if (automode) { + const uint32_t burst_cmd_a = QSPIC->QSPIC_BURSTCMDA_REG; + const uint32_t burst_cmd_b = QSPIC->QSPIC_BURSTCMDB_REG; + const uint32_t status_cmd = QSPIC->QSPIC_STATUSCMD_REG; + const uint32_t erase_cmd_b = QSPIC->QSPIC_ERASECMDB_REG; + const uint32_t burstbrk = QSPIC->QSPIC_BURSTBRK_REG; + if (GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_INST_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_ADR_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_DMY_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_EXT_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_ERS_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_WEN_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_SUS_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_RES_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_EAD_TX_MD) == HW_QSPI_BUS_MODE_QUAD || + GETBITS32(QSPIC, QSPIC_BURSTBRK_REG, burstbrk, QSPIC_BRK_TX_MD) == HW_QSPI_BUS_MODE_QUAD) { + hw_qspi_set_io2_output(false); + hw_qspi_set_io3_output(false); + } } - } - - HW_QSPIC_REG_SETF(CTRLMODE, AUTO_MD, automode); + HW_QSPIC_REG_SETF(CTRLMODE, AUTO_MD, automode); } void hw_qspi_set_wrapping_burst_instruction(uint8_t inst, HW_QSPI_WRAP_LEN len, - HW_QSPI_WRAP_SIZE size) + HW_QSPI_WRAP_SIZE size) { - HW_QSPIC_REG_SETF(BURSTCMDA, INST_WB, inst); - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE, size) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN, len) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_MD, 1); + HW_QSPIC_REG_SETF(BURSTCMDA, INST_WB, inst); + QSPIC->QSPIC_BURSTCMDB_REG = + (QSPIC->QSPIC_BURSTCMDB_REG & + ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE) | + REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN))) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE, size) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN, len) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_MD, 1); } void hw_qspi_set_dummy_bytes_count(uint8_t count) { - if (count == 3) - { - HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1); - } - else - { - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, - dummy_num[count]); - } + if (count == 3) { + HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1); + } else { + QSPIC->QSPIC_BURSTCMDB_REG = + (QSPIC->QSPIC_BURSTCMDB_REG & + ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) | + REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, + dummy_num[count]); + } } void hw_qspi_erase_block(uint32_t addr) { - if (!hw_qspi_get_automode()) - { - hw_qspi_set_automode(true); - } + if (!hw_qspi_get_automode()) { + hw_qspi_set_automode(true); + } + // Wait for previous erase to end + while (hw_qspi_get_erase_status() != 0) { + } - // Wait for previous erase to end - while (hw_qspi_get_erase_status() != 0) - { - } - - if (hw_qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32) - { - addr >>= 12; - } - else - { - addr >>= 4; - } - - // Setup erase block page - HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr); - // Fire erase - HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); + if (hw_qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32) { + addr >>= 12; + } else { + addr >>= 4; + } + // Setup erase block page + HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr); + // Fire erase + HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); } void hw_qspi_set_pads(HW_QSPI_SLEW_RATE rate, HW_QSPI_DRIVE_CURRENT current) { - QSPIC->QSPIC_GP_REG = - BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_SLEW, rate) | - BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_DRV, current); + QSPIC->QSPIC_GP_REG = + BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_SLEW, rate) | + BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_DRV, current); } void hw_qspi_init(const qspi_config *cfg) { - hw_qspi_enable_clock(); - hw_qspi_set_automode(false); - hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - hw_qspi_set_io2_output(true); - hw_qspi_set_io2(1); - hw_qspi_set_io3_output(true); - hw_qspi_set_io3(1); + hw_qspi_enable_clock(); + hw_qspi_set_automode(false); + hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + hw_qspi_set_io2_output(true); + hw_qspi_set_io2(1); + hw_qspi_set_io3_output(true); + hw_qspi_set_io3(1); - if (cfg) - { - hw_qspi_set_address_size(cfg->address_size); - hw_qspi_set_clock_mode(cfg->idle_clock); - hw_qspi_set_read_sampling_edge(cfg->sampling_edge); - } + if (cfg) { + hw_qspi_set_address_size(cfg->address_size); + hw_qspi_set_clock_mode(cfg->idle_clock); + hw_qspi_set_read_sampling_edge(cfg->sampling_edge); + } } #endif /* dg_configUSE_HW_QSPI */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c index cc2c6c71e..68f2caf26 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c @@ -10,7 +10,7 @@ /** ***************************************************************************************** * - * @file + * @file hw_rf.c * * @brief Radio module (RF) Low Level Driver API definition. * @@ -84,34 +84,30 @@ bool hw_rf_check_iff_timeout(uint64_t start_time) __attribute__((weak)); #include "hw_fem_sky66112-11.h" #endif -typedef enum rf_states_e -{ - RF_ST_OFF = 0, - RF_ST_ON, - RF_ST_CONFIG, - RF_ST_WAIT_NEXT1, - RF_ST_WAIT_NEXT2 +typedef enum rf_states_e { + RF_ST_OFF = 0, + RF_ST_ON, + RF_ST_CONFIG, + RF_ST_WAIT_NEXT1, + RF_ST_WAIT_NEXT2 } rf_states_e; #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -typedef enum -{ - IFF_MODE_CTRL_BLE = 0, - IFF_MODE_CTRL_FTDF = 1, - IFF_MODE_CTRL_COMBO = 2 +typedef enum { + IFF_MODE_CTRL_BLE = 0, + IFF_MODE_CTRL_FTDF = 1, + IFF_MODE_CTRL_COMBO = 2 } iff_mode_ctrl_e; -typedef enum -{ - IFF_MODE_OVR_BLE = 1, - IFF_MODE_OVR_FTDF = 2 +typedef enum { + IFF_MODE_OVR_BLE = 1, + IFF_MODE_OVR_FTDF = 2 } iff_mode_ovr_e; -typedef enum -{ - MGC_MODE_CTRL_BLE_GAUSSDAC = 0, - MGC_MODE_CTRL_BLE_TXDAC = 1, - MGC_MODE_CTRL_FTDF = 2 +typedef enum { + MGC_MODE_CTRL_BLE_GAUSSDAC = 0, + MGC_MODE_CTRL_BLE_TXDAC = 1, + MGC_MODE_CTRL_FTDF = 2 } mgc_mode_ctrl_e; #endif @@ -160,45 +156,42 @@ static uint16_t rf_enable_config45_ftdf_reg_value; #endif bool hw_rf_system_init(void) { - bool calib_succeeded; + bool calib_succeeded; - rf_state = RF_ST_OFF; - rf_request = 0; + rf_state = RF_ST_OFF; + rf_request = 0; #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - - /* Initially set kmoda_cal to its preferred settings value */ - if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) - && (CHIP_IS_AE))) - { - kmoda_cal = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, - KMOD_ALPHA_BLE); - } - + /* Initially set kmoda_cal to its preferred settings value */ + if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) + && (CHIP_IS_AE))) { + kmoda_cal = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, + KMOD_ALPHA_BLE); + } #endif #if dg_configCOEX_ENABLE_CONFIG == 1 - hw_coex_init(); + hw_coex_init(); #endif - /* Apply tcs and preferred settings */ - hw_rf_apply_tcs_cb(); - hw_rf_set_recommended_settings(); + /* Apply tcs and preferred settings */ + hw_rf_apply_tcs_cb(); + hw_rf_set_recommended_settings(); - /* Perform calibration */ - calib_succeeded = hw_rf_calibration(); + /* Perform calibration */ + calib_succeeded = hw_rf_calibration(); #ifndef CONFIG_USE_BLE - /* Force disable the ble, making the ftdf the only requester */ - REG_SET_BIT(CRG_TOP, FORCE_SLEEP_REG, FORCE_BLE_SLEEP); + /* Force disable the ble, making the ftdf the only requester */ + REG_SET_BIT(CRG_TOP, FORCE_SLEEP_REG, FORCE_BLE_SLEEP); #endif #ifndef CONFIG_USE_FTDF - /* Force disable the ftdf, making the ble the only requester */ - REG_SET_BIT(CRG_TOP, FORCE_SLEEP_REG, FORCE_FTDF_SLEEP); + /* Force disable the ftdf, making the ble the only requester */ + REG_SET_BIT(CRG_TOP, FORCE_SLEEP_REG, FORCE_FTDF_SLEEP); #endif - /* System is ready to be used */ - return calib_succeeded; + /* System is ready to be used */ + return calib_succeeded; } /** @@ -208,173 +201,174 @@ bool hw_rf_system_init(void) void hw_rf_set_recommended_settings(void) { - // Preferred Settings File for DCTMON - // Device : DA14680AA - // Package : All packages, no dependency on package. - // Last change date : June 18, 2015 - 18:00:48 - // Last change item : Register: RF_KMOD_ALPHA_REG, Field: KMOD_ALPHA_FTDF, Value: 0x10 - // File date : June 18, 2015 - 19:16:16 + // Preferred Settings File for DCTMON + // Device : DA14680AA + // Package : All packages, no dependency on package. + // Last change date : June 18, 2015 - 18:00:48 + // Last change item : Register: RF_KMOD_ALPHA_REG, Field: KMOD_ALPHA_FTDF, Value: 0x10 + // File date : June 18, 2015 - 19:16:16 #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - if (((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)) - || (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, E))) - { - REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0030, 0x00F5); - REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); + if (((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)) + || (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, E))) { + REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0030, 0x00F5); + REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); - // MP - REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_10_REG, 0xFF00, 0x182E); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_11_REG, 0xFF00, 0x1830); - RFCU_POWER->RF_CNTRL_TIMER_12_REG = 0x3C; - RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x163C; - RFCU_POWER->RF_CNTRL_TIMER_15_REG = 0x183C; - RFCU_POWER->RF_CNTRL_TIMER_16_REG = 0x2207; - RFCU_POWER->RF_CNTRL_TIMER_17_REG = 0x410; - RFCU_POWER->RF_CNTRL_TIMER_18_REG = 0x218; - RFCU_POWER->RF_CNTRL_TIMER_19_REG = 0x218; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x1E00); - RFCU_POWER->RF_CNTRL_TIMER_20_REG = 0x508; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_21_REG, 0x00FF, 0x44); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_22_REG, 0x00FF, 0x40); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_23_REG, 0x00FF, 0x52); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x1B08); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x1A10); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x1818); - REG_SET_MASKED(RFCU, RF_CP_CTRL_BLE_REG, 0x0F0F, 0x7575); - REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); - REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0202, 0x01D0); - REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL3_REG, 0x00FF, 0xDCE4); - REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_BLE_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_FTDF_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_BLE_REG, 0x03E0, 0x01E0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_FTDF_REG, 0x03E0, 0x01E0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_BLE_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_FTDF_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG24_FTDF_REG, 0x03E0, 0x01A0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG25_FTDF_REG, 0x03E0, 0x0060); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_BLE_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_FTDF_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_BLE_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_FTDF_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_BLE_REG, 0x001F, 0x00F3); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_FTDF_REG, 0x001F, 0x00F3); - RFCU_POWER->RF_ENABLE_CONFIG42_BLE_REG = 0x210; - RFCU_POWER->RF_ENABLE_CONFIG42_FTDF_REG = 0x210; - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_BLE_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_FTDF_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_BLE_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_FTDF_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_BLE_REG, 0x001F, 0x0017); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_FTDF_REG, 0x001F, 0x0017); - REG_SET_MASKED(DEM, RF_FTDF_CTRL1_REG, 0xC000, 0x87C0); - REG_SET_MASKED(DEM, RF_FTDF_CTRL2_REG, 0x0700, 0x6810); - REG_SET_MASKED(DEM, RF_FTDF_CTRL5_REG, 0x1FFF, 0x4708); - REG_SET_MASKED(DEM, RF_FTDF_LOOP_GAIN_DS_REG, 0x00FF, 0x0060); - REG_SET_MASKED(DEM, RF_FTDF_LOOP_GAIN_PD_REG, 0x00FF, 0x0060); - PLLDIG->RF_KMOD_ALPHA_REG = KMODE_ALPHA_ACAD_PREF; - REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x001F, 0x00C0); - REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_BLE_REG, 0x0F0F, 0x7474); - REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); + // MP + REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_10_REG, 0xFF00, 0x182E); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_11_REG, 0xFF00, 0x1830); + RFCU_POWER->RF_CNTRL_TIMER_12_REG = 0x3C; + RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x163C; + RFCU_POWER->RF_CNTRL_TIMER_15_REG = 0x183C; + RFCU_POWER->RF_CNTRL_TIMER_16_REG = 0x2207; + RFCU_POWER->RF_CNTRL_TIMER_17_REG = 0x410; + RFCU_POWER->RF_CNTRL_TIMER_18_REG = 0x218; + RFCU_POWER->RF_CNTRL_TIMER_19_REG = 0x218; + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x1E00); + RFCU_POWER->RF_CNTRL_TIMER_20_REG = 0x508; + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_21_REG, 0x00FF, 0x44); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_22_REG, 0x00FF, 0x40); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_23_REG, 0x00FF, 0x52); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x1B08); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x1A10); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x1818); + REG_SET_MASKED(RFCU, RF_CP_CTRL_BLE_REG, 0x0F0F, 0x7575); + REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); + REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0202, 0x01D0); + REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL3_REG, 0x00FF, 0xDCE4); + REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_BLE_REG, 0x001F, 0x0054); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_FTDF_REG, 0x001F, 0x0054); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_BLE_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_FTDF_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_BLE_REG, 0x03E0, 0x01E0); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_FTDF_REG, 0x03E0, 0x01E0); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_BLE_REG, 0x001F, 0x0054); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_FTDF_REG, 0x001F, 0x0054); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_BLE_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_FTDF_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_BLE_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_FTDF_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_BLE_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_FTDF_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG24_FTDF_REG, 0x03E0, 0x01A0); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG25_FTDF_REG, 0x03E0, 0x0060); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_BLE_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_FTDF_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_BLE_REG, 0x001F, 0x00B2); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_FTDF_REG, 0x001F, 0x00B2); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_BLE_REG, 0x001F, 0x00B2); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_FTDF_REG, 0x001F, 0x00B2); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_BLE_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_FTDF_REG, 0x001F, 0x0071); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_BLE_REG, 0x001F, 0x00F3); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_FTDF_REG, 0x001F, 0x00F3); + RFCU_POWER->RF_ENABLE_CONFIG42_BLE_REG = 0x210; + RFCU_POWER->RF_ENABLE_CONFIG42_FTDF_REG = 0x210; + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_BLE_REG, 0x001F, 0x0015); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_FTDF_REG, 0x001F, 0x0015); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_BLE_REG, 0x001F, 0x0016); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_FTDF_REG, 0x001F, 0x0016); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_BLE_REG, 0x001F, 0x0017); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_FTDF_REG, 0x001F, 0x0017); + REG_SET_MASKED(DEM, RF_FTDF_CTRL1_REG, 0xC000, 0x87C0); + REG_SET_MASKED(DEM, RF_FTDF_CTRL2_REG, 0x0700, 0x6810); + REG_SET_MASKED(DEM, RF_FTDF_CTRL5_REG, 0x1FFF, 0x4708); + REG_SET_MASKED(DEM, RF_FTDF_LOOP_GAIN_DS_REG, 0x00FF, 0x0060); + REG_SET_MASKED(DEM, RF_FTDF_LOOP_GAIN_PD_REG, 0x00FF, 0x0060); + PLLDIG->RF_KMOD_ALPHA_REG = KMODE_ALPHA_ACAD_PREF; + REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x001F, 0x00C0); + REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_BLE_REG, 0x0F0F, 0x7474); + REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); - PLLDIG->RF_MGAIN_CTRL2_REG = 0x0006; - REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_BLE_REG, 0x1C00, 0x1403); + PLLDIG->RF_MGAIN_CTRL2_REG = 0x0006; + REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_BLE_REG, 0x1C00, 0x1403); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL2_REG, 0x001F, 0x0000); - REG_SET_MASKED(PLLDIG, RF_MSKMOD_CTRL1_REG, 0x0003, 0x0003); - REG_SET_MASKED(RFCU, RF_REF_OSC_BLE_REG, 0x7FC0, 0x302C); - REG_SET_MASKED(RFCU, RF_REF_OSC_FTDF_REG, 0x7FC0, 0x302C); - REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL2_REG, 0x001F, 0x0000); + REG_SET_MASKED(PLLDIG, RF_MSKMOD_CTRL1_REG, 0x0003, 0x0003); + REG_SET_MASKED(RFCU, RF_REF_OSC_BLE_REG, 0x7FC0, 0x302C); + REG_SET_MASKED(RFCU, RF_REF_OSC_FTDF_REG, 0x7FC0, 0x302C); + REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); - REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x4800, 0x4000); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x14C0, 0x108B); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x00C0, 0x009B); - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_1_REG, 0x003F, 0x003B); - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_2_REG, 0x003F, 0x0037); - RFCU->RF_TX_PWR_LUT_3_REG = 0x01F6; - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_4_REG, 0x003F, 0x0036); - PLLDIG->RF_VCO_CALCAP_BIT14_REG = 0xD59D; + REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x4800, 0x4000); + REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x14C0, 0x108B); + REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x00C0, 0x009B); + REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_1_REG, 0x003F, 0x003B); + REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_2_REG, 0x003F, 0x0037); + RFCU->RF_TX_PWR_LUT_3_REG = 0x01F6; + REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_4_REG, 0x003F, 0x0036); + PLLDIG->RF_VCO_CALCAP_BIT14_REG = 0xD59D; - /* FTDF specific */ - REG_SETF(DEM, RF_FTDF_CTRL5_REG, RSSITH, 1800); - } + /* FTDF specific */ + REG_SETF(DEM, RF_FTDF_CTRL5_REG, RSSITH, 1800); + } - REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); + REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); #else - REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0330, 0x01F5); - REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); - REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); - REG_SET_MASKED(DEM, RF_CCA_RSSITH_REG, 0xE000, 0xE708); + REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0330, 0x01F5); + REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); + REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); + REG_SET_MASKED(DEM, RF_CCA_RSSITH_REG, 0xE000, 0xE708); - RFCU_POWER->RF_CNTRL_TIMER_10_REG = 0x0A42; - RFCU_POWER->RF_CNTRL_TIMER_11_REG = 0x0A44; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_12_REG, 0x00FF, 0x0050); - RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x0850; - RFCU_POWER->RF_CNTRL_TIMER_14_REG = 0x1858; - RFCU_POWER->RF_CNTRL_TIMER_15_REG = 0x0A50; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_16_REG, 0xFF00, 0x1207); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x0F00); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_21_REG, 0x00FF, 0x0044); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_22_REG, 0x00FF, 0x0040); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_23_REG, 0x00FF, 0x0052); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x0D08); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x0C10); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x0A18); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x0A18); - RFCU->RF_CP_CTRL_BLE_REG = 0x3535; - REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); - REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0402, 0x05D0); - REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG16_REG, 0x001F, 0x0014); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, 0x03E0, 0x0000); - RFCU_POWER->RF_ENABLE_CONFIG42_REG = 0x0210; - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, 0x03E0, 0x0060); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_BLE_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_FTDF_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_BLE_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_FTDF_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_BLE_REG, 0x001F, 0x0017); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_FTDF_REG, 0x001F, 0x0017); - REG_SET_MASKED(DEM, RF_FTDF_CTRL1_REG, 0xC000, 0x47C0); - REG_SET_MASKED(DEM, RF_FTDF_SIGDET_CTRL_REG, 0x1FFF, 0x0B6A); - REG_SET_MASKED(PLLDIG, RF_KMOD_ALPHA_BLE_REG, 0x0FC0, 0x030C); - PLLDIG->RF_KMOD_ALPHA_FTDF_REG = 0x000D; - RFCU->RF_LF_RES_CTRL_BLE_REG = 0x3434; - REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x0040, 0x0080); - REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); - RFCU->RF_LO_IQ_TRIM_REG = 0x0001; - PLLDIG->RF_MGAIN_CTRL3_REG = 0x0050; - REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_FTDF_REG, 0xFF00, 0x5000); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_OVERRULE_REG, 0x3C00, 0x5800); - REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); - REG_SET_MASKED(RFCU, RF_SPARE1_BLE_REG, 0x0038, 0x0018); - REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x0008, 0x0008); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x20C0, 0x304B); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x0040, 0x004B); - RFCU->RF_TX_PWR_LUT_5_REG = 0x09FF; - REG_SET_MASKED(RFCU, RF_TXDAC_CTRL_REG, 0x0040, 0x0000); + RFCU_POWER->RF_CNTRL_TIMER_10_REG = 0x0A42; + RFCU_POWER->RF_CNTRL_TIMER_11_REG = 0x0A44; + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_12_REG, 0x00FF, 0x0050); + RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x0850; + RFCU_POWER->RF_CNTRL_TIMER_14_REG = 0x1858; + RFCU_POWER->RF_CNTRL_TIMER_15_REG = 0x0A50; + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_16_REG, 0xFF00, 0x1207); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x0F00); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_21_REG, 0x00FF, 0x0044); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_22_REG, 0x00FF, 0x0040); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_23_REG, 0x00FF, 0x0052); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x0D08); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x0C10); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x0A18); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x0A18); + RFCU->RF_CP_CTRL_BLE_REG = 0x3535; + REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); + REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0402, 0x05D0); + REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG16_REG, 0x001F, 0x0014); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, 0x03E0, 0x0000); + RFCU_POWER->RF_ENABLE_CONFIG42_REG = 0x0210; + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, 0x03E0, 0x0060); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_BLE_REG, 0x001F, 0x0015); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_FTDF_REG, 0x001F, 0x0015); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_BLE_REG, 0x001F, 0x0016); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_FTDF_REG, 0x001F, 0x0016); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_BLE_REG, 0x001F, 0x0017); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_FTDF_REG, 0x001F, 0x0017); + REG_SET_MASKED(DEM, RF_FTDF_CTRL1_REG, 0xCC00, 0x4BC0); + REG_SET_MASKED(DEM, RF_FTDF_CTRL4_REG, 0x0500, 0xC6A7); + REG_SET_MASKED(DEM, RF_FTDF_SIGDET_CTRL_REG, 0x1FFF, 0x0BC3); + REG_SET_MASKED(PLLDIG, RF_KMOD_ALPHA_BLE_REG, 0x0FC0, 0x030C); + PLLDIG->RF_KMOD_ALPHA_FTDF_REG = 0x000D; + RFCU->RF_LF_RES_CTRL_BLE_REG = 0x3434; + REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x0040, 0x0080); + REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); + RFCU->RF_LO_IQ_TRIM_REG = 0x0001; + PLLDIG->RF_MGAIN_CTRL3_REG = 0x0050; + REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_FTDF_REG, 0xFF00, 0x5000); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); + REG_SET_MASKED(RFCU, RF_OVERRULE_REG, 0x3C00, 0x5800); + REG_SET_MASKED(RFCU, RF_REF_OSC_FTDF_REG, 0x7FFF, 0x31EB); + REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); + REG_SET_MASKED(RFCU, RF_SPARE1_BLE_REG, 0x0038, 0x0018); + REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x0008, 0x0008); + REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x20C0, 0x304B); + REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x0040, 0x004B); + RFCU->RF_TX_PWR_LUT_5_REG = 0x09FF; + REG_SET_MASKED(RFCU, RF_TXDAC_CTRL_REG, 0x0040, 0x0000); #endif } @@ -391,488 +385,438 @@ void hw_rf_set_recommended_settings(void) static void hw_rf_modulation_gain_calibration_start(bool mode_ble) { - uint32_t calcap_mid; // MP-12-02-2016 + uint32_t calcap_mid; // MP-12-02-2016 - // Store all the registers that will be changed in this function - rf_cntrl_timer14_reg_set_offset = REG_GETF(RFCU_POWER, RF_CNTRL_TIMER_14_REG, - SET_OFFSET); - rf_cntrl_timer_7_reg_value = RFCU_POWER->RF_CNTRL_TIMER_7_REG; - rf_enable_config14_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG; - rf_enable_config15_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG; - rf_enable_config14_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG; - rf_enable_config15_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG; - rf_cal_ctrl_reg_value = RFCU->RF_CAL_CTRL_REG; - rf_mgain_ctrl_reg_value = PLLDIG->RF_MGAIN_CTRL_BLE_REG; - rf_mgain_ctrl2_reg_value = PLLDIG->RF_MGAIN_CTRL2_REG; - rf_synth_ctrl2_ble_reg_value = PLLDIG->RF_SYNTH_CTRL2_BLE_REG; - rf_synth_ctrl2_ftdf_reg_value = PLLDIG->RF_SYNTH_CTRL2_FTDF_REG; - rf_bmcw_reg_value = PLLDIG->RF_BMCW_REG; - rf_vcocal_ctrl_reg_value = PLLDIG->RF_VCOCAL_CTRL_REG; + // Store all the registers that will be changed in this function + rf_cntrl_timer14_reg_set_offset = REG_GETF(RFCU_POWER, RF_CNTRL_TIMER_14_REG, + SET_OFFSET); + rf_cntrl_timer_7_reg_value = RFCU_POWER->RF_CNTRL_TIMER_7_REG; + rf_enable_config14_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG; + rf_enable_config15_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG; + rf_enable_config14_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG; + rf_enable_config15_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG; + rf_cal_ctrl_reg_value = RFCU->RF_CAL_CTRL_REG; + rf_mgain_ctrl_reg_value = PLLDIG->RF_MGAIN_CTRL_BLE_REG; + rf_mgain_ctrl2_reg_value = PLLDIG->RF_MGAIN_CTRL2_REG; + rf_synth_ctrl2_ble_reg_value = PLLDIG->RF_SYNTH_CTRL2_BLE_REG; + rf_synth_ctrl2_ftdf_reg_value = PLLDIG->RF_SYNTH_CTRL2_FTDF_REG; + rf_bmcw_reg_value = PLLDIG->RF_BMCW_REG; + rf_vcocal_ctrl_reg_value = PLLDIG->RF_VCOCAL_CTRL_REG; - // move PLLCLOSED_EN to after PLL is in lock - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_7_REG, SET_OFFSET, - rf_cntrl_timer14_reg_set_offset + 150); + // move PLLCLOSED_EN to after PLL is in lock + REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_7_REG, SET_OFFSET, + rf_cntrl_timer14_reg_set_offset + 150); - // Disable PA and PA ramp. - RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG = 0x0000; + // Disable PA and PA ramp. + RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG = 0x0000; + RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG = 0x0000; + RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG = 0x0000; + RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG = 0x0000; - // Disable end-of-packet detection (not needed for the MGC) - REG_SET_BIT(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, EO_PACKET_DIS); + // Disable end-of-packet detection (not needed for the MGC) + REG_SET_BIT(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, EO_PACKET_DIS); - //Set modulator inversion + //Set modulator inversion // REG_CLR_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_SDM_POL); // Normal SDM polarity // REG_SET_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_DAC_POL); // Inverted DAC polarity - //Make sure that normal operation is selected. - REG_CLR_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); + //Make sure that normal operation is selected. + REG_CLR_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); - // Settings for modulation gain calibration - REG_SET_BIT(RFCU, RF_MGC_CTRL_REG, MGC_GAIN_SET); - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, 0x2); + // Settings for modulation gain calibration + REG_SET_BIT(RFCU, RF_MGC_CTRL_REG, MGC_GAIN_SET); + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, 0x2); - // invert the comparator value if mode bit is set to true. - if (!mode_ble) - { - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x2); // Set radio in FTDF mode - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - // Set length dependent on mode , JH-09-11-2015 - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 12); - // Need to set ModIndex value to 0x3F. - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, FTDF_MODINDEX, 0x3F); - } - else - { - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Set radio in BLE mode - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - // Set length dependent on mode , JH-09-11-2015 - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); - // Set modindex to 266kHz to improve df2/df1 , JH-09-17-2015 - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); + // invert the comparator value if mode bit is set to true. + if (!mode_ble) { + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x2); // Set radio in FTDF mode + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + // Set length dependent on mode , JH-09-11-2015 + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 12); + // Need to set ModIndex value to 0x3F. + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, FTDF_MODINDEX, 0x3F); + } else { + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Set radio in BLE mode + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + // Set length dependent on mode , JH-09-11-2015 + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); + // Set modindex to 266kHz to improve df2/df1 , JH-09-17-2015 + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); - // Start with a VCO coarse cal to find the calcap for mid channel - REG_SETF(PLLDIG, RF_BMCW_REG, CN_SEL, 1); - REG_SETF(PLLDIG, RF_BMCW_REG, CN_WR, 18); + // Start with a VCO coarse cal to find the calcap for mid channel + REG_SETF(PLLDIG, RF_BMCW_REG, CN_SEL, 1); + REG_SETF(PLLDIG, RF_BMCW_REG, CN_WR, 18); - // Disable all calibrations except the VCO coarse cal. - RFCU->RF_CAL_CTRL_REG = 0x001C; + // Disable all calibrations except the VCO coarse cal. + RFCU->RF_CAL_CTRL_REG = 0x001C; - // Clear eo-cal interrupt, such that new calibration can be stared + // Clear eo-cal interrupt, such that new calibration can be stared + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + // Wait until the VCO coarse calibration can be started + while ((RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL))) {} + + // Start the VCO coarse calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); + + // Wait until the VCO coarse calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} + + // Wait until the VCO coarse calibration is completed + while ((RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} + + // Clear eo_cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + calcap_mid = REG_GETF(PLLDIG, RF_SYNTH_RESULT_BLE_REG, VCO_FREQTRIM_RD); + REG_SETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_WR, + calcap_mid - REG_GETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL)); + + REG_SETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL, 2); // manual calcap + + } + + // Disable all calibrations except the modulation gain cal. + RFCU->RF_CAL_CTRL_REG = 0x0038; + + // Clear eo-cal interrupt, such that new calibration can be started RFCU->RF_IRQ_CTRL_REG = 0x0000; - // Wait until the VCO coarse calibration can be started - while ((RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL))) {} + // Wait until next calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - // Start the VCO coarse calibration + NVIC_ClearPendingIRQ(RFCAL_IRQn); + + // Start the modulation gain calibration REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - // Wait until the VCO coarse calibration has started + // Wait until the modulation gain calibration has started while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - - // Wait until the VCO coarse calibration is completed - while ((RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - - // Clear eo_cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - calcap_mid = REG_GETF(PLLDIG, RF_SYNTH_RESULT_BLE_REG, VCO_FREQTRIM_RD); - REG_SETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_WR, - calcap_mid - REG_GETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL)); - - REG_SETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL, 2); // manual calcap - - } - - // Disable all calibrations except the modulation gain cal. - RFCU->RF_CAL_CTRL_REG = 0x0038; - - // Clear eo-cal interrupt, such that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Wait until next calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - - NVIC_ClearPendingIRQ(RFCAL_IRQn); - - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} } #else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ static void hw_rf_modulation_gain_calibration_generic_start(mgc_mode_ctrl_e mode_ctrl, - int16_t average, int16_t mgain_mode, int16_t force, int16_t length) + int16_t average, int16_t mgain_mode, int16_t force, int16_t length) { - // Store all the registers that will be changed in this function - rf_cntrl_timer14_reg_set_offset = REG_GETF(RFCU_POWER, RF_CNTRL_TIMER_14_REG, - SET_OFFSET); - rf_cntrl_timer_7_reg_value = RFCU_POWER->RF_CNTRL_TIMER_7_REG; - rf_enable_config14_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_REG; - rf_enable_config15_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_REG; - rf_cal_ctrl_reg_value = RFCU->RF_CAL_CTRL_REG; - rf_mgain_ctrl_reg_value = PLLDIG->RF_MGAIN_CTRL_BLE_REG; - rf_mgain_ctrl2_reg_value = PLLDIG->RF_MGAIN_CTRL2_REG; - rf_synth_ctrl2_ble_reg_value = PLLDIG->RF_SYNTH_CTRL2_BLE_REG; - rf_synth_ctrl2_ftdf_reg_value = PLLDIG->RF_SYNTH_CTRL2_FTDF_REG; - rf_overrule_reg_value = RFCU->RF_OVERRULE_REG; - rf_enable_config23_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG; - rf_enable_config23_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG; - rf_enable_config45_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG; - rf_enable_config45_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG; + // Store all the registers that will be changed in this function + rf_cntrl_timer14_reg_set_offset = REG_GETF(RFCU_POWER, RF_CNTRL_TIMER_14_REG, + SET_OFFSET); + rf_cntrl_timer_7_reg_value = RFCU_POWER->RF_CNTRL_TIMER_7_REG; + rf_enable_config14_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_REG; + rf_enable_config15_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_REG; + rf_cal_ctrl_reg_value = RFCU->RF_CAL_CTRL_REG; + rf_mgain_ctrl_reg_value = PLLDIG->RF_MGAIN_CTRL_BLE_REG; + rf_mgain_ctrl2_reg_value = PLLDIG->RF_MGAIN_CTRL2_REG; + rf_synth_ctrl2_ble_reg_value = PLLDIG->RF_SYNTH_CTRL2_BLE_REG; + rf_synth_ctrl2_ftdf_reg_value = PLLDIG->RF_SYNTH_CTRL2_FTDF_REG; + rf_overrule_reg_value = RFCU->RF_OVERRULE_REG; + rf_enable_config23_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG; + rf_enable_config23_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG; + rf_enable_config45_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG; + rf_enable_config45_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG; - // move PLLCLOSED_EN to after PLL is in lock - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_7_REG, SET_OFFSET, - rf_cntrl_timer14_reg_set_offset + 150); + // move PLLCLOSED_EN to after PLL is in lock + REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_7_REG, SET_OFFSET, + rf_cntrl_timer14_reg_set_offset + 150); - // Disable PA and PA ramp. - RFCU_POWER->RF_ENABLE_CONFIG14_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG15_REG = 0x0000; + // Disable PA and PA ramp. + RFCU_POWER->RF_ENABLE_CONFIG14_REG = 0x0000; + RFCU_POWER->RF_ENABLE_CONFIG15_REG = 0x0000; - // Disable end-of-packet detection (not needed for the MGC) - REG_SET_BIT(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, EO_PACKET_DIS); + // Disable end-of-packet detection (not needed for the MGC) + REG_SET_BIT(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, EO_PACKET_DIS); - // Set Gain in Analog comparator to 1 - REG_SET_BIT(RFCU, RF_MGC_CTRL_REG, MGC_GAIN_SET); + // Set Gain in Analog comparator to 1 + REG_SET_BIT(RFCU, RF_MGC_CTRL_REG, MGC_GAIN_SET); - /* Set mode specific settings for BLE mode with GaussDAC */ - if (mode_ctrl == MGC_MODE_CTRL_BLE_GAUSSDAC) - { - /* Set radio in BLE mode */ - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); - /* Inversion of analog comparator signal */ - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + /* Set mode specific settings for BLE mode with GaussDAC */ + if (mode_ctrl == MGC_MODE_CTRL_BLE_GAUSSDAC) { + /* Set radio in BLE mode */ + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); + /* Inversion of analog comparator signal */ + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - if (force != -1) - { - /* Disable Gauss Gain override */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); + if (force != -1) { + /* Disable Gauss Gain override */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); + } + + if (average != -1) { + /* Set number of averaging */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); + } + + /* Setting number of zeros and ones */ + if (length == -1) { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); + } else { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, + length & 0x7f); + } + + /* Set modindex to 266kHz */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); + /* Select the GaussDac in BLE mode */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x0); + + if (mgain_mode != -1) { + /* Use the new algorithm */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); + } + + /* Disable TXDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x0); + /* Enable GaussDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x3); + /* Disable TX-DAC output selection */ + REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); + /* Enable GaussDAC output selection switch */ + REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); } - if (average != -1) - { - /* Set number of averaging */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); + /* Set mode specific settings for BLE mode with TXDAC */ + if (mode_ctrl == MGC_MODE_CTRL_BLE_TXDAC) { + /* Set radio in BLE mode */ + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); + /* Inversion of analog comparator signal */ + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + + if (force != -1) { + /* Disable Gauss Gain override */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); + } + + if (average != -1) { + /* Set number of averaging */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); + } + + /* Setting number of zeros and ones */ + if (length == -1) { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); + } else { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, + length & 0x7f); + } + + /* Set modindex to 250kHz */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x0); + /* Select the TXDAC in BLE mode */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x1); + + if (mgain_mode != -1) { + /* Use the new algorithm */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); + } + + /* Enable TXDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x3); + /* Disable GaussDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x0); + /* Select TX-DAC output selection */ + REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x2); + /* Unselect GaussDAC output selection switch */ + REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x1); } - /* Setting number of zeros and ones */ - if (length == -1) - { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); - } - else - { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, - length & 0x7f); + /* Set mode specific settings for FTDF mode */ + if (mode_ctrl == MGC_MODE_CTRL_FTDF) { + /* Set radio in FTDF mode */ + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x2); + /* Inversion of analog comparator signal */ + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + + if (force != -1) { + /* Disable Gauss Gain override */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); + } + + if (average != -1) { + /* Set number of averaging */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); + } + + /* Setting number of zeros and ones */ + if (length == -1) { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 16); + } else { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, + length & 0x7f); + } + + if (mgain_mode != -1) { + /* Use the new algorithm */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); + } + + /* Enable TXDAC in FTDF mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_FTDF_REG, txdac_en_ftdf_dcf_tx, 0x3); + /* Disable GaussDAC in FTDF mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_FTDF_REG, gauss_en_ftdf_dcf_tx, 0x0); + /* Select TX-DAC output selection */ + REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); + /* Unselect GaussDAC output selection switch */ + REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); } - /* Set modindex to 266kHz */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); - /* Select the GaussDac in BLE mode */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x0); + // Disable all calibrations except the modulation gain cal. + RFCU->RF_CAL_CTRL_REG = 0x0038; - if (mgain_mode != -1) - { - /* Use the new algorithm */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); - } + // Clear eo-cal interrupt, such that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; - /* Disable TXDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x0); - /* Enable GaussDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x3); - /* Disable TX-DAC output selection */ - REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); - /* Enable GaussDAC output selection switch */ - REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); - } + // Wait until next calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - /* Set mode specific settings for BLE mode with TXDAC */ - if (mode_ctrl == MGC_MODE_CTRL_BLE_TXDAC) - { - /* Set radio in BLE mode */ - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); - /* Inversion of analog comparator signal */ - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + NVIC_ClearPendingIRQ(RFCAL_IRQn); - if (force != -1) - { - /* Disable Gauss Gain override */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); - } + // Start the modulation gain calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - if (average != -1) - { - /* Set number of averaging */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); - } - - /* Setting number of zeros and ones */ - if (length == -1) - { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); - } - else - { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, - length & 0x7f); - } - - /* Set modindex to 250kHz */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x0); - /* Select the TXDAC in BLE mode */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x1); - - if (mgain_mode != -1) - { - /* Use the new algorithm */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); - } - - /* Enable TXDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x3); - /* Disable GaussDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x0); - /* Select TX-DAC output selection */ - REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x2); - /* Unselect GaussDAC output selection switch */ - REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x1); - } - - /* Set mode specific settings for FTDF mode */ - if (mode_ctrl == MGC_MODE_CTRL_FTDF) - { - /* Set radio in FTDF mode */ - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x2); - /* Inversion of analog comparator signal */ - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - - if (force != -1) - { - /* Disable Gauss Gain override */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); - } - - if (average != -1) - { - /* Set number of averaging */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); - } - - /* Setting number of zeros and ones */ - if (length == -1) - { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 16); - } - else - { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, - length & 0x7f); - } - - if (mgain_mode != -1) - { - /* Use the new algorithm */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); - } - - /* Enable TXDAC in FTDF mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_FTDF_REG, txdac_en_ftdf_dcf_tx, 0x3); - /* Disable GaussDAC in FTDF mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_FTDF_REG, gauss_en_ftdf_dcf_tx, 0x0); - /* Select TX-DAC output selection */ - REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); - /* Unselect GaussDAC output selection switch */ - REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); - } - - // Disable all calibrations except the modulation gain cal. - RFCU->RF_CAL_CTRL_REG = 0x0038; - - // Clear eo-cal interrupt, such that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Wait until next calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - - NVIC_ClearPendingIRQ(RFCAL_IRQn); - - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} + // Wait until the modulation gain calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} } static inline void hw_rf_modulation_gain_calibration_start(bool mode_ble) { - if (mode_ble) - { - hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_BLE_TXDAC, 2, 1, 0, 8); - } - else - { - hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_FTDF, 2, 1, 0, 8); - } + if (mode_ble) { + hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_BLE_TXDAC, 2, 1, 0, 8); + } else { + hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_FTDF, 2, 1, 0, 8); + } } #endif static void hw_rf_modulation_gain_calibration_end(void) { #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - uint32_t ch_cal, gg_cal, gg_ch_prod, kmoda_max, gg0, gg_th1, gg_th2; // MP-12-02-2016 - uint32_t kmoda_base; - uint32_t Y; - uint32_t tmp; - uint32_t dgain_kill_second_jump; - uint32_t dgain; + uint32_t ch_cal,gg_cal,gg_ch_prod,kmoda_max, gg0, gg_th1, gg_th2; // MP-12-02-2016 + uint32_t kmoda_base; + uint32_t Y; + uint32_t tmp; + uint32_t dgain_kill_second_jump; + uint32_t dgain; - if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) - && (CHIP_IS_AE))) - { - kmoda_base = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, - KMOD_ALPHA_BLE); - } + if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) + && (CHIP_IS_AE))) { + kmoda_base = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, + KMOD_ALPHA_BLE); + } - // Clear eo_cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Clear eo_cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; - ch_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT2_BLE_REG, CN_CAL_RD); - gg_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT_BLE_REG, GAUSS_GAIN_CAL_RD); + ch_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT2_BLE_REG, CN_CAL_RD); + gg_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT_BLE_REG, GAUSS_GAIN_CAL_RD); - gg0 = gg_cal + ((gg_cal * kmoda_base * ch_cal + 1024) >> 11); - gg_th1 = (gg_cal & 0xE0) + DF1_DAC_CHECK_VALUE; // gg_th1 = (gg_cal&0xE0)+32; - gg_th2 = (gg_th1 + DF1_DAC_CHECK_VALUE); // gg_th2 = (gg_th1+32); + gg0 = gg_cal + ((gg_cal*kmoda_base*ch_cal+1024)>>11); + gg_th1 = (gg_cal&0xE0) + DF1_DAC_CHECK_VALUE; // gg_th1 = (gg_cal&0xE0)+32; + gg_th2 = (gg_th1 + DF1_DAC_CHECK_VALUE); // gg_th2 = (gg_th1+32); - if (gg0 >= gg_th2) //so 2 jumps are on the left of the cal. channel - { - /* - Formula (MP): - Y = 1 + ((kmoda_base*ch_cal)/2048); - dgain_kill_second_jump = gg_cal - (gg_th2-1)/Y; + if (gg0 >= gg_th2) { //so 2 jumps are on the left of the cal. channel + /* + Formula (MP): + Y = 1 + ((kmoda_base*ch_cal)/2048); + dgain_kill_second_jump = gg_cal - (gg_th2-1)/Y; - Improve the resolution, - Y = 2048* + (kmoda_base*ch_cal); - dgain_kill_second_jump = gg_cal - (gg_th2-1)*2048/Y; - */ + Improve the resolution, + Y = 2048* + (kmoda_base*ch_cal); + dgain_kill_second_jump = gg_cal - (gg_th2-1)*2048/Y; + */ - Y = 2048 + (kmoda_base * ch_cal); - tmp = (((gg_th2 - 1) << 11) / Y); + Y = 2048 + (kmoda_base*ch_cal); + tmp = (((gg_th2-1)<<11)/Y); - if (gg_cal > tmp) //check to prevent negative value for dgain_kill_second_jump - { - dgain_kill_second_jump = gg_cal - tmp; + if (gg_cal > tmp) {//check to prevent negative value for dgain_kill_second_jump + dgain_kill_second_jump = gg_cal - tmp; - if (dgain_kill_second_jump <= DF1_DGAIN_THR1) - { + if (dgain_kill_second_jump <= DF1_DGAIN_THR1) { + dgain = DF1_DGAIN_THR1; + } else if (dgain_kill_second_jump >= DF1_DGAIN_THR2) { + dgain = DF1_DGAIN_THR2; // Should never end up here � but better to be safe than sorry. dgain_thr2 is default 16 + } else { + dgain = dgain_kill_second_jump; + } + } else { + dgain = 0; // End up here because something went wrong with the calculation of tmp! + } + + } else if (gg0 >= gg_th1) { dgain = DF1_DGAIN_THR1; - } - else if (dgain_kill_second_jump >= DF1_DGAIN_THR2) - { - dgain = DF1_DGAIN_THR2; // Should never end up here � but better to be safe than sorry. dgain_thr2 is default 16 - } - else - { - dgain = dgain_kill_second_jump; - } - } - else - { - dgain = 0; // End up here because something went wrong with the calculation of tmp! + } else { + dgain = DF1_DGAIN_THR0; } - } - else if (gg0 >= gg_th1) - { - dgain = DF1_DGAIN_THR1; - } - else - { - dgain = DF1_DGAIN_THR0; - } - - if (gg_cal > dgain) - { - gg_cal_modified = gg_cal - dgain; - } - else - { - gg_cal_modified = gg_cal; - } - - gg_ch_prod = (uint32_t)(gg_cal_modified * ch_cal); - - if (gg_ch_prod == 0) // Avoid HardFault due to division by 0 (not likely) - { - kmoda_cal = kmoda_base; - } - else - { - - kmoda_max = (255 * 2048 - 2048 * gg_cal_modified) / gg_ch_prod ; - - if (kmoda_max >= kmoda_base) - { - kmoda_cal = kmoda_base; + if (gg_cal>dgain) { + gg_cal_modified = gg_cal-dgain; + } else { + gg_cal_modified = gg_cal; } - else - { - kmoda_cal = kmoda_max; + + gg_ch_prod = (uint32_t) (gg_cal_modified * ch_cal); + + if (gg_ch_prod == 0) { // Avoid HardFault due to division by 0 (not likely) + kmoda_cal = kmoda_base; + } else { + + kmoda_max = (255*2048 - 2048 * gg_cal_modified) / gg_ch_prod ; + + if (kmoda_max >= kmoda_base) { + kmoda_cal = kmoda_base; + } else { + kmoda_cal = kmoda_max; + } } - } - // This should be done both here (to take effect after calib) AND after preferred settings - REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); + // This should be done both here (to take effect after calib) AND after preferred settings + REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); - //Restore the values of the registers that were changed in the function - //REG_SET_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_SDM_POL); // Inverted SDM polarity - //REG_CLR_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_DAC_POL); // Normal DAC polarity - RFCU_POWER->RF_CNTRL_TIMER_7_REG = rf_cntrl_timer_7_reg_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG = rf_enable_config14_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG = rf_enable_config14_ftdf_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG = rf_enable_config15_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG = rf_enable_config15_ftdf_reg_value; + //Restore the values of the registers that were changed in the function + //REG_SET_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_SDM_POL); // Inverted SDM polarity + //REG_CLR_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_DAC_POL); // Normal DAC polarity + RFCU_POWER->RF_CNTRL_TIMER_7_REG = rf_cntrl_timer_7_reg_value; + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG = rf_enable_config14_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG = rf_enable_config14_ftdf_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG = rf_enable_config15_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG = rf_enable_config15_ftdf_reg_value; - PLLDIG->RF_MGAIN_CTRL_BLE_REG = rf_mgain_ctrl_reg_value; - PLLDIG->RF_MGAIN_CTRL2_REG = rf_mgain_ctrl2_reg_value; - PLLDIG->RF_SYNTH_CTRL2_BLE_REG = rf_synth_ctrl2_ble_reg_value; - PLLDIG->RF_SYNTH_CTRL2_FTDF_REG = rf_synth_ctrl2_ftdf_reg_value; + PLLDIG->RF_MGAIN_CTRL_BLE_REG = rf_mgain_ctrl_reg_value; + PLLDIG->RF_MGAIN_CTRL2_REG = rf_mgain_ctrl2_reg_value; + PLLDIG->RF_SYNTH_CTRL2_BLE_REG = rf_synth_ctrl2_ble_reg_value; + PLLDIG->RF_SYNTH_CTRL2_FTDF_REG = rf_synth_ctrl2_ftdf_reg_value; - PLLDIG->RF_BMCW_REG = rf_bmcw_reg_value; // MP-12-02-2016 - PLLDIG->RF_VCOCAL_CTRL_REG = rf_vcocal_ctrl_reg_value; // MP-12-02-2016 + PLLDIG->RF_BMCW_REG = rf_bmcw_reg_value; // MP-12-02-2016 + PLLDIG->RF_VCOCAL_CTRL_REG = rf_vcocal_ctrl_reg_value; // MP-12-02-2016 - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); - // Disable overrule mode - RFCU->RF_OVERRULE_REG &= ~REG_MSK(RFCU, RF_OVERRULE_REG, RF_MODE_OVR); + // Disable overrule mode + RFCU->RF_OVERRULE_REG &= ~REG_MSK(RFCU, RF_OVERRULE_REG, RF_MODE_OVR); #else - // Clear eo_cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Clear eo_cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; - //Restore the values of the registers that were changed in the function - RFCU_POWER->RF_CNTRL_TIMER_7_REG = rf_cntrl_timer_7_reg_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG14_REG = rf_enable_config14_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG15_REG = rf_enable_config15_reg_value; - PLLDIG->RF_MGAIN_CTRL_BLE_REG = rf_mgain_ctrl_reg_value; - PLLDIG->RF_MGAIN_CTRL2_REG = rf_mgain_ctrl2_reg_value; - PLLDIG->RF_SYNTH_CTRL2_BLE_REG = rf_synth_ctrl2_ble_reg_value; - PLLDIG->RF_SYNTH_CTRL2_FTDF_REG = rf_synth_ctrl2_ftdf_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG = rf_enable_config23_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG = rf_enable_config23_ftdf_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG = rf_enable_config45_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG = rf_enable_config45_ftdf_reg_value; + //Restore the values of the registers that were changed in the function + RFCU_POWER->RF_CNTRL_TIMER_7_REG = rf_cntrl_timer_7_reg_value; + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG14_REG = rf_enable_config14_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG15_REG = rf_enable_config15_reg_value; + PLLDIG->RF_MGAIN_CTRL_BLE_REG = rf_mgain_ctrl_reg_value; + PLLDIG->RF_MGAIN_CTRL2_REG = rf_mgain_ctrl2_reg_value; + PLLDIG->RF_SYNTH_CTRL2_BLE_REG = rf_synth_ctrl2_ble_reg_value; + PLLDIG->RF_SYNTH_CTRL2_FTDF_REG = rf_synth_ctrl2_ftdf_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG = rf_enable_config23_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG = rf_enable_config23_ftdf_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG = rf_enable_config45_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG = rf_enable_config45_ftdf_reg_value; - // Disable overrule mode - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value; + // Disable overrule mode + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value; #endif } @@ -888,117 +832,126 @@ static void hw_rf_modulation_gain_calibration_end(void) */ void hw_rf_modulation_gain_calibration(bool mode_ble) { - /* Start the gain calibration */ - hw_rf_modulation_gain_calibration_start(mode_ble); + /* Start the gain calibration */ + hw_rf_modulation_gain_calibration_start(mode_ble); - // Wait until the modulation gain calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + // Wait until the modulation gain calibration is completed + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} - hw_rf_modulation_gain_calibration_end(); + hw_rf_modulation_gain_calibration_end(); } void hw_rf_dc_offset_calibration(void) { #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - // Save the values of registers that will be changed in the function - uint32_t RF_ENABLE_CONFIG0_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG; - uint32_t RF_ENABLE_CONFIG1_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG; - uint32_t RF_ENABLE_CONFIG2_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG; - uint32_t RF_ENABLE_CONFIG46_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; + // Save the values of registers that will be changed in the function + uint32_t RF_ENABLE_CONFIG0_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG; + uint32_t RF_ENABLE_CONFIG1_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG; + uint32_t RF_ENABLE_CONFIG2_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG; + uint32_t RF_ENABLE_CONFIG46_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; - uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; - uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; + uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; + uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; + uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = 0x0000; // Disable LNA_CGM - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC + // Required setting for the DC-offset calibration + RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = 0x0000; // Disable LNA_LDO + RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = 0x0000; // Disable LNA_CORE + RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = 0x0000; // Disable LNA_CGM + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC - // DCNGAIN = 3, DCNSTEP = 5, DCPARCAL_EN = 0, DCOFFSET_SEL = 0 - DEM->RF_DC_OFFSET_CTRL2_REG = 0x01D0; - // Disable all calibrations except the DC-offset cal. - RFCU->RF_CAL_CTRL_REG = 0x002C; + // DCNGAIN = 3, DCNSTEP = 5, DCPARCAL_EN = 0, DCOFFSET_SEL = 0 + DEM->RF_DC_OFFSET_CTRL2_REG = 0x01D0; + // Disable all calibrations except the DC-offset cal. + RFCU->RF_CAL_CTRL_REG = 0x002C; - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Overrule RF_MODE <- BLE_MODE + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Overrule RF_MODE <- BLE_MODE - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Clear eo-cal interrupt, so that new calibration can be stared + RFCU->RF_IRQ_CTRL_REG = 0x0000; - // Wait until the DC-offset calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} + // Wait until the DC-offset calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); + // Start the modulation gain calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} + // Wait until the modulation gain calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - // Wait until the modulation gain calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + // Wait until the modulation gain calibration is completed + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Clear eo-cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; - // Restore the values of registers that were changed in the function - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = RF_ENABLE_CONFIG0_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = RF_ENABLE_CONFIG1_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = RF_ENABLE_CONFIG2_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = RF_ENABLE_CONFIG46_BLE_REG_value; + // Restore the values of registers that were changed in the function + RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = RF_ENABLE_CONFIG0_BLE_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = RF_ENABLE_CONFIG1_BLE_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = RF_ENABLE_CONFIG2_BLE_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = RF_ENABLE_CONFIG46_BLE_REG_value; - DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; + DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; #else /* REV_B */ - // Save the values of registers that will be changed in the function - uint32_t RF_ENABLE_CONFIG0_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; - uint32_t RF_ENABLE_CONFIG1_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; - uint32_t RF_ENABLE_CONFIG2_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; + // Save the values of registers that will be changed in the function + uint32_t RF_ENABLE_CONFIG0_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; + uint32_t RF_ENABLE_CONFIG1_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; + uint32_t RF_ENABLE_CONFIG2_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; - uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; - uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; + uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; + uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; + uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM + uint32_t rf_enable_config46_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; + uint32_t rf_enable_config46_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG; - // DCNGAIN = 3, DCNSTEP = 5, DCPARCAL_EN = 0, DCOFFSET_SEL = 0 - DEM->RF_DC_OFFSET_CTRL2_REG = 0x01D0; - // Disable all calibrations except the DC-offset cal. - RFCU->RF_CAL_CTRL_REG = 0x002C; + // Required setting for the DC-offset calibration + RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO + RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE + RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Overrule RF_MODE <- BLE_MODE + // DCNGAIN = 3, DCNSTEP = 5, DCPARCAL_EN = 0, DCOFFSET_SEL = 0 + DEM->RF_DC_OFFSET_CTRL2_REG = 0x01D0; + // Disable all calibrations except the DC-offset cal. + RFCU->RF_CAL_CTRL_REG = 0x002C; - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; + RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = 0x0000; - // Wait until the DC-offset calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Overrule RF_MODE <- BLE_MODE - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); + // Clear eo-cal interrupt, so that new calibration can be stared + RFCU->RF_IRQ_CTRL_REG = 0x0000; - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} + // Wait until the DC-offset calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - // Wait until the modulation gain calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + // Start the modulation gain calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Wait until the modulation gain calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - // Restore the values of registers that were changed in the function - RFCU_POWER->RF_ENABLE_CONFIG0_REG = RF_ENABLE_CONFIG0_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG1_REG = RF_ENABLE_CONFIG1_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG2_REG = RF_ENABLE_CONFIG2_REG_value; + // Wait until the modulation gain calibration is completed + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + + // Clear eo-cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + // Restore the values of registers that were changed in the function + RFCU_POWER->RF_ENABLE_CONFIG0_REG = RF_ENABLE_CONFIG0_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG1_REG = RF_ENABLE_CONFIG1_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG2_REG = RF_ENABLE_CONFIG2_REG_value; + + DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = rf_enable_config46_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = rf_enable_config46_ftdf_reg_value; - DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; #endif } @@ -1007,399 +960,269 @@ void hw_rf_dc_offset_calibration(void) #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A bool hw_rf_iff_calibration(void) { - uint64_t start_time; + uint64_t start_time; - uint16_t calcap_result; + uint16_t calcap_result; - // Save the values of registers that will be changed in the function - uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; + // Save the values of registers that will be changed in the function + uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - // Configure the reference oscillator for the calibration - // 21-04-2015 : JH - Removed to use preferred settings instead - //uint16_t reg = RFCU->RF_REF_OSC_BLE_REG; - //REG_SET_FIELD(RFCU, RF_REF_OSC_BLE_REG, CNT_CLK, reg, 0xA6); - //REG_SET_FIELD(RFCU, RF_REF_OSC_BLE_REG, CNT_RO, reg, 0x2C); - //RFCU->RF_REF_OSC_BLE_REG = reg; - //reg = RFCU->RF_REF_OSC_FTDF_REG; - //REG_SET_FIELD(RFCU, RF_REF_OSC_FTDF_REG, CNT_CLK, reg, 0xA6); - //REG_SET_FIELD(RFCU, RF_REF_OSC_FTDF_REG, CNT_RO, reg, 0x2C); - //RFCU->RF_REF_OSC_FTDF_REG = reg; + // Configure the reference oscillator for the calibration + // 21-04-2015 : JH - Removed to use preferred settings instead + //uint16_t reg = RFCU->RF_REF_OSC_BLE_REG; + //REG_SET_FIELD(RFCU, RF_REF_OSC_BLE_REG, CNT_CLK, reg, 0xA6); + //REG_SET_FIELD(RFCU, RF_REF_OSC_BLE_REG, CNT_RO, reg, 0x2C); + //RFCU->RF_REF_OSC_BLE_REG = reg; + //reg = RFCU->RF_REF_OSC_FTDF_REG; + //REG_SET_FIELD(RFCU, RF_REF_OSC_FTDF_REG, CNT_CLK, reg, 0xA6); + //REG_SET_FIELD(RFCU, RF_REF_OSC_FTDF_REG, CNT_RO, reg, 0x2C); + //RFCU->RF_REF_OSC_FTDF_REG = reg; - // Save the values of registers that will be changed in the function - uint32_t RF_ENABLE_CONFIG0_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG; - uint32_t RF_ENABLE_CONFIG1_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG; - uint32_t RF_ENABLE_CONFIG2_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG; - uint32_t RF_ENABLE_CONFIG46_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; + // Save the values of registers that will be changed in the function + uint32_t RF_ENABLE_CONFIG0_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG; + uint32_t RF_ENABLE_CONFIG1_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG; + uint32_t RF_ENABLE_CONFIG2_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG; + uint32_t RF_ENABLE_CONFIG46_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = 0x0000; // Disable LNA_CGM - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC + // Required setting for the DC-offset calibration + RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = 0x0000; // Disable LNA_LDO + RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = 0x0000; // Disable LNA_CORE + RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = 0x0000; // Disable LNA_CGM + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC - // Disable all calibrations except the Iff cal. - RFCU->RF_CAL_CTRL_REG = 0x0034; - // Select the IF calcap to use the FSM value - REG_SET_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); + // Disable all calibrations except the Iff cal. + RFCU->RF_CAL_CTRL_REG = 0x0034; + // Select the IF calcap to use the FSM value + REG_SET_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Clear eo-cal interrupt, so that new calibration can be stared + RFCU->RF_IRQ_CTRL_REG = 0x0000; - start_time = hw_rf_get_start_iff_time(); + start_time = hw_rf_get_start_iff_time(); - // Wait until the IFF calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) - { - if (hw_rf_check_iff_timeout(start_time)) - { - /* IFF lockup detected. Abort */ - return false; + // Wait until the IFF calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) { + if (hw_rf_check_iff_timeout(start_time)) { + /* IFF lockup detected. Abort */ + return false; + } } - } - /* - * New code by SR 3/23/2016 - * (Disable partial calibration before IFF calibrations starts) - * - * Save current content of RF_DC_OFFSET_CTRl2_REG and set DCPARCAL_EN = 0 - * - */ - uint16_t rf_dc_offset_ctrl2_reg = DEM->RF_DC_OFFSET_CTRL2_REG; //GetWord16(RF_DC_OFFSET_CTRL2_REG); - REG_CLR_BIT(DEM, RF_DC_OFFSET_CTRL2_REG, DCPARCAL_EN); + /* + * New code by SR 3/23/2016 + * (Disable partial calibration before IFF calibrations starts) + * + * Save current content of RF_DC_OFFSET_CTRl2_REG and set DCPARCAL_EN = 0 + * + */ + uint16_t rf_dc_offset_ctrl2_reg = DEM->RF_DC_OFFSET_CTRL2_REG; //GetWord16(RF_DC_OFFSET_CTRL2_REG); + REG_CLR_BIT(DEM, RF_DC_OFFSET_CTRL2_REG, DCPARCAL_EN); - // Start the IFF calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); + // Start the IFF calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - // Wait until the IFF calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) - { - if (hw_rf_check_iff_timeout(start_time)) - { - /* IFF lockup detected. Abort */ - return false; + // Wait until the IFF calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) { + if (hw_rf_check_iff_timeout(start_time)) { + /* IFF lockup detected. Abort */ + return false; + } } - } - // Wait until the IFF calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) - { - if (hw_rf_check_iff_timeout(start_time)) - { - /* IFF lockup detected. Abort */ - return false; + // Wait until the IFF calibration is completed + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) { + if (hw_rf_check_iff_timeout(start_time)) { + /* IFF lockup detected. Abort */ + return false; + } } - } - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Clear eo-cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; - // Store the result to all IFF CC registers - calcap_result = RFCU->RF_IFF_CAL_CAP_STAT_REG; - RFCU->RF_IFF_CC_BLE_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_BLE_SET2_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; + // Store the result to all IFF CC registers + calcap_result = RFCU->RF_IFF_CAL_CAP_STAT_REG; + RFCU->RF_IFF_CC_BLE_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_BLE_SET2_REG = calcap_result; + RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; - // Restore the values of registers that were changed in the function - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - // De-select the IF calcap to use the FSM value - REG_CLR_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); + // Restore the values of registers that were changed in the function + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; + // De-select the IF calcap to use the FSM value + REG_CLR_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - /* - * New code by SR 3/23/2016 - * (Disable partial calibration before IFF calibrations starts) - * - * Restore RF_DC_OFFSET_CTRl2_REG - * - */ - DEM->RF_DC_OFFSET_CTRL2_REG = rf_dc_offset_ctrl2_reg; + /* + * New code by SR 3/23/2016 + * (Disable partial calibration before IFF calibrations starts) + * + * Restore RF_DC_OFFSET_CTRl2_REG + * + */ + DEM->RF_DC_OFFSET_CTRL2_REG = rf_dc_offset_ctrl2_reg; - // Restore the values of registers that were changed in the function - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = RF_ENABLE_CONFIG0_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = RF_ENABLE_CONFIG1_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = RF_ENABLE_CONFIG2_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = RF_ENABLE_CONFIG46_BLE_REG_value; - return true; + // Restore the values of registers that were changed in the function + RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = RF_ENABLE_CONFIG0_BLE_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = RF_ENABLE_CONFIG1_BLE_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = RF_ENABLE_CONFIG2_BLE_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = RF_ENABLE_CONFIG46_BLE_REG_value; + return true; } #else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ static bool iff_calib_internal(iff_mode_ovr_e rf_mode_ovr, iff_mode_ctrl_e mode_ctrl) { - uint16_t calcap_result; - uint64_t start_time; + uint16_t calcap_result; + uint64_t start_time; - // Set mode - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, rf_mode_ovr); + // Set mode + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, rf_mode_ovr); - // Disable all calibrations except the Iff cal. - RFCU->RF_CAL_CTRL_REG = 0x0034; + // Disable all calibrations except the Iff cal. + RFCU->RF_CAL_CTRL_REG = 0x0034; - // Select the IF calcap to use the FSM value - REG_SET_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); + // Select the IF calcap to use the FSM value + REG_SET_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; + // Clear eo-cal interrupt, so that new calibration can be stared + RFCU->RF_IRQ_CTRL_REG = 0x0000; - start_time = hw_rf_get_start_iff_time(); + start_time = hw_rf_get_start_iff_time(); - // Wait until the IFF calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) - { - if (hw_rf_check_iff_timeout(start_time)) - { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Start the IFF calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the IFF calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) - { - if (hw_rf_check_iff_timeout(start_time)) - { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Wait until the IFF calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) - { - if (hw_rf_check_iff_timeout(start_time)) - { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Store the result to all IFF CC BLE registers - calcap_result = RFCU->RF_IFF_CAL_CAP_STAT_REG; - - if (mode_ctrl != IFF_MODE_CTRL_COMBO || rf_mode_ovr == IFF_MODE_OVR_BLE) - { - RFCU->RF_IFF_CC_BLE_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_BLE_SET2_REG = calcap_result; - } - - switch (mode_ctrl) - { - case IFF_MODE_CTRL_BLE: // BLE - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result - 2; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result - 2; - break; - - case IFF_MODE_CTRL_FTDF: // FTDF - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result + 2; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result + 2; - break; - - case IFF_MODE_CTRL_COMBO: // COMBO - if (rf_mode_ovr == IFF_MODE_OVR_FTDF) - { - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; + // Wait until the IFF calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) { + if (hw_rf_check_iff_timeout(start_time)) { + /* IFF lockup detected. Abort */ + return false; + } } - break; - } + // Start the IFF calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - return true; + // Wait until the IFF calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) { + if (hw_rf_check_iff_timeout(start_time)) { + /* IFF lockup detected. Abort */ + return false; + } + } + + // Wait until the IFF calibration is completed + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) { + if (hw_rf_check_iff_timeout(start_time)) { + /* IFF lockup detected. Abort */ + return false; + } + } + + // Clear eo-cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + // Store the result to all IFF CC BLE registers + calcap_result = RFCU->RF_IFF_CAL_CAP_STAT_REG; + if (mode_ctrl != IFF_MODE_CTRL_COMBO || rf_mode_ovr == IFF_MODE_OVR_BLE) { + RFCU->RF_IFF_CC_BLE_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_BLE_SET2_REG = calcap_result; + } + + switch (mode_ctrl) { + case IFF_MODE_CTRL_BLE: // BLE + RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; + break; + case IFF_MODE_CTRL_FTDF: // FTDF + RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; + break; + case IFF_MODE_CTRL_COMBO: // COMBO + if (rf_mode_ovr == IFF_MODE_OVR_FTDF) { + RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; + } + break; + } + return true; } static bool hw_rf_iff_calibration(iff_mode_ctrl_e mode_ctrl) { - bool ret; + bool ret = false; - ////////////////////////////////////////////////////////////// - /// Capacitance calibration for different modes - /// mode_ctrl=0 : Calibration in BLE mode, use offsetted values in FTDF - /// mode_ctrl=1 : Calibration in FTDF mode, use offsetted values in BLE - /// mode_ctrl=2 : Calibration done in BLE mode and FTDF mode - ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + /// Capacitance calibration for different modes + /// mode_ctrl=0 : Calibration in BLE mode, use offsetted values in FTDF + /// mode_ctrl=1 : Calibration in FTDF mode, use offsetted values in BLE + /// mode_ctrl=2 : Calibration done in BLE mode and FTDF mode + ////////////////////////////////////////////////////////////// - // Save the values of registers that will be changed in the function - uint16_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - uint16_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; - uint16_t rf_enable_config0_reg_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; - uint16_t rf_enable_config1_reg_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; - uint16_t rf_enable_config2_reg_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; - uint16_t rf_enable_config46_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; - uint16_t rf_enable_config46_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG; - uint16_t rf_dc_offset_ctrl2_reg_value = DEM->RF_DC_OFFSET_CTRL2_REG; + // Save the values of registers that will be changed in the function + uint16_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; + uint16_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; + uint16_t rf_enable_config0_reg_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; + uint16_t rf_enable_config1_reg_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; + uint16_t rf_enable_config2_reg_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; + uint16_t rf_enable_config46_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; + uint16_t rf_enable_config46_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG; + uint16_t rf_dc_offset_ctrl2_reg_value = DEM->RF_DC_OFFSET_CTRL2_REG; - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC - RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = 0x0000; // Disable the DCF triggered Partial DCOC - REG_SETF(DEM, RF_DC_OFFSET_CTRL2_REG, DCPARCAL_EN, 0x0); + // Required setting for the DC-offset calibration + RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO + RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE + RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC + RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = 0x0000; // Disable the DCF triggered Partial DCOC + REG_SETF(DEM, RF_DC_OFFSET_CTRL2_REG, DCPARCAL_EN, 0x0); - switch (mode_ctrl) - { - case IFF_MODE_CTRL_BLE: // BLE - ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_BLE); - break; - - case IFF_MODE_CTRL_FTDF: // FTDF - ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_FTDF); - break; - - case IFF_MODE_CTRL_COMBO: // COMBO - ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_COMBO); - - if (!ret) - { - ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_COMBO); + switch (mode_ctrl) { + case IFF_MODE_CTRL_BLE: // BLE + ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_BLE); + break; + case IFF_MODE_CTRL_FTDF: // FTDF + ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_FTDF); + break; + case IFF_MODE_CTRL_COMBO: // COMBO + ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_COMBO); + if (ret) + ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_COMBO); + break; + default: + /* should never reach this point */ + ASSERT_WARNING(0); } - break; - } + if (!ret) + return false; - if (!ret) - { - return false; - } + // Restore the values of registers that were changed in the function + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; + RFCU_POWER->RF_ENABLE_CONFIG0_REG = rf_enable_config0_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG1_REG = rf_enable_config1_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG2_REG = rf_enable_config2_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = rf_enable_config46_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = rf_enable_config46_ftdf_reg_value; + DEM->RF_DC_OFFSET_CTRL2_REG = rf_dc_offset_ctrl2_reg_value; - // Restore the values of registers that were changed in the function - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; - RFCU_POWER->RF_ENABLE_CONFIG0_REG = rf_enable_config0_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG1_REG = rf_enable_config1_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG2_REG = rf_enable_config2_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = rf_enable_config46_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = rf_enable_config46_ftdf_reg_value; - DEM->RF_DC_OFFSET_CTRL2_REG = rf_dc_offset_ctrl2_reg_value; + // De-select the IF calcap to use the FSM value + REG_CLR_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - // De-select the IF calcap to use the FSM value - REG_CLR_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - - return true; + return true; } #endif bool hw_rf_calibration(void) { - bool iff_result; + bool iff_result; - GLOBAL_INT_DISABLE(); - hw_rf_dc_offset_calibration(); -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - iff_result = hw_rf_iff_calibration(); -#else -#if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) - iff_result = hw_rf_iff_calibration(0x2); -#elif defined(CONFIG_USE_BLE) - iff_result = hw_rf_iff_calibration(0x0); -#elif defined(CONFIG_USE_FTDF) - iff_result = hw_rf_iff_calibration(0x1); -#endif -#endif - - if (iff_result) - { -#ifdef CONFIG_USE_FTDF - hw_rf_modulation_gain_calibration(0); -#endif -#ifdef CONFIG_USE_BLE - hw_rf_modulation_gain_calibration(1); -#endif - } - - GLOBAL_INT_RESTORE(); - - return iff_result; -} - -void hw_rf_request_on(bool mode_ble) -{ - /* First RF requester. Switch it on */ - if (rf_request == 0) - { - if (rf_state == RF_ST_OFF) - { - hw_rf_poweron(); - rf_state = RF_ST_ON; -#if dg_configCOEX_ENABLE_CONFIG == 1 - hw_coex_apply_config(); -#endif - } - } - - if (mode_ble) - { - rf_request |= RF_REQUEST_BLE_ON; - } - else - { - rf_request |= RF_REQUEST_FTDF_ON; - } - -} - - -void hw_rf_request_off(bool mode_ble) -{ - if (mode_ble) - { - rf_request &= ~RF_REQUEST_BLE_ON; - } - else - { - rf_request &= ~RF_REQUEST_FTDF_ON; - } - - /* If not already off or during recalibration... */ - if (rf_state == RF_ST_ON || rf_state == RF_ST_CONFIG) - { - /* If not RF requesters remain, switch it off */ - if (rf_request == 0) - { - /* If user pre-off cb returns true, don't shutdown */ - if (hw_rf_preoff_cb() == false) - { - hw_rf_poweroff(); - rf_state = RF_ST_OFF; - } - } - } -} - - -bool hw_rf_start_calibration() -{ - bool iff_result; - - if (rf_state == RF_ST_CONFIG) - { - /* Call pre-calibration user cb */ - hw_rf_precalib_cb(); - - /* force RADIO_BUSY to BLE to 0 */ - REG_SETF(COEX, COEX_CTRL_REG, SEL_BLE_RADIO_BUSY, 1); - /* Ignore BLE/FTDF TX/RX_EN */ - REG_SET_BIT(COEX, COEX_CTRL_REG, IGNORE_BLE); - REG_SET_BIT(COEX, COEX_CTRL_REG, IGNORE_FTDF); - - /* Wait until DCFs have settled */ - while (REG_GETF(COEX, COEX_STAT_REG, COEX_RADIO_BUSY)); - - /* Perform DC offset calibration */ + GLOBAL_INT_DISABLE(); hw_rf_dc_offset_calibration(); - - /* Perform IFF calibration */ #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A iff_result = hw_rf_iff_calibration(); -#else /* BLACK_ORCA_IC_REV_B */ +#else #if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) iff_result = hw_rf_iff_calibration(0x2); #elif defined(CONFIG_USE_BLE) @@ -1408,186 +1231,275 @@ bool hw_rf_start_calibration() iff_result = hw_rf_iff_calibration(0x1); #endif #endif + if (iff_result) { +#ifdef CONFIG_USE_FTDF + hw_rf_modulation_gain_calibration(0); +#endif +#ifdef CONFIG_USE_BLE + hw_rf_modulation_gain_calibration(1); +#endif + } + GLOBAL_INT_RESTORE(); - if (iff_result == false) - { - return false; + return iff_result; +} + +void hw_rf_request_on(bool mode_ble) +{ + /* First RF requester. Switch it on */ + if (rf_request == 0) { + if (rf_state == RF_ST_OFF) { + hw_rf_poweron(); + rf_state = RF_ST_ON; +#if dg_configCOEX_ENABLE_CONFIG == 1 + hw_coex_apply_config(); +#endif + } } - NVIC_EnableIRQ(RFCAL_IRQn); + if (mode_ble) { + rf_request |= RF_REQUEST_BLE_ON; + } else { + rf_request |= RF_REQUEST_FTDF_ON; + } +} + + +void hw_rf_request_off(bool mode_ble) +{ + if (mode_ble) { + rf_request &= ~RF_REQUEST_BLE_ON; + } else { + rf_request &= ~RF_REQUEST_FTDF_ON; + } + + /* If not already off or during recalibration... */ + if (rf_state == RF_ST_ON || rf_state == RF_ST_CONFIG) { + /* If not RF requesters remain, switch it off */ + if (rf_request == 0) { + /* If user pre-off cb returns true, don't shutdown */ + if (hw_rf_preoff_cb() == false) { + hw_rf_poweroff(); + rf_state = RF_ST_OFF; + } + } + } +} + + +bool hw_rf_start_calibration() +{ + bool iff_result; + if (rf_state == RF_ST_CONFIG) { + /* Call pre-calibration user cb */ + hw_rf_precalib_cb(); + + /* force RADIO_BUSY to BLE to 0 */ + REG_SETF(COEX, COEX_CTRL_REG, SEL_BLE_RADIO_BUSY, 1); + /* Ignore BLE/FTDF TX/RX_EN */ + REG_SET_BIT(COEX, COEX_CTRL_REG, IGNORE_BLE); + REG_SET_BIT(COEX, COEX_CTRL_REG, IGNORE_FTDF); + + /* Wait until DCFs have settled */ + while (REG_GETF(COEX, COEX_STAT_REG, COEX_RADIO_BUSY)); + + /* Perform DC offset calibration */ + hw_rf_dc_offset_calibration(); + + /* Perform IFF calibration */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + iff_result = hw_rf_iff_calibration(); +#else /* BLACK_ORCA_IC_REV_B */ #if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) - /* Start the gain calibration, on ftdf mode */ - hw_rf_modulation_gain_calibration_start(0); - rf_state = RF_ST_WAIT_NEXT1; -#elif defined(CONFIG_USE_FTDF) - /* Start the gain calibration, on ftdf mode */ - hw_rf_modulation_gain_calibration_start(0); - rf_state = RF_ST_WAIT_NEXT2; + iff_result = hw_rf_iff_calibration(0x2); #elif defined(CONFIG_USE_BLE) - /* Start the gain calibration, on ble mode */ - hw_rf_modulation_gain_calibration_start(1); - rf_state = RF_ST_WAIT_NEXT2; + iff_result = hw_rf_iff_calibration(0x0); +#elif defined(CONFIG_USE_FTDF) + iff_result = hw_rf_iff_calibration(0x1); +#endif #endif - } + if (iff_result == false) { + return false; + } - return true; + NVIC_EnableIRQ(RFCAL_IRQn); + +#if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) + /* Start the gain calibration, on ftdf mode */ + hw_rf_modulation_gain_calibration_start(0); + rf_state = RF_ST_WAIT_NEXT1; +#elif defined(CONFIG_USE_FTDF) + /* Start the gain calibration, on ftdf mode */ + hw_rf_modulation_gain_calibration_start(0); + rf_state = RF_ST_WAIT_NEXT2; +#elif defined(CONFIG_USE_BLE) + /* Start the gain calibration, on ble mode */ + hw_rf_modulation_gain_calibration_start(1); + rf_state = RF_ST_WAIT_NEXT2; +#endif + + } + + return true; } void RFCAL_Handler(void) { - SEGGER_SYSTEMVIEW_ISR_ENTER(); + SEGGER_SYSTEMVIEW_ISR_ENTER(); - uint32_t iser; + uint32_t iser; - /* Interrupts must be disabled. However, some callbacks actually - * use FreeRTOS critical sections. To overcome this problem. use - * ISER/ICER to enable/disable interrupts - */ - GLOBAL_INT_DISABLE(); - iser = NVIC->ISER[0];; - NVIC->ICER[0] = iser; - GLOBAL_INT_RESTORE(); - - switch (rf_state) - { - case RF_ST_WAIT_NEXT1: - - /* FTDF gain calib (boot) completed. Proceed with ble gain - * calib + /* Interrupts must be disabled. However, some callbacks actually + * use FreeRTOS critical sections. To overcome this problem. use + * ISER/ICER to enable/disable interrupts */ - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + GLOBAL_INT_DISABLE(); + iser = NVIC->ISER[0];; + NVIC->ICER[0] = iser; + GLOBAL_INT_RESTORE(); - hw_rf_modulation_gain_calibration_end(); + switch (rf_state) { + case RF_ST_WAIT_NEXT1: + /* FTDF gain calib (boot) completed. Proceed with ble gain + * calib + */ + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + hw_rf_modulation_gain_calibration_end(); - /* Make sure RFCAL IRQ will be enabled when interrupts are enabled */ - iser |= ((uint32_t)(1 << RFCAL_IRQn)); + /* Make sure RFCAL IRQ will be enabled when interrupts are enabled */ + iser |= ((uint32_t)(1 << RFCAL_IRQn)); - /* Start the gain calibration, on ble mode */ - hw_rf_modulation_gain_calibration_start(1); + /* Start the gain calibration, on ble mode */ + hw_rf_modulation_gain_calibration_start(1); - rf_state = RF_ST_WAIT_NEXT2; - break; + rf_state = RF_ST_WAIT_NEXT2; + break; + case RF_ST_WAIT_NEXT2: + /* BLE (or ftdf) gain calib (boot) completed. + */ + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + hw_rf_modulation_gain_calibration_end(); - case RF_ST_WAIT_NEXT2: + /* Make sure RFCAL IRQ will be disabled when interrupts are enabled */ + iser &= ~((uint32_t)(1 << RFCAL_IRQn)); - /* BLE (or ftdf) gain calib (boot) completed. - */ - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + /* Restore state to normal BLE/FTDF MAC operation */ + REG_CLR_BIT(COEX, COEX_CTRL_REG, IGNORE_BLE); + REG_CLR_BIT(COEX, COEX_CTRL_REG, IGNORE_FTDF); + REG_SETF(COEX, COEX_CTRL_REG, SEL_BLE_RADIO_BUSY, 0); - hw_rf_modulation_gain_calibration_end(); + /* Calibration complete. */ + /* Call post-calibration user cb */ + hw_rf_postcalib_cb(); - /* Make sure RFCAL IRQ will be disabled when interrupts are enabled */ - iser &= ~((uint32_t)(1 << RFCAL_IRQn)); - - /* Restore state to normal BLE/FTDF MAC operation */ - REG_CLR_BIT(COEX, COEX_CTRL_REG, IGNORE_BLE); - REG_CLR_BIT(COEX, COEX_CTRL_REG, IGNORE_FTDF); - REG_SETF(COEX, COEX_CTRL_REG, SEL_BLE_RADIO_BUSY, 0); - - /* Calibration complete. */ - /* Call post-calibration user cb */ - hw_rf_postcalib_cb(); - - /* Check if RF is still needed on, - * otherwise, switch it off - */ - if (rf_request == 0) - { - hw_rf_poweroff(); - rf_state = RF_ST_OFF; - } - else - { - rf_state = RF_ST_CONFIG; - hw_rf_postconf_cb(); + /* Check if RF is still needed on, + * otherwise, switch it off + */ + if (rf_request == 0) { + hw_rf_poweroff(); + rf_state = RF_ST_OFF; + } else { + rf_state = RF_ST_CONFIG; + hw_rf_postconf_cb(); + } + break; + default: + break; } - break; + /* Re-enable interrupts */ + NVIC->ISER[0] = iser; - default: - break; - } - - /* Re-enable interrupts */ - NVIC->ISER[0] = iser; - - SEGGER_SYSTEMVIEW_ISR_EXIT(); + SEGGER_SYSTEMVIEW_ISR_EXIT(); } void hw_rf_request_recommended_settings(void) { - if (rf_state == RF_ST_ON) - { - hw_rf_apply_tcs_cb(); - hw_rf_set_recommended_settings(); + if (rf_state == RF_ST_ON) { + hw_rf_apply_tcs_cb(); + hw_rf_set_recommended_settings(); - /* Initialize TX Power LUTs */ + /* Initialize TX Power LUTs */ #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - hw_rf_set_tx_power(rf_tx_power_luts.tx_power_ble); + hw_rf_set_tx_power(rf_tx_power_luts.tx_power_ble); #else #ifdef CONFIG_USE_BLE - hw_rf_set_tx_power_ble(rf_tx_power_luts.tx_power_ble); + hw_rf_set_tx_power_ble(rf_tx_power_luts.tx_power_ble); #endif #ifdef CONFIG_USE_FTDF - hw_rf_set_tx_power_ftdf(rf_tx_power_luts.tx_power_ftdf); + hw_rf_set_tx_power_ftdf(rf_tx_power_luts.tx_power_ftdf); #endif #endif - rf_state = RF_ST_CONFIG; - hw_rf_postconf_cb(); - } + rf_state = RF_ST_CONFIG; + hw_rf_postconf_cb(); + } } bool __attribute__((weak)) hw_rf_preoff_cb(void) { - return false; + return false; } void hw_rf_start_continuous_wave(uint8_t mode, uint8_t ch) { - REG_SETF(RFCU, RF_OVERRULE_REG, TX_EN_OVR, 1); // disable TX overrule - REG_SETF(RFCU, RF_OVERRULE_REG, TX_EN_OVR, 0); // NORMAL TX + REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 1); // disable TX overrule + REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 0); // NORMAL TX - REG_SETF(PLLDIG, RF_BMCW_REG, CN_SEL, 1); - REG_SETF(PLLDIG, RF_BMCW_REG, CN_WR, ch); + REG_SETF(PLLDIG,RF_BMCW_REG, CN_SEL, 1); + REG_SETF(PLLDIG,RF_BMCW_REG, CN_WR, ch); - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, mode); - REG_SETF(RFCU, RF_OVERRULE_REG, TX_EN_OVR, 2); // OVERRULE TX ENABLED + REG_SETF(RFCU,RF_OVERRULE_REG, RF_MODE_OVR, mode); + REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 2); // OVERRULE TX ENABLED +} + +void hw_rf_start_continuous_wave_rx(uint8_t mode, uint8_t ch) +{ + REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 1); // disable RX overrule + REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 0); // NORMAL RX + + REG_SETF(PLLDIG,RF_BMCW_REG, CN_SEL, 1); + REG_SETF(PLLDIG,RF_BMCW_REG, CN_WR, ch); + + REG_SETF(RFCU,RF_OVERRULE_REG, RF_MODE_OVR, mode); // BLE MODE + REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 2); // OVERRULE RX ENABLED } void hw_rf_stop_continuous_wave(void) { - REG_SETF(PLLDIG, RF_BMCW_REG, CN_SEL, 0); - REG_SETF(PLLDIG, RF_BMCW_REG, CN_WR, 0); + REG_SETF(PLLDIG,RF_BMCW_REG, CN_SEL, 0); + REG_SETF(PLLDIG,RF_BMCW_REG, CN_WR, 0); - REG_SETF(RFCU, RF_OVERRULE_REG, TX_EN_OVR, 1); // disable TX overrule - REG_SETF(RFCU, RF_OVERRULE_REG, TX_EN_OVR, 0); // NORMAL TX - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0); // NORMAL RF mode, so disable BLE mode + REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 1); // disable TX overrule + REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 0); // NORMAL TX + REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 1); // disable RX overrule + REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 0); // NORMAL RX + REG_SETF(RFCU,RF_OVERRULE_REG, RF_MODE_OVR, 0); // NORMAL RF mode, so disable BLE mode } #if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A void hw_rf_set_tx_power(HW_RF_PWR_LUT_SETTING lut) { - RFCU->RF_TX_PWR_REG = lut; - rf_tx_power_luts.tx_power_ble = lut; + RFCU->RF_TX_PWR_REG = lut; + rf_tx_power_luts.tx_power_ble = lut; } #else #ifdef CONFIG_USE_BLE void hw_rf_set_tx_power_ble(HW_RF_PWR_LUT_SETTING lut) { - RFCU->RF_TX_PWR_BLE_REG = lut; - rf_tx_power_luts.tx_power_ble = lut; + RFCU->RF_TX_PWR_BLE_REG = lut; + rf_tx_power_luts.tx_power_ble = lut; } #endif #ifdef CONFIG_USE_FTDF void hw_rf_set_tx_power_ftdf(HW_RF_PWR_LUT_SETTING lut) { - RFCU->RF_TX_PWR_FTDF_REG = lut; - rf_tx_power_luts.tx_power_ftdf = lut; + RFCU->RF_TX_PWR_FTDF_REG = lut; + rf_tx_power_luts.tx_power_ftdf = lut; } #endif diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c index 17cff4b7c..9bac6479b 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c @@ -60,58 +60,58 @@ static hw_timer0_interrupt_cb intr_cb; void hw_timer0_init(const timer0_config *cfg) { - /* Enable clock for peripheral */ - uint32_t clk_tmr_reg = CRG_TOP->CLK_TMR_REG; - clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk; - clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk; - clk_tmr_reg |= CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk; - CRG_TOP->CLK_TMR_REG = clk_tmr_reg ; + /* Enable clock for peripheral */ + GLOBAL_INT_DISABLE(); + uint32_t clk_tmr_reg = CRG_TOP->CLK_TMR_REG; + clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk; + clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk; + clk_tmr_reg |= CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk; + CRG_TOP->CLK_TMR_REG = clk_tmr_reg ; + GLOBAL_INT_RESTORE(); - /* Reset control register, i.e. disable timer */ - GP_TIMERS->TIMER0_CTRL_REG = 0x0; + /* Reset control register, i.e. disable timer */ + GP_TIMERS->TIMER0_CTRL_REG = 0x0; - /* Disable NVIC interrupt */ - NVIC_DisableIRQ(SWTIM0_IRQn); + /* Disable NVIC interrupt */ + NVIC_DisableIRQ(SWTIM0_IRQn); - intr_cb = NULL; + intr_cb = NULL; - hw_timer0_configure(cfg); + hw_timer0_configure(cfg); } void hw_timer0_configure(const timer0_config *cfg) { - if (cfg) - { - hw_timer0_set_clock_source(cfg->clk_src); - hw_timer0_set_fast_clock_div(cfg->fast_clk_div); - hw_timer0_set_on_clock_div(cfg->on_clock_div); - hw_timer0_set_on_reload(cfg->on_reload); - hw_timer0_set_t0_reload(cfg->t0_reload_m, cfg->t0_reload_n); - } + if (cfg) { + hw_timer0_set_clock_source(cfg->clk_src); + hw_timer0_set_fast_clock_div(cfg->fast_clk_div); + hw_timer0_set_on_clock_div(cfg->on_clock_div); + hw_timer0_set_on_reload(cfg->on_reload); + hw_timer0_set_t0_reload(cfg->t0_reload_m, cfg->t0_reload_n); + } } void hw_timer0_register_int(hw_timer0_interrupt_cb handler) { - intr_cb = handler; - NVIC_EnableIRQ(SWTIM0_IRQn); + intr_cb = handler; + NVIC_EnableIRQ(SWTIM0_IRQn); } void hw_timer0_unregister_int(void) { - NVIC_DisableIRQ(SWTIM0_IRQn); - intr_cb = NULL; + NVIC_DisableIRQ(SWTIM0_IRQn); + intr_cb = NULL; } void SWTIM0_Handler(void) { - SEGGER_SYSTEMVIEW_ISR_ENTER(); + SEGGER_SYSTEMVIEW_ISR_ENTER(); - if (intr_cb) - { - intr_cb(); - } + if (intr_cb) { + intr_cb(); + } - SEGGER_SYSTEMVIEW_ISR_EXIT(); + SEGGER_SYSTEMVIEW_ISR_EXIT(); } #endif /* dg_configUSE_HW_TIMER0 */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c index 253deca7a..a8510eede 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c @@ -50,82 +50,76 @@ static hw_trng_cb trng_cb; void hw_trng_disable_clk(void) { - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); - GLOBAL_INT_RESTORE(); + GLOBAL_INT_DISABLE(); + REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); + GLOBAL_INT_RESTORE(); } void hw_trng_clear_pending(void) { - uint32_t dummy __attribute__((unused)); - /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ - dummy = TRNG->TRNG_FIFOLVL_REG; - NVIC_ClearPendingIRQ(TRNG_IRQn); + uint32_t dummy __attribute__((unused)); + /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ + dummy = TRNG->TRNG_FIFOLVL_REG; + NVIC_ClearPendingIRQ(TRNG_IRQn); } void hw_trng_enable(hw_trng_cb callback) { - if (callback != NULL) - { - trng_cb = callback; - hw_trng_clear_pending(); - NVIC_EnableIRQ(TRNG_IRQn); - } + if (callback != NULL) { + trng_cb = callback; + hw_trng_clear_pending(); + NVIC_EnableIRQ(TRNG_IRQn); + } - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); - GLOBAL_INT_RESTORE(); - REG_SET_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); + GLOBAL_INT_RESTORE(); + REG_SET_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); } -void hw_trng_get_numbers(uint32_t *buffer, uint8_t size) +void hw_trng_get_numbers(uint32_t* buffer, uint8_t size) { - if (size > HW_TRNG_FIFO_DEPTH) - { - size = HW_TRNG_FIFO_DEPTH; - } + if (size > HW_TRNG_FIFO_DEPTH) + size = HW_TRNG_FIFO_DEPTH; - for (int i = 0; i < size ; i++) - { - buffer[i] = hw_trng_get_number(); - } + for (int i = 0; i < size ; i++) { + buffer[i] = hw_trng_get_number(); + } } __RETAINED_CODE uint8_t hw_trng_get_fifo_level(void) { - return (TRNG->TRNG_FIFOLVL_REG) & (REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOLVL) | - REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOFULL)); + return (TRNG->TRNG_FIFOLVL_REG) & (REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOLVL) | + REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOFULL)); } void hw_trng_disable_interrupt(void) { - NVIC_DisableIRQ(TRNG_IRQn); - trng_cb = NULL; + NVIC_DisableIRQ(TRNG_IRQn); + trng_cb = NULL; } void hw_trng_disable(void) { - hw_trng_stop(); - hw_trng_disable_interrupt(); - hw_trng_clear_pending(); - hw_trng_disable_clk(); + hw_trng_stop(); + hw_trng_disable_interrupt(); + hw_trng_clear_pending(); + hw_trng_disable_clk(); } void TRNG_Handler(void) { - uint32_t dummy __attribute__((unused)); + uint32_t dummy __attribute__((unused)); - SEGGER_SYSTEMVIEW_ISR_ENTER(); + SEGGER_SYSTEMVIEW_ISR_ENTER(); - if (trng_cb != NULL) - { - trng_cb(); - } + if (trng_cb != NULL) + trng_cb(); - /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ - dummy = TRNG->TRNG_FIFOLVL_REG; + /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ + dummy = TRNG->TRNG_FIFOLVL_REG; - SEGGER_SYSTEMVIEW_ISR_EXIT(); + SEGGER_SYSTEMVIEW_ISR_EXIT(); } #endif /* dg_configUSE_HW_TRNG */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c index c10efde77..b08bded9a 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c @@ -107,47 +107,67 @@ __RETAINED static uint8_t uart2_rx_dma_buf[dg_configUART2_RX_CIRCULAR_DMA_BUF_SI #endif /* dg_configUART_RX_CIRCULAR_DMA */ -typedef struct -{ +typedef struct { #ifdef HW_UART_ENABLE_USER_ISR - hw_uart_interrupt_isr user_isr; + hw_uart_interrupt_isr user_isr; #endif - const uint8_t *tx_buffer; - void *tx_user_data; - hw_uart_tx_callback tx_cb; - uint16_t tx_len; - uint16_t tx_ix; + const uint8_t *tx_buffer; + void *tx_user_data; + hw_uart_tx_callback tx_cb; + uint16_t tx_len; + uint16_t tx_ix; - void *rx_user_data; - uint8_t *rx_buffer; - hw_uart_rx_callback rx_cb; - uint16_t rx_len; - uint16_t rx_ix; + void *rx_user_data; + uint8_t *rx_buffer; + hw_uart_rx_callback rx_cb; + uint16_t rx_len; + uint16_t rx_ix; - uint8_t tx_fifo_on: 1; - uint8_t rx_fifo_on: 1; - uint8_t tx_fifo_level: 2; - uint8_t rx_fifo_level: 2; + uint8_t tx_fifo_on:1; + uint8_t rx_fifo_on:1; + uint8_t tx_fifo_level:2; + uint8_t rx_fifo_level:2; #if dg_configUART_SOFTWARE_FIFO - uint8_t *rx_soft_fifo; - fifo_size_t rx_soft_fifo_size; - fifo_ptr_t rx_soft_fifo_rd_ptr; - fifo_ptr_t rx_soft_fifo_wr_ptr; + uint8_t *rx_soft_fifo; + fifo_size_t rx_soft_fifo_size; + fifo_ptr_t rx_soft_fifo_rd_ptr; + fifo_ptr_t rx_soft_fifo_wr_ptr; #endif #if HW_UART_USE_DMA_SUPPORT - uint8_t use_dma: 1; - DMA_setup tx_dma; - DMA_setup rx_dma; + uint8_t use_dma:1; + DMA_setup tx_dma; + DMA_setup rx_dma; #if dg_configUART_RX_CIRCULAR_DMA - bool rx_dma_active; - uint8_t *rx_dma_buf; - uint16_t rx_dma_buf_size; - uint16_t rx_dma_head; + bool rx_dma_active; + uint8_t *rx_dma_buf; + uint16_t rx_dma_buf_size; + uint16_t rx_dma_head; #endif /* dg_configUART_RX_CIRCULAR_DMA */ #endif /* HW_UART_USE_DMA_SUPPORT */ } UART_Data; -__RETAINED_RW static UART_Data uart_data[2]; +__RETAINED_RW static UART_Data uart_data[2] = { + { +#if dg_configUART_SOFTWARE_FIFO + .rx_soft_fifo = uart1_sw_fifo, + .rx_soft_fifo_size = dg_configUART1_SOFTWARE_FIFO_SIZE, +#endif +#if dg_configUART_RX_CIRCULAR_DMA + .rx_dma_buf = uart1_rx_dma_buf, + .rx_dma_buf_size = dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE, +#endif + }, + { +#if dg_configUART_SOFTWARE_FIFO + .rx_soft_fifo = uart2_sw_fifo, + .rx_soft_fifo_size = dg_configUART2_SOFTWARE_FIFO_SIZE, +#endif +#if dg_configUART_RX_CIRCULAR_DMA + .rx_dma_buf = uart2_rx_dma_buf, + .rx_dma_buf_size = dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE, +#endif + }, +}; #define UART_INT(id) ((id) == HW_UART1 ? (UART_IRQn) : (UART2_IRQn)) #define UARTIX(id) ((id) == HW_UART1 ? 0 : 1) @@ -157,7 +177,7 @@ __RETAINED_RW static UART_Data uart_data[2]; #ifdef HW_UART_ENABLE_USER_ISR void hw_uart_set_isr(HW_UART_ID uart, hw_uart_interrupt_isr isr) { - uart_data[UARTIX(uart)].user_isr = isr; + uart_data[UARTIX(uart)].user_isr = isr; } #endif @@ -165,81 +185,75 @@ void hw_uart_set_isr(HW_UART_ID uart, hw_uart_interrupt_isr isr) uint8_t hw_uart_read(HW_UART_ID uart) { - // Wait until received data are available - while (hw_uart_read_buf_empty(uart)); + // Wait until received data are available + while (hw_uart_read_buf_empty(uart)); - // Read element from the receive FIFO - return UBA(uart)->UART2_RBR_THR_DLL_REG; + // Read element from the receive FIFO + return UBA(uart)->UART2_RBR_THR_DLL_REG; } void hw_uart_write(HW_UART_ID uart, uint8_t data) { - // Wait if Transmit Holding Register is full - while (hw_uart_write_buf_full(uart)); + // Wait if Transmit Holding Register is full + while (hw_uart_write_buf_full(uart)); - // Write data to the transmit FIFO - UBA(uart)->UART2_RBR_THR_DLL_REG = data; + // Write data to the transmit FIFO + UBA(uart)->UART2_RBR_THR_DLL_REG = data; } void hw_uart_write_buffer(HW_UART_ID uart, const void *data, uint16_t len) { - const uint8_t *p = data; + const uint8_t *p = data; - while (len > 0) - { - hw_uart_write(uart, *p++); - len--; - } + while (len > 0) { + hw_uart_write(uart, *p++); + len--; + } } void hw_uart_send(HW_UART_ID uart, const void *data, uint16_t len, hw_uart_tx_callback cb, - void *user_data) + void *user_data) { - UART_Data *ud = &uart_data[UARTIX(uart)]; + UART_Data *ud = &uart_data[UARTIX(uart)]; - if (cb == NULL) - { - hw_uart_write_buffer(uart, data, len); + if (cb == NULL) { + hw_uart_write_buffer(uart, data, len); + ud->tx_ix = 0; + ud->tx_len = 0; + return; + } + ud->tx_buffer = data; + ud->tx_user_data = user_data; + ud->tx_len = len; ud->tx_ix = 0; - ud->tx_len = 0; - return; - } - - ud->tx_buffer = data; - ud->tx_user_data = user_data; - ud->tx_len = len; - ud->tx_ix = 0; - ud->tx_cb = cb; + ud->tx_cb = cb; #if HW_UART_USE_DMA_SUPPORT - - if (ud->tx_dma.channel_number != HW_DMA_CHANNEL_INVALID && len > 1) - { - ud->tx_dma.src_address = (uint32) data; - ud->tx_dma.length = len; - // DMA requested - hw_uart_clear_dma_request(uart); - hw_dma_channel_initialization(&ud->tx_dma); - hw_dma_channel_enable(ud->tx_dma.channel_number, HW_DMA_STATE_ENABLED); - return; - } - + if (ud->tx_dma.channel_number != HW_DMA_CHANNEL_INVALID && len > 1) { + ud->tx_dma.src_address = (uint32) data; + ud->tx_dma.length = len; + // DMA requested + hw_uart_clear_dma_request(uart); + hw_dma_channel_initialization(&ud->tx_dma); + hw_dma_channel_enable(ud->tx_dma.channel_number, HW_DMA_STATE_ENABLED); + return; + } #endif - // Interrupt driven - NVIC_DisableIRQ(UART_INT(uart)); - // Enable transmit interrupts - uint16_t ier_dlh_reg = UBA(uart)->UART2_IER_DLH_REG; - ier_dlh_reg |= ((1 << UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos) | (1 << UART_UART_IER_DLH_REG_PTIME_dlh7_Pos)); - UBA(uart)->UART2_IER_DLH_REG = ier_dlh_reg; + // Interrupt driven + NVIC_DisableIRQ(UART_INT(uart)); + // Enable transmit interrupts + uint16_t ier_dlh_reg = UBA(uart)->UART2_IER_DLH_REG; + ier_dlh_reg |= ((1 << UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos) | (1 << UART_UART_IER_DLH_REG_PTIME_dlh7_Pos)); + UBA(uart)->UART2_IER_DLH_REG = ier_dlh_reg; - NVIC_EnableIRQ(UART_INT(uart)); + NVIC_EnableIRQ(UART_INT(uart)); } static inline void hw_uart_enable_rx_int(HW_UART_ID uart, bool enable) { - NVIC_DisableIRQ(UART_INT(uart)); - HW_UART_REG_SETF(uart, IER_DLH, ERBFI_dlh0, enable); - NVIC_EnableIRQ(UART_INT(uart)); + NVIC_DisableIRQ(UART_INT(uart)); + HW_UART_REG_SETF(uart, IER_DLH, ERBFI_dlh0, enable); + NVIC_EnableIRQ(UART_INT(uart)); } #if dg_configUART_SOFTWARE_FIFO @@ -254,131 +268,122 @@ static inline void hw_uart_enable_rx_int(HW_UART_ID uart, bool enable) */ static bool hw_uart_drain_rx(HW_UART_ID uart, UART_Data *ud, int len) { - /* - * This function is called with RX interrupt disabled. - * - * Get current software FIFO pointers before enabling interrupt again. - * ud->rx_len is still set to 0, so interrupt will not try to copy data to - * application buffer till all data from software FIFO is drained to user buffer. - */ - fifo_ptr_t rd_ptr = ud->rx_soft_fifo_rd_ptr; - fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr; - int idx = 0; + /* + * This function is called with RX interrupt disabled. + * + * Get current software FIFO pointers before enabling interrupt again. + * ud->rx_len is still set to 0, so interrupt will not try to copy data to + * application buffer till all data from software FIFO is drained to user buffer. + */ + fifo_ptr_t rd_ptr = ud->rx_soft_fifo_rd_ptr; + fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr; + int idx = 0; - /* - * ud->rx_ix is 0, set ud->rx_len to 0 to prevent interrupt from using it - * before all data from software FIFO is moved to application buffer. - */ - ud->rx_len = 0; + /* + * ud->rx_ix is 0, set ud->rx_len to 0 to prevent interrupt from using it + * before all data from software FIFO is moved to application buffer. + */ + ud->rx_len = 0; - hw_uart_enable_rx_int(uart, true); + hw_uart_enable_rx_int(uart, true); - while (idx < len) - { + while (idx < len) { - if (wr_ptr == rd_ptr) - { - /* - * No more data in software FIFO, at least from state before - * interrupt was enabled. - * Disable interrupt and update read pointer to reflect position - * of already copied data. - */ - hw_uart_enable_rx_int(uart, false); - ud->rx_soft_fifo_rd_ptr = rd_ptr; + if (wr_ptr == rd_ptr) { + /* + * No more data in software FIFO, at least from state before + * interrupt was enabled. + * Disable interrupt and update read pointer to reflect position + * of already copied data. + */ + hw_uart_enable_rx_int(uart, false); + ud->rx_soft_fifo_rd_ptr = rd_ptr; - /* - * Check if write pointer moved, if so interrupt put some more data - * in buffer. Remember current write position and try again with - * interrupts enabled. - */ - if (ud->rx_soft_fifo_wr_ptr != wr_ptr) - { - wr_ptr = ud->rx_soft_fifo_wr_ptr; - hw_uart_enable_rx_int(uart, true); - continue; - } + /* + * Check if write pointer moved, if so interrupt put some more data + * in buffer. Remember current write position and try again with + * interrupts enabled. + */ + if (ud->rx_soft_fifo_wr_ptr != wr_ptr) { + wr_ptr = ud->rx_soft_fifo_wr_ptr; + hw_uart_enable_rx_int(uart, true); + continue; + } - /* - * All was copied from software FIFO. - * Setup user transaction ix and len so when interrupts are enabled - * again (not in this function) interrupt or DMA can continue. - */ - ud->rx_ix = idx; - ud->rx_len = len; + /* + * All was copied from software FIFO. + * Setup user transaction ix and len so when interrupts are enabled + * again (not in this function) interrupt or DMA can continue. + */ + ud->rx_ix = idx; + ud->rx_len = len; - return false; + return false; + } + + /* Copy from software FIFO to user provided buffer */ + ud->rx_buffer[idx++] = ud->rx_soft_fifo[rd_ptr++]; + + if (rd_ptr >= ud->rx_soft_fifo_size) { + rd_ptr = 0; + } } - /* Copy from software FIFO to user provided buffer */ - ud->rx_buffer[idx++] = ud->rx_soft_fifo[rd_ptr++]; + /* + * User buffer is filled, block interrupt so end of transmission callback will not be + * called from interrupt. + */ + hw_uart_enable_rx_int(uart, false); + ud->rx_soft_fifo_rd_ptr = rd_ptr; + ud->rx_len = len; + ud->rx_ix = len; - if (rd_ptr >= ud->rx_soft_fifo_size) - { - rd_ptr = 0; - } - } - - /* - * User buffer is filled, block interrupt so end of transmission callback will not be - * called from interrupt. - */ - hw_uart_enable_rx_int(uart, false); - ud->rx_soft_fifo_rd_ptr = rd_ptr; - ud->rx_len = len; - ud->rx_ix = len; - - return true; + return true; } void hw_uart_read_buffer(HW_UART_ID uart, void *data, uint16_t len) { - UART_Data *ud = UARTDATA(uart); - uint8_t *p = data; + UART_Data *ud = UARTDATA(uart); + uint8_t *p = data; - /* - * Disable RX interrupt before draining software FIFO. - */ - hw_uart_enable_rx_int(uart, false); - - if (SOFTWARE_FIFO_PRESENT(ud)) - { /* - * Drain uses ud fields so setup them accordingly. + * Disable RX interrupt before draining software FIFO. */ - ud->rx_buffer = data; + hw_uart_enable_rx_int(uart, false); + if (SOFTWARE_FIFO_PRESENT(ud)) { + /* + * Drain uses ud fields so setup them accordingly. + */ + ud->rx_buffer = data; - hw_uart_drain_rx(uart, ud, len); - len -= ud->rx_ix; - p += ud->rx_ix; - } - - /* - * Read all remaining bytes with RX interrupt still disabled. - */ - while (len > 0) - { - *p++ = hw_uart_read(uart); - len--; - } - - ud->rx_ix = 0; - ud->rx_len = 0; - hw_uart_enable_rx_int(uart, SOFTWARE_FIFO_PRESENT(ud)); + hw_uart_drain_rx(uart, ud, len); + len -= ud->rx_ix; + p += ud->rx_ix; + } + /* + * Read all remaining bytes with RX interrupt still disabled. + */ + while (len > 0) { + *p++ = hw_uart_read(uart); + len--; + } + ud->rx_ix = 0; + ud->rx_len = 0; + hw_uart_enable_rx_int(uart, SOFTWARE_FIFO_PRESENT(ud)); } void hw_uart_set_soft_fifo(HW_UART_ID uart, uint8_t *buf, uint8_t size) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - hw_uart_enable_rx_int(uart, false); + hw_uart_enable_rx_int(uart, false); - ud->rx_soft_fifo = buf; - ud->rx_soft_fifo_size = size; - ud->rx_soft_fifo_rd_ptr = 0; - ud->rx_soft_fifo_wr_ptr = 0; + ud->rx_soft_fifo = buf; + ud->rx_soft_fifo_size = size; + ud->rx_soft_fifo_rd_ptr = 0; + ud->rx_soft_fifo_wr_ptr = 0; - hw_uart_enable_rx_int(uart, buf != NULL); + hw_uart_enable_rx_int(uart, buf != NULL); } #else @@ -387,420 +392,345 @@ void hw_uart_set_soft_fifo(HW_UART_ID uart, uint8_t *buf, uint8_t size) void hw_uart_read_buffer(HW_UART_ID uart, void *data, uint16_t len) { - uint8_t *p = data; + uint8_t *p = data; - while (len > 0) - { - *p++ = hw_uart_read(uart); - len--; - } + while (len > 0) { + *p++ = hw_uart_read(uart); + len--; + } } #endif static void hw_uart_fire_callback(UART_Data *ud) { - hw_uart_rx_callback cb = ud->rx_cb; - ud->rx_cb = NULL; - /* Just finished receiving, disable RX interrupts unless software FIFO is enabled */ - hw_uart_enable_rx_int(UARTID(ud), SOFTWARE_FIFO_PRESENT(ud)); - - if (cb) - { - cb(ud->rx_user_data, ud->rx_len); - } + hw_uart_rx_callback cb = ud->rx_cb; + ud->rx_cb = NULL; + /* Just finished receiving, disable RX interrupts unless software FIFO is enabled */ + hw_uart_enable_rx_int(UARTID(ud), SOFTWARE_FIFO_PRESENT(ud)); + if (cb) { + cb(ud->rx_user_data, ud->rx_len); + } } void hw_uart_receive(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callback cb, - void *user_data) + void *user_data) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - if (cb == NULL) - { - hw_uart_read_buffer(uart, data, len); + if (cb == NULL) { + hw_uart_read_buffer(uart, data, len); + ud->rx_ix = 0; + ud->rx_len = 0; + return; + } + + ud->rx_buffer = data; + ud->rx_user_data = user_data; + hw_uart_enable_rx_int(uart, false); + ud->rx_len = len; ud->rx_ix = 0; - ud->rx_len = 0; - return; - } - - ud->rx_buffer = data; - ud->rx_user_data = user_data; - hw_uart_enable_rx_int(uart, false); - ud->rx_len = len; - ud->rx_ix = 0; - ud->rx_cb = cb; + ud->rx_cb = cb; #if dg_configUART_SOFTWARE_FIFO - - if (hw_uart_drain_rx(uart, ud, len)) - { - hw_uart_fire_callback(ud); - return; - } - + if (hw_uart_drain_rx(uart, ud, len)) { + hw_uart_fire_callback(ud); + return; + } #endif #if dg_configUART_RX_CIRCULAR_DMA + if (ud->rx_dma_buf_size > 0) { + ASSERT_ERROR(len < ud->rx_dma_buf_size); - if (ud->rx_dma_buf_size > 0) - { - ASSERT_ERROR(len < ud->rx_dma_buf_size); + uint16_t new_int, cur_idx; + bool data_ready = false; - uint16_t new_int, cur_idx; - bool data_ready = false; + ASSERT_ERROR(ud->rx_dma_active == false); - ASSERT_ERROR(ud->rx_dma_active == false); + /* Calculate index of end of requested data (do not wrap it!) */ + new_int = ud->rx_dma_head + ud->rx_len - 1; - /* Calculate index of end of requested data (do not wrap it!) */ - new_int = ud->rx_dma_head + ud->rx_len - 1; + /* Freeze DMA so it does not move pointers while we try to update them */ + hw_dma_freeze(); - /* Freeze DMA so it does not move pointers while we try to update them */ - hw_dma_freeze(); + cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); - cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); + /* cur_idx is lower than rx_head only if it wrapped-around - fix it */ + if (cur_idx < ud->rx_dma_head) { + cur_idx += ud->rx_dma_buf_size; + } - /* cur_idx is lower than rx_head only if it wrapped-around - fix it */ - if (cur_idx < ud->rx_dma_head) - { - cur_idx += ud->rx_dma_buf_size; + /* + * If DMA has not read past the calculated index, we can set it and just wait for an + * interrupt. In other case, data are ready immediately in buffer. + */ + if (cur_idx <= new_int) { + new_int %= ud->rx_dma_buf_size; + hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, new_int); + ud->rx_dma_active = true; + } else { + hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, cur_idx - 1); + data_ready = true; + } + + /* Unfreeze DMA now, it can start reading */ + hw_dma_unfreeze(); + + /* Fire callback immediately if data already available in buffer */ + if (data_ready) { + hw_uart_fire_callback(ud); + } + + return; } - - /* - * If DMA has not read past the calculated index, we can set it and just wait for an - * interrupt. In other case, data are ready immediately in buffer. - */ - if (cur_idx <= new_int) - { - new_int %= ud->rx_dma_buf_size; - hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, new_int); - ud->rx_dma_active = true; - } - else - { - hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, cur_idx - 1); - data_ready = true; - } - - /* Unfreeze DMA now, it can start reading */ - hw_dma_unfreeze(); - - /* Fire callback immediately if data already available in buffer */ - if (data_ready) - { - hw_uart_fire_callback(ud); - } - - return; - } - #endif #if HW_UART_USE_DMA_SUPPORT - - if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID && (ud->rx_len - ud->rx_ix > 1)) - { - /* rx_ix could already be changed by hw_uart_drain_rx() */ - ud->rx_dma.dest_address = (uint32) data + ud->rx_ix; - ud->rx_dma.length = ud->rx_len - ud->rx_ix; - hw_uart_clear_dma_request(uart); - /* Prepare and start DMA */ - hw_dma_channel_initialization(&ud->rx_dma); - hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_ENABLED); - return; - } - + if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID && (ud->rx_len - ud->rx_ix > 1)) { + /* rx_ix could already be changed by hw_uart_drain_rx() */ + ud->rx_dma.dest_address = (uint32) data + ud->rx_ix; + ud->rx_dma.length = ud->rx_len - ud->rx_ix; + hw_uart_clear_dma_request(uart); + /* Prepare and start DMA */ + hw_dma_channel_initialization(&ud->rx_dma); + hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_ENABLED); + return; + } #endif - /* Interrupt driven */ - hw_uart_enable_rx_int(uart, true); + /* Interrupt driven */ + hw_uart_enable_rx_int(uart, true); } static void hw_uart_irq_stop_receive(HW_UART_ID uart) { - UART_Data *ud = &uart_data[UARTIX(uart)]; + UART_Data *ud = &uart_data[UARTIX(uart)]; - // Disable RX interrupt - hw_uart_enable_rx_int(uart, false); + // Disable RX interrupt + hw_uart_enable_rx_int(uart, false); - ud->rx_len = ud->rx_ix; + ud->rx_len = ud->rx_ix; - hw_uart_fire_callback(ud); + hw_uart_fire_callback(ud); } #if dg_configUART_RX_CIRCULAR_DMA static void hw_uart_copy_dma_rx_to_user_buffer(HW_UART_ID uart) { - UART_Data *ud = &uart_data[UARTIX(uart)]; + UART_Data *ud = &uart_data[UARTIX(uart)]; - uint16_t cur_idx; - uint16_t to_copy = 0; - hw_uart_rx_callback cb; + uint16_t cur_idx; + uint16_t to_copy = 0; + hw_uart_rx_callback cb; - ud->rx_dma_active = false; - cb = ud->rx_cb; + ud->rx_dma_active = false; + cb = ud->rx_cb; - if (cb) - { - ud->rx_cb = NULL; - /* - * User callback was not fired, since rx_dma_active is false it will not - * fire even if requested number of bytes was received when abort was initiated. - */ - cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); + if (cb) { + ud->rx_cb = NULL; + /* + * User callback was not fired, since rx_dma_active is false it will not + * fire even if requested number of bytes was received when abort was initiated. + */ + cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); - if (ud->rx_ix < ud->rx_len) - { - if (cur_idx < ud->rx_dma_head) - { - cur_idx += ud->rx_dma_buf_size; - } - - to_copy = cur_idx - ud->rx_dma_head; - - if (to_copy >= ud->rx_len - ud->rx_ix) - { + if (ud->rx_ix < ud->rx_len) { + if (cur_idx < ud->rx_dma_head) { + cur_idx += ud->rx_dma_buf_size; + } + to_copy = cur_idx - ud->rx_dma_head; + if (to_copy >= ud->rx_len - ud->rx_ix) { + to_copy = ud->rx_len - ud->rx_ix; + } + } + } else { + /* + * Callback already fired, circular buffer holds enough data. + */ to_copy = ud->rx_len - ud->rx_ix; - } } - } - else - { - /* - * Callback already fired, circular buffer holds enough data. - */ - to_copy = ud->rx_len - ud->rx_ix; - } - hw_uart_copy_rx_circular_dma_buffer(uart, ud->rx_buffer + ud->rx_ix, to_copy); - ud->rx_ix += to_copy; - ud->rx_len = ud->rx_ix; + hw_uart_copy_rx_circular_dma_buffer(uart, ud->rx_buffer + ud->rx_ix, to_copy); + ud->rx_ix += to_copy; + ud->rx_len = ud->rx_ix; - if (cb) - { - cb(ud->rx_user_data, ud->rx_len); - } + if (cb) { + cb(ud->rx_user_data, ud->rx_len); + } } #endif uint16_t hw_uart_abort_receive(HW_UART_ID uart) { - UART_Data *ud = &uart_data[UARTIX(uart)]; + UART_Data *ud = &uart_data[UARTIX(uart)]; #if HW_UART_USE_DMA_SUPPORT - - if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID) - { + if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID) { #if dg_configUART_RX_CIRCULAR_DMA - - if (ud->rx_dma_buf_size > 0) - { - hw_uart_copy_dma_rx_to_user_buffer(uart); - return ud->rx_ix; - } - + if (ud->rx_dma_buf_size > 0) { + hw_uart_copy_dma_rx_to_user_buffer(uart); + return ud->rx_ix; + } #else - /* No DMA circular buffer, stop DMA */ - hw_dma_channel_stop(ud->rx_dma.channel_number); + /* No DMA circular buffer, stop DMA */ + hw_dma_channel_stop(ud->rx_dma.channel_number); #endif - } - else + } + else #endif - hw_uart_irq_stop_receive(uart); + hw_uart_irq_stop_receive(uart); - return ud->rx_ix; + return ud->rx_ix; } uint16_t hw_uart_peek_received(HW_UART_ID uart) { - UART_Data *ud = &uart_data[UARTIX(uart)]; + UART_Data *ud = &uart_data[UARTIX(uart)]; #if HW_UART_USE_DMA_SUPPORT - - if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID) - { - ud->rx_ix = hw_dma_transfered_bytes(ud->rx_dma.channel_number); - } - + if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID) + ud->rx_ix = hw_dma_transfered_bytes(ud->rx_dma.channel_number); #endif - return ud->rx_ix; + return ud->rx_ix; } //============== Interrupt handling ============================================ static inline void hw_uart_tx_isr(HW_UART_ID uart) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - while (ud->tx_ix < ud->tx_len) - { - if (ud->tx_fifo_on) - { - if (!hw_uart_transmit_fifo_not_full(uart)) - { - break; - } + while (ud->tx_ix < ud->tx_len) { + if (ud->tx_fifo_on) { + if (!hw_uart_transmit_fifo_not_full(uart)) { + break; + } + } else if (!hw_uart_thr_empty_getf(uart)) { + break; + } + hw_uart_txdata_setf(uart, ud->tx_buffer[ud->tx_ix++]); } - else if (!hw_uart_thr_empty_getf(uart)) - { - break; + // Everything sent? + if (ud->tx_ix >= ud->tx_len) { + hw_uart_tx_callback cb = ud->tx_cb; + // Disable TX interrupts + // They can be re-enabled in user callback + uint16_t ier_dlh_reg = UBA(uart)->UART2_IER_DLH_REG; + ier_dlh_reg &= ~((1 << UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos) | (1 << UART_UART_IER_DLH_REG_PTIME_dlh7_Pos)); + UBA(uart)->UART2_IER_DLH_REG = ier_dlh_reg; + ud->tx_cb = NULL; + if (cb) { + cb(ud->tx_user_data, ud->tx_len); + } } - - hw_uart_txdata_setf(uart, ud->tx_buffer[ud->tx_ix++]); - } - - // Everything sent? - if (ud->tx_ix >= ud->tx_len) - { - hw_uart_tx_callback cb = ud->tx_cb; - // Disable TX interrupts - // They can be re-enabled in user callback - uint16_t ier_dlh_reg = UBA(uart)->UART2_IER_DLH_REG; - ier_dlh_reg &= ~((1 << UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos) | (1 << UART_UART_IER_DLH_REG_PTIME_dlh7_Pos)); - UBA(uart)->UART2_IER_DLH_REG = ier_dlh_reg; - ud->tx_cb = NULL; - - if (cb) - { - cb(ud->tx_user_data, ud->tx_len); - } - } } static inline void hw_uart_rx_isr(HW_UART_ID uart) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - if (SOFTWARE_FIFO_PRESENT(ud)) - { + if (SOFTWARE_FIFO_PRESENT(ud)) { #if dg_configUART_SOFTWARE_FIFO + for (;;) { + fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr + 1; + if (wr_ptr >= ud->rx_soft_fifo_size) { + wr_ptr = 0; + } + if (wr_ptr == ud->rx_soft_fifo_rd_ptr) { + /* Software FIFO full, disable interrupt since no one is reading */ + hw_uart_enable_rx_int(uart, false); + return; + } + if (!hw_uart_is_data_ready(uart)) { + break; + } + ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr] = hw_uart_rxdata_getf(uart); - for (;;) - { - fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr + 1; - - if (wr_ptr >= ud->rx_soft_fifo_size) - { - wr_ptr = 0; - } - - if (wr_ptr == ud->rx_soft_fifo_rd_ptr) - { - /* Software FIFO full, disable interrupt since no one is reading */ - hw_uart_enable_rx_int(uart, false); - return; - } - - if (!hw_uart_is_data_ready(uart)) - { - break; - } - - ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr] = hw_uart_rxdata_getf(uart); - - /* - * Application read is in progress. Copy data from software FIFO to - * user provided buffer. - */ - if (ud->rx_ix < ud->rx_len) - { - ud->rx_buffer[ud->rx_ix++] = ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr]; - /* - * When application read is in progress, rx_ix < rx_len - * This interrupt is enabled only if all data was already copied from - * FIFO to user buffer. It is safe to modify rx_soft_fifo_rd_ptr. - */ - ud->rx_soft_fifo_rd_ptr = wr_ptr; - } - - ud->rx_soft_fifo_wr_ptr = wr_ptr; - } + /* + * Application read is in progress. Copy data from software FIFO to + * user provided buffer. + */ + if (ud->rx_ix < ud->rx_len) { + ud->rx_buffer[ud->rx_ix++] = ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr]; + /* + * When application read is in progress, rx_ix < rx_len + * This interrupt is enabled only if all data was already copied from + * FIFO to user buffer. It is safe to modify rx_soft_fifo_rd_ptr. + */ + ud->rx_soft_fifo_rd_ptr = wr_ptr; + } + ud->rx_soft_fifo_wr_ptr = wr_ptr; + } #endif - } - else - { - while (ud->rx_ix < ud->rx_len) - { - if (hw_uart_is_data_ready(uart)) - { - ud->rx_buffer[ud->rx_ix++] = hw_uart_rxdata_getf(uart); - } - else - { - break; - } + } else { + while (ud->rx_ix < ud->rx_len) { + if (hw_uart_is_data_ready(uart)) { + ud->rx_buffer[ud->rx_ix++] = hw_uart_rxdata_getf(uart); + } else { + break; + } + } } - } - // Everything read? - if (ud->rx_len > 0 && ud->rx_ix >= ud->rx_len) - { - // Disable RX interrupts, fire callback if present - hw_uart_irq_stop_receive(uart); - } + // Everything read? + if (ud->rx_len > 0 && ud->rx_ix >= ud->rx_len) { + // Disable RX interrupts, fire callback if present + hw_uart_irq_stop_receive(uart); + } } static inline void hw_uart_rx_timeout_isr(HW_UART_ID uart) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - hw_uart_rx_isr(uart); + hw_uart_rx_isr(uart); - /* - * Not everything was received yet, disable interrupt anyway since - * some data was received. - */ - if (ud->rx_ix > 0 && ud->rx_ix < ud->rx_len) - { - // Disable RX interrupts fire callback if present - hw_uart_irq_stop_receive(uart); - } + /* + * Not everything was received yet, disable interrupt anyway since + * some data was received. + */ + if (ud->rx_ix > 0 && ud->rx_ix < ud->rx_len) { + // Disable RX interrupts fire callback if present + hw_uart_irq_stop_receive(uart); + } } void UART_Interrupt_Handler(HW_UART_ID uart) { - HW_UART_INT int_id; + HW_UART_INT int_id; - for (;;) - { - int_id = hw_uart_get_interrupt_id(uart); - - switch (int_id) - { - case HW_UART_INT_TIMEOUT: - hw_uart_rx_timeout_isr(uart); - break; - - case HW_UART_INT_MODEM_STAT: - break; - - case HW_UART_INT_NO_INT_PEND: - return; - break; - - case HW_UART_INT_THR_EMPTY: - hw_uart_tx_isr(uart); - break; - - case HW_UART_INT_RECEIVED_AVAILABLE: - hw_uart_rx_isr(uart); - break; - - case HW_UART_INT_RECEIVE_LINE_STAT: - break; - - case HW_UART_INT_BUSY_DETECTED: + for (;;) { + int_id = hw_uart_get_interrupt_id(uart); + switch (int_id) { + case HW_UART_INT_TIMEOUT: + hw_uart_rx_timeout_isr(uart); + break; + case HW_UART_INT_MODEM_STAT: + break; + case HW_UART_INT_NO_INT_PEND: + return; + break; + case HW_UART_INT_THR_EMPTY: + hw_uart_tx_isr(uart); + break; + case HW_UART_INT_RECEIVED_AVAILABLE: + hw_uart_rx_isr(uart); + break; + case HW_UART_INT_RECEIVE_LINE_STAT: + break; + case HW_UART_INT_BUSY_DETECTED: #ifdef CONFIG_UART_IGNORE_BUSY_DETECT - hw_uart_transmit_fifo_empty(uart); + hw_uart_transmit_fifo_empty(uart); #else - /* - * Stop here means that timing rules for access divisor latch were not - * followed. See description of register RBR_THR_DLL. - */ - __BKPT(0); + /* + * Stop here means that timing rules for access divisor latch were not + * followed. See description of register RBR_THR_DLL. + */ + __BKPT(0); #endif - break; + break; + } } - } } /** @@ -809,24 +739,19 @@ void UART_Interrupt_Handler(HW_UART_ID uart) */ void UART_Handler(void) { - SEGGER_SYSTEMVIEW_ISR_ENTER(); + SEGGER_SYSTEMVIEW_ISR_ENTER(); #ifdef HW_UART_ENABLE_USER_ISR - - if (uart_data[UARTIX(HW_UART1)].user_isr) - { - uart_data[UARTIX(HW_UART1)].user_isr(); - } - else - { + if (uart_data[UARTIX(HW_UART1)].user_isr) { + uart_data[UARTIX(HW_UART1)].user_isr(); + } else { #endif - UART_Interrupt_Handler(HW_UART1); + UART_Interrupt_Handler(HW_UART1); #ifdef HW_UART_ENABLE_USER_ISR - } - + } #endif - SEGGER_SYSTEMVIEW_ISR_EXIT(); + SEGGER_SYSTEMVIEW_ISR_EXIT(); } /** @@ -835,92 +760,84 @@ void UART_Handler(void) */ void UART2_Handler(void) { - SEGGER_SYSTEMVIEW_ISR_ENTER(); + SEGGER_SYSTEMVIEW_ISR_ENTER(); #ifdef HW_UART_ENABLE_USER_ISR - - if (uart_data[UARTIX(HW_UART2)].user_isr) - { - uart_data[UARTIX(HW_UART2)].user_isr(); - } - else - { + if (uart_data[UARTIX(HW_UART2)].user_isr) { + uart_data[UARTIX(HW_UART2)].user_isr(); + } else { #endif - UART_Interrupt_Handler(HW_UART2); + UART_Interrupt_Handler(HW_UART2); #ifdef HW_UART_ENABLE_USER_ISR - } - + } #endif - SEGGER_SYSTEMVIEW_ISR_EXIT(); + SEGGER_SYSTEMVIEW_ISR_EXIT(); } //==================== Configuration functions ================================= HW_UART_BAUDRATE hw_uart_baudrate_get(HW_UART_ID uart) { - uint32_t baud_rate; + uint32_t baud_rate; - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Read baud rate low byte from DLL register - baud_rate = (0xFF & UBA(uart)->UART2_RBR_THR_DLL_REG) << 8; - // Read baud rate high byte from DLH register - baud_rate += (0xFF & UBA(uart)->UART2_IER_DLH_REG) << 16; - // Read baud rate fraction byte from DLF register - baud_rate += 0xFF & UBA(uart)->UART2_DLF_REG; - // Reset Divisor Latch Access Bit in Line Control Register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); + // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); + // Read baud rate low byte from DLL register + baud_rate = (0xFF & UBA(uart)->UART2_RBR_THR_DLL_REG) << 8; + // Read baud rate high byte from DLH register + baud_rate += (0xFF & UBA(uart)->UART2_IER_DLH_REG) << 16; + // Read baud rate fraction byte from DLF register + baud_rate += 0xFF & UBA(uart)->UART2_DLF_REG; + // Reset Divisor Latch Access Bit in Line Control Register + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - return (HW_UART_BAUDRATE) baud_rate; + return (HW_UART_BAUDRATE) baud_rate; } void hw_uart_baudrate_set(HW_UART_ID uart, HW_UART_BAUDRATE baud_rate) { - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (baud_rate >> 8); - // Set high byte of baud rare - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); + // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); + // Set fraction byte of baud rate + UBA(uart)->UART2_DLF_REG = 0xFF & baud_rate; + // Set low byte of baud rate + UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (baud_rate >> 8); + // Set high byte of baud rare + UBA(uart)->UART2_IER_DLH_REG = 0xFF & (baud_rate >> 16); + // Reset Divisor Latch Access Bit in LCR register + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); } //=========================== FIFO control functions =========================== uint8_t hw_uart_fifo_en_getf(HW_UART_ID uart) { - uint16_t fifo_enabled; + uint16_t fifo_enabled; - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); + /* Only UART2 has a FIFO */ + ASSERT_ERROR(uart == HW_UART2); - fifo_enabled = (UBA(uart)->UART2_IIR_FCR_REG & 0x00C0); /* Bits[7:6] */ + fifo_enabled = (UBA(uart)->UART2_IIR_FCR_REG & 0x00C0); /* Bits[7:6] */ - switch (fifo_enabled) - { - case 0x00C0: - return 1; - - case 0x0000: - return 0; - - default: - ASSERT_ERROR(0); - return 255; // To satisfy the compiler - } + switch (fifo_enabled) { + case 0x00C0: + return 1; + case 0x0000: + return 0; + default: + ASSERT_ERROR(0); + return 255; // To satisfy the compiler + } } uint8_t hw_uart_tx_fifo_tr_lvl_getf(HW_UART_ID uart) { - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); + /* Only UART2 has a FIFO */ + ASSERT_ERROR(uart == HW_UART2); - return (UART2->UART2_STET_REG & HW_UART_REG_FIELD_MASK(2, STET, UART_SHADOW_TX_EMPTY_TRIGGER)) - >> HW_UART_REG_FIELD_POS(2, STET, UART_SHADOW_TX_EMPTY_TRIGGER); + return (UART2->UART2_STET_REG & HW_UART_REG_FIELD_MASK(2, STET, UART_SHADOW_TX_EMPTY_TRIGGER)) + >> HW_UART_REG_FIELD_POS(2, STET, UART_SHADOW_TX_EMPTY_TRIGGER); } //=========================== DMA control functions ============================ @@ -929,240 +846,220 @@ uint8_t hw_uart_tx_fifo_tr_lvl_getf(HW_UART_ID uart) static void hw_uart_rx_dma_callback(void *user_data, uint16_t len) { - UART_Data *ud = user_data; - hw_uart_rx_callback cb = ud->rx_cb; + UART_Data *ud = user_data; + hw_uart_rx_callback cb = ud->rx_cb; - ud->rx_cb = NULL; - ud->rx_ix += len; - - if (cb) - { - ud->rx_len = ud->rx_ix; - hw_uart_enable_rx_int(UARTID(ud), SOFTWARE_FIFO_PRESENT(ud)); - cb(ud->rx_user_data, ud->rx_ix); - } + ud->rx_cb = NULL; + ud->rx_ix += len; + if (cb) { + ud->rx_len = ud->rx_ix; + hw_uart_enable_rx_int(UARTID(ud), SOFTWARE_FIFO_PRESENT(ud)); + cb(ud->rx_user_data, ud->rx_ix); + } } static void hw_uart_tx_dma_callback(void *user_data, uint16_t len) { - UART_Data *ud = user_data; - hw_uart_tx_callback cb = ud->tx_cb; + UART_Data *ud = user_data; + hw_uart_tx_callback cb = ud->tx_cb; - ud->tx_cb = NULL; - ud->tx_ix = len; - - if (cb) - { - cb(ud->tx_user_data, len); - } + ud->tx_cb = NULL; + ud->tx_ix = len; + if (cb) { + cb(ud->tx_user_data, len); + } } void hw_uart_set_dma_channels(HW_UART_ID uart, int8_t channel, HW_DMA_PRIO pri) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - /* Only specific DMA channels (or -1 for no DMA) are allowed */ - ASSERT_ERROR(channel < 0 || - channel == HW_DMA_CHANNEL_0 || - channel == HW_DMA_CHANNEL_2 || - channel == HW_DMA_CHANNEL_4 || - channel == HW_DMA_CHANNEL_6 || - channel == HW_DMA_CHANNEL_INVALID); + /* Only specific DMA channels (or -1 for no DMA) are allowed */ + ASSERT_ERROR(channel < 0 || + channel == HW_DMA_CHANNEL_0 || + channel == HW_DMA_CHANNEL_2 || + channel == HW_DMA_CHANNEL_4 || + channel == HW_DMA_CHANNEL_6 || + channel == HW_DMA_CHANNEL_INVALID); - if (channel < 0) - { - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - } - else - { - ud->use_dma = 1; + if (channel < 0) { + ud->use_dma = 0; + ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + } else { + ud->use_dma = 1; - ud->rx_dma.channel_number = channel; - ud->rx_dma.bus_width = HW_DMA_BW_BYTE; - ud->rx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->rx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->rx_dma.irq_nr_of_trans = 0; - ud->rx_dma.a_inc = HW_DMA_AINC_FALSE; - ud->rx_dma.b_inc = HW_DMA_BINC_TRUE; - ud->rx_dma.circular = HW_DMA_MODE_NORMAL; - ud->rx_dma.dma_prio = pri; - ud->rx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->rx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->rx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->rx_dma.src_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->rx_dma.dest_address = 0; // Change during transmission - ud->rx_dma.length = 0; // Change during transmission - ud->rx_dma.callback = hw_uart_rx_dma_callback; - ud->rx_dma.user_data = ud; + ud->rx_dma.channel_number = channel; + ud->rx_dma.bus_width = HW_DMA_BW_BYTE; + ud->rx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; + ud->rx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : + HW_DMA_TRIG_UART2_RXTX; + ud->rx_dma.irq_nr_of_trans = 0; + ud->rx_dma.a_inc = HW_DMA_AINC_FALSE; + ud->rx_dma.b_inc = HW_DMA_BINC_TRUE; + ud->rx_dma.circular = HW_DMA_MODE_NORMAL; + ud->rx_dma.dma_prio = pri; + ud->rx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ + ud->rx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; + ud->rx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; + ud->rx_dma.src_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; + ud->rx_dma.dest_address = 0; // Change during transmission + ud->rx_dma.length = 0; // Change during transmission + ud->rx_dma.callback = hw_uart_rx_dma_callback; + ud->rx_dma.user_data = ud; - ud->tx_dma.channel_number = channel + 1; - ud->tx_dma.bus_width = HW_DMA_BW_BYTE; - ud->tx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->tx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->tx_dma.irq_nr_of_trans = 0; - ud->tx_dma.a_inc = HW_DMA_AINC_TRUE; - ud->tx_dma.b_inc = HW_DMA_BINC_FALSE; - ud->tx_dma.circular = HW_DMA_MODE_NORMAL; - ud->tx_dma.dma_prio = pri; - ud->tx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->tx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->tx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->tx_dma.src_address = 0; // Change during transmission - ud->tx_dma.dest_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->tx_dma.length = 0; // Change during transmission - ud->tx_dma.callback = hw_uart_tx_dma_callback; - ud->tx_dma.user_data = ud; - } + ud->tx_dma.channel_number = channel + 1; + ud->tx_dma.bus_width = HW_DMA_BW_BYTE; + ud->tx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; + ud->tx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : + HW_DMA_TRIG_UART2_RXTX; + ud->tx_dma.irq_nr_of_trans = 0; + ud->tx_dma.a_inc = HW_DMA_AINC_TRUE; + ud->tx_dma.b_inc = HW_DMA_BINC_FALSE; + ud->tx_dma.circular = HW_DMA_MODE_NORMAL; + ud->tx_dma.dma_prio = pri; + ud->tx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ + ud->tx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; + ud->tx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; + ud->tx_dma.src_address = 0; // Change during transmission + ud->tx_dma.dest_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; + ud->tx_dma.length = 0; // Change during transmission + ud->tx_dma.callback = hw_uart_tx_dma_callback; + ud->tx_dma.user_data = ud; + } } void hw_uart_set_dma_channels_ex(HW_UART_ID uart, int8_t tx_channel, int8_t rx_channel, HW_DMA_PRIO pri) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - /* Only specific DMA channels are allowed (or HW_DMA_CHANNEL_INVALID for no DMA) */ - ASSERT_ERROR(tx_channel >= HW_DMA_CHANNEL_0 && - tx_channel <= HW_DMA_CHANNEL_INVALID); + /* Only specific DMA channels are allowed (or HW_DMA_CHANNEL_INVALID for no DMA) */ + ASSERT_ERROR(tx_channel >= HW_DMA_CHANNEL_0 && + tx_channel <= HW_DMA_CHANNEL_INVALID); - /* Only specific DMA channels are allowed (or HW_DMA_CHANNEL_INVALID for no DMA) */ - ASSERT_ERROR(rx_channel >= HW_DMA_CHANNEL_0 && - rx_channel <= HW_DMA_CHANNEL_INVALID); + /* Only specific DMA channels are allowed (or HW_DMA_CHANNEL_INVALID for no DMA) */ + ASSERT_ERROR(rx_channel >= HW_DMA_CHANNEL_0 && + rx_channel <= HW_DMA_CHANNEL_INVALID); - if (tx_channel == HW_DMA_CHANNEL_INVALID && rx_channel == HW_DMA_CHANNEL_INVALID) - { - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - } - else - { - if (tx_channel != HW_DMA_CHANNEL_INVALID && rx_channel != HW_DMA_CHANNEL_INVALID) //not both invalid - { - ASSERT_ERROR(tx_channel != rx_channel);//not equal - ASSERT_ERROR(tx_channel >> 1 == rx_channel >> 1); //on same pair + if (tx_channel == HW_DMA_CHANNEL_INVALID && rx_channel== HW_DMA_CHANNEL_INVALID) { + ud->use_dma = 0; + ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + } else { + if (tx_channel != HW_DMA_CHANNEL_INVALID && rx_channel!= HW_DMA_CHANNEL_INVALID) {//not both invalid + ASSERT_ERROR(tx_channel != rx_channel);//not equal + ASSERT_ERROR(tx_channel>>1 == rx_channel>>1);//on same pair + } + if (tx_channel != HW_DMA_CHANNEL_INVALID) { + ASSERT_ERROR(tx_channel & 1);//odd number + } + if (rx_channel != HW_DMA_CHANNEL_INVALID) { + ASSERT_ERROR((rx_channel & 1) == 0);//odd number + } + + ud->use_dma = 1; + + ud->rx_dma.channel_number = rx_channel; + ud->rx_dma.bus_width = HW_DMA_BW_BYTE; + ud->rx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; + ud->rx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : + HW_DMA_TRIG_UART2_RXTX; + ud->rx_dma.irq_nr_of_trans = 0; + ud->rx_dma.a_inc = HW_DMA_AINC_FALSE; + ud->rx_dma.b_inc = HW_DMA_BINC_TRUE; + ud->rx_dma.circular = HW_DMA_MODE_NORMAL; + ud->rx_dma.dma_prio = pri; + ud->rx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ + ud->rx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; + ud->rx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; + ud->rx_dma.src_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; + ud->rx_dma.dest_address = 0; // Change during transmission + ud->rx_dma.length = 0; // Change during transmission + ud->rx_dma.callback = hw_uart_rx_dma_callback; + ud->rx_dma.user_data = ud; + + ud->tx_dma.channel_number = tx_channel; + ud->tx_dma.bus_width = HW_DMA_BW_BYTE; + ud->tx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; + ud->tx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : + HW_DMA_TRIG_UART2_RXTX; + ud->tx_dma.irq_nr_of_trans = 0; + ud->tx_dma.a_inc = HW_DMA_AINC_TRUE; + ud->tx_dma.b_inc = HW_DMA_BINC_FALSE; + ud->tx_dma.circular = HW_DMA_MODE_NORMAL; + ud->tx_dma.dma_prio = pri; + ud->tx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ + ud->tx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; + ud->tx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; + ud->tx_dma.src_address = 0; // Change during transmission + ud->tx_dma.dest_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; + ud->tx_dma.length = 0; // Change during transmission + ud->tx_dma.callback = hw_uart_tx_dma_callback; + ud->tx_dma.user_data = ud; } - - if (tx_channel != HW_DMA_CHANNEL_INVALID) - { - ASSERT_ERROR(tx_channel & 1);//odd number - } - - if (rx_channel != HW_DMA_CHANNEL_INVALID) - { - ASSERT_ERROR((rx_channel & 1) == 0);//odd number - } - - ud->use_dma = 1; - - ud->rx_dma.channel_number = rx_channel; - ud->rx_dma.bus_width = HW_DMA_BW_BYTE; - ud->rx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->rx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->rx_dma.irq_nr_of_trans = 0; - ud->rx_dma.a_inc = HW_DMA_AINC_FALSE; - ud->rx_dma.b_inc = HW_DMA_BINC_TRUE; - ud->rx_dma.circular = HW_DMA_MODE_NORMAL; - ud->rx_dma.dma_prio = pri; - ud->rx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->rx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->rx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->rx_dma.src_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->rx_dma.dest_address = 0; // Change during transmission - ud->rx_dma.length = 0; // Change during transmission - ud->rx_dma.callback = hw_uart_rx_dma_callback; - ud->rx_dma.user_data = ud; - - ud->tx_dma.channel_number = tx_channel; - ud->tx_dma.bus_width = HW_DMA_BW_BYTE; - ud->tx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->tx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->tx_dma.irq_nr_of_trans = 0; - ud->tx_dma.a_inc = HW_DMA_AINC_TRUE; - ud->tx_dma.b_inc = HW_DMA_BINC_FALSE; - ud->tx_dma.circular = HW_DMA_MODE_NORMAL; - ud->tx_dma.dma_prio = pri; - ud->tx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->tx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->tx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->tx_dma.src_address = 0; // Change during transmission - ud->tx_dma.dest_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->tx_dma.length = 0; // Change during transmission - ud->tx_dma.callback = hw_uart_tx_dma_callback; - ud->tx_dma.user_data = ud; - } } #if dg_configUART_RX_CIRCULAR_DMA static void hw_uart_rx_circular_dma_callback(void *user_data, uint16_t len) { - UART_Data *ud = user_data; - hw_uart_rx_callback cb = ud->rx_cb; + UART_Data *ud = user_data; + hw_uart_rx_callback cb = ud->rx_cb; - if (!ud->rx_dma_active) - { - return; - } + if (!ud->rx_dma_active) { + return; + } - ud->rx_cb = NULL; - ud->rx_dma_active = false; + ud->rx_cb = NULL; + ud->rx_dma_active = false; - if (cb) - { - cb(ud->rx_user_data, ud->rx_len); - } + if (cb) { + cb(ud->rx_user_data, ud->rx_len); + } } void hw_uart_enable_rx_circular_dma(HW_UART_ID uart) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - ASSERT_ERROR(ud->rx_dma_buf_size > 0); + ASSERT_ERROR(ud->rx_dma_buf_size > 0); - hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_DISABLED); + hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_DISABLED); - /* Need to reconfigure few things for circular operation... */ - ud->rx_dma.circular = HW_DMA_MODE_CIRCULAR; - ud->rx_dma.dest_address = (uint32_t) ud->rx_dma_buf; - ud->rx_dma.length = ud->rx_dma_buf_size; - ud->rx_dma.callback = hw_uart_rx_circular_dma_callback; - ud->rx_dma.user_data = ud; + /* Need to reconfigure few things for circular operation... */ + ud->rx_dma.circular = HW_DMA_MODE_CIRCULAR; + ud->rx_dma.dest_address = (uint32_t) ud->rx_dma_buf; + ud->rx_dma.length = ud->rx_dma_buf_size; + ud->rx_dma.callback = hw_uart_rx_circular_dma_callback; + ud->rx_dma.user_data = ud; - /* Reset DMA buffer read pointer */ - ud->rx_dma_head = 0; + /* Reset DMA buffer read pointer */ + ud->rx_dma_head = 0; - /* Start DMA now since it should be always-running */ - hw_uart_clear_dma_request(uart); - hw_dma_channel_initialization(&ud->rx_dma); - hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_ENABLED); + /* Start DMA now since it should be always-running */ + hw_uart_clear_dma_request(uart); + hw_dma_channel_initialization(&ud->rx_dma); + hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_ENABLED); } void hw_uart_copy_rx_circular_dma_buffer(HW_UART_ID uart, uint8_t *buf, uint16_t len) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - ASSERT_ERROR(len < ud->rx_dma_buf_size); + ASSERT_ERROR(len < ud->rx_dma_buf_size); - if (ud->rx_dma_head + len <= ud->rx_dma_buf_size) - { - memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], len); - } - else - { - uint16_t chunk_len = ud->rx_dma_buf_size - ud->rx_dma_head; - memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], chunk_len); - memcpy(buf + chunk_len, &ud->rx_dma_buf[0], len - chunk_len); - } + if (ud->rx_dma_head + len <= ud->rx_dma_buf_size) { + memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], len); + } else { + uint16_t chunk_len = ud->rx_dma_buf_size - ud->rx_dma_head; + memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], chunk_len); + memcpy(buf + chunk_len, &ud->rx_dma_buf[0], len - chunk_len); + } - /* This should be protected so ISR does not try to read rx_dma_head while we update it */ - GLOBAL_INT_DISABLE(); - ud->rx_dma_head = (ud->rx_dma_head + len) % ud->rx_dma_buf_size; - GLOBAL_INT_RESTORE(); + /* This should be protected so ISR does not try to read rx_dma_head while we update it */ + GLOBAL_INT_DISABLE(); + ud->rx_dma_head = (ud->rx_dma_head + len) % ud->rx_dma_buf_size; + GLOBAL_INT_RESTORE(); } #endif /* dg_configUART_RX_CIRCULAR_DMA */ @@ -1172,442 +1069,391 @@ void hw_uart_copy_rx_circular_dma_buffer(HW_UART_ID uart, uint8_t *buf, uint16_t //=========================== Line control functions ============================ void hw_uart_init_ex(HW_UART_ID uart, const uart_config_ex *uart_init) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); + /* + * Read UART_USR_REG to clear any pending busy interrupt. + */ + hw_uart_transmit_fifo_empty(uart); - if (uart == HW_UART1) - { - // there is no FIFO for UART0 as yet - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; -#if dg_configUART_SOFTWARE_FIFO - ud->rx_soft_fifo = uart1_sw_fifo; - ud->rx_soft_fifo_size = dg_configUART1_SOFTWARE_FIFO_SIZE; -#endif -#if dg_configUART_RX_CIRCULAR_DMA - ud->rx_dma_buf = uart1_rx_dma_buf; - ud->rx_dma_buf_size = dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE; -#endif - hw_uart_disable_fifo(uart); - } - else - { - if (uart_init->use_fifo) - { - ud->rx_fifo_on = 1; - ud->tx_fifo_on = 1; -#if dg_configUART_SOFTWARE_FIFO - ud->rx_soft_fifo = uart2_sw_fifo; - ud->rx_soft_fifo_size = dg_configUART2_SOFTWARE_FIFO_SIZE; -#endif -#if dg_configUART_RX_CIRCULAR_DMA - ud->rx_dma_buf = uart2_rx_dma_buf; - ud->rx_dma_buf_size = dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE; -#endif - hw_uart_enable_fifo(uart); - ud->rx_fifo_level = uart_init->rx_fifo_tr_lvl; - hw_uart_rx_fifo_tr_lvl_setf(uart, uart_init->rx_fifo_tr_lvl); - ud->tx_fifo_level = uart_init->tx_fifo_tr_lvl; - hw_uart_tx_fifo_tr_lvl_setf(uart, uart_init->tx_fifo_tr_lvl); + + if (uart == HW_UART1) { + // there is no FIFO for UART0 as yet + ud->rx_fifo_on = 0; + ud->tx_fifo_on = 0; + hw_uart_disable_fifo(uart); + } else { + if (uart_init->use_fifo) { + ud->rx_fifo_on = 1; + ud->tx_fifo_on = 1; + hw_uart_enable_fifo(uart); + ud->rx_fifo_level = uart_init->rx_fifo_tr_lvl; + hw_uart_rx_fifo_tr_lvl_setf(uart, uart_init->rx_fifo_tr_lvl); + ud->tx_fifo_level = uart_init->tx_fifo_tr_lvl; + hw_uart_tx_fifo_tr_lvl_setf(uart, uart_init->tx_fifo_tr_lvl); + } else { + ud->rx_fifo_on = 0; + ud->tx_fifo_on = 0; + hw_uart_disable_fifo(uart); + } } - else - { - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; - hw_uart_disable_fifo(uart); - } - } + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rate - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - ud->tx_cb = NULL; - ud->rx_cb = NULL; - ud->rx_len = 0; - ud->tx_len = 0; - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); + // Set fraction byte of baud rate + UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; + // Set low byte of baud rate + UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); + // Set high byte of baud rate + UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); + // Reset Divisor Latch Access Bit in LCR register + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); + // Set Parity + UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; + // Set Data Bits + HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); + // Set Stop Bits + HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); + // Set Auto flow control + HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); + HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); + ud->tx_cb = NULL; + ud->rx_cb = NULL; + ud->rx_len = 0; + ud->tx_len = 0; + ud->use_dma = 0; + ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; #if HW_UART_USE_DMA_SUPPORT - - if (uart_init->use_dma) - { - hw_uart_set_dma_channels_ex(uart, uart_init->tx_dma_channel, uart_init->rx_dma_channel, HW_DMA_PRIO_2); - } - + if (uart_init->use_dma) { + hw_uart_set_dma_channels_ex(uart, uart_init->tx_dma_channel, uart_init->rx_dma_channel, HW_DMA_PRIO_2); + } #endif } void hw_uart_reinit_ex(HW_UART_ID uart, const uart_config_ex *uart_init) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); + /* + * Read UART_USR_REG to clear any pending busy interrupt. + */ + hw_uart_transmit_fifo_empty(uart); - if (uart == HW_UART2) - { - if (uart_init->use_fifo) - { - hw_uart_enable_fifo(uart); - hw_uart_rx_fifo_tr_lvl_setf(uart, uart_init->rx_fifo_tr_lvl); - hw_uart_tx_fifo_tr_lvl_setf(uart, uart_init->tx_fifo_tr_lvl); + if (uart == HW_UART2) { + if (uart_init->use_fifo) { + hw_uart_enable_fifo(uart); + hw_uart_rx_fifo_tr_lvl_setf(uart, uart_init->rx_fifo_tr_lvl); + hw_uart_tx_fifo_tr_lvl_setf(uart, uart_init->tx_fifo_tr_lvl); + } else { + hw_uart_disable_fifo(uart); + } } - else - { - hw_uart_disable_fifo(uart); - } - } - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rare - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); + // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); + // Set fraction byte of baud rate + UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; + // Set low byte of baud rate + UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); + // Set high byte of baud rare + UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); + // Reset Divisor Latch Access Bit in LCR register + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); + // Set Parity + UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; + // Set Data Bits + HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); + // Set Stop Bits + HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); + // Set Auto flow control + HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); + HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - if (ud->rx_cb && ud->rx_len != ud->rx_ix) - { - if (ud->rx_len > 1 && uart_init->use_dma && uart_init->rx_dma_channel != HW_DMA_CHANNEL_INVALID) - { + if (ud->rx_cb && ud->rx_len != ud->rx_ix) { + if (ud->rx_len > 1 && uart_init->use_dma && uart_init->rx_dma_channel != HW_DMA_CHANNEL_INVALID) { + } else { + // Interrupt driven + hw_uart_enable_rx_int(uart, true); + } } - else - { - // Interrupt driven - hw_uart_enable_rx_int(uart, true); - } - } } void hw_uart_init(HW_UART_ID uart, const uart_config *uart_init) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); + /* + * Read UART_USR_REG to clear any pending busy interrupt. + */ + hw_uart_transmit_fifo_empty(uart); - if (uart == HW_UART1) - { - // there is no FIFO for UART0 as yet - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; - hw_uart_disable_fifo(uart); - } - else - { - if (uart_init->use_fifo) - { - ud->rx_fifo_on = 1; - ud->tx_fifo_on = 1; - hw_uart_enable_fifo(uart); - hw_uart_rx_fifo_tr_lvl_setf(uart, 0); - hw_uart_tx_fifo_tr_lvl_setf(uart, 0); + if (uart == HW_UART1) { + // there is no FIFO for UART0 as yet + ud->rx_fifo_on = 0; + ud->tx_fifo_on = 0; + hw_uart_disable_fifo(uart); + } else { + if (uart_init->use_fifo) { + ud->rx_fifo_on = 1; + ud->tx_fifo_on = 1; + hw_uart_enable_fifo(uart); + hw_uart_rx_fifo_tr_lvl_setf(uart, 0); + hw_uart_tx_fifo_tr_lvl_setf(uart, 0); + } else { + ud->rx_fifo_on = 0; + ud->tx_fifo_on = 0; + hw_uart_disable_fifo(uart); + } } - else - { - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; - hw_uart_disable_fifo(uart); - } - } + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rate - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - ud->tx_cb = NULL; - ud->rx_cb = NULL; - ud->rx_len = 0; - ud->tx_len = 0; - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); + // Set fraction byte of baud rate + UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; + // Set low byte of baud rate + UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); + // Set high byte of baud rate + UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); + // Reset Divisor Latch Access Bit in LCR register + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); + // Set Parity + UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; + // Set Data Bits + HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); + // Set Stop Bits + HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); + // Set Auto flow control + HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); + HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); + ud->tx_cb = NULL; + ud->rx_cb = NULL; + ud->rx_len = 0; + ud->tx_len = 0; + ud->use_dma = 0; + ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; + ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; #if HW_UART_USE_DMA_SUPPORT - - if (uart_init->use_dma) - { - hw_uart_set_dma_channels_ex(uart, uart_init->tx_dma_channel, uart_init->rx_dma_channel, HW_DMA_PRIO_2); - } - + if (uart_init->use_dma) { + hw_uart_set_dma_channels_ex(uart, uart_init->tx_dma_channel, uart_init->rx_dma_channel, HW_DMA_PRIO_2); + } #endif } void hw_uart_reinit(HW_UART_ID uart, const uart_config *uart_init) { - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); + /* + * Read UART_USR_REG to clear any pending busy interrupt. + */ + hw_uart_transmit_fifo_empty(uart); - if (uart == HW_UART2) - { - if (uart_init->use_fifo) - { - hw_uart_enable_fifo(uart); - hw_uart_rx_fifo_tr_lvl_setf(uart, 0); - hw_uart_tx_fifo_tr_lvl_setf(uart, 0); + if (uart == HW_UART2) { + if (uart_init->use_fifo) { + hw_uart_enable_fifo(uart); + hw_uart_rx_fifo_tr_lvl_setf(uart, 0); + hw_uart_tx_fifo_tr_lvl_setf(uart, 0); + } else { + hw_uart_disable_fifo(uart); + } } - else - { - hw_uart_disable_fifo(uart); - } - } - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rare - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); + // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); + // Set fraction byte of baud rate + UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; + // Set low byte of baud rate + UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); + // Set high byte of baud rare + UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); + // Reset Divisor Latch Access Bit in LCR register + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); + // Set Parity + UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; + // Set Data Bits + HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); + // Set Stop Bits + HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); + // Set Auto flow control + HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); + HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - if (ud->rx_cb && ud->rx_len != ud->rx_ix) - { - if (ud->rx_len > 1 && uart_init->use_dma && uart_init->rx_dma_channel != HW_DMA_CHANNEL_INVALID) - { + if (ud->rx_cb && ud->rx_len != ud->rx_ix) { + if (ud->rx_len > 1 && uart_init->use_dma && uart_init->rx_dma_channel != HW_DMA_CHANNEL_INVALID) { + } else { + // Interrupt driven + hw_uart_enable_rx_int(uart, true); + } } - else - { - // Interrupt driven - hw_uart_enable_rx_int(uart, true); - } - } } void hw_uart_cfg_get(HW_UART_ID uart, uart_config *uart_cfg) { #if HW_UART_USE_DMA_SUPPORT - UART_Data *ud = UARTDATA(uart); + UART_Data *ud = UARTDATA(uart); #endif - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Read baud rate low byte from DLL register - uart_cfg->baud_rate = (0xFF & UBA(uart)->UART2_RBR_THR_DLL_REG) << 8; - // Read baud rate high byte from DLH register - uart_cfg->baud_rate += (0xFF & UBA(uart)->UART2_IER_DLH_REG) << 16; - // Read baud rate fraction byte from DLF register - uart_cfg->baud_rate += 0xFF & UBA(uart)->UART2_DLF_REG; - // Reset Divisor Latch Access Bit in Line Control Register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); + // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); + // Read baud rate low byte from DLL register + uart_cfg->baud_rate = (0xFF & UBA(uart)->UART2_RBR_THR_DLL_REG) << 8; + // Read baud rate high byte from DLH register + uart_cfg->baud_rate += (0xFF & UBA(uart)->UART2_IER_DLH_REG) << 16; + // Read baud rate fraction byte from DLF register + uart_cfg->baud_rate += 0xFF & UBA(uart)->UART2_DLF_REG; + // Reset Divisor Latch Access Bit in Line Control Register + HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Fill-in the rest of the configuration settings - uart_cfg->data = HW_UART_REG_GETF(uart, LCR, UART_DLS); - uart_cfg->parity = UBA(uart)->UART2_LCR_REG; - uart_cfg->parity &= ((1 << UART_UART_LCR_REG_UART_EPS_Pos) | (1 << UART_UART_LCR_REG_UART_PEN_Pos)); - uart_cfg->parity = uart_cfg->parity >> UART_UART_LCR_REG_UART_PEN_Pos; - uart_cfg->stop = HW_UART_REG_GETF(uart, LCR, UART_STOP); + // Fill-in the rest of the configuration settings + uart_cfg->data = HW_UART_REG_GETF(uart, LCR, UART_DLS); + uart_cfg->parity = UBA(uart)->UART2_LCR_REG; + uart_cfg->parity &= ((1 << UART_UART_LCR_REG_UART_EPS_Pos) | (1 << UART_UART_LCR_REG_UART_PEN_Pos)); + uart_cfg->parity = uart_cfg->parity >> UART_UART_LCR_REG_UART_PEN_Pos; + uart_cfg->stop = HW_UART_REG_GETF(uart, LCR, UART_STOP); #if HW_UART_USE_DMA_SUPPORT - uart_cfg->tx_dma_channel = ud->tx_dma.channel_number; - uart_cfg->rx_dma_channel = ud->rx_dma.channel_number; - uart_cfg->use_dma = ud->use_dma; + uart_cfg->tx_dma_channel = ud->tx_dma.channel_number; + uart_cfg->rx_dma_channel = ud->rx_dma.channel_number; + uart_cfg->use_dma = ud->use_dma; #endif - uart_cfg->auto_flow_control = hw_uart_afce_getf(uart); + uart_cfg->auto_flow_control = hw_uart_afce_getf(uart); } //=========================== Modem control functions ========================== uint8_t hw_uart_sire_getf(HW_UART_ID uart) { - // Get the value of the SIRE bit from the Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MCR, UART_SIRE); + // Get the value of the SIRE bit from the Modem Control Register + return (uint8_t) HW_UART_REG_GETF(uart, MCR, UART_SIRE); } void hw_uart_sire_setf(HW_UART_ID uart, uint8_t sire) { - // Set the value of the SIRE bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_SIRE, sire); + // Set the value of the SIRE bit in the Modem Control Register + HW_UART_REG_SETF(uart, MCR, UART_SIRE, sire); } uint8_t hw_uart_afce_getf(HW_UART_ID uart) { - // Get the value of the AFCE bit from the Modem Control Register - return 0xFF & HW_UART_REG_GETF(uart, MCR, UART_AFCE); + // Get the value of the AFCE bit from the Modem Control Register + return 0xFF & HW_UART_REG_GETF(uart, MCR, UART_AFCE); } void hw_uart_afce_setf(HW_UART_ID uart, uint8_t afce) { - // Set the value of the AFCE bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_AFCE, afce); + // Set the value of the AFCE bit in the Modem Control Register + HW_UART_REG_SETF(uart, MCR, UART_AFCE, afce); } uint8_t hw_uart_loopback_getf(HW_UART_ID uart) { - // Get the value of the loop back (LB) bit from the Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MCR, UART_LB); + // Get the value of the loop back (LB) bit from the Modem Control Register + return (uint8_t) HW_UART_REG_GETF(uart, MCR, UART_LB); } void hw_uart_loopback_setf(HW_UART_ID uart, uint8_t lb) { - // Set the value of the loop back (LB) bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_LB, lb); + // Set the value of the loop back (LB) bit in the Modem Control Register + HW_UART_REG_SETF(uart, MCR, UART_LB, lb); } uint8_t hw_uart_rts_getf(HW_UART_ID uart) { - // Get the value of the RTS bit from the Modem Control Register - return 0xFF & HW_UART_REG_GETF(uart, MCR, UART_RTS); + // Get the value of the RTS bit from the Modem Control Register + return 0xFF & HW_UART_REG_GETF(uart, MCR, UART_RTS); } void hw_uart_rts_setf(HW_UART_ID uart, uint8_t rtsn) { - // Set the value of the RTS bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_RTS, rtsn); + // Set the value of the RTS bit in the Modem Control Register + HW_UART_REG_SETF(uart, MCR, UART_RTS, rtsn); } //=========================== Line status functions ============================ uint8_t hw_uart_rx_fifo_err_getf(HW_UART_ID uart) { - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - // Get Receiver FIFO Error bit - return (uint8_t) HW_UART_REG_GETF(uart, LSR, UART_RFE); + /* Only UART2 has a FIFO */ + ASSERT_ERROR(uart == HW_UART2); + // Get Receiver FIFO Error bit + return (uint8_t) HW_UART_REG_GETF(uart, LSR, UART_RFE); } uint8_t hw_uart_is_tx_fifo_empty(HW_UART_ID uart) { - // Get Transmitter Empty bit from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_TEMT) != 0; + // Get Transmitter Empty bit from Line Status Register + return HW_UART_REG_GETF(uart, LSR, UART_TEMT) != 0; } uint8_t hw_uart_thr_empty_getf(HW_UART_ID uart) { - // Get Transmit Holding Register Empty bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_THRE); + // Get Transmit Holding Register Empty bit value from Line Status Register + return HW_UART_REG_GETF(uart, LSR, UART_THRE); } uint8_t hw_uart_break_int_getf(HW_UART_ID uart) { - // Get Break Interrupt bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_BI); + // Get Break Interrupt bit value from Line Status Register + return HW_UART_REG_GETF(uart, LSR, UART_BI); } uint8_t hw_uart_frame_err_getf(HW_UART_ID uart) { - // Get Framing Error bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_FE); + // Get Framing Error bit value from Line Status Register + return HW_UART_REG_GETF(uart, LSR, UART_FE); } uint8_t hw_uart_parity_err_getf(HW_UART_ID uart) { - // Get Parity Error bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_PE); + // Get Parity Error bit value from Line Status Register + return HW_UART_REG_GETF(uart, LSR, UART_PE); } uint8_t hw_uart_overrun_err_getf(HW_UART_ID uart) { - // Get Overrun Error bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_OE); + // Get Overrun Error bit value from Line Status Register + return HW_UART_REG_GETF(uart, LSR, UART_OE); } //=========================== Modem status functions =========================== uint8_t hw_uart_cts_getf(HW_UART_ID uart) { - // Get CTS bit from Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MSR, UART_CTS); + // Get CTS bit from Modem Control Register + return (uint8_t) HW_UART_REG_GETF(uart, MSR, UART_CTS); } uint8_t hw_uart_delta_cts_getf(HW_UART_ID uart) { - // Get the DCTS bit value from the Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MSR, UART_DCTS); + // Get the DCTS bit value from the Modem Control Register + return (uint8_t) HW_UART_REG_GETF(uart, MSR, UART_DCTS); } bool hw_uart_tx_in_progress(HW_UART_ID uart) { - UART_Data *ud = UARTDATA(uart); - return ud->tx_cb != NULL; + UART_Data *ud = UARTDATA(uart); + return ud->tx_cb != NULL; } bool hw_uart_rx_in_progress(HW_UART_ID uart) { - UART_Data *ud = UARTDATA(uart); - return ud->rx_cb != NULL; + UART_Data *ud = UARTDATA(uart); + return ud->rx_cb != NULL; } #endif /* dg_configUSE_HW_UART */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c index 5c764b3b6..78a90e3f9 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c @@ -62,101 +62,94 @@ static hw_watchdog_interrupt_cb int_handler __RETAINED = NULL; bool hw_watchdog_freeze(void) { - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; + GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; - return !REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST); + return !REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST); } void hw_watchdog_unfreeze(void) { - GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk; + GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk; } HW_WDG_RESET hw_watchdog_is_irq_or_rst_gen(void) { - if (REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST)) - { - return HW_WDG_RESET_RST; - } + if (REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST)) { + return HW_WDG_RESET_RST; + } - return HW_WDG_RESET_NMI; + return HW_WDG_RESET_NMI; } void hw_watchdog_register_int(hw_watchdog_interrupt_cb handler) { - int_handler = handler; + int_handler = handler; } void hw_watchdog_unregister_int(void) { - int_handler = NULL; + int_handler = NULL; } __RETAINED_CODE void hw_watchdog_handle_int(unsigned long *exception_args) { - // Reached this point due to a WDOG timeout - uint16_t pmu_ctrl_reg = CRG_TOP->PMU_CTRL_REG; - pmu_ctrl_reg |= ((1 << CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos) | /* turn off BLE */ - (1 << CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos) | /* turn off FTDF */ - (1 << CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos) | /* turn off radio PD */ - (1 << CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos)); /* turn off peripheral power domain */ - CRG_TOP->PMU_CTRL_REG = pmu_ctrl_reg; - REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, BLE_LP_RESET); /* reset the BLE LP timer */ + // Reached this point due to a WDOG timeout + uint16_t pmu_ctrl_reg = CRG_TOP->PMU_CTRL_REG; + pmu_ctrl_reg |= ((1 << CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos) | /* turn off BLE */ + (1 << CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos) | /* turn off FTDF */ + (1 << CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos) | /* turn off radio PD */ + (1 << CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos)); /* turn off peripheral power domain */ + CRG_TOP->PMU_CTRL_REG = pmu_ctrl_reg; + REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, BLE_LP_RESET); /* reset the BLE LP timer */ #if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) - hw_watchdog_freeze(); // Stop WDOG + hw_watchdog_freeze(); // Stop WDOG - ENABLE_DEBUGGER; + ENABLE_DEBUGGER; - if (exception_args != NULL) - { - *(volatile unsigned long *)(STATUS_BASE) = exception_args[0]; // R0 - *(volatile unsigned long *)(STATUS_BASE + 0x04) = exception_args[1]; // R1 - *(volatile unsigned long *)(STATUS_BASE + 0x08) = exception_args[2]; // R2 - *(volatile unsigned long *)(STATUS_BASE + 0x0C) = exception_args[3]; // R3 - *(volatile unsigned long *)(STATUS_BASE + 0x10) = exception_args[4]; // R12 - *(volatile unsigned long *)(STATUS_BASE + 0x14) = exception_args[5]; // LR - *(volatile unsigned long *)(STATUS_BASE + 0x18) = exception_args[6]; // PC - *(volatile unsigned long *)(STATUS_BASE + 0x1C) = exception_args[7]; // PSR - *(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)exception_args; // Stack Pointer + if (exception_args != NULL) { + *(volatile unsigned long *)(STATUS_BASE ) = exception_args[0]; // R0 + *(volatile unsigned long *)(STATUS_BASE + 0x04) = exception_args[1]; // R1 + *(volatile unsigned long *)(STATUS_BASE + 0x08) = exception_args[2]; // R2 + *(volatile unsigned long *)(STATUS_BASE + 0x0C) = exception_args[3]; // R3 + *(volatile unsigned long *)(STATUS_BASE + 0x10) = exception_args[4]; // R12 + *(volatile unsigned long *)(STATUS_BASE + 0x14) = exception_args[5]; // LR + *(volatile unsigned long *)(STATUS_BASE + 0x18) = exception_args[6]; // PC + *(volatile unsigned long *)(STATUS_BASE + 0x1C) = exception_args[7]; // PSR + *(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)exception_args; // Stack Pointer - *(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR - *(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR - *(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR - *(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR - *(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR - *(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR - } + *(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR + *(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR + *(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR + *(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR + *(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR + *(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR + } - hw_cpm_assert_trigger_gpio(); + hw_cpm_assert_trigger_gpio(); - if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE)) - { - __BKPT(0); - } - else - { - while (1); - } + if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE)) { + __BKPT(0); + } + else { + while (1); + } #else // dg_configIMAGE_SETUP == DEVELOPMENT_MODE + if (exception_args != NULL) { + nmi_event_data[0] = NMI_MAGIC_NUMBER; + nmi_event_data[1] = exception_args[0]; // R0 + nmi_event_data[2] = exception_args[1]; // R1 + nmi_event_data[3] = exception_args[2]; // R2 + nmi_event_data[4] = exception_args[3]; // R3 + nmi_event_data[5] = exception_args[4]; // R12 + nmi_event_data[6] = exception_args[5]; // LR + nmi_event_data[7] = exception_args[6]; // PC + nmi_event_data[8] = exception_args[7]; // PSR + } - if (exception_args != NULL) - { - nmi_event_data[0] = NMI_MAGIC_NUMBER; - nmi_event_data[1] = exception_args[0]; // R0 - nmi_event_data[2] = exception_args[1]; // R1 - nmi_event_data[3] = exception_args[2]; // R2 - nmi_event_data[4] = exception_args[3]; // R3 - nmi_event_data[5] = exception_args[4]; // R12 - nmi_event_data[6] = exception_args[5]; // LR - nmi_event_data[7] = exception_args[6]; // PC - nmi_event_data[8] = exception_args[7]; // PSR - } - - // Wait for the reset to occur - while (1); - + // Wait for the reset to occur + while (1); #endif // dg_configIMAGE_SETUP == DEVELOPMENT_MODE } @@ -164,14 +157,12 @@ __RETAINED_CODE void NMI_HandlerC(unsigned long *exception_args); void NMI_HandlerC(unsigned long *exception_args) { - if (int_handler) - { - int_handler(exception_args); - } - else - { - hw_watchdog_handle_int(exception_args); - } + if (int_handler) { + int_handler(exception_args); + } + else { + hw_watchdog_handle_int(exception_args); + } } /** diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c index 5b2de0bfb..b97f2d192 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c @@ -8,7 +8,7 @@ */ /** -**************************************************************************************** + **************************************************************************************** * * @file sys_tcs.c * @@ -16,37 +16,36 @@ * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, + * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation + * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without * specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * * -**************************************************************************************** -*/ + **************************************************************************************** + */ #include #include "hw_cpm.h" #include "sys_tcs.h" #include "hw_gpadc.h" -#include "hw_gpio.h" #define APPEND_TCS_LENGTH (0) @@ -78,58 +77,57 @@ bool sys_tcs_is_calibrated_chip __RETAINED_UNINIT; // Initial value: false * Local variables */ -static const uint32_t uncalibrated_tcs_data[] = -{ - /* BANDGAP_REG: (offset 0) - * [14]: BYPASS_COLD_BOOT_DISABLE = 0 - * [13:10]: LDO_SLEEP_TRIM = 0x4 - * [9:5]: BGR_ITRIM = 0x00 - * [4:0]: BGR_TRIM = 0x13 (change until V12 is 1.2V) - * - * Especially for this register, merge the trimmed and preferred settings. - */ - (uint32_t) &CRG_TOP->BANDGAP_REG, 0x1013, +static const uint32_t uncalibrated_tcs_data[] = { + /* BANDGAP_REG: (offset 0) + * [14]: BYPASS_COLD_BOOT_DISABLE = 0 + * [13:10]: LDO_SLEEP_TRIM = 0x4 + * [9:5]: BGR_ITRIM = 0x00 + * [4:0]: BGR_TRIM = 0x13 (change until V12 is 1.2V) + * + * Especially for this register, merge the trimmed and preferred settings. + */ + (uint32_t)&CRG_TOP->BANDGAP_REG, 0x1013, - /* CLK_FREQ_TRIM_REG: (offset 2) - * [10:8]: COARSE_ADJ = 0x4 - * [7:0]: FINE_ADJ = 0x60 - */ - (uint32_t) &CRG_TOP->CLK_FREQ_TRIM_REG, 0x0460, + /* CLK_FREQ_TRIM_REG: (offset 2) + * [10:8]: COARSE_ADJ = 0x4 + * [7:0]: FINE_ADJ = 0x60 + */ + (uint32_t)&CRG_TOP->CLK_FREQ_TRIM_REG, 0x0460, - /* CLK_16M_REG: (offset 4) - * [15]: RC16M_STARTUP_DISABLE = 0 - * [14]: XTAL16_HPASS_FLT_EN = 0 - * [13]: XTAL16_SPIKE_FLT_BYPASS = 0 - * [12:10]: XTAL16_AMP_TRIM = 0x5 - * [9]: XTAL16_EXT_CLK_ENABLE = 0 - * [8]: XTAL16_MAX_CURRENT = 0 - * [7:5]: XTAL16_CUR_SET = 0x5 - * [4:1]: RC16M_TRIM = 0x9 - * [0]: RC16M_ENABLE = 0 - * - * Apply the trimmed and a default preferred value. The correct one is applied - * later. - */ - (uint32_t) &CRG_TOP->CLK_16M_REG, 0x14B2, + /* CLK_16M_REG: (offset 4) + * [15]: RC16M_STARTUP_DISABLE = 0 + * [14]: XTAL16_HPASS_FLT_EN = 0 + * [13]: XTAL16_SPIKE_FLT_BYPASS = 0 + * [12:10]: XTAL16_AMP_TRIM = 0x5 + * [9]: XTAL16_EXT_CLK_ENABLE = 0 + * [8]: XTAL16_MAX_CURRENT = 0 + * [7:5]: XTAL16_CUR_SET = 0x5 + * [4:1]: RC16M_TRIM = 0x9 + * [0]: RC16M_ENABLE = 0 + * + * Apply the trimmed and a default preferred value. The correct one is applied + * later. + */ + (uint32_t)&CRG_TOP->CLK_16M_REG, 0x14B2, - /* CLK_32K_REG: (offset 6) - * [15:13]: 0 - * [12]: XTAL32K_DISABLE_AMPREG0 = 0 - * [11:8]: RC32K_TRIM = 0x07 - * [7]: RC32K_ENABLE = 0x1 (reset value) - * [6:3]: XTAL32K_CUR = 0x3 (reset value) - * [2:1]: XTAL32K_RBIAS = 0x2 (reset value) - * [0]: XTAL32K_ENABLE = 0 - */ - (uint32_t) &CRG_TOP->CLK_32K_REG, 0x79C, + /* CLK_32K_REG: (offset 6) + * [15:13]: 0 + * [12]: XTAL32K_DISABLE_AMPREG0 = 0 + * [11:8]: RC32K_TRIM = 0x07 + * [7]: RC32K_ENABLE = 0x1 (reset value) + * [6:3]: XTAL32K_CUR = 0x3 (reset value) + * [2:1]: XTAL32K_RBIAS = 0x2 (reset value) + * [0]: XTAL32K_ENABLE = 0 + */ + (uint32_t)&CRG_TOP->CLK_32K_REG, 0x79C, - /* CHARGER_CTRL2_REG: (offset 8) - * [15:13]: 0 - * [12:8]: CURRENT_OFFSET_TRIM = 0x0C - * [7:4]: CHARGER_VFLOAT_ADJ = 0x5 - * [3:0]: CURRENT_GAIN_TRIM = 0xA - */ - (uint32_t) &ANAMISC->CHARGER_CTRL2_REG, 0x0C5A, + /* CHARGER_CTRL2_REG: (offset 8) + * [15:13]: 0 + * [12:8]: CURRENT_OFFSET_TRIM = 0x0C + * [7:4]: CHARGER_VFLOAT_ADJ = 0x5 + * [3:0]: CURRENT_GAIN_TRIM = 0xA + */ + (uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 0x0C5A, }; #define UNCALIBRATED_DATA_NON_RETAINED_OFFSET (8) @@ -176,14 +174,12 @@ static const uint32_t uncalibrated_tcs_data[] = */ static void apply_pair(uint32_t address, uint32_t value) { - if (address & 0x2) - { - *(volatile uint16_t *)address = value; - } - else - { - *(volatile uint32_t *)address = value; - } + if (address & 0x2) { + *(volatile uint16_t *)address = value; + } + else { + *(volatile uint32_t *)address = value; + } } /** @@ -195,17 +191,15 @@ static void apply_pair(uint32_t address, uint32_t value) */ static void apply_entry(uint8_t index) { - uint32_t address = tcs_ptr[index]; - uint32_t value = tcs_ptr[index + 1]; + uint32_t address = tcs_ptr[index]; + uint32_t value = tcs_ptr[index + 1]; - if (address & 0x2) - { - *(volatile uint16_t *)address = value; - } - else - { - *(volatile uint32_t *)address = value; - } + if (address & 0x2) { + *(volatile uint16_t *)address = value; + } + else { + *(volatile uint32_t *)address = value; + } } /** @@ -217,10 +211,10 @@ static void apply_entry(uint8_t index) */ static void store_in_array(uint32_t address, uint32_t value) { - tcs_data[tcs_length] = address; - tcs_length++; - tcs_data[tcs_length] = value; - tcs_length++; + tcs_data[tcs_length] = address; + tcs_length++; + tcs_data[tcs_length] = value; + tcs_length++; } /** @@ -234,15 +228,15 @@ static void store_in_array(uint32_t address, uint32_t value) */ static void swap_entries(uint32_t first_pos, uint32_t second_pos) { - uint32_t address_stored; - uint32_t value_stored; + uint32_t address_stored; + uint32_t value_stored; - address_stored = tcs_data[second_pos]; - value_stored = tcs_data[second_pos + 1]; - tcs_data[second_pos] = tcs_data[first_pos]; - tcs_data[second_pos + 1] = tcs_data[first_pos + 1]; - tcs_data[first_pos] = address_stored; - tcs_data[first_pos + 1] = value_stored; + address_stored = tcs_data[second_pos]; + value_stored = tcs_data[second_pos + 1]; + tcs_data[second_pos] = tcs_data[first_pos]; + tcs_data[second_pos + 1] = tcs_data[first_pos + 1]; + tcs_data[first_pos] = address_stored; + tcs_data[first_pos + 1] = value_stored; } /** @@ -260,240 +254,197 @@ static void swap_entries(uint32_t first_pos, uint32_t second_pos) */ static int sys_tcs_sort_area(uint32_t area_base, uint32_t area_size, uint32_t array_ptr, uint8_t *ptr, uint8_t *size) { - uint32_t i = array_ptr; - uint32_t sort_start; - uint32_t sort_end; + uint32_t i = array_ptr; + uint32_t sort_start; + uint32_t sort_end; - if (array_ptr == tcs_length) - { - return array_ptr; // Nothing else is left in the array or tcs_length is zero - } - - sort_start = array_ptr; - sort_end = array_ptr; - - /* Make sure that the values in TCS don't overflow the allocated array */ - ASSERT_WARNING(tcs_length <= sizeof(tcs_data) / sizeof(tcs_data[0])); - - while (i < (tcs_length - 1)) - { - if (IS_IN_AREA(tcs_data[i], area_base, area_size)) - { - if (i == array_ptr) - { - if (sort_start == array_ptr) - { - sort_start = array_ptr; - sort_end = sort_start + 2; - } - } - else - { - // Copy it to the proper place. - if (i != sort_end) - { - swap_entries(sort_end, i); - } - - sort_end += 2; - } + if (array_ptr == tcs_length) { + return array_ptr; // Nothing else is left in the array or tcs_length is zero } - i += 2; - } + sort_start = array_ptr; + sort_end = array_ptr; - *ptr = sort_start; - *size = sort_end - sort_start; + /* Make sure that the values in TCS don't overflow the allocated array */ + ASSERT_WARNING(tcs_length <= sizeof(tcs_data)/sizeof(tcs_data[0])); - return sort_end; + while (i < (tcs_length - 1)) { + if (IS_IN_AREA(tcs_data[i], area_base, area_size)) { + if (i == array_ptr) { + if (sort_start == array_ptr) { + sort_start = array_ptr; + sort_end = sort_start + 2; + } + } + else { + // Copy it to the proper place. + if (i != sort_end) { + swap_entries(sort_end, i); + } + sort_end += 2; + } + } + i += 2; + } + + *ptr = sort_start; + *size = sort_end - sort_start; + + return sort_end; } void sys_tcs_init(void) { - tcs_length = 0; - sys_tcs_is_calibrated_chip = false; - hw_cpm_bod_enabled_in_tcs = 0; + tcs_length = 0; + sys_tcs_is_calibrated_chip = false; + hw_cpm_bod_enabled_in_tcs = 0; } bool sys_tcs_store_pair(uint32_t address, uint32_t value) { - // If it stops here then tcs_length must become uint16_t. - ASSERT_WARNING((256 * sizeof(tcs_length)) >= (24 * 2 + APPEND_TCS_LENGTH)); + // If it stops here then tcs_length must become uint16_t. + ASSERT_WARNING( (256 * sizeof(tcs_length)) >= (24 * 2 + APPEND_TCS_LENGTH) ); - // Check if the address is in Always-ON or of a retained register and apply it. - if (IS_IN_AREA(address, CRG_TOP_BASE, sizeof(CRG_TOP_Type)) - || IS_IN_AREA(address, TIMER1_BASE, sizeof(TIMER1_Type)) - || IS_IN_AREA(address, WAKEUP_BASE, sizeof(WAKEUP_Type)) - || IS_IN_AREA(address, DCDC_BASE, sizeof(DCDC_Type)) - || IS_IN_AREA(address, QSPIC_BASE, sizeof(QSPIC_Type)) - || IS_IN_AREA(address, CACHE_BASE, sizeof(CACHE_Type)) - || IS_IN_AREA(address, OTPC_BASE, sizeof(OTPC_Type))) - { - if (address == (uint32_t)&CRG_TOP->BANDGAP_REG) - { - sys_tcs_is_calibrated_chip = true; - } - else if (address == (uint32_t)&CRG_TOP->CLK_16M_REG) - { - value |= CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk; // Make sure that RC16 is enabled! - } - else if (address == (uint32_t)&CRG_TOP->XTALRDY_CTRL_REG) - { - sys_tcs_xtal16m_settling_time = value; - } - else if (address == (uint32_t)&CRG_TOP->BOD_CTRL2_REG) - { - hw_cpm_bod_enabled_in_tcs = value; - /* - * Read the ADC Gain Error. Given that the Chip Configuration Section - * (CCS) of OTP is out of space, the values are stored in the TCS section - * using as address the read-only register SYS_STAT_REG. - * The 16 LSB of the 32bit data-value is the single ended gain error. - * The 16 MSB of the 32bit data-value is the differential gain error. - * Both gain error values should be interpreted as signed 16bit integers. - */ - } - else if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) - { - if (address == (uint32_t)&CRG_TOP->SYS_STAT_REG) - { - hw_gpadc_store_se_gain_error(ADC_SE_GAIN_ERROR(value)); - hw_gpadc_store_diff_gain_error(ADC_DIFF_GAIN_ERROR(value)); - } + // Check if the address is in Always-ON or of a retained register and apply it. + if (IS_IN_AREA(address, CRG_TOP_BASE, sizeof(CRG_TOP_Type)) + || IS_IN_AREA(address, TIMER1_BASE, sizeof(TIMER1_Type)) + || IS_IN_AREA(address, WAKEUP_BASE, sizeof(WAKEUP_Type)) + || IS_IN_AREA(address, DCDC_BASE, sizeof(DCDC_Type)) + || IS_IN_AREA(address, QSPIC_BASE, sizeof(QSPIC_Type)) + || IS_IN_AREA(address, CACHE_BASE, sizeof(CACHE_Type)) + || IS_IN_AREA(address, OTPC_BASE, sizeof(OTPC_Type))) { + if (address == (uint32_t)&CRG_TOP->BANDGAP_REG) { + sys_tcs_is_calibrated_chip = true; + } else if (address == (uint32_t)&CRG_TOP->CLK_16M_REG) { + value |= CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk; // Make sure that RC16 is enabled! + } else if (address == (uint32_t)&CRG_TOP->XTALRDY_CTRL_REG) { + sys_tcs_xtal16m_settling_time = value; + } else if (address == (uint32_t)&CRG_TOP->BOD_CTRL2_REG) { + hw_cpm_bod_enabled_in_tcs = value; + /* + * Read the ADC Gain Error. Given that the Chip Configuration Section + * (CCS) of OTP is out of space, the values are stored in the TCS section + * using as address the read-only register SYS_STAT_REG. + * The 16 LSB of the 32bit data-value is the single ended gain error. + * The 16 MSB of the 32bit data-value is the differential gain error. + * Both gain error values should be interpreted as signed 16bit integers. + */ + } else if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) { + if (address == (uint32_t)&CRG_TOP->SYS_STAT_REG) { + hw_gpadc_store_se_gain_error(ADC_SE_GAIN_ERROR(value)); + hw_gpadc_store_diff_gain_error(ADC_DIFF_GAIN_ERROR(value)); + } + } + apply_pair(address, value); + } else { + store_in_array(address, value); } - apply_pair(address, value); - } - else - { - store_in_array(address, value); - } - - return sys_tcs_is_calibrated_chip; + return sys_tcs_is_calibrated_chip; } void sys_tcs_sort_array(void) { - int entry_ptr = 0; - int i; + int entry_ptr = 0; + int i; - /* - * Apply a default value to CLK_FREQ_TRIM_REG, if not set in TCS. - * [10:8]: COARSE_ADJ = 0x4 - * [7:0]: FINE_ADJ = 0x60 - */ - if (CRG_TOP->CLK_FREQ_TRIM_REG == 0) - { - CRG_TOP->CLK_FREQ_TRIM_REG = 0x0460; - } + /* + * Apply a default value to CLK_FREQ_TRIM_REG, if not set in TCS. + * [10:8]: COARSE_ADJ = 0x4 + * [7:0]: FINE_ADJ = 0x60 + */ + if (CRG_TOP->CLK_FREQ_TRIM_REG == 0) { + CRG_TOP->CLK_FREQ_TRIM_REG = 0x0460; + } - if (sys_tcs_is_calibrated_chip) - { + if (sys_tcs_is_calibrated_chip) { #ifdef CONFIG_USE_BLE - entry_ptr = sys_tcs_sort_area(BLE_BASE, sizeof(BLE_Type), entry_ptr, - &area_offset[tcs_ble], &area_size[tcs_ble]); + entry_ptr = sys_tcs_sort_area(BLE_BASE, sizeof(BLE_Type), entry_ptr, + &area_offset[tcs_ble], &area_size_global[tcs_ble]); #endif #ifdef CONFIG_USE_FTDF - entry_ptr = sys_tcs_sort_area(FTDF_BASE, sizeof(FTDF_Type), entry_ptr, - &area_offset[tcs_ftdf], &area_size_global[tcs_ftdf]); + entry_ptr = sys_tcs_sort_area(FTDF_BASE, sizeof(FTDF_Type), entry_ptr, + &area_offset[tcs_ftdf], &area_size_global[tcs_ftdf]); #endif - entry_ptr = sys_tcs_sort_area(RFCU_BASE, RADIO_AREA_SIZE, entry_ptr, - &area_offset[tcs_radio], &area_size_global[tcs_radio]); + entry_ptr = sys_tcs_sort_area(RFCU_BASE, RADIO_AREA_SIZE, entry_ptr, + &area_offset[tcs_radio], &area_size_global[tcs_radio]); - entry_ptr = sys_tcs_sort_area((uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 1, entry_ptr, - &area_offset[tcs_charger], &area_size_global[tcs_charger]); + entry_ptr = sys_tcs_sort_area((uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 1, entry_ptr, + &area_offset[tcs_charger], &area_size_global[tcs_charger]); - entry_ptr = sys_tcs_sort_area(APU_BASE, sizeof(APU_Type), entry_ptr, - &area_offset[tcs_audio], &area_size_global[tcs_audio]); + entry_ptr = sys_tcs_sort_area(APU_BASE, sizeof(APU_Type), entry_ptr, + &area_offset[tcs_audio], &area_size_global[tcs_audio]); - // The rest should be System. Assert if not! - for (i = entry_ptr; i < tcs_length; i += 2) - { - if (IS_IN_AREA(tcs_data[i], UART_BASE, PERIPHERAL_AREA_SIZE)) - { - ASSERT_WARNING(0); - } + // The rest should be System. Assert if not! + for (i = entry_ptr; i < tcs_length; i += 2) { + if (IS_IN_AREA(tcs_data[i], UART_BASE, PERIPHERAL_AREA_SIZE)) { + ASSERT_WARNING(0); + } - if (IS_IN_AREA(tcs_data[i], CRG_TOP_BASE, 0x6100)) - { - // It is ok (most probably). - } - else - { - ASSERT_WARNING(0); - } + if (IS_IN_AREA(tcs_data[i], CRG_TOP_BASE, 0x6100)) { + // It is ok (most probably). + } + else { + ASSERT_WARNING(0); + } + } + area_offset[tcs_system] = entry_ptr; + area_size_global[tcs_system] = tcs_length - entry_ptr; + + tcs_ptr = tcs_data; } + else { + tcs_ptr = uncalibrated_tcs_data; - area_offset[tcs_system] = entry_ptr; - area_size_global[tcs_system] = tcs_length - entry_ptr; - - tcs_ptr = tcs_data; - } - else - { - tcs_ptr = uncalibrated_tcs_data; - - for (i = 0; i < UNCALIBRATED_DATA_NON_RETAINED_OFFSET; i += 2) - { - apply_pair(tcs_ptr[i], tcs_ptr[i + 1]); - } + for (i = 0; i < UNCALIBRATED_DATA_NON_RETAINED_OFFSET; i += 2) { + apply_pair(tcs_ptr[i], tcs_ptr[i + 1]); + } #ifdef CONFIG_USE_BLE - - if (UNCALIBRATED_DATA_BLE_SIZE > 0) - { - area_offset[tcs_ble] = UNCALIBRATED_DATA_BLE_OFFSET; - area_size[tcs_ble] = UNCALIBRATED_DATA_BLE_SIZE; - } - + if (UNCALIBRATED_DATA_BLE_SIZE > 0) { + area_offset[tcs_ble] = UNCALIBRATED_DATA_BLE_OFFSET; + area_size_global[tcs_ble] = UNCALIBRATED_DATA_BLE_SIZE; + } #endif #ifdef CONFIG_USE_FTDF - - if (UNCALIBRATED_DATA_FTDF_SIZE > 0) - { - area_offset[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_OFFSET; - area_size_global[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_SIZE; - } - + if (UNCALIBRATED_DATA_FTDF_SIZE > 0) { + area_offset[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_OFFSET; + area_size_global[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_SIZE; + } #endif - if (UNCALIBRATED_DATA_RADIO_SIZE > 0) - { - area_offset[tcs_radio] = UNCALIBRATED_DATA_RADIO_OFFSET; - area_size_global[tcs_radio] = UNCALIBRATED_DATA_RADIO_SIZE; - } + if (UNCALIBRATED_DATA_RADIO_SIZE > 0) { + area_offset[tcs_radio] = UNCALIBRATED_DATA_RADIO_OFFSET; + area_size_global[tcs_radio] = UNCALIBRATED_DATA_RADIO_SIZE; + } - if (UNCALIBRATED_DATA_CHARGER_SIZE > 0) - { - area_offset[tcs_charger] = UNCALIBRATED_DATA_CHARGER_OFFSET; - area_size_global[tcs_charger] = UNCALIBRATED_DATA_CHARGER_SIZE; - } + if (UNCALIBRATED_DATA_CHARGER_SIZE > 0) { + area_offset[tcs_charger] = UNCALIBRATED_DATA_CHARGER_OFFSET; + area_size_global[tcs_charger] = UNCALIBRATED_DATA_CHARGER_SIZE; + } - if (UNCALIBRATED_DATA_AUDIO_SIZE > 0) - { - area_offset[tcs_audio] = UNCALIBRATED_DATA_AUDIO_OFFSET; - area_size_global[tcs_audio] = UNCALIBRATED_DATA_AUDIO_SIZE; - } + if (UNCALIBRATED_DATA_AUDIO_SIZE > 0) { + area_offset[tcs_audio] = UNCALIBRATED_DATA_AUDIO_OFFSET; + area_size_global[tcs_audio] = UNCALIBRATED_DATA_AUDIO_SIZE; + } - if (UNCALIBRATED_DATA_SYSTEM_SIZE > 0) - { - area_offset[tcs_system] = UNCALIBRATED_DATA_SYSTEM_OFFSET; - area_size_global[tcs_system] = UNCALIBRATED_DATA_SYSTEM_SIZE; + if (UNCALIBRATED_DATA_SYSTEM_SIZE > 0) { + area_offset[tcs_system] = UNCALIBRATED_DATA_SYSTEM_OFFSET; + area_size_global[tcs_system] = UNCALIBRATED_DATA_SYSTEM_SIZE; + } } - } } void sys_tcs_apply(sys_tcs_area_t area) { - int i; + int i; - for (i = area_offset[area]; i < (area_offset[area] + area_size_global[area]); i += 2) - { - apply_entry(i); - } + for (i = area_offset[area]; i < (area_offset[area] + area_size_global[area]); i += 2) { + apply_entry(i); + } } /** diff --git a/third_party/dialog/DialogSDK/bsp/startup/config.c b/third_party/dialog/DialogSDK/bsp/startup/config.c index 9fa26c60d..4a2b82304 100755 --- a/third_party/dialog/DialogSDK/bsp/startup/config.c +++ b/third_party/dialog/DialogSDK/bsp/startup/config.c @@ -1,19 +1,37 @@ /** -**************************************************************************************** -* -* @file config.c -* -* @brief Configure system. -* -* Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer -* program includes Confidential, Proprietary Information and is a Trade Secret of -* Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited -* unless authorized in writing. All Rights Reserved. -* -* and contributors. -* -**************************************************************************************** -*/ + **************************************************************************************** + * + * @file config.c + * + * @brief Configure system. + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ /** \addtogroup BSP diff --git a/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c b/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c index 118c06fa9..2e7339544 100755 --- a/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c +++ b/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c @@ -203,7 +203,7 @@ static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entr if ((address == 0) && (value == 0)) { if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E)) || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) - && (CHIP_IS_AE || CHIP_IS_BA))) { + && (CHIP_IS_AE || CHIP_IS_BB))) { if (!forward_reading) { break; } @@ -429,7 +429,7 @@ void SystemInit(void) if (dg_configUSE_AUTO_CHIP_DETECTION == 1) { black_orca_chip_version = black_orca_get_chip_version(); - if (!CHIP_IS_AE && !CHIP_IS_BA) { + if (!CHIP_IS_AE && !CHIP_IS_BB) { // Oldest supported version is AE. ASSERT_WARNING_UNINIT(0); } diff --git a/third_party/dialog/DialogSDK/bsp/startup/vector_table.S b/third_party/dialog/DialogSDK/bsp/startup/vector_table.S index ea26c7961..2700c1777 100755 --- a/third_party/dialog/DialogSDK/bsp/startup/vector_table.S +++ b/third_party/dialog/DialogSDK/bsp/startup/vector_table.S @@ -5,15 +5,34 @@ * * @brief Interrupt Vector Table and Patch Table * - * Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer - * program includes Confidential, Proprietary Information and is a Trade Secret of - * Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited - * unless authorized in writing. All Rights Reserved. + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. * - * and contributors. * **************************************************************************************** */ + .syntax unified .arch armv6-m diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h index 777c87cb0..26a3858b7 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h @@ -7,6 +7,7 @@ /** **************************************************************************************** + * * @file ad_ftdf_config.h * * @brief FTDF Adapter API @@ -105,7 +106,7 @@ * \brief Sleep value compensation * * Defines the sleep value compensation expressed in microseconds. This value - * is subtracted from the sleep time returned by FTDF_canSleep( ) + * is subtracted from the sleep time returned by ftdf_can_sleep() */ #define AD_FTDF_SLEEP_COMPENSATION 1500 diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h index d096c6956..4b878cf8c 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h @@ -7,6 +7,7 @@ /** **************************************************************************************** + * * @file ad_ftdf_phy_api.h * * @brief FTDF PHY Adapter API @@ -58,7 +59,7 @@ void ad_ftdf_init(void); * * \param[in] address - The extended address to set */ -void ad_ftdf_setExtAddress( FTDF_ExtAddress address); +void ad_ftdf_set_ext_address(ftdf_ext_address_t address); /** * \brief Get Extended Address @@ -67,24 +68,24 @@ void ad_ftdf_setExtAddress( FTDF_ExtAddress address); * * \returns The extended address of the interface */ -FTDF_ExtAddress ad_ftdf_getExtAddress( void); +ftdf_ext_address_t ad_ftdf_get_ext_address(void); /** * \brief Transmits a frame * * Transmits a frame. Params: * - * \param[in] frameLength - The total length of the frame passed in bytes + * \param[in] frame_length - The total length of the frame passed in bytes * \param[in] frame - a pointer to the passed frame buffer * \param[in] channel - The channel to use for transmission in [11, 26] - * \param[in] csmaSuppress - If true, csma protocol (i.e. CCA) will not be performed + * \param[in] csma_suppress - If true, csma protocol (i.e. CCA) will not be performed * \param[in] pti - Packet Traffic Information that will be used for this transaction. */ -FTDF_Status ad_ftdf_send_frame_simple( FTDF_DataLength frameLength, - FTDF_Octet* frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean csmaSuppress); +ftdf_status_t ad_ftdf_send_frame_simple(ftdf_data_length_t frame_length, + ftdf_octet_t* frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t csma_suppress); /** * \brief Instructs the MAC and PHY to go to sleep @@ -94,7 +95,7 @@ FTDF_Status ad_ftdf_send_frame_simple( FTDF_DataLength frameLength, * as soon as possible. If false, and the MAC cannot go to sleep * immediately, sleep will be aborted. */ -void ad_ftdf_sleep_when_possible( FTDF_Boolean allow_deferred_sleep); +void ad_ftdf_sleep_when_possible(ftdf_boolean_t allow_deferred_sleep); /** * \brief Instructs the MAC and PHY to wakeup, if sleeping @@ -106,7 +107,7 @@ void ad_ftdf_wake_up(void); /** * \brief Configures GPIO pins for the FTDF debug bus * - * Debug bus uses the following (fixed) GPIO pins: + * if FTDF_DBG_BUS_USE_PORT_4 == 0, the FTDF debug bus uses the following (fixed) GPIO pins, * * bit 0: HW_GPIO_PORT_1, HW_GPIO_PIN_4 * bit 1: HW_GPIO_PORT_1, HW_GPIO_PIN_5 @@ -116,8 +117,20 @@ void ad_ftdf_wake_up(void); * bit 5: HW_GPIO_PORT_0, HW_GPIO_PIN_7 * bit 6: HW_GPIO_PORT_1, HW_GPIO_PIN_3 * bit 7: HW_GPIO_PORT_2, HW_GPIO_PIN_3 + * + * if FTDF_DBG_BUS_USE_PORT_4 == 1, the FTDF debug bus uses the following pins: + * + * bit 0: HW_GPIO_PORT_4, HW_GPIO_PIN_0 + * bit 1: HW_GPIO_PORT_4, HW_GPIO_PIN_1 + * bit 2: HW_GPIO_PORT_4, HW_GPIO_PIN_2 + * bit 3: HW_GPIO_PORT_4, HW_GPIO_PIN_3 + * bit 4: HW_GPIO_PORT_4, HW_GPIO_PIN_4 + * bit 5: HW_GPIO_PORT_4, HW_GPIO_PIN_5 + * bit 6: HW_GPIO_PORT_4, HW_GPIO_PIN_6 + * bit 7: HW_GPIO_PORT_4, HW_GPIO_PIN_7 + * */ -void ad_ftdf_dbgBusGpioConfig(void); +void ad_ftdf_dbg_bus_gpio_config(void); #endif /* FTDF_DBG_BUS_ENABLE */ #endif /* AD_FTDF_PHY_API_H */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h index 8398c6ace..3b0b157bd 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h @@ -107,7 +107,7 @@ #define FTDF_TRANSPARENT_RCV_UNEXP_BEACON 0x00000040 #define FTDF_TRANSPARENT_RCV_UNEXP_NO_DEST_ADDR 0x00000080 -typedef uint8_t FTDF_MsgId; +typedef uint8_t ftdf_msg_id_t; #define FTDF_DATA_REQUEST 1 #define FTDF_DATA_INDICATION 2 #define FTDF_DATA_CONFIRM 3 @@ -164,9 +164,8 @@ typedef uint8_t FTDF_MsgId; #if FTDF_DBG_BUS_ENABLE #define FTDF_DBG_MODE_SET_REQUEST 54 #endif /* FTDF_DBG_BUS_ENABLE */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A #define FTDF_FPPR_MODE_SET_REQUEST 55 -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + /** * \brief Request status * \remark Valid statuses: @@ -201,7 +200,7 @@ typedef uint8_t FTDF_MsgId; * - FTDF_PAN_ACCESS_DENIED: PAN access denied * - FTDF_HOPPING_SEQUENCE_OFFSET_DUPLICATION: Hopping sequence offset duplication */ -typedef uint8_t FTDF_Status; +typedef uint8_t ftdf_status_t; #define FTDF_SUCCESS 0 #define FTDF_CHANNEL_ACCESS_FAILURE 1 #define FTDF_NO_ACK 2 @@ -246,7 +245,7 @@ typedef uint8_t FTDF_Status; * - FTDF_ASSOCIATION_PAN_ACCESS_DENIED: Associate denied * - FTDF_FAST_ASSOCIATION_SUCCESSFUL: Associate request granted (fast) */ -typedef uint8_t FTDF_AssociationStatus; +typedef uint8_t ftdf_association_status_t; #define FTDF_ASSOCIATION_SUCCESSFUL 0x00 #define FTDF_ASSOCIATION_PAN_AT_CAPACITY 0x01 #define FTDF_ASSOCIATION_PAN_ACCESS_DENIED 0x02 @@ -256,57 +255,56 @@ typedef uint8_t FTDF_AssociationStatus; /** * \brief Address mode * \remark Supported address modes: - * - FTDF_NO_ADDRESS - * - FTDF_SHORT_ADDRESS - * - FTDF_EXTENDED_ADDRESS + * - FTDF_NO_ADDRESS + * - FTDF_SHORT_ADDRESS + * - FTDF_EXTENDED_ADDRESS */ -typedef uint8_t FTDF_AddressMode; +typedef uint8_t ftdf_address_mode_t; #define FTDF_NO_ADDRESS 0 #define FTDF_SIMPLE_ADDRESS 1 #define FTDF_SHORT_ADDRESS 2 #define FTDF_EXTENDED_ADDRESS 3 /** - * \brief PAN ID + * \brief PAN id * \remark Range 0.. 65535 */ -typedef uint16_t FTDF_PANId; +typedef uint16_t ftdf_pan_id_t; -typedef uint8_t FTDF_SimpleAddress; +typedef uint8_t ftdf_simple_address_t; /** * \brief Short address * \remark Range 00:00 - ff:ff */ -typedef uint16_t FTDF_ShortAddress; +typedef uint16_t ftdf_short_address_t; /** * \brief Extended address * \remark Range 00:00:00:00:00:00:00:00 - ff:ff:ff:ff:ff:ff:ff:ff */ -typedef uint64_t FTDF_ExtAddress; +typedef uint64_t ftdf_ext_address_t; -typedef union -{ - /** \brief DO NOT USE */ - FTDF_SimpleAddress simpleAddress; - /** \brief Short address */ - FTDF_ShortAddress shortAddress; - /** \brief Extended address */ - FTDF_ExtAddress extAddress; -} FTDF_Address; +typedef union { + /** \brief DO NOT USE */ + ftdf_simple_address_t simple_address; + /** \brief Short address */ + ftdf_short_address_t short_address; + /** \brief Extended address */ + ftdf_ext_address_t ext_address; +} ftdf_address_t; #ifdef SIMULATOR -typedef uint16_t FTDF_DataLength; +typedef uint16_t ftdf_data_length_t; #else -typedef uint8_t FTDF_DataLength; +typedef uint8_t ftdf_data_length_t; #endif /** * \brief Handle * \remark Range 0..255 */ -typedef uint8_t FTDF_Handle; +typedef uint8_t ftdf_handle_t; /** * \brief Boolean @@ -314,91 +312,102 @@ typedef uint8_t FTDF_Handle; * - FTDF_FALSE * - FTDF_TRUE */ -typedef uint8_t FTDF_Boolean; +typedef uint8_t ftdf_boolean_t; + +/** \brief FTDF boolean FALSE */ #define FTDF_FALSE 0 +/** \brief FTDF boolean TRUE */ #define FTDF_TRUE 1 /** * \brief Security level * \remark Valid range 0..7 */ -typedef uint8_t FTDF_SecurityLevel; +typedef uint8_t ftdf_security_level_t; /** - * \brief Security key ID mode + * \brief Security key id mode * \remark Valid range 0..3 */ -typedef uint8_t FTDF_KeyIdMode; +typedef uint8_t ftdf_key_id_mode_t; /** * \brief Security key index * \remark Valid range 0..255 */ -typedef uint8_t FTDF_KeyIndex; +typedef uint8_t ftdf_key_index_t; /** * \brief Sequence number * \remark Valid range 0..255 */ -typedef uint8_t FTDF_SN; +typedef uint8_t ftdf_sn_t; /** * \brief Sequence number * \remark Valid range 0..0xffffffffff (5 octets) */ -typedef uint64_t FTDF_ASN; +typedef uint64_t ftdf_asn_t; /** * \brief Order */ -typedef uint8_t FTDF_Order; +typedef uint8_t ftdf_order_t; /** * \brief Time * \remark Timestamp in symbols which wraps around every 0x100000000 symbols */ -typedef uint32_t FTDF_Time; +typedef uint32_t ftdf_time_t; /** * \brief Real time * \remark Timestamp in symbols which does not wrap (in the lifetime of the device) */ -typedef uint64_t FTDF_Time64; +typedef uint64_t ftdf_time64_t; -typedef uint32_t FTDF_USec; +typedef uint32_t ftdf_usec_t; -typedef uint64_t FTDF_PSec; +typedef uint64_t ftdf_psec_t; -typedef uint32_t FTDF_NrLowPowerClockCycles; +typedef uint32_t ftdf_nr_low_power_clock_cycles_t; -typedef uint8_t FTDF_NrBackoffPeriods; +typedef uint8_t ftdf_nr_backoff_periods_t; + +/** + * \brief Link Quality mode + * \remark 0: RSSI, 1: LQI + */ +typedef uint8_t ftdf_link_quality_mode_t; +#define FTDF_LINK_QUALITY_MODE_RSSI 0 +#define FTDF_LINK_QUALITY_MODE_LQI 1 /** * \brief Period of time * \remark Range 0..65535 */ -typedef uint16_t FTDF_Period; +typedef uint16_t ftdf_period_t; /** * \brief Size type */ -typedef uint8_t FTDF_Size; +typedef uint8_t ftdf_size_t; /** * \brief Length type */ -typedef uint8_t FTDF_Length; +typedef uint8_t ftdf_length_t; /** * \brief Priority type */ -typedef uint8_t FTDF_Priority; +typedef uint8_t ftdf_priority_t; /** * \brief Performance counter * \remark Range 0..0xffffffff */ -typedef uint32_t FTDF_Count; +typedef uint32_t ftdf_count_t; /** * \brief Disassociate reason @@ -406,7 +415,7 @@ typedef uint32_t FTDF_Count; * - FTDF_COORD_WISH_DEVICE_LEAVE_PAN: Coordinator wishes that device leaves PAN * - FTDF_DEVICE_WISH_LEAVE_PAN: Device wishes to leave PAN */ -typedef uint8_t FTDF_DisassociateReason; +typedef uint8_t ftdf_disassociate_reason_t; #define FTDF_COORD_WISH_DEVICE_LEAVE_PAN 1 #define FTDF_DEVICE_WISH_LEAVE_PAN 2 @@ -416,7 +425,7 @@ typedef uint8_t FTDF_DisassociateReason; * - FTDF_NORMAL_BEACON: Normal beacon * - FTDF_ENHANCED_BEACON: Enhanced beacon */ -typedef uint8_t FTDF_BeaconType; +typedef uint8_t ftdf_beacon_type_t; #define FTDF_NORMAL_BEACON 0 #define FTDF_ENHANCED_BEACON 1 @@ -426,7 +435,7 @@ typedef uint8_t FTDF_BeaconType; /** \brief aNumSuperframeSlots */ #define FTDF_NUM_SUPERFRAME_SLOTS 16 /** \brief aBaseSuperframeDuration */ -#define FTDF_BASE_SUPERFRAME_DURATION ( FTDF_BASE_SLOT_DURATION * FTDF_NUM_SUPERFRAME_SLOTS ) +#define FTDF_BASE_SUPERFRAME_DURATION (FTDF_BASE_SLOT_DURATION * FTDF_NUM_SUPERFRAME_SLOTS) /** \brief NOT USED */ #define FTDF_GTS_PERSISTENCE_TIME 4 /** \brief aMaxBeaconOverhead */ @@ -434,7 +443,7 @@ typedef uint8_t FTDF_BeaconType; /** \brief aMaxBeaconOverhead */ #define FTDF_MAX_PHY_PACKET_SIZE 127 /** \brief aMaxPHYPacketSize */ -#define FTDF_MAX_BEACON_PAYLOAD_LENGTH ( FTDF_MAX_PHY_PACKET_SIZE - FTDF_MAX_BEACON_OVERHEAD ) +#define FTDF_MAX_BEACON_PAYLOAD_LENGTH (FTDF_MAX_PHY_PACKET_SIZE - FTDF_MAX_BEACON_OVERHEAD) /** \brief NOT USED */ #define FTDF_MAX_LOST_BEACONS 4 /** \brief aMaxMPDUUnsecuredOverhead */ @@ -442,9 +451,9 @@ typedef uint8_t FTDF_BeaconType; /** \brief aMinMPDUOverhead */ #define FTDF_MIN_MPDU_OVERHEAD 9 /** \brief aMaxMACSafePayloadSize */ -#define FTDF_MAX_MAC_SAFE_PAYLOAD_SIZE ( FTDF_MAX_PHY_PACKET_SIZE - FTDF_MAX_MPDU_UNSECURED_OVERHEAD ) +#define FTDF_MAX_MAC_SAFE_PAYLOAD_SIZE (FTDF_MAX_PHY_PACKET_SIZE - FTDF_MAX_MPDU_UNSECURED_OVERHEAD) /** \brief aMaxMACSafePayloadSize */ -#define FTDF_MAX_PAYLOAD_SIZE ( FTDF_MAX_PHY_PACKET_SIZE - FTDF_MIN_MPDU_OVERHEAD ) +#define FTDF_MAX_PAYLOAD_SIZE (FTDF_MAX_PHY_PACKET_SIZE - FTDF_MIN_MPDU_OVERHEAD) /** \brief aMaxMACPayloadSize */ #define FTDF_MAX_SIFS_FRAME_SIZE 18 /** \brief NOT USED */ @@ -453,96 +462,154 @@ typedef uint8_t FTDF_BeaconType; #define FTDF_UNIT_BACKOFF_PERIOD 20 /** - * \brief PIB attribute ID + * \brief PIB attribute id * \remark List of supported PIB attributes, their types/structures and description - * - FTDF_PIB_EXTENDED_ADDRESS, \link FTDF_ExtAddress \endlink, + * - FTDF_PIB_EXTENDED_ADDRESS, \link ftdf_ext_address_t \endlink, * The extended address of the device - * - FTDF_PIB_ACK_WAIT_DURATION, \link FTDF_Period \endlink, The maximum time in symbols that is waited for an ack, Read only - * - FTDF_PIB_ASSOCIATION_PAN_COORD, \link FTDF_Boolean \endlink, Indication whether the device is associated with a PAN coordinator - * - FTDF_PIB_ASSOCIATION_PERMIT, \link FTDF_Boolean \endlink, Indication whether the PAN coordinator grats association requests - * - FTDF_PIB_AUTO_REQUEST, \link FTDF_Boolean \endlink, Indication whether beacon received while scanning are forwarded to the application or not - * - FTDF_PIB_BEACON_PAYLOAD, FTDF_Octet*, Pointer to the data to be included in a beacon as payload - * - FTDF_PIB_BEACON_PAYLOAD_LENGTH, \link FTDF_Size \endlink, Size of the data to be included in a beacon as payload - * - FTDF_PIB_BEACON_ORDER, \link FTDF_Order \endlink, Fixed to 15 indicating beaconless mode - * - FTDF_PIB_BSN, \link FTDF_SN \endlink, The current beacon sequence number - * - FTDF_PIB_COORD_EXTENDED_ADDRESS, \link FTDF_ExtAddress \endlink, The extended address of the coordinator - * - FTDF_PIB_COORD_SHORT_ADDRESS, \link FTDF_ShortAddress \endlink, The short address of the coordinator - * - FTDF_PIB_DSN, \link FTDF_SN \endlink, The current data sequence number - * - FTDF_PIB_MAX_BE, \link FTDF_BEExponent \endlink, The maximum backoff exponent - * - FTDF_PIB_MAX_CSMA_BACKOFFS, \link FTDF_Size \endlink, The maximum number of backoffs - * - FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME, \link FTDF_Period \endlink, The maximum time in symbols that RX is ON after that a frame is received with FP set. - * - FTDF_PIB_MAX_FRAME_RETRIES, \link FTDF_Size \endlink, The maximum number of frame retries - * - FTDF_PIB_MIN_BE, \link FTDF_BEExponent \endlink, The minimum backoff exponent - * - FTDF_PIB_LIFS_PERIOD, \link FTDF_Period \endlink, The long IFS period in number of symbols, Read oonly - * - FTDF_PIB_SIFS_PERIOD, \link FTDF_Period \endlink, The short IFS period in number of symbols, Read oonly - * - FTDF_PIB_PAN_ID, \link FTDF_PANId \endlink, The PAN ID of the device - * - FTDF_PIB_PROMISCUOUS_MODE, \link FTDF_Boolean \endlink, Indication whether the promiscuous is enable or not - * - FTDF_PIB_RESPONSE_WAIT_TIME, \link FTDF_Size \endlink, The maximum time in aBaseSuperFramePeriod's (960 symbols) that is waited for a command frame response - * - FTDF_PIB_RX_ON_WHEN_IDLE, \link FTDF_Boolean \endlink, Indication whether the receiver must be on when idle - * - FTDF_PIB_SECURITY_ENABLED, \link FTDF_Boolean \endlink, Indication whether the security is enabled - * - FTDF_PIB_SHORT_ADDRESS, \link FTDF_ShortAddress \endlink, The short address of the device - * - FTDF_PIB_SYNC_SYMBOL_OFFSET, \link FTDF_Period \endlink, The offset in symbols between the start of frame and that the timestamp is taken - * - FTDF_PIB_TIMESTAMP_SUPPORTED, \link FTDF_Boolean \endlink, Indication whether timestamping is supported - * - FTDF_PIB_TRANSACTION_PERSISTENCE_TIME, \link FTDF_Period \endlink, The maximum time in aBaseSuperFramePeriod's (960 symbols) that indirect data requests are queued - * - FTDF_PIB_ENH_ACK_WAIT_DURATION, \link FTDF_Period \endlink, The maximum time in symbols that is waited for an enhanced ack - * - FTDF_PIB_IMPLICIT_BROADCAST, \link FTDF_Boolean \endlink, Indication whether frames without a destination PAN are treated as broadcasts - * - FTDF_PIB_DISCONNECT_TIME, \link FTDF_Period \endlink, The time in timeslots that disassoctate frames are send before disconnecting - * - FTDF_PIB_JOIN_PRIORITY, \link FTDF_Priority \endlink, The join priority - * - FTDF_PIB_ASN, \link FTDF_ASN \endlink, The current ASN - * - FTDF_PIB_SLOTFRAME_TABLE, \link FTDF_SlotframeTable \endlink, The slotframe table, Read only + * - FTDF_PIB_ACK_WAIT_DURATION, \link ftdf_period_t \endlink, The maximum time in symbols that is + waited for an ack, Read only + * - FTDF_PIB_ASSOCIATION_PAN_COORD, \link ftdf_boolean_t \endlink, Indication whether the device + is associated with a PAN coordinator + * - FTDF_PIB_ASSOCIATION_PERMIT, \link ftdf_boolean_t \endlink, Indication whether the PAN + coordinator grats association requests + * - FTDF_PIB_AUTO_REQUEST, \link ftdf_boolean_t \endlink, Indication whether beacon received while + scanning are forwarded to the application or not + * - FTDF_PIB_BEACON_PAYLOAD, ftdf_octet_t*, Pointer to the data to be included in a beacon as + payload + * - FTDF_PIB_BEACON_PAYLOAD_LENGTH, \link ftdf_size_t \endlink, Size of the data to be included + in a beacon as payload + * - FTDF_PIB_BEACON_ORDER, \link ftdf_order_t \endlink, Fixed to 15 indicating beaconless mode + * - FTDF_PIB_BSN, \link ftdf_sn_t \endlink, The current beacon sequence number + * - FTDF_PIB_COORD_EXTENDED_ADDRESS, \link ftdf_ext_address_t \endlink, The extended address of + the coordinator + * - FTDF_PIB_COORD_SHORT_ADDRESS, \link ftdf_short_address_t \endlink, The short address of the + coordinator + * - FTDF_PIB_DSN, \link ftdf_sn_t \endlink, The current data sequence number + * - FTDF_PIB_MAX_BE, \link ftdf_be_exponent_t \endlink, The maximum backoff exponent + * - FTDF_PIB_MAX_CSMA_BACKOFFS, \link ftdf_size_t \endlink, The maximum number of backoffs + * - FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME, \link ftdf_period_t \endlink, The maximum time in symbols + that RX is ON after that a frame is received with FP set. + * - FTDF_PIB_MAX_FRAME_RETRIES, \link ftdf_size_t \endlink, The maximum number of frame retries + * - FTDF_PIB_MIN_BE, \link ftdf_be_exponent_t \endlink, The minimum backoff exponent + * - FTDF_PIB_LIFS_PERIOD, \link ftdf_period_t \endlink, The long IFS period in number of symbols, + Read oonly + * - FTDF_PIB_SIFS_PERIOD, \link ftdf_period_t \endlink, The short IFS period in number of symbols, + Read oonly + * - FTDF_PIB_PAN_ID, \link ftdf_pan_id_t \endlink, The PAN id of the device + * - FTDF_PIB_PROMISCUOUS_MODE, \link ftdf_boolean_t \endlink, Indication whether the promiscuous + is enable or not + * - FTDF_PIB_RESPONSE_WAIT_TIME, \link ftdf_size_t \endlink, The maximum time in + aBaseSuperFramePeriod's (960 symbols) that is waited for a command frame response + * - FTDF_PIB_RX_ON_WHEN_IDLE, \link ftdf_boolean_t \endlink, Indication whether the receiver + must be on when idle + * - FTDF_PIB_SECURITY_ENABLED, \link ftdf_boolean_t \endlink, Indication whether the security + is enabled + * - FTDF_PIB_SHORT_ADDRESS, \link ftdf_short_address_t \endlink, The short address of the device + * - FTDF_PIB_SYNC_SYMBOL_OFFSET, \link ftdf_period_t \endlink, The offset in symbols between the + start of frame and that the timestamp is taken + * - FTDF_PIB_TIMESTAMP_SUPPORTED, \link ftdf_boolean_t \endlink, Indication whether + timestamping is supported + * - FTDF_PIB_TRANSACTION_PERSISTENCE_TIME, \link ftdf_period_t \endlink, The maximum time in + aBaseSuperFramePeriod's (960 symbols) that indirect data requests are queued + * - FTDF_PIB_ENH_ACK_WAIT_DURATION, \link ftdf_period_t \endlink, The maximum time in symbols + that is waited for an enhanced ack + * - FTDF_PIB_IMPLICIT_BROADCAST, \link ftdf_boolean_t \endlink, Indication whether frames without + a destination PAN are treated as broadcasts + * - FTDF_PIB_DISCONNECT_TIME, \link ftdf_period_t \endlink, The time in timeslots that disassoctate + frames are send before disconnecting + * - FTDF_PIB_JOIN_PRIORITY, \link ftdf_priority_t \endlink, The join priority + * - FTDF_PIB_ASN, \link ftdf_asn_t \endlink, The current ASN + * - FTDF_PIB_SLOTFRAME_TABLE, \link ftdf_slotframe_table_t \endlink, The slotframe table, Read only * - FTDF_PIB_LINK_TABLE, \link FTDF_LinkTable \endlink, The link table, Read only - * - FTDF_PIB_TIMESLOT_TEMPLATE, \link FTDF_TimeslotTemplate \endlink, The current timeslot template - * - FTDF_PIB_HOPPINGSEQUENCE_ID, \link FTDF_HoppingSequenceId \endlink, The ID of the current hopping sequence - * - FTDF_PIB_CHANNEL_PAGE, \link FTDF_ChannelPage \endlink, The current channel page - * - FTDF_PIB_HOPPING_SEQUENCE_LENGTH, \link FTDF_Length \endlink, Length of the current hopping sequence - * - FTDF_PIB_HOPPING_SEQUENCE_LIST, \link FTDF_ChannelNumber \endlink, Hopping sequence - * - FTDF_PIB_CURRENT_HOP, \link FTDF_Length \endlink, The current hop - * - FTDF_PIB_CSL_PERIOD, \link FTDF_Period \endlink, The CSL sample period in units of 10 symbols - * - FTDF_PIB_CSL_MAX_PERIOD, \link FTDF_Period \endlink, The maximum CSL sample period of devices in the PAN in units of 10 symbols - * - FTDF_PIB_CSL_CHANNEL_MASK, \link FTDF_Bitmap32 \endlink, Bitmapped list of channels to be sample in CSL mode - * - FTDF_PIB_CSL_FRAME_PENDING_WAIT_T, \link FTDF_Period \endlink, The maximum time in symbols that RX is ON after that a frame is received with FP set in CSL mode. - * - FTDF_PIB_PERFORMANCE_METRICS, \link FTDF_PerformanceMetrics \endlink, The performance metrics, Read only - * - FTDF_PIB_EB_IE_LIST, \link FTDF_IEList \endlink, Payload IE list to be added to an enhanced beacon - * - FTDF_PIB_EBSN, \link FTDF_SN \endlink, Current enhanced beacon sequence number - * - FTDF_PIB_EB_AUTO_SA, \link FTDF_AutoSA \endlink, Source address mode of auto generated enhanced beacons - * - FTDF_PIB_EACK_IE_LIST, \link FTDF_IEList \endlink, Payload IE list to be added to an enhanced ack - * - FTDF_PIB_KEY_TABLE, \link FTDF_KeyTable \endlink, Security key table - * - FTDF_PIB_DEVICE_TABLE, \link FTDF_DeviceTable \endlink, Security device table - * - FTDF_PIB_SECURITY_LEVEL_TABLE, \link FTDF_SecurityLevelTable \endlink, Security level table - * - FTDF_PIB_FRAME_COUNTER, \link FTDF_FrameCounter \endlink, Current security frame counter - * - FTDF_PIB_MT_DATA_SECURITY_LEVEL, \link FTDF_SecurityLevel \endlink, Security level for auto generated data frames - * - FTDF_PIB_MT_DATA_KEY_ID_MODE, \link FTDF_KeyIdMode \endlink, Security key ID mode for auto generated data frames - * - FTDF_PIB_MT_DATA_KEY_SOURCE, FTDF_Octet[ 8 ], Security key source for auto generated data frames - * - FTDF_PIB_MT_DATA_KEY_INDEX, \link FTDF_KeyIndex \endlink, Security key index for auto generated data frames - * - FTDF_PIB_DEFAULT_KEY_SOURCE, FTDF_Octet[ 8 ], Default key source - * - FTDF_PIB_FRAME_COUNTER_MODE, \link FTDF_FrameCounterMode \endlink, Security frame counter mode - * - FTDF_PIB_CSL_SYNC_TX_MARGIN, \link FTDF_Period \endlink, The margin in unit of 10 symbols used by FTDF in CSL mode in case of a synchronised transmission - * - FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO, \link FTDF_Period \endlink, The time in unit of 10 symbols after which FTDF discard the remote synchronisation info. - * - FTDF_PIB_TSCH_ENABLED, \link FTDF_Boolean \endlink, Indicates whether the TSCH mode is enabled or not, Read only - * - FTDF_PIB_LE_ENABLED, \link FTDF_Boolean \endlink, Indicates whether the CSL mode is enabled or not - * - FTDF_PIB_CURRENT_CHANNEL, \link FTDF_ChannelNumber \endlink, The current channel used by FTDF - * - FTDF_PIB_CHANNELS_SUPPORTED, \link FTDF_ChannelDescriptorList \endlink, List of channels supported by FTDF - * - FTDF_PIB_TX_POWER_TOLERANCE, \link FTDF_TXPowerTolerance \endlink, TX power tolerance - * - FTDF_PIB_TX_POWER, \link FTDF_DBm \endlink, TX power - * - FTDF_PIB_CCA_MODE, \link FTDF_CCAMode \endlink, CCA mode - * - FTDF_PIB_CURRENT_PAGE, \link FTDF_ChannelPage \endlink, Current channel page - * - FTDF_PIB_MAX_FRAME_DURATION, \link FTDF_Period \endlink, The maximum number of symbols in frame, Read only - * - FTDF_PIB_SHR_DURATION, \link FTDF_Period \endlink, Synchronisation header length in symbols, Read only - * - FTDF_PIB_TRAFFIC_COUNTERS, \link FTDF_TrafficCounters \endlink, Miscelaneous traffic counters, Read only - * - FTDF_PIB_LE_CAPABLE, \link FTDF_Boolean \endlink, Indicates whether FTDF supports LE (CSL), Read only - * - FTDF_PIB_LL_CAPABLE, \link FTDF_Boolean \endlink, Indicates whether FTDF supports LL, Read only - * - FTDF_PIB_DSME_CAPABLE, \link FTDF_Boolean \endlink, Indicates whether FTDF supports DSME, Read only - * - FTDF_PIB_RFID_CAPABLE, \link FTDF_Boolean \endlink, Indicates whether FTDF supports RFID, Read only - * - FTDF_PIB_AMCA_CAPABLE, \link FTDF_Boolean \endlink, Indicates whether FTDF supports AMCA, Read only - * - FTDF_PIB_TSCH_CAPABLE, \link FTDF_Boolean \endlink, Indicates whether FTDF supports FTDF, Read only - * - FTDF_PIB_METRICS_CAPABLE, \link FTDF_Boolean \endlink, Indicates whether FTDF supports metrics, Read only - * - FTDF_PIB_RANGING_SUPPORTED, \link FTDF_Boolean \endlink, Indicates whether FTDF supports ranging, Read only - * - FTDF_PIB_KEEP_PHY_ENABLED, \link FTDF_Boolean \endlink, Indicates whether the PHY must be kept enabled - * - FTDF_PIB_METRICS_ENABLED, \link FTDF_Boolean \endlink, Indicates whether metrics are enabled or not - * - FTDF_PIB_BEACON_AUTO_RESPOND, \link FTDF_Boolean \endlink, Indicates whether FTDF must send automatically a beacon at a BECAON_REQUEST command frame or must forward the request to the application using FTDF_BEACON_REQUEST_INDICATION. - * - FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD, \link FTDF_Period \endlink, The minimum TSCH slot sync offset in microseconds before resyncing + * - FTDF_PIB_TIMESLOT_TEMPLATE, \link ftdf_timeslot_template_t \endlink, The current timeslot + template + * - FTDF_PIB_HOPPINGSEQUENCE_ID, \link ftdf_hopping_sequence_id_t \endlink, The id of the current + hopping sequence + * - FTDF_PIB_CHANNEL_PAGE, \link ftdf_channel_page_t \endlink, The current channel page + * - FTDF_PIB_HOPPING_SEQUENCE_LENGTH, \link ftdf_length_t \endlink, Length of the current hopping + sequence + * - FTDF_PIB_HOPPING_SEQUENCE_LIST, \link ftdf_channel_number_t \endlink, Hopping sequence + * - FTDF_PIB_CURRENT_HOP, \link ftdf_length_t \endlink, The current hop + * - FTDF_PIB_CSL_PERIOD, \link ftdf_period_t \endlink, The CSL sample period in units of 10 symbols + * - FTDF_PIB_CSL_MAX_PERIOD, \link ftdf_period_t \endlink, The maximum CSL sample period of devices + in the PAN in units of 10 symbols + * - FTDF_PIB_CSL_CHANNEL_MASK, \link ftdf_bitmap32_t \endlink, Bitmapped list of channels to be + sample in CSL mode + * - FTDF_PIB_CSL_FRAME_PENDING_WAIT_T, \link ftdf_period_t \endlink, The maximum time in symbols + that RX is ON after that a frame is received with FP set in CSL mode. + * - FTDF_PIB_PERFORMANCE_METRICS, \link ftdf_performance_metrics_t \endlink, + The performance metrics, Read only + * - FTDF_PIB_EB_IE_LIST, \link ftdf_ie_list_t \endlink, Payload IE list to be added to an + enhanced beacon + * - FTDF_PIB_EBSN, \link ftdf_sn_t \endlink, Current enhanced beacon sequence number + * - FTDF_PIB_EB_AUTO_SA, \link ftdf_auto_sa_t \endlink, Source address mode of auto generated + enhanced beacons + * - FTDF_PIB_EACK_IE_LIST, \link ftdf_ie_list_t \endlink, Payload IE list to be added + to an enhanced ack + * - FTDF_PIB_KEY_TABLE, \link ftdf_key_table_t \endlink, Security key table + * - FTDF_PIB_DEVICE_TABLE, \link ftdf_device_table_t \endlink, Security device table + * - FTDF_PIB_SECURITY_LEVEL_TABLE, \link ftdf_security_level_table_t \endlink, Security level table + * - FTDF_PIB_FRAME_COUNTER, \link ftdf_frame_counter_t \endlink, Current security frame counter + * - FTDF_PIB_MT_DATA_SECURITY_LEVEL, \link ftdf_security_level_t \endlink, Security level for + auto generated data frames + * - FTDF_PIB_MT_DATA_KEY_ID_MODE, \link ftdf_key_id_mode_t \endlink, Security key id mode for + auto generated data frames + * - FTDF_PIB_MT_DATA_KEY_SOURCE, ftdf_octet_t[8], Security key source for auto generated + data frames + * - FTDF_PIB_MT_DATA_KEY_INDEX, \link ftdf_key_index_t \endlink, Security key index for auto + generated data frames + * - FTDF_PIB_DEFAULT_KEY_SOURCE, ftdf_octet_t[8], Default key source + * - FTDF_PIB_FRAME_COUNTER_MODE, \link ftdf_frame_counter_mode_t \endlink, Security frame counter + mode + * - FTDF_PIB_CSL_SYNC_TX_MARGIN, \link ftdf_period_t \endlink, The margin in unit of 10 symbols + used by FTDF in CSL mode in case of a synchronised transmission + * - FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO, \link ftdf_period_t \endlink, The time in unit of 10 symbols + after which FTDF discard the remote synchronisation info. + * - FTDF_PIB_TSCH_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether the TSCH mode is + enabled or not, Read only + * - FTDF_PIB_LE_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether the CSL mode is + enabled or not + * - FTDF_PIB_CURRENT_CHANNEL, \link ftdf_channel_number_t \endlink, The current channel used + by FTDF + * - FTDF_PIB_CHANNELS_SUPPORTED, \link ftdf_channel_descriptor_list_t \endlink, List of channels + supported by FTDF + * - FTDF_PIB_TX_POWER_TOLERANCE, \link ftdf_tx_power_tolerance_t \endlink, TX power tolerance + * - FTDF_PIB_TX_POWER, \link ftdf_dbm \endlink, TX power + * - FTDF_PIB_CCA_MODE, \link ftdf_cca_mode_t \endlink, CCA mode + * - FTDF_PIB_CURRENT_PAGE, \link ftdf_channel_page_t \endlink, Current channel page + * - FTDF_PIB_MAX_FRAME_DURATION, \link ftdf_period_t \endlink, The maximum number of symbols in + frame, Read only + * - FTDF_PIB_SHR_DURATION, \link ftdf_period_t \endlink, Synchronisation header length in + symbols, Read only + * - FTDF_PIB_TRAFFIC_COUNTERS, \link ftdf_traffic_counters_t \endlink, Miscelaneous + traffic counters, Read only + * - FTDF_PIB_LE_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports LE (CSL), + Read only + * - FTDF_PIB_LL_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports LL, + Read only + * - FTDF_PIB_DSME_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports DSME, + Read only + * - FTDF_PIB_RFID_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports RFID, + Read only + * - FTDF_PIB_AMCA_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports AMCA, + Read only + * - FTDF_PIB_TSCH_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports FTDF, + Read only + * - FTDF_PIB_METRICS_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports + metrics, Read only + * - FTDF_PIB_RANGING_SUPPORTED, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports + ranging, Read only + * - FTDF_PIB_KEEP_PHY_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether the PHY must + be kept enabled + * - FTDF_PIB_METRICS_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether metrics + are enabled or not + * - FTDF_PIB_BEACON_AUTO_RESPOND, \link ftdf_boolean_t \endlink, Indicates whether FTDF must + send automatically a beacon at a BECAON_REQUEST command frame or must forward the request + to the application using FTDF_BEACON_REQUEST_INDICATION. + * - FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD, \link ftdf_period_t \endlink, The minimum TSCH slot sync + offset in microseconds before resyncing */ -typedef uint8_t FTDF_PIBAttribute; +typedef uint8_t ftdf_pib_attribute_t; // See Table 52 "MAC PIB attributes" of IEEE 802.15.4-2011 and IEEE 802.15.4e-2012 for more details // NOTE: Be careful with changing the order of these PIB attributes because initialization of related @@ -656,17 +723,12 @@ typedef uint8_t FTDF_PIBAttribute; #define FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD 104 /* Proprietary PIB. */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A #define FTDF_PIB_BO_IRQ_THRESHOLD 105 #define FTDF_PIB_PTI_CONFIG 106 -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ +#define FTDF_PIB_LINK_QUALITY_MODE 107 // Total number of PIB attributes -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -#define FTDF_NR_OF_PIB_ATTRIBUTES 106 -#else /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ -#define FTDF_NR_OF_PIB_ATTRIBUTES 104 -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ +#define FTDF_NR_OF_PIB_ATTRIBUTES 107 /* Default values */ #ifndef FTDF_BO_IRQ_THRESHOLD @@ -678,7 +740,7 @@ typedef uint8_t FTDF_PIBAttribute; * \brief Debug bus mode. * */ -typedef uint8_t FTDF_DbgMode; +typedef uint8_t ftdf_dbg_mode_t; /** * \brief Disable debug signals @@ -799,7 +861,7 @@ typedef uint8_t FTDF_DbgMode; * diagnose_bus bit 7-3 = * Prt statements mac frame parser * 0 Reset - * 1 Multipurpose frame with no destination PAN ID and macImplicitBroadcast is + * 1 Multipurpose frame with no destination PAN id and macImplicitBroadcast is * false and not PAN coordinator dropped * 2 Multipurpose frame with no destination address and macImplicitBroadcast is * false and not PAN coordinator dropped @@ -808,12 +870,12 @@ typedef uint8_t FTDF_DbgMode; * 5 RX frame passed due to macAlwaysPassFrmType set * 6 RX unsupported da_mode = 01 for frame_version 0x0- detected * 7 RX unsupported sa_mode = 01 for frame_version 0x0- detected - * 8 Data or command frame with no destination PAN ID and macImplicitBroadcast + * 8 Data or command frame with no destination PAN id and macImplicitBroadcast * is false and not PAN coordinator dropped * 9 Data or command frame with no destination address and macImplicitBroadcast * is false and not PAN coordinator dropped * 10 RX unsupported frame_version detected - * 11 Multipurpose frame with no destination PAN ID and macImplicitBroadcast is + * 11 Multipurpose frame with no destination PAN id and macImplicitBroadcast is * false and not PAN coordinator dropped * 12 Multipurpose frame with no destination address and macImplicitBroadcast * is false and not PAN coordinator dropped @@ -1241,33 +1303,32 @@ typedef uint8_t FTDF_DbgMode; #define FTDF_MAX_HOPPING_SEQUENCE_LENGTH 16 -typedef void FTDF_PIBAttributeValue; +typedef void ftdf_pib_attribute_value_t; /** * \brief Link quality * \remark Range: 0..255 * \remark A higher number is a higher quality */ -typedef uint8_t FTDF_LinkQuality; +typedef uint8_t ftdf_link_quality_t; /** - * \brief Hopping sequence ID + * \brief Hopping sequence id */ -typedef uint16_t FTDF_HoppingSequenceId; +typedef uint16_t ftdf_hopping_sequence_id_t; /** * \brief Channel number * \remark Supported range: 11..27 */ -typedef uint8_t FTDF_ChannelNumber; +typedef uint8_t ftdf_channel_number_t; /** * \brief Packet Traffic Information (PTI) used to classify a transaction in the radio arbiter. */ -typedef uint8_t FTDF_PTI; +typedef uint8_t ftdf_pti_t; -enum -{ +enum { /* PTI index for explicit Rx. */ FTDF_PTI_CONFIG_RX, /* PTI index for Tx. */ @@ -1282,39 +1343,38 @@ enum FTDF_PTIS, }; -typedef struct -{ - FTDF_PTI ptis[FTDF_PTIS]; -} FTDF_PtiConfig; +typedef struct { + ftdf_pti_t ptis[FTDF_PTIS]; +} ftdf_pti_config_t; /** * \brief Channel page * \remark Supported values: 0 */ -typedef uint8_t FTDF_ChannelPage; +typedef uint8_t ftdf_channel_page_t; -typedef uint8_t FTDF_ChannelOffset; +typedef uint8_t ftdf_channel_offset_t; -typedef uint8_t FTDF_Octet; +typedef uint8_t ftdf_octet_t; /** * \brief 8-bit type bitmap */ -typedef uint8_t FTDF_Bitmap8; +typedef uint8_t ftdf_bitmap8_t; /** * \brief 16-bit type bitmap */ -typedef uint16_t FTDF_Bitmap16; +typedef uint16_t ftdf_bitmap16_t; /** * \brief 32-bit type bitmap */ -typedef uint32_t FTDF_Bitmap32; +typedef uint32_t ftdf_bitmap32_t; -typedef uint8_t FTDF_NumOfBackoffs; +typedef uint8_t ftdf_num_of_backoffs_t; -typedef uint8_t FTDF_GTSCharateristics; +typedef uint8_t ftdf_gts_charateristics_t; /** * \brief Scan type @@ -1325,14 +1385,14 @@ typedef uint8_t FTDF_GTSCharateristics; * - FTDF_ORPHAN_SCAN: Orphan scan * - FTDF_ENHANCED_ACTIVE_SCAN: Enhanced active scan */ -typedef uint8_t FTDF_ScanType; +typedef uint8_t ftdf_scan_type_t; #define FTDF_ED_SCAN 1 #define FTDF_ACTIVE_SCAN 2 #define FTDF_PASSIVE_SCAN 3 #define FTDF_ORPHAN_SCAN 4 #define FTDF_ENHANCED_ACTIVE_SCAN 7 -typedef uint8_t FTDF_ScanDuration; +typedef uint8_t ftdf_scan_duration_t; /** * \brief Loss operation @@ -1341,12 +1401,12 @@ typedef uint8_t FTDF_ScanDuration; * - FTDF_REALIGNMENT * - FTDF_BEACON_LOST (not supported because only beaconless mode is supported) */ -typedef uint8_t FTDF_LossReason; +typedef uint8_t ftdf_loss_reason_t; #define FTDF_PAN_ID_CONFLICT 1 #define FTDF_REALIGNMENT 2 #define FTDF_BEACON_LOST 3 -typedef uint16_t FTDF_SlotframeSize; +typedef uint16_t ftdf_slotframe_size_t; /** * \brief Set operation @@ -1355,12 +1415,12 @@ typedef uint16_t FTDF_SlotframeSize; * - FTDF_DELETE: Delete an entry * - FTDF_MODIFY: Modify an entry */ -typedef uint8_t FTDF_Operation; +typedef uint8_t ftdf_operation_t; #define FTDF_ADD 0 #define FTDF_DELETE 2 #define FTDF_MODIFY 3 -typedef uint16_t FTDF_Timeslot; +typedef uint16_t ftdf_timeslot_t; /** * \brief Set operation @@ -1368,7 +1428,7 @@ typedef uint16_t FTDF_Timeslot; * - FTDF_NORMAL_LINK * - FTDF_ADVERTISING_LINK */ -typedef uint8_t FTDF_LinkType; +typedef uint8_t ftdf_link_type_t; #define FTDF_NORMAL_LINK 0 #define FTDF_ADVERTISING_LINK 1 @@ -1378,34 +1438,32 @@ typedef uint8_t FTDF_LinkType; * - FTDF_TSCH_OFF * - FTDF_TSCH_ON */ -typedef uint8_t FTDF_TSCHMode; +typedef uint8_t ftdf_tsch_mode_t; #define FTDF_TSCH_OFF 0 #define FTDF_TSCH_ON 1 -typedef uint16_t FTDF_KeepAlivePeriod; +typedef uint16_t ftdf_keep_alive_period_t; /** * \brief BE exponent */ -typedef uint8_t FTDF_BEExponent; +typedef uint8_t ftdf_be_exponent_t; #define FTDF_MAX_SLOTFRAMES 4 -typedef struct -{ - /** \brief Handle of this slotframe */ - FTDF_Handle slotframeHandle; - /** \brief The number of timeslots in this slotframe */ - FTDF_SlotframeSize slotframeSize; -} FTDF_SlotframeEntry; +typedef struct { + /** \brief Handle of this slotframe */ + ftdf_handle_t slotframe_handle; + /** \brief The number of timeslots in this slotframe */ + ftdf_slotframe_size_t slotframe_size; +} ftdf_slotframe_entry_t; -typedef struct -{ - /** \brief Number of slotframes in the slotframe table */ - FTDF_Size nrOfSlotframes; - /** \brief Pointer to the first slotframe entry */ - FTDF_SlotframeEntry* slotframeEntries; -} FTDF_SlotframeTable; +typedef struct { + /** \brief Number of slotframes in the slotframe table */ + ftdf_size_t nr_of_slotframes; + /** \brief Pointer to the first slotframe entry */ + ftdf_slotframe_entry_t* slotframe_entries; +} ftdf_slotframe_table_t; #define FTDF_MAX_LINKS 16 @@ -1414,129 +1472,122 @@ typedef struct #define FTDF_LINK_OPTION_SHARED 0x04 #define FTDF_LINK_OPTION_TIME_KEEPING 0x08 -typedef struct -{ - /** \brief Handle of this link, used for delete and modify operations */ - FTDF_Handle linkHandle; - /** - * \brief Bit mapped link options, the following options are supported:
- * FTDF_LINK_OPTION_TRANSMIT: Lik can be used for transmitting
- * FTDF_LINK_OPTION_RECEIVE: Link can be used for receiving
- * FTDF_LINK_OPTION_SHARED: Shared link, multiple device can transmit in this link
- * FTDF_LINK_OPTION_TIME_KEEPING: Link will be used to synchronise timeslots
- * Multiple options can be defined by or-ing them. - */ - FTDF_Bitmap8 linkOptions; - /** \brief Link type */ - FTDF_LinkType linkType; - /** \brief Handle of the slotframe of this link */ - FTDF_Handle slotframeHandle; - /** \brief Short address of the peer node, only valid if is a transmit link */ - FTDF_ShortAddress nodeAddress; - /** \brief Timeslot in the slotframe */ - FTDF_Timeslot timeslot; - /** \brief Channel offset */ - FTDF_ChannelOffset channelOffset; - /** \brief DO NOT USE */ - void* __private1; - /** \brief DO NOT USE */ - uint64_t __private2; -} FTDF_LinkEntry; +typedef struct { + /** \brief Handle of this link, used for delete and modify operations */ + ftdf_handle_t link_handle; + /** + * \brief Bit mapped link options, the following options are supported:
+ * FTDF_LINK_OPTION_TRANSMIT: Lik can be used for transmitting
+ * FTDF_LINK_OPTION_RECEIVE: Link can be used for receiving
+ * FTDF_LINK_OPTION_SHARED: Shared link, multiple device can transmit in this link
+ * FTDF_LINK_OPTION_TIME_KEEPING: Link will be used to synchronise timeslots
+ * Multiple options can be defined by or-ing them. + */ + ftdf_bitmap8_t link_options; + /** \brief Link type */ + ftdf_link_type_t link_type; + /** \brief Handle of the slotframe of this link */ + ftdf_handle_t slotframe_handle; + /** \brief Short address of the peer node, only valid if is a transmit link */ + ftdf_short_address_t node_address; + /** \brief Timeslot in the slotframe */ + ftdf_timeslot_t timeslot; + /** \brief Channel offset */ + ftdf_channel_offset_t channel_offset; + /** \brief DO NOT USE */ + void* __private1; + /** \brief DO NOT USE */ + uint64_t __private2; +} ftdf_link_entry_t; -typedef struct -{ - /** \brief Number of links in the link table */ - FTDF_Size nrOfLinks; - /** \brief Pointer to the first link entry */ - FTDF_LinkEntry* linkEntries; +typedef struct { + /** \brief Number of links in the link table */ + ftdf_size_t nr_of_links; + /** \brief Pointer to the first link entry */ + ftdf_link_entry_t* link_entries; } FTDF_LinkTable; -typedef struct -{ - FTDF_Handle timeslotTemplateId; - FTDF_Period tsCCAOffset; - FTDF_Period tsCCA; - FTDF_Period tsTxOffset; - FTDF_Period tsRxOffset; - FTDF_Period tsRxAckDelay; - FTDF_Period tsTxAckDelay; - FTDF_Period tsRxWait; - FTDF_Period tsAckWait; - FTDF_Period tsRxTx; - FTDF_Period tsMaxAck; - FTDF_Period tsMaxTs; - FTDF_Period tsTimeslotLength; -} FTDF_TimeslotTemplate; +typedef struct { + ftdf_handle_t timeslot_template_id; + ftdf_period_t ts_cca_offset; + ftdf_period_t ts_cca; + ftdf_period_t ts_tx_offset; + ftdf_period_t ts_rx_offset; + ftdf_period_t ts_rx_ack_delay; + ftdf_period_t ts_tx_ack_delay; + ftdf_period_t ts_rx_wait; + ftdf_period_t ts_ack_wait; + ftdf_period_t ts_rx_tx; + ftdf_period_t ts_max_ack; + ftdf_period_t ts_max_ts; + ftdf_period_t ts_timeslot_length; +} ftdf_timeslot_template_t; -typedef struct -{ - FTDF_Size counterOctets; - FTDF_Count retryCount; - FTDF_Count multipleRetryCount; - FTDF_Count TXFailCount; - FTDF_Count TXSuccessCount; - FTDF_Count FCSErrorCount; - FTDF_Count securityFailureCount; - FTDF_Count duplicateFrameCount; - FTDF_Count RXSuccessCount; - FTDF_Count NACKCount; - FTDF_Count RxExpiredCount; - FTDF_Count BOIrqCount; -} FTDF_PerformanceMetrics; +typedef struct { + ftdf_size_t counter_octets; + ftdf_count_t retry_count; + ftdf_count_t multiple_retry_count; + ftdf_count_t tx_fail_count; + ftdf_count_t tx_success_count; + ftdf_count_t fcs_error_count; + ftdf_count_t security_failure_count; + ftdf_count_t duplicate_frame_count; + ftdf_count_t rx_success_count; + ftdf_count_t nack_count; + ftdf_count_t rx_expired_count; + ftdf_count_t bo_irq_count; +} ftdf_performance_metrics_t; -typedef struct -{ - FTDF_Count txDataFrmCnt; - FTDF_Count txCmdFrmCnt; - FTDF_Count txStdAckFrmCnt; - FTDF_Count txEnhAckFrmCnt; - FTDF_Count txBeaconFrmCnt; - FTDF_Count txMultiPurpFrmCnt; - FTDF_Count rxDataFrmOkCnt; - FTDF_Count rxCmdFrmOkCnt; - FTDF_Count rxStdAckFrmOkCnt; - FTDF_Count rxEnhAckFrmOkCnt; - FTDF_Count rxBeaconFrmOkCnt; - FTDF_Count rxMultiPurpFrmOkCnt; -} FTDF_TrafficCounters; +typedef struct { + ftdf_count_t tx_data_frm_cnt; + ftdf_count_t tx_cmd_frm_cnt; + ftdf_count_t tx_std_ack_frm_cnt; + ftdf_count_t tx_enh_ack_frm_cnt; + ftdf_count_t tx_ceacon_frm_cnt; + ftdf_count_t tx_multi_purp_frm_cnt; + ftdf_count_t rx_data_frm_ok_cnt; + ftdf_count_t rx_cmd_frm_ok_cnt; + ftdf_count_t rx_std_ack_frm_ok_cnt; + ftdf_count_t rx_enh_ack_frm_ok_cnt; + ftdf_count_t rx_beacon_frm_ok_cnt; + ftdf_count_t rx_multi_purp_frm_ok_cnt; +} ftdf_traffic_counters_t; -typedef uint8_t FTDF_Energy; +typedef uint8_t ftdf_energy_t; -typedef struct -{ - /** \brief Coordinator address mode */ - FTDF_AddressMode coordAddrMode; - /** \brief Coordinator PAN ID */ - FTDF_PANId coordPANId; - /** \brief Coordinator address */ - FTDF_Address coordAddr; - /** \brief Channel number */ - FTDF_ChannelNumber channelNumber; - /** \brief Channnel page */ - FTDF_ChannelPage channelPage; - /** \brief NOT USED */ - FTDF_Bitmap16 superframeSpec; - /** \brief NOT USED */ - FTDF_Boolean GTSPermit; - /** \brief Link quality */ - FTDF_LinkQuality linkQuality; - /** \brief */ - FTDF_Time timestamp; -} FTDF_PANDescriptor; +typedef struct { + /** \brief Coordinator address mode */ + ftdf_address_mode_t coord_addr_mode; + /** \brief Coordinator PAN id */ + ftdf_pan_id_t coord_pan_id; + /** \brief Coordinator address */ + ftdf_address_t coord_addr; + /** \brief Channel number */ + ftdf_channel_number_t channel_number; + /** \brief Channnel page */ + ftdf_channel_page_t channel_page; + /** \brief NOT USED */ + ftdf_bitmap16_t superframe_spec; + /** \brief NOT USED */ + ftdf_boolean_t gts_permit; + /** \brief Link quality */ + ftdf_link_quality_t link_quality; + /** \brief */ + ftdf_time_t timestamp; +} ftdf_pan_descriptor_t; -typedef struct -{ - /** \brief Coordinator PAN ID */ - FTDF_PANId coordPANId; - /** \brief Coordinator short address */ - FTDF_ShortAddress coordShortAddr; - /** \brief Channel number */ - FTDF_ChannelNumber channelNumber; - /** \brief Device short address */ - FTDF_ShortAddress shortAddr; - /** \brief Channnel page */ - FTDF_ChannelPage channelPage; -} FTDF_CoordRealignDescriptor; +typedef struct { + /** \brief Coordinator PAN id */ + ftdf_pan_id_t coord_pan_id; + /** \brief Coordinator short address */ + ftdf_short_address_t coord_short_addr; + /** \brief Channel number */ + ftdf_channel_number_t channel_number; + /** \brief Device short address */ + ftdf_short_address_t short_addr; + /** \brief Channnel page */ + ftdf_channel_page_t channel_page; +} ftdf_coord_realign_descriptor_t; /** * \brief Auto frame source address mode @@ -1545,7 +1596,7 @@ typedef struct * - FTDF_AUTO_SHORT: Short address * - FTDF_AUTO_FULL: Extended address */ -typedef uint8_t FTDF_AutoSA; +typedef uint8_t ftdf_auto_sa_t; #define FTDF_AUTO_NONE 1 #define FTDF_AUTO_SHORT 2 #define FTDF_AUTO_FULL 3 @@ -1557,7 +1608,7 @@ typedef uint8_t FTDF_AutoSA; * - FTDF_POWER_TOLERANCE_3_DB * - FTDF_POWER_TOLERANCE_6_DB */ -typedef uint8_t FTDF_TXPowerTolerance; +typedef uint8_t ftdf_tx_power_tolerance_t; #define FTDF_POWER_TOLERANCE_1_DB 1 #define FTDF_POWER_TOLERANCE_3_DB 2 #define FTDF_POWER_TOLERANCE_6_DB 3 @@ -1569,7 +1620,7 @@ typedef uint8_t FTDF_TXPowerTolerance; * - FTDF_CCA_MODE_2 * - FTDF_CCA_MODE_3 */ -typedef uint8_t FTDF_CCAMode; +typedef uint8_t ftdf_cca_mode_t; #define FTDF_CCA_MODE_1 1 #define FTDF_CCA_MODE_2 2 #define FTDF_CCA_MODE_3 3 @@ -1577,35 +1628,34 @@ typedef uint8_t FTDF_CCAMode; /** * \brief Frame control options * \remark Supported options: - * - FTDF_PAN_ID_PRESENT: Controls the PAN ID compression/present bit in multipurpose and version 2 frames - * - FTDF_IES_INCLUDED: Indicates that IEs must be included + * - FTDF_PAN_ID_PRESENT: Controls the PAN id compression/present bit in multipurpose and + version 2 frames + * - FTDF_IES_INCLUDED: Indicates that ie must be included * - FTDF_SEQ_NR_SUPPRESSED: Controls suppression of the sequence number * \remark Multiple options can specified by bit wise or-ing them */ -typedef uint8_t FTDF_FrameControlOptions; +typedef uint8_t ftdf_frame_control_options_t; #define FTDF_PAN_ID_PRESENT 0x01 #define FTDF_IES_INCLUDED 0x02 #define FTDF_SEQ_NR_SUPPRESSED 0x04 -typedef struct -{ - FTDF_ChannelPage channelPage; - FTDF_Size nrOfChannels; - FTDF_ChannelNumber* channels; -} FTDF_ChannelDescriptor; +typedef struct { + ftdf_channel_page_t channel_page; + ftdf_size_t nr_of_channels; + ftdf_channel_number_t* channels; +} ftdf_channel_descriptor_t; -typedef struct -{ - FTDF_Size nrOfChannelDescriptors; - FTDF_ChannelDescriptor* channelDescriptors; -} FTDF_ChannelDescriptorList; +typedef struct { + ftdf_size_t nr_of_channel_descriptors; + ftdf_channel_descriptor_t* channel_descriptors; +} ftdf_channel_descriptor_list_t; /** * \brief Dbm data type */ -typedef int8_t FTDF_DBm; +typedef int8_t ftdf_dbm; -typedef uint8_t FTDF_FrameType; +typedef uint8_t ftdf_frame_type_t; #define FTDF_BEACON_FRAME 0 #define FTDF_DATA_FRAME 1 #define FTDF_ACKNOWLEDGEMENT_FRAME 2 @@ -1614,7 +1664,7 @@ typedef uint8_t FTDF_FrameType; #define FTDF_MULTIPURPOSE_FRAME 5 /** - * \brief Command frame ID + * \brief Command frame id * \remark Supported command frame IDs: * - FTDF_COMMAND_ASSOCIATION_REQUEST * - FTDF_COMMAND_ASSOCIATION_RESPONSE @@ -1626,7 +1676,7 @@ typedef uint8_t FTDF_FrameType; * - FTDF_COMMAND_COORDINATOR_REALIGNMENT * - FTDF_COMMAND_GTS_REQUEST */ -typedef uint8_t FTDF_CommandFrameId; +typedef uint8_t ftdf_command_frame_id_t; #define FTDF_COMMAND_ASSOCIATION_REQUEST 1 #define FTDF_COMMAND_ASSOCIATION_RESPONSE 2 #define FTDF_COMMAND_DISASSOCIATION_NOTIFICATION 3 @@ -1642,122 +1692,114 @@ typedef uint8_t FTDF_CommandFrameId; * \remark Valid range 0..0xffffffff (4 octets) if frame counter mode equals 4 * \remark Valid range 0..0xffffffffff (5 octets) if frame counter mode equals 5 */ -typedef uint64_t FTDF_FrameCounter; +typedef uint64_t ftdf_frame_counter_t; /** * \brief Security frame counter mode * \remark Valid range 4..5 */ -typedef uint8_t FTDF_FrameCounterMode; +typedef uint8_t ftdf_frame_counter_mode_t; -typedef struct -{ - FTDF_KeyIdMode keyIdMode; - FTDF_Octet keySource[ 8 ]; - FTDF_KeyIndex keyIndex; - FTDF_AddressMode deviceAddrMode; - FTDF_PANId devicePANId; - FTDF_Address deviceAddress; -} FTDF_KeyIdLookupDescriptor; +typedef struct { + ftdf_key_id_mode_t key_id_mode; + ftdf_octet_t key_source[8]; + ftdf_key_index_t key_index; + ftdf_address_mode_t device_addr_mode; + ftdf_pan_id_t device_pan_id; + ftdf_address_t device_address; +} ftdf_key_id_lookup_descriptor_t; -typedef struct -{ - FTDF_PANId PANId; - FTDF_ShortAddress shortAddress; - FTDF_ExtAddress extAddress; - FTDF_FrameCounter frameCounter; - FTDF_Boolean exempt; -} FTDF_DeviceDescriptor; +typedef struct { + ftdf_pan_id_t pan_id; + ftdf_short_address_t short_address; + ftdf_ext_address_t ext_address; + ftdf_frame_counter_t frame_counter; + ftdf_boolean_t exempt; +} ftdf_device_descriptor_t; /** * \brief Device descriptor handle - * \remark This is the index of a device in \link FTDF_DeviceTable \endlink + * \remark This is the index of a device in \link ftdf_device_table_t \endlink */ -typedef uint8_t FTDF_DeviceDescriptorHandle; +typedef uint8_t ftdf_device_descriptor_handle_t; -typedef struct -{ - /** \brief Frame type */ - FTDF_FrameType frameType; - /** \brief Command frame ID */ - FTDF_CommandFrameId commandFrameId; -} FTDF_KeyUsageDescriptor; +typedef struct { + /** \brief Frame type */ + ftdf_frame_type_t frame_type; + /** \brief Command frame id */ + ftdf_command_frame_id_t command_frame_id; +} ftdf_key_usage_descriptor_t; -typedef struct -{ - FTDF_Size nrOfKeyIdLookupDescriptors; - FTDF_KeyIdLookupDescriptor* keyIdLookupDescriptors; - FTDF_Size nrOfDeviceDescriptorHandles; - FTDF_DeviceDescriptorHandle* deviceDescriptorHandles; - FTDF_Size nrOfKeyUsageDescriptors; - FTDF_KeyUsageDescriptor* keyUsageDescriptors; - FTDF_Octet key[ 16 ]; -} FTDF_KeyDescriptor; +typedef struct { + ftdf_size_t nr_of_key_id_lookup_descriptors; + ftdf_key_id_lookup_descriptor_t *key_id_lookup_descriptors; + ftdf_size_t nr_of_device_descriptor_handles; + ftdf_device_descriptor_handle_t *device_descriptor_handles; + ftdf_size_t nr_of_key_usage_descriptors; + ftdf_key_usage_descriptor_t *key_usage_descriptors; + ftdf_octet_t key[16]; +} ftdf_key_descriptor_t; -typedef struct -{ - FTDF_FrameType frameType; - FTDF_CommandFrameId commandFrameId; - FTDF_SecurityLevel securityMinimum; - FTDF_Boolean deviceOverrideSecurityMinimum; - FTDF_Bitmap8 allowedSecurityLevels; -} FTDF_SecurityLevelDescriptor; +typedef struct { + ftdf_frame_type_t frame_type; + ftdf_command_frame_id_t command_frame_id; + ftdf_security_level_t security_minimum; + ftdf_boolean_t device_override_security_minimum; + ftdf_bitmap8_t allowed_security_levels; +} ftdf_security_level_descriptor_t; /** * \brief Key table * \remark As followes an example how to initialize a key table for usage with FTDF_SET_REQUEST: * \code - * FTDF_KeyIdLookupDescriptor lookupDescriptorsKey1[ ] = + * ftdf_key_id_lookup_descriptor_t lookupDescriptorsKey1[] = * { { 2, { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef }, 7, 0, 0 0 }, * { 0, { 0, 0, 0, 0, 0, 0, 0, 0 }, 0, 2, 0x1234, 0x0001 } }; - * FTDF_KeyIdLookupDescriptor lookupDescriptorsKey2[ ] = + * ftdf_key_id_lookup_descriptor_t lookupDescriptorsKey2[] = * { { 1, { 0, 0, 0, 0, 0, 0, 0, 0 }, 5, 0, 0, 0 } }; - * FTDF_DeviceDescriptorHandle deviceDescriptorHandlesKey1[ ] = { 0, 2 }; - * FTDF_DeviceDescriptorHandle deviceDescriptorHandlesKey2[ ] = { 1 }; - * FTDF_KeyUsageDescriptor keyUsageDescriptorKey1[ ] = { { 1, 0 }, { 3, 4 } }; - * FTDF_KeyUsageDescriptor keyUsageDescriptorKey2[ ] = { { 1, 0 } }; - * FTDF_KeyDescriptor keyDescriptors[ ] = - * { { sizeof( lookupDescriptorsKey1 ) / sizeof( FTDF_KeyIdLookupDescriptor ), + * ftdf_device_descriptor_handle_t deviceDescriptorHandlesKey1[] = { 0, 2 }; + * ftdf_device_descriptor_handle_t deviceDescriptorHandlesKey2[] = { 1 }; + * ftdf_key_usage_descriptor_t keyUsageDescriptorKey1[] = { { 1, 0 }, { 3, 4 } }; + * ftdf_key_usage_descriptor_t keyUsageDescriptorKey2[] = { { 1, 0 } }; + * ftdf_key_descriptor_t key_descriptors[] = + * { { sizeof(lookupDescriptorsKey1) / sizeof(ftdf_key_id_lookup_descriptor_t), * lookupDescriptorsKey1, - * sizeof( deviceDescriptorHandlesKey1 ) / sizeof( FTDF_DeviceDescriptorHandle ), + * sizeof(deviceDescriptorHandlesKey1) / sizeof(ftdf_device_descriptor_handle_t), * deviceDescriptorHandlesKey1, - * sizeof( keyUsageDescriptorKey1 ) / sizeof( FTDF_KeyUsageDescriptor ), + * sizeof(keyUsageDescriptorKey1) / sizeof(ftdf_key_usage_descriptor_t), * keyUsageDescriptorKey1, * { 0x7e, 0x37, 0x2d, 0x41, 0xdf, 0x74, 0x72, 0x3f, 0x4c, 0x3a, 0xa7, 0x53, 0xa1, 0x11, 0x46, 0x8b } }, - * { sizeof( lookupDescriptorsKey2 ) / sizeof( FTDF_KeyIdLookupDescriptor ), + * { sizeof(lookupDescriptorsKey2) / sizeof(ftdf_key_id_lookup_descriptor_t), * lookupDescriptorsKey2, - * sizeof( deviceDescriptorHandlesKey2 ) / sizeof( FTDF_DeviceDescriptorHandle ), + * sizeof(deviceDescriptorHandlesKey2) / sizeof(ftdf_device_descriptor_handle_t), * deviceDescriptorHandlesKey2, - * sizeof( keyUsageDescriptorKey2 ) / sizeof( FTDF_KeyUsageDescriptor ), + * sizeof(keyUsageDescriptorKey2) / sizeof(ftdf_key_usage_descriptor_t), * keyUsageDescriptorKey1, * { 0xdf, 0x74, 0x72, 0x3f, 0x7e, 0x37, 0x2d, 0x41, 0x4c, 0x3a, 0xa1, 0x11, 0x46, 0x8, 0xa7, 0x53b } } }; - * FTDF_KeyTable keyTable = - * { sizeof( keyDescriptors ) / sizeof( FTDF_KeyDescriptor ), keyDescriptors }; + * ftdf_key_table_t keyTable = + * { sizeof(key_descriptors) / sizeof(ftdf_key_descriptor_t), key_descriptors }; * \endcode */ -typedef struct -{ - /** \brief Number of key descriptors in the key table */ - FTDF_Size nrOfKeyDescriptors; - /** \brief Pointer to the first key descriptor entry */ - FTDF_KeyDescriptor* keyDescriptors; -} FTDF_KeyTable; +typedef struct { + /** \brief Number of key descriptors in the key table */ + ftdf_size_t nr_of_key_descriptors; + /** \brief Pointer to the first key descriptor entry */ + ftdf_key_descriptor_t *key_descriptors; +} ftdf_key_table_t; -typedef struct -{ - /** \brief Number of device descriptors in the key table */ - FTDF_Size nrOfDeviceDescriptors; - /** \brief Pointer to the first device descriptor entry */ - FTDF_DeviceDescriptor* deviceDescriptors; -} FTDF_DeviceTable; +typedef struct { + /** \brief Number of device descriptors in the key table */ + ftdf_size_t nr_of_device_descriptors; + /** \brief Pointer to the first device descriptor entry */ + ftdf_device_descriptor_t *device_descriptors; +} ftdf_device_table_t; -typedef struct -{ - /** \brief Number of security level descriptors in the key table */ - FTDF_Size nrOfSecurityLevelDescriptors; - /** \brief Pointer to the first security level descriptor entry */ - FTDF_SecurityLevelDescriptor* securityLevelDescriptors; -} FTDF_SecurityLevelTable; +typedef struct { + /** \brief Number of security level descriptors in the key table */ + ftdf_size_t nr_of_security_level_descriptors; + /** \brief Pointer to the first security level descriptor entry */ + ftdf_security_level_descriptor_t *security_level_descriptors; +} ftdf_security_level_table_t; /** * \brief IE type @@ -1765,1125 +1807,1067 @@ typedef struct * - FTDF_SHORT_IE * - FTDF_LONG_IE */ -typedef uint8_t FTDF_IEType; +typedef uint8_t ftdf_ie_type_t; #define FTDF_SHORT_IE 0 #define FTDF_LONG_IE 1 -typedef uint8_t FTDF_IEId; +typedef uint8_t ftdf_ie_id_t; -typedef uint8_t FTDF_IELength; +typedef uint8_t ftdf_ie_length_t; -typedef struct -{ - /** \brief IE type */ - FTDF_IEType type; - /** \brief Sub IE ID*/ - FTDF_IEId subID; - /** \brief Sub IE length */ - FTDF_IELength length; - /** \brief Pointer to sub IE content */ - FTDF_Octet* subContent; -} FTDF_SubIEDescriptor; +typedef struct { + /** \brief IE type */ + ftdf_ie_type_t type; + /** \brief Sub IE id*/ + ftdf_ie_id_t sub_id; + /** \brief Sub IE length */ + ftdf_ie_length_t length; + /** \brief Pointer to sub IE content */ + ftdf_octet_t *sub_content; +} ftdf_sub_ie_descriptor_t; -typedef struct -{ - /** \brief Number of sub IE descriptors in an MLME payload IE (ID = 1) */ - FTDF_Size nrOfSubIEs; - /** \brief Pointer to the first sub IE descriptor */ - FTDF_SubIEDescriptor* subIEs; -} FTDF_SubIEList; +typedef struct { + /** \brief Number of sub IE descriptors in an MLME payload IE (id = 1) */ + ftdf_size_t nr_of_sub_ie; + /** \brief Pointer to the first sub IE descriptor */ + ftdf_sub_ie_descriptor_t *sub_ie; +} ftdf_sub_ie_list_t; -typedef union -{ - /** \brief IE content if not a MLME payload IE (ID = 1) */ - FTDF_Octet* raw; - /** \brief IE content if a MLME payload IE (ID = 1) */ - FTDF_SubIEList* nested; -} FTDF_IEContent; +typedef union { + /** \brief IE content if not a MLME payload IE (id = 1) */ + ftdf_octet_t *raw; + /** \brief IE content if a MLME payload IE (id = 1) */ + ftdf_sub_ie_list_t *nested; +} ftdf_ie_content_t; -typedef struct -{ - /** \brief IE ID */ - FTDF_IEId ID; - /** \brief Content length of the IE, undefined/unused in case of a MLME payload IE (ID = 1) */ - FTDF_IELength length; - /** \brief Content of the IE */ - FTDF_IEContent content; -} FTDF_IEDescriptor; +typedef struct { + /** \brief IE id */ + ftdf_ie_id_t id; + /** \brief Content length of the IE, undefined/unused in case of a MLME payload IE (id = 1) */ + ftdf_ie_length_t length; + /** \brief Content of the IE */ + ftdf_ie_content_t content; +} ftdf_ie_descriptor_t; -typedef struct -{ - /** \brief Number of IE descriptors */ - FTDF_Size nrOfIEs; - /** \brief Pointer to the first IE descriptor */ - FTDF_IEDescriptor* IEs; -} FTDF_IEList; +typedef struct { + /** \brief Number of IE descriptors */ + ftdf_size_t nr_of_ie; + /** \brief Pointer to the first IE descriptor */ + ftdf_ie_descriptor_t *ie; +} ftdf_ie_list_t; -typedef struct -{ - /** \brief Message ID */ - FTDF_MsgId msgId; -} FTDF_MsgBuffer; +typedef struct { + /** \brief Message id */ + ftdf_msg_id_t msg_id; +} ftdf_msg_buffer_t; -typedef struct -{ - /** \brief Message ID = FTDF_DATA_REQUEST */ - FTDF_MsgId msgId; - /** \brief Source address mode */ - FTDF_AddressMode srcAddrMode; - /** \brief Destination address mode */ - FTDF_AddressMode dstAddrMode; - /** \brief Destination PAN ID */ - FTDF_PANId dstPANId; - /** \brief Destination address */ - FTDF_Address dstAddr; - /** \brief Length of MSDU payload */ - FTDF_DataLength msduLength; - /** - * \brief MSDU payload data buffer. Must be freed by the application using FTDF_REL_DATA_BUFFER - * when it receives the FTDF_DATA_CONFIRM message - */ - FTDF_Octet* msdu; - /** \brief Handle */ - FTDF_Handle msduHandle; - /** \brief Whether the data frame needs to be acknowledged or */ - FTDF_Boolean ackTX; - /** \brief NOT USED */ - FTDF_Boolean GTSTX; - /** - * \brief Indication whether the frame must be send directly or be queued until a DATA_REQUEST COMMAND - * frame is received - */ - FTDF_Boolean indirectTX; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; - /** \brief Frame control option bitmap */ - FTDF_FrameControlOptions frameControlOptions; - /** - * \brief Header IE list to be inserted. - * Ignored if the FTDF_IES_INCLUDED frame control option is NOT set. - * The IE list must be located in rentention RAM - */ - FTDF_IEList* headerIEList; - /** - * \brief Payload IE list to be inserted. - * Ignored if the FTDF_IES_INCLUDED frame control option is NOT set. - * The IE list must be located in rentention RAM - */ - FTDF_IEList* payloadIEList; - /** Indication whether a DATA or MULTIPURPOSE frame must be set */ - FTDF_Boolean sendMultiPurpose; - /** \brief DO NOT USE */ - uint8_t __private3; -} FTDF_DataRequest; +typedef struct { + /** \brief Message id = FTDF_DATA_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Source address mode */ + ftdf_address_mode_t src_addr_mode; + /** \brief Destination address mode */ + ftdf_address_mode_t dst_addr_mode; + /** \brief Destination PAN id */ + ftdf_pan_id_t dst_pan_id; + /** \brief Destination address */ + ftdf_address_t dst_addr; + /** \brief Length of MSDU payload */ + ftdf_data_length_t msdu_length; + /** + * \brief MSDU payload data buffer. Must be freed by the application using FTDF_REL_DATA_BUFFER + * when it receives the FTDF_DATA_CONFIRM message + */ + ftdf_octet_t *msdu; + /** \brief Handle */ + ftdf_handle_t msdu_handle; + /** \brief Whether the data frame needs to be acknowledged or */ + ftdf_boolean_t ack_tx; + /** \brief NOT USED */ + ftdf_boolean_t gts_tx; + /** + * \brief Indication whether the frame must be send directly or be queued until a + * DATA_REQUEST COMMAND frame is received + */ + ftdf_boolean_t indirect_tx; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; + /** \brief Frame control option bitmap */ + ftdf_frame_control_options_t frame_control_options; + /** + * \brief Header IE list to be inserted. + * Ignored if the FTDF_IES_INCLUDED frame control option is NOT set. + * The IE list must be located in rentention RAM + */ + ftdf_ie_list_t *header_ie_list; + /** + * \brief Payload IE list to be inserted. + * Ignored if the FTDF_IES_INCLUDED frame control option is NOT set. + * The IE list must be located in rentention RAM + */ + ftdf_ie_list_t *payload_ie_list; + /** Indication whether a DATA or MULTIPURPOSE frame must be set */ + ftdf_boolean_t send_multi_purpose; + /** \brief DO NOT USE */ + uint8_t __private3; +} ftdf_data_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_DATA_INDICATION */ - FTDF_MsgId msgId; - /** \brief Source address mode */ - FTDF_AddressMode srcAddrMode; - /** \brief Source PAN ID */ - FTDF_PANId srcPANId; - /** \brief Source address */ - FTDF_Address srcAddr; - /** \brief Destination address mode */ - FTDF_AddressMode dstAddrMode; - /** \brief Destination PAN ID */ - FTDF_PANId dstPANId; - /** \brief Destination address */ - FTDF_Address dstAddr; - /** \brief Length of MSDU payload */ - FTDF_DataLength msduLength; - /** \brief MSDU payload data buffer Must be freed by the application using FTDF_REL_DATA_BUFFER */ - FTDF_Octet* msdu; - /** \brief MPDU link quality */ - FTDF_LinkQuality mpduLinkQuality; - /** \brief Data sequence number */ - FTDF_SN DSN; - /** \brief Timestamp of the time the frame was received */ - FTDF_Time timestamp; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; - /** /brief Payload IE list
- * The whole payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocated in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER - * with the IEList pointer as parameter - */ - FTDF_IEList* payloadIEList; -} FTDF_DataIndication; +typedef struct { + /** \brief Message id = FTDF_DATA_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief Source address mode */ + ftdf_address_mode_t src_addr_mode; + /** \brief Source PAN id */ + ftdf_pan_id_t src_pan_id; + /** \brief Source address */ + ftdf_address_t src_addr; + /** \brief Destination address mode */ + ftdf_address_mode_t dst_addr_mode; + /** \brief Destination PAN id */ + ftdf_pan_id_t dst_pan_id; + /** \brief Destination address */ + ftdf_address_t dst_addr; + /** \brief Length of MSDU payload */ + ftdf_data_length_t msdu_length; + /** \brief MSDU payload data buffer Must be freed by the application using FTDF_REL_DATA_BUFFER */ + ftdf_octet_t *msdu; + /** \brief MPDU link quality */ + ftdf_link_quality_t mpdu_link_quality; + /** \brief Data sequence number */ + ftdf_sn_t dsn; + /** \brief Timestamp of the time the frame was received */ + ftdf_time_t timestamp; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; + /** /brief Payload IE list
+ * The whole payload IE list (including IE descriptors, Sub IE descriptors and content) + * is allocated in one data buffer that must be freed by the application using + * FTDF_REL_DATA_BUFFER + * with the ie_list pointer as parameter + */ + ftdf_ie_list_t *payload_ie_list; +} ftdf_data_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_DATA_CONFIRM */ - FTDF_MsgId msgId; - /** /brief The handle given by the application in the correspoding FTDF_DATA_REQUEST */ - FTDF_Handle msduHandle; - /** /brief Timestmap of the time the frame has been sent */ - FTDF_Time timestamp; - /** /brief Status of the data request */ - FTDF_Status status; - /** /brief Number of backoffs, undefined in case status not equal to FTDF_SUCCESS or TSCH enabled */ - FTDF_NumOfBackoffs numOfBackoffs; - /** /brief Data sequence number of the sent frame */ - FTDF_SN DSN; - /** /brief Acknowledgement payload IE list
- * The whole payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocated in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER - * with the IEList pointer as parameter - */ - FTDF_IEList* ackPayload; -} FTDF_DataConfirm; +typedef struct { + /** \brief Message id = FTDF_DATA_CONFIRM */ + ftdf_msg_id_t msg_id; + /** /brief The handle given by the application in the correspoding FTDF_DATA_REQUEST */ + ftdf_handle_t msdu_handle; + /** /brief Timestmap of the time the frame has been sent */ + ftdf_time_t timestamp; + /** /brief Status of the data request */ + ftdf_status_t status; + /** /brief Number of backoffs, undefined in case status not equal to FTDF_SUCCESS or TSCH enabled */ + ftdf_num_of_backoffs_t num_of_backoffs; + /** /brief Data sequence number of the sent frame */ + ftdf_sn_t dsn; + /** /brief Acknowledgement payload IE list
+ * The whole payload IE list (including IE descriptors, Sub IE descriptors and content) + * is allocated in one data buffer that must be freed by the application using + * FTDF_REL_DATA_BUFFER with the ie_list pointer as parameter + */ + ftdf_ie_list_t *ack_payload; +} ftdf_data_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_PURGE_REQUEST */ - FTDF_MsgId msgId; - /** \brief Handle the data request to be purged */ - FTDF_Handle msduHandle; -} FTDF_PurgeRequest; +typedef struct { + /** \brief Message id = FTDF_PURGE_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Handle the data request to be purged */ + ftdf_handle_t msdu_handle; +} ftdf_purge_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_PURGE_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Handle of the purged data request */ - FTDF_Handle msduHandle; - /** /brief Status of the purge request */ - FTDF_Status status; -} FTDF_PurgeConfirm; +typedef struct { + /** \brief Message id = FTDF_PURGE_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Handle of the purged data request */ + ftdf_handle_t msdu_handle; + /** /brief Status of the purge request */ + ftdf_status_t status; +} ftdf_purge_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_ASSOCIATE_REQUEST */ - FTDF_MsgId msgId; - /** \brief Channel number to be used for the associate request. Ignored in TSCH mode */ - FTDF_ChannelNumber channelNumber; - /** \brief Channel page to be used for the associate request. Ignored in TSCH mode */ - FTDF_ChannelPage channelPage; - /** \brief Coordinator address mode */ - FTDF_AddressMode coordAddrMode; - /** \brief Coordinator PAN ID */ - FTDF_PANId coordPANId; - /** \brief Coordinator address */ - FTDF_Address coordAddr; - /** - * \brief Capabillity information bitmap. The following capabilities are defined:
- * FTDF_CAPABILITY_IS_FFD: Device is a full function device
- * FTDF_CAPABILITY_AC_POWER: Device has AC power
- * FTDF_CAPABILITY_RECEIVER_ON_WHEN_IDLE: Device receiver is on when idle
- * FTDF_CAPABILITY_FAST_ASSOCIATION: Device wants a fast association
- * FTDF_CAPABILITY_SUPPORTS_SECURITY: Device supports security
- * FTDF_CAPABILITY_WANTS_SHORT_ADDRESS: Device wants short address
- */ - FTDF_Bitmap8 capabilityInformation; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; - /** \brief NOT USED */ - FTDF_ChannelOffset channelOffset; - /** \brief NOT USED */ - FTDF_HoppingSequenceId hoppingSequenceId; - /** \brief DO NOT USE */ - uint8_t __private3; -} FTDF_AssociateRequest; +typedef struct { + /** \brief Message id = FTDF_ASSOCIATE_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Channel number to be used for the associate request. Ignored in TSCH mode */ + ftdf_channel_number_t channel_number; + /** \brief Channel page to be used for the associate request. Ignored in TSCH mode */ + ftdf_channel_page_t channel_page; + /** \brief Coordinator address mode */ + ftdf_address_mode_t coord_addr_mode; + /** \brief Coordinator PAN id */ + ftdf_pan_id_t coord_pan_id; + /** \brief Coordinator address */ + ftdf_address_t coord_addr; + /** + * \brief Capabillity information bitmap. The following capabilities are defined:
+ * FTDF_CAPABILITY_IS_FFD: Device is a full function device
+ * FTDF_CAPABILITY_AC_POWER: Device has AC power
+ * FTDF_CAPABILITY_RECEIVER_ON_WHEN_IDLE: Device receiver is on when idle
+ * FTDF_CAPABILITY_FAST_ASSOCIATION: Device wants a fast association
+ * FTDF_CAPABILITY_SUPPORTS_SECURITY: Device supports security
+ * FTDF_CAPABILITY_WANTS_SHORT_ADDRESS: Device wants short address
+ */ + ftdf_bitmap8_t capability_information; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; + /** \brief NOT USED */ + ftdf_channel_offset_t channel_offset; + /** \brief NOT USED */ + ftdf_hopping_sequence_id_t hopping_sequence_id; + /** \brief DO NOT USE */ + uint8_t __private3; +} ftdf_associate_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_ASSOCIATE_INDICATION */ - FTDF_MsgId msgId; - /** \brief Extended address of the device that did the association request */ - FTDF_ExtAddress deviceAddress; - /** - * \brief Capabillity information bitmap. The following capabilities are defined:
- * FTDF_CAPABILITY_IS_FFD: Device is a full function device
- * FTDF_CAPABILITY_AC_POWER: Device has AC power
- * FTDF_CAPABILITY_RECEIVER_ON_WHEN_IDLE: Device receiver is on when idle
- * FTDF_CAPABILITY_FAST_ASSOCIATION: Device wants a fast association
- * FTDF_CAPABILITY_SUPPORTS_SECURITY: Device supports security
- * FTDF_CAPABILITY_WANTS_SHORT_ADDRESS: Device wants short address
- */ - FTDF_Bitmap8 capabilityInformation; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; - /** \brief NOT USED */ - FTDF_ChannelOffset channelOffset; - /** \brief NOT USED */ - FTDF_HoppingSequenceId hoppingSequenceId; -} FTDF_AssociateIndication; +typedef struct { + /** \brief Message id = FTDF_ASSOCIATE_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief Extended address of the device that did the association request */ + ftdf_ext_address_t device_address; + /** + * \brief Capabillity information bitmap. The following capabilities are defined:
+ * FTDF_CAPABILITY_IS_FFD: Device is a full function device
+ * FTDF_CAPABILITY_AC_POWER: Device has AC power
+ * FTDF_CAPABILITY_RECEIVER_ON_WHEN_IDLE: Device receiver is on when idle
+ * FTDF_CAPABILITY_FAST_ASSOCIATION: Device wants a fast association
+ * FTDF_CAPABILITY_SUPPORTS_SECURITY: Device supports security
+ * FTDF_CAPABILITY_WANTS_SHORT_ADDRESS: Device wants short address
+ */ + ftdf_bitmap8_t capability_information; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; + /** \brief NOT USED */ + ftdf_channel_offset_t channel_offset; + /** \brief NOT USED */ + ftdf_hopping_sequence_id_t hopping_sequence_id; +} ftdf_associate_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_ASSOCIATE_RESPONSE */ - FTDF_MsgId msgId; - /** \brief Extended address of the device that did association request and to which the response needs to be send */ - FTDF_ExtAddress deviceAddress; - /** \brief The short address for the device that did the associate request */ - FTDF_ShortAddress assocShortAddress; - /** \brief The association status of the associate request */ - FTDF_AssociationStatus status; - /** \brief Indication whether this a response to fast or normal association request */ - FTDF_Boolean fastA; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; - /** \brief NOT USED */ - FTDF_ChannelOffset channelOffset; - /** \brief NOT USED */ - FTDF_Length hoppingSequenceLength; - /** \brief NOT USED */ - FTDF_Octet* hoppingSequence; - /** \brief DO NOT USE */ - uint8_t __private3; -} FTDF_AssociateResponse; +typedef struct { + /** \brief Message id = FTDF_ASSOCIATE_RESPONSE */ + ftdf_msg_id_t msg_id; + /** \brief Extended address of the device that did association request and to which the response needs to be send */ + ftdf_ext_address_t device_address; + /** \brief The short address for the device that did the associate request */ + ftdf_short_address_t assoc_short_address; + /** \brief The association status of the associate request */ + ftdf_association_status_t status; + /** \brief Indication whether this a response to fast or normal association request */ + ftdf_boolean_t fast_a; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; + /** \brief NOT USED */ + ftdf_channel_offset_t channel_offset; + /** \brief NOT USED */ + ftdf_length_t hopping_sequence_length; + /** \brief NOT USED */ + ftdf_octet_t* hopping_sequence; + /** \brief DO NOT USE */ + uint8_t __private3; +} ftdf_associate_response_t; -typedef struct -{ - /** \brief Message ID = FTDF_ASSOCIATE_CONFIRM */ - FTDF_MsgId msgId; - /** \brief The short adddress assigned by the coordinator */ - FTDF_ShortAddress assocShortAddress; - /** \brief Status of the associate request */ - FTDF_Status status; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; - /** \brief NOT USED */ - FTDF_ChannelOffset channelOffset; - /** \brief NOT USED */ - FTDF_Length hoppingSequenceLength; - /** \brief NOT USED */ - FTDF_Octet* hoppingSequence; -} FTDF_AssociateConfirm; +typedef struct { + /** \brief Message id = FTDF_ASSOCIATE_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief The short adddress assigned by the coordinator */ + ftdf_short_address_t assoc_short_address; + /** \brief Status of the associate request */ + ftdf_status_t status; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; + /** \brief NOT USED */ + ftdf_channel_offset_t channel_offset; + /** \brief NOT USED */ + ftdf_length_t hopping_sequence_length; + /** \brief NOT USED */ + ftdf_octet_t *hopping_sequence; +} ftdf_associate_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_DISASSOCIATE_REQUEST */ - FTDF_MsgId msgId; - /** \brief Device address mode */ - FTDF_AddressMode deviceAddrMode; - /** \brief Device PAN ID */ - FTDF_PANId devicePANId; - /** \brief Device address */ - FTDF_Address deviceAddress; - /** \brief Disassociate reason */ - FTDF_DisassociateReason disassociateReason; - /** - * \brief Indication whether the disassociate request must be send directly or be queued until a - * DATA_REQUEST command frame is received - */ - FTDF_Boolean txIndirect; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; - /** \brief DO NOT USE */ - uint8_t __private3; -} FTDF_DisassociateRequest; +typedef struct { + /** \brief Message id = FTDF_DISASSOCIATE_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Device address mode */ + ftdf_address_mode_t device_addr_mode; + /** \brief Device PAN id */ + ftdf_pan_id_t device_pan_id; + /** \brief Device address */ + ftdf_address_t device_address; + /** \brief Disassociate reason */ + ftdf_disassociate_reason_t disassociate_reason; + /** + * \brief Indication whether the disassociate request must be send directly or be queued until a + * DATA_REQUEST command frame is received + */ + ftdf_boolean_t tx_indirect; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; + /** \brief DO NOT USE */ + uint8_t __private3; +} ftdf_disassociate_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_DISASSOCIATE_INDICATION */ - FTDF_MsgId msgId; - /** \brief Extended address of the device that did disassociate request */ - FTDF_ExtAddress deviceAddress; - /** \brief Disassociate reason */ - FTDF_DisassociateReason disassociateReason; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; -} FTDF_DisassociateIndication; +typedef struct { + /** \brief Message id = FTDF_DISASSOCIATE_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief Extended address of the device that did disassociate request */ + ftdf_ext_address_t device_address; + /** \brief Disassociate reason */ + ftdf_disassociate_reason_t disassociate_reason; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; +} ftdf_disassociate_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_DISASSOCIATE_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Disassociate request status */ - FTDF_Status status; - /** \brief Address mode of the device that want/must disassociate */ - FTDF_AddressMode deviceAddrMode; - /** \brief PAN ID of the device that want/must disassociate */ - FTDF_PANId devicePANId; - /** \brief address of the device that want/must disassociate */ - FTDF_Address deviceAddress; -} FTDF_DisassociateConfirm; +typedef struct { + /** \brief Message id = FTDF_DISASSOCIATE_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Disassociate request status */ + ftdf_status_t status; + /** \brief Address mode of the device that want/must disassociate */ + ftdf_address_mode_t device_addr_mode; + /** \brief PAN id of the device that want/must disassociate */ + ftdf_pan_id_t device_pan_id; + /** \brief address of the device that want/must disassociate */ + ftdf_address_t device_address; +} ftdf_disassociate_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_BEACON_NOTIFY_INDCATION */ - FTDF_MsgId msgId; - /** \brief Beacon sequence number, valid only when beacon type is FTDF_NORMAL_BEACON */ - FTDF_SN BSN; - /** \brief PAN descriptor*/ - FTDF_PANDescriptor* PANDescriptor; - /** \brief NOT USED */ - FTDF_Bitmap8 pendAddrSpec; - /** \brief NOT USED */ - FTDF_Address* addrList; - /** \brief Length of the beacon payload */ - FTDF_DataLength sduLength; - /** \brief Beacon payload */ - FTDF_Octet* sdu; - /** \brief Enhanced beacon sequence number, valid only when beacon type is FTDF_ENHANCED_BEACON */ - FTDF_SN EBSN; - /** \brief Beacon type */ - FTDF_BeaconType beaconType; - /** - * \brief Payload IE list
- * The whole Payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocate in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER - * with the IEList pointer as parameter. - */ - FTDF_IEList* IEList; - /** - * \brief Timestamp of the time the beacon frame was received
- * In TSCH mode this timestamp should be used to calculate the TSCH timeslot start time - * required in a FTDF_TSCH_MODE_REQUEST message - */ - FTDF_Time64 timestamp; -} FTDF_BeaconNotifyIndication; +typedef struct { + /** \brief Message id = FTDF_BEACON_NOTIFY_INDCATION */ + ftdf_msg_id_t msg_id; + /** \brief Beacon sequence number, valid only when beacon type is FTDF_NORMAL_BEACON */ + ftdf_sn_t bsn; + /** \brief PAN descriptor*/ + ftdf_pan_descriptor_t *pan_descriptor; + /** \brief NOT USED */ + ftdf_bitmap8_t pend_addr_spec; + /** \brief NOT USED */ + ftdf_address_t *addr_list; + /** \brief Length of the beacon payload */ + ftdf_data_length_t sdu_length; + /** \brief Beacon payload */ + ftdf_octet_t *sdu; + /** \brief Enhanced beacon sequence number, valid only when beacon type is FTDF_ENHANCED_BEACON */ + ftdf_sn_t eb_sn; + /** \brief Beacon type */ + ftdf_beacon_type_t beacon_type; + /** + * \brief Payload IE list
+ * The whole Payload IE list (including IE descriptors, Sub IE descriptors and content) + * is allocate in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER + * with the ie_list pointer as parameter. + */ + ftdf_ie_list_t *ie_list; + /** + * \brief Timestamp of the time the beacon frame was received
+ * In TSCH mode this timestamp should be used to calculate the TSCH timeslot start time + * required in a FTDF_TSCH_MODE_REQUEST message + */ + ftdf_time64_t timestamp; +} ftdf_beacon_notify_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_COMM_STATUS_INDICATION */ - FTDF_MsgId msgId; - /** \brief PAN ID of the frame causing the error */ - FTDF_PANId PANId; - /** \brief Source address mode of the frame causing the error */ - FTDF_AddressMode srcAddrMode; - /** \brief Source address of the frame causing the error */ - FTDF_Address srcAddr; - /** \brief Destination address mode of the frame causing the error */ - FTDF_AddressMode dstAddrMode; - /** \brief Destination address of the frame causing the error */ - FTDF_Address dstAddr; - /** \brief Error status */ - FTDF_Status status; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; -} FTDF_CommStatusIndication; +typedef struct { + /** \brief Message id = FTDF_COMM_STATUS_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief PAN id of the frame causing the error */ + ftdf_pan_id_t pan_id; + /** \brief Source address mode of the frame causing the error */ + ftdf_address_mode_t src_addr_mode; + /** \brief Source address of the frame causing the error */ + ftdf_address_t src_addr; + /** \brief Destination address mode of the frame causing the error */ + ftdf_address_mode_t dst_addr_mode; + /** \brief Destination address of the frame causing the error */ + ftdf_address_t dst_addr; + /** \brief Error status */ + ftdf_status_t status; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; +} ftdf_comm_status_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_GET_REQUEST */ - FTDF_MsgId msgId; - FTDF_PIBAttribute PIBAttribute; -} FTDF_GetRequest; +typedef struct { + /** \brief Message id = FTDF_GET_REQUEST */ + ftdf_msg_id_t msg_id; + ftdf_pib_attribute_t pib_attribute; +} ftdf_get_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_GET_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the get request */ - FTDF_Status status; - /** \brief PIB attribute ID of PIB attribute gotten */ - FTDF_PIBAttribute PIBAttribute; - /** - * \brief Pointer to the PIB attribute value to be set
- * Each PIB attribute has its own type, see \link FTDF_PIBAttribute \endlink
- * In order to access the attribute value the application must cast this pinter - * to the correct type. - */ - const FTDF_PIBAttributeValue* PIBAttributeValue; -} FTDF_GetConfirm; +typedef struct { + /** \brief Message id = FTDF_GET_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the get request */ + ftdf_status_t status; + /** \brief PIB attribute id of PIB attribute gotten */ + ftdf_pib_attribute_t pib_attribute; + /** + * \brief Pointer to the PIB attribute value to be set
+ * Each PIB attribute has its own type, see \link ftdf_pib_attribute_t \endlink
+ * In order to access the attribute value the application must cast this pinter + * to the correct type. + */ + const ftdf_pib_attribute_value_t *pib_attribute_value; +} ftdf_get_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_SET_REQUEST */ - FTDF_MsgId msgId; - /** \brief PIB attribute ID of attribute to be set */ - FTDF_PIBAttribute PIBAttribute; - /** - * \brief Pointer to the PIB attribute value to be set
- * Each PIB attribute has its own type, see \link FTDF_PIBAttribute \endlink
- * FTDF does a shallow copy of the PIB attribute. So if the PIB attribute contains pointers to - * other data this data is NOT copied by FTDF. The application must make sure that data referred - * from a PIB attribute is statically allocated in retention RAM. - */ - const FTDF_PIBAttributeValue* PIBAttributeValue; -} FTDF_SetRequest; +typedef struct { + /** \brief Message id = FTDF_SET_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief PIB attribute id of attribute to be set */ + ftdf_pib_attribute_t pib_attribute; + /** + * \brief Pointer to the PIB attribute value to be set
+ * Each PIB attribute has its own type, see \link ftdf_pib_attribute_t \endlink
+ * FTDF does a shallow copy of the PIB attribute. So if the PIB attribute contains pointers to + * other data this data is NOT copied by FTDF. The application must make sure that data referred + * from a PIB attribute is statically allocated in retention RAM. + */ + const ftdf_pib_attribute_value_t *pib_attribute_value; +} ftdf_set_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_GET_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Set request status */ - FTDF_Status status; - /** \brief PIB Attribute ID of PIB attribute that has been set */ - FTDF_PIBAttribute PIBAttribute; -} FTDF_SetConfirm; +typedef struct { + /** \brief Message id = FTDF_GET_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Set request status */ + ftdf_status_t status; + /** \brief PIB Attribute id of PIB attribute that has been set */ + ftdf_pib_attribute_t pib_attribute; +} ftdf_set_confirm_t; -typedef struct -{ - FTDF_MsgId msgId; - FTDF_GTSCharateristics GTSCharateristics; - FTDF_SecurityLevel securityLevel; - FTDF_KeyIdMode keyIdMode; - FTDF_Octet keySource[ 8 ]; - FTDF_KeyIndex keyIndex; -} FTDF_GtsRequest; +typedef struct { + ftdf_msg_id_t msg_id; + ftdf_gts_charateristics_t gts_charateristics; + ftdf_security_level_t security_level; + ftdf_key_id_mode_t key_id_mode; + ftdf_octet_t key_source[8]; + ftdf_key_index_t key_index; +} ftdf_gts_request_t; -typedef struct -{ - FTDF_MsgId msgId; - FTDF_GTSCharateristics GTSCharateristics; - FTDF_Status status; -} FTDF_GtsConfirm; +typedef struct { + ftdf_msg_id_t msg_id; + ftdf_gts_charateristics_t gts_charateristics; + ftdf_status_t status; +} ftdf_gts_confirm_t; -typedef struct -{ - FTDF_MsgId msgId; - FTDF_ShortAddress deviceAddress; - FTDF_GTSCharateristics GTSCharateristics; - FTDF_SecurityLevel securityLevel; - FTDF_KeyIdMode keyIdMode; - FTDF_Octet keySource[ 8 ]; - FTDF_KeyIndex keyIndex; -} FTDF_GtsIndication; +typedef struct { + ftdf_msg_id_t msg_id; + ftdf_short_address_t device_address; + ftdf_gts_charateristics_t gts_charateristics; + ftdf_security_level_t security_level; + ftdf_key_id_mode_t key_id_mode; + ftdf_octet_t key_source[8]; + ftdf_key_index_t key_index; +} ftdf_gts_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_ORPHAN_INDICATION */ - FTDF_MsgId msgId; - /** \brief Extended address of orphaned device */ - FTDF_ExtAddress orphanAddress; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; -} FTDF_OrphanIndication; +typedef struct { + /** \brief Message id = FTDF_ORPHAN_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief Extended address of orphaned device */ + ftdf_ext_address_t orphan_address; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; +} ftdf_orphan_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_ORPHAN_RESPONSE */ - FTDF_MsgId msgId; - /** \brief Extended address of orphaned device */ - FTDF_ExtAddress orphanAddress; - /** \brief Short address of orphaned device */ - FTDF_ShortAddress shortAddress; - /** \brief Indication whether the device is associated with this coordinator or not */ - FTDF_Boolean associatedMember; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; -} FTDF_OrphanResponse; +typedef struct { + /** \brief Message id = FTDF_ORPHAN_RESPONSE */ + ftdf_msg_id_t msg_id; + /** \brief Extended address of orphaned device */ + ftdf_ext_address_t orphan_address; + /** \brief Short address of orphaned device */ + ftdf_short_address_t short_address; + /** \brief Indication whether the device is associated with this coordinator or not */ + ftdf_boolean_t associated_member; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; +} ftdf_orphan_response_t; -typedef struct -{ - /** \brief Message ID = FTDF_RESET_REQUEST */ - FTDF_MsgId msgId; - /** \brief Indicatione whether the PIB attributes must be reset to their default values or not */ - FTDF_Boolean setDefaultPIB; -} FTDF_ResetRequest; +typedef struct { + /** \brief Message id = FTDF_RESET_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Indication whether the PIB attributes must be reset to their default values or not */ + ftdf_boolean_t set_default_pib; +} ftdf_reset_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_RESET_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the reset request */ - FTDF_Status status; -} FTDF_ResetConfirm; +typedef struct { + /** \brief Message id = FTDF_RESET_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the reset request */ + ftdf_status_t status; +} ftdf_reset_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_RX_ENABLE_REQUEST */ - FTDF_MsgId msgId; - /** \brief NOT USED */ - FTDF_Boolean deferPermit; - /** \brief NOT USED */ - FTDF_Time rxOnTime; - /** \brief The time in aBaseSuperFramePeriod's (960 symbols) that the receiver will be on */ - FTDF_Time rxOnDuration; -} FTDF_RxEnableRequest; +typedef struct { + /** \brief Message id = FTDF_RX_ENABLE_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief NOT USED */ + ftdf_boolean_t defer_permit; + /** \brief NOT USED */ + ftdf_time_t rx_on_time; + /** \brief The time in aBaseSuperFramePeriod's (960 symbols) that the receiver will be on */ + ftdf_time_t rx_on_duration; +} ftdf_rx_enable_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_RX_ENABLE_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the RX enable request */ - FTDF_Status status; -} FTDF_RxEnableConfirm; +typedef struct { + /** \brief Message id = FTDF_RX_ENABLE_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the RX enable request */ + ftdf_status_t status; +} ftdf_rx_enable_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_SCAN_REQUEST */ - FTDF_MsgId msgId; - /** \brief Scan Type */ - FTDF_ScanType scanType; - /** \brief Bitmap of the channels to be scanned (only channel 11 - 27 are supported ) */ - FTDF_Bitmap32 scanChannels; - /** \brief Channel page of the channels to be scanned (only page 0 is supported ) */ - FTDF_ChannelPage channelPage; - /** \brief Scan duration per channel, duration = ( ( scanDuration ^ 2 ) - 1 ) * aBaseSuperFramePeriod symbols */ - FTDF_ScanDuration scanDuration; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; -} FTDF_ScanRequest; +typedef struct { + /** \brief Message id = FTDF_SCAN_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Scan Type */ + ftdf_scan_type_t scan_type; + /** \brief Bitmap of the channels to be scanned (only channel 11 - 27 are supported) */ + ftdf_bitmap32_t scan_channels; + /** \brief Channel page of the channels to be scanned (only page 0 is supported) */ + ftdf_channel_page_t channel_page; + /** \brief Scan duration per channel, duration = ((scan_duration ^ 2) - 1) * aBaseSuperFramePeriod symbols */ + ftdf_scan_duration_t scan_duration; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; +} ftdf_scan_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_SCAN_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the scan request */ - FTDF_Status status; - /** \brief Scan Type */ - FTDF_ScanType scanType; - /** \brief Channel page of the scanned channels */ - FTDF_ChannelPage channelPage; - /** \brief Bitmap of the channels not scanned but were requested to be scanned */ - FTDF_Bitmap32 unscannedChannels; - /** \brief Number of entries in energyDetectList or PANDescriptorList */ - FTDF_Size resultListSize; - /** \brief Pointer to the first energy detect result */ - FTDF_Energy* energyDetectList; - /** \brief Pointer to the first PAN descriptor */ - FTDF_PANDescriptor* PANDescriptorList; - /** \brief */ - FTDF_CoordRealignDescriptor* coordRealignDescriptor; -} FTDF_ScanConfirm; +typedef struct { + /** \brief Message id = FTDF_SCAN_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the scan request */ + ftdf_status_t status; + /** \brief Scan Type */ + ftdf_scan_type_t scan_type; + /** \brief Channel page of the scanned channels */ + ftdf_channel_page_t channel_page; + /** \brief Bitmap of the channels not scanned but were requested to be scanned */ + ftdf_bitmap32_t unscanned_channels; + /** \brief Number of entries in energy_detect_list or pan_descriptor_list */ + ftdf_size_t result_list_size; + /** \brief Pointer to the first energy detect result */ + ftdf_energy_t *energy_detect_list; + /** \brief Pointer to the first PAN descriptor */ + ftdf_pan_descriptor_t *pan_descriptor_list; + /** \brief */ + ftdf_coord_realign_descriptor_t *coord_realign_descriptor; +} ftdf_scan_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_START_REQUEST */ - FTDF_MsgId msgId; - /** \brief PAN ID that will be used by the coordinator */ - FTDF_PANId PANId; - /** \brief Channel number that will be used by the coordinator */ - FTDF_ChannelNumber channelNumber; - /** \brief Channel page that will be used by the coordinator */ - FTDF_ChannelPage channelPage; - /** \brief NOT USED */ - FTDF_Time startTime; - /** \brief Beacon order, only beacon order 15 (beaconless) is supported */ - FTDF_Order beaconOrder; - /** \brief NOT USED */ - FTDF_Order superframeOrder; - /** \brief Indication whether the device must be a coordinator or a PAN coordinator */ - FTDF_Boolean PANCoordinator; - /** \brief NOT USED */ - FTDF_Boolean batteryLifeExtension; - /** \brief NOT USED */ - FTDF_Boolean coordRealignment; - /** \brief NOT USED */ - FTDF_SecurityLevel coordRealignSecurityLevel; - /** \brief NOT USED */ - FTDF_KeyIdMode coordRealignKeyIdMode; - /** \brief NOT USED */ - FTDF_Octet coordRealignKeySource[ 8 ]; - /** \brief NOT USED */ - FTDF_KeyIndex coordRealignKeyIndex; - /** \brief NOT USED */ - FTDF_SecurityLevel beaconSecurityLevel; - /** \brief NOT USED */ - FTDF_KeyIdMode beaconKeyIdMode; - /** \brief NOT USED */ - FTDF_Octet beaconKeySource[ 8 ]; - /** \brief NOT USED */ - FTDF_KeyIndex beaconKeyIndex; -} FTDF_StartRequest; +typedef struct { + /** \brief Message id = FTDF_START_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief PAN id that will be used by the coordinator */ + ftdf_pan_id_t pan_id; + /** \brief Channel number that will be used by the coordinator */ + ftdf_channel_number_t channel_number; + /** \brief Channel page that will be used by the coordinator */ + ftdf_channel_page_t channel_page; + /** \brief NOT USED */ + ftdf_time_t start_time; + /** \brief Beacon order, only beacon order 15 (beaconless) is supported */ + ftdf_order_t beacon_order; + /** \brief NOT USED */ + ftdf_order_t superframe_order; + /** \brief Indication whether the device must be a coordinator or a PAN coordinator */ + ftdf_boolean_t pan_coordinator; + /** \brief NOT USED */ + ftdf_boolean_t battery_life_extension; + /** \brief NOT USED */ + ftdf_boolean_t coord_realignment; + /** \brief NOT USED */ + ftdf_security_level_t coord_realign_security_level; + /** \brief NOT USED */ + ftdf_key_id_mode_t coord_realign_key_id_mode; + /** \brief NOT USED */ + ftdf_octet_t coord_realign_key_source[8]; + /** \brief NOT USED */ + ftdf_key_index_t coord_realign_key_index; + /** \brief NOT USED */ + ftdf_security_level_t beacon_security_level; + /** \brief NOT USED */ + ftdf_key_id_mode_t beacon_key_id_mode; + /** \brief NOT USED */ + ftdf_octet_t beacon_key_source[8]; + /** \brief NOT USED */ + ftdf_key_index_t beacon_key_index; +} ftdf_start_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_START_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the start request */ - FTDF_Status status; -} FTDF_StartConfirm; +typedef struct { + /** \brief Message id = FTDF_START_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the start request */ + ftdf_status_t status; +} ftdf_start_confirm_t; -typedef struct -{ - FTDF_MsgId msgId; - FTDF_ChannelNumber channnelNumber; - FTDF_ChannelPage channelPage; - FTDF_Boolean trackbeacon; -} FTDF_SyncRequest; +typedef struct { + ftdf_msg_id_t msg_id; + ftdf_channel_number_t channnel_number; + ftdf_channel_page_t channel_page; + ftdf_boolean_t trackbeacon; +} ftdf_sync_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_SYNC_LOSS_INDICATION */ - FTDF_MsgId msgId; - /** \brief Loss Reason */ - FTDF_LossReason lossReason; - /** \brief PAN ID */ - FTDF_PANId PANId; - /** \brief Channel number */ - FTDF_ChannelNumber channelNumber; - /** \brief Channel page */ - FTDF_ChannelPage channelPage; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; -} FTDF_SyncLossIndication; +typedef struct { + /** \brief Message id = FTDF_SYNC_LOSS_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief Loss Reason */ + ftdf_loss_reason_t loss_reason; + /** \brief PAN id */ + ftdf_pan_id_t pan_id; + /** \brief Channel number */ + ftdf_channel_number_t channel_number; + /** \brief Channel page */ + ftdf_channel_page_t channel_page; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; +} ftdf_sync_loss_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_POLL_REQUEST */ - FTDF_MsgId msgId; - /** \brief Coordinator address mode */ - FTDF_AddressMode coordAddrMode; - /** \brief coordinator PAN ID */ - FTDF_PANId coordPANId; - /** \brief Coordinator address */ - FTDF_Address coordAddr; - /** \brief Security level */ - FTDF_SecurityLevel securityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode keyIdMode; - /** \brief Security key source */ - FTDF_Octet keySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex keyIndex; -} FTDF_PollRequest; +typedef struct { + /** \brief Message id = FTDF_POLL_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Coordinator address mode */ + ftdf_address_mode_t coord_addr_mode; + /** \brief coordinator PAN id */ + ftdf_pan_id_t coord_pan_id; + /** \brief Coordinator address */ + ftdf_address_t coord_addr; + /** \brief Security level */ + ftdf_security_level_t security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t key_id_mode; + /** \brief Security key source */ + ftdf_octet_t key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t key_index; +} ftdf_poll_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_POLL_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the poll request */ - FTDF_Status status; -} FTDF_PollConfirm; +typedef struct { + /** \brief Message id = FTDF_POLL_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the poll request */ + ftdf_status_t status; +} ftdf_poll_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_SET_SLOTFRAME_REQUEST */ - FTDF_MsgId msgId; - /** \brief Slotframe handle */ - FTDF_Handle handle; - /** \brief Set operation */ - FTDF_Operation operation; - /** \brief Number of timeslots in this slotframe */ - FTDF_SlotframeSize size; -} FTDF_SetSlotframeRequest; +typedef struct { + /** \brief Message id = FTDF_SET_SLOTFRAME_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Slotframe handle */ + ftdf_handle_t handle; + /** \brief Set operation */ + ftdf_operation_t operation; + /** \brief Number of timeslots in this slotframe */ + ftdf_slotframe_size_t size; +} ftdf_set_slotframe_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_SET_SLOTFRAME_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Slotframe handle */ - FTDF_Handle handle; - /** \brief Status of the set sloytframe request */ - FTDF_Status status; -} FTDF_SetSlotframeConfirm; +typedef struct { + /** \brief Message id = FTDF_SET_SLOTFRAME_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Slotframe handle */ + ftdf_handle_t handle; + /** \brief Status of the set sloytframe request */ + ftdf_status_t status; +} ftdf_set_slotframe_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_SET_LINK_REQUEST */ - FTDF_MsgId msgId; - /** \brief Set operation */ - FTDF_Operation operation; - /** \brief Handle of this link, used for delete and modify operations */ - FTDF_Handle linkHandle; - /** \brief Handle of the slotframe of this link */ - FTDF_Handle slotframeHandle; - /** \brief Timeslot in the slotframe */ - FTDF_Timeslot timeslot; - /** \brief Channel offset */ - FTDF_ChannelOffset channelOffset; - /** - * \brief Bit mapped link options, the following options are supported:
- * FTDF_LINK_OPTION_TRANSMIT: Lik can be used for transmitting
- * FTDF_LINK_OPTION_RECEIVE: Link can be used for receiving
- * FTDF_LINK_OPTION_SHARED: Shared link, multiple device can transmit in this link
- * FTDF_LINK_OPTION_TIME_KEEPING: Link will be used to synchronise timeslots
- * Multiple options can be defined by or-ing them. - */ - FTDF_Bitmap8 linkOptions; - /** \brief Link type */ - FTDF_LinkType linkType; - /** \brief Short address of the peer node, only valid if is a transmit link */ - FTDF_ShortAddress nodeAddress; -} FTDF_SetLinkRequest; +typedef struct { + /** \brief Message id = FTDF_SET_LINK_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Set operation */ + ftdf_operation_t operation; + /** \brief Handle of this link, used for delete and modify operations */ + ftdf_handle_t link_handle; + /** \brief Handle of the slotframe of this link */ + ftdf_handle_t slotframe_handle; + /** \brief Timeslot in the slotframe */ + ftdf_timeslot_t timeslot; + /** \brief Channel offset */ + ftdf_channel_offset_t channel_offset; + /** + * \brief Bit mapped link options, the following options are supported:
+ * FTDF_LINK_OPTION_TRANSMIT: Lik can be used for transmitting
+ * FTDF_LINK_OPTION_RECEIVE: Link can be used for receiving
+ * FTDF_LINK_OPTION_SHARED: Shared link, multiple device can transmit in this link
+ * FTDF_LINK_OPTION_TIME_KEEPING: Link will be used to synchronise timeslots
+ * Multiple options can be defined by or-ing them. + */ + ftdf_bitmap8_t link_options; + /** \brief Link type */ + ftdf_link_type_t link_type; + /** \brief Short address of the peer node, only valid if is a transmit link */ + ftdf_short_address_t node_address; +} ftdf_set_link_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_SET_LINK_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the set link request */ - FTDF_Status status; - /** \brief Link handle */ - FTDF_Handle linkHandle; - /** \brief Slotframe handle */ - FTDF_Handle slotframeHandle; -} FTDF_SetLinkConfirm; +typedef struct { + /** \brief Message id = FTDF_SET_LINK_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the set link request */ + ftdf_status_t status; + /** \brief Link handle */ + ftdf_handle_t link_handle; + /** \brief Slotframe handle */ + ftdf_handle_t slotframe_handle; +} ftdf_set_link_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_TSCH_MODE_REQUEST */ - FTDF_MsgId msgId; - /** \brief The new TSCH mode */ - FTDF_TSCHMode tschMode; - /** - * \brief The timestamp in symbols of the start of the timeslot with ASN equal to the PIB attribute - * FTDF_PIB_ASN
- * The timestamp should be calculated from the timestamp of the BEACON_NOTIFY_INDICATION message
- * Before sending the FTDF_TSCH_MODE_REQUEST message the application should set FTDF_PIB_ASN with - * the ASN of the TSCH synchronization IE of the IEList of the BEACON_NOTIFY_INDICATION message - */ - FTDF_Time timeslotStartTime; -} FTDF_TschModeRequest; +typedef struct { + /** \brief Message id = FTDF_TSCH_MODE_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief The new TSCH mode */ + ftdf_tsch_mode_t tschMode; + /** + * \brief The timestamp in symbols of the start of the timeslot with ASN equal to the PIB attribute + * FTDF_PIB_ASN
+ * The timestamp should be calculated from the timestamp of the BEACON_NOTIFY_INDICATION message
+ * Before sending the FTDF_TSCH_MODE_REQUEST message the application should set FTDF_PIB_ASN with + * the ASN of the TSCH synchronization IE of the ie_list of the BEACON_NOTIFY_INDICATION message + */ + ftdf_time_t timeslotStartTime; +} ftdf_tsch_mode_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_TSCH_MODE_CONFIRM */ - FTDF_MsgId msgId; - /** \brief The new TSCH mode */ - FTDF_TSCHMode tschMode; - /** \brief Status of the TSCH mode request */ - FTDF_Status status; -} FTDF_TschModeConfirm; +typedef struct { + /** \brief Message id = FTDF_TSCH_MODE_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief The new TSCH mode */ + ftdf_tsch_mode_t tschMode; + /** \brief Status of the TSCH mode request */ + ftdf_status_t status; +} ftdf_tsch_mode_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_KEEP_ALIVE_REQUEST */ - FTDF_MsgId msgId; - /** \brief Short address to which keep alive message should be send */ - FTDF_ShortAddress dstAddress; - /** \brief */ - FTDF_KeepAlivePeriod keepAlivePeriod; -} FTDF_KeepAliveRequest; +typedef struct { + /** \brief Message id = FTDF_KEEP_ALIVE_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Short address to which keep alive message should be send */ + ftdf_short_address_t dst_address; + /** \brief */ + ftdf_keep_alive_period_t keep_alive_period; +} ftdf_keep_alive_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_KEEP_ALIVE_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the keep alive request */ - FTDF_Status status; -} FTDF_KeepAliveConfirm; +typedef struct { + /** \brief Message id = FTDF_KEEP_ALIVE_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the keep alive request */ + ftdf_status_t status; +} ftdf_keep_alive_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_BEACON_REQUEST */ - FTDF_MsgId msgId; - /** \brief Beacon type */ - FTDF_BeaconType beaconType; - /** \brief Channel number at which the beacon must be sent, ignored in TSCH mode */ - FTDF_ChannelNumber channel; - /** \brief Channel page, ignored in TSCH mode */ - FTDF_ChannelPage channelPage; - /** \brief NOT USED */ - FTDF_Order superframeOrder; - /** \brief Security level */ - FTDF_SecurityLevel beaconSecurityLevel; - /** \brief Security key ID mode */ - FTDF_KeyIdMode beaconKeyIdMode; - /** \brief Security key source */ - FTDF_Octet beaconKeySource[ 8 ]; - /** \brief Security key index */ - FTDF_KeyIndex beaconKeyIndex; - /** \brief Beacon destination address mode */ - FTDF_AddressMode dstAddrMode; - /** \brief Beacon destination address */ - FTDF_Address dstAddr; - /** \brief Indication whether the BSN (or EBSN) in the beacon frame must suppressed */ - FTDF_Boolean BSNSuppression; - /** \brief DO NOT USE */ - uint8_t __private3; -} FTDF_BeaconRequest; +typedef struct { + /** \brief Message id = FTDF_BEACON_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Beacon type */ + ftdf_beacon_type_t beacon_type; + /** \brief Channel number at which the beacon must be sent, ignored in TSCH mode */ + ftdf_channel_number_t channel; + /** \brief Channel page, ignored in TSCH mode */ + ftdf_channel_page_t channel_page; + /** \brief NOT USED */ + ftdf_order_t superframe_order; + /** \brief Security level */ + ftdf_security_level_t beacon_security_level; + /** \brief Security key id mode */ + ftdf_key_id_mode_t beacon_key_id_mode; + /** \brief Security key source */ + ftdf_octet_t beacon_key_source[8]; + /** \brief Security key index */ + ftdf_key_index_t beacon_key_index; + /** \brief Beacon destination address mode */ + ftdf_address_mode_t dst_addr_mode; + /** \brief Beacon destination address */ + ftdf_address_t dst_addr; + /** \brief Indication whether the bsn (or eb_sn) in the beacon frame must suppressed */ + ftdf_boolean_t bsn_suppression; + /** \brief DO NOT USE */ + uint8_t __private3; +} ftdf_beacon_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_BEACON_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Status of the beacon request */ - FTDF_Status status; -} FTDF_BeaconConfirm; +typedef struct { + /** \brief Message id = FTDF_BEACON_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Status of the beacon request */ + ftdf_status_t status; +} ftdf_beacon_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_BEACON_REQUEST_INDICATION */ - FTDF_MsgId msgId; - /** \brief Beacon type */ - FTDF_BeaconType beaconType; - /** \brief Source address mode */ - FTDF_AddressMode srcAddrMode; - /** \brief Source address */ - FTDF_Address srcAddr; - /** \brief Source PAN ID */ - FTDF_PANId dstPANId; - /** - * \brief Payload IE list
- * The whole Payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocate in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER - * with the IEList pointer as parameter. - */ - FTDF_IEList* IEList; -} FTDF_BeaconRequestIndication; +typedef struct { + /** \brief Message id = FTDF_BEACON_REQUEST_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief Beacon type */ + ftdf_beacon_type_t beacon_type; + /** \brief Source address mode */ + ftdf_address_mode_t src_addr_mode; + /** \brief Source address */ + ftdf_address_t src_addr; + /** \brief Source PAN id */ + ftdf_pan_id_t dst_pan_id; + /** + * \brief Payload IE list
+ * The whole Payload IE list (including IE descriptors, Sub IE descriptors and content) + * is allocate in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER + * with the ie_list pointer as parameter. + */ + ftdf_ie_list_t *ie_list; +} ftdf_beacon_request_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_TRANSPARENT_ENABLE_REQUEST */ - FTDF_MsgId msgId; - /** \brief Enable or disable of transparent mode */ - FTDF_Boolean enable; - /** \brief Bitmapped transparent options, see FTDF_enableTransparentMode */ - FTDF_Bitmap32 options; -} FTDF_TransparentEnableRequest; +typedef struct { + /** \brief Message id = FTDF_TRANSPARENT_ENABLE_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Enable or disable of transparent mode */ + ftdf_boolean_t enable; + /** \brief Bitmapped transparent options, see ftdf_enable_transparent_mode */ + ftdf_bitmap32_t options; +} ftdf_transparent_enable_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_TRANSPARENT_REQUEST */ - FTDF_MsgId msgId; - /** \brief Frame length */ - FTDF_DataLength frameLength; - /** \brief Pointer to frame, must be allocated with FTDF_GET_DATA_BUFFER */ - FTDF_Octet* frame; - /** \brief Channel number */ - FTDF_ChannelNumber channel; - /** \brief Packet Traffic Information (PTI) used for transmitting the frame. */ - FTDF_PTI pti; - /** \brief CSMA suppression */ - FTDF_Boolean cmsaSuppress; - /** \brief Application provided handle, will be returned in the transparent confirm call */ - void* handle; -} FTDF_TransparentRequest; +typedef struct { + /** \brief Message id = FTDF_TRANSPARENT_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Frame length */ + ftdf_data_length_t frame_length; + /** \brief Pointer to frame, must be allocated with FTDF_GET_DATA_BUFFER */ + ftdf_octet_t *frame; + /** \brief Channel number */ + ftdf_channel_number_t channel; + /** \brief Packet Traffic Information (PTI) used for transmitting the frame. */ + ftdf_pti_t pti; + /** \brief CSMA suppression */ + ftdf_boolean_t cmsa_suppress; + /** \brief Application provided handle, will be returned in the transparent confirm call */ + void *handle; +} ftdf_transparent_request_t; -typedef struct -{ - /** \brief Message ID = FTDF_TRANSPARENT_CONFIRM */ - FTDF_MsgId msgId; - /** \brief Application provided handle of the corresponding FTDF_sendFrameTransparent call */ - void* handle; - /** \brief Bit mapped status */ - FTDF_Bitmap32 status; -} FTDF_TransparentConfirm; +typedef struct { + /** \brief Message id = FTDF_TRANSPARENT_CONFIRM */ + ftdf_msg_id_t msg_id; + /** \brief Application provided handle of the corresponding FTDF_SEND_FRAME_TRANSPARENT call */ + void *handle; + /** \brief Bit mapped status */ + ftdf_bitmap32_t status; +} ftdf_transparent_confirm_t; -typedef struct -{ - /** \brief Message ID = FTDF_TRANSPARENT_INDICATION */ - FTDF_MsgId msgId; - /** \brief Frame length */ - FTDF_DataLength frameLength; - /** \brief Pointer to frame, must be freed by the application using FTDF_REL_DATA_BUFFER */ - FTDF_Octet* frame; - /** \brief Bit mapped receive status */ - FTDF_Bitmap32 status; -} FTDF_TransparentIndication; +typedef struct { + /** \brief Message id = FTDF_TRANSPARENT_INDICATION */ + ftdf_msg_id_t msg_id; + /** \brief Frame length */ + ftdf_data_length_t frame_length; + /** \brief Pointer to frame, must be freed by the application using FTDF_REL_DATA_BUFFER */ + ftdf_octet_t *frame; + /** \brief Bit mapped receive status */ + ftdf_bitmap32_t status; +} ftdf_transparent_indication_t; -typedef struct -{ - /** \brief Message ID = FTDF_SLEEP_REQUEST */ - FTDF_MsgId msgId; - /** \brief Sleep time */ - FTDF_USec sleepTime; -} FTDF_SleepRequest; +typedef struct { + /** \brief Message id = FTDF_SLEEP_REQUEST */ + ftdf_msg_id_t msg_id; + /** \brief Sleep time */ + ftdf_usec_t sleep_time; +} ftdf_sleep_request_t; #if FTDF_DBG_BUS_ENABLE -typedef struct -{ - /** \brief Message ID = FTDF_DBG_MODE_SET_REQUEST */ - FTDF_MsgId msgId; +typedef struct { + /** \brief Message id = FTDF_DBG_MODE_SET_REQUEST */ + ftdf_msg_id_t msg_id; /** \brief Debug bus mode */ - FTDF_DbgMode dbgMode; -} FTDF_DbgModeSetRequest; + ftdf_dbg_mode_t dbg_mode; +} ftdf_dbg_mode_set_request_t; #endif /* FTDF_DBG_BUS_ENABLE */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A typedef struct { /** \brief Message ID = FTDF_FPPR_MODE_SET_REQUEST */ - FTDF_MsgId msgId; + ftdf_msg_id_t msg_id; /** \brief fp bit value to set when src address matches*/ - FTDF_Bitmap8 matchFp; + ftdf_bitmap8_t match_fp; /** \brief When set, fp_force_value will be applied to fp bit for all src addresses*/ - FTDF_Bitmap8 fpOverride; + ftdf_bitmap8_t fp_override; /** \brief The value will be set to fp bit for all src addresses when fp_override is set*/ - FTDF_Bitmap8 fpForce; -} FTDF_FpprModeSetRequest; -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + ftdf_bitmap8_t fp_force; +} ftdf_fppr_mode_set_request_t; + /** - * \brief FTDF_getReleaseInfo - gets the LMAC (FPGA) and UMAC (FTDF SW driver) release info - * \param[out] lmacRelName: LMAC release name - * \param[out] lmacBuildTime: LMAC build time - * \param[out] umacRelName: UMAC release name - * \param[out] umacBuildTime: UMAC build time + * \brief ftdf_get_release_info - gets the LMAC (FPGA) and UMAC (FTDF SW driver) release info + * \param[out] lmac_rel_name: LMAC release name + * \param[out] lmac_build_time: LMAC build time + * \param[out] umac_rel_name: UMAC release name + * \param[out] umac_build_time: UMAC build time * \remark Sets the application character strings pointers to character strings containing the release - * info. The character string space is statically allocated by FTDF and does not need + * info. The character string space is statically allocated by FTDF and does not need * to be released by the application. */ -void FTDF_getReleaseInfo( char** lmacRelName, char** lmacBuildTime, char** umacRelName, - char** umacBuildTime ); +void ftdf_get_release_info(char **lmac_rel_name, char **lmac_build_time, char **umac_rel_name, + char **umac_build_time); /** - * \brief FTDF_confirmLmacInterrupt - Confirmation that the LMAC interrupt has been received + * \brief ftdf_confirm_lmac_interrupt - Confirmation that the LMAC interrupt has been received * by the application * \remark This function disables the LMAC interrupt. The application must wait for any other - * FTDF API function to be completed and call the function FTDF_eventHandler. This function - * will enable the LMAC interrupt again the function FTDF_eventHandler. + * FTDF API function to be completed and call the function ftdf_event_handler. This function + * will enable the LMAC interrupt again the function ftdf_event_handler. */ -void FTDF_confirmLmacInterrupt( void ); +void ftdf_confirm_lmac_interrupt(void); /** - * \brief FTDF_eventHandler - Handles an event signalled by the LMAC interrupt + * \brief ftdf_event_handler - Handles an event signalled by the LMAC interrupt * \remark This function handles the event signalled by the LMAC interrupt and enables the LMAC * interrupt when finished. - * \warning FTDF is strictly NON reentrant, so FTDF_eventHandler is NOT allowed to be called when another FTDF + * \warning FTDF is strictly NON reentrant, so ftdf_event_handler is NOT allowed to be called when another FTDF * is being executed */ -void FTDF_eventHandler( void ); +void ftdf_event_handler(void); /** - * \brief FTDF_sndMsg - Sends a request (response) message to FTDF driver - * \param[in] msgBuf: The message to be send. To application must set the msgId field and the request + * \brief ftdf_snd_msg - Sends a request (response) message to FTDF driver + * \param[in] msg_buf: The message to be send. To application must set the msg_id field and the request * specific parameters by casting it to the appropriate request message structure. - * \remark The message must be allocated by the application using the function FTDF_GET_MSG_BUFFER - * and will be released by FTDF using FTDF_REL_MSG_BUFFER. When finished FTDF releases the message - * buffer and sends a confirm (indication) to the application using the function FTDF_RCV_MSG. - * \remark As follows a table of message IDs accepted by FTDF_sndMsg, the message structure corresponding - * to this message ID and the confirm send back to the application when the request has been + * \remark The message must be allocated by the application using the function ftdf_get_msg_buffer + * and will be released by FTDF using ftdf_rel_msg_buffer. When finished FTDF releases the message + * buffer and sends a confirm (indication) to the application using the function ftdf_rcv_msg. + * \remark As follows a table of message IDs accepted by ftdf_snd_msg, the message structure corresponding + * to this message id and the confirm send back to the application when the request has been * completed by FTDF: * \remark
- * \remark Request message ID, Request structure, Request confirm + * \remark Request message id, Request structure, Request confirm * \remark --------------------------------------------------------------------------------- - * \remark FTDF_DATA_REQUEST, FTDF_DataRequest, FTDF_DATA_CONFIRM - * \remark FTDF_PURGE_REQUEST, FTDF_PurgeRequest, FTDF_DATA_CONFIRM - * \remark FTDF_ASSOCIATE_REQUEST, FTDF_AssociateRequest, FTDF_ASSOCIATE_CONFIRM - * \remark FTDF_ASSOCIATE_RESPONSE, FTDF_AssociateResponse, FTDF_COMM_STATUS_INDICATION - * \remark FTDF_DISASSOCIATE_REQUEST, FTDF_DisassociateRequest, FTDF_DISASSOCIATE_CONFIRM - * \remark FTDF_GET_REQUEST, FTDF_GetRequest, FTDF_GET_CONFIRM - * \remark FTDF_SET_REQUEST, FTDF_SetRequest, FTDF_SET_CONFIRM - * \remark FTDF_ORPHAN_RESPONSE, FTDF_OrphanResponse, FTDF_COMM_STATUS_INDICATION - * \remark FTDF_RESET_REQUEST, FTDF_ResetRequest, FTDF_RESET_CONFIRM - * \remark FTDF_RX_ENABLE_REQUEST, FTDF_ScanRequest, FTDF_RX_ENABLE_CONFIRM - * \remark FTDF_SCAN_REQUEST, FTDF_ScanRequest, FTDF_SCAN_CONFIRM - * \remark FTDF_START_REQUEST, FTDF_StartRequest, FTDF_START_CONFIRM - * \remark FTDF_POLL_REQUEST, FTDF_PollRequest, FTDF_POLL_CONFIRM - * \remark FTDF_SET_SLOTFRAME_REQUEST, FTDF_SetSlotframeRequest, FTDF_SET_SLOTFRAME_CONFIRM - * \remark FTDF_SET_LINK_REQUEST, FTDF_SetLinkRequest, FTDF_SET_LINK_CONFIRM - * \remark FTDF_TSCH_MODE_REQUEST, FTDF_TschModeRequest, FTDF_TSCH_MODE_CONFIRM - * \remark FTDF_KEEP_ALIVE_REQUEST, FTDF_KeepAliveRequest, FTDF_KEEP_ALIVE_CONFIRM - * \remark FTDF_BEACON_REQUEST, FTDF_BeaconRequest, FTDF_BEACON_CONFIRM - * \warning FTDF is strictly NON reentrant, so it is NOT allowed to call any other FTDF function before this API has been completed. This including the FTDF_eventHandler function. + * \remark FTDF_DATA_REQUEST, ftdf_data_request_t, FTDF_DATA_CONFIRM + * \remark FTDF_PURGE_REQUEST, ftdf_purge_request_t, FTDF_DATA_CONFIRM + * \remark FTDF_ASSOCIATE_REQUEST, ftdf_associate_request_t, FTDF_ASSOCIATE_CONFIRM + * \remark FTDF_ASSOCIATE_RESPONSE, ftdf_associate_response_t, FTDF_COMM_STATUS_INDICATION + * \remark FTDF_DISASSOCIATE_REQUEST, ftdf_disassociate_request_t, FTDF_DISASSOCIATE_CONFIRM + * \remark FTDF_GET_REQUEST, ftdf_get_request_t, FTDF_GET_CONFIRM + * \remark FTDF_SET_REQUEST, ftdf_set_request_t, FTDF_SET_CONFIRM + * \remark FTDF_ORPHAN_RESPONSE, ftdf_orphan_response_t, FTDF_COMM_STATUS_INDICATION + * \remark FTDF_RESET_REQUEST, ftdf_reset_request_t, FTDF_RESET_CONFIRM + * \remark FTDF_RX_ENABLE_REQUEST, ftdf_scan_request_t, FTDF_RX_ENABLE_CONFIRM + * \remark FTDF_SCAN_REQUEST, ftdf_scan_request_t, FTDF_SCAN_CONFIRM + * \remark FTDF_START_REQUEST, ftdf_start_request_t, FTDF_START_CONFIRM + * \remark FTDF_POLL_REQUEST, ftdf_poll_request_t, FTDF_POLL_CONFIRM + * \remark FTDF_SET_SLOTFRAME_REQUEST, ftdf_set_slotframe_request_t, FTDF_SET_SLOTFRAME_CONFIRM + * \remark FTDF_SET_LINK_REQUEST, ftdf_set_link_request_t, FTDF_SET_LINK_CONFIRM + * \remark FTDF_TSCH_MODE_REQUEST, ftdf_tsch_mode_request_t, FTDF_TSCH_MODE_CONFIRM + * \remark FTDF_KEEP_ALIVE_REQUEST, ftdf_keep_alive_request_t, FTDF_KEEP_ALIVE_CONFIRM + * \remark FTDF_BEACON_REQUEST, ftdf_beacon_request_t, FTDF_BEACON_CONFIRM + * \warning FTDF is strictly NON reentrant, so it is NOT allowed to call any other FTDF function before this API has been completed. This including the ftdf_event_handler function. */ -void FTDF_sndMsg( FTDF_MsgBuffer* msgBuf ); +void ftdf_snd_msg(ftdf_msg_buffer_t *msg_buf); /** * \brief FTDF_RCV_MSG - Receives a confir or indication message from the FTDF driver - * \param[in] msgBuf: The received message. The msgId field indicates the received message - * \remark This function must be implemented by the application and is called by FTDF to pass + * \param[in] msg_buf: The received message. The msg_id field indicates the received message + * \remark This function must be implemented by the application and is called by FTDF to pass * a confirm or indication message to the application. It must be configured in the * configuration file ftdf_config.h. * \remark The message buffer is allocated by FTDF using FTDF_GET_MSG_BUFFER and must be released - * by the application using FTDF_REL_MSG_BUFFER + * by the application using ftdf_rel_msg_buffer * \remark As follows a table of the confirm and indications messages and their message structures. * \remark
- * \remark Confirm/indication message ID, Confirm/indication structure + * \remark Confirm/indication message id, Confirm/indication structure * \remark --------------------------------------------------------------------------------- - * \remark FTDF_DATA_INDICATION, FTDF_DataIndication - * \remark FTDF_DATA_CONFIRM, FTDF_DataConfirm - * \remark FTDF_PURGE_CONFIRM, FTDF_PurgeConfirm - * \remark FTDF_ASSOCIATE_INDICATION, FTDF_AssociateIndication - * \remark FTDF_ASSOCIATE_CONFIRM, FTDF_AssociateConfirm - * \remark FTDF_DISASSOCIATE_INDICATION, FTDF_DisassociateIndication - * \remark FTDF_DISASSOCIATE_CONFIRM,FTDF_DisassociateConfirm - * \remark FTDF_BEACON_NOTIFY_INDICATION, FTDF_BeaconNotifyIndication - * \remark FTDF_COMM_STATUS_INDICATION, FTDF_CommStatusIndication - * \remark FTDF_GET_CONFIRM, FTDF_GetConfirm - * \remark FTDF_SET_CONFIRM, FTDF_SetConfirm - * \remark FTDF_ORPHAN_INDICATION, FTDF_OrphanIndication - * \remark FTDF_RESET_CONFIRM, FTDF_ResetConfirm - * \remark FTDF_RX_ENABLE_CONFIRM, FTDF_RxEnableConfirm - * \remark FTDF_SCAN_CONFIRM, FTDF_ScanConfirm - * \remark FTDF_START_CONFIRM, FTDF_StartConfirm - * \remark FTDF_SYNC_LOSS_INDICATION, FTDF_SyncLossIndication - * \remark FTDF_POLL_CONFIRM, FTDF_PollConfirm - * \remark FTDF_SET_SLOTFRAME_CONFIRM, FTDF_SetSlotframeConfirm - * \remark FTDF_SET_LINK_CONFIRM, FTDF_SetLinkConfirm - * \remark FTDF_TSCH_MODE_CONFIRM, FTDF_TschModeConfirm - * \remark FTDF_KEEP_ALIVE_CONFIRM, FTDF_KeepAliveConfirm - * \remark FTDF_BEACON_CONFIRM, FTDF_BeaconConfirm - * \remark FTDF_BEACON_REQUEST_INDICATION, FTDF_BeaconRequestIndication - * \warning FTDF is strictly NON reentrant. Because FTDF_RCV_MSG can be called by FTDF_sndMsg or FTDF_eventHandler - * it is not allowed to call other FTDF functions within FTDF_RCV_MSG + * \remark FTDF_DATA_INDICATION, ftdf_data_indication_t + * \remark FTDF_DATA_CONFIRM, ftdf_data_confirm_t + * \remark FTDF_PURGE_CONFIRM, ftdf_purge_confirm_t + * \remark FTDF_ASSOCIATE_INDICATION, ftdf_associate_indication_t + * \remark FTDF_ASSOCIATE_CONFIRM, ftdf_associate_confirm_t + * \remark FTDF_DISASSOCIATE_INDICATION, ftdf_disassociate_indication_t + * \remark FTDF_DISASSOCIATE_CONFIRM,ftdf_disassociate_confirm_t + * \remark FTDF_BEACON_NOTIFY_INDICATION, ftdf_beacon_notify_indication_t + * \remark FTDF_COMM_STATUS_INDICATION, ftdf_comm_status_indication_t + * \remark FTDF_GET_CONFIRM, ftdf_get_confirm_t + * \remark FTDF_SET_CONFIRM, ftdf_set_confirm_t + * \remark FTDF_ORPHAN_INDICATION, ftdf_orphan_indication_t + * \remark FTDF_RESET_CONFIRM, ftdf_reset_confirm_t + * \remark FTDF_RX_ENABLE_CONFIRM, ftdf_rx_enable_confirm_t + * \remark FTDF_SCAN_CONFIRM, ftdf_scan_confirm_t + * \remark FTDF_START_CONFIRM, ftdf_start_confirm_t + * \remark FTDF_SYNC_LOSS_INDICATION, ftdf_sync_loss_indication_t + * \remark FTDF_POLL_CONFIRM, ftdf_poll_confirm_t + * \remark FTDF_SET_SLOTFRAME_CONFIRM, ftdf_set_slotframe_confirm_t + * \remark FTDF_SET_LINK_CONFIRM, ftdf_set_link_confirm_t + * \remark FTDF_TSCH_MODE_CONFIRM, ftdf_tsch_mode_confirm_t + * \remark FTDF_KEEP_ALIVE_CONFIRM, ftdf_keep_alive_confirm_t + * \remark FTDF_BEACON_CONFIRM, ftdf_beacon_confirm_t + * \remark FTDF_BEACON_REQUEST_INDICATION, ftdf_beacon_request_indication_t + * \warning FTDF is strictly NON reentrant. Because ftdf_rcv_msg can be called by ftdf_snd_msg or ftdf_event_handler + * it is not allowed to call other FTDF functions within ftdf_rcv_msg */ -void FTDF_RCV_MSG( FTDF_MsgBuffer* msgBuf ); +void FTDF_RCV_MSG(ftdf_msg_buffer_t *msg_buf); /** * \brief FTDF_GET_MSG_BUFFER - Allocates a message buffer * \param[in] len: The length of the message buffer to be allocated * \remark This function must be implemented by the application it will called by both the * application and FTDF. It must be configured in the configuration file ftdf_config.h. - * \remark The allocated message buffer must be freed using FTDF_REL_MSG_BUFFER + * \remark The allocated message buffer must be freed using ftdf_rel_msg_buffer * \remark The message buffer must be located in retention RAM * \return pointer to the allocated message buffer. */ -FTDF_MsgBuffer* FTDF_GET_MSG_BUFFER( FTDF_Size len ); +ftdf_msg_buffer_t *FTDF_GET_MSG_BUFFER(ftdf_size_t len); /** * \brief FTDF_REL_MSG_BUFFER - Frees a message buffer - * \param[in] msgBuf: Pointer to the message buffer to be released + * \param[in] msg_buf: Pointer to the message buffer to be released * \remark This function must be implemented by the application it will called by both the * application and FTDF. It must be configured in the configuration file ftdf_config.h. - * \remark It will free message buffers allocated with FTDF_GET_MSG_BUFFER + * \remark It will free message buffers allocated with ftdf_get_msg_buffer */ -void FTDF_REL_MSG_BUFFER( FTDF_MsgBuffer* msgBuf ); +void FTDF_REL_MSG_BUFFER(ftdf_msg_buffer_t *msg_buf); /** * \brief FTDF_GET_DATA_BUFFER - Allocates a data buffer @@ -2894,35 +2878,35 @@ void FTDF_REL_MSG_BUFFER( FTDF_MsgBuffer* msgBuf ); * \remark The data buffer must located in retention RAM * \return pointer to the allocated data buffer. */ -FTDF_Octet* FTDF_GET_DATA_BUFFER( FTDF_DataLength len ); +ftdf_octet_t *FTDF_GET_DATA_BUFFER(ftdf_data_length_t len); /** * \brief FTDF_REL_DATA_BUFFER - Frees a data buffer - * \param[in] dataBuf: Pointer to the data buffer to be released + * \param[in] data_buf: Pointer to the data buffer to be released * \remark This function must be implemented by the application it will called by both the * application and FTDF. It must be configured in the configuration file ftdf_config.h. * \remark It will free data buffers allocated with FTDF_GET_DATA_BUFFER */ -void FTDF_REL_DATA_BUFFER( FTDF_Octet* dataBuf ); +void FTDF_REL_DATA_BUFFER(ftdf_octet_t *data_buf); /** * \brief FTDF_GET_EXT_ADDRESS - Gets the extended address * \remark This function must be implemented by the application it will called by FTDF. It must * be configured in the configuration file ftdf_config.h. * \remark After a reset it is used by FTDF to get the extended address of the device - * \return An extended address. + * \return An extended address. */ -FTDF_ExtAddress FTDF_GET_EXT_ADDRESS( void ); +ftdf_ext_address_t FTDF_GET_EXT_ADDRESS(void); /** - * \brief FTDF_enableTransparentMode - Enables or disables the transparent mode + * \brief ftdf_enable_transparent_mode - Enables or disables the transparent mode * \param[in] enable: If FTDF_TRUE transparent mode is enabled else it will be disabled * \param[in] options: A bitmap of transparent mode options. Not used if enable equals to FTDF_FALSE. * \remark If the transparent mode is enabled received frame are passed to the application using * FTDF_RCV_FRAME_TRANSPARENT. The whole MAC frame including frame headers, security headers * and FCS are passed to the application. Depending on the defined options some filtering * is done. - * \remark When the transparent mode is enabled frames must be send using the function FTDF_sendFrameTransparent + * \remark When the transparent mode is enabled frames must be send using the function FTDF_SEND_FRAME_TRANSPARENT * \remark When the transparent mode is enabled only the following request messages are supported: * \remark
* \remark FTDF_GET_REQUEST @@ -2951,73 +2935,73 @@ FTDF_ExtAddress FTDF_GET_EXT_ADDRESS( void ); * \remark FTDF_TRANSPARENT_PASS_CRC_ERROR: Frames with a CRC (FCS) error are passed to the application * \remark FTDF_TRANSPARENT_PASS_ALL_FRAME_VERSION: Frames with any frame version are passed to the * application - * \remark FTDF_TRANSPARENT_PASS_ALL_PAN_ID: Frames with any PAN ID (even when it does not match its own - * PAN ID) are passed to the application + * \remark FTDF_TRANSPARENT_PASS_ALL_PAN_ID: Frames with any PAN id (even when it does not match its own + * PAN id) are passed to the application * \remark FTDF_TRANSPARENT_PASS_ALL_PAN_ID: Frames with any address (even when it does not match its own * extended or short address) are passed to the application * \remark FTDF_TRANSPARENT_PASS_ALL_BEACON: Any beacon frame is passed to the application * \remark FTDF_TRANSPARENT_PASS_ALL_NO_DEST_ADDR: Frames with no destination address are always passed to * the application - * \remark FTDF_TRANSPARENT_ENABLE_FCS_GENERATION: FTDF adds an FCS to frames send with FTDF_sendFrameTransparent + * \remark FTDF_TRANSPARENT_ENABLE_FCS_GENERATION: FTDF adds an FCS to frames send with FTDF_SEND_FRAME_TRANSPARENT */ -void FTDF_enableTransparentMode( FTDF_Boolean enable, - FTDF_Bitmap32 options ); +void ftdf_enable_transparent_mode(ftdf_boolean_t enable, ftdf_bitmap32_t options); /** - * \brief FTDF_sendFrameTransparent - Sends a frame transparent - * \param[in] frameLength: Length of the MAC frame to be send + * \brief ftdf_send_frame_transparent - Sends a frame transparent + * \param[in] frame_length: Length of the MAC frame to be send * \param[in] frame: Data buffer with the frame to be sent. Must be allocate using FTDF_GET_DATA_BUFFER * \param[in] channel: The channel used to send the frame * \param[in] pti: Packet Traffic Information used for transmitting the packet - * \param[in] cmsaSuppress: If FTDF_TRUE no CSMA-CA is performed before sending the frame + * \param[in] cmsa_suppress: If FTDF_TRUE no CSMA-CA is performed before sending the frame * \param[in] handle: A user defined handle. - * \remark FTDF sends the frame tarnsparently. That is the application has to compose the MAC frame header, + * \remark FTDF sends the frame tarnsparently. That is the application has to compose the MAC frame header, * security header, etc and make sure that it complies with the IEEE802.15.4 standard. Before sending * it FTDF adds the preamble, frame start, phy header octets and optionally an FCS to the frame provide * by the application. * \remark When FTDF has send the frame or failed to send the frame it will call FTDF_SEND_FRAME_TRANSPARENT_CONFIRM * with the handle provided by the application and the send status. */ -void FTDF_sendFrameTransparent( FTDF_DataLength frameLength, - FTDF_Octet* frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean cmsaSuppress, - void* handle ); +void ftdf_send_frame_transparent(ftdf_data_length_t frame_length, + ftdf_octet_t *frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t cmsa_suppress, + void *handle); /** * \brief FTDF_SEND_FRAME_TRANSPARENT_CONFIRM - Confirms a transparent send - * \param[in] handle: The application provided handle of the corresponding FTDF_sendFrameTransparent call + * \param[in] handle: The application provided handle of the corresponding ftdf_send_frame_transparent call call * \param[in] status: Bit mapped status * \remark This function must be implemented by the application it will called by FTDF. It must * be configured in the configuration file ftdf_config.h. * \remark FTDF calls this function when a frame has send successfully or failed to send. The application can - * now free the data buffer of the corresponding FTDF_sendFrameTransparent using FTDF_REL_DATA_BUFFER + * now free the data buffer of the corresponding ftdf_send_frame_transparent call using ftdf_rel_data_buffer * \remark If the frame is send successfully status is equal to 0 * \remark If sending the frame failed one of more of the following status bits is set: * - FTDF_TRANSPARENT_CSMACA_FAILURE: Sending failed because CSMA-CA failed * - FTDF_TRANSPARENT_OVERFLOW: Sending failed because of internal resource overflow */ -void FTDF_SEND_FRAME_TRANSPARENT_CONFIRM( void* handle, - FTDF_Bitmap32 status ); +void FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(void *handle, ftdf_bitmap32_t status); /** - * \brief FTDF_sendFrameTransparentConfirm - Converts the FTDF_SEND_FRAME_TRANSPARENT_CONFIRM to a msg buffer - * and then calls FTDF_RCV_MSG. - * \param[in] handle: The application provided handle of the corresponding FTDF_sendFrameTransparent call + * \brief ftdf_send_frame_transparent_confirm - Converts the FTDF_SEND_FRAME_TRANSPARENT_CONFIRM to a msg buffer + * and then calls ftdf_rcv_msg. + * \param[in] handle: The application provided handle of the corresponding ftdf_send_frame_transparent call * \param[in] status: Bit mapped status - * \remark This function converts the input parameters to a FTDF_TransparentConfirm structure - * and then calls FTDF_RCV_MSG. + * \remark This function converts the input parameters to a ftdf_transparent_confirm_t structure + * and then calls ftdf_rcv_msg. * \remark FTDF_SEND_FRAME_TRANSPARENT_CONFIRM can be defined to be this function. */ -void FTDF_sendFrameTransparentConfirm( void* handle, - FTDF_Bitmap32 status ); +void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status); /** * \brief FTDF_RCV_FRAME_TRANSPARENT - Receive frame transparent - * \param[in] frameLength: Length of the received frame - * \param[in] frame: Pointer to received frame. + * \param[in] frame_length: Length of the received frame + * \param[in] frame: Pointer to received frame. * \param[in] status: Bitmapped receive status + * \param[in] link_quality: LQI/RSSI value for this packet. Depends on FTDF_PIB_LINK_QUALITY_MODE + * PIB parameter. + * * \remark This function must be implemented by the application it will called by FTDF. It must * be configured in the configuration file ftdf_config.h. * \remark FTDF calls this function when a frame is received when transparent mode is enabled @@ -3027,66 +3011,63 @@ void FTDF_sendFrameTransparentConfirm( void* handle, * - FTDF_TRANSPARENT_RCV_RES_FRAMETYPE: Received a reserved frame type * - FTDF_TRANSPARENT_RCV_RES_FRAME_VERSION: Received a reserved frame version * - FTDF_TRANSPARENT_RCV_UNEXP_DST_ADDR: Unexpected destination address - * - FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID: Unexpected destionation PAN ID + * - FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID: Unexpected destionation PAN id * - FTDF_TRANSPARENT_RCV_UNEXP_BEACON: Unexpected beacon frame * - FTDF_TRANSPARENT_RCV_UNEXP_NO_DEST_ADDR: Unexpected frame without destination adres. */ -void FTDF_RCV_FRAME_TRANSPARENT( FTDF_DataLength frameLength, - FTDF_Octet* frame, - FTDF_Bitmap32 status, - FTDF_LinkQuality lqi); +void FTDF_RCV_FRAME_TRANSPARENT(ftdf_data_length_t frame_length, ftdf_octet_t *frame, + ftdf_bitmap32_t status, ftdf_link_quality_t link_quality); /** - * \brief FTDF_rcvFrameTransparent - Converts the FTDF_RCV_FRAME_TRANSPARENT to a msg buffer - * and then calls FTDF_RCV_MSG. - * \param[in] frameLength: Length of the received frame - * \param[in] frame: Pointer to received frame. + * \brief ftdf_rcv_frame_transparent - Converts the FTDF_RCV_FRAME_TRANSPARENT to a msg buffer + * and then calls ftdf_rcv_msg. + * \param[in] frame_length: Length of the received frame + * \param[in] frame: Pointer to received frame. * \param[in] status: Bitmapped receive status - * \remark This function convers the input parameters to a FTDF_TransparentIndication structure - * and then calls FTDF_RCV_MSG. + * \param[in] link_quality: Received packet link quality (RSSI/LQI) + * \remark This function convers the input parameters to a ftdf_transparent_indication_t structure + * and then calls ftdf_rcv_msg. * \remark FTDF_RCV_FRAME_TRANSPARENT can be defined to be this function. */ -void FTDF_rcvFrameTransparent( FTDF_DataLength frameLength, - FTDF_Octet* frame, - FTDF_Bitmap32 status, - FTDF_LinkQuality lqi); +void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length, ftdf_octet_t *frame, + ftdf_bitmap32_t status, ftdf_link_quality_t link_quality); /** - * \brief FTDF_setSleepAttributes - Set sleep atributes - * \param[in] lowPowerClockCycle: The LP clock cycle in picoseconds - * \param[in] wakeUpLatency: The wakep up latency time in low power clock cycles + * \brief ftdf_set_sleep_attributes - Set sleep atributes + * \param[in] low_power_clock_cycle: The LP clock cycle in picoseconds + * \param[in] wakeup_latency: The wakep up latency time in low power clock cycles * \remark This functions sets some attributes required by FTDF to go into a deep sleep and wake up from it. * \remark The wake up latency is the time between the wakeup signal send by FTDF and the moment that the * clocks are stable. It will be used by FTDF to determine when it must must send the wakeup signal. - * \remark The low power clock cycle will be used to determine how long the system has slept and recover + * \remark The low power clock cycle will be used to determine how long the system has slept and recover * the symbol counter internally used by FTDF. */ -void FTDF_setSleepAttributes( FTDF_PSec lowPowerClockCycle, - FTDF_NrLowPowerClockCycles wakeUpLatency ); +void ftdf_set_sleep_attributes(ftdf_psec_t low_power_clock_cycle, + ftdf_nr_low_power_clock_cycles_t wakeup_latency); /** - * \brief FTDF_canSleep - Indicates whether FTDF can go in a deep sleep + * \brief ftdf_can_sleep - Indicates whether FTDF can go in a deep sleep * \remark This function returns the time in microseconds that the FTDF can deep sleep. * \remark It does NOT take into account the wakeup latency. * \return The number of microseconds that the FTDF can deep sleep. If equal to 0 the FTDF is still active * and cannot deep sleep */ -FTDF_USec FTDF_canSleep( void ); +ftdf_usec_t ftdf_can_sleep(void); /** - * \brief FTDF_prepareForSleep - Prepare the FTDF for a deep sleep - * \param[in] sleepTime: The sleep time. After the sleep time the FTDF must be ready to do next scheduled activity. + * \brief ftdf_prepare_for_sleep - Prepare the FTDF for a deep sleep + * \param[in] sleep_time: The sleep time. After the sleep time the FTDF must be ready to do next scheduled activity. * \remark When this function is completed the application can safely power off the FTDF and put the uP in * a deep sleep. At least wake up latency time microseconds before sleep time is expired the FTDF - * will send a wakeup signal. FTDF expect that the application calls FTDF_wakeUp as it has been + * will send a wakeup signal. FTDF expect that the application calls ftdf_wakeup as it has been * woken up. - * \return FTDF_TRUE if the FTDF can be put in deep sleep, FTDF_FALSE if the sleepTime is too short to go to - * deep sleep and wake up again after sleepTime microseconds, the FTDF cannot be put in deep sleep. + * \return FTDF_TRUE if the FTDF can be put in deep sleep, FTDF_FALSE if the sleep_time is too short to go to + * deep sleep and wake up again after sleep_time microseconds, the FTDF cannot be put in deep sleep. */ -FTDF_Boolean FTDF_prepareForSleep( FTDF_USec sleepTime ); +ftdf_boolean_t ftdf_prepare_for_sleep(ftdf_usec_t sleep_time); /** - * \brief FTDF_wakeUp - Wake up the FTDF after a sleep + * \brief ftdf_wakeup - Wake up the FTDF after a sleep * \remark This function will restores the FTDF to state before the deep sleep. It will does this in 2 steps * 1. It initialises it internal states and data structures and all the non timing specific HW. After * that it waits until the wake up latency time has been expired. When expired FTDF assumes that the @@ -3094,7 +3075,7 @@ FTDF_Boolean FTDF_prepareForSleep( FTDF_USec sleepTime ); * 2. It restores timers in HW and calls the function FTDF_WAKE_UP_READY to indicate FTDF is up again, * ready to perform scheduled activities and ready to process new requests from the application. */ -void FTDF_wakeUp( void ); +void ftdf_wakeup(void); /** * \brief FTDF_WAKE_UP_READY - Indication that FTDF has woke up @@ -3103,48 +3084,53 @@ void FTDF_wakeUp( void ); * \remark FTDF calls this function when it is up again, ready to perform scheduled activities and ready to * process new requests from the application. */ -void FTDF_WAKE_UP_READY( void ); +void FTDF_WAKE_UP_READY(void); /** * \brief FTDF_SLEEP_CALLBACK - Callback from FTDF_SLEEP_REQUEST * \remark This function must be implemented by the application, it will be called by FTDF. * It must be configured in the configuration file ftdf_config.h - * \remark FTDF calls this function when an FTDF_SLEEP_REQUEST message is sent through the FTDF_sndMsg function. + * \remark FTDF calls this function when an FTDF_SLEEP_REQUEST message is sent through the ftdf_snd_msg function. */ -void FTDF_SLEEP_CALLBACK( FTDF_USec sleepTime ); +void FTDF_SLEEP_CALLBACK(ftdf_usec_t sleep_time); -void FTDF_reset(int setDefaultPIB); +void ftdf_reset(int set_default_pib); -FTDF_PTI FTDF_getRxPti( void ); +ftdf_pti_t ftdf_get_rx_pti(void); -#if FTDF_USE_PTI -void FTDF_setRxPti( FTDF_PTI rx_pti ); + +#if dg_configCOEX_ENABLE_CONFIG +void ftdf_set_rx_pti(ftdf_pti_t rx_pti); #if FTDF_USE_AUTO_PTI -void FTDF_restoreRxPti(void); +void ftdf_restore_rx_pti(void); #endif #endif + #ifdef FTDF_PHY_API -FTDF_Status FTDF_sendFrameSimple( FTDF_DataLength frameLength, - FTDF_Octet* frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean csmaSuppress); -FTDF_PIBAttributeValue *FTDF_getValue(FTDF_PIBAttribute PIBAttribute); -FTDF_Status FTDF_setValue(FTDF_PIBAttribute PIBAttribute, const FTDF_PIBAttributeValue *PIBAttributeValue); -void FTDF_rxEnable(FTDF_Time rxOnDuration); +ftdf_status_t ftdf_send_frame_simple(ftdf_data_length_t frame_length, + ftdf_octet_t *frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t csmaSuppress); + +ftdf_pib_attribute_value_t *ftdf_get_value(ftdf_pib_attribute_t pib_attribute); +ftdf_status_t ftdf_set_value(ftdf_pib_attribute_t pib_attribute, + const ftdf_pib_attribute_value_t *pib_attribute_value); + +void ftdf_rx_enable(ftdf_time_t rx_on_duration); #endif /* FTDF_PHY_API */ #if FTDF_DBG_BUS_ENABLE /** * \brief Checks current debug mode and makes appropriate hardware configurations. */ -void FTDF_checkDbgMode(void); +void ftdf_check_dbg_mode(void); /** * \brief Sets debug bus mode. */ -void FTDF_setDbgMode(FTDF_DbgMode dbgMode); +void ftdf_set_dbg_mode(ftdf_dbg_mode_t dbg_mode); /** * \brief Debug bus GPIO configuration callback. Makes appropriate GPIO configurations for the debug @@ -3154,11 +3140,9 @@ void FTDF_DBG_BUS_GPIO_CONFIG(void); #endif /* FTDF_DBG_BUS_ENABLE */ #if dg_configUSE_FTDF_DDPHY == 1 -void FTDF_ddphySet(uint16_t ccaReg); +void ftdf_ddphy_set(uint16_t cca_reg); #endif /* dg_configUSE_FTDF_DDPHY == 1 */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO #ifndef FTDF_LITE /** @@ -3175,62 +3159,62 @@ void FTDF_ddphySet(uint16_t ccaReg); * * A short address FP FSM accepts the following notifications (events): * - * - New address (initialize) by calling @ref FTDF_fpFsmShortAddressNew() + * - New address (initialize) by calling @ref ftdf_fp_fsm_short_address_new() * - Last frame pending (passed to direct sending) by calling @ref - * FTDF_fpFsmShortAddressLastFramePending() - * - Last pending frame sent by calling @ref FTDF_fpFsmClearPending() + * ftdf_fp_fsm_short_address_last_frame_pending() + * - Last pending frame sent by calling @ref ftdf_fp_fsm_clear_pending() * * A new address may be rejected if there is no adequate space left in FPPR. * - * \param [in] panId Destination PAN ID. - * \param [in] shortAddress Destination short address. + * \param [in] pan_id Destination PAN ID. + * \param [in] short_address Destination short address. * * \return \ref FTDF_TRUE on success. */ -FTDF_Boolean FTDF_fpFsmShortAddressNew(FTDF_PANId panId, FTDF_ShortAddress shortAddress); +ftdf_boolean_t ftdf_fp_fsm_short_address_new(ftdf_pan_id_t pan_id, ftdf_short_address_t short_address); /** * \brief Adds a new extended address to FPPR, initializing the corresponding FSM. * * An extended address FP FSM accepts the following notifications (events): * - * - New address (initialize) by calling @ref FTDF_fpFsmExtAddressNew() + * - New address (initialize) by calling @ref ftdf_fp_fsm_rxt_address_new() * - Last frame pending (passed to direct sending) by calling @ref - * FTDF_fpFsmExtAddressLastFramePending() - * - Last pending frame sent by calling @ref FTDF_fpFsmClearPending() + * ftdf_fp_fsm_ext_address_last_frame_pending() + * - Last pending frame sent by calling @ref ftdf_fp_fsm_clear_pending() * * A new address may be rejected if there is no adequate space left in FPPR. * - * \param [in] panId Destination PAN ID. - * \param [in] extAddress Destination extended address. + * \param [in] pan_id Destination PAN ID. + * \param [in] ext_address Destination extended address. * * \return \ref FTDF_TRUE on success. */ -FTDF_Boolean FTDF_fpFsmExtAddressNew(FTDF_PANId panId, FTDF_ExtAddress extAddress); +ftdf_boolean_t ftdf_fp_fsm_rxt_address_new(ftdf_pan_id_t pan_id, ftdf_ext_address_t ext_address); /** * \brief Notifies FP FSM that the last packet for the associated destination has been passed for * direct transmission. * - * \param [in] panId Destination PAN ID. - * \param [in] shortAddress Destination short address. + * \param [in] pan_id Destination PAN ID. + * \param [in] short_address Destination short address. */ -void FTDF_fpFsmShortAddressLastFramePending(FTDF_PANId panId, FTDF_ShortAddress shortAddress); +void ftdf_fp_fsm_short_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_short_address_t short_address); /** * \brief Notifies FP FSM that the last packet for the associated destination has been passed for * direct transmission. * - * \param [in] panId Destination PAN ID. - * \param [in] shortAddress Destination extended address. + * \param [in] pan_id Destination PAN ID. + * \param [in] ext_address Destination extended address. */ -void FTDF_fpFsmExtAddressLastFramePending(FTDF_PANId panId, FTDF_ExtAddress extAddress); +void ftdf_fp_fsm_ext_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_ext_address_t ext_address); /** * \brief Notifies FP FSM that the last pending packet has been transmitted (UMAC state machine * closed). */ -void FTDF_fpFsmClearPending(void); +void ftdf_fp_fsm_clear_pending(void); #endif /* #ifndef FTDF_LITE */ @@ -3252,47 +3236,47 @@ void FTDF_fpFsmClearPending(void); /** * \brief Resets FPPR table, invalidating all addresses. */ -void FTDF_fpprReset(void); +void ftdf_fppr_reset(void); /** * \brief Gets the short address programmed at the specified FPPR table position. * * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] shortAddrIdx Short address position within the entry (0 to 3). + * \param [in] short_addr_idx Short address position within the entry (0 to 3). * * \return Requested short address */ -FTDF_ShortAddress FTDF_fpprGetShortAddress(uint8_t entry, uint8_t shortAddrIdx); +ftdf_short_address_t ftdf_fppr_get_short_address(uint8_t entry, uint8_t short_addr_idx); /** * \brief Programs a short address programmed at the specified FPPR table position. * * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] shortAddrIdx Short address position within the entry (0 to 3). - * \param [in] Associated short address. + * \param [in] short_addr_idx Short address position within the entry (0 to 3). + * \param [in] short_address short address. */ -void FTDF_fpprSetShortAddress(uint8_t entry, uint8_t shortAddrIdx, - FTDF_ShortAddress shortAddress); +void ftdf_fppr_set_short_address(uint8_t entry, uint8_t short_addr_idx, + ftdf_short_address_t short_address); /** * \brief Determines validity of a short address programmed at the specified FPPR table position. * * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] shortAddrIdx Short address position within the entry (0 to 3). + * \param [in] short_addr_idx Short address position within the entry (0 to 3). * * \return FTDF_TRUE if the address is valid. */ -FTDF_Boolean FTDF_fpprGetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx); +ftdf_boolean_t ftdf_fppr_get_short_address_valid(uint8_t entry, uint8_t short_addr_idx); /** * \brief Sets validity of a short address programmed at the specified FPPR table position. * * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] shortAddrIdx Short address position within the entry (0 to 3). + * \param [in] short_addr_idx Short address position within the entry (0 to 3). * \param [in] valid Associated validity. */ -void FTDF_fpprSetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx, - FTDF_Boolean valid); +void ftdf_fppr_set_short_address_valid(uint8_t entry, uint8_t short_addr_idx, + ftdf_boolean_t valid); /** * \brief Gets the extended address programmed at the specified FPPR table position. @@ -3301,15 +3285,15 @@ void FTDF_fpprSetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx, * * \return Requested extended address */ -FTDF_ExtAddress FTDF_fpprGetExtAddress(uint8_t entry); +ftdf_ext_address_t ftdf_fppr_get_ext_address(uint8_t entry); /** * \brief Programs an extended address programmed at the specified FPPR table position. * * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] Associated extended address. + * \param [in] ext_address Associated extended address. */ -void FTDF_fpprSetExtAddress(uint8_t entry, FTDF_ExtAddress extAddress); +void ftdf_fppr_set_ext_address(uint8_t entry, ftdf_ext_address_t ext_address); /** * \brief Determines validity of an extended address programmed at the specified FPPR table @@ -3319,7 +3303,7 @@ void FTDF_fpprSetExtAddress(uint8_t entry, FTDF_ExtAddress extAddress); * * \return \ref FTDF_TRUE if the address is valid. */ -FTDF_Boolean FTDF_fpprGetExtAddressValid(uint8_t entry); +ftdf_boolean_t ftdf_fppr_get_ext_address_valid(uint8_t entry); /** * \brief Sets validity of an extended address programmed at the specified FPPR table position. @@ -3327,18 +3311,17 @@ FTDF_Boolean FTDF_fpprGetExtAddressValid(uint8_t entry); * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). * \param [in] valid Associated validity. */ -void FTDF_fpprSetExtAddressValid(uint8_t entry, FTDF_Boolean valid); +void ftdf_fppr_set_ext_address_valid(uint8_t entry, ftdf_boolean_t valid); /** * \brief Gets a free (invalid) short address position in the FPPR table. * * \param [out] entry Reference to the FPPR table entry. - * \param [out] shortAddrIdx Reference to the short address position within the entry. + * \param [out] short_addr_idx Reference to the short address position within the entry. * * \return \ref FTDF_TRUE if a free position was found. */ -FTDF_Boolean FTDF_fpprGetFreeShortAddress(uint8_t * entry, - uint8_t * shortAddrIdx); +ftdf_boolean_t ftdf_fppr_get_free_short_address(uint8_t * entry, uint8_t *short_addr_idx); /** * \brief Gets a free (invalid) extended address position in the FPPR table. @@ -3347,57 +3330,57 @@ FTDF_Boolean FTDF_fpprGetFreeShortAddress(uint8_t * entry, * * \return \ref FTDF_TRUE if a free position was found. */ -FTDF_Boolean FTDF_fpprGetFreeExtAddress(uint8_t * entry); +ftdf_boolean_t ftdf_fppr_get_free_ext_address(uint8_t * entry); /** * \brief Looks up a short address within the FPPR table. * * \param [in] shortAddr Associated short address. * \param [out] entry Reference to the FPPR table entry. - * \param [out] shortAddrIdx Reference to the short address position within the entry. + * \param [out] short_addr_idx Reference to the short address position within the entry. * * * \return \ref FTDF_TRUE if the address was found. */ -FTDF_Boolean FTDF_fpprLookupShortAddress(FTDF_ShortAddress shortAddr, uint8_t * entry, - uint8_t * shortAddrIdx); +ftdf_boolean_t ftdf_fppr_lookup_short_address(ftdf_short_address_t shortAddr, uint8_t *entry, + uint8_t *short_addr_idx); /** * \brief Looks up an extended address within the FPPR table. * - * \param [in] extAddr Associated extended address. + * \param [in] ext_addr Associated extended address. * \param [out] entry Reference to the FPPR table entry. * * * \return \ref FTDF_TRUE if the address was found. */ -FTDF_Boolean FTDF_fpprLookupExtAddress(FTDF_ExtAddress extAddr, uint8_t * entry); +ftdf_boolean_t ftdf_fppr_lookup_ext_address(ftdf_ext_address_t ext_addr, uint8_t *entry); #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ /** * \brief Sets FPPR mode. * - * \param [in] matchFp Specifies the value of the FP bit when acknowledging a received frame with a + * \param [in] match_fp Specifies the value of the FP bit when acknowledging a received frame with a * source address that matches a valid a address in the FPPR table. The opposite value is set if the - * source address does not match. Ignored if \a fpOverride is \ref FTDF_TRUE. + * source address does not match. Ignored if \a fp_override is \ref FTDF_TRUE. * - * \param [in] fpOverride If \ref FTDF_TRUE, the value of \a fpForce is used for setting the FP bit, + * \param [in] fp_override If \ref FTDF_TRUE, the value of \a fp_force is used for setting the FP bit, * regardless of the address table matching result. * - * \param [in] fpForce FP bit value when fpOverride is \ref FTDF_TRUE. Ignored otherwise. + * \param [in] fp_force FP bit value when fp_override is \ref FTDF_TRUE. Ignored otherwise. */ -void FTDF_fpprSetMode(FTDF_Boolean matchFp, FTDF_Boolean fpOverride, FTDF_Boolean fpForce); +void ftdf_fppr_set_mode(ftdf_boolean_t match_fp, ftdf_boolean_t fp_override, ftdf_boolean_t fp_force); #if FTDF_FP_BIT_TEST_MODE /** * \brief Gets FPPR mode. * - * \param [out] matchFp Reference to the returned value. \see FTDF_fpprRamSetMode + * \param [out] match_fp Reference to the returned value. \see FTDF_fpprRamSetMode * - * \param [out] fpOverride Reference to the returned value. \see FTDF_fpprRamSetMode + * \param [out] fp_override Reference to the returned value. \see FTDF_fpprRamSetMode * - * \param [out] fpForce FP Reference to the returned value. \see FTDF_fpprRamSetMode + * \param [out] fp_force FP Reference to the returned value. \see FTDF_fpprRamSetMode */ -void FTDF_fpprGetMode(FTDF_Boolean * matchFp, FTDF_Boolean * fpOverride, FTDF_Boolean * fpForce); +void ftdf_fppr_get_mode(ftdf_boolean_t *match_fp, ftdf_boolean_t *fp_override, ftdf_boolean_t *fp_force); #endif //FTDF_FP_BIT_TEST_MODE #if FTDF_USE_LPDP == 1 @@ -3407,7 +3390,7 @@ void FTDF_fpprGetMode(FTDF_Boolean * matchFp, FTDF_Boolean * fpOverride, FTDF_Bo * * \param [in] enable if FTDF_TRUE, LPDP functionality is enabled. */ -void FTDF_lpdpEnable(FTDF_Boolean enable); +void ftdf_lpdp_enable(ftdf_boolean_t enable); #if FTDF_FP_BIT_TEST_MODE /** @@ -3415,11 +3398,10 @@ void FTDF_lpdpEnable(FTDF_Boolean enable); * * \return FTDF_TRUE, if LPDP functionality is enabled. */ -FTDF_Boolean FTDF_lpdpIsEnabled(void); +ftdf_boolean_t ftdf_lpdp_is_enabled(void); #endif #endif /* #if FTDF_USE_LPDP == 1 */ -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ #endif /* FTDF_H_ */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h index 04e68c09c..ceaec5e2d 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h @@ -36,16 +36,18 @@ #ifndef FTDF_CONFIG_PHY_API_H_ #define FTDF_CONFIG_PHY_API_H_ +#include "osal.h" // OS_FREERTOS macro is checked within the header file. + /** * \remark phy configuration values in microseconds */ #define FTDF_PHYTXSTARTUP 0x4c -#define FTDF_PHYTXLATENCY 0x01 +#define FTDF_PHYTXLATENCY 0x02 #define FTDF_PHYTXFINISH 0x00 -#define FTDF_PHYTRXWAIT 0x20 -#define FTDF_PHYRXSTARTUP 0 +#define FTDF_PHYTRXWAIT 0x22 +#define FTDF_PHYRXSTARTUP 0x54 #define FTDF_PHYRXLATENCY 0 -#define FTDF_PHYENABLE 0x21 +#define FTDF_PHYENABLE 0x20 #ifndef FTDF_LITE #define FTDF_LITE @@ -54,81 +56,82 @@ /** * \remark See FTDF_GET_MSG_BUFFER in ftdf.h */ -#define FTDF_GET_MSG_BUFFER ad_ftdf_getMsgBuffer +#define FTDF_GET_MSG_BUFFER ad_ftdf_get_msg_buffer /** * \remark See FTDF_REL_MSG_BUFFER in ftdf.h */ -#define FTDF_REL_MSG_BUFFER ad_ftdf_relMsgBuffer +#define FTDF_REL_MSG_BUFFER ad_ftdf_rel_msg_buffer /** * \remark See FTDF_REC_MSG in ftdf.h */ -#define FTDF_RCV_MSG ad_ftdf_rcvMsg +#define FTDF_RCV_MSG ad_ftdf_rcv_msg /** * \remark See FTDF_GET_DATA_BUFFER in ftdf.h */ -#define FTDF_GET_DATA_BUFFER ad_ftdf_getDataBuffer +#define FTDF_GET_DATA_BUFFER ad_ftdf_get_data_buffer /** * \remark See FTDF_REL_DATA_BUFFER in ftdf.h */ -#define FTDF_REL_DATA_BUFFER ad_ftdf_relDataBuffer +#define FTDF_REL_DATA_BUFFER ad_ftdf_rel_data_buffer /** * \remark See FTDF_GET_EXT_ADDRESS in ftdf.h */ -#define FTDF_GET_EXT_ADDRESS ad_ftdf_getExtAddress +#define FTDF_GET_EXT_ADDRESS ad_ftdf_get_ext_address /** * \remark See FTDF_RCV_FRAME_TRANSPARENT in ftdf.h */ -#define FTDF_RCV_FRAME_TRANSPARENT FTDF_rcvFrameTransparent +#define FTDF_RCV_FRAME_TRANSPARENT ftdf_rcv_frame_transparent /** * \remark See FTDF_SEND_FRAME_TRANSPARENT_CONFIRM in ftdf.h */ -#define FTDF_SEND_FRAME_TRANSPARENT_CONFIRM FTDF_sendFrameTransparentConfirm +#define FTDF_SEND_FRAME_TRANSPARENT_CONFIRM ftdf_send_frame_transparent_confirm /** * \remark See FTDF_WAKE_UP_READY in ftdf.h */ -#define FTDF_WAKE_UP_READY ad_ftdf_wakeUpReady +#define FTDF_WAKE_UP_READY ad_ftdf_wake_up_ready /** * \remark See FTDF_SLEEP_CALLBACK in ftdf.h */ -#define FTDF_SLEEP_CALLBACK ad_ftdf_sleepCb +#define FTDF_SLEEP_CALLBACK ad_ftdf_sleep_cb /* Forward declaration */ -void sleep_when_possible( uint8_t explicit_request, uint32_t sleepTime ); +void sleep_when_possible(uint8_t explicit_request, uint32_t sleep_time); -#define FTDF_LMACREADY4SLEEP_CB sleep_when_possible +#define FTDF_LMACREADY4SLEEP_CB sleep_when_possible #ifndef OS_FREERTOS #define portDISABLE_INTERRUPTS() \ do { \ - __asm volatile ( " cpsid i " ); \ + __asm volatile (" cpsid i "); \ DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \ } while (0) #define portENABLE_INTERRUPTS() \ do { \ DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \ - __asm volatile ( " cpsie i " ); \ + __asm volatile (" cpsie i "); \ } while (0) -void vPortEnterCritical( void ); -void vPortExitCritical( void ); +void vPortEnterCritical(void); +void vPortExitCritical(void); +#define OS_ENTER_CRITICAL_SECTION vPortEnterCritical +#define OS_LEAVE_CRITICAL_SECTION vPortExitCritical #endif /** * \remark Critical section */ - -#define FTDF_criticalVar( ) -#define FTDF_enterCritical( ) vPortEnterCritical() -#define FTDF_exitCritical( ) vPortExitCritical() +#define ftdf_critical_var( ) +#define ftdf_enter_critical( ) OS_ENTER_CRITICAL_SECTION() +#define ftdf_exit_critical( ) OS_LEAVE_CRITICAL_SECTION() #ifndef FTDF_DBG_BUS_ENABLE /** @@ -142,20 +145,47 @@ void vPortExitCritical( void ); #endif #if FTDF_DBG_BUS_ENABLE -#define FTDF_DBG_BUS_GPIO_CONFIG ad_ftdf_dbgBusGpioConfig +#define FTDF_DBG_BUS_GPIO_CONFIG ad_ftdf_dbg_bus_gpio_config + +#ifndef FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 +/** + * \brief Enables FTDF diagnostics on diagnostic pins 6 and 7 on GPIO P1_3 and P2_3. + * + * When enabled, UART must use pins other than the default P1_3, P2_3. + */ +#define FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 (0) +#endif + +#ifndef FTDF_DBG_BUS_USE_SWDIO_PIN +/** + * \brief Enables diagnostics on diagnostic pin 4 on GPIO P0_6. + * + * When enabled, the debugger must be disabled since SWD uses the same pin for SWDIO. + */ +#define FTDF_DBG_BUS_USE_SWDIO_PIN (0) +#endif + +#ifndef FTDF_DBG_BUS_USE_PORT_4 +/** + * \brief Uses Port 4 (instead of GPIOs at Ports 0, 1 and 2) for diagnostics + * + * When enabled, FTDF diagnostics pins uses P4_0 to P4_7 + */ +#define FTDF_DBG_BUS_USE_PORT_4 (0) +#endif + #endif /* FTDF_DBG_BUS_ENABLE */ +#ifndef FTDF_USE_AUTO_PTI +#define FTDF_USE_AUTO_PTI 0 +#endif + #ifndef FTDF_USE_FP_PROCESSING_RAM /** * \brief Whether to use HW acceleration for indirect sending. * - * Feature is supported as of IC revision 14683-00. */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A #define FTDF_USE_FP_PROCESSING_RAM 1 -#else -#define FTDF_USE_FP_PROCESSING_RAM 0 -#endif #endif /* FTDF_USE_FP_PROCESSING_RAM */ #endif /* FTDF_CONFIG_PHY_API_H_ */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c index cc829d982..84147e561 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c @@ -1,7 +1,7 @@ /** **************************************************************************************** * - * @file ftdf.c + * @file ad_ftdf.c * * @brief FTDF FreeRTOS Adapter * @@ -43,14 +43,17 @@ #include "sys_power_mgr.h" #endif +#if dg_configRF_ADAPTER #include "ad_rf.h" +#else +#include "hw_rf.h" +#endif #include "sys_tcs.h" #include "sdk_defs.h" #include "ad_ftdf.h" #include "internal.h" -#include "regmap.h" #if FTDF_DBG_BUS_ENABLE #include "hw_gpio.h" #endif /* FTDF_DBG_BUS_ENABLE */ @@ -74,166 +77,155 @@ #endif #endif -PRIVILEGED_DATA FTDF_Boolean explicit_sleep; /* = FTDF_FALSE; */ -PRIVILEGED_DATA eSleepStatus sleep_status; +PRIVILEGED_DATA ftdf_boolean_t explicit_sleep; /* = FTDF_FALSE; */ +PRIVILEGED_DATA sleep_status_t sleep_status; -PRIVILEGED_DATA FTDF_ExtAddress uExtAddress; +PRIVILEGED_DATA ftdf_ext_address_t u_ext_address; static void ad_ftdf_sleep(void) { + ftdf_critical_var(); + ftdf_enter_critical(); + REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go sleep + ftdf_exit_critical(); - FTDF_criticalVar(); - FTDF_enterCritical(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go sleep - FTDF_exitCritical(); - - while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_DOWN) == 0x0) // don't go-go before I sleep - { - } + // don't go-go before I sleep + while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_DOWN) == 0x0) { + } #if FTDF_DBG_BLOCK_SLEEP_ENABLE - hw_gpio_set_inactive(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN); + hw_gpio_set_inactive(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN); #endif } void ad_ftdf_wake_up_internal(bool sync) { - if (sleep_status != BLOCK_SLEEPING) - { - return; - } + if ( sleep_status != BLOCK_SLEEPING ) { + return; + } - FTDF_criticalVar(); - FTDF_enterCritical(); - /* Wake up power domains */ - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up - FTDF_exitCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); + /* Wake up power domains */ + REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up + ftdf_exit_critical(); - while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) // don't go-go before I sleep - { - } + // don't go-go before I sleep + while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) { + } #if FTDF_DBG_BLOCK_SLEEP_ENABLE - hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); + hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); #endif - /* Power on and configure RF */ - ad_rf_request_on(false); + /* Power on and configure RF */ +#if dg_configRF_ADAPTER + ad_rf_request_on(false); +#else + hw_rf_request_on(false); +#endif - /* Apply trim values */ -// sys_tcs_apply(tcs_ftdf); + /* Apply trim values */ + sys_tcs_apply(tcs_ftdf); - ad_rf_request_recommended_settings(); +#if dg_configRF_ADAPTER + ad_rf_request_recommended_settings(); +#else + hw_rf_request_recommended_settings(); +#endif - if (sync) - { - FTDF_initLmac(); - sleep_status = BLOCK_ACTIVE; - } - else - { - /* Wake up FTDF block */ - sleep_status = BLOCK_WAKING_UP; - FTDF_wakeUp(); + + if (sync) { + ftdf_init_lmac( ); + sleep_status = BLOCK_ACTIVE; + } else { + /* Wake up FTDF block */ + sleep_status = BLOCK_WAKING_UP; + ftdf_wakeup(); #if defined(FTDF_NO_CSL) && defined(FTDF_NO_TSCH) - ad_ftdf_wakeUpReady(); + ad_ftdf_wake_up_ready(); #endif - } + } } void ad_ftdf_wake_up_async(void) { - ad_ftdf_wake_up_internal(false); + ad_ftdf_wake_up_internal(false); } void ad_ftdf_wake_up_sync(void) { - ad_ftdf_wake_up_internal(true); + ad_ftdf_wake_up_internal(true); } -void sleep_when_possible(uint8_t explicit_request, uint32_t sleepTime) +void sleep_when_possible(uint8_t explicit_request, uint32_t sleep_time ) { - FTDF_Boolean blockSleep = FTDF_FALSE; + ftdf_boolean_t block_sleep = FTDF_FALSE; - if ((!AD_FTDF_SLEEP_WHEN_IDLE && !explicit_request) || sleep_status != BLOCK_ACTIVE) - { - return; - } - - FTDF_USec us; - - - FTDF_criticalVar(); - FTDF_enterCritical(); -#ifdef FTDF_PHY_API - - if (explicit_request && FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) - { - volatile uint32_t *lmacCtrlMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_CONTROL_MASK); - volatile uint32_t *lmacReady4sleepEvent = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_LMACREADY4SLEEP_D); - - /* clear a previous interrupt */ - *lmacReady4sleepEvent = MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D; - - /* Enable (unmask) interrupt */ - *lmacCtrlMask |= MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M; - us = 0; - } - else - { - us = FTDF_canSleep(); - } - -#else - us = FTDF_canSleep(); -#endif - - /* Try to sleep as much as needed (if sleepTime is 0, then sleep as much as possible). - * Otherwise, sleep as much as possible. */ - if (explicit_request == FTDF_TRUE) - { - if (sleepTime && us > sleepTime) - { - us = sleepTime; + if ((!AD_FTDF_SLEEP_WHEN_IDLE && !explicit_request) || sleep_status != BLOCK_ACTIVE) { + return; } - } - if (us > (WUP_LATENCY / 1000000) + AD_FTDF_SLEEP_COMPENSATION) - { - // Subtract sleep compensation from the sleep time, compensating for delays - us -= AD_FTDF_SLEEP_COMPENSATION; + ftdf_usec_t us; - blockSleep = FTDF_prepareForSleep(us); - if (blockSleep) - { - // FTDF ready to sleep, disable clocks - sleep_status = BLOCK_SLEEPING; - explicit_sleep = explicit_request; + ftdf_critical_var(); + ftdf_enter_critical(); +#ifdef FTDF_PHY_API + if (explicit_request && (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0)) { + + /* clear a previous interrupt */ + FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, LMACREADY4SLEEP_D); + + /* Enable (unmask) interrupt */ + REG_SET_BIT(FTDF, FTDF_LMAC_CONTROL_MASK_REG, LMACREADY4SLEEP_M); + us = 0; + } else { + us = ftdf_can_sleep(); + } +#else + us = ftdf_can_sleep(); +#endif + /* Try to sleep as much as needed (if sleep_time is 0, then sleep as much as possible). + * Otherwise, sleep as much as possible. */ + if ( explicit_request == FTDF_TRUE ) { + if (sleep_time && us > sleep_time) + us = sleep_time; + } + + if (us > ( WUP_LATENCY / 1000000) + AD_FTDF_SLEEP_COMPENSATION) { + // Subtract sleep compensation from the sleep time, compensating for delays + us -= AD_FTDF_SLEEP_COMPENSATION; + + block_sleep = ftdf_prepare_for_sleep(us); + + if (block_sleep) { + // FTDF ready to sleep, disable clocks + sleep_status = BLOCK_SLEEPING; + explicit_sleep = explicit_request; #if FTDF_USE_SLEEP_DURING_BACKOFF - FTDF_sdbFsmSleep(); + ftdf_sdb_fsm_sleep(); #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ #if dg_configUSE_FTDF_DDPHY == 1 - FTDF_ddphySave(); + ftdf_ddphy_save(); #endif /* dg_configUSE_FTDF_DDPHY */ - ad_ftdf_sleep(); - } - else - { + ad_ftdf_sleep(); + } else { #if FTDF_USE_SLEEP_DURING_BACKOFF - FTDF_sdbFsmAbortSleep(); + ftdf_sdb_fsm_abort_sleep(); #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + } + } + ftdf_exit_critical(); + if (block_sleep) { +#if dg_configRF_ADAPTER + ad_rf_request_off(false); +#else + hw_rf_request_off(false); +#endif } - } - - FTDF_exitCritical(); - - if (blockSleep) - { - ad_rf_request_off(false); - } } /** @@ -241,76 +233,109 @@ void sleep_when_possible(uint8_t explicit_request, uint32_t sleepTime) */ void ad_ftdf_init(void) { - /* Wake up power domains */ - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up + /* Wake up power domains */ + GLOBAL_INT_DISABLE(); + REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up + GLOBAL_INT_RESTORE(); - while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) // don't go-go before I sleep - { - } + // don't go-go before I sleep + while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) { + + } #if FTDF_DBG_BLOCK_SLEEP_ENABLE - hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); + hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); #endif - REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE); // on - REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); // divide by 1 + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE); // on + REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); // divide by 1 + GLOBAL_INT_RESTORE(); - /* Power on and configure RF */ - ad_rf_request_on(false); + /* Power on and configure RF */ +#if dg_configRF_ADAPTER + ad_rf_request_on(false); +#else + hw_rf_request_on(false); +#endif - /* Apply trim values */ - sys_tcs_apply(tcs_ftdf); + /* Apply trim values */ + sys_tcs_apply(tcs_ftdf); - ad_rf_request_recommended_settings(); +#if dg_configRF_ADAPTER + ad_rf_request_recommended_settings(); +#else + hw_rf_request_recommended_settings(); +#endif - FTDF_setSleepAttributes(AD_FTDF_LP_CLOCK_CYCLE, - AD_FTDF_WUP_LATENCY); + ftdf_set_sleep_attributes( AD_FTDF_LP_CLOCK_CYCLE, AD_FTDF_WUP_LATENCY ); #ifdef FTDF_PHY_API - ad_ftdf_init_phy_api(); + ad_ftdf_init_phy_api(); #else - ad_ftdf_init_mac_api(); + ad_ftdf_init_mac_api(); #endif } -void ad_ftdf_sleepCb(FTDF_USec sleepTime) +void ad_ftdf_sleep_cb(ftdf_usec_t sleep_time ) { - sleep_when_possible(FTDF_TRUE, sleepTime); - - + sleep_when_possible( FTDF_TRUE, sleep_time ); } #if FTDF_DBG_BUS_ENABLE -void ad_ftdf_dbgBusGpioConfig(void) +void ad_ftdf_dbg_bus_gpio_config(void) { - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); + +#if FTDF_DBG_BUS_USE_PORT_4 == 1 + + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_0, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_1, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_2, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + + +#else + hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); #if FTDF_DBG_BUS_USE_SWDIO_PIN - /* - * Note that this pin has a conflict with SWD. Disable the debugger in order to use this - * pin. - */ - hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); + /* + * Note that this pin has a conflict with SWD. Disable the debugger in order to use this + * pin. + */ + hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); #endif - hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); #if FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 - /* - * Note that these pins have a conflict with the pins used for UART by default. Configure - * UART on different pins if you would like to use the pins below for diagnostics. - */ - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); + /* + * Note that these pins have a conflict with the pins used for UART by default. Configure + * UART on different pins if you would like to use the pins below for diagnostics. + */ + hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); + hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, + HW_GPIO_FUNC_FTDF_DIAG); #endif +#endif /* FTDF_DBG_BUS_USE_PORT_4 == 1 */ } #endif /* FTDF_DBG_BUS_ENABLE */ #endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h index 74da2d3d1..b432d7a9f 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h @@ -7,6 +7,7 @@ /** **************************************************************************************** + * * @file ad_ftdf.h * * @brief FTDF Adapter internal header file @@ -53,11 +54,11 @@ typedef enum { BLOCK_ACTIVE = 0, BLOCK_SLEEPING, BLOCK_WAKING_UP -} eSleepStatus; +} sleep_status_t; -extern eSleepStatus sleep_status; -extern FTDF_ExtAddress uExtAddress; -extern FTDF_Boolean explicit_sleep; +extern sleep_status_t sleep_status; +extern ftdf_ext_address_t u_ext_address; +extern ftdf_boolean_t explicit_sleep; void ad_ftdf_init_mac_api(void); void ad_ftdf_init_phy_api(void); @@ -65,7 +66,7 @@ void ad_ftdf_init_phy_api(void); void ad_ftdf_wake_up_async(void); void ad_ftdf_wake_up_sync(void); -void sleep_when_possible( uint8_t explicit_request, uint32_t sleepTime ); +void sleep_when_possible( uint8_t explicit_request, uint32_t sleep_time ); #if FTDF_DBG_BUS_ENABLE /** @@ -82,7 +83,7 @@ void sleep_when_possible( uint8_t explicit_request, uint32_t sleepTime ); * bit 6: HW_GPIO_PORT_1, HW_GPIO_PIN_3 * bit 7: HW_GPIO_PORT_2, HW_GPIO_PIN_3 */ -void ad_ftdf_dbgBusGpioConfig(void); +void ad_ftdf_dbg_bus_gpio_config(void); #endif /* FTDF_DBG_BUS_ENABLE */ #endif /* AD_FTDF_H */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c index 48ce71514..098817ec3 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c @@ -1,7 +1,7 @@ /** **************************************************************************************** * - * @file ftdf.c + * @file ad_ftdf_phy_api.c * * @brief FTDF FreeRTOS Adapter * @@ -50,122 +50,115 @@ #ifndef OS_FREERTOS static unsigned long uxCriticalNesting = 0xaaaaaaaa; -void vPortEnterCritical(void) +void vPortEnterCritical( void ) { - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; - __asm volatile("dsb"); - __asm volatile("isb"); + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __asm volatile( "dsb" ); + __asm volatile( "isb" ); } /*-----------------------------------------------------------*/ -void vPortExitCritical(void) +void vPortExitCritical( void ) { - uxCriticalNesting--; - - if (uxCriticalNesting == 0) - { - portENABLE_INTERRUPTS(); - } + uxCriticalNesting--; + if ( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } } #endif /* !OS_FREERTOS */ /** * @brief ftdf_gen_irq interrupt service routine */ -void FTDF_GEN_Handler(void) +void FTDF_GEN_Handler( void) { - FTDF_confirmLmacInterrupt(); - FTDF_eventHandler(); + ftdf_confirm_lmac_interrupt(); + ftdf_event_handler(); } /** * @brief ftdf_wakup_irq interrupt service routine */ -void FTDF_WAKEUP_Handler(void) +void FTDF_WAKEUP_Handler( void) { - ad_ftdf_wake_up_async(); -} - -void ad_ftdf_setExtAddress(FTDF_ExtAddress address) -{ - uExtAddress = address; -} - -FTDF_ExtAddress ad_ftdf_getExtAddress(void) -{ - return uExtAddress; -} - -void ad_ftdf_wakeUpReady(void) -{ -} - -FTDF_Status ad_ftdf_send_frame_simple(FTDF_DataLength frameLength, - FTDF_Octet *frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean csmaSuppress) -{ - FTDF_criticalVar(); - FTDF_enterCritical(); - - if (FTDF_txInProgress == FTDF_TRUE) - { - FTDF_exitCritical(); - return FTDF_TRANSPARENT_OVERFLOW; - } - - FTDF_txInProgress = FTDF_TRUE; - FTDF_exitCritical(); - - if (sleep_status == BLOCK_SLEEPING) - { - /* Wake-up the block */ ad_ftdf_wake_up_async(); -#if FTDF_DBG_BUS_ENABLE - FTDF_checkDbgMode(); -#endif /* FTDF_DBG_BUS_ENABLE */ - sleep_status = BLOCK_ACTIVE; - } +} - return FTDF_sendFrameSimple(frameLength, frame, channel, pti, csmaSuppress); +void ad_ftdf_set_ext_address( ftdf_ext_address_t address) +{ + u_ext_address = address; +} + +ftdf_ext_address_t ad_ftdf_get_ext_address( void) +{ + return u_ext_address; +} + +void ad_ftdf_wake_up_ready( void) +{ +} + +ftdf_status_t ad_ftdf_send_frame_simple( ftdf_data_length_t frameLength, + ftdf_octet_t *frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t csmaSuppress) +{ + ftdf_critical_var(); + ftdf_enter_critical(); + if (ftdf_tx_in_progress == FTDF_TRUE) { + ftdf_exit_critical(); + return FTDF_TRANSPARENT_OVERFLOW; + } + ftdf_tx_in_progress = FTDF_TRUE; + ftdf_exit_critical(); + + if (sleep_status == BLOCK_SLEEPING) { + /* Wake-up the block */ + ad_ftdf_wake_up_async(); +#if FTDF_DBG_BUS_ENABLE + ftdf_check_dbg_mode(); +#endif /* FTDF_DBG_BUS_ENABLE */ + sleep_status = BLOCK_ACTIVE; + } + return ftdf_send_frame_simple(frameLength, frame, channel, pti, csmaSuppress); } -void ad_ftdf_sleep_when_possible(FTDF_Boolean allow_deferred_sleep) +void ad_ftdf_sleep_when_possible( ftdf_boolean_t allow_deferred_sleep) { - sleep_when_possible(allow_deferred_sleep, 0); + sleep_when_possible(allow_deferred_sleep, 0); } void ad_ftdf_wake_up(void) { - if (sleep_status == BLOCK_SLEEPING) - { - /* Wake-up the block */ - ad_ftdf_wake_up_async(); + if (sleep_status == BLOCK_SLEEPING) { + /* Wake-up the block */ + ad_ftdf_wake_up_async(); #if FTDF_DBG_BUS_ENABLE - FTDF_checkDbgMode(); + ftdf_check_dbg_mode(); #endif /* FTDF_DBG_BUS_ENABLE */ - sleep_status = BLOCK_ACTIVE; - } + sleep_status = BLOCK_ACTIVE; + } } void ad_ftdf_init_phy_api(void) { - NVIC_ClearPendingIRQ(FTDF_WAKEUP_IRQn); - NVIC_EnableIRQ(FTDF_WAKEUP_IRQn); + NVIC_ClearPendingIRQ(FTDF_WAKEUP_IRQn); + NVIC_EnableIRQ(FTDF_WAKEUP_IRQn); - NVIC_ClearPendingIRQ(FTDF_GEN_IRQn); // Disable ftdf interrupts - NVIC_EnableIRQ(FTDF_GEN_IRQn); // ftdf will be handled by poiling - sleep_status = BLOCK_ACTIVE; + NVIC_ClearPendingIRQ(FTDF_GEN_IRQn); + NVIC_EnableIRQ(FTDF_GEN_IRQn); + sleep_status = BLOCK_ACTIVE; #ifndef OS_FREERTOS - uxCriticalNesting = 0; + uxCriticalNesting = 0; #endif - FTDF_reset(1); + ftdf_reset(1); } #endif /* FTDF_PHY_API */ #endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c index caa379bff..4f7342079 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c @@ -38,5562 +38,5180 @@ #include #include "internal.h" -#include "regmap.h" #include "sdk_defs.h" +#ifdef CONFIG_USE_FTDF #if dg_configCOEX_ENABLE_CONFIG #include "hw_coex.h" #endif -typedef struct -{ - void *addr; - uint8_t size; - void (* getFunc)(void); - void (* setFunc)(void); -} PIBAttributeDef; +typedef struct { + void *addr; + uint8_t size; + void (*getFunc)(void); + void (*setFunc)(void); +} pib_attribute_def_t; -typedef struct -{ - PIBAttributeDef attributeDefs[ FTDF_NR_OF_PIB_ATTRIBUTES + 1 ]; -} PIBAttributeTable; +typedef struct { + pib_attribute_def_t attribute_defs[FTDF_NR_OF_PIB_ATTRIBUTES + 1]; +} pib_attribute_table_h; -struct FTDF_Pib FTDF_pib __attribute__((section(".retention"))); +ftdf_pib_t ftdf_pib __attribute__ ((section(".retention"))); #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO #if FTDF_FPPR_DEFER_INVALIDATION -static struct -{ - FTDF_AddressMode addrMode; - FTDF_PANId PANId; - FTDF_Address addr; -} FTDF_fpprPending __attribute__((section(".retention"))); +static struct { + ftdf_address_mode_t addr_mode; + ftdf_pan_id_t pan_id; + ftdf_address_t addr; +} ftdf_fppr_pending __attribute__ ((section(".retention"))); #endif /* FTDF_FPPR_DEFER_INVALIDATION */ #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ #ifndef FTDF_LITE -const FTDF_ChannelNumber page0Channels[ FTDF_NR_OF_CHANNELS ] = -{ 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; -const FTDF_ChannelDescriptor channelDescriptors[ 1 ] = { { 0, 16, (FTDF_ChannelNumber *) page0Channels } }; -const FTDF_ChannelDescriptorList channelsSupported = { 1, (FTDF_ChannelDescriptor *) channelDescriptors }; +const ftdf_channel_number_t page_0_channels[FTDF_NR_OF_CHANNELS] = { + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; +const ftdf_channel_descriptor_t channel_descriptors[1] = { + { 0, 16, (ftdf_channel_number_t*)page_0_channels } }; +const ftdf_channel_descriptor_list_t channels_supported = { + 1, (ftdf_channel_descriptor_t*)channel_descriptors }; #endif -const PIBAttributeTable pibAttributeTable = -{ - .attributeDefs[ FTDF_PIB_EXTENDED_ADDRESS ].addr = &FTDF_pib.extAddress, - .attributeDefs[ FTDF_PIB_EXTENDED_ADDRESS ].size = sizeof(FTDF_pib.extAddress), - .attributeDefs[ FTDF_PIB_EXTENDED_ADDRESS ].getFunc = FTDF_getExtAddress, - .attributeDefs[ FTDF_PIB_EXTENDED_ADDRESS ].setFunc = FTDF_setExtAddress, - .attributeDefs[ FTDF_PIB_ACK_WAIT_DURATION ].addr = &FTDF_pib.ackWaitDuration, - .attributeDefs[ FTDF_PIB_ACK_WAIT_DURATION ].size = 0, - .attributeDefs[ FTDF_PIB_ACK_WAIT_DURATION ].getFunc = FTDF_getAckWaitDuration, - .attributeDefs[ FTDF_PIB_ACK_WAIT_DURATION ].setFunc = NULL, +const pib_attribute_table_h pib_attribute_table = { + .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].addr = &ftdf_pib.ext_address, + .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].size = sizeof(ftdf_pib.ext_address), + .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].getFunc = ftdf_get_ext_address, + .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].setFunc = ftdf_set_ext_address, + .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].addr = &ftdf_pib.ack_wait_duration, + .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].size = 0, + .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].getFunc = ftdf_get_ack_wait_duration, + .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].setFunc = NULL, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_ASSOCIATION_PAN_COORD ].addr = &FTDF_pib.associatedPANCoord, - .attributeDefs[ FTDF_PIB_ASSOCIATION_PAN_COORD ].size = sizeof(FTDF_pib.associatedPANCoord), - .attributeDefs[ FTDF_PIB_ASSOCIATION_PAN_COORD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_ASSOCIATION_PAN_COORD ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_ASSOCIATION_PERMIT ].addr = &FTDF_pib.associationPermit, - .attributeDefs[ FTDF_PIB_ASSOCIATION_PERMIT ].size = sizeof(FTDF_pib.associationPermit), - .attributeDefs[ FTDF_PIB_ASSOCIATION_PERMIT ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_ASSOCIATION_PERMIT ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_AUTO_REQUEST ].addr = &FTDF_pib.autoRequest, - .attributeDefs[ FTDF_PIB_AUTO_REQUEST ].size = sizeof(FTDF_pib.autoRequest), - .attributeDefs[ FTDF_PIB_AUTO_REQUEST ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_AUTO_REQUEST ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT ].addr = &FTDF_pib.battLifeExt, - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT ].size = sizeof(FTDF_pib.battLifeExt), - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT_PERIODS ].addr = &FTDF_pib.battLifeExtPeriods, - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT_PERIODS ].size = sizeof(FTDF_pib.battLifeExtPeriods), - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT_PERIODS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BATT_LIFE_EXT_PERIODS ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD ].addr = &FTDF_pib.beaconPayload, - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD ].size = sizeof(FTDF_pib.beaconPayload), - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD_LENGTH ].addr = &FTDF_pib.beaconPayloadLength, - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD_LENGTH ].size = sizeof(FTDF_pib.beaconPayloadLength), - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD_LENGTH ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_PAYLOAD_LENGTH ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_ORDER ].addr = &FTDF_pib.beaconOrder, - .attributeDefs[ FTDF_PIB_BEACON_ORDER ].size = 0, - .attributeDefs[ FTDF_PIB_BEACON_ORDER ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_ORDER ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_TX_TIME ].addr = &FTDF_pib.beaconTxTime, - .attributeDefs[ FTDF_PIB_BEACON_TX_TIME ].size = sizeof(FTDF_pib.beaconTxTime), - .attributeDefs[ FTDF_PIB_BEACON_TX_TIME ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_TX_TIME ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_BSN ].addr = &FTDF_pib.BSN, - .attributeDefs[ FTDF_PIB_BSN ].size = sizeof(FTDF_pib.BSN), - .attributeDefs[ FTDF_PIB_BSN ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BSN ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_COORD_EXTENDED_ADDRESS ].addr = &FTDF_pib.coordExtAddress, - .attributeDefs[ FTDF_PIB_COORD_EXTENDED_ADDRESS ].size = sizeof(FTDF_pib.coordExtAddress), - .attributeDefs[ FTDF_PIB_COORD_EXTENDED_ADDRESS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_COORD_EXTENDED_ADDRESS ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_COORD_SHORT_ADDRESS ].addr = &FTDF_pib.coordShortAddress, - .attributeDefs[ FTDF_PIB_COORD_SHORT_ADDRESS ].size = sizeof(FTDF_pib.coordShortAddress), - .attributeDefs[ FTDF_PIB_COORD_SHORT_ADDRESS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_COORD_SHORT_ADDRESS ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_DSN ].addr = &FTDF_pib.DSN, - .attributeDefs[ FTDF_PIB_DSN ].size = sizeof(FTDF_pib.DSN), - .attributeDefs[ FTDF_PIB_DSN ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_DSN ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_GTS_PERMIT ].addr = &FTDF_pib.GTSPermit, - .attributeDefs[ FTDF_PIB_GTS_PERMIT ].size = 0, - .attributeDefs[ FTDF_PIB_GTS_PERMIT ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_GTS_PERMIT ].setFunc = NULL, + .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].addr = &ftdf_pib.associated_pan_coord, + .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].size = sizeof(ftdf_pib.associated_pan_coord), + .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].getFunc = NULL, + .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].setFunc = NULL, + .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].addr = &ftdf_pib.association_permit, + .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].size = sizeof(ftdf_pib.association_permit), + .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].getFunc = NULL, + .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].setFunc = NULL, + .attribute_defs[FTDF_PIB_AUTO_REQUEST].addr = &ftdf_pib.auto_request, + .attribute_defs[FTDF_PIB_AUTO_REQUEST].size = sizeof(ftdf_pib.auto_request), + .attribute_defs[FTDF_PIB_AUTO_REQUEST].getFunc = NULL, + .attribute_defs[FTDF_PIB_AUTO_REQUEST].setFunc = NULL, + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].addr = &ftdf_pib.batt_life_ext, + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].size = sizeof(ftdf_pib.batt_life_ext), + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].getFunc = NULL, + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].setFunc = NULL, + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].addr = &ftdf_pib.batt_life_ext_periods, + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].size = sizeof(ftdf_pib.batt_life_ext_periods), + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].getFunc = NULL, + .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].setFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].addr = &ftdf_pib.beacon_payload, + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].size = sizeof(ftdf_pib.beacon_payload), + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].getFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].setFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].addr = &ftdf_pib.beacon_payload_length, + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].size = sizeof(ftdf_pib.beacon_payload_length), + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].getFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].setFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_ORDER].addr = &ftdf_pib.beacon_order, + .attribute_defs[FTDF_PIB_BEACON_ORDER].size = 0, + .attribute_defs[FTDF_PIB_BEACON_ORDER].getFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_ORDER].setFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_TX_TIME].addr = &ftdf_pib.beacon_tx_time, + .attribute_defs[FTDF_PIB_BEACON_TX_TIME].size = sizeof(ftdf_pib.beacon_tx_time), + .attribute_defs[FTDF_PIB_BEACON_TX_TIME].getFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_TX_TIME].setFunc = NULL, + .attribute_defs[FTDF_PIB_BSN].addr = &ftdf_pib.bsn, + .attribute_defs[FTDF_PIB_BSN].size = sizeof(ftdf_pib.bsn), + .attribute_defs[FTDF_PIB_BSN].getFunc = NULL, + .attribute_defs[FTDF_PIB_BSN].setFunc = NULL, + .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].addr = &ftdf_pib.coord_ext_address, + .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].size = sizeof(ftdf_pib.coord_ext_address), + .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].getFunc = NULL, + .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].setFunc = NULL, + .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].addr = &ftdf_pib.coord_short_address, + .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].size = sizeof(ftdf_pib.coord_short_address), + .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].getFunc = NULL, + .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].setFunc = NULL, + .attribute_defs[FTDF_PIB_DSN].addr = &ftdf_pib.dsn, + .attribute_defs[FTDF_PIB_DSN].size = sizeof(ftdf_pib.dsn), + .attribute_defs[FTDF_PIB_DSN].getFunc = NULL, + .attribute_defs[FTDF_PIB_DSN].setFunc = NULL, + .attribute_defs[FTDF_PIB_GTS_PERMIT].addr = &ftdf_pib.gts_permit, + .attribute_defs[FTDF_PIB_GTS_PERMIT].size = 0, + .attribute_defs[FTDF_PIB_GTS_PERMIT].getFunc = NULL, + .attribute_defs[FTDF_PIB_GTS_PERMIT].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_MAX_BE ].addr = &FTDF_pib.maxBE, - .attributeDefs[ FTDF_PIB_MAX_BE ].size = sizeof(FTDF_pib.maxBE), - .attributeDefs[ FTDF_PIB_MAX_BE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MAX_BE ].setFunc = FTDF_setMaxBE, - .attributeDefs[ FTDF_PIB_MAX_CSMA_BACKOFFS ].addr = &FTDF_pib.maxCSMABackoffs, - .attributeDefs[ FTDF_PIB_MAX_CSMA_BACKOFFS ].size = sizeof(FTDF_pib.maxCSMABackoffs), - .attributeDefs[ FTDF_PIB_MAX_CSMA_BACKOFFS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MAX_CSMA_BACKOFFS ].setFunc = FTDF_setMaxCSMABackoffs, - .attributeDefs[ FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME ].addr = &FTDF_pib.maxFrameTotalWaitTime, - .attributeDefs[ FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME ].size = sizeof(FTDF_pib.maxFrameTotalWaitTime), - .attributeDefs[ FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME ].getFunc = FTDF_getMaxFrameTotalWaitTime, - .attributeDefs[ FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME ].setFunc = FTDF_setMaxFrameTotalWaitTime, - .attributeDefs[ FTDF_PIB_MAX_FRAME_RETRIES ].addr = &FTDF_pib.maxFrameRetries, - .attributeDefs[ FTDF_PIB_MAX_FRAME_RETRIES ].size = sizeof(FTDF_pib.maxFrameRetries), - .attributeDefs[ FTDF_PIB_MAX_FRAME_RETRIES ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MAX_FRAME_RETRIES ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_MIN_BE ].addr = &FTDF_pib.minBE, - .attributeDefs[ FTDF_PIB_MIN_BE ].size = sizeof(FTDF_pib.minBE), - .attributeDefs[ FTDF_PIB_MIN_BE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MIN_BE ].setFunc = FTDF_setMinBE, + .attribute_defs[FTDF_PIB_MAX_BE].addr = &ftdf_pib.max_be, + .attribute_defs[FTDF_PIB_MAX_BE].size = sizeof(ftdf_pib.max_be), + .attribute_defs[FTDF_PIB_MAX_BE].getFunc = NULL, + .attribute_defs[FTDF_PIB_MAX_BE].setFunc = ftdf_set_max_be, + .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].addr = &ftdf_pib.max_csma_backoffs, + .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].size = sizeof(ftdf_pib.max_csma_backoffs), + .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].getFunc = NULL, + .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].setFunc = ftdf_set_max_csma_backoffs, + .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].addr = &ftdf_pib.max_frame_total_wait_time, + .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].size = sizeof(ftdf_pib.max_frame_total_wait_time), + .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].getFunc = ftdf_get_max_frame_total_wait_time, + .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].setFunc = ftdf_set_max_frame_total_wait_time, + .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].addr = &ftdf_pib.max_frame_retries, + .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].size = + sizeof(ftdf_pib.max_frame_retries), + .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].getFunc = NULL, + .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].setFunc = NULL, + .attribute_defs[FTDF_PIB_MIN_BE].addr = &ftdf_pib.min_be, + .attribute_defs[FTDF_PIB_MIN_BE].size = sizeof(ftdf_pib.min_be), + .attribute_defs[FTDF_PIB_MIN_BE].getFunc = NULL, + .attribute_defs[FTDF_PIB_MIN_BE].setFunc = ftdf_set_min_be, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_LIFS_PERIOD ].addr = &FTDF_pib.LIFSPeriod, - .attributeDefs[ FTDF_PIB_LIFS_PERIOD ].size = 0, - .attributeDefs[ FTDF_PIB_LIFS_PERIOD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LIFS_PERIOD ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_SIFS_PERIOD ].addr = &FTDF_pib.SIFSPeriod, - .attributeDefs[ FTDF_PIB_SIFS_PERIOD ].size = 0, - .attributeDefs[ FTDF_PIB_SIFS_PERIOD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SIFS_PERIOD ].setFunc = NULL, + .attribute_defs[FTDF_PIB_LIFS_PERIOD].addr = &ftdf_pib.lifs_period, + .attribute_defs[FTDF_PIB_LIFS_PERIOD].size = 0, + .attribute_defs[FTDF_PIB_LIFS_PERIOD].getFunc = NULL, + .attribute_defs[FTDF_PIB_LIFS_PERIOD].setFunc = NULL, + .attribute_defs[FTDF_PIB_SIFS_PERIOD].addr = &ftdf_pib.sifs_period, + .attribute_defs[FTDF_PIB_SIFS_PERIOD].size = 0, + .attribute_defs[FTDF_PIB_SIFS_PERIOD].getFunc = NULL, + .attribute_defs[FTDF_PIB_SIFS_PERIOD].setFunc = NULL, #endif - .attributeDefs[ FTDF_PIB_PAN_ID ].addr = &FTDF_pib.PANId, - .attributeDefs[ FTDF_PIB_PAN_ID ].size = sizeof(FTDF_pib.PANId), - .attributeDefs[ FTDF_PIB_PAN_ID ].getFunc = FTDF_getPANId, - .attributeDefs[ FTDF_PIB_PAN_ID ].setFunc = FTDF_setPANId, + .attribute_defs[FTDF_PIB_PAN_ID].addr = &ftdf_pib.pan_id, + .attribute_defs[FTDF_PIB_PAN_ID].size = sizeof(ftdf_pib.pan_id), + .attribute_defs[FTDF_PIB_PAN_ID].getFunc = ftdf_getpan_id, + .attribute_defs[FTDF_PIB_PAN_ID].setFunc = ftdf_setpan_id, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_PROMISCUOUS_MODE ].addr = &FTDF_pib.promiscuousMode, - .attributeDefs[ FTDF_PIB_PROMISCUOUS_MODE ].size = sizeof(FTDF_pib.promiscuousMode), - .attributeDefs[ FTDF_PIB_PROMISCUOUS_MODE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_PROMISCUOUS_MODE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_RESPONSE_WAIT_TIME ].addr = &FTDF_pib.responseWaitTime, - .attributeDefs[ FTDF_PIB_RESPONSE_WAIT_TIME ].size = sizeof(FTDF_pib.responseWaitTime), - .attributeDefs[ FTDF_PIB_RESPONSE_WAIT_TIME ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_RESPONSE_WAIT_TIME ].setFunc = NULL, + .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].addr = &ftdf_pib.promiscuous_mode, + .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].size = sizeof(ftdf_pib.promiscuous_mode), + .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].getFunc = NULL, + .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].setFunc = NULL, + .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].addr = &ftdf_pib.response_wait_time, + .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].size = sizeof(ftdf_pib.response_wait_time), + .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].getFunc = NULL, + .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_RX_ON_WHEN_IDLE ].addr = &FTDF_pib.rxOnWhenIdle, - .attributeDefs[ FTDF_PIB_RX_ON_WHEN_IDLE ].size = sizeof(FTDF_pib.rxOnWhenIdle), - .attributeDefs[ FTDF_PIB_RX_ON_WHEN_IDLE ].getFunc = FTDF_getRxOnWhenIdle, - .attributeDefs[ FTDF_PIB_RX_ON_WHEN_IDLE ].setFunc = FTDF_setRxOnWhenIdle, + .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].addr = &ftdf_pib.rx_on_when_idle, + .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].size = sizeof(ftdf_pib.rx_on_when_idle), + .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].getFunc = ftdf_get_rx_on_when_idle, + .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].setFunc = ftdf_set_rx_on_when_idle, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_SECURITY_ENABLED ].addr = &FTDF_pib.securityEnabled, - .attributeDefs[ FTDF_PIB_SECURITY_ENABLED ].size = sizeof(FTDF_pib.securityEnabled), - .attributeDefs[ FTDF_PIB_SECURITY_ENABLED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SECURITY_ENABLED ].setFunc = NULL, + .attribute_defs[FTDF_PIB_SECURITY_ENABLED].addr = &ftdf_pib.security_enabled, + .attribute_defs[FTDF_PIB_SECURITY_ENABLED].size = sizeof(ftdf_pib.security_enabled), + .attribute_defs[FTDF_PIB_SECURITY_ENABLED].getFunc = NULL, + .attribute_defs[FTDF_PIB_SECURITY_ENABLED].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_SHORT_ADDRESS ].addr = &FTDF_pib.shortAddress, - .attributeDefs[ FTDF_PIB_SHORT_ADDRESS ].size = sizeof(FTDF_pib.shortAddress), - .attributeDefs[ FTDF_PIB_SHORT_ADDRESS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SHORT_ADDRESS ].setFunc = FTDF_setShortAddress, + .attribute_defs[FTDF_PIB_SHORT_ADDRESS].addr = &ftdf_pib.short_address, + .attribute_defs[FTDF_PIB_SHORT_ADDRESS].size = sizeof(ftdf_pib.short_address), + .attribute_defs[FTDF_PIB_SHORT_ADDRESS].getFunc = NULL, + .attribute_defs[FTDF_PIB_SHORT_ADDRESS].setFunc = ftdf_set_short_address, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_SUPERFRAME_ORDER ].addr = &FTDF_pib.superframeOrder, - .attributeDefs[ FTDF_PIB_SUPERFRAME_ORDER ].size = 0, - .attributeDefs[ FTDF_PIB_SUPERFRAME_ORDER ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SUPERFRAME_ORDER ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_SYNC_SYMBOL_OFFSET ].addr = &FTDF_pib.syncSymbolOffset, - .attributeDefs[ FTDF_PIB_SYNC_SYMBOL_OFFSET ].size = 0, - .attributeDefs[ FTDF_PIB_SYNC_SYMBOL_OFFSET ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SYNC_SYMBOL_OFFSET ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_TIMESTAMP_SUPPORTED ].addr = &FTDF_pib.timestampSupported, - .attributeDefs[ FTDF_PIB_TIMESTAMP_SUPPORTED ].size = 0, - .attributeDefs[ FTDF_PIB_TIMESTAMP_SUPPORTED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TIMESTAMP_SUPPORTED ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_TRANSACTION_PERSISTENCE_TIME ].addr = &FTDF_pib.transactionPersistenceTime, - .attributeDefs[ FTDF_PIB_TRANSACTION_PERSISTENCE_TIME ].size = - sizeof(FTDF_pib.transactionPersistenceTime), - .attributeDefs[ FTDF_PIB_TRANSACTION_PERSISTENCE_TIME ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TRANSACTION_PERSISTENCE_TIME ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_ENH_ACK_WAIT_DURATION ].addr = &FTDF_pib.enhAckWaitDuration, - .attributeDefs[ FTDF_PIB_ENH_ACK_WAIT_DURATION ].size = sizeof(FTDF_pib.enhAckWaitDuration), - .attributeDefs[ FTDF_PIB_ENH_ACK_WAIT_DURATION ].getFunc = FTDF_getEnhAckWaitDuration, - .attributeDefs[ FTDF_PIB_ENH_ACK_WAIT_DURATION ].setFunc = FTDF_setEnhAckWaitDuration, - .attributeDefs[ FTDF_PIB_IMPLICIT_BROADCAST ].addr = &FTDF_pib.implicitBroadcast, - .attributeDefs[ FTDF_PIB_IMPLICIT_BROADCAST ].size = sizeof(FTDF_pib.implicitBroadcast), - .attributeDefs[ FTDF_PIB_IMPLICIT_BROADCAST ].getFunc = FTDF_getImplicitBroadcast, - .attributeDefs[ FTDF_PIB_IMPLICIT_BROADCAST ].setFunc = FTDF_setImplicitBroadcast, - .attributeDefs[ FTDF_PIB_SIMPLE_ADDRESS ].addr = &FTDF_pib.simpleAddress, - .attributeDefs[ FTDF_PIB_SIMPLE_ADDRESS ].size = sizeof(FTDF_pib.simpleAddress), - .attributeDefs[ FTDF_PIB_SIMPLE_ADDRESS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SIMPLE_ADDRESS ].setFunc = FTDF_setSimpleAddress, - .attributeDefs[ FTDF_PIB_DISCONNECT_TIME ].addr = &FTDF_pib.disconnectTime, - .attributeDefs[ FTDF_PIB_DISCONNECT_TIME ].size = sizeof(FTDF_pib.disconnectTime), - .attributeDefs[ FTDF_PIB_DISCONNECT_TIME ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_DISCONNECT_TIME ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_JOIN_PRIORITY ].addr = &FTDF_pib.joinPriority, - .attributeDefs[ FTDF_PIB_JOIN_PRIORITY ].size = sizeof(FTDF_pib.joinPriority), - .attributeDefs[ FTDF_PIB_JOIN_PRIORITY ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_JOIN_PRIORITY ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_ASN ].addr = &FTDF_pib.ASN, - .attributeDefs[ FTDF_PIB_ASN ].size = sizeof(FTDF_pib.ASN), - .attributeDefs[ FTDF_PIB_ASN ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_ASN ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_NO_HL_BUFFERS ].addr = &FTDF_pib.noHLBuffers, - .attributeDefs[ FTDF_PIB_NO_HL_BUFFERS ].size = sizeof(FTDF_pib.noHLBuffers), - .attributeDefs[ FTDF_PIB_NO_HL_BUFFERS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_NO_HL_BUFFERS ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_SLOTFRAME_TABLE ].addr = &FTDF_pib.slotframeTable, - .attributeDefs[ FTDF_PIB_SLOTFRAME_TABLE ].size = 0, - .attributeDefs[ FTDF_PIB_SLOTFRAME_TABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SLOTFRAME_TABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_LINK_TABLE ].addr = &FTDF_pib.linkTable, - .attributeDefs[ FTDF_PIB_LINK_TABLE ].size = 0, - .attributeDefs[ FTDF_PIB_LINK_TABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LINK_TABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_TIMESLOT_TEMPLATE ].addr = &FTDF_pib.timeslotTemplate, - .attributeDefs[ FTDF_PIB_TIMESLOT_TEMPLATE ].size = sizeof(FTDF_pib.timeslotTemplate), - .attributeDefs[ FTDF_PIB_TIMESLOT_TEMPLATE ].getFunc = NULL, + .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].addr = &ftdf_pib.superframe_order, + .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].size = 0, + .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].getFunc = NULL, + .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].setFunc = NULL, + .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].addr = &ftdf_pib.sync_symbol_offset, + .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].size = 0, + .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].getFunc = NULL, + .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].setFunc = NULL, + .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].addr = &ftdf_pib.timestamp_supported, + .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].size = 0, + .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].getFunc = NULL, + .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].setFunc = NULL, + .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].addr = &ftdf_pib.transaction_persistence_time, + .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].size = sizeof(ftdf_pib.transaction_persistence_time), + .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].getFunc = NULL, + .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].setFunc = NULL, + .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].addr = &ftdf_pib.enh_ack_wait_duration, + .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].size = sizeof(ftdf_pib.enh_ack_wait_duration), + .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].getFunc = ftdf_get_enh_ack_wait_duration, + .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].setFunc = ftdf_set_enh_ack_wait_duration, + .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].addr = &ftdf_pib.implicit_broadcast, + .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].size = sizeof(ftdf_pib.implicit_broadcast), + .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].getFunc = ftdf_get_implicit_broadcast, + .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].setFunc = ftdf_set_implicit_broadcast, + .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].addr = &ftdf_pib.simple_address, + .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].size = sizeof(ftdf_pib.simple_address), + .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].getFunc = NULL, + .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].setFunc = ftdf_set_simple_address, + .attribute_defs[FTDF_PIB_DISCONNECT_TIME].addr = &ftdf_pib.disconnect_time, + .attribute_defs[FTDF_PIB_DISCONNECT_TIME].size = sizeof(ftdf_pib.disconnect_time), + .attribute_defs[FTDF_PIB_DISCONNECT_TIME].getFunc = NULL, + .attribute_defs[FTDF_PIB_DISCONNECT_TIME].setFunc = NULL, + .attribute_defs[FTDF_PIB_JOIN_PRIORITY].addr = &ftdf_pib.join_priority, + .attribute_defs[FTDF_PIB_JOIN_PRIORITY].size = sizeof(ftdf_pib.join_priority), + .attribute_defs[FTDF_PIB_JOIN_PRIORITY].getFunc = NULL, + .attribute_defs[FTDF_PIB_JOIN_PRIORITY].setFunc = NULL, + .attribute_defs[FTDF_PIB_ASN].addr = &ftdf_pib.asn, + .attribute_defs[FTDF_PIB_ASN].size = sizeof(ftdf_pib.asn), + .attribute_defs[FTDF_PIB_ASN].getFunc = NULL, + .attribute_defs[FTDF_PIB_ASN].setFunc = NULL, + .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].addr = &ftdf_pib.no_hl_buffers, + .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].size = sizeof(ftdf_pib.no_hl_buffers), + .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].getFunc = NULL, + .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].setFunc = NULL, + .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].addr = &ftdf_pib.slotframe_table, + .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].size = 0, + .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_LINK_TABLE].addr = &ftdf_pib.link_table, + .attribute_defs[FTDF_PIB_LINK_TABLE].size = 0, + .attribute_defs[FTDF_PIB_LINK_TABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_LINK_TABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].addr = &ftdf_pib.timeslot_template, + .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].size = sizeof(ftdf_pib.timeslot_template), + .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].getFunc = NULL, #ifdef FTDF_NO_TSCH - .attributeDefs[ FTDF_PIB_TIMESLOT_TEMPLATE ].setFunc = NULL, + .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].setFunc = NULL, #else - .attributeDefs[ FTDF_PIB_TIMESLOT_TEMPLATE ].setFunc = FTDF_setTimeslotTemplate, + .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].setFunc = ftdf_set_timeslot_template, #endif /* FTDF_NO_TSCH */ - .attributeDefs[ FTDF_PIB_HOPPINGSEQUENCE_ID ].addr = &FTDF_pib.HoppingSequenceId, - .attributeDefs[ FTDF_PIB_HOPPINGSEQUENCE_ID ].size = sizeof(FTDF_pib.HoppingSequenceId), - .attributeDefs[ FTDF_PIB_HOPPINGSEQUENCE_ID ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_HOPPINGSEQUENCE_ID ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CHANNEL_PAGE ].addr = &FTDF_pib.channelPage, - .attributeDefs[ FTDF_PIB_CHANNEL_PAGE ].size = sizeof(FTDF_pib.channelPage), - .attributeDefs[ FTDF_PIB_CHANNEL_PAGE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CHANNEL_PAGE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_NUMBER_OF_CHANNELS ].addr = &FTDF_pib.numberOfChannels, - .attributeDefs[ FTDF_PIB_NUMBER_OF_CHANNELS ].size = sizeof(FTDF_pib.numberOfChannels), - .attributeDefs[ FTDF_PIB_NUMBER_OF_CHANNELS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_NUMBER_OF_CHANNELS ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_PHY_CONFIGURATION ].addr = &FTDF_pib.phyConfiguration, - .attributeDefs[ FTDF_PIB_PHY_CONFIGURATION ].size = sizeof(FTDF_pib.phyConfiguration), - .attributeDefs[ FTDF_PIB_PHY_CONFIGURATION ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_PHY_CONFIGURATION ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_EXTENTED_BITMAP ].addr = &FTDF_pib.extendedBitmap, - .attributeDefs[ FTDF_PIB_EXTENTED_BITMAP ].size = sizeof(FTDF_pib.extendedBitmap), - .attributeDefs[ FTDF_PIB_EXTENTED_BITMAP ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_EXTENTED_BITMAP ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LENGTH ].addr = &FTDF_pib.hoppingSequenceLength, - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LENGTH ].size = sizeof(FTDF_pib.hoppingSequenceLength), - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LENGTH ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LENGTH ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LIST ].addr = FTDF_pib.hoppingSequenceList, - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LIST ].size = sizeof(FTDF_pib.hoppingSequenceList), - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LIST ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_HOPPING_SEQUENCE_LIST ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CURRENT_HOP ].addr = &FTDF_pib.currentHop, - .attributeDefs[ FTDF_PIB_CURRENT_HOP ].size = sizeof(FTDF_pib.currentHop), - .attributeDefs[ FTDF_PIB_CURRENT_HOP ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CURRENT_HOP ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_DWELL_TIME ].addr = &FTDF_pib.dwellTime, - .attributeDefs[ FTDF_PIB_DWELL_TIME ].size = sizeof(FTDF_pib.dwellTime), - .attributeDefs[ FTDF_PIB_DWELL_TIME ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_DWELL_TIME ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_PERIOD ].addr = &FTDF_pib.CSLPeriod, - .attributeDefs[ FTDF_PIB_CSL_PERIOD ].size = sizeof(FTDF_pib.CSLPeriod), - .attributeDefs[ FTDF_PIB_CSL_PERIOD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_PERIOD ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_MAX_PERIOD ].addr = &FTDF_pib.CSLMaxPeriod, - .attributeDefs[ FTDF_PIB_CSL_MAX_PERIOD ].size = sizeof(FTDF_pib.CSLMaxPeriod), - .attributeDefs[ FTDF_PIB_CSL_MAX_PERIOD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_MAX_PERIOD ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_CHANNEL_MASK ].addr = &FTDF_pib.CSLChannelMask, - .attributeDefs[ FTDF_PIB_CSL_CHANNEL_MASK ].size = sizeof(FTDF_pib.CSLChannelMask), - .attributeDefs[ FTDF_PIB_CSL_CHANNEL_MASK ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_CHANNEL_MASK ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_FRAME_PENDING_WAIT_T ].addr = &FTDF_pib.CSLFramePendingWaitT, - .attributeDefs[ FTDF_PIB_CSL_FRAME_PENDING_WAIT_T ].size = sizeof(FTDF_pib.CSLFramePendingWaitT), + .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].addr = &ftdf_pib.hopping_sequence_id, + .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].size = sizeof(ftdf_pib.hopping_sequence_id), + .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].getFunc = NULL, + .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].setFunc = NULL, + .attribute_defs[FTDF_PIB_CHANNEL_PAGE].addr = &ftdf_pib.channel_page, + .attribute_defs[FTDF_PIB_CHANNEL_PAGE].size = sizeof(ftdf_pib.channel_page), + .attribute_defs[FTDF_PIB_CHANNEL_PAGE].getFunc = NULL, + .attribute_defs[FTDF_PIB_CHANNEL_PAGE].setFunc = NULL, + .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].addr = &ftdf_pib.number_of_channels, + .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].size = sizeof(ftdf_pib.number_of_channels), + .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].getFunc = NULL, + .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].setFunc = NULL, + .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].addr = &ftdf_pib.phy_configuration, + .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].size = sizeof(ftdf_pib.phy_configuration), + .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].getFunc = NULL, + .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].setFunc = NULL, + .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].addr = &ftdf_pib.extended_bitmap, + .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].size = sizeof(ftdf_pib.extended_bitmap), + .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].getFunc = NULL, + .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].setFunc = NULL, + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].addr = &ftdf_pib.hopping_sequence_length, + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].size = sizeof(ftdf_pib.hopping_sequence_length), + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].getFunc = NULL, + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].setFunc = NULL, + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].addr = ftdf_pib.hopping_sequence_list, + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].size = sizeof(ftdf_pib.hopping_sequence_list), + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].getFunc = NULL, + .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].setFunc = NULL, + .attribute_defs[FTDF_PIB_CURRENT_HOP].addr = &ftdf_pib.current_hop, + .attribute_defs[FTDF_PIB_CURRENT_HOP].size = sizeof(ftdf_pib.current_hop), + .attribute_defs[FTDF_PIB_CURRENT_HOP].getFunc = NULL, + .attribute_defs[FTDF_PIB_CURRENT_HOP].setFunc = NULL, + .attribute_defs[FTDF_PIB_DWELL_TIME].addr = &ftdf_pib.dwell_time, + .attribute_defs[FTDF_PIB_DWELL_TIME].size = sizeof(ftdf_pib.dwell_time), + .attribute_defs[FTDF_PIB_DWELL_TIME].getFunc = NULL, + .attribute_defs[FTDF_PIB_DWELL_TIME].setFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_PERIOD].addr = &ftdf_pib.csl_period, + .attribute_defs[FTDF_PIB_CSL_PERIOD].size = sizeof(ftdf_pib.csl_period), + .attribute_defs[FTDF_PIB_CSL_PERIOD].getFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_PERIOD].setFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].addr = &ftdf_pib.csl_max_period, + .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].size = sizeof(ftdf_pib.csl_max_period), + .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].getFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].setFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].addr = &ftdf_pib.csl_channel_mask, + .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].size = sizeof(ftdf_pib.csl_channel_mask), + .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].getFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].setFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].addr = &ftdf_pib.csl_frame_pending_wait, + .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].size = sizeof(ftdf_pib.csl_frame_pending_wait), #ifdef FTDF_NO_CSL - .attributeDefs[ FTDF_PIB_CSL_FRAME_PENDING_WAIT_T ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_FRAME_PENDING_WAIT_T ].setFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].getFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].setFunc = NULL, #else - .attributeDefs[ FTDF_PIB_CSL_FRAME_PENDING_WAIT_T ].getFunc = FTDF_getCslFramePendingWaitT, - .attributeDefs[ FTDF_PIB_CSL_FRAME_PENDING_WAIT_T ].setFunc = FTDF_setCslFramePendingWaitT, + .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].getFunc = ftdf_get_csl_frame_pending_wait, + .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].setFunc = ftdf_set_csl_frame_pending_wait, #endif /* FTDF_NO_CSL */ - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED ].addr = &FTDF_pib.lowEnergySuperframeSupported, - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED ].size = - sizeof(FTDF_pib.lowEnergySuperframeSupported), - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL ].addr = &FTDF_pib.lowEnergySuperframeSyncInterval, - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL ].size = - sizeof(FTDF_pib.lowEnergySuperframeSyncInterval), - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL ].setFunc = NULL, + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].addr = &ftdf_pib.low_energy_superframe_supported, + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].size = sizeof(ftdf_pib.low_energy_superframe_supported), + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].getFunc = NULL, + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].setFunc = NULL, + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].addr = &ftdf_pib.low_energy_superframe_sync_interval, + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].size = sizeof(ftdf_pib.low_energy_superframe_sync_interval), + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].getFunc = NULL, + .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_PERFORMANCE_METRICS ].addr = &FTDF_pib.performanceMetrics, - .attributeDefs[ FTDF_PIB_PERFORMANCE_METRICS ].size = sizeof(FTDF_pib.performanceMetrics), - .attributeDefs[ FTDF_PIB_PERFORMANCE_METRICS ].getFunc = FTDF_getLmacPmData, - .attributeDefs[ FTDF_PIB_PERFORMANCE_METRICS ].setFunc = NULL, + .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].addr = &ftdf_pib.performance_metrics, + .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].size = sizeof(ftdf_pib.performance_metrics), + .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].getFunc = ftdf_get_lmac_pm_data, + .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].setFunc = NULL, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_USE_ENHANCED_BEACON ].addr = &FTDF_pib.useEnhancedBecaon, - .attributeDefs[ FTDF_PIB_USE_ENHANCED_BEACON ].size = sizeof(FTDF_pib.useEnhancedBecaon), - .attributeDefs[ FTDF_PIB_USE_ENHANCED_BEACON ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_USE_ENHANCED_BEACON ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_EB_IE_LIST ].addr = &FTDF_pib.EBIEList, - .attributeDefs[ FTDF_PIB_EB_IE_LIST ].size = sizeof(FTDF_pib.EBIEList), - .attributeDefs[ FTDF_PIB_EB_IE_LIST ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_EB_IE_LIST ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_EB_FILTERING_ENABLED ].addr = &FTDF_pib.EBFilteringEnabled, - .attributeDefs[ FTDF_PIB_EB_FILTERING_ENABLED ].size = sizeof(FTDF_pib.EBFilteringEnabled), - .attributeDefs[ FTDF_PIB_EB_FILTERING_ENABLED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_EB_FILTERING_ENABLED ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_EBSN ].addr = &FTDF_pib.EBSN, - .attributeDefs[ FTDF_PIB_EBSN ].size = sizeof(FTDF_pib.EBSN), - .attributeDefs[ FTDF_PIB_EBSN ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_EBSN ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_EB_AUTO_SA ].addr = &FTDF_pib.EBAutoSA, - .attributeDefs[ FTDF_PIB_EB_AUTO_SA ].size = sizeof(FTDF_pib.EBAutoSA), - .attributeDefs[ FTDF_PIB_EB_AUTO_SA ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_EB_AUTO_SA ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_EACK_IE_LIST ].addr = &FTDF_pib.EAckIEList, - .attributeDefs[ FTDF_PIB_EACK_IE_LIST ].size = sizeof(FTDF_pib.EAckIEList), - .attributeDefs[ FTDF_PIB_EACK_IE_LIST ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_EACK_IE_LIST ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_KEY_TABLE ].addr = &FTDF_pib.keyTable, - .attributeDefs[ FTDF_PIB_KEY_TABLE ].size = sizeof(FTDF_pib.keyTable), - .attributeDefs[ FTDF_PIB_KEY_TABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_KEY_TABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_DEVICE_TABLE ].addr = &FTDF_pib.deviceTable, - .attributeDefs[ FTDF_PIB_DEVICE_TABLE ].size = sizeof(FTDF_pib.deviceTable), - .attributeDefs[ FTDF_PIB_DEVICE_TABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_DEVICE_TABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_SECURITY_LEVEL_TABLE ].addr = &FTDF_pib.securityLevelTable, - .attributeDefs[ FTDF_PIB_SECURITY_LEVEL_TABLE ].size = sizeof(FTDF_pib.securityLevelTable), - .attributeDefs[ FTDF_PIB_SECURITY_LEVEL_TABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SECURITY_LEVEL_TABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_FRAME_COUNTER ].addr = &FTDF_pib.frameCounter, - .attributeDefs[ FTDF_PIB_FRAME_COUNTER ].size = sizeof(FTDF_pib.frameCounter), - .attributeDefs[ FTDF_PIB_FRAME_COUNTER ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_FRAME_COUNTER ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_SECURITY_LEVEL ].addr = &FTDF_pib.mtDataSecurityLevel, - .attributeDefs[ FTDF_PIB_MT_DATA_SECURITY_LEVEL ].size = - sizeof(FTDF_pib.mtDataSecurityLevel), - .attributeDefs[ FTDF_PIB_MT_DATA_SECURITY_LEVEL ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_SECURITY_LEVEL ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_ID_MODE ].addr = &FTDF_pib.mtDataKeyIdMode, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_ID_MODE ].size = sizeof(FTDF_pib.mtDataKeyIdMode), - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_ID_MODE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_ID_MODE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_SOURCE ].addr = &FTDF_pib.mtDataKeySource, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_SOURCE ].size = sizeof(FTDF_pib.mtDataKeySource), - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_SOURCE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_SOURCE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_INDEX ].addr = &FTDF_pib.mtDataKeyIndex, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_INDEX ].size = sizeof(FTDF_pib.mtDataKeyIndex), - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_INDEX ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MT_DATA_KEY_INDEX ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_DEFAULT_KEY_SOURCE ].addr = &FTDF_pib.defaultKeySource, - .attributeDefs[ FTDF_PIB_DEFAULT_KEY_SOURCE ].size = sizeof(FTDF_pib.defaultKeySource), - .attributeDefs[ FTDF_PIB_DEFAULT_KEY_SOURCE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_DEFAULT_KEY_SOURCE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS ].addr = &FTDF_pib.PANCoordExtAddress, - .attributeDefs[ FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS ].size = sizeof(FTDF_pib.PANCoordExtAddress), - .attributeDefs[ FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_PAN_COORD_SHORT_ADDRESS ].addr = &FTDF_pib.PANCoordShortAddress, - .attributeDefs[ FTDF_PIB_PAN_COORD_SHORT_ADDRESS ].size = sizeof(FTDF_pib.PANCoordShortAddress), - .attributeDefs[ FTDF_PIB_PAN_COORD_SHORT_ADDRESS ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_PAN_COORD_SHORT_ADDRESS ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_FRAME_COUNTER_MODE ].addr = &FTDF_pib.frameCounterMode, - .attributeDefs[ FTDF_PIB_FRAME_COUNTER_MODE ].size = sizeof(FTDF_pib.frameCounterMode), - .attributeDefs[ FTDF_PIB_FRAME_COUNTER_MODE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_FRAME_COUNTER_MODE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_SYNC_TX_MARGIN ].addr = &FTDF_pib.CSLSyncTxMargin, - .attributeDefs[ FTDF_PIB_CSL_SYNC_TX_MARGIN ].size = sizeof(FTDF_pib.CSLSyncTxMargin), - .attributeDefs[ FTDF_PIB_CSL_SYNC_TX_MARGIN ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_SYNC_TX_MARGIN ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO ].addr = &FTDF_pib.CSLMaxAgeRemoteInfo, - .attributeDefs[ FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO ].size = sizeof(FTDF_pib.CSLMaxAgeRemoteInfo), - .attributeDefs[ FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_TSCH_ENABLED ].addr = &FTDF_pib.tschEnabled, - .attributeDefs[ FTDF_PIB_TSCH_ENABLED ].size = 0, - .attributeDefs[ FTDF_PIB_TSCH_ENABLED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TSCH_ENABLED ].setFunc = NULL, + .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].addr = &ftdf_pib.use_enhanced_becaon, + .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].size = sizeof(ftdf_pib.use_enhanced_becaon), + .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].getFunc = NULL, + .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].setFunc = NULL, + .attribute_defs[FTDF_PIB_EB_IE_LIST].addr = &ftdf_pib.eb_ie_list, + .attribute_defs[FTDF_PIB_EB_IE_LIST].size = sizeof(ftdf_pib.eb_ie_list), + .attribute_defs[FTDF_PIB_EB_IE_LIST].getFunc = NULL, + .attribute_defs[FTDF_PIB_EB_IE_LIST].setFunc = NULL, + .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].addr = &ftdf_pib.eb_filtering_enabled, + .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].size = sizeof(ftdf_pib.eb_filtering_enabled), + .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].getFunc = NULL, + .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].setFunc = NULL, + .attribute_defs[FTDF_PIB_EBSN].addr = &ftdf_pib.eb_sn, + .attribute_defs[FTDF_PIB_EBSN].size = sizeof(ftdf_pib.eb_sn), + .attribute_defs[FTDF_PIB_EBSN].getFunc = NULL, + .attribute_defs[FTDF_PIB_EBSN].setFunc = NULL, + .attribute_defs[FTDF_PIB_EB_AUTO_SA].addr = &ftdf_pib.eb_auto_sa, + .attribute_defs[FTDF_PIB_EB_AUTO_SA].size = sizeof(ftdf_pib.eb_auto_sa), + .attribute_defs[FTDF_PIB_EB_AUTO_SA].getFunc = NULL, + .attribute_defs[FTDF_PIB_EB_AUTO_SA].setFunc = NULL, + .attribute_defs[FTDF_PIB_EACK_IE_LIST].addr = &ftdf_pib.e_ack_ie_list, + .attribute_defs[FTDF_PIB_EACK_IE_LIST].size = sizeof(ftdf_pib.e_ack_ie_list), + .attribute_defs[FTDF_PIB_EACK_IE_LIST].getFunc = NULL, + .attribute_defs[FTDF_PIB_EACK_IE_LIST].setFunc = NULL, + .attribute_defs[FTDF_PIB_KEY_TABLE].addr = &ftdf_pib.key_table, + .attribute_defs[FTDF_PIB_KEY_TABLE].size = sizeof(ftdf_pib.key_table), + .attribute_defs[FTDF_PIB_KEY_TABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_KEY_TABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_DEVICE_TABLE].addr = &ftdf_pib.device_table, + .attribute_defs[FTDF_PIB_DEVICE_TABLE].size = sizeof(ftdf_pib.device_table), + .attribute_defs[FTDF_PIB_DEVICE_TABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_DEVICE_TABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].addr = &ftdf_pib.security_level_table, + .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].size = sizeof(ftdf_pib.security_level_table), + .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_FRAME_COUNTER].addr = &ftdf_pib.frame_counter, + .attribute_defs[FTDF_PIB_FRAME_COUNTER].size = sizeof(ftdf_pib.frame_counter), + .attribute_defs[FTDF_PIB_FRAME_COUNTER].getFunc = NULL, + .attribute_defs[FTDF_PIB_FRAME_COUNTER].setFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].addr = &ftdf_pib.mt_data_security_level, + .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].size = sizeof(ftdf_pib.mt_data_security_level), + .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].getFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].setFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].addr = &ftdf_pib.mt_data_key_id_mode, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].size = sizeof(ftdf_pib.mt_data_key_id_mode), + .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].getFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].setFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].addr = &ftdf_pib.mt_data_key_source, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].size = sizeof(ftdf_pib.mt_data_key_source), + .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].getFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].setFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].addr = &ftdf_pib.mt_data_key_index, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].size = sizeof(ftdf_pib.mt_data_key_index), + .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].getFunc = NULL, + .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].setFunc = NULL, + .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].addr = &ftdf_pib.default_key_source, + .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].size = sizeof(ftdf_pib.default_key_source), + .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].getFunc = NULL, + .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].setFunc = NULL, + .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].addr = &ftdf_pib.pan_coord_ext_address, + .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].size = sizeof(ftdf_pib.pan_coord_ext_address), + .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].getFunc = NULL, + .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].setFunc = NULL, + .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].addr = &ftdf_pib.pan_coord_short_address, + .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].size = sizeof(ftdf_pib.pan_coord_short_address), + .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].getFunc = NULL, + .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].setFunc = NULL, + .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].addr = &ftdf_pib.frame_counter_mode, + .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].size = sizeof(ftdf_pib.frame_counter_mode), + .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].getFunc = NULL, + .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].setFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].addr = &ftdf_pib.csl_sync_tx_margin, + .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].size = sizeof(ftdf_pib.csl_sync_tx_margin), + .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].getFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].setFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].addr = &ftdf_pib.csl_max_age_remote_info, + .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].size = sizeof(ftdf_pib.csl_max_age_remote_info), + .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].getFunc = NULL, + .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].setFunc = NULL, + .attribute_defs[FTDF_PIB_TSCH_ENABLED].addr = &ftdf_pib.tsch_enabled, + .attribute_defs[FTDF_PIB_TSCH_ENABLED].size = 0, + .attribute_defs[FTDF_PIB_TSCH_ENABLED].getFunc = NULL, + .attribute_defs[FTDF_PIB_TSCH_ENABLED].setFunc = NULL, #ifdef FTDF_NO_CSL - .attributeDefs[ FTDF_PIB_LE_ENABLED ].addr = &FTDF_pib.leEnabled, - .attributeDefs[ FTDF_PIB_LE_ENABLED ].size = 0, - .attributeDefs[ FTDF_PIB_LE_ENABLED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LE_ENABLED ].setFunc = NULL, + .attribute_defs[FTDF_PIB_LE_ENABLED].addr = &ftdf_pib.le_enabled, + .attribute_defs[FTDF_PIB_LE_ENABLED].size = 0, + .attribute_defs[FTDF_PIB_LE_ENABLED].getFunc = NULL, + .attribute_defs[FTDF_PIB_LE_ENABLED].setFunc = NULL, #else - .attributeDefs[ FTDF_PIB_LE_ENABLED ].addr = &FTDF_pib.leEnabled, - .attributeDefs[ FTDF_PIB_LE_ENABLED ].size = sizeof(FTDF_pib.leEnabled), - .attributeDefs[ FTDF_PIB_LE_ENABLED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LE_ENABLED ].setFunc = FTDF_setLeEnabled, + .attribute_defs[FTDF_PIB_LE_ENABLED].addr = &ftdf_pib.le_enabled, + .attribute_defs[FTDF_PIB_LE_ENABLED].size = sizeof(ftdf_pib.le_enabled), + .attribute_defs[FTDF_PIB_LE_ENABLED].getFunc = NULL, + .attribute_defs[FTDF_PIB_LE_ENABLED].setFunc = ftdf_set_le_enabled, #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_CURRENT_CHANNEL ].addr = &FTDF_pib.currentChannel, - .attributeDefs[ FTDF_PIB_CURRENT_CHANNEL ].size = sizeof(FTDF_pib.currentChannel), - .attributeDefs[ FTDF_PIB_CURRENT_CHANNEL ].getFunc = FTDF_getCurrentChannel, - .attributeDefs[ FTDF_PIB_CURRENT_CHANNEL ].setFunc = FTDF_setCurrentChannel, + .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].addr = &ftdf_pib.current_channel, + .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].size = sizeof(ftdf_pib.current_channel), + .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].getFunc = ftdf_get_current_channel, + .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].setFunc = ftdf_set_current_channel, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_CHANNELS_SUPPORTED ].addr = (void *) &channelsSupported, - .attributeDefs[ FTDF_PIB_CHANNELS_SUPPORTED ].size = 0, - .attributeDefs[ FTDF_PIB_CHANNELS_SUPPORTED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CHANNELS_SUPPORTED ].setFunc = NULL, + .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].addr = (void*)&channels_supported, + .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].size = 0, + .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].getFunc = NULL, + .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_TX_POWER_TOLERANCE ].addr = &FTDF_pib.TXPowerTolerance, - .attributeDefs[ FTDF_PIB_TX_POWER_TOLERANCE ].size = sizeof(FTDF_pib.TXPowerTolerance), - .attributeDefs[ FTDF_PIB_TX_POWER_TOLERANCE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TX_POWER_TOLERANCE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_TX_POWER ].addr = &FTDF_pib.TXPower, - .attributeDefs[ FTDF_PIB_TX_POWER ].size = sizeof(FTDF_pib.TXPower), - .attributeDefs[ FTDF_PIB_TX_POWER ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TX_POWER ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_CCA_MODE ].addr = &FTDF_pib.CCAMode, - .attributeDefs[ FTDF_PIB_CCA_MODE ].size = sizeof(FTDF_pib.CCAMode), - .attributeDefs[ FTDF_PIB_CCA_MODE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CCA_MODE ].setFunc = FTDF_setTXPower, + .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].addr = &ftdf_pib.tx_power_tolerance, + .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].size = sizeof(ftdf_pib.tx_power_tolerance), + .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].getFunc = NULL, + .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].setFunc = NULL, + .attribute_defs[FTDF_PIB_TX_POWER].addr = &ftdf_pib.tx_power, + .attribute_defs[FTDF_PIB_TX_POWER].size = sizeof(ftdf_pib.tx_power), + .attribute_defs[FTDF_PIB_TX_POWER].getFunc = NULL, + .attribute_defs[FTDF_PIB_TX_POWER].setFunc = NULL, + .attribute_defs[FTDF_PIB_CCA_MODE].addr = &ftdf_pib.cca_mode, + .attribute_defs[FTDF_PIB_CCA_MODE].size = sizeof(ftdf_pib.cca_mode), + .attribute_defs[FTDF_PIB_CCA_MODE].getFunc = NULL, + .attribute_defs[FTDF_PIB_CCA_MODE].setFunc = NULL, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_CURRENT_PAGE ].addr = &FTDF_pib.currentPage, - .attributeDefs[ FTDF_PIB_CURRENT_PAGE ].size = 0, - .attributeDefs[ FTDF_PIB_CURRENT_PAGE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CURRENT_PAGE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_MAX_FRAME_DURATION ].addr = &FTDF_pib.maxFrameDuration, - .attributeDefs[ FTDF_PIB_MAX_FRAME_DURATION ].size = 0, - .attributeDefs[ FTDF_PIB_MAX_FRAME_DURATION ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_MAX_FRAME_DURATION ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_SHR_DURATION ].addr = &FTDF_pib.SHRDuration, - .attributeDefs[ FTDF_PIB_SHR_DURATION ].size = 0, - .attributeDefs[ FTDF_PIB_SHR_DURATION ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_SHR_DURATION ].setFunc = NULL, + .attribute_defs[FTDF_PIB_CURRENT_PAGE].addr = &ftdf_pib.current_page, + .attribute_defs[FTDF_PIB_CURRENT_PAGE].size = 0, + .attribute_defs[FTDF_PIB_CURRENT_PAGE].getFunc = NULL, + .attribute_defs[FTDF_PIB_CURRENT_PAGE].setFunc = NULL, + .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].addr = &ftdf_pib.max_frame_duration, + .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].size = 0, + .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].getFunc = NULL, + .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].setFunc = NULL, + .attribute_defs[FTDF_PIB_SHR_DURATION].addr = &ftdf_pib.shr_duration, + .attribute_defs[FTDF_PIB_SHR_DURATION].size = 0, + .attribute_defs[FTDF_PIB_SHR_DURATION].getFunc = NULL, + .attribute_defs[FTDF_PIB_SHR_DURATION].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_TRAFFIC_COUNTERS ].addr = &FTDF_pib.trafficCounters, - .attributeDefs[ FTDF_PIB_TRAFFIC_COUNTERS ].size = 0, - .attributeDefs[ FTDF_PIB_TRAFFIC_COUNTERS ].getFunc = FTDF_getLmacTrafficCounters, - .attributeDefs[ FTDF_PIB_TRAFFIC_COUNTERS ].setFunc = NULL, + .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].addr = &ftdf_pib.traffic_counters, + .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].size = 0, + .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].getFunc = ftdf_get_lmac_traffic_counters, + .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].setFunc = NULL, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_LE_CAPABLE ].addr = &FTDF_pib.LECapable, - .attributeDefs[ FTDF_PIB_LE_CAPABLE ].size = 0, - .attributeDefs[ FTDF_PIB_LE_CAPABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LE_CAPABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_LL_CAPABLE ].addr = &FTDF_pib.LLCapable, - .attributeDefs[ FTDF_PIB_LL_CAPABLE ].size = 0, - .attributeDefs[ FTDF_PIB_LL_CAPABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_LL_CAPABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_DSME_CAPABLE ].addr = &FTDF_pib.DSMECapable, - .attributeDefs[ FTDF_PIB_DSME_CAPABLE ].size = 0, - .attributeDefs[ FTDF_PIB_DSME_CAPABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_DSME_CAPABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_RFID_CAPABLE ].addr = &FTDF_pib.RFIDCapable, - .attributeDefs[ FTDF_PIB_RFID_CAPABLE ].size = 0, - .attributeDefs[ FTDF_PIB_RFID_CAPABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_RFID_CAPABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_AMCA_CAPABLE ].addr = &FTDF_pib.AMCACapable, - .attributeDefs[ FTDF_PIB_AMCA_CAPABLE ].size = 0, - .attributeDefs[ FTDF_PIB_AMCA_CAPABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_AMCA_CAPABLE ].setFunc = NULL, + .attribute_defs[FTDF_PIB_LE_CAPABLE].addr = &ftdf_pib.le_capable, + .attribute_defs[FTDF_PIB_LE_CAPABLE].size = 0, + .attribute_defs[FTDF_PIB_LE_CAPABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_LE_CAPABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_LL_CAPABLE].addr = &ftdf_pib.ll_capable, + .attribute_defs[FTDF_PIB_LL_CAPABLE].size = 0, + .attribute_defs[FTDF_PIB_LL_CAPABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_LL_CAPABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_DSME_CAPABLE].addr = &ftdf_pib.dsme_capable, + .attribute_defs[FTDF_PIB_DSME_CAPABLE].size = 0, + .attribute_defs[FTDF_PIB_DSME_CAPABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_DSME_CAPABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_RFID_CAPABLE].addr = &ftdf_pib.rfid_capable, + .attribute_defs[FTDF_PIB_RFID_CAPABLE].size = 0, + .attribute_defs[FTDF_PIB_RFID_CAPABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_RFID_CAPABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_AMCA_CAPABLE].addr = &ftdf_pib.amca_capable, + .attribute_defs[FTDF_PIB_AMCA_CAPABLE].size = 0, + .attribute_defs[FTDF_PIB_AMCA_CAPABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_AMCA_CAPABLE].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_METRICS_CAPABLE ].addr = &FTDF_pib.metricsCapable, - .attributeDefs[ FTDF_PIB_METRICS_CAPABLE ].size = 0, - .attributeDefs[ FTDF_PIB_METRICS_CAPABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_METRICS_CAPABLE ].setFunc = NULL, + .attribute_defs[FTDF_PIB_METRICS_CAPABLE].addr = &ftdf_pib.metrics_capable, + .attribute_defs[FTDF_PIB_METRICS_CAPABLE].size = 0, + .attribute_defs[FTDF_PIB_METRICS_CAPABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_METRICS_CAPABLE].setFunc = NULL, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_RANGING_SUPPORTED ].addr = &FTDF_pib.rangingSupported, - .attributeDefs[ FTDF_PIB_RANGING_SUPPORTED ].size = 0, - .attributeDefs[ FTDF_PIB_RANGING_SUPPORTED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_RANGING_SUPPORTED ].setFunc = NULL, + .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].addr = &ftdf_pib.ranging_supported, + .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].size = 0, + .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].getFunc = NULL, + .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].setFunc = NULL, #endif /* !FTDF_LITE */ - .attributeDefs[ FTDF_PIB_KEEP_PHY_ENABLED ].addr = &FTDF_pib.keepPhyEnabled, - .attributeDefs[ FTDF_PIB_KEEP_PHY_ENABLED ].size = sizeof(FTDF_pib.keepPhyEnabled), - .attributeDefs[ FTDF_PIB_KEEP_PHY_ENABLED ].getFunc = FTDF_getKeepPhyEnabled, - .attributeDefs[ FTDF_PIB_KEEP_PHY_ENABLED ].setFunc = FTDF_setKeepPhyEnabled, - .attributeDefs[ FTDF_PIB_METRICS_ENABLED ].addr = &FTDF_pib.metricsEnabled, - .attributeDefs[ FTDF_PIB_METRICS_ENABLED ].size = sizeof(FTDF_pib.metricsEnabled), - .attributeDefs[ FTDF_PIB_METRICS_ENABLED ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_METRICS_ENABLED ].setFunc = NULL, + .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].addr = &ftdf_pib.keep_phy_enabled, + .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].size = sizeof(ftdf_pib.keep_phy_enabled), + .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].getFunc = ftdf_get_keep_phy_enabled, + .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].setFunc = ftdf_set_keep_phy_enabled, + .attribute_defs[FTDF_PIB_METRICS_ENABLED].addr = &ftdf_pib.metrics_enabled, + .attribute_defs[FTDF_PIB_METRICS_ENABLED].size = sizeof(ftdf_pib.metrics_enabled), + .attribute_defs[FTDF_PIB_METRICS_ENABLED].getFunc = NULL, + .attribute_defs[FTDF_PIB_METRICS_ENABLED].setFunc = NULL, #ifndef FTDF_LITE - .attributeDefs[ FTDF_PIB_BEACON_AUTO_RESPOND ].addr = &FTDF_pib.beaconAutoRespond, - .attributeDefs[ FTDF_PIB_BEACON_AUTO_RESPOND ].size = sizeof(FTDF_pib.beaconAutoRespond), - .attributeDefs[ FTDF_PIB_BEACON_AUTO_RESPOND ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_BEACON_AUTO_RESPOND ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_TSCH_CAPABLE ].addr = &FTDF_pib.tschCapable, - .attributeDefs[ FTDF_PIB_TSCH_CAPABLE ].size = 0, - .attributeDefs[ FTDF_PIB_TSCH_CAPABLE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TSCH_CAPABLE ].setFunc = NULL, - .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].addr = &FTDF_pib.tsSyncCorrectThreshold, - .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].size = sizeof(FTDF_pib.tsSyncCorrectThreshold), - .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].setFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].addr = &ftdf_pib.beacon_auto_respond, + .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].size = sizeof(ftdf_pib.beacon_auto_respond), + .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].getFunc = NULL, + .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].setFunc = NULL, + .attribute_defs[FTDF_PIB_TSCH_CAPABLE].addr = &ftdf_pib.tsch_capable, + .attribute_defs[FTDF_PIB_TSCH_CAPABLE].size = 0, + .attribute_defs[FTDF_PIB_TSCH_CAPABLE].getFunc = NULL, + .attribute_defs[FTDF_PIB_TSCH_CAPABLE].setFunc = NULL, + .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].addr = &ftdf_pib.ts_sync_correct_threshold, + .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].size = sizeof(ftdf_pib.ts_sync_correct_threshold), + .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].getFunc = NULL, + .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].setFunc = NULL, #endif /* !FTDF_LITE */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].addr = &FTDF_pib.boIrqThreshold, - .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].size = sizeof(FTDF_pib.boIrqThreshold), - .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].getFunc = FTDF_getBoIrqThreshold, - .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].setFunc = FTDF_setBoIrqThreshold, - .attributeDefs[ FTDF_PIB_PTI_CONFIG ].addr = &FTDF_pib.ptiConfig, - .attributeDefs[ FTDF_PIB_PTI_CONFIG ].size = sizeof(FTDF_pib.ptiConfig), - .attributeDefs[ FTDF_PIB_PTI_CONFIG ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_PTI_CONFIG ].setFunc = FTDF_setPtiConfig, -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].addr = &ftdf_pib.bo_irq_threshold, + .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].size = sizeof(ftdf_pib.bo_irq_threshold), + .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].getFunc = ftdf_get_bo_irq_threshold, + .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].setFunc = ftdf_set_bo_irq_threshold, + .attribute_defs[FTDF_PIB_PTI_CONFIG].addr = &ftdf_pib.pti_config, + .attribute_defs[FTDF_PIB_PTI_CONFIG].size = sizeof(ftdf_pib.pti_config), + .attribute_defs[FTDF_PIB_PTI_CONFIG].getFunc = NULL, + .attribute_defs[FTDF_PIB_PTI_CONFIG].setFunc = ftdf_set_pti_config, + .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].addr = &ftdf_pib.link_quality_mode, + .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].size = sizeof(ftdf_pib.link_quality_mode), + .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].getFunc = NULL, + .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].setFunc = NULL, }; -FTDF_Boolean FTDF_transparentMode __attribute__((section(".retention"))); -FTDF_Bitmap32 FTDF_transparentModeOptions __attribute__((section(".retention"))); +ftdf_boolean_t ftdf_transparent_mode __attribute__ ((section(".retention"))); +ftdf_bitmap32_t ftdf_transparent_mode_options __attribute__ ((section(".retention"))); #if FTDF_DBG_BUS_ENABLE -FTDF_DbgMode FTDF_dbgMode __attribute__((section(".retention"))); +ftdf_dbg_mode_t ftdf_dbg_mode __attribute__ ((section(".retention"))); #endif #if dg_configUSE_FTDF_DDPHY == 1 -uint16_t FTDF_ddphyCcaReg __attribute__((section(".retention"))); +uint16_t ftdf_ddphy_cca_reg __attribute__ ((section(".retention"))); #endif #ifndef FTDF_LITE -FTDF_Buffer FTDF_reqBuffers[ FTDF_NR_OF_REQ_BUFFERS ] __attribute__((section(".retention"))); -FTDF_Queue FTDF_reqQueue __attribute__((section(".retention"))); -FTDF_Queue FTDF_freeQueue __attribute__((section(".retention"))); -FTDF_Pending FTDF_txPendingList[ FTDF_NR_OF_REQ_BUFFERS ] __attribute__((section(".retention"))); -FTDF_PendingTL FTDF_txPendingTimerList[ FTDF_NR_OF_REQ_BUFFERS ] __attribute__((section(".retention"))); -FTDF_PendingTL *FTDF_txPendingTimerHead __attribute__((section(".retention"))); -FTDF_Time FTDF_txPendingTimerLT __attribute__((section(".retention"))); -FTDF_Time FTDF_txPendingTimerTime __attribute__((section(".retention"))); +ftdf_buffer_t ftdf_req_buffers[FTDF_NR_OF_REQ_BUFFERS] __attribute__ ((section(".retention"))); +ftdf_queue_t ftdf_req_queue __attribute__ ((section(".retention"))); +ftdf_queue_t ftdf_free_queue __attribute__ ((section(".retention"))); +ftdf_pending_t ftdf_tx_pending_list[FTDF_NR_OF_REQ_BUFFERS] __attribute__ ((section(".retention"))); +ftdf_pending_tl_t ftdf_tx_pending_timer_list[FTDF_NR_OF_REQ_BUFFERS] __attribute__ ((section(".retention"))); +ftdf_pending_tl_t *ftdf_tx_pending_timer_head __attribute__ ((section(".retention"))); +ftdf_time_t ftdf_tx_pending_timer_lt __attribute__ ((section(".retention"))); +ftdf_time_t ftdf_tx_pending_timer_time __attribute__ ((section(".retention"))); #endif /* !FTDF_LITE */ #ifndef FTDF_PHY_API -FTDF_MsgBuffer *FTDF_reqCurrent __attribute__((section(".retention"))); +ftdf_msg_buffer_t *ftdf_req_current __attribute__ ((section(".retention"))); #endif -FTDF_Size FTDF_nrOfRetries __attribute__((section(".retention"))); +ftdf_size_t ftdf_nr_of_retries __attribute__ ((section(".retention"))); #if FTDF_USE_SLEEP_DURING_BACKOFF -static FTDF_Sdb FTDF_sdb __attribute__((section(".retention"))); +static ftdf_sdb_t ftdf_sdb __attribute__ ((section(".retention"))); #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ #ifndef FTDF_LITE -FTDF_Boolean FTDF_isPANCoordinator __attribute__((section(".retention"))); -FTDF_Time FTDF_startCslSampleTime __attribute__((section(".retention"))); -FTDF_RxAddressAdmin FTDF_rxa[ FTDF_NR_OF_RX_ADDRS ] __attribute__((section(".retention"))); +ftdf_boolean_t ftdf_is_pan_coordinator __attribute__ ((section(".retention"))); +ftdf_time_t ftdf_start_csl_sample_time __attribute__ ((section(".retention"))); +ftdf_rx_address_admin_t ftdf_rxa[FTDF_NR_OF_RX_ADDRS] __attribute__ ((section(".retention"))); #endif /* !FTDF_LITE */ -FTDF_Boolean FTDF_txInProgress __attribute__((section(".retention"))); +ftdf_boolean_t ftdf_tx_in_progress __attribute__ ((section(".retention"))); #ifndef FTDF_LITE #ifndef FTDF_NO_CSL -FTDF_PeerCslTiming FTDF_peerCslTiming[ FTDF_NR_OF_CSL_PEERS ] __attribute__((section(".retention"))); -FTDF_Boolean FTDF_oldLeEnabled __attribute__((section(".retention"))); -FTDF_Time FTDF_rzTime __attribute__((section(".retention"))); -FTDF_ShortAddress FTDF_sendFramePending __attribute__((section(".retention"))); +ftdf_peer_csl_timing_t ftdf_peer_csl_timing[FTDF_NR_OF_CSL_PEERS] __attribute__ ((section(".retention"))); +ftdf_boolean_t ftdf_old_le_enabled __attribute__ ((section(".retention"))); +ftdf_time_t ftdf_rz_time __attribute__ ((section(".retention"))); +ftdf_short_address_t ftdf_send_frame_pending __attribute__ ((section(".retention"))); #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ -uint32_t FTDF_curTime[ 2 ] __attribute__((section(".retention"))); -FTDF_LmacCounters FTDF_lmacCounters __attribute__((section(".retention"))); -FTDF_FrameHeader FTDF_fh; +uint32_t ftdf_cur_time[2] __attribute__ ((section(".retention"))); +ftdf_lmac_counters_t ftdf_lmac_counters __attribute__ ((section(".retention"))); +ftdf_frame_header_t ftdf_fh; #ifndef FTDF_LITE -FTDF_SecurityHeader FTDF_sh; -FTDF_AssocAdmin FTDF_aa; +ftdf_security_header ftdf_sh; +ftdf_assoc_admin_t ftdf_aa; #endif /* !FTDF_LITE */ -#if FTDF_USE_PTI +#if dg_configCOEX_ENABLE_CONFIG /* Packet traffic information used when FTDF is in RX enable. */ -static FTDF_PTI FTDF_RxPti __attribute__((section(".retention"))); +static ftdf_pti_t ftdf_rx_pti __attribute__ ((section(".retention"))); #endif -static void sendConfirm(FTDF_Status status, - FTDF_MsgId msgId); +static void send_confirm(ftdf_status_t status, ftdf_msg_id_t msg_id); -void FTDF_reset(int setDefaultPIB) +void ftdf_reset(int set_default_pib) { - if (setDefaultPIB) - { - // Reset PIB values to their default values - memset(&FTDF_pib, 0, sizeof(FTDF_pib)); + if (set_default_pib) { + /* Reset PIB values to their default values */ + memset(&ftdf_pib, 0, sizeof(ftdf_pib)); - FTDF_pib.extAddress = FTDF_GET_EXT_ADDRESS(); - FTDF_pib.ackWaitDuration = 0x36; + ftdf_pib.ext_address = FTDF_GET_EXT_ADDRESS(); + ftdf_pib.ack_wait_duration = 0x36; #ifndef FTDF_LITE - FTDF_pib.autoRequest = FTDF_TRUE; - FTDF_pib.beaconOrder = 15; - FTDF_pib.DSN = FTDF_pib.extAddress & 0xff; - FTDF_pib.BSN = FTDF_pib.extAddress & 0xff; - FTDF_pib.EBSN = FTDF_pib.extAddress & 0xff; - FTDF_pib.coordShortAddress = 0xffff; + ftdf_pib.auto_request = FTDF_TRUE; + ftdf_pib.beacon_order = 15; + ftdf_pib.dsn = ftdf_pib.ext_address & 0xff; + ftdf_pib.bsn = ftdf_pib.ext_address & 0xff; + ftdf_pib.eb_sn = ftdf_pib.ext_address & 0xff; + ftdf_pib.coord_short_address = 0xffff; #endif /* !FTDF_LITE */ - FTDF_pib.maxBE = 5; - FTDF_pib.maxCSMABackoffs = 4; - FTDF_pib.maxFrameTotalWaitTime = 1026; // see asic_vol v40.100.2.30 PR2540 - FTDF_pib.maxFrameRetries = 3; - FTDF_pib.minBE = 3; + ftdf_pib.max_be = 5; + ftdf_pib.max_csma_backoffs = 4; + ftdf_pib.max_frame_total_wait_time = 1026; /* see asic_vol v40.100.2.30 PR2540 */ + ftdf_pib.max_frame_retries = 3; + ftdf_pib.min_be = 3; #ifndef FTDF_LITE - FTDF_pib.LIFSPeriod = 40; - FTDF_pib.SIFSPeriod = 12; + ftdf_pib.lifs_period = 40; + ftdf_pib.sifs_period = 12; #endif /* !FTDF_LITE */ - FTDF_pib.PANId = 0xffff; + ftdf_pib.pan_id = 0xffff; #ifndef FTDF_LITE - FTDF_pib.responseWaitTime = 32; + ftdf_pib.response_wait_time = 32; #endif /* !FTDF_LITE */ - FTDF_pib.shortAddress = 0xffff; + ftdf_pib.short_address = 0xffff; #ifndef FTDF_LITE - FTDF_pib.superframeOrder = 15; - FTDF_pib.timestampSupported = FTDF_TRUE; - FTDF_pib.transactionPersistenceTime = 0x1f4; - FTDF_pib.enhAckWaitDuration = 0x360; - FTDF_pib.EBAutoSA = FTDF_AUTO_FULL; + ftdf_pib.superframe_order = 15; + ftdf_pib.timestamp_supported = FTDF_TRUE; + ftdf_pib.transaction_persistence_time = 0x1f4; + ftdf_pib.enh_ack_wait_duration = 0x360; + ftdf_pib.eb_auto_sa = FTDF_AUTO_FULL; #endif /* !FTDF_LITE */ - FTDF_pib.currentChannel = 11; - FTDF_pib.CCAMode = FTDF_CCA_MODE_1; + ftdf_pib.current_channel = 11; + ftdf_pib.cca_mode = FTDF_CCA_MODE_1; #ifndef FTDF_LITE - FTDF_pib.maxFrameDuration = FTDF_TBD; - FTDF_pib.SHRDuration = FTDF_TBD; - FTDF_pib.frameCounterMode = 4; + ftdf_pib.max_frame_duration = FTDF_TBD; + ftdf_pib.shr_duration = FTDF_TBD; + ftdf_pib.frame_counter_mode = 4; #endif /* !FTDF_LITE */ - FTDF_pib.metricsCapable = FTDF_TRUE; + ftdf_pib.metrics_capable = FTDF_TRUE; #ifndef FTDF_LITE - FTDF_pib.beaconAutoRespond = FTDF_TRUE; + ftdf_pib.beacon_auto_respond = FTDF_TRUE; #endif /* !FTDF_LITE */ - FTDF_pib.performanceMetrics.counterOctets = 4; // 32 bit counters + ftdf_pib.performance_metrics.counter_octets = 4; /* 32 bit counters */ #ifndef FTDF_LITE - FTDF_pib.joinPriority = 1; - FTDF_pib.slotframeTable.slotframeEntries = FTDF_slotframeTable; - FTDF_pib.linkTable.linkEntries = FTDF_linkTable; - FTDF_pib.timeslotTemplate.tsCCAOffset = 1800; - FTDF_pib.timeslotTemplate.tsCCA = 128; - FTDF_pib.timeslotTemplate.tsTxOffset = 2120; - FTDF_pib.timeslotTemplate.tsRxOffset = 1020; - FTDF_pib.timeslotTemplate.tsRxAckDelay = 800; - FTDF_pib.timeslotTemplate.tsTxAckDelay = 1000; - FTDF_pib.timeslotTemplate.tsRxWait = 2200; - FTDF_pib.timeslotTemplate.tsAckWait = 400; - FTDF_pib.timeslotTemplate.tsRxTx = 192; - FTDF_pib.timeslotTemplate.tsMaxAck = 2400; - FTDF_pib.timeslotTemplate.tsMaxTs = 4256; - FTDF_pib.timeslotTemplate.tsTimeslotLength = 10000; - FTDF_pib.tsSyncCorrectThreshold = 220; - FTDF_pib.hoppingSequenceLength = 16; -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - int i; - - for (i = 0; i < FTDF_PTIS; i++) - { - FTDF_pib.ptiConfig.ptis[i] = 0; - } - -#endif + ftdf_pib.join_priority = 1; + ftdf_pib.slotframe_table.slotframe_entries = ftdf_slotframe_table; + ftdf_pib.link_table.link_entries = ftdf_link_table; + ftdf_pib.timeslot_template.ts_cca_offset = 1800; + ftdf_pib.timeslot_template.ts_cca = 128; + ftdf_pib.timeslot_template.ts_tx_offset = 2120; + ftdf_pib.timeslot_template.ts_rx_offset = 1020; + ftdf_pib.timeslot_template.ts_rx_ack_delay = 800; + ftdf_pib.timeslot_template.ts_tx_ack_delay = 1000; + ftdf_pib.timeslot_template.ts_rx_wait = 2200; + ftdf_pib.timeslot_template.ts_ack_wait = 400; + ftdf_pib.timeslot_template.ts_rx_tx = 192; + ftdf_pib.timeslot_template.ts_max_ack = 2400; + ftdf_pib.timeslot_template.ts_max_ts = 4256; + ftdf_pib.timeslot_template.ts_timeslot_length = 10000; + ftdf_pib.ts_sync_correct_threshold = 220; + ftdf_pib.hopping_sequence_length = 16; + int i; + for (i = 0; i < FTDF_PTIS; i++) { + ftdf_pib.pti_config.ptis[i] = 0; + } #ifdef FTDF_NO_CSL - FTDF_pib.LECapable = FTDF_FALSE; + ftdf_pib.le_capable = FTDF_FALSE; #else - FTDF_pib.LECapable = FTDF_TRUE; + ftdf_pib.le_capable = FTDF_TRUE; #endif /* FTDF_NO_CSL */ #ifdef FTDF_NO_TSCH - FTDF_pib.tschCapable = FTDF_FALSE; + ftdf_pib.tsch_capable = FTDF_FALSE; #else - FTDF_pib.tschCapable = FTDF_TRUE; + ftdf_pib.tsch_capable = FTDF_TRUE; #endif /* FTDF_NO_TSCH */ - int n; + int n; - for (n = 0; n < FTDF_MAX_HOPPING_SEQUENCE_LENGTH; n++) - { - FTDF_pib.hoppingSequenceList[ n ] = n + 11; + for (n = 0; n < FTDF_MAX_HOPPING_SEQUENCE_LENGTH; n++) { + ftdf_pib.hopping_sequence_list[n] = n + 11; + } +#endif /* !FTDF_LITE */ + + ftdf_transparent_mode = FTDF_FALSE; +#ifndef FTDF_LITE + ftdf_is_pan_coordinator = FTDF_FALSE; +#endif /* !FTDF_LITE */ + ftdf_lmac_counters.fcs_error_cnt = 0; + ftdf_lmac_counters.tx_std_ack_cnt = 0; + ftdf_lmac_counters.rx_std_ack_cnt = 0; + +#ifndef FTDF_LITE + memset(ftdf_pib.default_key_source, 0xff, 8); +#endif /* !FTDF_LITE */ + ftdf_pib.bo_irq_threshold = FTDF_BO_IRQ_THRESHOLD; + ftdf_pib.link_quality_mode = FTDF_LINK_QUALITY_MODE_RSSI; } -#endif /* !FTDF_LITE */ + ftdf_init_queues(); - FTDF_transparentMode = FTDF_FALSE; -#ifndef FTDF_LITE - FTDF_isPANCoordinator = FTDF_FALSE; -#endif /* !FTDF_LITE */ - FTDF_lmacCounters.fcsErrorCnt = 0; - FTDF_lmacCounters.txStdAckCnt = 0; - FTDF_lmacCounters.rxStdAckCnt = 0; + FTDF->FTDF_LMACRESET_REG = REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_CONTROL) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_RX) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_TX) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_AHB) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_OREG) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_TSTIM) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_SEC) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_COUNT) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_TIMCTRL) | + REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACGLOBRESET_COUNT); + + uint32_t wait = 0; + + while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) { + wait++; + } + + REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_OS_REG, WAKEUPTIMERENABLE_CLEAR, 1); + + while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, WAKEUPTIMERENABLESTATUS)) {} + + REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_OS_REG, WAKEUPTIMERENABLE_SET, 1); + + while ((REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, WAKEUPTIMERENABLESTATUS)) == 0) {} #ifndef FTDF_LITE - memset(FTDF_pib.defaultKeySource, 0xff, 8); -#endif /* !FTDF_LITE */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - FTDF_pib.boIrqThreshold = FTDF_BO_IRQ_THRESHOLD; -#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ - } - - FTDF_initQueues(); - - volatile uint32_t *lmacReset = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMACRESET); - *lmacReset = MSK_R_FTDF_ON_OFF_REGMAP_LMACRESET; - - volatile uint32_t *controlStatus = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_CONTROL_STATUS); - uint32_t wait = 0; - - while ((*controlStatus & MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) - { - wait++; - } - - volatile uint32_t *wakeupTimerEnableStatus = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS); - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE, 0); - -#else - FTDF_SET_FIELD(ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR, 1); -#endif - - while (*wakeupTimerEnableStatus & MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS) - { } - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE, 1); - -#else - FTDF_SET_FIELD(ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET, 1); -#endif - - while ((*wakeupTimerEnableStatus & MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS) == 0) - { } - -#ifndef FTDF_LITE - int n; + int n; #ifndef FTDF_NO_CSL + for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { + ftdf_peer_csl_timing[n].addr = 0xffff; + } - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) - { - FTDF_peerCslTiming[ n ].addr = 0xffff; - } - - FTDF_oldLeEnabled = FTDF_FALSE; - FTDF_wakeUpEnableLe = FTDF_FALSE; - FTDF_sendFramePending = 0xfffe; + ftdf_old_le_enabled = FTDF_FALSE; + ftdf_wake_up_enable_le = FTDF_FALSE; + ftdf_send_frame_pending = 0xfffe; #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ - FTDF_txInProgress = FTDF_FALSE; + ftdf_tx_in_progress = FTDF_FALSE; - FTDF_initCurTime64(); + ftdf_init_cur_time64(); #ifndef FTDF_NO_TSCH - FTDF_initTschRetries(); - FTDF_initBackoff(); + ftdf_init_tsch_retries(); + ftdf_init_backoff(); #endif /* FTDF_NO_TSCH */ #ifndef FTDF_LITE - - for (n = 0; n < FTDF_NR_OF_RX_ADDRS; n++) - { - FTDF_rxa[ n ].addrMode = FTDF_NO_ADDRESS; - FTDF_rxa[ n ].dsnValid = FTDF_FALSE; - FTDF_rxa[ n ].bsnValid = FTDF_FALSE; - FTDF_rxa[ n ].ebsnValid = FTDF_FALSE; - } + for (n = 0; n < FTDF_NR_OF_RX_ADDRS; n++) { + ftdf_rxa[n].addr_mode = FTDF_NO_ADDRESS; + ftdf_rxa[n].dsn_valid = FTDF_FALSE; + ftdf_rxa[n].bsn_valid = FTDF_FALSE; + ftdf_rxa[n].ebsn_valid = FTDF_FALSE; + } #ifndef FTDF_NO_TSCH - - for (n = 0; n < FTDF_NR_OF_NEIGHBORS; n++) - { - FTDF_neighborTable[ n ].dstAddr = 0xffff; - } - + for (n = 0; n < FTDF_NR_OF_NEIGHBORS; n++) { + ftdf_neighbor_table[n].dst_addr = 0xffff; + } #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ #if FTDF_USE_SLEEP_DURING_BACKOFF - FTDF_sdbFsmReset(); + ftdf_sdb_fsm_reset(); #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - FTDF_initLmac(); + ftdf_init_lmac(); #ifndef FTDF_NO_CSL - FTDF_rzTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + ftdf_rz_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); #endif /* FTDF_NO_CSL */ #if dg_configUSE_FTDF_DDPHY == 1 - FTDF_ddphySet(0); + ftdf_ddphy_set(0); #endif } -#ifndef FTDF_PHY_API -void FTDF_processResetRequest(FTDF_ResetRequest *resetRequest) + +#ifndef FTDF_LITE +void ftdf_cleanup_queues(void) { + while (!ftdf_is_queue_empty(&ftdf_req_queue)) { + ftdf_msg_buffer_t *request = ftdf_dequeue_req_tail(&ftdf_req_queue); + if (request) { + ad_ftdf_rel_msg_data(request); + } + } - FTDF_reset(resetRequest->setDefaultPIB); - FTDF_ResetConfirm *resetConfirm = (FTDF_ResetConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_ResetConfirm)); + int n; + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { + while (!ftdf_is_queue_empty(&ftdf_tx_pending_list[n].queue)) { + ftdf_msg_buffer_t *request = ftdf_dequeue_req_tail(&ftdf_tx_pending_list[n].queue); + if (request) { + ad_ftdf_rel_msg_data(request); + } + } + } +} +#endif /* !FTDF_LITE */ - resetConfirm->msgId = FTDF_RESET_CONFIRM; - resetConfirm->status = FTDF_SUCCESS; +#ifndef FTDF_PHY_API +void ftdf_process_reset_request(ftdf_reset_request_t *reset_request) +{ +#ifndef FTDF_LITE + ftdf_cleanup_queues(); +#endif + ftdf_reset(reset_request->set_default_pib); + ftdf_reset_confirm_t* resetConfirm = + (ftdf_reset_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_reset_confirm_t)); - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) resetRequest); + resetConfirm->msg_id = FTDF_RESET_CONFIRM; + resetConfirm->status = FTDF_SUCCESS; - FTDF_RCV_MSG((FTDF_MsgBuffer *) resetConfirm); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)reset_request); + + FTDF_RCV_MSG((ftdf_msg_buffer_t*)resetConfirm); } #endif /* FTDF_PHY_API */ -void FTDF_initLmac(void) +void ftdf_init_lmac(void) { - FTDF_PIBAttribute PIBAttribute; + ftdf_pib_attribute_t pib_attribute; - for (PIBAttribute = 1; PIBAttribute <= FTDF_NR_OF_PIB_ATTRIBUTES; PIBAttribute++) - { - if (pibAttributeTable.attributeDefs[ PIBAttribute ].setFunc != NULL) - { - pibAttributeTable.attributeDefs[ PIBAttribute ].setFunc(); + for (pib_attribute = 1; pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES; pib_attribute++) { + if (pib_attribute_table.attribute_defs[pib_attribute].setFunc != NULL) { + pib_attribute_table.attribute_defs[pib_attribute].setFunc(); + } } - } - if (FTDF_transparentMode == FTDF_TRUE) - { - FTDF_enableTransparentMode(FTDF_TRUE, FTDF_transparentModeOptions); - } + if (ftdf_transparent_mode == FTDF_TRUE) { + ftdf_enable_transparent_mode(FTDF_TRUE, ftdf_transparent_mode_options); + } #ifndef FTDF_LITE - - if (FTDF_isPANCoordinator) - { - FTDF_SET_FIELD(ON_OFF_REGMAP_ISPANCOORDINATOR, 1); - } - + if (ftdf_is_pan_coordinator) { + REG_SETF(FTDF, FTDF_GLOB_CONTROL_0_REG, ISPANCOORDINATOR, 1); + } #endif /* !FTDF_LITE */ - FTDF_SET_FIELD(ON_OFF_REGMAP_CCAIDLEWAIT, 192); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, CCAIDLEWAIT, 192); - volatile uint32_t *txFlagClear = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_CLEAR); - *txFlagClear = MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR; + FTDF->FTDF_TX_CLEAR_OS_REG = REG_MSK(FTDF, FTDF_TX_CLEAR_OS_REG, TX_FLAG_CLEAR); - volatile uint32_t *phyParams = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_PHY_PARAMETERS_2); - *phyParams = (FTDF_PHYTXSTARTUP << OFF_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP) | - (FTDF_PHYTXLATENCY << OFF_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY) | - (FTDF_PHYTXFINISH << OFF_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH) | - (FTDF_PHYTRXWAIT << OFF_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT); + uint32_t phy_params = 0; + REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTXSTARTUP, phy_params, FTDF_PHYTXSTARTUP); + REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTXLATENCY, phy_params, FTDF_PHYTXLATENCY); + REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTXFINISH, phy_params, FTDF_PHYTXFINISH); + REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTRXWAIT, phy_params, FTDF_PHYTRXWAIT); + FTDF->FTDF_PHY_PARAMETERS_2_REG = phy_params; - phyParams = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_PHY_PARAMETERS_3); - *phyParams = (FTDF_PHYRXSTARTUP << OFF_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP) | - (FTDF_PHYRXLATENCY << OFF_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY) | - (FTDF_PHYENABLE << OFF_F_FTDF_ON_OFF_REGMAP_PHYENABLE); + phy_params = 0; + REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_3_REG, PHYRXSTARTUP, phy_params, FTDF_PHYRXSTARTUP); + REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_3_REG, PHYRXLATENCY, phy_params, FTDF_PHYRXLATENCY); + REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_3_REG, PHYENABLE, phy_params, FTDF_PHYENABLE); + FTDF->FTDF_PHY_PARAMETERS_3_REG = phy_params; - volatile uint32_t *ftdfCm = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CM); - *ftdfCm = FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE; - volatile uint32_t *rxMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_RX_MASK); - *rxMask = MSK_R_FTDF_ON_OFF_REGMAP_RX_MASK; + REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM, + (FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE)); - volatile uint32_t *lmacMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_MASK); - *lmacMask = MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M; + uint32_t rx_mask = REG_MSK(FTDF, FTDF_RX_MASK_REG, RXSOF_M) | + REG_MSK(FTDF, FTDF_RX_MASK_REG, RX_OVERFLOW_M) | + REG_MSK(FTDF, FTDF_RX_MASK_REG, RX_BUF_AVAIL_M) | + REG_MSK(FTDF, FTDF_RX_MASK_REG, RXBYTE_M); + FTDF->FTDF_RX_MASK_REG = rx_mask; - volatile uint32_t *lmacCtrlMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_CONTROL_MASK); - *lmacCtrlMask = MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M | - MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M | - MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M; + FTDF->FTDF_LMAC_MASK_REG = REG_MSK(FTDF, FTDF_LMAC_MASK_REG, RXTIMEREXPIRED_M); + + uint32_t lmac_ctrl_mask = REG_MSK(FTDF, FTDF_LMAC_CONTROL_MASK_REG, SYMBOLTIMETHR_M) | + REG_MSK(FTDF, FTDF_LMAC_CONTROL_MASK_REG, SYMBOLTIME2THR_M) | + REG_MSK(FTDF, FTDF_LMAC_CONTROL_MASK_REG, SYNCTIMESTAMP_M); + FTDF->FTDF_LMAC_CONTROL_MASK_REG = lmac_ctrl_mask; + + FTDF->FTDF_TX_FLAG_CLEAR_M_0_REG |= REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_M_0_REG, TX_FLAG_CLEAR_M); + FTDF->FTDF_TX_FLAG_CLEAR_M_1_REG |= REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_M_1_REG, TX_FLAG_CLEAR_M); - volatile uint32_t *txFlagClearM; - txFlagClearM = FTDF_GET_FIELD_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_CLEAR_M, FTDF_TX_DATA_BUFFER); - *txFlagClearM |= MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M; - txFlagClearM = FTDF_GET_FIELD_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_CLEAR_M, FTDF_TX_WAKEUP_BUFFER); - *txFlagClearM |= MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M; -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - FTDF_fpprReset(); - FTDF_fpprSetMode(FTDF_TRUE, FTDF_FALSE, FTDF_FALSE); + ftdf_fppr_reset(); + ftdf_fppr_set_mode(FTDF_TRUE, FTDF_FALSE, FTDF_FALSE); #else - FTDF_fpprSetMode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); + ftdf_fppr_set_mode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); #endif /* #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ #if FTDF_USE_SLEEP_DURING_BACKOFF /* Unmask long BO interrupt. */ - FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THR_M, 1); + REG_SETF(FTDF, FTDF_LMAC_MASK_REG, CSMA_CA_BO_THR_M, 1); #else /* FTDF_USE_SLEEP_DURING_BACKOFF */ /* Set BO threshold. */ - FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD, FTDF_BO_IRQ_THRESHOLD); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_BO_THRESHOLD, FTDF_BO_IRQ_THRESHOLD); /* Mask long BO interrupt. */ - FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THR_M, 0); + REG_SETF(FTDF, FTDF_LMAC_MASK_REG, CSMA_CA_BO_THR_M, 0); #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ #if FTDF_USE_LPDP == 1 - FTDF_lpdpEnable(FTDF_TRUE); + ftdf_lpdp_enable(FTDF_TRUE); #endif /* #if FTDF_USE_LPDP == 1 */ -#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ } #ifdef FTDF_PHY_API -FTDF_PIBAttributeValue *FTDF_getValue(FTDF_PIBAttribute PIBAttribute) +ftdf_pib_attribute_value_t *ftdf_get_value(ftdf_pib_attribute_t pib_attribute) { - if (PIBAttribute <= FTDF_NR_OF_PIB_ATTRIBUTES && - pibAttributeTable.attributeDefs[ PIBAttribute ].addr != NULL) - { - // Update PIB attribute with current LMAC status if a getFunc is defined - if (pibAttributeTable.attributeDefs[ PIBAttribute ].getFunc != NULL) - { - pibAttributeTable.attributeDefs[ PIBAttribute ].getFunc(); + if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && + (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { + + /* Update PIB attribute with current LMAC status if a getFunc is defined */ + if (pib_attribute_table.attribute_defs[pib_attribute].getFunc != NULL) { + pib_attribute_table.attribute_defs[pib_attribute].getFunc(); + } + + return pib_attribute_table.attribute_defs[pib_attribute].addr; } - return pibAttributeTable.attributeDefs[ PIBAttribute ].addr; - } - - return NULL; + return NULL; } -FTDF_Status FTDF_setValue(FTDF_PIBAttribute PIBAttribute, const FTDF_PIBAttributeValue *PIBAttributeValue) +ftdf_status_t ftdf_set_value(ftdf_pib_attribute_t pib_attribute, const ftdf_pib_attribute_value_t *pib_attribute_value) { - if (PIBAttribute <= FTDF_NR_OF_PIB_ATTRIBUTES && - pibAttributeTable.attributeDefs[ PIBAttribute ].addr != NULL) - { - if (pibAttributeTable.attributeDefs[ PIBAttribute ].size != 0) - { - memcpy(pibAttributeTable.attributeDefs[ PIBAttribute ].addr, - PIBAttributeValue, - pibAttributeTable.attributeDefs[ PIBAttribute ].size); + if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && + (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { - // Update LMAC with new PIB attribute value if a setFunc is defined - if (pibAttributeTable.attributeDefs[ PIBAttribute ].setFunc != NULL) - { - pibAttributeTable.attributeDefs[ PIBAttribute ].setFunc(); - } + if (pib_attribute_table.attribute_defs[pib_attribute].size != 0) { + memcpy(pib_attribute_table.attribute_defs[pib_attribute].addr, + pib_attribute_value, + pib_attribute_table.attribute_defs[pib_attribute].size); - return FTDF_SUCCESS; + /* Update LMAC with new PIB attribute value if a setFunc is defined */ + if (pib_attribute_table.attribute_defs[pib_attribute].setFunc != NULL) { + pib_attribute_table.attribute_defs[pib_attribute].setFunc(); + } + return FTDF_SUCCESS; + + } else { + return FTDF_READ_ONLY; + } } - else - { - return FTDF_READ_ONLY; - } - } - return FTDF_UNSUPPORTED_ATTRIBUTE; + return FTDF_UNSUPPORTED_ATTRIBUTE; } #else /* FTDF_PHY_API */ -void FTDF_processGetRequest(FTDF_GetRequest *getRequest) +void ftdf_process_get_request(ftdf_get_request_t *get_request) { - FTDF_GetConfirm *getConfirm = (FTDF_GetConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_GetConfirm)); - FTDF_PIBAttribute PIBAttribute = getRequest->PIBAttribute; + ftdf_get_confirm_t *get_confirm = + (ftdf_get_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_get_confirm_t)); + ftdf_pib_attribute_t pib_attribute = get_request->pib_attribute; - getConfirm->msgId = FTDF_GET_CONFIRM; - getConfirm->PIBAttribute = PIBAttribute; + get_confirm->msg_id = FTDF_GET_CONFIRM; + get_confirm->pib_attribute = pib_attribute; - if (PIBAttribute <= FTDF_NR_OF_PIB_ATTRIBUTES && - pibAttributeTable.attributeDefs[ PIBAttribute ].addr != NULL) - { - // Update PIB attribute with current LMAC status if a getFunc is defined - if (pibAttributeTable.attributeDefs[ PIBAttribute ].getFunc != NULL) - { - pibAttributeTable.attributeDefs[ PIBAttribute ].getFunc(); + if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && + (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { + + /* Update PIB attribute with current LMAC status if a getFunc is defined */ + if (pib_attribute_table.attribute_defs[pib_attribute].getFunc != NULL) { + pib_attribute_table.attribute_defs[pib_attribute].getFunc(); + } + + get_confirm->status = FTDF_SUCCESS; + get_confirm->pib_attribute_value = + pib_attribute_table.attribute_defs[pib_attribute].addr; + + } else { + get_confirm->status = FTDF_UNSUPPORTED_ATTRIBUTE; } - getConfirm->status = FTDF_SUCCESS; - getConfirm->PIBAttributeValue = pibAttributeTable.attributeDefs[ PIBAttribute ].addr; - } - else - { - getConfirm->status = FTDF_UNSUPPORTED_ATTRIBUTE; - } + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)get_request); - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) getRequest); - - FTDF_RCV_MSG((FTDF_MsgBuffer *) getConfirm); + FTDF_RCV_MSG((ftdf_msg_buffer_t*)get_confirm); } -void FTDF_processSetRequest(FTDF_SetRequest *setRequest) +void ftdf_process_set_request(ftdf_set_request_t *set_request) { - FTDF_SetConfirm *setConfirm = (FTDF_SetConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_SetConfirm)); - FTDF_PIBAttribute PIBAttribute = setRequest->PIBAttribute; + ftdf_set_confirm_t *set_confirm = + (ftdf_set_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_set_confirm_t)); + ftdf_pib_attribute_t pib_attribute = set_request->pib_attribute; - setConfirm->msgId = FTDF_SET_CONFIRM; - setConfirm->PIBAttribute = PIBAttribute; + set_confirm->msg_id = FTDF_SET_CONFIRM; + set_confirm->pib_attribute = pib_attribute; - if (PIBAttribute <= FTDF_NR_OF_PIB_ATTRIBUTES && - pibAttributeTable.attributeDefs[ PIBAttribute ].addr != NULL) - { - if (pibAttributeTable.attributeDefs[ PIBAttribute ].size != 0) - { - setConfirm->status = FTDF_SUCCESS; - memcpy(pibAttributeTable.attributeDefs[ PIBAttribute ].addr, - setRequest->PIBAttributeValue, - pibAttributeTable.attributeDefs[ PIBAttribute ].size); + if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && + (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { - // Update LMAC with new PIB attribute value if a setFunc is defined - if (pibAttributeTable.attributeDefs[ PIBAttribute ].setFunc != NULL) - { - pibAttributeTable.attributeDefs[ PIBAttribute ].setFunc(); - } + if (pib_attribute_table.attribute_defs[pib_attribute].size != 0) { + + set_confirm->status = FTDF_SUCCESS; + memcpy(pib_attribute_table.attribute_defs[pib_attribute].addr, + set_request->pib_attribute_value, + pib_attribute_table.attribute_defs[pib_attribute].size); + + /* Update LMAC with new PIB attribute value if a setFunc is defined */ + if (pib_attribute_table.attribute_defs[pib_attribute].setFunc != NULL) { + pib_attribute_table.attribute_defs[pib_attribute].setFunc(); + } + + } else { + set_confirm->status = FTDF_READ_ONLY; + } + + } else { + set_confirm->status = FTDF_UNSUPPORTED_ATTRIBUTE; } - else - { - setConfirm->status = FTDF_READ_ONLY; - } - } - else - { - setConfirm->status = FTDF_UNSUPPORTED_ATTRIBUTE; - } - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) setRequest); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)set_request); - FTDF_RCV_MSG((FTDF_MsgBuffer *) setConfirm); + FTDF_RCV_MSG((ftdf_msg_buffer_t*)set_confirm); } - -void FTDF_sendCommStatusIndication(FTDF_MsgBuffer *request, - FTDF_Status status, - FTDF_PANId PANId, - FTDF_AddressMode srcAddrMode, - FTDF_Address srcAddr, - FTDF_AddressMode dstAddrMode, - FTDF_Address dstAddr, - FTDF_SecurityLevel securityLevel, - FTDF_KeyIdMode keyIdMode, - FTDF_Octet *keySource, - FTDF_KeyIndex keyIndex) +void ftdf_send_comm_status_indication(ftdf_msg_buffer_t *request, + ftdf_status_t status, + ftdf_pan_id_t pan_id, + ftdf_address_mode_t src_addr_mode, + ftdf_address_t src_addr, + ftdf_address_mode_t dst_addr_mode, + ftdf_address_t dst_addr, + ftdf_security_level_t security_level, + ftdf_key_id_mode_t key_id_mode, + ftdf_octet_t *key_source, + ftdf_key_index_t key_index) { - FTDF_CommStatusIndication *commStatus = - (FTDF_CommStatusIndication *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_CommStatusIndication)); + ftdf_comm_status_indication_t *comm_status = + (ftdf_comm_status_indication_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_comm_status_indication_t)); - commStatus->msgId = FTDF_COMM_STATUS_INDICATION; - commStatus->PANId = PANId; - commStatus->srcAddrMode = srcAddrMode; - commStatus->srcAddr = srcAddr; - commStatus->dstAddrMode = dstAddrMode; - commStatus->dstAddr = dstAddr; - commStatus->status = status; - commStatus->securityLevel = securityLevel; - commStatus->keyIdMode = keyIdMode; - commStatus->keyIndex = keyIndex; + comm_status->msg_id = FTDF_COMM_STATUS_INDICATION; + comm_status->pan_id = pan_id; + comm_status->src_addr_mode = src_addr_mode; + comm_status->src_addr = src_addr; + comm_status->dst_addr_mode = dst_addr_mode; + comm_status->dst_addr = dst_addr; + comm_status->status = status; + comm_status->security_level = security_level; + comm_status->key_id_mode = key_id_mode; + comm_status->key_index = key_index; - uint8_t n; + uint8_t n; - if (securityLevel != 0) - { - if (keyIdMode == 0x2) - { - for (n = 0; n < 4; n++) - { - commStatus->keySource[ n ] = keySource[ n ]; - } + if (security_level != 0) { + if (key_id_mode == 0x2) { + for (n = 0; n < 4; n++) { + comm_status->key_source[n] = key_source[n]; + } + } else if (key_id_mode == 0x3) { + for (n = 0; n < 8; n++) { + comm_status->key_source[n] = key_source[n]; + } + } } - else if (keyIdMode == 0x3) - { - for (n = 0; n < 8; n++) - { - commStatus->keySource[ n ] = keySource[ n ]; - } - } - } - #ifndef FTDF_LITE + if (request && ((request->msg_id == FTDF_ORPHAN_RESPONSE) || + (request->msg_id == FTDF_ASSOCIATE_RESPONSE))) { - if (request && - (request->msgId == FTDF_ORPHAN_RESPONSE || - request->msgId == FTDF_ASSOCIATE_RESPONSE)) - { - if (FTDF_reqCurrent == request) - { - FTDF_reqCurrent = NULL; - } + if (ftdf_req_current == request) { + ftdf_req_current = NULL; + } - FTDF_REL_MSG_BUFFER(request); - FTDF_RCV_MSG((FTDF_MsgBuffer *) commStatus); - /* Check for orphan response. */ + FTDF_REL_MSG_BUFFER(request); + FTDF_RCV_MSG((ftdf_msg_buffer_t*)comm_status); #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - FTDF_fpFsmClearPending(); + ftdf_fp_fsm_clear_pending(); #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - FTDF_processNextRequest(); - return; - } - + ftdf_process_next_request(); + return; + } #endif /* !FTDF_LITE */ - FTDF_RCV_MSG((FTDF_MsgBuffer *) commStatus); + FTDF_RCV_MSG((ftdf_msg_buffer_t*)comm_status); } #endif /* FTDF_PHY_API */ #ifndef FTDF_LITE -FTDF_Octet *FTDF_addFrameHeader(FTDF_Octet *txPtr, - FTDF_FrameHeader *frameHeader, - FTDF_DataLength msduLength) +ftdf_octet_t* ftdf_add_frame_header(ftdf_octet_t *tx_ptr, + ftdf_frame_header_t *frame_header, + ftdf_data_length_t msdu_length) { - uint8_t frameVersion; - uint8_t longFrameControl = 0x00; - FTDF_Boolean panIdCompression = FTDF_FALSE; - FTDF_Bitmap8 options = frameHeader->options; - FTDF_Boolean secure = options & FTDF_OPT_SECURITY_ENABLED; - FTDF_Boolean framePending = options & FTDF_OPT_FRAME_PENDING; - FTDF_Boolean ackTX = options & FTDF_OPT_ACK_REQUESTED; - FTDF_Boolean panIdPresent = options & FTDF_OPT_PAN_ID_PRESENT; - FTDF_Boolean seqNrSuppressed = options & FTDF_OPT_SEQ_NR_SUPPRESSED; - FTDF_Boolean iesIncluded = options & FTDF_OPT_IES_PRESENT; - FTDF_FrameType frameType = frameHeader->frameType; - FTDF_AddressMode dstAddrMode = frameHeader->dstAddrMode; - FTDF_AddressMode srcAddrMode = frameHeader->srcAddrMode; - FTDF_PANId dstPANId = frameHeader->dstPANId; + uint8_t frame_version; + uint8_t long_frame_control = 0x00; + ftdf_boolean_t pan_id_compression = FTDF_FALSE; + ftdf_bitmap8_t options = frame_header->options; + ftdf_boolean_t secure = options & FTDF_OPT_SECURITY_ENABLED; + ftdf_boolean_t frame_pending = options & FTDF_OPT_FRAME_PENDING; + ftdf_boolean_t ack_tx = options & FTDF_OPT_ACK_REQUESTED; + ftdf_boolean_t pan_id_present = options & FTDF_OPT_PAN_ID_PRESENT; + ftdf_boolean_t seq_nr_suppressed = options & FTDF_OPT_SEQ_NR_SUPPRESSED; + ftdf_boolean_t ies_included = options & FTDF_OPT_IES_PRESENT; + ftdf_frame_type_t frame_type = frame_header->frame_type; + ftdf_address_mode_t dst_addr_mode = frame_header->dst_addr_mode; + ftdf_address_mode_t src_addr_mode = frame_header->src_addr_mode; + ftdf_pan_id_t dstpan_id = frame_header->dst_pan_id; - if (frameType == FTDF_MULTIPURPOSE_FRAME) - { - if (options & (FTDF_OPT_SECURITY_ENABLED | FTDF_OPT_ACK_REQUESTED | FTDF_OPT_PAN_ID_PRESENT | - FTDF_OPT_IES_PRESENT | FTDF_OPT_SEQ_NR_SUPPRESSED | FTDF_OPT_FRAME_PENDING)) - { - longFrameControl = 0x08; + if (frame_type == FTDF_MULTIPURPOSE_FRAME) { + + if (options & (FTDF_OPT_SECURITY_ENABLED | FTDF_OPT_ACK_REQUESTED | + FTDF_OPT_PAN_ID_PRESENT | FTDF_OPT_IES_PRESENT | + FTDF_OPT_SEQ_NR_SUPPRESSED | FTDF_OPT_FRAME_PENDING)) { + + long_frame_control = 0x08; + } + + /* Frame control field byte 1 */ + *tx_ptr++ = 0x05 | long_frame_control | dst_addr_mode << 4 | src_addr_mode << 6; + + if (long_frame_control) { + /* Frame control field byte 2 */ + *tx_ptr++ = (pan_id_present ? 0x01 : 0x00) | + (secure ? 0x02 : 0x00) | + (seq_nr_suppressed ? 0x04 : 0x00) | + (frame_pending ? 0x08 : 0x00) | + (ack_tx ? 0x40 : 0x00) | + (ies_included ? 0x80 : 0x00); + } + + } else { + // if (panIdPresent || iesIncluded || seqNrSuppressed || (options & FTDF_OPT_ENHANCED) || ftdf_pib.tsch_enabled) + if (pan_id_present || ies_included || seq_nr_suppressed || (options & FTDF_OPT_ENHANCED)) { + frame_version = 0x02; + } else { + + if (secure || (msdu_length > FTDF_MAX_MAC_SAFE_PAYLOAD_SIZE)) { + frame_version = 0x01; + } else { + frame_version = 0x00; + } + } + + if (frame_version < 0x02) { + if ((dst_addr_mode != FTDF_NO_ADDRESS) && + (src_addr_mode != FTDF_NO_ADDRESS) && + (dstpan_id == frame_header->src_pan_id)) { + + pan_id_compression = FTDF_TRUE; + } + + } else { + pan_id_compression = pan_id_present; + } + + /* Frame control field byte 1 */ + *tx_ptr++ = (frame_type & 0x7) | + (secure ? 0x08 : 0x00) | + (frame_pending ? 0x10 : 0x00) | + (ack_tx ? 0x20 : 0x00) | + (pan_id_compression ? 0x40 : 0x00); + + /* Frame control field byte 2 */ + *tx_ptr++ = (seq_nr_suppressed ? 0x01 : 0x00) | + (ies_included ? 0x02 : 0x00) | + (dst_addr_mode << 2) | + (frame_version << 4) | + (src_addr_mode << 6); } - // Frame control field byte 1 - *txPtr++ = 0x05 | longFrameControl | dstAddrMode << 4 | srcAddrMode << 6; - - if (longFrameControl) - { - // Frame control field byte 2 - *txPtr++ = - (panIdPresent ? 0x01 : 0x00) | - (secure ? 0x02 : 0x00) | - (seqNrSuppressed ? 0x04 : 0x00) | - (framePending ? 0x08 : 0x00) | - (ackTX ? 0x40 : 0x00) | - (iesIncluded ? 0x80 : 0x00); - } - } - else - { - // if ( panIdPresent || iesIncluded || seqNrSuppressed || ( options & FTDF_OPT_ENHANCED ) || FTDF_pib.tschEnabled ) - if (panIdPresent || iesIncluded || seqNrSuppressed || (options & FTDF_OPT_ENHANCED)) - { - frameVersion = 0b10; - } - else - { - if (secure || - msduLength > FTDF_MAX_MAC_SAFE_PAYLOAD_SIZE) - { - frameVersion = 0b01; - } - else - { - frameVersion = 0b00; - } + if (!seq_nr_suppressed) { + *tx_ptr++ = frame_header->sn; } - if (frameVersion < 0b10) - { - if (dstAddrMode != FTDF_NO_ADDRESS && - srcAddrMode != FTDF_NO_ADDRESS && - dstPANId == frameHeader->srcPANId) - { - panIdCompression = FTDF_TRUE; - } - } - else - { - panIdCompression = panIdPresent; + ftdf_boolean_t add_dstpan_id = FTDF_FALSE; + + if (frame_type == FTDF_MULTIPURPOSE_FRAME) { + if (pan_id_present) { + add_dstpan_id = FTDF_TRUE; + } + + } else { + + if (frame_version < 0x02) { + if (dst_addr_mode != FTDF_NO_ADDRESS) { + add_dstpan_id = FTDF_TRUE; + } + + } else { + + /* See Table 2a "PAN ID Compression" of IEEE 802.15.4-2011 for more details */ + if (((src_addr_mode == FTDF_NO_ADDRESS) && + (dst_addr_mode == FTDF_NO_ADDRESS) && pan_id_compression) || + ((src_addr_mode == FTDF_NO_ADDRESS) && + (dst_addr_mode != FTDF_NO_ADDRESS && !pan_id_compression)) || + ((src_addr_mode != FTDF_NO_ADDRESS) && + (dst_addr_mode != FTDF_NO_ADDRESS && !pan_id_compression))) { + + add_dstpan_id = FTDF_TRUE; + } + } } - // Frame control field byte 1 - *txPtr++ = - (frameType & 0x7) | - (secure ? 0x08 : 0x00) | - (framePending ? 0x10 : 0x00) | - (ackTX ? 0x20 : 0x00) | - (panIdCompression ? 0x40 : 0x00); + if (add_dstpan_id) { + ftdf_octet_t *pan_idPtr = (ftdf_octet_t*)&dstpan_id; - // Frame control field byte 2 - *txPtr++ = - (seqNrSuppressed ? 0x01 : 0x00) | - (iesIncluded ? 0x02 : 0x00) | - dstAddrMode << 2 | - frameVersion << 4 | - srcAddrMode << 6; - } - - if (!seqNrSuppressed) - { - *txPtr++ = frameHeader->SN; - } - - FTDF_Boolean addDstPANId = FTDF_FALSE; - - if (frameType == FTDF_MULTIPURPOSE_FRAME) - { - if (panIdPresent) - { - addDstPANId = FTDF_TRUE; + *tx_ptr++ = *pan_idPtr++; + *tx_ptr++ = *pan_idPtr; } - } - else - { - if (frameVersion < 0b10) - { - if (dstAddrMode != FTDF_NO_ADDRESS) - { - addDstPANId = FTDF_TRUE; - } + + ftdf_address_t dst_addr = frame_header->dst_addr; + + if (dst_addr_mode == FTDF_SIMPLE_ADDRESS) { + *tx_ptr++ = dst_addr.simple_address; + } else if (dst_addr_mode == FTDF_SHORT_ADDRESS) { + ftdf_octet_t* short_address_ptr = (ftdf_octet_t*)&dst_addr.short_address; + + *tx_ptr++ = *short_address_ptr++; + *tx_ptr++ = *short_address_ptr; + } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { + ftdf_octet_t* ext_address_ptr = (ftdf_octet_t*)&dst_addr.ext_address; + int n; + + for (n = 0; n < 8; n++) { + *tx_ptr++ = *ext_address_ptr++; + } } - else - { - // See Table 2a "PAN ID Compression" of IEEE 802.15.4-2011 for more details - if ((srcAddrMode == FTDF_NO_ADDRESS && dstAddrMode == FTDF_NO_ADDRESS && panIdCompression) || - (srcAddrMode == FTDF_NO_ADDRESS && dstAddrMode != FTDF_NO_ADDRESS && !panIdCompression) || - (srcAddrMode != FTDF_NO_ADDRESS && dstAddrMode != FTDF_NO_ADDRESS && !panIdCompression)) - { - addDstPANId = FTDF_TRUE; - } + + ftdf_boolean_t add_srcpan_id = FTDF_FALSE; + + if (frame_type != FTDF_MULTIPURPOSE_FRAME) { + if (frame_version < 0x02) { + if ((src_addr_mode != FTDF_NO_ADDRESS) && !pan_id_compression) { + add_srcpan_id = FTDF_TRUE; + } + + } else { + + /* See Table 2a "PAN ID Compression" of IEEE 802.15.4-2011 for more details */ + if ((src_addr_mode != FTDF_NO_ADDRESS) && (dst_addr_mode == FTDF_NO_ADDRESS) && + !pan_id_compression) { + + add_srcpan_id = FTDF_TRUE; + } + } } - } - if (addDstPANId) - { - FTDF_Octet *PANIdPtr = (FTDF_Octet *)&dstPANId; + if (add_srcpan_id) { + ftdf_octet_t* pan_idPtr = (ftdf_octet_t*)&frame_header->src_pan_id; - *txPtr++ = *PANIdPtr++; - *txPtr++ = *PANIdPtr; - } - - FTDF_Address dstAddr = frameHeader->dstAddr; - - if (dstAddrMode == FTDF_SIMPLE_ADDRESS) - { - *txPtr++ = dstAddr.simpleAddress; - } - else if (dstAddrMode == FTDF_SHORT_ADDRESS) - { - FTDF_Octet *shortAddressPtr = (FTDF_Octet *)&dstAddr.shortAddress; - - *txPtr++ = *shortAddressPtr++; - *txPtr++ = *shortAddressPtr; - } - else if (dstAddrMode == FTDF_EXTENDED_ADDRESS) - { - FTDF_Octet *extAddressPtr = (FTDF_Octet *)&dstAddr.extAddress; - int n; - - for (n = 0; n < 8; n++) - { - *txPtr++ = *extAddressPtr++; + *tx_ptr++ = *pan_idPtr++; + *tx_ptr++ = *pan_idPtr; } - } - FTDF_Boolean addSrcPANId = FTDF_FALSE; - - if (frameType != FTDF_MULTIPURPOSE_FRAME) - { - if (frameVersion < 0b10) - { - if (srcAddrMode != FTDF_NO_ADDRESS && !panIdCompression) - { - addSrcPANId = FTDF_TRUE; - } + if (src_addr_mode == FTDF_SIMPLE_ADDRESS) { + *tx_ptr++ = ftdf_pib.simple_address; } - else - { - // See Table 2a "PAN ID Compression" of IEEE 802.15.4-2011 for more details - if (srcAddrMode != FTDF_NO_ADDRESS && dstAddrMode == FTDF_NO_ADDRESS && !panIdCompression) - { - addSrcPANId = FTDF_TRUE; - } + else if (src_addr_mode == FTDF_SHORT_ADDRESS) { + ftdf_octet_t* short_address_ptr = (ftdf_octet_t*)&ftdf_pib.short_address; + + *tx_ptr++ = *short_address_ptr++; + *tx_ptr++ = *short_address_ptr; } - } + else if (src_addr_mode == FTDF_EXTENDED_ADDRESS) { + ftdf_octet_t* ext_address_ptr = (ftdf_octet_t*)&ftdf_pib.ext_address; + int n; - if (addSrcPANId) - { - FTDF_Octet *PANIdPtr = (FTDF_Octet *)&frameHeader->srcPANId; - - *txPtr++ = *PANIdPtr++; - *txPtr++ = *PANIdPtr; - } - - if (srcAddrMode == FTDF_SIMPLE_ADDRESS) - { - *txPtr++ = FTDF_pib.simpleAddress; - } - else if (srcAddrMode == FTDF_SHORT_ADDRESS) - { - FTDF_Octet *shortAddressPtr = (FTDF_Octet *)&FTDF_pib.shortAddress; - - *txPtr++ = *shortAddressPtr++; - *txPtr++ = *shortAddressPtr; - } - else if (srcAddrMode == FTDF_EXTENDED_ADDRESS) - { - FTDF_Octet *extAddressPtr = (FTDF_Octet *)&FTDF_pib.extAddress; - int n; - - for (n = 0; n < 8; n++) - { - *txPtr++ = *extAddressPtr++; + for (n = 0; n < 8; n++) { + *tx_ptr++ = *ext_address_ptr++; + } } - } - return txPtr; + return tx_ptr; } #endif /* !FTDF_LITE */ -FTDF_PTI FTDF_getRxPti(void) -{ -#if FTDF_USE_PTI - FTDF_PTI rx_pti; - FTDF_criticalVar(); - FTDF_enterCritical(); - rx_pti = FTDF_RxPti; - FTDF_exitCritical(); - return rx_pti; -#else - return 0; -#endif -} - -#ifdef FTDF_PHY_API -void FTDF_rxEnable(FTDF_Time rxOnDuration) +ftdf_pti_t ftdf_get_rx_pti(void) { #if dg_configCOEX_ENABLE_CONFIG - /* We do not force decision here. It will be automatically made when FTDF begins - * transaction. - */ - hw_coex_update_ftdf_pti((hw_coex_pti_t) FTDF_getRxPti(), NULL, false); -#endif - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_RXONDURATION, rxOnDuration); - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 1); -} + ftdf_pti_t rx_pti; + ftdf_critical_var(); + ftdf_enter_critical(); + rx_pti = ftdf_rx_pti; + ftdf_exit_critical(); + + return rx_pti; #else -void FTDF_processRxEnableRequest(FTDF_RxEnableRequest *rxEnableRequest) -{ - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_RXONDURATION, rxEnableRequest->rxOnDuration); - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 1); - - FTDF_RxEnableConfirm *rxEnableConfirm = - (FTDF_RxEnableConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_RxEnableConfirm)); - - rxEnableConfirm->msgId = FTDF_RX_ENABLE_CONFIRM; - rxEnableConfirm->status = FTDF_SUCCESS; - - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) rxEnableRequest); - FTDF_RCV_MSG((FTDF_MsgBuffer *) rxEnableConfirm); + return 0; +#endif } -#endif /* FTDF_PHY_API */ - -FTDF_Octet *FTDF_getFrameHeader(FTDF_Octet *rxBuffer, - FTDF_FrameHeader *frameHeader) -{ - FTDF_FrameType frameType = *rxBuffer & 0x07; - uint8_t frameVersion = 0; - FTDF_Bitmap8 options = 0; - FTDF_AddressMode dstAddrMode; - FTDF_AddressMode srcAddrMode; - FTDF_Boolean panIdCompression = FTDF_FALSE; - FTDF_Boolean panIdPresent = FTDF_FALSE; - - if (frameType == FTDF_MULTIPURPOSE_FRAME) - { - dstAddrMode = (*rxBuffer & 0x30) >> 4; - srcAddrMode = (*rxBuffer & 0xc0) >> 6; - - // Check Long Frame Control - if (*rxBuffer & 0x08) - { - rxBuffer++; - - panIdPresent = *rxBuffer & 0x01; - - if (*rxBuffer & 0x02) - { - options |= FTDF_OPT_SECURITY_ENABLED; - } - - if (*rxBuffer & 0x04) - { - options |= FTDF_OPT_SEQ_NR_SUPPRESSED; - } - - if (*rxBuffer & 0x08) - { - options |= FTDF_OPT_FRAME_PENDING; - } - - if (*rxBuffer & 0x40) - { - options |= FTDF_OPT_ACK_REQUESTED; - } - - if (*rxBuffer & 0x80) - { - options |= FTDF_OPT_IES_PRESENT; - } - - frameVersion = 0; - - frameHeader->frameVersion = FTDF_FRAME_VERSION_E; - - rxBuffer++; - } - else - { - rxBuffer++; - } - } - else - { - if (*rxBuffer & 0x08) - { - options |= FTDF_OPT_SECURITY_ENABLED; - } - - if (*rxBuffer & 0x10) - { - options |= FTDF_OPT_FRAME_PENDING; - } - - if (*rxBuffer & 0x20) - { - options |= FTDF_OPT_ACK_REQUESTED; - } - - panIdCompression = *rxBuffer & 0x40; - - rxBuffer++; - - frameVersion = (*rxBuffer & 0x30) >> 4; - - if (frameVersion == 0x02) - { - if (*rxBuffer & 0x01) - { - options |= FTDF_OPT_SEQ_NR_SUPPRESSED; - } - - if (*rxBuffer & 0x02) - { - options |= FTDF_OPT_IES_PRESENT; - } - - frameHeader->frameVersion = FTDF_FRAME_VERSION_E; - } - else if (frameVersion == 0x01) - { - frameHeader->frameVersion = FTDF_FRAME_VERSION_2011; - } - else if (frameVersion == 0x00) - { - frameHeader->frameVersion = FTDF_FRAME_VERSION_2003; - } - else - { - frameHeader->frameVersion = FTDF_FRAME_VERSION_NOT_SUPPORTED; - return rxBuffer; - } - - dstAddrMode = (*rxBuffer & 0x0c) >> 2; - srcAddrMode = (*rxBuffer & 0xc0) >> 6; - - rxBuffer++; - } - - if ((options & FTDF_OPT_SEQ_NR_SUPPRESSED) == 0) - { - frameHeader->SN = *rxBuffer++; - } - - FTDF_Boolean hasDstPANId = FTDF_FALSE; - - if (frameType == FTDF_MULTIPURPOSE_FRAME) - { - hasDstPANId = panIdPresent; - } - else - { - if (frameVersion < 0x02) - { - if (dstAddrMode != FTDF_NO_ADDRESS) - { - hasDstPANId = FTDF_TRUE; - } - } - else - { - if ((srcAddrMode == FTDF_NO_ADDRESS && dstAddrMode == FTDF_NO_ADDRESS && panIdCompression) || - (srcAddrMode == FTDF_NO_ADDRESS && dstAddrMode != FTDF_NO_ADDRESS && !panIdCompression) || - (srcAddrMode != FTDF_NO_ADDRESS && dstAddrMode != FTDF_NO_ADDRESS && !panIdCompression)) - { - hasDstPANId = FTDF_TRUE; - } - } - } - - if (hasDstPANId) - { - FTDF_Octet *PANIdPtr = (FTDF_Octet *) &frameHeader->dstPANId; - - *PANIdPtr++ = *rxBuffer++; - *PANIdPtr = *rxBuffer++; - } - - if (dstAddrMode == FTDF_SIMPLE_ADDRESS) - { - frameHeader->dstAddr.simpleAddress = *rxBuffer++; - } - else if (dstAddrMode == FTDF_SHORT_ADDRESS) - { - FTDF_Octet *shortAddressPtr = (FTDF_Octet *)&frameHeader->dstAddr.shortAddress; - - *shortAddressPtr++ = *rxBuffer++; - *shortAddressPtr = *rxBuffer++; - } - else if (dstAddrMode == FTDF_EXTENDED_ADDRESS) - { - FTDF_Octet *extAddressPtr = (FTDF_Octet *)&frameHeader->dstAddr.extAddress; - int n; - - for (n = 0; n < 8; n++) - { - *extAddressPtr++ = *rxBuffer++; - } - } - - FTDF_Boolean hasSrcPANId = FTDF_FALSE; - - if (frameVersion < 0x02 && frameType != FTDF_MULTIPURPOSE_FRAME) - { - if (srcAddrMode != FTDF_NO_ADDRESS && !panIdCompression) - { - hasSrcPANId = FTDF_TRUE; - } - } - else - { - if (srcAddrMode != FTDF_NO_ADDRESS && dstAddrMode == FTDF_NO_ADDRESS && !panIdCompression) - { - hasSrcPANId = FTDF_TRUE; - } - } - - if (hasSrcPANId) - { - FTDF_Octet *PANIdPtr = (FTDF_Octet *) &frameHeader->srcPANId; - - *PANIdPtr++ = *rxBuffer++; - *PANIdPtr = *rxBuffer++; - } - else - { - frameHeader->srcPANId = frameHeader->dstPANId; - } - - if (srcAddrMode == FTDF_SIMPLE_ADDRESS) - { - frameHeader->srcAddr.simpleAddress = *rxBuffer++; - } - else if (srcAddrMode == FTDF_SHORT_ADDRESS) - { - FTDF_Octet *shortAddressPtr = (FTDF_Octet *)&frameHeader->srcAddr.shortAddress; - - *shortAddressPtr++ = *rxBuffer++; - *shortAddressPtr = *rxBuffer++; - } - else if (srcAddrMode == FTDF_EXTENDED_ADDRESS) - { - FTDF_Octet *extAddressPtr = (FTDF_Octet *)&frameHeader->srcAddr.extAddress; - int n; - - for (n = 0; n < 8; n++) - { - *extAddressPtr++ = *rxBuffer++; - } - } - - frameHeader->frameType = frameType; - frameHeader->options = options; - frameHeader->dstAddrMode = dstAddrMode; - frameHeader->srcAddrMode = srcAddrMode; - - return rxBuffer; -} - -#ifndef FTDF_LITE -void FTDF_processNextRequest(void) -{ -#ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - FTDF_MsgBuffer *request = FTDF_tschGetPending(FTDF_tschSlotLink->request); - - FTDF_tschSlotLink->request = NULL; - - FTDF_scheduleTsch(request); - - return; - } - -#endif /* FTDF_NO_TSCH */ - - while (FTDF_reqCurrent == NULL) - { - FTDF_MsgBuffer *request = FTDF_dequeueReqTail(&FTDF_reqQueue); - - if (request) - { - FTDF_processRequest(request); - } - else - { - break; - } - } -} -#endif /* !FTDF_LITE */ - -static void processRxFrame(int readBuf) -{ - static FTDF_PANDescriptor PANDescriptor; - static FTDF_Address pendAddrList[ 7 ]; - - FTDF_FrameHeader *frameHeader = &FTDF_fh; -#ifndef FTDF_LITE - FTDF_SecurityHeader *securityHeader = &FTDF_sh; -#endif /* !FTDF_LITE */ - - uint8_t pendAddrSpec = 0; - - FTDF_Octet *rxBuffer = - (FTDF_Octet *)(IND_R_FTDF_RX_RAM_RX_FIFO + (intptr_t) readBuf * FTDF_BUFFER_LENGTH); - FTDF_Octet *rxPtr = rxBuffer; - FTDF_DataLength frameLen = *rxPtr++; - - if (FTDF_transparentMode) - { - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.RXSuccessCount++; - } - - uint32_t rxMeta1 = *FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_RX_META_1, (intptr_t)readBuf); - FTDF_LinkQuality lqi = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_QUALITY_INDICATOR, readBuf); - FTDF_Bitmap32 status = FTDF_TRANSPARENT_RCV_SUCCESSFUL; - - status |= rxMeta1 & MSK_F_FTDF_RETENTION_RAM_CRC16_ERROR ? FTDF_TRANSPARENT_RCV_CRC_ERROR : 0; - status |= rxMeta1 & MSK_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR ? FTDF_TRANSPARENT_RCV_RES_FRAMETYPE : 0; - status |= rxMeta1 & MSK_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR ? FTDF_TRANSPARENT_RCV_RES_FRAME_VERSION : 0; - status |= rxMeta1 & MSK_F_FTDF_RETENTION_RAM_DPANID_ERROR ? FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID : 0; - status |= rxMeta1 & MSK_F_FTDF_RETENTION_RAM_DADDR_ERROR ? FTDF_TRANSPARENT_RCV_UNEXP_DST_ADDR : 0; - - FTDF_RCV_FRAME_TRANSPARENT(frameLen, rxPtr, status, lqi); - -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - - if ((FTDF_transparentModeOptions & FTDF_TRANSPARENT_WAIT_FOR_ACK)) - { - FTDF_getFrameHeader(rxPtr, frameHeader); - - if (frameHeader->frameType == FTDF_ACKNOWLEDGEMENT_FRAME && - (status == FTDF_TRANSPARENT_RCV_SUCCESSFUL)) - { - -#ifndef FTDF_PHY_API - volatile uint32_t *txFlagS = FTDF_GET_REG_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_S, FTDF_TX_DATA_BUFFER); - - while (*txFlagS & MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT) - { } - - // It is required to call FTDF_processTxEvent here because an RX ack generates two events - // The RX event is raised first, then after an IFS the TX event is raised. However, - // the FTDF_processNextRequest requires that both events have been handled. - FTDF_processTxEvent(); -#endif /* !FTDF_PHY_API */ - - FTDF_SN SN = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_MACSN, FTDF_TX_DATA_BUFFER); #ifdef FTDF_PHY_API - FTDF_criticalVar(); - FTDF_enterCritical(); - - if (FTDF_txInProgress && - frameHeader->SN == SN) - { - FTDF_exitCritical(); - return; - } - - FTDF_exitCritical(); -#else - - if (FTDF_reqCurrent && - frameHeader->SN == SN) - { - FTDF_TransparentRequest *transparentRequest = (FTDF_TransparentRequest *) FTDF_reqCurrent; - - FTDF_criticalVar(); - FTDF_enterCritical(); - FTDF_reqCurrent = NULL; - FTDF_exitCritical(); - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparentRequest->handle, FTDF_TRANSPARENT_SEND_SUCCESSFUL); - - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) transparentRequest); - - return; - } - -#endif /* FTDF_PHY_API */ - } - } - -#endif /* FTDF_TRANSPARENT_USE_WAIT_FOR_ACK */ - return; - } - -#ifndef FTDF_LITE - rxPtr = FTDF_getFrameHeader(rxPtr, frameHeader); - -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_MANUAL - - if (frameHeader->options & FTDF_OPT_ACK_REQUESTED) - { - int n; - FTDF_Boolean addressFound = FTDF_FALSE; - - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) - { - if (FTDF_txPendingList[ n ].addrMode == frameHeader->srcAddrMode && - FTDF_txPendingList[ n ].PANId == frameHeader->srcPANId) - { - if (frameHeader->srcAddrMode == FTDF_SHORT_ADDRESS) - { - if (FTDF_txPendingList[ n ].addr.shortAddress == - frameHeader->srcAddr.shortAddress) - { - addressFound = FTDF_TRUE; - break; - } - } - else if (frameHeader->srcAddrMode == FTDF_EXTENDED_ADDRESS) - { - if (FTDF_txPendingList[ n ].addr.extAddress == - frameHeader->srcAddr.extAddress) - { - addressFound = FTDF_TRUE; - break; - } - } - else - { - // Invalid srcAddrMode - return; - } - } - } - - if (addressFound) - { - FTDF_fpprSetMode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); - } - else - { - FTDF_fpprSetMode(FTDF_FALSE, FTDF_TRUE, FTDF_FALSE); - } - } - +void ftdf_rx_enable(ftdf_time_t rx_on_duration) +{ +#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI + /* We do not force decision here. It will be automatically made when FTDF begins + * transaction. + */ + hw_coex_update_ftdf_pti((hw_coex_pti_t) ftdf_get_rx_pti(), NULL, false); #endif - if (frameHeader->frameVersion == FTDF_FRAME_VERSION_NOT_SUPPORTED) - { - return; - } + ftdf_set_link_quality_mode(); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 0); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXONDURATION, rx_on_duration); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 1); +} +#else +void ftdf_process_rx_enable_request(ftdf_rx_enable_request_t *rx_enable_request) +{ + ftdf_set_link_quality_mode(); + + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 0); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXONDURATION, rx_enable_request->rx_on_duration); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 1); + + ftdf_rx_enable_confirm_t *rx_enable_confirm = + (ftdf_rx_enable_confirm_t *) FTDF_GET_MSG_BUFFER(sizeof(ftdf_rx_enable_confirm_t)); + + rx_enable_confirm->msg_id = FTDF_RX_ENABLE_CONFIRM; + rx_enable_confirm->status = FTDF_SUCCESS; + + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t *)rx_enable_request); + FTDF_RCV_MSG((ftdf_msg_buffer_t *)rx_enable_confirm); +} +#endif /* FTDF_PHY_API */ + +ftdf_octet_t *ftdf_get_frame_header(ftdf_octet_t *rx_buffer, + ftdf_frame_header_t* frame_header) +{ + ftdf_frame_type_t frame_type = *rx_buffer & 0x07; + uint8_t frame_version = 0x00; + ftdf_bitmap8_t options = 0; + ftdf_address_mode_t dst_addr_mode; + ftdf_address_mode_t src_addr_mode; + ftdf_boolean_t pan_id_compression = FTDF_FALSE; + ftdf_boolean_t pan_id_present = FTDF_FALSE; + + if (frame_type == FTDF_MULTIPURPOSE_FRAME) { + dst_addr_mode = (*rx_buffer & 0x30) >> 4; + src_addr_mode = (*rx_buffer & 0xc0) >> 6; + + /* Check Long Frame Control */ + if (*rx_buffer & 0x08) { + rx_buffer++; + + pan_id_present = *rx_buffer & 0x01; + + if (*rx_buffer & 0x02) { + options |= FTDF_OPT_SECURITY_ENABLED; + } + + if (*rx_buffer & 0x04) { + options |= FTDF_OPT_SEQ_NR_SUPPRESSED; + } + + if (*rx_buffer & 0x08) { + options |= FTDF_OPT_FRAME_PENDING; + } + + if (*rx_buffer & 0x40) { + options |= FTDF_OPT_ACK_REQUESTED; + } + + if (*rx_buffer & 0x80) { + options |= FTDF_OPT_IES_PRESENT; + } + + frame_version = 0x00; + + frame_header->frame_version = FTDF_FRAME_VERSION_E; + + rx_buffer++; + } else { + rx_buffer++; + } + + } else { + + if (*rx_buffer & 0x08) { + options |= FTDF_OPT_SECURITY_ENABLED; + } + + if (*rx_buffer & 0x10) { + options |= FTDF_OPT_FRAME_PENDING; + } + + if (*rx_buffer & 0x20) { + options |= FTDF_OPT_ACK_REQUESTED; + } + + pan_id_compression = *rx_buffer & 0x40; + + rx_buffer++; + + frame_version = (*rx_buffer & 0x30) >> 4; + + if (frame_version == 0x02) { + if (*rx_buffer & 0x01) { + options |= FTDF_OPT_SEQ_NR_SUPPRESSED; + } + + if (*rx_buffer & 0x02) { + options |= FTDF_OPT_IES_PRESENT; + } + + frame_header->frame_version = FTDF_FRAME_VERSION_E; + } else if (frame_version == 0x01) { + frame_header->frame_version = FTDF_FRAME_VERSION_2011; + } else if (frame_version == 0x00) { + frame_header->frame_version = FTDF_FRAME_VERSION_2003; + } else { + frame_header->frame_version = FTDF_FRAME_VERSION_NOT_SUPPORTED; + return rx_buffer; + } + + dst_addr_mode = (*rx_buffer & 0x0c) >> 2; + src_addr_mode = (*rx_buffer & 0xc0) >> 6; + + rx_buffer++; + } + + if ((options & FTDF_OPT_SEQ_NR_SUPPRESSED) == 0) { + frame_header->sn = *rx_buffer++; + } + + ftdf_boolean_t has_dstpan_id = FTDF_FALSE; + + if (frame_type == FTDF_MULTIPURPOSE_FRAME) { + has_dstpan_id = pan_id_present; + } else { + + if (frame_version < 0x02) { + if (dst_addr_mode != FTDF_NO_ADDRESS) { + has_dstpan_id = FTDF_TRUE; + } + + } else { + + if (((src_addr_mode == FTDF_NO_ADDRESS) && + (dst_addr_mode == FTDF_NO_ADDRESS) && pan_id_compression) || + ((src_addr_mode == FTDF_NO_ADDRESS) && + (dst_addr_mode != FTDF_NO_ADDRESS) && !pan_id_compression) || + ((src_addr_mode != FTDF_NO_ADDRESS) && + (dst_addr_mode != FTDF_NO_ADDRESS) && !pan_id_compression)) { + + has_dstpan_id = FTDF_TRUE; + } + } + } + + if (has_dstpan_id) { + ftdf_octet_t *pan_id_ptr = (ftdf_octet_t*)&frame_header->dst_pan_id; + + *pan_id_ptr++ = *rx_buffer++; + *pan_id_ptr = *rx_buffer++; + } + + if (dst_addr_mode == FTDF_SIMPLE_ADDRESS) { + frame_header->dst_addr.simple_address = *rx_buffer++; + } else if (dst_addr_mode == FTDF_SHORT_ADDRESS) { + ftdf_octet_t *short_address_ptr = (ftdf_octet_t*)&frame_header->dst_addr.short_address; + + *short_address_ptr++ = *rx_buffer++; + *short_address_ptr = *rx_buffer++; + } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { + ftdf_octet_t *ext_address_ptr = (ftdf_octet_t*)&frame_header->dst_addr.ext_address; + int n; + + for (n = 0; n < 8; n++) { + *ext_address_ptr++ = *rx_buffer++; + } + } + + ftdf_boolean_t has_srcpan_id = FTDF_FALSE; + + if (frame_version < 0x02 && frame_type != FTDF_MULTIPURPOSE_FRAME) { + if (src_addr_mode != FTDF_NO_ADDRESS && !pan_id_compression) { + has_srcpan_id = FTDF_TRUE; + } + + } else { + + if ((src_addr_mode != FTDF_NO_ADDRESS) && (dst_addr_mode == FTDF_NO_ADDRESS) && + !pan_id_compression) { + + has_srcpan_id = FTDF_TRUE; + } + } + + if (has_srcpan_id) { + ftdf_octet_t *pan_id_ptr = (ftdf_octet_t*)&frame_header->src_pan_id; + + *pan_id_ptr++ = *rx_buffer++; + *pan_id_ptr = *rx_buffer++; + } else { + frame_header->src_pan_id = frame_header->dst_pan_id; + } + + if (src_addr_mode == FTDF_SIMPLE_ADDRESS) { + frame_header->src_addr.simple_address = *rx_buffer++; + } else if (src_addr_mode == FTDF_SHORT_ADDRESS) { + ftdf_octet_t *short_address_ptr = + (ftdf_octet_t*)&frame_header->src_addr.short_address; + + *short_address_ptr++ = *rx_buffer++; + *short_address_ptr = *rx_buffer++; + } else if (src_addr_mode == FTDF_EXTENDED_ADDRESS) { + ftdf_octet_t* ext_address_ptr = (ftdf_octet_t*)&frame_header->src_addr.ext_address; + int n; + + for (n = 0; n < 8; n++) { + *ext_address_ptr++ = *rx_buffer++; + } + } + + frame_header->frame_type = frame_type; + frame_header->options = options; + frame_header->dst_addr_mode = dst_addr_mode; + frame_header->src_addr_mode = src_addr_mode; + + return rx_buffer; +} + +#ifndef FTDF_LITE +void ftdf_process_next_request(void) +{ +#ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled) { + ftdf_msg_buffer_t *request = ftdf_tsch_get_pending(ftdf_tsch_slot_link->request); + + ftdf_tsch_slot_link->request = NULL; + + ftdf_schedule_tsch(request); + + return; + } +#endif /* FTDF_NO_TSCH */ + + while (ftdf_req_current == NULL) { + ftdf_msg_buffer_t *request = ftdf_dequeue_req_tail(&ftdf_req_queue); + + if (request) { + ftdf_process_request(request); + } else { + break; + } + } +} +#endif /* !FTDF_LITE */ + +static void process_rx_frame(int read_buf) +{ + static ftdf_pan_descriptor_t pan_descriptor; + static ftdf_address_t pend_addr_list[7]; + + ftdf_frame_header_t *frame_header = &ftdf_fh; +#ifndef FTDF_LITE + ftdf_security_header *security_header = &ftdf_sh; +#endif /* !FTDF_LITE */ + + uint8_t pend_addr_spec = 0; + + ftdf_octet_t *rx_buffer = + (ftdf_octet_t*) (&FTDF->FTDF_RX_FIFO_0_0_REG) + (read_buf * FTDF_BUFFER_LENGTH); + ftdf_octet_t *rx_ptr = rx_buffer; + ftdf_data_length_t frameLen = *rx_ptr++; + + if (ftdf_transparent_mode) { + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.rx_success_count++; + } + + uint32_t rx_meta_1 = 0; + + ftdf_bitmap32_t status = FTDF_TRANSPARENT_RCV_SUCCESSFUL; + + switch (read_buf) { + case 0: + rx_meta_1 = FTDF->FTDF_RX_META_1_0_REG; + break; + case 1: + rx_meta_1 = FTDF->FTDF_RX_META_1_1_REG; + break; + case 2: + rx_meta_1 = FTDF->FTDF_RX_META_1_2_REG; + break; + case 3: + rx_meta_1 = FTDF->FTDF_RX_META_1_3_REG; + break; + case 4: + rx_meta_1 = FTDF->FTDF_RX_META_1_4_REG; + break; + case 5: + rx_meta_1 = FTDF->FTDF_RX_META_1_5_REG; + break; + case 6: + rx_meta_1 = FTDF->FTDF_RX_META_1_6_REG; + break; + case 7: + rx_meta_1 = FTDF->FTDF_RX_META_1_7_REG; + break; + default: + OS_ASSERT(0); + } + + status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, CRC16_ERROR) ? + FTDF_TRANSPARENT_RCV_CRC_ERROR : 0; + status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, RES_FRM_TYPE_ERROR) ? + FTDF_TRANSPARENT_RCV_RES_FRAMETYPE : 0; + status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, RES_FRM_VERSION_ERROR) ? + FTDF_TRANSPARENT_RCV_RES_FRAME_VERSION : 0; + status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, DPANID_ERROR) ? + FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID : 0; + status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, DADDR_ERROR) ? + FTDF_TRANSPARENT_RCV_UNEXP_DST_ADDR : 0; + +#ifdef FTDF_PASS_ACK_FRAME + FTDF_RCV_FRAME_TRANSPARENT(frameLen, rx_ptr, status, + REG_GET_FIELD(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR, rx_meta_1)); +#endif /* FTDF_PASS_ACK_FRAME */ + +#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK + if ((ftdf_transparent_mode_options & FTDF_TRANSPARENT_WAIT_FOR_ACK)) { + + ftdf_get_frame_header(rx_ptr, frame_header); + + if ((frame_header->frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) && + (status == FTDF_TRANSPARENT_RCV_SUCCESSFUL)) { + +#ifndef FTDF_PHY_API + while (REG_GETF(FTDF, FTDF_TX_FLAG_S_0_REG, TX_FLAG_STAT)) {} + + /* It is required to call FTDF_processTxEvent here because an RX ack + * generates two events. The RX event is raised first, then after + * an IFS the TX event is raised. However, the ftdf_process_next_request + * requires that both events have been handled. */ + ftdf_process_tx_event(); +#endif /* !FTDF_PHY_API */ + + ftdf_sn_t SN = REG_GETF(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN); + +#ifdef FTDF_PHY_API + ftdf_critical_var(); + ftdf_enter_critical(); + if (ftdf_tx_in_progress && (frame_header->sn == SN)) { + ftdf_exit_critical(); + return; + } + + ftdf_exit_critical(); +#else + if (ftdf_req_current && (frame_header->sn == SN)) { + + ftdf_transparent_request_t *transparent_request = + (ftdf_transparent_request_t*)ftdf_req_current; + + ftdf_critical_var(); + ftdf_enter_critical(); + ftdf_req_current = NULL; + ftdf_exit_critical(); + FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, + FTDF_TRANSPARENT_SEND_SUCCESSFUL); + + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t *)transparent_request); + + return; + } +#endif /* FTDF_PHY_API */ + } + } +#endif /* FTDF_TRANSPARENT_USE_WAIT_FOR_ACK */ +#ifndef FTDF_PASS_ACK_FRAME + FTDF_RCV_FRAME_TRANSPARENT(frameLen, rx_ptr, status, + REG_GET_FIELD(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR, rx_meta_1)); +#endif /* !FTDF_PASS_ACK_FRAME */ + + return; + } + +#ifndef FTDF_LITE + rx_ptr = ftdf_get_frame_header(rx_ptr, frame_header); + +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_MANUAL + if (frame_header->options & FTDF_OPT_ACK_REQUESTED) { + int n; + ftdf_boolean_t address_found = FTDF_FALSE; + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { + if (ftdf_tx_pending_list[n].addr_mode == frame_header->src_addr_mode && + ftdf_tx_pending_list[n].pan_id == frame_header->src_pan_id) { + if (frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) { + if (ftdf_tx_pending_list[n].addr.short_address == frame_header->src_addr.short_address) { + address_found = FTDF_TRUE; + break; + } + } else if (frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) { + if (ftdf_tx_pending_list[n].addr.ext_address == frame_header->src_addr.ext_address) { + address_found = FTDF_TRUE; + break; + } + } else { + // Invalid srcAddrMode + return; + } + } + } + if (address_found) { + ftdf_fppr_set_mode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); + } else { + ftdf_fppr_set_mode(FTDF_FALSE, FTDF_TRUE, FTDF_FALSE); + } + } +#endif + + if (frame_header->frame_version == FTDF_FRAME_VERSION_NOT_SUPPORTED) { + return; + } #if defined(FTDF_NO_CSL) && defined(FTDF_NO_TSCH) - else if (frameHeader->frameVersion == FTDF_FRAME_VERSION_E || - frameHeader->frameType == FTDF_MULTIPURPOSE_FRAME) - { - return; - } + else if ((frame_header->frame_version == FTDF_FRAME_VERSION_E) || + (frame_header->frame_type == FTDF_MULTIPURPOSE_FRAME)) { + return; + } #endif /* FTDF_NO_CSL && FTDF_NO_TSCH */ - FTDF_FrameType frameType = frameHeader->frameType; - FTDF_Boolean duplicate = FTDF_FALSE; + ftdf_frame_type_t frame_type = frame_header->frame_type; + ftdf_boolean_t duplicate = FTDF_FALSE; - if ((frameHeader->options & FTDF_OPT_SEQ_NR_SUPPRESSED) == 0 && - frameHeader->srcAddrMode != FTDF_NO_ADDRESS) - { - FTDF_Time timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_RX_TIMESTAMP, readBuf); - FTDF_SNSel snSel = FTDF_SN_SEL_DSN; - FTDF_Boolean drop; + if (((frame_header->options & FTDF_OPT_SEQ_NR_SUPPRESSED) == 0) && + (frame_header->src_addr_mode != FTDF_NO_ADDRESS)) { - if ((FTDF_pib.tschEnabled || frameHeader->frameVersion == FTDF_FRAME_VERSION_E) && - (frameHeader->options & FTDF_OPT_ACK_REQUESTED)) - { - drop = FTDF_FALSE; - } - else - { - drop = FTDF_TRUE; - } + ftdf_time_t timestamp; + ftdf_sn_sel sn_sel = FTDF_SN_SEL_DSN; + ftdf_boolean_t drop; - if (frameType == FTDF_BEACON_FRAME) - { - snSel = frameHeader->frameVersion == FTDF_FRAME_VERSION_E ? FTDF_SN_SEL_EBSN : FTDF_SN_SEL_BSN; - } - - uint8_t i; - - for (i = 0; i < FTDF_NR_OF_RX_ADDRS; i++) - { - // Check if entry is empty or matches - if (FTDF_rxa[ i ].addrMode == FTDF_NO_ADDRESS || - (FTDF_rxa[ i ].addrMode == frameHeader->srcAddrMode && - ((frameHeader->srcAddrMode == FTDF_SHORT_ADDRESS && - frameHeader->srcAddr.shortAddress == FTDF_rxa[ i ].addr.shortAddress) || - (frameHeader->srcAddrMode == FTDF_EXTENDED_ADDRESS && - frameHeader->srcAddr.extAddress == FTDF_rxa[ i ].addr.extAddress)))) - { - break; - } - } - - if (i < FTDF_NR_OF_RX_ADDRS) - { - if (FTDF_rxa[ i ].addrMode != FTDF_NO_ADDRESS) - { - switch (snSel) - { - case FTDF_SN_SEL_DSN: - - if (FTDF_rxa[ i ].dsnValid == FTDF_TRUE) - { - if (frameHeader->SN == FTDF_rxa[ i ].dsn) - { - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.duplicateFrameCount++; - } - - if (drop) - { - return; - } - - duplicate = FTDF_TRUE; - } - } - else - { - FTDF_rxa[ i ].dsnValid = FTDF_TRUE; - } - - FTDF_rxa[ i ].dsn = frameHeader->SN; - break; - - case FTDF_SN_SEL_BSN: - - if (FTDF_rxa[ i ].bsnValid == FTDF_TRUE) - { - if (frameHeader->SN == FTDF_rxa[ i ].bsn) - { - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.duplicateFrameCount++; - } - - if (drop) - { - return; - } - - duplicate = FTDF_TRUE; - } - } - else - { - FTDF_rxa[ i ].bsnValid = FTDF_TRUE; - } - - FTDF_rxa[ i ].bsn = frameHeader->SN; - break; - - case FTDF_SN_SEL_EBSN: - - if (FTDF_rxa[ i ].ebsnValid == FTDF_TRUE) - { - if (frameHeader->SN == FTDF_rxa[ i ].ebsn) - { - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.duplicateFrameCount++; - } - - if (drop) - { - return; - } - - duplicate = FTDF_TRUE; - } - } - else - { - FTDF_rxa[ i ].ebsnValid = FTDF_TRUE; - } - - FTDF_rxa[ i ].ebsn = frameHeader->SN; - break; + switch(read_buf) { + case 0: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); + break; + case 1: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); + break; + case 2: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); + break; + case 3: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); + break; + case 4: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); + break; + case 5: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); + break; + case 6: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); + break; + case 7: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); + break; + default: + OS_ASSERT(0); } - } - else - { - FTDF_rxa[ i ].addrMode = frameHeader->srcAddrMode; - FTDF_rxa[ i ].addr = frameHeader->srcAddr; - switch (snSel) - { - case FTDF_SN_SEL_DSN: - FTDF_rxa[ i ].dsnValid = FTDF_TRUE; - FTDF_rxa[ i ].dsn = frameHeader->SN; - break; + if ((ftdf_pib.tsch_enabled || (frame_header->frame_version == FTDF_FRAME_VERSION_E)) && + (frame_header->options & FTDF_OPT_ACK_REQUESTED)) { - case FTDF_SN_SEL_BSN: - FTDF_rxa[ i ].bsnValid = FTDF_TRUE; - FTDF_rxa[ i ].bsn = frameHeader->SN; - break; - - case FTDF_SN_SEL_EBSN: - FTDF_rxa[ i ].ebsnValid = FTDF_TRUE; - FTDF_rxa[ i ].ebsn = frameHeader->SN; - break; + drop = FTDF_FALSE; + } else { + drop = FTDF_TRUE; } - } - FTDF_rxa[ i ].timestamp = timestamp; - } - else - { - // find oldest entry and overwrite it - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_Time delta, greatestDelta = 0; - uint8_t entry = 0; - - for (i = 0; i < FTDF_NR_OF_RX_ADDRS; i++) - { - delta = curTime - FTDF_rxa[ i ].timestamp; - - if (delta > greatestDelta) - { - greatestDelta = delta; - entry = i; + if (frame_type == FTDF_BEACON_FRAME) { + sn_sel = (frame_header->frame_version == FTDF_FRAME_VERSION_E) ? + FTDF_SN_SEL_EBSN : FTDF_SN_SEL_BSN; } - } - FTDF_rxa[ entry ].addrMode = frameHeader->srcAddrMode; - FTDF_rxa[ entry ].addr = frameHeader->srcAddr; + uint8_t i; - switch (snSel) - { - case FTDF_SN_SEL_DSN: - FTDF_rxa[ entry ].bsnValid = FTDF_FALSE; - FTDF_rxa[ entry ].ebsnValid = FTDF_FALSE; - FTDF_rxa[ entry ].dsnValid = FTDF_TRUE; - FTDF_rxa[ entry ].dsn = frameHeader->SN; - break; + for (i = 0; i < FTDF_NR_OF_RX_ADDRS; i++) { - case FTDF_SN_SEL_BSN: - FTDF_rxa[ entry ].dsnValid = FTDF_FALSE; - FTDF_rxa[ entry ].ebsnValid = FTDF_FALSE; - FTDF_rxa[ entry ].bsnValid = FTDF_TRUE; - FTDF_rxa[ entry ].bsn = frameHeader->SN; - break; + /* Check if entry is empty or matches */ + if ((ftdf_rxa[i].addr_mode == FTDF_NO_ADDRESS) || + ((ftdf_rxa[i].addr_mode == frame_header->src_addr_mode) && + (((frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) && + (frame_header->src_addr.short_address == ftdf_rxa[i].addr.short_address)) || + ((frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) && + (frame_header->src_addr.ext_address == ftdf_rxa[i].addr.ext_address))))) { - case FTDF_SN_SEL_EBSN: - FTDF_rxa[ entry ].dsnValid = FTDF_FALSE; - FTDF_rxa[ entry ].bsnValid = FTDF_FALSE; - FTDF_rxa[ entry ].ebsnValid = FTDF_TRUE; - FTDF_rxa[ entry ].ebsn = frameHeader->SN; - break; - } + break; + } + } + + if (i < FTDF_NR_OF_RX_ADDRS) { + if (ftdf_rxa[i].addr_mode != FTDF_NO_ADDRESS) { + switch (sn_sel) { + case FTDF_SN_SEL_DSN: + + if (ftdf_rxa[i].dsn_valid == FTDF_TRUE) { + if (frame_header->sn == ftdf_rxa[i].dsn) { + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.duplicate_frame_count++; + } + + if (drop) { + return; + } + + duplicate = FTDF_TRUE; + } + } else { + ftdf_rxa[i].dsn_valid = FTDF_TRUE; + } + + ftdf_rxa[i].dsn = frame_header->sn; + break; + case FTDF_SN_SEL_BSN: + + if (ftdf_rxa[i].bsn_valid == FTDF_TRUE) { + if (frame_header->sn == ftdf_rxa[i].bsn) { + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.duplicate_frame_count++; + } + + if (drop) { + return; + } + + duplicate = FTDF_TRUE; + } + } else { + ftdf_rxa[i].bsn_valid = FTDF_TRUE; + } + + ftdf_rxa[i].bsn = frame_header->sn; + break; + case FTDF_SN_SEL_EBSN: + + if (ftdf_rxa[i].ebsn_valid == FTDF_TRUE) { + if (frame_header->sn == ftdf_rxa[i].eb_sn) { + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.duplicate_frame_count++; + } + + if (drop) { + return; + } + + duplicate = FTDF_TRUE; + } + } else { + ftdf_rxa[i].ebsn_valid = FTDF_TRUE; + } + + ftdf_rxa[i].eb_sn = frame_header->sn; + break; + } + } else { + ftdf_rxa[i].addr_mode = frame_header->src_addr_mode; + ftdf_rxa[i].addr = frame_header->src_addr; + + switch (sn_sel) { + case FTDF_SN_SEL_DSN: + ftdf_rxa[i].dsn_valid = FTDF_TRUE; + ftdf_rxa[i].dsn = frame_header->sn; + break; + case FTDF_SN_SEL_BSN: + ftdf_rxa[i].bsn_valid = FTDF_TRUE; + ftdf_rxa[i].bsn = frame_header->sn; + break; + case FTDF_SN_SEL_EBSN: + ftdf_rxa[i].ebsn_valid = FTDF_TRUE; + ftdf_rxa[i].eb_sn = frame_header->sn; + break; + } + } + + ftdf_rxa[i].timestamp = timestamp; + } else { + /* find oldest entry and overwrite it */ + ftdf_time_t cur_time = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t delta, greatest_delta = 0; + uint8_t entry = 0; + + for (i = 0; i < FTDF_NR_OF_RX_ADDRS; i++) { + delta = cur_time - ftdf_rxa[i].timestamp; + + if (delta > greatest_delta) { + greatest_delta = delta; + entry = i; + } + } + + ftdf_rxa[entry].addr_mode = frame_header->src_addr_mode; + ftdf_rxa[entry].addr = frame_header->src_addr; + + switch (sn_sel) { + case FTDF_SN_SEL_DSN: + ftdf_rxa[entry].bsn_valid = FTDF_FALSE; + ftdf_rxa[entry].ebsn_valid = FTDF_FALSE; + ftdf_rxa[entry].dsn_valid = FTDF_TRUE; + ftdf_rxa[entry].dsn = frame_header->sn; + break; + case FTDF_SN_SEL_BSN: + ftdf_rxa[entry].dsn_valid = FTDF_FALSE; + ftdf_rxa[entry].ebsn_valid = FTDF_FALSE; + ftdf_rxa[entry].bsn_valid = FTDF_TRUE; + ftdf_rxa[entry].bsn = frame_header->sn; + break; + case FTDF_SN_SEL_EBSN: + ftdf_rxa[entry].dsn_valid = FTDF_FALSE; + ftdf_rxa[entry].bsn_valid = FTDF_FALSE; + ftdf_rxa[entry].ebsn_valid = FTDF_TRUE; + ftdf_rxa[entry].eb_sn = frame_header->sn; + break; + } + } } - } - if (frameHeader->options & FTDF_OPT_SECURITY_ENABLED) - { - rxPtr = FTDF_getSecurityHeader(rxPtr, frameHeader->frameVersion, securityHeader); - } - else - { - securityHeader->securityLevel = 0; - securityHeader->keyIdMode = 0; - } + if (frame_header->options & FTDF_OPT_SECURITY_ENABLED) { + rx_ptr = ftdf_get_security_header(rx_ptr, frame_header->frame_version, security_header); + } else { + security_header->security_level = 0; + security_header->key_id_mode = 0; + } - FTDF_IEList *headerIEList = NULL; - FTDF_IEList *payloadIEList = NULL; - int micLength = FTDF_getMicLength(securityHeader->securityLevel); + ftdf_ie_list_t* header_ie_list = NULL; + ftdf_ie_list_t* payload_ie_list = NULL; + int mic_length = ftdf_get_mic_length(security_header->security_level); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (frameHeader->options & FTDF_OPT_IES_PRESENT) - { - rxPtr = - FTDF_getIes(rxPtr, rxBuffer + (frameLen - micLength - FTDF_FCS_LENGTH), &headerIEList, &payloadIEList); - } - + if (frame_header->options & FTDF_OPT_IES_PRESENT) { + rx_ptr = ftdf_get_ies(rx_ptr, rx_buffer + (frameLen - mic_length - FTDF_FCS_LENGTH), + &header_ie_list, &payload_ie_list); + } #endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - // Get start of private data (needed to unsecure a frame) - if (frameType == FTDF_MAC_COMMAND_FRAME) - { - frameHeader->commandFrameId = *rxPtr++; - } - else if (frameType == FTDF_BEACON_FRAME) - { - PANDescriptor.coordAddrMode = frameHeader->srcAddrMode; - PANDescriptor.coordPANId = frameHeader->srcPANId; - PANDescriptor.coordAddr = frameHeader->srcAddr; - PANDescriptor.channelNumber = ((FTDF_GET_FIELD(ON_OFF_REGMAP_PHYRXATTR) >> 4) & 0xf) + 11; - PANDescriptor.channelPage = 0; - PANDescriptor.timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_RX_TIMESTAMP, readBuf); - PANDescriptor.linkQuality = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_QUALITY_INDICATOR, readBuf); + /* Get start of private data (needed to unsecure a frame) */ + if (frame_type == FTDF_MAC_COMMAND_FRAME) { - FTDF_Octet *superframeSpecPtr = (FTDF_Octet *) &PANDescriptor.superframeSpec; - *superframeSpecPtr++ = *rxPtr++; - *superframeSpecPtr = *rxPtr++; + frame_header->command_frame_id = *rx_ptr++; - uint8_t gtsSpec = *rxPtr++; + } else if (frame_type == FTDF_BEACON_FRAME) { - PANDescriptor.GTSPermit = (gtsSpec & 0x08) ? FTDF_TRUE : FTDF_FALSE; - uint8_t gtsDescrCount = gtsSpec & 0x7; + pan_descriptor.coord_addr_mode = frame_header->src_addr_mode; + pan_descriptor.coord_pan_id = frame_header->src_pan_id; + pan_descriptor.coord_addr = frame_header->src_addr; + pan_descriptor.channel_number = REG_GETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN) + 11; + pan_descriptor.channel_page = 0; - if (gtsDescrCount != 0) - { - // GTS is not supported, so just skip the GTS direction and GTS list fields if present - rxPtr += (1 + (3 * gtsDescrCount)); - } - - pendAddrSpec = *rxPtr++; - uint8_t nrOfShortAddrs = pendAddrSpec & 0x07; - uint8_t nrOfExtAddrs = (pendAddrSpec & 0x70) >> 4; - - int n; - - for (n = 0; n < (nrOfShortAddrs + nrOfExtAddrs); n++) - { - if (n < nrOfShortAddrs) - { - FTDF_Octet *shortAddressPtr = (FTDF_Octet *) &pendAddrList[ n ].shortAddress; - *shortAddressPtr++ = *rxBuffer++; - *shortAddressPtr = *rxBuffer++; - } - else - { - FTDF_Octet *extAddressPtr = (FTDF_Octet *) &pendAddrList[ n ].extAddress; - int m; - - for (m = 0; m < 8; m++) - { - *extAddressPtr++ = *rxBuffer++; + switch (read_buf) { + case 0: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR); + break; + case 1: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_1_REG, QUALITY_INDICATOR); + break; + case 2: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_2_REG, QUALITY_INDICATOR); + break; + case 3: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_3_REG, QUALITY_INDICATOR); + break; + case 4: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_4_REG, QUALITY_INDICATOR); + break; + case 5: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_5_REG, QUALITY_INDICATOR); + break; + case 6: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_6_REG, QUALITY_INDICATOR); + break; + case 7: + pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); + pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_7_REG, QUALITY_INDICATOR); + break; + default: + /* Unsupported register index occurred */ + OS_ASSERT(0); } - } - } - } - else if (frameType == FTDF_ACKNOWLEDGEMENT_FRAME && - securityHeader->securityLevel != 0) - { - if (FTDF_reqCurrent) - { - switch (FTDF_reqCurrent->msgId) - { - case FTDF_DATA_REQUEST: - { - FTDF_DataRequest *dataRequest = (FTDF_DataRequest *) FTDF_reqCurrent; - frameHeader->srcPANId = dataRequest->dstPANId; - frameHeader->srcAddrMode = dataRequest->dstAddrMode; - frameHeader->srcAddr = dataRequest->dstAddr; - break; - } - case FTDF_POLL_REQUEST: - { - FTDF_PollRequest *pollRequest = (FTDF_PollRequest *) FTDF_reqCurrent; - frameHeader->srcPANId = pollRequest->coordPANId; - frameHeader->srcAddrMode = pollRequest->coordAddrMode; - frameHeader->srcAddr = pollRequest->coordAddr; - break; - } + ftdf_octet_t* superframe_spec_ptr = (ftdf_octet_t*)&pan_descriptor.superframe_spec; + *superframe_spec_ptr++ = *rx_ptr++; + *superframe_spec_ptr = *rx_ptr++; - case FTDF_ASSOCIATE_REQUEST: - { - FTDF_AssociateRequest *associateRequest = (FTDF_AssociateRequest *) FTDF_reqCurrent; - frameHeader->srcPANId = associateRequest->coordPANId; - frameHeader->srcAddrMode = associateRequest->coordAddrMode; - frameHeader->srcAddr = associateRequest->coordAddr; - break; - } + uint8_t gts_spec = *rx_ptr++; - case FTDF_DISASSOCIATE_REQUEST: - { - FTDF_DisassociateRequest *disassociateRequest = - (FTDF_DisassociateRequest *) FTDF_reqCurrent; - frameHeader->srcPANId = disassociateRequest->devicePANId; - frameHeader->srcAddrMode = disassociateRequest->deviceAddrMode; - frameHeader->srcAddr = disassociateRequest->deviceAddress; - break; - } + pan_descriptor.gts_permit = (gts_spec & 0x08) ? FTDF_TRUE : FTDF_FALSE; + uint8_t gts_descr_count = gts_spec & 0x7; - case FTDF_ASSOCIATE_RESPONSE: - { - FTDF_AssociateResponse *associateResponse = (FTDF_AssociateResponse *) FTDF_reqCurrent; - frameHeader->srcAddrMode = FTDF_EXTENDED_ADDRESS; - frameHeader->srcAddr.extAddress = associateResponse->deviceAddress; - break; - } - } - } - } + if (gts_descr_count != 0) { + /* GTS is not supported, so just skip the GTS direction and GTS list + * fields if present */ + rx_ptr += (1 + (3 * gts_descr_count)); + } - FTDF_Status status = FTDF_unsecureFrame(rxBuffer, rxPtr, frameHeader, securityHeader); + pend_addr_spec = *rx_ptr++; + uint8_t nr_of_short_addrs = pend_addr_spec & 0x07; + uint8_t nr_of_ext_addrs = (pend_addr_spec & 0x70) >> 4; - if (status != FTDF_SUCCESS) - { - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.securityFailureCount++; + int n; + + for (n = 0; n < (nr_of_short_addrs + nr_of_ext_addrs); n++) { + if (n < nr_of_short_addrs) { + + ftdf_octet_t* short_address_ptr = + (ftdf_octet_t*)&pend_addr_list[n].short_address; + *short_address_ptr++ = *rx_buffer++; + *short_address_ptr = *rx_buffer++; + + } else { + + ftdf_octet_t* ext_address_ptr = + (ftdf_octet_t*)&pend_addr_list[n].ext_address; + int m; + + for (m = 0; m < 8; m++) { + *ext_address_ptr++ = *rx_buffer++; + } + } + } + } else if ((frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) && + (security_header->security_level != 0)) { + + if (ftdf_req_current) { + switch (ftdf_req_current->msg_id) { + case FTDF_DATA_REQUEST: + { + ftdf_data_request_t *data_request = + (ftdf_data_request_t*)ftdf_req_current; + + frame_header->src_pan_id = data_request->dst_pan_id; + frame_header->src_addr_mode = data_request->dst_addr_mode; + frame_header->src_addr = data_request->dst_addr; + break; + } + case FTDF_POLL_REQUEST: + { + ftdf_poll_request_t *poll_request = + (ftdf_poll_request_t*)ftdf_req_current; + + frame_header->src_pan_id = poll_request->coord_pan_id; + frame_header->src_addr_mode = poll_request->coord_addr_mode; + frame_header->src_addr = poll_request->coord_addr; + break; + } + case FTDF_ASSOCIATE_REQUEST: + { + ftdf_associate_request_t *associate_request = + (ftdf_associate_request_t*)ftdf_req_current; + + frame_header->src_pan_id = associate_request->coord_pan_id; + frame_header->src_addr_mode = associate_request->coord_addr_mode; + frame_header->src_addr = associate_request->coord_addr; + break; + } + case FTDF_DISASSOCIATE_REQUEST: + { + ftdf_disassociate_request_t *disassociate_request = + (ftdf_disassociate_request_t*)ftdf_req_current; + + frame_header->src_pan_id = disassociate_request->device_pan_id; + frame_header->src_addr_mode = + disassociate_request->device_addr_mode; + frame_header->src_addr = disassociate_request->device_address; + break; + } + case FTDF_ASSOCIATE_RESPONSE: + { + ftdf_associate_response_t *associate_response = + (ftdf_associate_response_t*)ftdf_req_current; + + frame_header->src_addr_mode = FTDF_EXTENDED_ADDRESS; + frame_header->src_addr.ext_address = + associate_response->device_address; + break; + } + } + } } - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); + ftdf_status_t status = ftdf_unsecure_frame(rx_buffer, rx_ptr, frame_header, security_header); - // Since unsecure of acknowledgement frame is always successful, - // nothing special has to be done to get the address information correct. - FTDF_sendCommStatusIndication(FTDF_reqCurrent, status, - FTDF_pib.PANId, - frameHeader->srcAddrMode, - frameHeader->srcAddr, - frameHeader->dstAddrMode, - frameHeader->dstAddr, - securityHeader->securityLevel, - securityHeader->keyIdMode, - securityHeader->keySource, - securityHeader->keyIndex); + if (status != FTDF_SUCCESS) { + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.security_failure_count++; + } - if (frameType == FTDF_ACKNOWLEDGEMENT_FRAME && FTDF_reqCurrent) - { - sendConfirm(FTDF_NO_ACK, - FTDF_reqCurrent->msgId); + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - FTDF_processNextRequest(); + /* Since unsecure of acknowledgement frame is always successful, + * nothing special has to be done to get the address information correct. */ + ftdf_send_comm_status_indication(ftdf_req_current, status, + ftdf_pib.pan_id, + frame_header->src_addr_mode, + frame_header->src_addr, + frame_header->dst_addr_mode, + frame_header->dst_addr, + security_header->security_level, + security_header->key_id_mode, + security_header->key_source, + security_header->key_index); + + if ((frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) && ftdf_req_current) { + + send_confirm(FTDF_NO_ACK, ftdf_req_current->msg_id); + + ftdf_process_next_request(); + } + + return; } - return; - } - - if (FTDF_pib.metricsEnabled && frameType != FTDF_ACKNOWLEDGEMENT_FRAME) - { - FTDF_pib.performanceMetrics.RXSuccessCount++; - } + if (ftdf_pib.metrics_enabled && frame_type != FTDF_ACKNOWLEDGEMENT_FRAME) { + ftdf_pib.performance_metrics.rx_success_count++; + } #ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled && frame_type != FTDF_ACKNOWLEDGEMENT_FRAME) { + ftdf_time_t timestamp; - if (FTDF_pib.tschEnabled && frameType != FTDF_ACKNOWLEDGEMENT_FRAME) - { - FTDF_Time timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_RX_TIMESTAMP, readBuf); - - FTDF_correctSlotTime(timestamp); - } + switch (read_buf) { + case 0: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); + break; + case 1: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); + break; + case 2: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); + break; + case 3: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); + break; + case 4: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); + break; + case 5: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); + break; + case 6: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); + break; + case 7: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); + break; + default: + /* Unsupported register index occurred */ + OS_ASSERT(0); + } + ftdf_correct_slot_time(timestamp); + } #endif /* FTDF_NO_TSCH */ - switch (frameType) - { - case FTDF_ACKNOWLEDGEMENT_FRAME: + switch (frame_type) { + case FTDF_ACKNOWLEDGEMENT_FRAME: + if (ftdf_pib.metrics_enabled) { + if (ftdf_nr_of_retries == 0) { + ftdf_pib.performance_metrics.tx_success_count++; + } else if (ftdf_nr_of_retries == 1) { + ftdf_pib.performance_metrics.retry_count++; + } else { + ftdf_pib.performance_metrics.multiple_retry_count++; + } + } - if (FTDF_pib.metricsEnabled) - { - if (FTDF_nrOfRetries == 0) - { - FTDF_pib.performanceMetrics.TXSuccessCount++; - } - else if (FTDF_nrOfRetries == 1) - { - FTDF_pib.performanceMetrics.retryCount++; - } - else - { - FTDF_pib.performanceMetrics.multipleRetryCount++; - } + if (frame_header->frame_version == FTDF_FRAME_VERSION_E) { + ftdf_pib.traffic_counters.rx_enh_ack_frm_ok_cnt++; + } + break; + case FTDF_BEACON_FRAME: + ftdf_pib.traffic_counters.rx_beacon_frm_ok_cnt++; + break; + case FTDF_DATA_FRAME: + ftdf_pib.traffic_counters.rx_data_frm_ok_cnt++; + break; + case FTDF_MAC_COMMAND_FRAME: + ftdf_pib.traffic_counters.rx_cmd_frm_ok_cnt++; + break; + case FTDF_MULTIPURPOSE_FRAME: + ftdf_pib.traffic_counters.rx_multi_purp_frm_ok_cnt++; + break; } - if (frameHeader->frameVersion == FTDF_FRAME_VERSION_E) - { - FTDF_pib.trafficCounters.rxEnhAckFrmOkCnt++; - } + if (frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) { - break; + while (REG_GETF(FTDF, FTDF_TX_FLAG_S_0_REG, TX_FLAG_STAT)) {} - case FTDF_BEACON_FRAME: - FTDF_pib.trafficCounters.rxBeaconFrmOkCnt++; - break; + /* It is required to call ftdf_process_tx_event here because an RX ack generates two events + * The RX event is raised first, then after an IFS the TX event is raised. However, + * the ftdf_process_next_request requires that both events have been handled. */ + ftdf_process_tx_event(); - case FTDF_DATA_FRAME: - FTDF_pib.trafficCounters.rxDataFrmOkCnt++; - break; + ftdf_sn_t SN = REG_GETF(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN); - case FTDF_MAC_COMMAND_FRAME: - FTDF_pib.trafficCounters.rxCmdFrmOkCnt++; - break; - - case FTDF_MULTIPURPOSE_FRAME: - FTDF_pib.trafficCounters.rxMultiPurpFrmOkCnt++; - break; - } - - if (frameType == FTDF_ACKNOWLEDGEMENT_FRAME) - { - volatile uint32_t *txFlagS = FTDF_GET_REG_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_S, FTDF_TX_DATA_BUFFER); - - while (*txFlagS & MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT) - { } - - // It is required to call FTDF_processTxEvent here because an RX ack generates two events - // The RX event is raised first, then after an IFS the TX event is raised. However, - // the FTDF_processNextRequest requires that both events have been handled. - FTDF_processTxEvent(); - - FTDF_SN SN = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_MACSN, FTDF_TX_DATA_BUFFER); - - if (FTDF_reqCurrent && - frameHeader->SN == SN) - { + if (ftdf_req_current && frame_header->sn == SN) { #ifndef FTDF_NO_CSL + if (ftdf_pib.le_enabled == FTDF_TRUE) { + ftdf_time_t timestamp; - if (FTDF_pib.leEnabled == FTDF_TRUE) - { - FTDF_Time timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_RX_TIMESTAMP, - readBuf); - - FTDF_setPeerCslTiming(headerIEList, timestamp); - } + switch (read_buf) { + case 0: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); + break; + case 1: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); + break; + case 2: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); + break; + case 3: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); + break; + case 4: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); + break; + case 5: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); + break; + case 6: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); + break; + case 7: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); + break; + default: + /* Unsupported register index occurred */ + OS_ASSERT(0); + } + ftdf_set_peer_csl_timing(header_ie_list, timestamp); + } #endif /* FTDF_NO_CSL */ #ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled == FTDF_TRUE) { + ftdf_correct_slot_time_from_ack(header_ie_list); - if (FTDF_pib.tschEnabled == FTDF_TRUE) - { - FTDF_correctSlotTimeFromAck(headerIEList); - - FTDF_TschRetry *tschRetry = FTDF_getTschRetry(FTDF_getRequestAddress(FTDF_reqCurrent)); - - tschRetry->nrOfRetries = 0; - FTDF_tschSlotLink->request = NULL; - } + ftdf_tsch_retry_t* tsch_retry = + ftdf_get_tsch_retry(ftdf_get_request_address(ftdf_req_current)); + tsch_retry->nr_of_retries = 0; + ftdf_tsch_slot_link->request = NULL; + } #endif /* FTDF_NO_TSCH */ - switch (FTDF_reqCurrent->msgId) - { - case FTDF_DATA_REQUEST: - { - FTDF_Time timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_TXTIMESTAMP, - FTDF_TX_DATA_BUFFER); - FTDF_NumOfBackoffs numOfBackoffs = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_CSMACANRRETRIES, - FTDF_TX_DATA_BUFFER); + switch (ftdf_req_current->msg_id) { + case FTDF_DATA_REQUEST: + { + ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_0_0_REG, TXTIMESTAMP); + ftdf_num_of_backoffs_t num_of_backoffs = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, CSMACANRRETRIES); - FTDF_sendDataConfirm((FTDF_DataRequest *)FTDF_reqCurrent, - FTDF_SUCCESS, - timestamp, - SN, - numOfBackoffs, - payloadIEList); + ftdf_send_data_confirm((ftdf_data_request_t*)ftdf_req_current, + FTDF_SUCCESS, + timestamp, + SN, + num_of_backoffs, + payload_ie_list); + break; + } + case FTDF_POLL_REQUEST: + { + if (!(frame_header->options & FTDF_OPT_FRAME_PENDING)) { + ftdf_send_poll_confirm((ftdf_poll_request_t*)ftdf_req_current, + FTDF_NO_DATA); + } + break; + } + case FTDF_ASSOCIATE_REQUEST: + { + ftdf_assoc_admin_t* assoc_admin = &ftdf_aa; - break; - } + if ((assoc_admin->fast_a == FTDF_TRUE) || (assoc_admin->data_r == FTDF_FALSE)) { + uint32_t timestamp = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - case FTDF_POLL_REQUEST: - { - if (!(frameHeader->options & FTDF_OPT_FRAME_PENDING)) - { - FTDF_sendPollConfirm((FTDF_PollRequest *)FTDF_reqCurrent, FTDF_NO_DATA); + REG_SETF(FTDF, FTDF_SYMBOLTIME2THR_REG, SYMBOLTIME2THR, + (timestamp + ftdf_pib.response_wait_time * FTDF_BASE_SUPERFRAME_DURATION)); + + } else if (!(frame_header->options & FTDF_OPT_FRAME_PENDING)) { + + ftdf_send_associate_confirm((ftdf_associate_request_t*)ftdf_req_current, + FTDF_NO_DATA, + 0xffff); + } + break; + } + case FTDF_ASSOCIATE_RESPONSE: + { + ftdf_associate_response_t* assoc_resp = + (ftdf_associate_response_t*)ftdf_req_current; + + ftdf_address_t src_addr, dst_addr; + src_addr.ext_address = ftdf_pib.ext_address; + dst_addr.ext_address = assoc_resp->device_address; + + ftdf_send_comm_status_indication(ftdf_req_current, FTDF_SUCCESS, + ftdf_pib.pan_id, + FTDF_EXTENDED_ADDRESS, + src_addr, + FTDF_EXTENDED_ADDRESS, + dst_addr, + assoc_resp->security_level, + assoc_resp->key_id_mode, + assoc_resp->key_source, + assoc_resp->key_index); + break; + } + case FTDF_ORPHAN_RESPONSE: + { + ftdf_orphan_response_t* orphan_resp = + (ftdf_orphan_response_t*)ftdf_req_current; + + ftdf_address_t src_addr, dst_addr; + src_addr.ext_address = ftdf_pib.ext_address; + dst_addr.ext_address = orphan_resp->orphan_address; + + ftdf_send_comm_status_indication(ftdf_req_current, FTDF_SUCCESS, + ftdf_pib.pan_id, + FTDF_EXTENDED_ADDRESS, + src_addr, + FTDF_EXTENDED_ADDRESS, + dst_addr, + orphan_resp->security_level, + orphan_resp->key_id_mode, + orphan_resp->key_source, + orphan_resp->key_index); + break; + } + case FTDF_DISASSOCIATE_REQUEST: + { + ftdf_send_disassociate_confirm((ftdf_disassociate_request_t*)ftdf_req_current, + FTDF_SUCCESS); + break; + } + case FTDF_REMOTE_REQUEST: + { + ftdf_remote_request_t* remote_request = + (ftdf_remote_request_t*)ftdf_req_current; + + if (remote_request->remote_id == + FTDF_REMOTE_PAN_ID_CONFLICT_NOTIFICATION) { + + ftdf_send_sync_loss_indication(FTDF_PAN_ID_CONFLICT, + security_header); + } + + ftdf_req_current = NULL; + break; + } + } + + if (ftdf_req_current->msg_id != FTDF_DATA_REQUEST) { + /* for data request the application owns the memory */ + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + } + + ftdf_process_next_request(); + } else { + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); } + } else if (((frame_header->frame_version == FTDF_FRAME_VERSION_E) || ftdf_pib.tsch_enabled) && + (frame_header->options & FTDF_OPT_ACK_REQUESTED)) { - break; - } - - case FTDF_ASSOCIATE_REQUEST: - { - FTDF_AssocAdmin *assocAdmin = &FTDF_aa; - - if (assocAdmin->fastA == FTDF_TRUE || - assocAdmin->dataR == FTDF_FALSE) - { - uint32_t timestamp = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIME2THR, - (timestamp + FTDF_pib.responseWaitTime * FTDF_BASE_SUPERFRAME_DURATION)); - } - else if (!(frameHeader->options & FTDF_OPT_FRAME_PENDING)) - { - FTDF_sendAssociateConfirm((FTDF_AssociateRequest *)FTDF_reqCurrent, - FTDF_NO_DATA, - 0xffff); - } - - break; - } - - case FTDF_ASSOCIATE_RESPONSE: - { - FTDF_AssociateResponse *assocResp = (FTDF_AssociateResponse *)FTDF_reqCurrent; - - FTDF_Address srcAddr, dstAddr; - srcAddr.extAddress = FTDF_pib.extAddress; - dstAddr.extAddress = assocResp->deviceAddress; - - FTDF_sendCommStatusIndication(FTDF_reqCurrent, FTDF_SUCCESS, - FTDF_pib.PANId, - FTDF_EXTENDED_ADDRESS, - srcAddr, - FTDF_EXTENDED_ADDRESS, - dstAddr, - assocResp->securityLevel, - assocResp->keyIdMode, - assocResp->keySource, - assocResp->keyIndex); - break; - } - - case FTDF_ORPHAN_RESPONSE: - { - FTDF_OrphanResponse *orphanResp = (FTDF_OrphanResponse *)FTDF_reqCurrent; - - FTDF_Address srcAddr, dstAddr; - srcAddr.extAddress = FTDF_pib.extAddress; - dstAddr.extAddress = orphanResp->orphanAddress; - - FTDF_sendCommStatusIndication(FTDF_reqCurrent, FTDF_SUCCESS, - FTDF_pib.PANId, - FTDF_EXTENDED_ADDRESS, - srcAddr, - FTDF_EXTENDED_ADDRESS, - dstAddr, - orphanResp->securityLevel, - orphanResp->keyIdMode, - orphanResp->keySource, - orphanResp->keyIndex); - break; - } - - case FTDF_DISASSOCIATE_REQUEST: - { - FTDF_sendDisassociateConfirm((FTDF_DisassociateRequest *)FTDF_reqCurrent, FTDF_SUCCESS); - break; - } - - case FTDF_REMOTE_REQUEST: - { - FTDF_RemoteRequest *remoteRequest = (FTDF_RemoteRequest *) FTDF_reqCurrent; - - if (remoteRequest->remoteId == FTDF_REMOTE_PAN_ID_CONFLICT_NOTIFICATION) - { - FTDF_sendSyncLossIndication(FTDF_PAN_ID_CONFLICT, securityHeader); - } - - FTDF_reqCurrent = NULL; - - break; - } - } - - if (FTDF_reqCurrent->msgId != FTDF_DATA_REQUEST) - { - // for data request the application owns the memory - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - } - - FTDF_processNextRequest(); - } - else - { - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - } - } - else if ((frameHeader->frameVersion == FTDF_FRAME_VERSION_E || FTDF_pib.tschEnabled) && - (frameHeader->options & FTDF_OPT_ACK_REQUESTED)) - { #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - static FTDF_FrameHeader afh; - FTDF_FrameHeader *ackFrameHeader = &afh; + static ftdf_frame_header_t afh; + ftdf_frame_header_t *ack_frame_header = &afh; - ackFrameHeader->frameType = FTDF_ACKNOWLEDGEMENT_FRAME; - ackFrameHeader->options = - (frameHeader->options & - (FTDF_OPT_SECURITY_ENABLED | FTDF_OPT_SEQ_NR_SUPPRESSED)) | FTDF_OPT_ENHANCED; + ack_frame_header->frame_type = FTDF_ACKNOWLEDGEMENT_FRAME; + ack_frame_header->options = + (frame_header->options & (FTDF_OPT_SECURITY_ENABLED | FTDF_OPT_SEQ_NR_SUPPRESSED)) | + FTDF_OPT_ENHANCED; - if (FTDF_pib.leEnabled == FTDF_TRUE || - FTDF_pib.tschEnabled == FTDF_TRUE || - FTDF_pib.EAckIEList.nrOfIEs != 0) - { - ackFrameHeader->options |= FTDF_OPT_IES_PRESENT; - } + if ((ftdf_pib.le_enabled == FTDF_TRUE) || (ftdf_pib.tsch_enabled == FTDF_TRUE) || + (ftdf_pib.e_ack_ie_list.nr_of_ie != 0)) { - ackFrameHeader->dstAddrMode = FTDF_NO_ADDRESS; - ackFrameHeader->srcAddrMode = FTDF_NO_ADDRESS; - ackFrameHeader->SN = frameHeader->SN; + ack_frame_header->options |= FTDF_OPT_IES_PRESENT; + } - FTDF_Octet *txPtr = (FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO) + - (FTDF_BUFFER_LENGTH * FTDF_TX_ACK_BUFFER); + ack_frame_header->dst_addr_mode = FTDF_NO_ADDRESS; + ack_frame_header->src_addr_mode = FTDF_NO_ADDRESS; + ack_frame_header->sn = frame_header->sn; - // Skip PHY header (= MAC length) - txPtr++; + ftdf_octet_t *tx_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_2_0_REG; - txPtr = FTDF_addFrameHeader(txPtr, - ackFrameHeader, - 0); + /* Skip PHY header (= MAC length) */ + tx_ptr++; - if (frameHeader->options & FTDF_OPT_SECURITY_ENABLED) - { - securityHeader->frameCounter = FTDF_pib.frameCounter; - securityHeader->frameCounterMode = FTDF_pib.frameCounterMode; + tx_ptr = ftdf_add_frame_header(tx_ptr, ack_frame_header, 0); - txPtr = FTDF_addSecurityHeader(txPtr, - securityHeader); - } + if (frame_header->options & FTDF_OPT_SECURITY_ENABLED) { + security_header->frame_counter = ftdf_pib.frame_counter; + security_header->frame_counter_mode = ftdf_pib.frame_counter_mode; + + tx_ptr = ftdf_add_security_header(tx_ptr, security_header); + } #ifndef FTDF_NO_CSL + if (ftdf_pib.le_enabled == FTDF_TRUE) { + static ftdf_octet_t phase_and_period[4]; + static ftdf_ie_descriptor_t cslIE = { 0x1a, 4, { phase_and_period } }; + static ftdf_ie_list_t cslIEList = { 1, &cslIE }; + ftdf_time_t curTime = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - if (FTDF_pib.leEnabled == FTDF_TRUE) - { - static FTDF_Octet phaseAndPeriod[ 4 ]; - static FTDF_IEDescriptor cslIE = { 0x1a, 4, { phaseAndPeriod } }; - static FTDF_IEList cslIEList = { 1, &cslIE }; - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t delta = + curTime - (ftdf_start_csl_sample_time - ftdf_pib.csl_period * 10); - FTDF_Time delta = curTime - - (FTDF_startCslSampleTime - FTDF_pib.CSLPeriod * 10); - - *(FTDF_Period *)(phaseAndPeriod + 0) = (FTDF_Period)(delta / 10); - *(FTDF_Period *)(phaseAndPeriod + 2) = FTDF_pib.CSLPeriod; - - txPtr = FTDF_addIes(txPtr, - &cslIEList, - &FTDF_pib.EAckIEList, - FTDF_FALSE); - } + *(ftdf_period_t*)(phase_and_period + 0) = (ftdf_period_t)(delta / 10); + *(ftdf_period_t*)(phase_and_period + 2) = ftdf_pib.csl_period; + tx_ptr = ftdf_add_ies(tx_ptr, &cslIEList, &ftdf_pib.e_ack_ie_list, FTDF_FALSE); + } #endif /* FTDF_NO_CSL */ #ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled == FTDF_TRUE) { + ftdf_time_t rx_timestamp; - if (FTDF_pib.tschEnabled == FTDF_TRUE) - { - FTDF_Time rxTimestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_RX_TIMESTAMP, readBuf); - - txPtr = FTDF_addCorrTimeIE(txPtr, rxTimestamp); - } + switch (read_buf) { + case 0: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); + break; + case 1: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); + break; + case 2: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); + break; + case 3: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); + break; + case 4: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); + break; + case 5: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); + break; + case 6: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); + break; + case 7: + rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); + break; + default: + /* Unsupported register index occurred */ + OS_ASSERT(0); + } + tx_ptr = ftdf_add_corr_time_ie(tx_ptr, rx_timestamp); + } #endif /* FTDF_NO_TSCH */ - if (!FTDF_pib.leEnabled && !FTDF_pib.tschEnabled) - { - txPtr = FTDF_addIes(txPtr, - NULL, - &FTDF_pib.EAckIEList, - FTDF_FALSE); - } + if (!ftdf_pib.le_enabled && !ftdf_pib.tsch_enabled) { + tx_ptr = ftdf_add_ies(tx_ptr, NULL, &ftdf_pib.e_ack_ie_list, FTDF_FALSE); + } - FTDF_sendAckFrame(frameHeader, - securityHeader, - txPtr); + ftdf_send_ack_frame(frame_header, security_header, tx_ptr); #endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - if (duplicate) - { - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - return; - } - } - - if (frameType == FTDF_DATA_FRAME || frameType == FTDF_MULTIPURPOSE_FRAME) - { - FTDF_DataLength payloadLength = frameLen - - (rxPtr - rxBuffer) + 1 - micLength - FTDF_FCS_LENGTH; - - if (FTDF_reqCurrent && - FTDF_reqCurrent->msgId == FTDF_POLL_REQUEST) - { - FTDF_PollRequest *pollRequest = (FTDF_PollRequest *) FTDF_reqCurrent; - - if (frameHeader->srcAddrMode == pollRequest->coordAddrMode && - frameHeader->srcPANId == pollRequest->coordPANId && - ((frameHeader->srcAddrMode == FTDF_SHORT_ADDRESS && - frameHeader->srcAddr.shortAddress == pollRequest->coordAddr.shortAddress) || - (frameHeader->srcAddrMode == FTDF_EXTENDED_ADDRESS && - frameHeader->srcAddr.extAddress == pollRequest->coordAddr.extAddress))) - { - if (payloadLength == 0) - { - FTDF_sendPollConfirm(pollRequest, FTDF_NO_DATA); + if (duplicate) { + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + return; } - else - { - FTDF_sendPollConfirm(pollRequest, FTDF_SUCCESS); + } + + if ((frame_type == FTDF_DATA_FRAME) || (frame_type == FTDF_MULTIPURPOSE_FRAME)) { + ftdf_data_length_t payload_length = + frameLen - (rx_ptr - rx_buffer) + 1 - mic_length - FTDF_FCS_LENGTH; + + if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_POLL_REQUEST)) { + ftdf_poll_request_t *poll_request = (ftdf_poll_request_t*)ftdf_req_current; + + if ((frame_header->src_addr_mode == poll_request->coord_addr_mode) && + (frame_header->src_pan_id == poll_request->coord_pan_id) && + (((frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) && + (frame_header->src_addr.short_address == poll_request->coord_addr.short_address)) || + ((frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) && + (frame_header->src_addr.ext_address = poll_request->coord_addr.ext_address)))) { + + if (payload_length == 0) { + ftdf_send_poll_confirm(poll_request, FTDF_NO_DATA); + } else { + ftdf_send_poll_confirm(poll_request, FTDF_SUCCESS); + } + } + } else if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_ASSOCIATE_REQUEST) && + (payload_length == 0)) { + + send_confirm(FTDF_NO_DATA, FTDF_ASSOCIATE_REQUEST); } - } - } - else if (FTDF_reqCurrent && - FTDF_reqCurrent->msgId == FTDF_ASSOCIATE_REQUEST && - payloadLength == 0) - { - sendConfirm(FTDF_NO_DATA, FTDF_ASSOCIATE_REQUEST); - } - if (payloadLength != 0) - { - FTDF_LinkQuality mpduLinkQuality = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_QUALITY_INDICATOR, - readBuf); - FTDF_Time timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_RX_TIMESTAMP, - readBuf); + if (payload_length != 0) { + ftdf_link_quality_t mpdu_link_quality; + ftdf_time_t timestamp; - FTDF_sendDataIndication(frameHeader, - securityHeader, - payloadIEList, - payloadLength, - rxPtr, - mpduLinkQuality, - timestamp); - } + switch (read_buf) { + case 0: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); + break; + case 1: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_1_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); + break; + case 2: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_2_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); + break; + case 3: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_3_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); + break; + case 4: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_4_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); + break; + case 5: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_5_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); + break; + case 6: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_6_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); + break; + case 7: + mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_7_REG, QUALITY_INDICATOR); + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); + break; + default: + OS_ASSERT(0); + } + ftdf_send_data_indication(frame_header, + security_header, + payload_ie_list, + payload_length, + rx_ptr, + mpdu_link_quality, + timestamp); + } #ifndef FTDF_NO_CSL - else if (headerIEList->nrOfIEs == 1 && - headerIEList->IEs[ 0 ].ID == 0x1d) - { - FTDF_Period rzTime = *(uint16_t *) headerIEList->IEs[ 0 ].content.raw; + else if ((header_ie_list->nr_of_ie == 1) && (header_ie_list->ie[0].id == 0x1d)) { + ftdf_period_t rz_time = *(uint16_t*)header_ie_list->ie[0].content.raw; - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t cur_time = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - FTDF_rzTime = curTime + (FTDF_Time) rzTime * 10 + 260; // 260 length of max frame in symbols + ftdf_rz_time = cur_time + (ftdf_time_t)rz_time * 10 + 260; /* 260 length of max frame in symbols */ - FTDF_Time CSLPeriod = FTDF_pib.CSLPeriod * 10; - FTDF_Time delta = FTDF_rzTime - FTDF_startCslSampleTime; + ftdf_time_t csl_period = ftdf_pib.csl_period * 10; + ftdf_time_t delta = ftdf_rz_time - ftdf_start_csl_sample_time; - while (delta < 0x80000000) // A delta larger than 0x80000000 is assumed a negative delta - { - FTDF_startCslSampleTime += CSLPeriod; - delta = FTDF_rzTime - FTDF_startCslSampleTime; - } + /* A delta larger than 0x80000000 is assumed a negative delta */ + while (delta < 0x80000000) { + ftdf_start_csl_sample_time += csl_period; + delta = ftdf_rz_time - ftdf_start_csl_sample_time; + } - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME, FTDF_startCslSampleTime); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, + ftdf_start_csl_sample_time); - FTDF_exitCritical(); - - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - } + ftdf_exit_critical(); + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + } #endif /* FTDF_NO_CSL */ - else - { - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); + else { + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + } + } else if (frame_type == FTDF_MAC_COMMAND_FRAME) { + ftdf_process_command_frame(rx_ptr, frame_header, security_header, payload_ie_list); + } else if (frame_type == FTDF_BEACON_FRAME) { + ftdf_octet_t* superframe_spec_ptr = (ftdf_octet_t*)&pan_descriptor.superframe_spec; + superframe_spec_ptr++; + + if (ftdf_is_pan_coordinator) { + if ((frame_header->src_pan_id == ftdf_pib.pan_id) && (*superframe_spec_ptr & 0x40)) { + + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + ftdf_send_sync_loss_indication(FTDF_PAN_ID_CONFLICT, + security_header); + + return; + } + } else if (ftdf_pib.associated_pan_coord) { + if ((frame_header->src_pan_id == ftdf_pib.pan_id) && (*superframe_spec_ptr & 0x40) && + (((frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) && + (frame_header->src_addr.short_address != ftdf_pib.coord_short_address)) || + ((frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) && + (frame_header->src_addr.ext_address != ftdf_pib.coord_ext_address)))) { + + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + ftdf_sendpan_id_conflict_notification(frame_header, security_header); + return; + } + } + + ftdf_data_length_t beacon_payload_length = + frameLen - (rx_ptr - rx_buffer) + 1- mic_length - FTDF_FCS_LENGTH; + + if ((ftdf_pib.auto_request == FTDF_FALSE) || (beacon_payload_length != 0)) { + ftdf_time_t timestamp; + + switch (read_buf) { + case 0: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); + break; + case 1: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); + break; + case 2: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); + break; + case 3: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); + break; + case 4: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); + break; + case 5: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); + break; + case 6: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); + break; + case 7: + timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); + break; + default: + /* Unsupported register index occurred */ + OS_ASSERT(0); + } + + ftdf_beacon_notify_indication_t* beacon_notify_indication = + (ftdf_beacon_notify_indication_t*) FTDF_GET_MSG_BUFFER( + sizeof(ftdf_beacon_notify_indication_t)); + + beacon_notify_indication->msg_id = FTDF_BEACON_NOTIFY_INDICATION; + beacon_notify_indication->bsn = frame_header->sn; + beacon_notify_indication->pan_descriptor = &pan_descriptor; + beacon_notify_indication->pend_addr_spec = pend_addr_spec; + beacon_notify_indication->addr_list = pend_addr_list; + beacon_notify_indication->sdu_length = beacon_payload_length; + beacon_notify_indication->sdu = FTDF_GET_DATA_BUFFER(beacon_payload_length); + beacon_notify_indication->eb_sn = frame_header->sn; + beacon_notify_indication->beacon_type = + frame_header->frame_version == FTDF_FRAME_VERSION_E ? + FTDF_ENHANCED_BEACON : FTDF_NORMAL_BEACON; + beacon_notify_indication->ie_list = payload_ie_list; + beacon_notify_indication->timestamp = timestamp; + + memcpy(beacon_notify_indication->sdu, rx_ptr, beacon_payload_length); + + FTDF_RCV_MSG((ftdf_msg_buffer_t*)beacon_notify_indication); + + } else if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_SCAN_REQUEST)) { + + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + ftdf_add_pan_descriptor(&pan_descriptor); + + } else { + FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); + } } - } - else if (frameType == FTDF_MAC_COMMAND_FRAME) - { - FTDF_processCommandFrame(rxPtr, frameHeader, securityHeader, payloadIEList); - } - else if (frameType == FTDF_BEACON_FRAME) - { - FTDF_Octet *superframeSpecPtr = (FTDF_Octet *)&PANDescriptor.superframeSpec; - superframeSpecPtr++; - - if (FTDF_isPANCoordinator) - { - if (frameHeader->srcPANId == FTDF_pib.PANId && (*superframeSpecPtr & 0x40)) - { - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - FTDF_sendSyncLossIndication(FTDF_PAN_ID_CONFLICT, securityHeader); - return; - } - } - else if (FTDF_pib.associatedPANCoord) - { - if (frameHeader->srcPANId == FTDF_pib.PANId && (*superframeSpecPtr & 0x40) && - ((frameHeader->srcAddrMode == FTDF_SHORT_ADDRESS && - frameHeader->srcAddr.shortAddress != FTDF_pib.coordShortAddress) || - (frameHeader->srcAddrMode == FTDF_EXTENDED_ADDRESS && - frameHeader->srcAddr.extAddress != FTDF_pib.coordExtAddress))) - { - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - FTDF_sendPANIdConflictNotification(frameHeader, securityHeader); - return; - } - } - - FTDF_DataLength beaconPayloadLength = frameLen - (rxPtr - rxBuffer) + 1 - micLength - FTDF_FCS_LENGTH; - - if (FTDF_pib.autoRequest == FTDF_FALSE || - beaconPayloadLength != 0) - { - FTDF_Time timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_RX_TIMESTAMP, - readBuf); - - FTDF_BeaconNotifyIndication *beaconNotifyIndication = - (FTDF_BeaconNotifyIndication *) FTDF_GET_MSG_BUFFER( - sizeof(FTDF_BeaconNotifyIndication)); - - beaconNotifyIndication->msgId = FTDF_BEACON_NOTIFY_INDICATION; - beaconNotifyIndication->BSN = frameHeader->SN; - beaconNotifyIndication->PANDescriptor = &PANDescriptor; - beaconNotifyIndication->pendAddrSpec = pendAddrSpec; - beaconNotifyIndication->addrList = pendAddrList; - beaconNotifyIndication->sduLength = beaconPayloadLength; - beaconNotifyIndication->sdu = FTDF_GET_DATA_BUFFER(beaconPayloadLength); - beaconNotifyIndication->EBSN = frameHeader->SN; - beaconNotifyIndication->beaconType = - frameHeader->frameVersion == FTDF_FRAME_VERSION_E ? FTDF_ENHANCED_BEACON : FTDF_NORMAL_BEACON; - beaconNotifyIndication->IEList = payloadIEList; - beaconNotifyIndication->timestamp = timestamp; - - memcpy(beaconNotifyIndication->sdu, rxPtr, beaconPayloadLength); - - FTDF_RCV_MSG((FTDF_MsgBuffer *) beaconNotifyIndication); - } - else if (FTDF_reqCurrent && - FTDF_reqCurrent->msgId == FTDF_SCAN_REQUEST) - { - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - FTDF_addPANdescriptor(&PANDescriptor); - } - else - { - FTDF_REL_DATA_BUFFER((FTDF_Octet *)payloadIEList); - } - } - #if FTDF_USE_LPDP #if FTDF_FP_BIT_TEST_MODE - - if (FTDF_lpdpIsEnabled() && !FTDF_reqCurrent && frameType == FTDF_DATA_FRAME) - { - FTDF_processTxPending(frameHeader, securityHeader); - } - + if (ftdf_lpdp_is_enabled() && !ftdf_req_current && (frame_type == FTDF_DATA_FRAME)) { + ftdf_process_tx_pending(frame_header, security_header); + } #else /* FTDF_FP_BIT_TEST_MODE */ - - if (!FTDF_reqCurrent && frameType == FTDF_DATA_FRAME) - { - FTDF_processTxPending(frameHeader, securityHeader); - } - + if (!ftdf_req_current && frame_type == FTDF_DATA_FRAME) { + ftdf_process_tx_pending(frame_header, security_header); + } #endif /* FTDF_FP_BIT_TEST_MODE */ #endif /* FTDF_USE_LPDP */ #ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled == FTDF_TRUE) - { - FTDF_scheduleTsch(NULL); - } - + if (ftdf_pib.tsch_enabled == FTDF_TRUE) { + ftdf_schedule_tsch(NULL); + } #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ } - - -void FTDF_processRxEvent(void) +void ftdf_process_rx_event(void) { - volatile uint32_t *rxEvent = (volatile uint32_t *) IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT; - - if (*rxEvent & MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_E) - { + if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RXSOF_E)) { #ifdef SIMULATOR - *rxEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_E; + REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RXSOF_E); #else - *rxEvent = MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_E; + FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RXSOF_E); #endif - } - - if (*rxEvent & MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_E) - { -#ifdef SIMULATOR - *rxEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_E; -#else - *rxEvent = MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_E; -#endif - } - - if (*rxEvent & MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E) - { - // No API defined to report this error to the higher layer, so just clear it. -#ifdef SIMULATOR - *rxEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E; -#else - *rxEvent = MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E; -#endif - } - - if (*rxEvent & MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E) - { - int readBuf = FTDF_GET_FIELD(ON_OFF_REGMAP_RX_READ_BUF_PTR); - int writeBuf = FTDF_GET_FIELD(ON_OFF_REGMAP_RX_WRITE_BUF_PTR); - - while (readBuf != writeBuf) - { - processRxFrame(readBuf % 8); - readBuf = (readBuf + 1) % 16; } - FTDF_SET_FIELD(ON_OFF_REGMAP_RX_READ_BUF_PTR, readBuf); - + if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RXBYTE_E)) { #ifdef SIMULATOR - *rxEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E; + REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RXBYTE_E); #else - *rxEvent = MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E; + FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RXBYTE_E); #endif - } + } - volatile uint32_t *lmacEvent = (volatile uint32_t *) IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT; - - if (*lmacEvent & MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E) - { + if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RX_OVERFLOW_E)) { + // No API defined to report this error to the higher layer, so just clear it. #ifdef SIMULATOR - *lmacEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E; + REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RX_OVERFLOW_E); #else - *lmacEvent = MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E; + FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RX_OVERFLOW_E); +#endif + } + + if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RX_BUF_AVAIL_E)) { + int read_buf = REG_GETF(FTDF, FTDF_RX_CONTROL_0_REG, RX_READ_BUF_PTR); + int write_buf = REG_GETF(FTDF, FTDF_RX_STATUS_REG, RX_WRITE_BUF_PTR); + + while (read_buf != write_buf) { + process_rx_frame(read_buf % 8); + read_buf = (read_buf + 1) % 16; + } + + REG_SETF(FTDF, FTDF_RX_CONTROL_0_REG, RX_READ_BUF_PTR, read_buf); + +#ifdef SIMULATOR + REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RX_BUF_AVAIL_E); +#else + FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RX_BUF_AVAIL_E); +#endif + } + + if (REG_GETF(FTDF, FTDF_LMAC_EVENT_REG, EDSCANREADY_E)) { +#ifdef SIMULATOR + REG_CLR_BIT(FTDF, FTDF_LMAC_EVENT_REG, EDSCANREADY_E); +#else + FTDF->FTDF_LMAC_EVENT_REG = REG_MSK(FTDF, FTDF_LMAC_EVENT_REG, EDSCANREADY_E); #endif #ifndef FTDF_LITE - FTDF_MsgBuffer *request = FTDF_reqCurrent; + ftdf_msg_buffer_t *request = ftdf_req_current; - if (request->msgId == FTDF_SCAN_REQUEST) - { - FTDF_scanReady((FTDF_ScanRequest *) request); + if (request->msg_id == FTDF_SCAN_REQUEST) { + ftdf_scan_ready((ftdf_scan_request_t*)request); + } +#endif /* !FTDF_LITE */ } -#endif /* !FTDF_LITE */ - } - - if (*lmacEvent & MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E) - { + if (REG_GETF(FTDF, FTDF_LMAC_EVENT_REG, RXTIMEREXPIRED_E)) { #ifdef SIMULATOR - *lmacEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E; + REG_CLR_BIT(FTDF, FTDF_LMAC_EVENT_REG, RXTIMEREXPIRED_E); #else - *lmacEvent = MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E; + FTDF->FTDF_LMAC_EVENT_REG = REG_MSK(FTDF, FTDF_LMAC_EVENT_REG, RXTIMEREXPIRED_E); #endif - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.RxExpiredCount++; + if ( ftdf_pib.metrics_enabled ) { + ftdf_pib.performance_metrics.rx_expired_count++; } - #ifndef FTDF_LITE #ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - FTDF_scheduleTsch(NULL); - } - else + if (ftdf_pib.tsch_enabled) { + ftdf_schedule_tsch(NULL); + } else #endif /* FTDF_NO_TSCH */ - if (FTDF_reqCurrent) - { - FTDF_MsgId msgId = FTDF_reqCurrent->msgId; + if (ftdf_req_current) { + ftdf_msg_id_t msg_id = ftdf_req_current->msg_id; - if (msgId == FTDF_POLL_REQUEST) - { - FTDF_sendPollConfirm((FTDF_PollRequest *)FTDF_reqCurrent, FTDF_NO_DATA); + if (msg_id == FTDF_POLL_REQUEST) { + ftdf_send_poll_confirm((ftdf_poll_request_t*)ftdf_req_current, + FTDF_NO_DATA); + } else if (msg_id == FTDF_SCAN_REQUEST) { + ftdf_scan_ready((ftdf_scan_request_t*)ftdf_req_current); + } else if (msg_id == FTDF_ASSOCIATE_REQUEST) { + ftdf_send_associate_confirm((ftdf_associate_request_t*)ftdf_req_current, + FTDF_NO_DATA, + 0xffff); + } } - else if (msgId == FTDF_SCAN_REQUEST) - { - FTDF_scanReady((FTDF_ScanRequest *) FTDF_reqCurrent); - } - else if (msgId == FTDF_ASSOCIATE_REQUEST) - { - FTDF_sendAssociateConfirm((FTDF_AssociateRequest *)FTDF_reqCurrent, - FTDF_NO_DATA, - 0xffff); - } - } - #endif /* !FTDF_LITE */ - } - -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - - if (*lmacEvent & MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E) - { -#ifdef SIMULATOR - *lmacEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E; -#else - *lmacEvent = MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E; -#endif -#if FTDF_USE_SLEEP_DURING_BACKOFF - - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.BOIrqCount++; } - FTDF_sdbFsmBackoffIRQ(); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - } + if (REG_GETF(FTDF, FTDF_LMAC_EVENT_REG, CSMA_CA_BO_THR_E)) { +#ifdef SIMULATOR + REG_CLEAR_BIT(FTDF, FTDF_LMAC_EVENT_REG, CSMA_CA_BO_THR_E); +#else + FTDF->FTDF_LMAC_EVENT_REG = REG_MSK(FTDF, FTDF_LMAC_EVENT_REG, CSMA_CA_BO_THR_E); +#if FTDF_USE_SLEEP_DURING_BACKOFF + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.bo_irq_count++; + } + ftdf_sdb_fsm_backoff_irq(); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + } #endif } -static void sendConfirm(FTDF_Status status, - FTDF_MsgId msgId) +static void send_confirm(ftdf_status_t status, ftdf_msg_id_t msg_id) { - switch (msgId) - { + + switch (msg_id) { #ifndef FTDF_LITE - - case FTDF_DATA_REQUEST: - { - FTDF_DataRequest *dataRequest = (FTDF_DataRequest *) FTDF_reqCurrent; - - FTDF_Time timestamp = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_TXTIMESTAMP, - FTDF_TX_DATA_BUFFER); - FTDF_SN SN = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_MACSN, FTDF_TX_DATA_BUFFER); - FTDF_NumOfBackoffs numOfBackoffs = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_CSMACANRRETRIES, - FTDF_TX_DATA_BUFFER); - - FTDF_sendDataConfirm(dataRequest, status, - timestamp, - SN, - numOfBackoffs, - NULL); - - break; - } - - case FTDF_POLL_REQUEST: - - if (status != FTDF_SUCCESS) + case FTDF_DATA_REQUEST: { - FTDF_sendPollConfirm((FTDF_PollRequest *)FTDF_reqCurrent, status); + ftdf_data_request_t* data_request = (ftdf_data_request_t*)ftdf_req_current; + + ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_0_0_REG, TXTIMESTAMP); + ftdf_sn_t sn = REG_GETF(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN); + ftdf_num_of_backoffs_t num_of_backoffs = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, CSMACANRRETRIES); + + ftdf_send_data_confirm(data_request, status, timestamp, sn, num_of_backoffs, NULL); + + break; } - break; + case FTDF_POLL_REQUEST: + if (status != FTDF_SUCCESS) { + ftdf_send_poll_confirm((ftdf_poll_request_t*)ftdf_req_current, status); + } - case FTDF_ASSOCIATE_REQUEST: + break; + case FTDF_ASSOCIATE_REQUEST: + if (status != FTDF_SUCCESS) { + ftdf_send_associate_confirm((ftdf_associate_request_t*)ftdf_req_current, + status, + 0xffff); + } - if (status != FTDF_SUCCESS) - { - FTDF_sendAssociateConfirm((FTDF_AssociateRequest *)FTDF_reqCurrent, - status, - 0xffff); - } + break; + case FTDF_ASSOCIATE_RESPONSE: + if (status != FTDF_SUCCESS) { + ftdf_associate_response_t *assoc_resp = + (ftdf_associate_response_t*)ftdf_req_current; - break; + ftdf_address_t src_addr, dst_addr; + src_addr.ext_address = ftdf_pib.ext_address; + dst_addr.ext_address = assoc_resp->device_address; - case FTDF_ASSOCIATE_RESPONSE: + ftdf_send_comm_status_indication(ftdf_req_current, status, + ftdf_pib.pan_id, + FTDF_EXTENDED_ADDRESS, + src_addr, + FTDF_EXTENDED_ADDRESS, + dst_addr, + assoc_resp->security_level, + assoc_resp->key_id_mode, + assoc_resp->key_source, + assoc_resp->key_index); + } - if (status != FTDF_SUCCESS) - { - FTDF_AssociateResponse *assocResp = (FTDF_AssociateResponse *)FTDF_reqCurrent; + break; + case FTDF_ORPHAN_RESPONSE: + if (status != FTDF_SUCCESS) { + ftdf_orphan_response_t *orphan_resp = + (ftdf_orphan_response_t*)ftdf_req_current; - FTDF_Address srcAddr, dstAddr; - srcAddr.extAddress = FTDF_pib.extAddress; - dstAddr.extAddress = assocResp->deviceAddress; + ftdf_address_t src_addr, dst_addr; + src_addr.ext_address = ftdf_pib.ext_address; + dst_addr.ext_address = orphan_resp->orphan_address; - FTDF_sendCommStatusIndication(FTDF_reqCurrent, status, - FTDF_pib.PANId, - FTDF_EXTENDED_ADDRESS, - srcAddr, - FTDF_EXTENDED_ADDRESS, - dstAddr, - assocResp->securityLevel, - assocResp->keyIdMode, - assocResp->keySource, - assocResp->keyIndex); - } + ftdf_send_comm_status_indication(ftdf_req_current, status, + ftdf_pib.pan_id, + FTDF_EXTENDED_ADDRESS, + src_addr, + FTDF_EXTENDED_ADDRESS, + dst_addr, + orphan_resp->security_level, + orphan_resp->key_id_mode, + orphan_resp->key_source, + orphan_resp->key_index); + } - break; + break; + case FTDF_DISASSOCIATE_REQUEST: + if (status != FTDF_SUCCESS) { + ftdf_send_disassociate_confirm( + (ftdf_disassociate_request_t*)ftdf_req_current, status); + } - case FTDF_ORPHAN_RESPONSE: + break; + case FTDF_SCAN_REQUEST: + if (status != FTDF_SUCCESS) { + ftdf_send_scan_confirm((ftdf_scan_request_t*)ftdf_req_current, status); + } - if (status != FTDF_SUCCESS) - { - FTDF_OrphanResponse *orphanResp = (FTDF_OrphanResponse *)FTDF_reqCurrent; - - FTDF_Address srcAddr, dstAddr; - srcAddr.extAddress = FTDF_pib.extAddress; - dstAddr.extAddress = orphanResp->orphanAddress; - - FTDF_sendCommStatusIndication(FTDF_reqCurrent, status, - FTDF_pib.PANId, - FTDF_EXTENDED_ADDRESS, - srcAddr, - FTDF_EXTENDED_ADDRESS, - dstAddr, - orphanResp->securityLevel, - orphanResp->keyIdMode, - orphanResp->keySource, - orphanResp->keyIndex); - } - - break; - - case FTDF_DISASSOCIATE_REQUEST: - - if (status != FTDF_SUCCESS) - { - FTDF_sendDisassociateConfirm((FTDF_DisassociateRequest *)FTDF_reqCurrent, status); - } - - break; - - case FTDF_SCAN_REQUEST: - - if (status != FTDF_SUCCESS) - { - FTDF_sendScanConfirm((FTDF_ScanRequest *)FTDF_reqCurrent, status); - } - - break; - - case FTDF_BEACON_REQUEST: - FTDF_sendBeaconConfirm((FTDF_BeaconRequest *)FTDF_reqCurrent, status); - break; - - case FTDF_REMOTE_REQUEST: - FTDF_reqCurrent = NULL; - break; + break; + case FTDF_BEACON_REQUEST: + ftdf_send_beacon_confirm((ftdf_beacon_request_t*)ftdf_req_current, status); + break; + case FTDF_REMOTE_REQUEST: + ftdf_req_current = NULL; + break; #endif /* !FTDF_LITE */ - - case FTDF_TRANSPARENT_REQUEST: - { + case FTDF_TRANSPARENT_REQUEST: + { #ifndef FTDF_PHY_API - FTDF_TransparentRequest *transparentRequest = (FTDF_TransparentRequest *) FTDF_reqCurrent; + ftdf_transparent_request_t *transparent_request = + (ftdf_transparent_request_t*)ftdf_req_current; #endif - FTDF_Bitmap32 transparentStatus = 0; + ftdf_bitmap32_t transparent_status = 0; - switch (status) - { - case FTDF_SUCCESS: - transparentStatus = FTDF_TRANSPARENT_SEND_SUCCESSFUL; - break; - - case FTDF_CHANNEL_ACCESS_FAILURE: - transparentStatus = FTDF_TRANSPARENT_CSMACA_FAILURE; - break; + switch (status) { + case FTDF_SUCCESS: + transparent_status = FTDF_TRANSPARENT_SEND_SUCCESSFUL; + break; + case FTDF_CHANNEL_ACCESS_FAILURE: + transparent_status = FTDF_TRANSPARENT_CSMACA_FAILURE; + break; #if FTDF_TRANSPARENT_WAIT_FOR_ACK - - case FTDF_NO_ACK: - transparentStatus = FTDF_TRANSPARENT_NO_ACK; - break; + case FTDF_NO_ACK: + transparent_status = FTDF_TRANSPARENT_NO_ACK; + break; #endif - } - - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.TXSuccessCount++; - } + } + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.tx_success_count++; + } #ifdef FTDF_PHY_API - FTDF_criticalVar(); - FTDF_enterCritical(); - FTDF_txInProgress = FTDF_FALSE; - FTDF_exitCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); + ftdf_tx_in_progress = FTDF_FALSE; + ftdf_exit_critical(); - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(NULL, transparentStatus); + FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(NULL, transparent_status); #else - FTDF_reqCurrent = NULL; + ftdf_req_current = NULL; - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparentRequest->handle, - transparentStatus); + FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, transparent_status); - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) transparentRequest); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)transparent_request); #ifndef FTDF_LITE - FTDF_processNextRequest(); + ftdf_process_next_request(); #endif /* !FTDF_LITE */ #endif /* FTDF_PHY_API */ - break; - } - } + break; + } + } } -void FTDF_processTxEvent(void) +void ftdf_process_tx_event(void) { - volatile uint32_t *txFlagStatE; - FTDF_Status status = FTDF_SUCCESS; + volatile uint32_t *tx_flag_state; + ftdf_status_t status = FTDF_SUCCESS; -#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI - /* Restore Rx PTI in case the Tx transaction that just ended interrupted an Rx-always-on - * transaction. */ - hw_coex_pti_t tx_pti; - hw_coex_update_ftdf_pti(FTDF_getRxPti(), &tx_pti, true); +#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI + /* Restore Rx PTI in case the Tx transaction that just ended interrupted an Rx-always-on + * transaction. */ + hw_coex_pti_t tx_pti; + hw_coex_update_ftdf_pti(ftdf_get_rx_pti(), &tx_pti, true); #endif - txFlagStatE = FTDF_GET_FIELD_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_CLEAR_E, FTDF_TX_WAKEUP_BUFFER); - - if (*txFlagStatE & MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E) - { + if (REG_GETF(FTDF, FTDF_TX_FLAG_CLEAR_E_1_REG, TX_FLAG_CLEAR_E)) { #ifdef SIMULATOR - *txFlagStatE &= ~MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E; + REG_CLR_BIT(FTDF, FTDF_TX_FLAG_CLEAR_E_1_REG, TX_FLAG_CLEAR_E); #else - *txFlagStatE = MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E; + FTDF->FTDF_TX_FLAG_CLEAR_E_1_REG = REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_E_1_REG, TX_FLAG_CLEAR_E); #endif - volatile uint32_t *txStatus = - FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_RETURN_STATUS_1, FTDF_TX_WAKEUP_BUFFER); + if (REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_1_REG, CSMACAFAIL)) { + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.tx_fail_count++; + } - if (*txStatus & MSK_F_FTDF_RETENTION_RAM_CSMACAFAIL) - { - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.TXFailCount++; - } - - status = FTDF_CHANNEL_ACCESS_FAILURE; + status = FTDF_CHANNEL_ACCESS_FAILURE; + } } - } - txFlagStatE = FTDF_GET_FIELD_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_CLEAR_E, FTDF_TX_DATA_BUFFER); - - if (*txFlagStatE & MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E) - { + if (REG_GETF(FTDF, FTDF_TX_FLAG_CLEAR_E_0_REG, TX_FLAG_CLEAR_E)) { #ifdef SIMULATOR - *txFlagStatE &= ~MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E; + REG_CLR_BIT(FTDF, FTDF_TX_FLAG_CLEAR_E_0_REG, TX_FLAG_CLEAR_E); #else - *txFlagStatE = MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E; + FTDF->FTDF_TX_FLAG_CLEAR_E_0_REG = REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_E_0_REG, TX_FLAG_CLEAR_E); #endif - } - else - { - return; - } + } else { + return; + } #ifndef FTDF_PHY_API - FTDF_txInProgress = FTDF_FALSE; - - if (FTDF_reqCurrent == NULL) - { - return; - } + ftdf_tx_in_progress = FTDF_FALSE; + if (ftdf_req_current == NULL) { + return; + } #else - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); - if (FTDF_txInProgress == FTDF_FALSE) - { - FTDF_exitCritical(); - return; - } + if (ftdf_tx_in_progress == FTDF_FALSE) { + ftdf_exit_critical(); - FTDF_exitCritical(); + return; + } + + ftdf_exit_critical(); #endif #if FTDF_USE_SLEEP_DURING_BACKOFF - FTDF_sdbFsmTxIRQ(); + ftdf_sdb_fsm_tx_irq(); #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - FTDF_Boolean ackTX = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_ACKREQUEST, FTDF_TX_DATA_BUFFER); + ftdf_boolean_t ack_tx = REG_GETF(FTDF, FTDF_TX_META_DATA_0_0_REG, ACKREQUEST); - if (status == FTDF_SUCCESS) - { - volatile uint32_t *txMeta = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_DATA_BUFFER); - FTDF_FrameType frameType = - (*txMeta & MSK_F_FTDF_RETENTION_RAM_FRAMETYPE) >> OFF_F_FTDF_RETENTION_RAM_FRAMETYPE; + if (status == FTDF_SUCCESS) { + ftdf_frame_type_t frame_type = REG_GETF(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAMETYPE); - switch (frameType) - { - case FTDF_BEACON_FRAME: - FTDF_pib.trafficCounters.txBeaconFrmCnt++; - break; - - case FTDF_DATA_FRAME: - FTDF_pib.trafficCounters.txDataFrmCnt++; - break; - - case FTDF_MAC_COMMAND_FRAME: - FTDF_pib.trafficCounters.txCmdFrmCnt++; - break; - - case FTDF_MULTIPURPOSE_FRAME: - FTDF_pib.trafficCounters.txMultiPurpFrmCnt++; - break; - } - - volatile uint32_t *txStatus = - FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_RETURN_STATUS_1, FTDF_TX_DATA_BUFFER); -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - FTDF_TschRetry *tschRetry = NULL; - - if (FTDF_pib.tschEnabled) - { - tschRetry = FTDF_getTschRetry(FTDF_getRequestAddress(FTDF_reqCurrent)); - } - -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - - if (*txStatus & MSK_F_FTDF_RETENTION_RAM_ACKFAIL) - { -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - tschRetry->nrOfRetries++; - FTDF_tschSlotLink->request = NULL; - status = FTDF_scheduleTsch(FTDF_reqCurrent); - - if (status == FTDF_SUCCESS) - { - // If FTDF_reqCurrent is not equal to NULL the retried request will be queued - // rather then send again - FTDF_reqCurrent = NULL; + switch (frame_type) { + case FTDF_BEACON_FRAME: + ftdf_pib.traffic_counters.tx_ceacon_frm_cnt++; + break; + case FTDF_DATA_FRAME: + ftdf_pib.traffic_counters.tx_data_frm_cnt++; + break; + case FTDF_MAC_COMMAND_FRAME: + ftdf_pib.traffic_counters.tx_cmd_frm_cnt++; + break; + case FTDF_MULTIPURPOSE_FRAME: + ftdf_pib.traffic_counters.tx_multi_purp_frm_cnt++; + break; } - } - else + +#ifndef FTDF_LITE +#ifndef FTDF_NO_TSCH + ftdf_tsch_retry_t *tsch_retry = NULL; + + if (ftdf_pib.tsch_enabled) { + tsch_retry = ftdf_get_tsch_retry(ftdf_get_request_address(ftdf_req_current)); + } +#endif /* FTDF_NO_TSCH */ +#endif /* !FTDF_LITE */ + if (REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, ACKFAIL)) { +#ifndef FTDF_LITE +#ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled) { + tsch_retry->nr_of_retries++; + ftdf_tsch_slot_link->request = NULL; + status = ftdf_schedule_tsch(ftdf_req_current); + + if (status == FTDF_SUCCESS) { + /* If ftdf_req_current is not equal to NULL the retried + * request will be queued rather then send again */ + ftdf_req_current = NULL; + } + + } else #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ - if (FTDF_nrOfRetries < FTDF_pib.maxFrameRetries) - { - FTDF_nrOfRetries++; + if (ftdf_nr_of_retries < ftdf_pib.max_frame_retries) { + ftdf_nr_of_retries++; #ifndef FTDF_LITE #ifndef FTDF_NO_CSL + if (ftdf_pib.le_enabled) { + ftdf_set_peer_csl_timing(NULL, 0); - if (FTDF_pib.leEnabled) - { - FTDF_setPeerCslTiming(NULL, 0); + ftdf_critical_var(); + ftdf_enter_critical(); - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_time_t cur_time = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + ftdf_tx_in_progress = FTDF_TRUE; + REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, + cur_time + 5); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACWUPERIOD, + ftdf_pib.csl_max_period); - FTDF_txInProgress = FTDF_TRUE; - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME, curTime + 5); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACWUPERIOD, FTDF_pib.CSLMaxPeriod); + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, + ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER))); - volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); - *txFlagSet |= ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER)); + ftdf_exit_critical(); - FTDF_exitCritical(); - } - else + } else #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ - { -#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI - hw_coex_update_ftdf_pti(tx_pti, NULL, true); + { +#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI + hw_coex_update_ftdf_pti(tx_pti, NULL, true); #endif - volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); - *txFlagSet |= (1 << FTDF_TX_DATA_BUFFER); - } + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_DATA_BUFFER)); + } - return; - } - else - { - if (FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.TXFailCount++; - } + return; - status = FTDF_NO_ACK; - } - } - else if (*txStatus & MSK_F_FTDF_RETENTION_RAM_CSMACAFAIL) - { + } else { + + if (ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.tx_fail_count++; + } + + status = FTDF_NO_ACK; + } + + } else if (REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, CSMACAFAIL)) { #ifndef FTDF_LITE #ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled) { + tsch_retry->nr_of_cca_retries++; - if (FTDF_pib.tschEnabled) - { - tschRetry->nrOfCcaRetries++; + if (tsch_retry->nr_of_cca_retries < ftdf_pib.max_csma_backoffs) { - if (tschRetry->nrOfCcaRetries < FTDF_pib.maxCSMABackoffs) - { - FTDF_tschSlotLink->request = NULL; - status = FTDF_scheduleTsch(FTDF_reqCurrent); + ftdf_tsch_slot_link->request = NULL; + status = ftdf_schedule_tsch(ftdf_req_current); - if (status == FTDF_SUCCESS) - { - // If FTDF_reqCurrent is not equal to NULL the retried request will be queued - // rather then send again - FTDF_reqCurrent = NULL; - } - } - else - { - status = FTDF_CHANNEL_ACCESS_FAILURE; - } - } - else + if (status == FTDF_SUCCESS) { + /* If ftdf_req_current is not equal to NULL the + * retried request will be queued rather then send again */ + ftdf_req_current = NULL; + } + + } else { + status = FTDF_CHANNEL_ACCESS_FAILURE; + } + } else #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ - { - status = FTDF_CHANNEL_ACCESS_FAILURE; - } + { + status = FTDF_CHANNEL_ACCESS_FAILURE; + } - if (FTDF_pib.metricsEnabled && status != FTDF_SUCCESS) - { - FTDF_pib.performanceMetrics.TXFailCount++; - } - } - else - { - if (ackTX == FTDF_FALSE && FTDF_pib.metricsEnabled) - { - FTDF_pib.performanceMetrics.TXSuccessCount++; - } + if (ftdf_pib.metrics_enabled && status != FTDF_SUCCESS) { + ftdf_pib.performance_metrics.tx_fail_count++; + } + + } else { + + if (ack_tx == FTDF_FALSE && ftdf_pib.metrics_enabled) { + ftdf_pib.performance_metrics.tx_success_count++; + } #ifndef FTDF_LITE #ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - tschRetry->nrOfCcaRetries = 0; - } - + if (ftdf_pib.tsch_enabled) { + tsch_retry->nr_of_cca_retries = 0; + } #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ + } } - } #ifndef FTDF_PHY_API - - if ((ackTX == FTDF_FALSE || status != FTDF_SUCCESS) && FTDF_reqCurrent) - { - sendConfirm(status, - FTDF_reqCurrent->msgId); + if (((ack_tx == FTDF_FALSE) || (status != FTDF_SUCCESS)) && ftdf_req_current) { + send_confirm(status, ftdf_req_current->msg_id); #ifndef FTDF_LITE - FTDF_processNextRequest(); + ftdf_process_next_request(); #endif /* !FTDF_LITE */ - } + } #else - - if (FTDF_txInProgress) - { - sendConfirm(status, FTDF_TRANSPARENT_REQUEST); - } - + if (ftdf_tx_in_progress) { + send_confirm(status, FTDF_TRANSPARENT_REQUEST); + } #endif } -void FTDF_processSymbolTimerEvent(void) +void ftdf_process_symbol_timer_event(void) { - volatile uint32_t *symbolTimeThrEvent = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_SYMBOLTIMETHR_E); - #ifdef FTDF_PHY_API - volatile uint32_t *lmacReady4sleepEvent = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_LMACREADY4SLEEP_D); + if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, LMACREADY4SLEEP_D)) { + FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, LMACREADY4SLEEP_D); - if (*lmacReady4sleepEvent & MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D) - { - *lmacReady4sleepEvent = MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D; - - /* If lmac ready 4 sleep, call respective callback, after disabling the interrupt */ - if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 1) - { - volatile uint32_t *lmacCtrlMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_CONTROL_MASK); - *lmacCtrlMask &= ~MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M; - FTDF_LMACREADY4SLEEP_CB(FTDF_TRUE, 0); + /* If lmac ready 4 sleep, call respective callback, after disabling the interrupt */ + if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 1) { + REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_MASK_REG, LMACREADY4SLEEP_M); + FTDF_LMACREADY4SLEEP_CB(FTDF_TRUE, 0); + } } - } - #endif - // sync timestamp event - if (*symbolTimeThrEvent & MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E) - { + /* sync timestamp event */ + if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYNCTIMESTAMP_E)) { #ifdef SIMULATOR - *symbolTimeThrEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E; + REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYNCTIMESTAMP_E); #else - *symbolTimeThrEvent = MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E; + FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYNCTIMESTAMP_E); #endif - FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPENA, 0); + REG_SETF(FTDF, FTDF_TIMER_CONTROL_1_REG, SYNCTIMESTAMPENA, 0); #ifndef FTDF_LITE #ifndef FTDF_NO_CSL - FTDF_oldLeEnabled = FTDF_FALSE; - - if (FTDF_wakeUpEnableLe) - { - FTDF_pib.leEnabled = FTDF_TRUE; - FTDF_setLeEnabled(); - FTDF_wakeUpEnableLe = FTDF_FALSE; - } + ftdf_old_le_enabled = FTDF_FALSE; + if (ftdf_wake_up_enable_le) { + ftdf_pib.le_enabled = FTDF_TRUE; + ftdf_set_le_enabled(); + ftdf_wake_up_enable_le = FTDF_FALSE; + } #endif /* FTDF_NO_CSL */ #ifndef FTDF_NO_TSCH - - if (FTDF_wakeUpEnableTsch) - { - FTDF_setTschEnabled(); - } - + if (ftdf_wake_up_enable_tsch) { + ftdf_set_tsch_enabled(); + } #endif /* FTDF_NO_TSCH */ - FTDF_restoreTxPendingTimer(); + ftdf_restore_tx_pending_timer(); #endif /* !FTDF_LITE */ - FTDF_WAKE_UP_READY(); - } + FTDF_WAKE_UP_READY(); + } - // miscellaneous event - // - Non-TSCH mode: association timer - // - TSCH mode: next active link timer - if (*symbolTimeThrEvent & MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E) - { + /* miscellaneous event + * - Non-TSCH mode: association timer + * - TSCH mode: next active link timer */ + if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIME2THR_E)) { #ifdef SIMULATOR - *symbolTimeThrEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E; + REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIME2THR_E); #else - *symbolTimeThrEvent = MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E; + FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIME2THR_E); #endif #ifndef FTDF_LITE #ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - FTDF_tschProcessRequest(); - } - else + if (ftdf_pib.tsch_enabled) { + ftdf_tsch_process_request(); + } else #endif /* FTDF_NO_TSCH */ - if (FTDF_reqCurrent && - FTDF_reqCurrent->msgId == FTDF_ASSOCIATE_REQUEST) - { - FTDF_AssocAdmin *assocAdmin = &FTDF_aa; + if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_ASSOCIATE_REQUEST)) { + ftdf_assoc_admin_t* assoc_admin = &ftdf_aa; - // macResponseWaitTime expired - assocAdmin->dataR = FTDF_TRUE; - - FTDF_sendAssociateDataRequest(); - } + /* macResponseWaitTime expired */ + assoc_admin->data_r = FTDF_TRUE; + ftdf_send_associate_data_request(); + } #endif /* !FTDF_LITE */ - } + } - // pending queue symbol timer event - if (*symbolTimeThrEvent & MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E) - { + /* pending queue symbol timer event */ + if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIMETHR_E)) { #ifdef SIMULATOR - *symbolTimeThrEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E; + REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIMETHR_E); #else - *symbolTimeThrEvent = MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E; + FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIMETHR_E); #endif #ifndef FTDF_LITE - FTDF_removeTxPendingTimer(NULL); + ftdf_remove_tx_pending_timer(NULL); #endif /* !FTDF_LITE */ - } + } } #ifndef FTDF_LITE -FTDF_Status FTDF_sendFrame(FTDF_ChannelNumber channel, - FTDF_FrameHeader *frameHeader, - FTDF_SecurityHeader *securityHeader, - FTDF_Octet *txPtr, - FTDF_DataLength payloadSize, - FTDF_Octet *payload) +ftdf_status_t ftdf_send_frame(ftdf_channel_number_t channel, + ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header, + ftdf_octet_t *tx_ptr, + ftdf_data_length_t payload_size, + ftdf_octet_t *payload) { - FTDF_Octet *txBufPtr = (FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO); + ftdf_octet_t *tx_buf_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG; - FTDF_DataLength micLength = FTDF_getMicLength(securityHeader->securityLevel); - FTDF_DataLength phyPayloadSize = (txPtr - txBufPtr) - 1 + payloadSize + micLength + FTDF_FCS_LENGTH; + ftdf_data_length_t mic_length = ftdf_get_mic_length(security_header->security_level); + ftdf_data_length_t phy_payload_size = + (tx_ptr - tx_buf_ptr) - 1 + payload_size + mic_length + FTDF_FCS_LENGTH; - if (phyPayloadSize > (FTDF_BUFFER_LENGTH - 1)) - { - return FTDF_FRAME_TOO_LONG; - } - - *txBufPtr = phyPayloadSize; - - FTDF_Octet *privPtr = txPtr; - - int n; - - for (n = 0; n < payloadSize; n++) - { - *txPtr++ = *payload++; - } - - FTDF_Status status = FTDF_secureFrame(txBufPtr, - privPtr, - frameHeader, - securityHeader); - - if (status != FTDF_SUCCESS) - { - return status; - } - - FTDF_Bitmap8 options = frameHeader->options; - - volatile uint32_t *metaData0 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_DATA_BUFFER); - volatile uint32_t *metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_DATA_BUFFER); - - uint16_t phyAttr = (FTDF_pib.CCAMode & 0x3) | 0x08 | ((channel - 11) & 0x0F) << 4 | - (FTDF_pib.TXPower & 0x07) << 12; - - metaData0 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_DATA_BUFFER); - metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_DATA_BUFFER); - - *metaData0 = - ((phyPayloadSize << OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH) & MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH) | - ((phyAttr << OFF_F_FTDF_RETENTION_RAM_PHYATTR) & MSK_F_FTDF_RETENTION_RAM_PHYATTR) | - ((frameHeader->frameType << OFF_F_FTDF_RETENTION_RAM_FRAMETYPE) & MSK_F_FTDF_RETENTION_RAM_FRAMETYPE) | - MSK_F_FTDF_RETENTION_RAM_CSMACA_ENA | - ((options & FTDF_OPT_ACK_REQUESTED) ? MSK_F_FTDF_RETENTION_RAM_ACKREQUEST : 0) | - MSK_F_FTDF_RETENTION_RAM_CRC16_ENA; - - *metaData1 = - ((frameHeader->SN << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); - - uint32_t phyCsmaCaAttr = (FTDF_pib.CCAMode & 0x3) | ((channel - 11) & 0xf) << 4 | - (FTDF_pib.TXPower & 0x07) << 12; - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR, phyCsmaCaAttr); - -#ifndef FTDF_NO_CSL - - if (FTDF_pib.leEnabled == FTDF_TRUE) - { - if (frameHeader->dstAddrMode != FTDF_SHORT_ADDRESS) - { - return FTDF_NO_SHORT_ADDRESS; + if (phy_payload_size > (FTDF_BUFFER_LENGTH - 1)) { + return FTDF_FRAME_TOO_LONG; } - // Clear CSMACA of data frame buffer - *metaData0 &= ~MSK_F_FTDF_RETENTION_RAM_CSMACA_ENA; + *tx_buf_ptr = phy_payload_size; - txPtr = txBufPtr = ((FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO)) + - (FTDF_BUFFER_LENGTH * FTDF_TX_WAKEUP_BUFFER); + ftdf_octet_t* priv_ptr = tx_ptr; - *txPtr++ = 0x0d; - *txPtr++ = 0x2d; - *txPtr++ = 0x81; - *txPtr++ = frameHeader->SN; - *(FTDF_PANId *) txPtr = frameHeader->dstPANId; - txPtr += 2; - *(FTDF_ShortAddress *) txPtr = frameHeader->dstAddr.shortAddress; - txPtr += 2; - *txPtr++ = 0x82; - *txPtr++ = 0x0e; + int n; - metaData0 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_WAKEUP_BUFFER); - metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_WAKEUP_BUFFER); - volatile uint32_t *txPriority = - FTDF_GET_REG_ADDR_INDEXED(ON_OFF_REGMAP_TX_PRIORITY, FTDF_TX_WAKEUP_BUFFER); + for (n = 0; n < payload_size; n++) { + *tx_ptr++ = *payload++; + } - *metaData0 = - ((0x0d << OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH) & MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH) | - ((phyAttr << OFF_F_FTDF_RETENTION_RAM_PHYATTR) & MSK_F_FTDF_RETENTION_RAM_PHYATTR) | - ((FTDF_MULTIPURPOSE_FRAME << OFF_F_FTDF_RETENTION_RAM_FRAMETYPE) & MSK_F_FTDF_RETENTION_RAM_FRAMETYPE) | - MSK_F_FTDF_RETENTION_RAM_CSMACA_ENA | - MSK_F_FTDF_RETENTION_RAM_CRC16_ENA; + ftdf_status_t status = ftdf_secure_frame(tx_buf_ptr, priv_ptr, frame_header, security_header); - *metaData1 = - ((frameHeader->SN << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); -#if FTDF_USE_PTI && FTDF_USE_AUTO_PTI - *txPriority |= MSK_F_FTDF_ON_OFF_REGMAP_ISWAKEUP; + if (status != FTDF_SUCCESS) { + return status; + } + + ftdf_bitmap8_t options = frame_header->options; + + uint32_t meta_data_0 = 0; + + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAME_LENGTH, meta_data_0, phy_payload_size); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_DEM_PTI, meta_data_0, ((ftdf_pib.cca_mode & 0x3) | 0x08)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_CN, meta_data_0, (channel - 11)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAMETYPE, meta_data_0, frame_header->frame_type); + + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CSMACA_ENA, meta_data_0, 1); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, ACKREQUEST, meta_data_0, + ((options & FTDF_OPT_ACK_REQUESTED) ? 1 : 0)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CRC16_ENA, meta_data_0, 1); + + FTDF->FTDF_TX_META_DATA_0_0_REG = meta_data_0; + + uint32_t meta_data_1 = 0; + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, frame_header->sn); + FTDF->FTDF_TX_META_DATA_1_0_REG = meta_data_1; + + uint32_t tmp = FTDF->FTDF_LMAC_CONTROL_5_REG; + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_DEM_PTI, tmp, (ftdf_pib.cca_mode & 0x3)); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CN, tmp, (channel - 11)); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CALCAP, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_RF_GPIO_PINS, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_HSI, tmp, 0); + FTDF->FTDF_LMAC_CONTROL_5_REG = tmp; + +#ifndef FTDF_NO_CSL + if (ftdf_pib.le_enabled == FTDF_TRUE) { + if (frame_header->dst_addr_mode != FTDF_SHORT_ADDRESS) { + return FTDF_NO_SHORT_ADDRESS; + } + + /* Clear CSMACA of data frame buffer */ + REG_SETF(FTDF, FTDF_TX_META_DATA_0_0_REG, CSMACA_ENA, 0); + + tx_ptr = tx_buf_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_1_0_REG; + + *tx_ptr++ = 0x0d; + *tx_ptr++ = 0x2d; + *tx_ptr++ = 0x81; + *tx_ptr++ = frame_header->sn; + *(ftdf_pan_id_t*)tx_ptr = frame_header->dst_pan_id; + tx_ptr += 2; + *(ftdf_short_address_t*)tx_ptr = frame_header->dst_addr.short_address; + tx_ptr += 2; + *tx_ptr++ = 0x82; + *tx_ptr++ = 0x0e; + + meta_data_0 = 0; + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, FRAME_LENGTH, meta_data_0, 0x0d); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, PHYATTR_DEM_PTI, meta_data_0, ((ftdf_pib.cca_mode & 0x3) | 0x08)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, PHYATTR_CN, meta_data_0, (channel - 11)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, FRAMETYPE, meta_data_0, FTDF_MULTIPURPOSE_FRAME); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, CSMACA_ENA, meta_data_0, 1); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, CRC16_ENA, meta_data_0, 1); + FTDF->FTDF_TX_META_DATA_0_1_REG = meta_data_0; + + uint32_t meta_data_1 = 0; + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_1_REG, MACSN, meta_data_1, frame_header->sn); + FTDF->FTDF_TX_META_DATA_1_1_REG = meta_data_1; + +#if FTDF_USE_AUTO_PTI + FTDF->FTDF_TX_PRIORITY_1_REG |= REG_MSK(FTDF, FTDF_TX_PRIORITY_1_REG, ISWAKEUP); #else - *txPriority = MSK_F_FTDF_ON_OFF_REGMAP_ISWAKEUP; + FTDF->FTDF_TX_PRIORITY_1_REG = REG_MSK(FTDF, FTDF_TX_PRIORITY_1_REG, ISWAKEUP); #endif - } - + } #endif /* FTDF_NO_CSL */ - volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); - #ifndef FTDF_NO_CSL + if (ftdf_pib.le_enabled == FTDF_TRUE) { + ftdf_time_t cur_time = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t delta = cur_time - ftdf_rz_time; - if (FTDF_pib.leEnabled == FTDF_TRUE) - { - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_Time delta = curTime - FTDF_rzTime; + if (delta > 0x80000000) { - if (delta > 0x80000000) - { - // Receiving an wakeup frame sequence, delay sending until RZ has passed. - FTDF_sendFramePending = frameHeader->dstAddr.shortAddress; - } - else - { - FTDF_Time wakeupStartTime; - FTDF_Period wakeupPeriod; + /* Receiving an wakeup frame sequence, delay sending until RZ has passed. */ + ftdf_send_frame_pending = frame_header->dst_addr.short_address; - FTDF_criticalVar(); - FTDF_enterCritical(); + } else { - FTDF_getWakeupParams(frameHeader->dstAddr.shortAddress, &wakeupStartTime, &wakeupPeriod); + ftdf_time_t wakeup_start_time; + ftdf_period_t wakeup_period; - FTDF_txInProgress = FTDF_TRUE; - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME, wakeupStartTime); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACWUPERIOD, wakeupPeriod); + ftdf_critical_var(); + ftdf_enter_critical(); - *txFlagSet |= ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER)); + ftdf_get_wakeup_params(frame_header->dst_addr.short_address, + &wakeup_start_time, &wakeup_period); - FTDF_exitCritical(); - } - } - else + ftdf_tx_in_progress = FTDF_TRUE; + REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, + wakeup_start_time); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACWUPERIOD, wakeup_period); + + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, + ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER))); + + ftdf_exit_critical(); + } + + } else #endif /* FTDF_NO_CSL */ - if (!FTDF_pib.tschEnabled) - { - *txFlagSet |= (1 << FTDF_TX_DATA_BUFFER); -// SetWord16(P2_SET_DATA_REG, (1 << 3)); -// SetWord16(P23_MODE_REG, 0x300); // SW trigger - output -// for (volatile int k = 0; k < 100; k++) { -// } -// SetWord16(P23_MODE_REG, 0x000);// SW trigger - high Z - - + if (!ftdf_pib.tsch_enabled) { + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_DATA_BUFFER)); } - return FTDF_SUCCESS; + return FTDF_SUCCESS; } #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -FTDF_Status FTDF_sendAckFrame(FTDF_FrameHeader *frameHeader, - FTDF_SecurityHeader *securityHeader, - FTDF_Octet *txPtr) +ftdf_status_t ftdf_send_ack_frame(ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header, + ftdf_octet_t *tx_ptr) { - FTDF_Octet *txBufPtr = ((FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO)) + - 2 * FTDF_BUFFER_LENGTH; - FTDF_DataLength micLength = FTDF_getMicLength(securityHeader->securityLevel); - FTDF_DataLength phyPayloadSize = (txPtr - txBufPtr) - 1 + micLength + FTDF_FCS_LENGTH; + ftdf_octet_t *tx_buf_ptr = ((ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_2_0_REG); + ftdf_data_length_t mic_length = ftdf_get_mic_length(security_header->security_level); + ftdf_data_length_t phy_payload_size = + (tx_ptr - tx_buf_ptr) - 1 + mic_length + FTDF_FCS_LENGTH; - *txBufPtr = phyPayloadSize; + *tx_buf_ptr = phy_payload_size; - FTDF_Status status = FTDF_secureFrame(txBufPtr, - txPtr, - frameHeader, - securityHeader); + ftdf_status_t status = ftdf_secure_frame(tx_buf_ptr, + tx_ptr, + frame_header, + security_header); - if (status != FTDF_SUCCESS) - { - return status; - } - - volatile uint32_t *metaData0 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_ACK_BUFFER); - volatile uint32_t *metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_ACK_BUFFER); - volatile uint32_t *txPriority = FTDF_GET_REG_ADDR_INDEXED(ON_OFF_REGMAP_TX_PRIORITY, FTDF_TX_ACK_BUFFER); - - uint16_t phyAttr = - (FTDF_pib.CCAMode & 0x3) | 0x08 | (FTDF_GET_FIELD(ON_OFF_REGMAP_PHYRXATTR) & 0x00f0) | - (FTDF_pib.TXPower & 0x07) << 12; - - *metaData0 = - ((phyPayloadSize << OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH) & MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH) | - ((phyAttr << OFF_F_FTDF_RETENTION_RAM_PHYATTR) & MSK_F_FTDF_RETENTION_RAM_PHYATTR) | - ((FTDF_ACKNOWLEDGEMENT_FRAME << OFF_F_FTDF_RETENTION_RAM_FRAMETYPE) & MSK_F_FTDF_RETENTION_RAM_FRAMETYPE) | - MSK_F_FTDF_RETENTION_RAM_CRC16_ENA; - - *metaData1 = - ((frameHeader->SN << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); - -#if FTDF_USE_PTI && FTDF_USE_AUTO_PTI - *txPriority |= 1; -#else - *txPriority = 1; -#endif - - volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); - -#ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - FTDF_criticalVar(); - FTDF_enterCritical(); - - FTDF_Period txAckDelayVal = FTDF_GET_FIELD(ON_OFF_REGMAP_MACTSTXACKDELAYVAL); - - if (txAckDelayVal > 20) - { - *txFlagSet |= 1 << FTDF_TX_ACK_BUFFER; + if (status != FTDF_SUCCESS) { + return status; } - FTDF_exitCritical(); - } - else -#endif /* FTDF_NO_TSCH */ - { - *txFlagSet |= 1 << FTDF_TX_ACK_BUFFER; - } + uint32_t meta_data_0 = 0; - FTDF_pib.trafficCounters.txEnhAckFrmCnt++; + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, FRAME_LENGTH, meta_data_0, phy_payload_size); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, PHYATTR_DEM_PTI, meta_data_0, ((ftdf_pib.cca_mode & 0x3) | 0x08)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, PHYATTR_CN, meta_data_0, REG_GETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, FRAMETYPE, meta_data_0, FTDF_ACKNOWLEDGEMENT_FRAME); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, CRC16_ENA, meta_data_0, 1); - return FTDF_SUCCESS; + FTDF->FTDF_TX_META_DATA_0_2_REG = meta_data_0; + + uint32_t meta_data_1 = 0; + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_2_REG, MACSN, meta_data_1, frame_header->sn); + FTDF->FTDF_TX_META_DATA_1_2_REG = meta_data_1; + +#if FTDF_USE_AUTO_PTI + REG_SETF(FTDF, FTDF_TX_PRIORITY_2_REG, TX_PRIORITY, 1); +#else + FTDF->FTDF_TX_PRIORITY_2_REG = 1; +#endif + +#ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled) { + + ftdf_critical_var(); + ftdf_enter_critical(); + + ftdf_period_t tx_ack_delay_val = + REG_GETF(FTDF, FTDF_MACTSTXACKDELAYVAL_REG, MACTSTXACKDELAYVAL); + + if (tx_ack_delay_val > 20) { + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_ACK_BUFFER)); + } + + ftdf_exit_critical(); + + } else + #endif /* FTDF_NO_TSCH */ + { + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_ACK_BUFFER)); + } + + ftdf_pib.traffic_counters.tx_enh_ack_frm_cnt++; + + return FTDF_SUCCESS; } #endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ -void FTDF_sendTransparentFrame(FTDF_DataLength frameLength, - FTDF_Octet *frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean cmsaSuppress) +void ftdf_send_transparent_frame(ftdf_data_length_t frame_length, + ftdf_octet_t *frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t cmsa_suppress) { - volatile uint32_t *metaData0 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_DATA_BUFFER); - volatile uint32_t *metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_DATA_BUFFER); - volatile uint32_t *txPriority = FTDF_GET_REG_ADDR_INDEXED(ON_OFF_REGMAP_TX_PRIORITY, FTDF_TX_DATA_BUFFER); + uint32_t meta_data_0 = 0; + uint32_t tmp; #if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - FTDF_Boolean useAck = FTDF_FALSE; - //FTDF_FrameHeader* frameHeader = &FTDF_fh; - FTDF_FrameHeader frameHeader; - FTDF_SN SN; + ftdf_boolean_t use_ack = FTDF_FALSE; + //ftdf_frame_header_t *frame_header = &ftdf_fh; + ftdf_frame_header_t frame_header; + ftdf_sn_t sn; #endif - uint16_t phyAttr = (FTDF_pib.CCAMode & 0x3) | 0x08 | ((channel - 11) & 0x0F) << 4 | - (FTDF_pib.TXPower & 0x07) << 12; + #if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - - if (FTDF_transparentModeOptions & FTDF_TRANSPARENT_WAIT_FOR_ACK) - { - FTDF_getFrameHeader(frame, &frameHeader); - - if (frameHeader.options & FTDF_OPT_ACK_REQUESTED) - { - useAck = FTDF_TRUE; + if (ftdf_transparent_mode_options & FTDF_TRANSPARENT_WAIT_FOR_ACK) { + ftdf_get_frame_header(frame, &frame_header); + if (frame_header.options & FTDF_OPT_ACK_REQUESTED) { + use_ack = FTDF_TRUE; + } + sn = frame_header.sn; } - - SN = frameHeader.SN; - } - #endif -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - *txPriority = ((pti << OFF_F_FTDF_ON_OFF_REGMAP_PTI_TX) & - MSK_F_FTDF_ON_OFF_REGMAP_PTI_TX) | 1; -#endif - *metaData0 = - ((frameLength << OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH) & MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH) | - ((phyAttr << OFF_F_FTDF_RETENTION_RAM_PHYATTR) & MSK_F_FTDF_RETENTION_RAM_PHYATTR) | - (((*frame & 0x7) << OFF_F_FTDF_RETENTION_RAM_FRAMETYPE) & MSK_F_FTDF_RETENTION_RAM_FRAMETYPE) | - ((cmsaSuppress) ? 0 : MSK_F_FTDF_RETENTION_RAM_CSMACA_ENA) | -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - ((useAck) ? MSK_F_FTDF_RETENTION_RAM_ACKREQUEST : 0) | -#endif - ((FTDF_transparentModeOptions & - FTDF_TRANSPARENT_ENABLE_FCS_GENERATION) ? MSK_F_FTDF_RETENTION_RAM_CRC16_ENA : 0); + tmp = 0; + REG_SET_FIELD(FTDF, FTDF_TX_PRIORITY_0_REG, PTI_TX, tmp, pti); + REG_SET_FIELD(FTDF, FTDF_TX_PRIORITY_0_REG, TX_PRIORITY, tmp, 1); + FTDF->FTDF_TX_PRIORITY_0_REG = tmp; + + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAME_LENGTH, meta_data_0, frame_length); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_DEM_PTI, meta_data_0, (ftdf_pib.cca_mode & 0x3) | 0x08); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_CN, meta_data_0, (channel - 11)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAMETYPE, meta_data_0, (*frame & 0x7)); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CSMACA_ENA, meta_data_0, ((cmsa_suppress) ? 0 : 1)); #if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - - if (useAck) - { - *metaData1 = ((SN << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); - } - else - { - *metaData1 = ((0 << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); - } - -#else - *metaData1 = - ((0 << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, ACKREQUEST, meta_data_0, (use_ack ? 1 : 0)); #endif + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CRC16_ENA, meta_data_0, + ((ftdf_transparent_mode_options & FTDF_TRANSPARENT_ENABLE_FCS_GENERATION) ? 1 : 0)); - uint32_t phyCsmaCaAttr = (FTDF_pib.CCAMode & 0x3) | ((channel - 11) & 0xf) << 4 | - (FTDF_pib.TXPower & 0x07) << 12; - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR, phyCsmaCaAttr); -#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI - hw_coex_update_ftdf_pti((hw_coex_pti_t) pti, NULL, true); + FTDF->FTDF_TX_META_DATA_0_0_REG = meta_data_0; + + uint32_t meta_data_1 = 0; +#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK + if (use_ack) { + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, sn); + } else { + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, 0); + } #else - // FTDF_SET_FIELD(ON_OFF_REGMAP_PTI_TX, pti); + REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, 0); #endif - volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); - *txFlagSet |= (1 << FTDF_TX_DATA_BUFFER); + FTDF->FTDF_TX_META_DATA_1_0_REG = meta_data_1; + + tmp = FTDF->FTDF_LMAC_CONTROL_5_REG; + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_DEM_PTI, tmp, (ftdf_pib.cca_mode & 0x3)); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CN, tmp, (channel - 11)); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CALCAP, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_RF_GPIO_PINS, tmp, (ftdf_pib.tx_power & 0x07)); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_HSI, tmp, 0); + FTDF->FTDF_LMAC_CONTROL_5_REG = tmp; + +#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI + hw_coex_update_ftdf_pti((hw_coex_pti_t)pti, NULL, true); +#else + // REG_SETF(FTDF, FTDF_TX_PRIORITY_0_REG, PTI_TX, pti); +#endif + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_DATA_BUFFER)); } -void FTDF_initQueues(void) +void ftdf_init_queues(void) { #ifndef FTDF_LITE - FTDF_initQueue(&FTDF_freeQueue); - FTDF_initQueue(&FTDF_reqQueue); + ftdf_init_queue(&ftdf_free_queue); + ftdf_init_queue(&ftdf_req_queue); - int n; + int n; - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) - { - FTDF_queueBufferHead(&FTDF_reqBuffers[ n ], &FTDF_freeQueue); + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { + ftdf_queue_buffer_head(&ftdf_req_buffers[n], &ftdf_free_queue); - FTDF_txPendingList[ n ].addr.extAddress = 0xFFFFFFFFFFFFFFFFLL; - FTDF_txPendingList[ n ].addrMode = FTDF_NO_ADDRESS; - FTDF_txPendingList[ n ].PANId = 0xFFFF; - FTDF_initQueue(&FTDF_txPendingList[ n ].queue); + ftdf_tx_pending_list[n].addr.ext_address = 0xFFFFFFFFFFFFFFFFLL; + ftdf_tx_pending_list[n].addr_mode = FTDF_NO_ADDRESS; + ftdf_tx_pending_list[n].pan_id = 0xFFFF; + ftdf_init_queue(&ftdf_tx_pending_list[n].queue); - FTDF_txPendingTimerList[ n ].free = FTDF_TRUE; - FTDF_txPendingTimerList[ n ].next = NULL; - } + ftdf_tx_pending_timer_list[n].free = FTDF_TRUE; + ftdf_tx_pending_timer_list[n].next = NULL; + } - FTDF_txPendingTimerHead = FTDF_txPendingTimerList; - FTDF_txPendingTimerTime = 0; + ftdf_tx_pending_timer_head = ftdf_tx_pending_timer_list; + ftdf_tx_pending_timer_time = 0; #endif /* !FTDF_LITE */ #ifndef FTDF_PHY_API - FTDF_reqCurrent = NULL; + ftdf_req_current = NULL; #endif } #ifndef FTDF_LITE -void FTDF_initQueue(FTDF_Queue *queue) +void ftdf_init_queue(ftdf_queue_t *queue) { - queue->head.next = (FTDF_Buffer *) &queue->tail; - queue->head.prev = NULL; - queue->tail.next = NULL; - queue->tail.prev = (FTDF_Buffer *) &queue->head; + queue->head.next = (ftdf_buffer_t*)&queue->tail; + queue->head.prev = NULL; + queue->tail.next = NULL; + queue->tail.prev = (ftdf_buffer_t*)&queue->head; } -void FTDF_queueBufferHead(FTDF_Buffer *buffer, FTDF_Queue *queue) +void ftdf_queue_buffer_head(ftdf_buffer_t *buffer, ftdf_queue_t *queue) { - FTDF_Buffer *next = queue->head.next; + ftdf_buffer_t *next = queue->head.next; - queue->head.next = buffer; - next->header.prev = buffer; - buffer->header.next = next; - buffer->header.prev = (FTDF_Buffer *) &queue->head; + queue->head.next = buffer; + next->header.prev = buffer; + buffer->header.next = next; + buffer->header.prev = (ftdf_buffer_t*)&queue->head; } -FTDF_Buffer *FTDF_dequeueBufferTail(FTDF_Queue *queue) +ftdf_buffer_t *ftdf_dequeue_buffer_tail(ftdf_queue_t *queue) { - FTDF_Buffer *buffer = queue->tail.prev; + ftdf_buffer_t *buffer = queue->tail.prev; - if (buffer->header.prev == NULL) - { - return NULL; - } - - queue->tail.prev = buffer->header.prev; - buffer->header.prev->header.next = (FTDF_Buffer *) &queue->tail; - - return buffer; -} - -FTDF_Status FTDF_queueReqHead(FTDF_MsgBuffer *request, FTDF_Queue *queue) -{ - FTDF_Buffer *buffer = FTDF_dequeueBufferTail(&FTDF_freeQueue); - - if (buffer == NULL) - { - return FTDF_TRANSACTION_OVERFLOW; - } - - FTDF_Buffer *next = queue->head.next; - - queue->head.next = buffer; - next->header.prev = buffer; - buffer->header.next = next; - buffer->header.prev = (FTDF_Buffer *) &queue->head; - buffer->request = request; - - return FTDF_SUCCESS; -} - -FTDF_MsgBuffer *FTDF_dequeueReqTail(FTDF_Queue *queue) -{ - FTDF_Buffer *buffer = queue->tail.prev; - - if (buffer->header.prev == NULL) - { - return NULL; - } - - queue->tail.prev = buffer->header.prev; - buffer->header.prev->header.next = (FTDF_Buffer *) &queue->tail; - - FTDF_MsgBuffer *request = buffer->request; - - FTDF_queueBufferHead(buffer, &FTDF_freeQueue); - - return request; -} - -FTDF_MsgBuffer *FTDF_dequeueByHandle(FTDF_Handle handle, FTDF_Queue *queue) -{ - FTDF_Buffer *buffer = queue->head.next; - - while (buffer->header.next != NULL) - { - if (buffer->request && - buffer->request->msgId == FTDF_DATA_REQUEST && - ((FTDF_DataRequest *) buffer->request)->msduHandle == handle) - { - buffer->header.prev->header.next = buffer->header.next; - buffer->header.next->header.prev = buffer->header.prev; - - FTDF_MsgBuffer *request = buffer->request; - - FTDF_queueBufferHead(buffer, &FTDF_freeQueue); - - return request; + if (buffer->header.prev == NULL) { + return NULL; } - buffer = buffer->header.next; - } + queue->tail.prev = buffer->header.prev; + buffer->header.prev->header.next = (ftdf_buffer_t*)&queue->tail; - return NULL; + return buffer; } -FTDF_MsgBuffer *FTDF_dequeueByRequest(FTDF_MsgBuffer *request, FTDF_Queue *queue) +ftdf_status_t ftdf_queue_req_head(ftdf_msg_buffer_t *request, ftdf_queue_t *queue) { - FTDF_Buffer *buffer = queue->head.next; + ftdf_buffer_t *buffer = ftdf_dequeue_buffer_tail(&ftdf_free_queue); - while (buffer->header.next != NULL) - { - if (buffer->request == request) - { - buffer->header.prev->header.next = buffer->header.next; - buffer->header.next->header.prev = buffer->header.prev; - - FTDF_MsgBuffer *req = buffer->request; - - FTDF_queueBufferHead(buffer, &FTDF_freeQueue); - - return req; + if (buffer == NULL) { + return FTDF_TRANSACTION_OVERFLOW; } - buffer = buffer->header.next; - } + ftdf_buffer_t *next = queue->head.next; - return NULL; + queue->head.next = buffer; + next->header.prev = buffer; + buffer->header.next = next; + buffer->header.prev = (ftdf_buffer_t*)&queue->head; + buffer->request = request; + + return FTDF_SUCCESS; } -FTDF_Boolean FTDF_isQueueEmpty(FTDF_Queue *queue) +ftdf_msg_buffer_t *ftdf_dequeue_req_tail(ftdf_queue_t *queue) { - if (queue->head.next->header.next == NULL) - { - return FTDF_TRUE; - } - else - { - return FTDF_FALSE; - } + ftdf_buffer_t *buffer = queue->tail.prev; + + if (buffer->header.prev == NULL) { + return NULL; + } + + queue->tail.prev = buffer->header.prev; + buffer->header.prev->header.next = (ftdf_buffer_t*)&queue->tail; + + ftdf_msg_buffer_t *request = buffer->request; + + ftdf_queue_buffer_head(buffer, &ftdf_free_queue); + + return request; } -static FTDF_PendingTL *FTDF_findFreePendingTimer(void) +ftdf_msg_buffer_t *ftdf_dequeue_by_handle(ftdf_handle_t handle, ftdf_queue_t *queue) { - uint8_t i; + ftdf_buffer_t *buffer = queue->head.next; - for (i = 0; i < FTDF_NR_OF_REQ_BUFFERS; i++) - { - if (FTDF_txPendingTimerList[ i ].free == FTDF_TRUE) - { - break; - } - } + while (buffer->header.next != NULL) { + if (buffer->request && buffer->request->msg_id == FTDF_DATA_REQUEST && + ((ftdf_data_request_t*)buffer->request)->msdu_handle == handle) { + buffer->header.prev->header.next = buffer->header.next; + buffer->header.next->header.prev = buffer->header.prev; - return &FTDF_txPendingTimerList[ i ]; -} + ftdf_msg_buffer_t *request = buffer->request; -void FTDF_addTxPendingTimer(FTDF_MsgBuffer *request, uint8_t pendListNr, FTDF_Time delta, void (* func)( - FTDF_PendingTL *)) -{ - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_queue_buffer_head(buffer, &ftdf_free_queue); - FTDF_PendingTL *ptr = FTDF_txPendingTimerHead; - FTDF_Time timestamp = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - - if (ptr->free == FTDF_FALSE) - { - while (ptr) - { - ptr->delta -= timestamp - FTDF_txPendingTimerLT; - ptr = ptr->next; - } - } - - FTDF_txPendingTimerLT = timestamp; - ptr = FTDF_txPendingTimerHead; - - if (ptr->free == FTDF_TRUE) - { - ptr->free = FTDF_FALSE; - ptr->next = NULL; - ptr->request = request; - ptr->delta = delta; - ptr->pendListNr = pendListNr; - ptr->func = func; - - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIMETHR, delta + timestamp); - FTDF_txPendingTimerTime = delta + timestamp; - FTDF_exitCritical(); - return; - } - - if (ptr->delta > delta) - { - FTDF_txPendingTimerHead = FTDF_findFreePendingTimer(); - FTDF_txPendingTimerHead->free = FTDF_FALSE; - FTDF_txPendingTimerHead->next = ptr; - FTDF_txPendingTimerHead->request = request; - FTDF_txPendingTimerHead->delta = delta; - FTDF_txPendingTimerHead->pendListNr = pendListNr; - FTDF_txPendingTimerHead->func = func; - - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIMETHR, delta + timestamp); - FTDF_txPendingTimerTime = delta + timestamp; - FTDF_exitCritical(); - return; - } - else if (ptr->delta == delta) - { - delta++; - } - - FTDF_PendingTL *prev; - - while (ptr->next) - { - prev = ptr; - ptr = ptr->next; - - if (ptr->delta == delta) - { - delta++; - } - - if (prev->delta < delta && ptr->delta > delta) - { - prev->next = FTDF_findFreePendingTimer(); - prev->next->next = ptr; - ptr = prev->next; - ptr->free = FTDF_FALSE; - ptr->request = request; - ptr->delta = delta; - ptr->pendListNr = pendListNr; - ptr->func = func; - - FTDF_exitCritical(); - return; - } - } - - ptr->next = FTDF_findFreePendingTimer(); - ptr = ptr->next; - ptr->free = FTDF_FALSE; - ptr->next = NULL; - ptr->request = request; - ptr->delta = delta; - ptr->pendListNr = pendListNr; - ptr->func = func; - - FTDF_exitCritical(); -} - -void FTDF_removeTxPendingTimer(FTDF_MsgBuffer *request) -{ - FTDF_criticalVar(); - FTDF_enterCritical(); - - FTDF_PendingTL *ptr = FTDF_txPendingTimerHead; - FTDF_Time timestamp = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - - if (ptr->free == FTDF_TRUE) - { - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIMETHR, timestamp - 1); - FTDF_txPendingTimerTime = timestamp - 1; - FTDF_exitCritical(); - return; - } - - while (ptr) - { - ptr->delta -= timestamp - FTDF_txPendingTimerLT; - ptr = ptr->next; - } - - FTDF_txPendingTimerLT = timestamp; - ptr = FTDF_txPendingTimerHead; - - if (!request || ptr->request == request) - { - if (ptr->next) - { - FTDF_PendingTL *temp = ptr; - - if (ptr->next->delta < 75) - { - while (temp) - { - temp->delta += 75; - temp = temp->next; + return request; } - } - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIMETHR, timestamp + ptr->next->delta); - FTDF_txPendingTimerTime = timestamp + ptr->next->delta; - FTDF_txPendingTimerHead = ptr->next; - - ptr->free = FTDF_TRUE; - ptr->next = NULL; - } - else - { - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIMETHR, timestamp - 1); - FTDF_txPendingTimerTime = timestamp - 1; - - ptr->free = FTDF_TRUE; - ptr->next = NULL; + buffer = buffer->header.next; } - FTDF_exitCritical(); - - if (!request) - { - if (ptr->func) - { - ptr->func(ptr); - } - } - - return; - } - - FTDF_PendingTL *prev = ptr; - - while (ptr->next) - { - prev = ptr; - ptr = ptr->next; - - if (ptr->request == request) - { - prev->next = ptr->next; - ptr->free = FTDF_TRUE; - ptr->next = NULL; - - FTDF_exitCritical(); - return; - } - } - - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIMETHR, timestamp - 1); - FTDF_txPendingTimerTime = timestamp - 1; - FTDF_exitCritical(); + return NULL; } -void FTDF_restoreTxPendingTimer(void) +ftdf_msg_buffer_t *ftdf_dequeue_by_request(ftdf_msg_buffer_t *request, ftdf_queue_t *queue) { - FTDF_SET_FIELD(ON_OFF_REGMAP_SYMBOLTIMETHR, FTDF_txPendingTimerTime); + ftdf_buffer_t *buffer = queue->head.next; + + while (buffer->header.next != NULL) { + if (buffer->request == request) { + buffer->header.prev->header.next = buffer->header.next; + buffer->header.next->header.prev = buffer->header.prev; + + ftdf_msg_buffer_t *req = buffer->request; + + ftdf_queue_buffer_head(buffer, &ftdf_free_queue); + + return req; + } + + buffer = buffer->header.next; + } + + return NULL; } -FTDF_Boolean FTDF_getTxPendingTimerHead(FTDF_Time *time) +ftdf_boolean_t ftdf_is_queue_empty(ftdf_queue_t *queue) { - FTDF_PendingTL *ptr = FTDF_txPendingTimerHead; + if (queue->head.next->header.next == NULL) { + return FTDF_TRUE; + } else { + return FTDF_FALSE; + } +} - if (ptr->free == FTDF_TRUE) - { - return FTDF_FALSE; - } +static ftdf_pending_tl_t *ftdf_find_free_pending_timer(void) +{ + uint8_t i; - *time = FTDF_txPendingTimerTime; - return FTDF_TRUE; + for (i = 0; i < FTDF_NR_OF_REQ_BUFFERS; i++) { + if (ftdf_tx_pending_timer_list[i].free == FTDF_TRUE) { + break; + } + } + + return &ftdf_tx_pending_timer_list[i]; +} + +void ftdf_add_tx_pending_timer(ftdf_msg_buffer_t *request, uint8_t pendListNr, ftdf_time_t delta, + void (*func)(ftdf_pending_tl_t*)) +{ + ftdf_critical_var(); + ftdf_enter_critical(); + + ftdf_pending_tl_t *ptr = ftdf_tx_pending_timer_head; + ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, + SYMBOLTIMESNAPSHOTVAL); + + if (ptr->free == FTDF_FALSE) { + while (ptr) { + ptr->delta -= timestamp - ftdf_tx_pending_timer_lt; + ptr = ptr->next; + } + } + + ftdf_tx_pending_timer_lt = timestamp; + ptr = ftdf_tx_pending_timer_head; + + if (ptr->free == FTDF_TRUE) { + ptr->free = FTDF_FALSE; + ptr->next = NULL; + ptr->request = request; + ptr->delta = delta; + ptr->pend_list_nr = pendListNr; + ptr->func = func; + + REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, delta + timestamp); + ftdf_tx_pending_timer_time = delta + timestamp; + ftdf_exit_critical(); + return; + } + + if (ptr->delta > delta) { + ftdf_tx_pending_timer_head = ftdf_find_free_pending_timer(); + ftdf_tx_pending_timer_head->free = FTDF_FALSE; + ftdf_tx_pending_timer_head->next = ptr; + ftdf_tx_pending_timer_head->request = request; + ftdf_tx_pending_timer_head->delta = delta; + ftdf_tx_pending_timer_head->pend_list_nr = pendListNr; + ftdf_tx_pending_timer_head->func = func; + + REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, delta + timestamp); + ftdf_tx_pending_timer_time = delta + timestamp; + ftdf_exit_critical(); + + return; + } else if (ptr->delta == delta) { + delta++; + } + + ftdf_pending_tl_t *prev; + + while (ptr->next) { + prev = ptr; + ptr = ptr->next; + + if (ptr->delta == delta) { + delta++; + } + + if (prev->delta < delta && ptr->delta > delta) { + prev->next = ftdf_find_free_pending_timer(); + prev->next->next = ptr; + ptr = prev->next; + ptr->free = FTDF_FALSE; + ptr->request = request; + ptr->delta = delta; + ptr->pend_list_nr = pendListNr; + ptr->func = func; + + ftdf_exit_critical(); + + return; + } + } + + ptr->next = ftdf_find_free_pending_timer(); + ptr = ptr->next; + ptr->free = FTDF_FALSE; + ptr->next = NULL; + ptr->request = request; + ptr->delta = delta; + ptr->pend_list_nr = pendListNr; + ptr->func = func; + + ftdf_exit_critical(); +} + +void ftdf_remove_tx_pending_timer(ftdf_msg_buffer_t *request) +{ + ftdf_critical_var(); + ftdf_enter_critical(); + + ftdf_pending_tl_t *ptr = ftdf_tx_pending_timer_head; + ftdf_time_t timestamp = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + + if (ptr->free == FTDF_TRUE) { + REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, timestamp - 1); + ftdf_tx_pending_timer_time = timestamp - 1; + ftdf_exit_critical(); + + return; + } + + while (ptr) { + ptr->delta -= timestamp - ftdf_tx_pending_timer_lt; + ptr = ptr->next; + } + + ftdf_tx_pending_timer_lt = timestamp; + ptr = ftdf_tx_pending_timer_head; + + if (!request || ptr->request == request) { + if (ptr->next) { + ftdf_pending_tl_t *temp = ptr; + + if (ptr->next->delta < 75) { + while (temp) { + temp->delta += 75; + temp = temp->next; + } + } + + REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, + timestamp + ptr->next->delta); + ftdf_tx_pending_timer_time = timestamp + ptr->next->delta; + ftdf_tx_pending_timer_head = ptr->next; + + ptr->free = FTDF_TRUE; + ptr->next = NULL; + } else { + REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, timestamp - 1); + ftdf_tx_pending_timer_time = timestamp - 1; + + ptr->free = FTDF_TRUE; + ptr->next = NULL; + } + + ftdf_exit_critical(); + + if (!request) { + if (ptr->func) { + ptr->func(ptr); + } + } + + return; + } + + ftdf_pending_tl_t *prev = ptr; + + while (ptr->next) { + prev = ptr; + ptr = ptr->next; + + if (ptr->request == request) { + prev->next = ptr->next; + ptr->free = FTDF_TRUE; + ptr->next = NULL; + + ftdf_exit_critical(); + + return; + } + } + + REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, timestamp - 1); + ftdf_tx_pending_timer_time = timestamp - 1; + ftdf_exit_critical(); +} + +void ftdf_restore_tx_pending_timer(void) +{ + REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, ftdf_tx_pending_timer_time); +} + +ftdf_boolean_t ftdf_get_tx_pending_timer_head(ftdf_time_t *time) +{ + ftdf_pending_tl_t *ptr = ftdf_tx_pending_timer_head; + + if (ptr->free == FTDF_TRUE) { + return FTDF_FALSE; + } + + *time = ftdf_tx_pending_timer_time; + + return FTDF_TRUE; } #ifndef FTDF_NO_TSCH -void FTDF_processKeepAliveTimerExp(FTDF_PendingTL *ptr) -{ - FTDF_RemoteRequest *remoteRequest = (FTDF_RemoteRequest *)ptr->request; +void ftdf_process_keep_alive_timer_exp(ftdf_pending_tl_t *ptr) { + ftdf_remote_request_t *remote_request = (ftdf_remote_request_t*)ptr->request; - remoteRequest->msgId = FTDF_REMOTE_REQUEST; - remoteRequest->remoteId = FTDF_REMOTE_KEEP_ALIVE; - remoteRequest->dstAddr = FTDF_neighborTable[ ptr->pendListNr ].dstAddr; + remote_request->msg_id = FTDF_REMOTE_REQUEST; + remote_request->remote_id = FTDF_REMOTE_KEEP_ALIVE; + remote_request->dst_addr = ftdf_neighbor_table[ptr->pend_list_nr].dst_addr; - FTDF_processRemoteRequest(remoteRequest); + ftdf_process_remote_request(remote_request); } #endif /* FTDF_NO_TSCH */ -void FTDF_sendTransactionExpired(FTDF_PendingTL *ptr) +void ftdf_send_transaction_expired(ftdf_pending_tl_t *ptr) { - FTDF_MsgBuffer *req = - FTDF_dequeueByRequest(ptr->request, &FTDF_txPendingList[ ptr->pendListNr ].queue); + ftdf_msg_buffer_t *req = + ftdf_dequeue_by_request(ptr->request, + &ftdf_tx_pending_list[ptr->pend_list_nr].queue); - if (!req) - { - return; - } - - if (FTDF_isQueueEmpty(&FTDF_txPendingList[ ptr->pendListNr ].queue)) - { -#ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - FTDF_txPendingList[ ptr->pendListNr ].addr.shortAddress = 0xfffe; + if (!req) { + return; } - else + + if (ftdf_is_queue_empty(&ftdf_tx_pending_list[ptr->pend_list_nr].queue)) { +#ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled) { + ftdf_tx_pending_list[ptr->pend_list_nr].addr.short_address = 0xfffe; + } else #endif /* FTDF_NO_TSCH */ - { + { #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - - if (FTDF_txPendingList[ ptr->pendListNr ].addrMode == FTDF_SHORT_ADDRESS) - { - uint8_t entry, shortAddrIdx; - FTDF_Boolean found = FTDF_fpprLookupShortAddress( - FTDF_txPendingList[ ptr->pendListNr ].addr.shortAddress, &entry, - &shortAddrIdx); - ASSERT_WARNING(found); - FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); + if (ftdf_tx_pending_list[ptr->pend_list_nr].addr_mode == FTDF_SHORT_ADDRESS) { + uint8_t entry, short_addr_idx; + ftdf_boolean_t found = ftdf_fppr_lookup_short_address( + ftdf_tx_pending_list[ptr->pend_list_nr].addr.short_address, &entry, + &short_addr_idx); + ASSERT_WARNING(found); + ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_FALSE); + } else if (ftdf_tx_pending_list[ptr->pend_list_nr].addr_mode == FTDF_EXTENDED_ADDRESS) { + uint8_t entry; + ftdf_boolean_t found = ftdf_fppr_lookup_ext_address( + ftdf_tx_pending_list[ptr->pend_list_nr].addr.ext_address, &entry); + ASSERT_WARNING(found); + ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); + } else { + ASSERT_WARNING(0); } - else if (FTDF_txPendingList[ ptr->pendListNr ].addrMode == FTDF_EXTENDED_ADDRESS) - { - uint8_t entry; - FTDF_Boolean found = FTDF_fpprLookupExtAddress( - FTDF_txPendingList[ ptr->pendListNr ].addr.extAddress, &entry); - ASSERT_WARNING(found); - FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); - } - else - { - ASSERT_WARNING(0); - } - #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - FTDF_txPendingList[ ptr->pendListNr ].addrMode = FTDF_NO_ADDRESS; + ftdf_tx_pending_list[ptr->pend_list_nr].addr_mode = FTDF_NO_ADDRESS; + } } - } - switch (req->msgId) - { - case FTDF_DATA_REQUEST: - { - FTDF_DataRequest *dataRequest = (FTDF_DataRequest *)req; + switch (req->msg_id) { + case FTDF_DATA_REQUEST: + { + ftdf_data_request_t *data_request = (ftdf_data_request_t*)req; - FTDF_sendDataConfirm(dataRequest, FTDF_TRANSACTION_EXPIRED, 0, 0, 0, NULL); + ftdf_send_data_confirm(data_request, FTDF_TRANSACTION_EXPIRED, 0, 0, 0, NULL); - break; - } + break; + } + case FTDF_ASSOCIATE_REQUEST: + { + ftdf_associate_request_t* associate_request = (ftdf_associate_request_t*)req; - case FTDF_ASSOCIATE_REQUEST: - { - FTDF_AssociateRequest *associateRequest = (FTDF_AssociateRequest *)req; + ftdf_send_associate_confirm(associate_request, FTDF_TRANSACTION_EXPIRED, 0xffff); - FTDF_sendAssociateConfirm(associateRequest, FTDF_TRANSACTION_EXPIRED, 0xffff); + break; + } + case FTDF_ASSOCIATE_RESPONSE: + { + ftdf_associate_response_t *assoc_resp = (ftdf_associate_response_t*)req; - break; - } + ftdf_address_t src_addr, dst_addr; + src_addr.ext_address = ftdf_pib.ext_address; + dst_addr.ext_address = assoc_resp->device_address; - case FTDF_ASSOCIATE_RESPONSE: - { - FTDF_AssociateResponse *assocResp = (FTDF_AssociateResponse *)req; + ftdf_send_comm_status_indication(req, FTDF_TRANSACTION_EXPIRED, + ftdf_pib.pan_id, + FTDF_EXTENDED_ADDRESS, + src_addr, + FTDF_EXTENDED_ADDRESS, + dst_addr, + assoc_resp->security_level, + assoc_resp->key_id_mode, + assoc_resp->key_source, + assoc_resp->key_index); - FTDF_Address srcAddr, dstAddr; - srcAddr.extAddress = FTDF_pib.extAddress; - dstAddr.extAddress = assocResp->deviceAddress; + break; + } + case FTDF_DISASSOCIATE_REQUEST: + { + ftdf_disassociate_request_t* dis_req = (ftdf_disassociate_request_t*)req; - FTDF_sendCommStatusIndication(req, FTDF_TRANSACTION_EXPIRED, - FTDF_pib.PANId, - FTDF_EXTENDED_ADDRESS, - srcAddr, - FTDF_EXTENDED_ADDRESS, - dstAddr, - assocResp->securityLevel, - assocResp->keyIdMode, - assocResp->keySource, - assocResp->keyIndex); + ftdf_send_disassociate_confirm(dis_req, FTDF_TRANSACTION_EXPIRED); - break; - } + break; + } + case FTDF_BEACON_REQUEST: + { + ftdf_beacon_request_t* beacon_request = (ftdf_beacon_request_t*)req; - case FTDF_DISASSOCIATE_REQUEST: - { - FTDF_DisassociateRequest *disReq = (FTDF_DisassociateRequest *)req; + ftdf_send_beacon_confirm(beacon_request, FTDF_TRANSACTION_EXPIRED); - FTDF_sendDisassociateConfirm(disReq, FTDF_TRANSACTION_EXPIRED); - - break; - } - - case FTDF_BEACON_REQUEST: - { - FTDF_BeaconRequest *beaconRequest = (FTDF_BeaconRequest *)req; - - FTDF_sendBeaconConfirm(beaconRequest, FTDF_TRANSACTION_EXPIRED); - - break; - } - } + break; + } + } } #ifndef FTDF_NO_TSCH -void FTDF_resetKeepAliveTimer(FTDF_ShortAddress dstAddr) +void ftdf_reset_keep_alive_timer(ftdf_short_address_t dst_addr) { - uint8_t n; + uint8_t n; - for (n = 0; n < FTDF_NR_OF_NEIGHBORS; n++) - { - if (FTDF_neighborTable[ n ].dstAddr == dstAddr) - { - break; + for (n = 0; n < FTDF_NR_OF_NEIGHBORS; n++) { + if (ftdf_neighbor_table[n].dst_addr == dst_addr) { + break; + } } - } - if (n == FTDF_NR_OF_NEIGHBORS) - { - return; - } + if (n == FTDF_NR_OF_NEIGHBORS) { + return; + } - FTDF_removeTxPendingTimer((FTDF_MsgBuffer *)&FTDF_neighborTable[ n ].msg); + ftdf_remove_tx_pending_timer((ftdf_msg_buffer_t*)&ftdf_neighbor_table[n].msg); - FTDF_Time tsTimeslotLength = (FTDF_Time) FTDF_pib.timeslotTemplate.tsTimeslotLength / 16; - FTDF_Time delta = tsTimeslotLength * FTDF_neighborTable[ n ].period; + ftdf_time_t ts_timeslot_length = (ftdf_time_t)ftdf_pib.timeslot_template.ts_timeslot_length + / 16; + ftdf_time_t delta = ts_timeslot_length * ftdf_neighbor_table[n].period; - FTDF_addTxPendingTimer((FTDF_MsgBuffer *)&FTDF_neighborTable[ n ].msg, n, delta, FTDF_processKeepAliveTimerExp); + ftdf_add_tx_pending_timer((ftdf_msg_buffer_t*)&ftdf_neighbor_table[n].msg, n, delta, + ftdf_process_keep_alive_timer_exp); } #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ -void FTDF_enableTransparentMode(FTDF_Boolean enable, - FTDF_Bitmap32 options) +void ftdf_enable_transparent_mode(ftdf_boolean_t enable, + ftdf_bitmap32_t options) { #ifndef FTDF_LITE - - if (FTDF_pib.leEnabled == FTDF_TRUE || - FTDF_pib.tschEnabled == FTDF_TRUE) - { - return; - } - + if ((ftdf_pib.le_enabled == FTDF_TRUE) || (ftdf_pib.tsch_enabled == FTDF_TRUE)) { + return; + } #endif /* !FTDF_LITE */ - FTDF_transparentMode = enable; - FTDF_transparentModeOptions = options; - if (enable) - { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE, - (options & FTDF_TRANSPARENT_PASS_ALL_FRAME_TYPES)); - FTDF_SET_FIELD(ON_OFF_REGMAP_DISRXACKREQUESTCA, (options & FTDF_TRANSPARENT_AUTO_ACK ? 0 : 1)); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSCRCERROR, (options & FTDF_TRANSPARENT_PASS_CRC_ERROR ? 1 : 0)); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION, - (options & FTDF_TRANSPARENT_PASS_ALL_FRAME_VERSION ? 1 : 0)); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID, - (options & FTDF_TRANSPARENT_PASS_ALL_PAN_ID ? 1 : 0)); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR, (options & FTDF_TRANSPARENT_PASS_ALL_ADDR ? 1 : 0)); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID, - (options & FTDF_TRANSPARENT_PASS_ALL_BEACON ? 1 : 0)); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR, - (options & FTDF_TRANSPARENT_PASS_ALL_NO_DEST_ADDR ? 1 : 0)); - } - else - { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_DISRXACKREQUESTCA, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSCRCERROR, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR, 0); - } + ftdf_transparent_mode = enable; + ftdf_transparent_mode_options = options; + + uint32_t tmp = FTDF->FTDF_RX_CONTROL_0_REG; + + if (enable) { + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSFRMTYPE, tmp, + (options & FTDF_TRANSPARENT_PASS_ALL_FRAME_TYPES)); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, DISRXACKREQUESTCA, tmp, + (options & FTDF_TRANSPARENT_AUTO_ACK ? 0 : 1)); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSCRCERROR, tmp, + (options & FTDF_TRANSPARENT_PASS_CRC_ERROR ? 1 : 0)); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSRESFRAMEVERSION, tmp, + (options & FTDF_TRANSPARENT_PASS_ALL_FRAME_VERSION ? 1 : 0)); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDPANID, tmp, + (options & FTDF_TRANSPARENT_PASS_ALL_PAN_ID ? 1 : 0)); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDADDR, tmp, + (options & FTDF_TRANSPARENT_PASS_ALL_ADDR ? 1 : 0)); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSBEACONWRONGPANID, tmp, + (options & FTDF_TRANSPARENT_PASS_ALL_BEACON ? 1 : 0)); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSTOPANCOORDINATOR, tmp, + (options & FTDF_TRANSPARENT_PASS_ALL_NO_DEST_ADDR ? 1 : 0)); + } else { + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSFRMTYPE, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, DISRXACKREQUESTCA, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSCRCERROR, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSRESFRAMEVERSION, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDPANID, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDADDR, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSBEACONWRONGPANID, tmp, 0); + REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSTOPANCOORDINATOR, tmp, 0); + } + + FTDF->FTDF_RX_CONTROL_0_REG = tmp; } #if FTDF_DBG_BUS_ENABLE -void FTDF_checkDbgMode(void) +void ftdf_check_dbg_mode(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_DBG_CONTROL, FTDF_dbgMode); - - if (FTDF_dbgMode) - { - FTDF_DBG_BUS_GPIO_CONFIG(); - } + REG_SET_MASKED(FTDF, FTDF_DEBUGCONTROL_REG, 0xFF, ftdf_dbg_mode); + if (ftdf_dbg_mode) { + FTDF_DBG_BUS_GPIO_CONFIG(); + } } -void FTDF_setDbgMode(FTDF_DbgMode dbgMode) +void ftdf_set_dbg_mode(ftdf_dbg_mode_t dbg_mode) { - FTDF_dbgMode = dbgMode; - FTDF_checkDbgMode(); + ftdf_dbg_mode = dbg_mode; + ftdf_check_dbg_mode(); } #endif /* FTDF_DBG_BUS_ENABLE */ #ifndef FTDF_LITE #ifndef FTDF_NO_CSL -void FTDF_setPeerCslTiming(FTDF_IEList *headerIEList, FTDF_Time timeStamp) +void ftdf_set_peer_csl_timing(ftdf_ie_list_t *header_ie_list, ftdf_time_t time_stamp) { - if (FTDF_reqCurrent->msgId != FTDF_DATA_REQUEST) - { - // Only use the CSL timing of data frame acks - return; - } - - FTDF_DataRequest *dataRequest = (FTDF_DataRequest *) FTDF_reqCurrent; - FTDF_ShortAddress dstAddr = dataRequest->dstAddr.shortAddress; - - if (dataRequest->dstAddrMode != FTDF_SHORT_ADDRESS || - dstAddr == 0xffff) - { - return; - } - - int n; - - // Search for an existing entry - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) - { - if (FTDF_peerCslTiming[ n ].addr == dstAddr) - { - break; - } - } - - if (headerIEList == NULL) - { - if (n < FTDF_NR_OF_CSL_PEERS) - { - // Delete entry - FTDF_peerCslTiming[ n ].addr = 0xffff; + if (ftdf_req_current->msg_id != FTDF_DATA_REQUEST) { + /* Only use the CSL timing of data frame acks */ + return; } - return; - } + ftdf_data_request_t* data_request = (ftdf_data_request_t*)ftdf_req_current; + ftdf_short_address_t dst_addr = data_request->dst_addr.short_address; - int ieNr = 0; - - while (ieNr < headerIEList->nrOfIEs && - headerIEList->IEs[ ieNr ].ID != 0x1a) - { - ieNr++; - } - - if (ieNr == headerIEList->nrOfIEs) - { - return; - } - - if (n == FTDF_NR_OF_CSL_PEERS) - { - // Search for an empty entry - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) - { - if (FTDF_peerCslTiming[ n ].addr == 0xffff) - { - break; - } - } - } - - if (n == FTDF_NR_OF_CSL_PEERS) - { - // No free entry, search for the least recently used entry - FTDF_Time maxDelta = 0; - int lru = 0; - - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) - { - FTDF_Time delta = timeStamp - FTDF_peerCslTiming[ n ].time; - - if (delta > maxDelta) - { - maxDelta = delta; - lru = n; - } + if ((data_request->dst_addr_mode != FTDF_SHORT_ADDRESS) || (dst_addr == 0xffff)) { + return; } - n = lru; - } + int n; - FTDF_Period phase = (*(FTDF_Period *)(headerIEList->IEs[ 0 ].content.raw + 0)); - FTDF_Period period = (*(FTDF_Period *)(headerIEList->IEs[ 0 ].content.raw + 2)); + /* Search for an existing entry */ + for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { + if (ftdf_peer_csl_timing[n].addr == dst_addr) { + break; + } + } - FTDF_peerCslTiming[ n ].addr = dstAddr; - FTDF_peerCslTiming[ n ].time = timeStamp - (phase * 10); - FTDF_peerCslTiming[ n ].period = period; + if (header_ie_list == NULL) { + if (n < FTDF_NR_OF_CSL_PEERS) { + /* Delete entry */ + ftdf_peer_csl_timing[n].addr = 0xffff; + } + + return; + } + + int ie_nr = 0; + + while (ie_nr < header_ie_list->nr_of_ie && header_ie_list->ie[ie_nr].id != 0x1a) { + ie_nr++; + } + + if (ie_nr == header_ie_list->nr_of_ie) { + return; + } + + if (n == FTDF_NR_OF_CSL_PEERS) { + /* Search for an empty entry */ + for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { + if (ftdf_peer_csl_timing[n].addr == 0xffff) { + break; + } + } + } + + if (n == FTDF_NR_OF_CSL_PEERS) { + /* No free entry, search for the least recently used entry */ + ftdf_time_t max_delta = 0; + int lru = 0; + + for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { + ftdf_time_t delta = time_stamp - ftdf_peer_csl_timing[n].time; + + if (delta > max_delta) { + max_delta = delta; + lru = n; + } + } + + n = lru; + } + + ftdf_period_t phase = (*(ftdf_period_t*)(header_ie_list->ie[0].content.raw + 0)); + ftdf_period_t period = (*(ftdf_period_t*)(header_ie_list->ie[0].content.raw + 2)); + + ftdf_peer_csl_timing[n].addr = dst_addr; + ftdf_peer_csl_timing[n].time = time_stamp - (phase * 10); + ftdf_peer_csl_timing[n].period = period; } -void FTDF_getWakeupParams(FTDF_ShortAddress dstAddr, - FTDF_Time *wakeupStartTime, - FTDF_Period *wakeupPeriod) +void ftdf_get_wakeup_params(ftdf_short_address_t dst_addr, ftdf_time_t *wakeup_start_time, + ftdf_period_t *wakeup_period) { - int n; + int n; - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) - { - if (FTDF_peerCslTiming[ n ].addr == dstAddr) - { - break; + for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { + if (ftdf_peer_csl_timing[n].addr == dst_addr) { + break; + } } - } - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, + SYMBOLTIMESNAPSHOTVAL); - if (dstAddr == 0xffff || - n == FTDF_NR_OF_CSL_PEERS) - { - *wakeupStartTime = curTime + 5; - *wakeupPeriod = FTDF_pib.CSLMaxPeriod; + if (dst_addr == 0xffff || + n == FTDF_NR_OF_CSL_PEERS) { + *wakeup_start_time = cur_time + 5; + *wakeup_period = ftdf_pib.csl_max_period; - return; - } + return; + } - FTDF_Time peerTime = FTDF_peerCslTiming[ n ].time; - FTDF_Time peerPeriod = FTDF_peerCslTiming[ n ].period * 10; - FTDF_Time delta = curTime - peerTime; + ftdf_time_t peer_time = ftdf_peer_csl_timing[n].time; + ftdf_time_t peer_period = ftdf_peer_csl_timing[n].period * 10; + ftdf_time_t delta = cur_time - peer_time; - if (delta > (uint32_t)(FTDF_pib.CSLMaxAgeRemoteInfo * 10)) - { - *wakeupStartTime = curTime + 5; - *wakeupPeriod = FTDF_pib.CSLMaxPeriod; + if (delta > (uint32_t)(ftdf_pib.csl_max_age_remote_info * 10)) { + *wakeup_start_time = cur_time + 5; + *wakeup_period = ftdf_pib.csl_max_period; - return; - } + return; + } - FTDF_Time wStart = peerTime + (((delta / peerPeriod) + 1) * peerPeriod) - FTDF_pib.CSLSyncTxMargin; - delta = wStart - curTime; + ftdf_time_t w_start = peer_time + (((delta / peer_period) + 1) * peer_period) + - ftdf_pib.csl_sync_tx_margin; + delta = w_start - cur_time; - if (delta < 3 || delta > 0x80000000) // A delta larger than 0x80000000 is assumed a negative delta - { - wStart += peerPeriod; - } + /* A delta larger than 0x80000000 is assumed a negative delta */ + if ((delta < 3) || (delta > 0x80000000)) { + w_start += peer_period; + } - *wakeupPeriod = (FTDF_pib.CSLSyncTxMargin / 10) * 2; - *wakeupStartTime = wStart; + *wakeup_period = (ftdf_pib.csl_sync_tx_margin / 10) * 2; + *wakeup_start_time = w_start; } -void FTDF_setCslSampleTime(void) +void ftdf_set_csl_sample_time(void) { - FTDF_Time CSLPeriod = FTDF_pib.CSLPeriod * 10; + ftdf_time_t csl_period = ftdf_pib.csl_period * 10; - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_Time delta = (curTime - FTDF_startCslSampleTime); + ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t delta = (cur_time - ftdf_start_csl_sample_time); - // A delta larger than 0x80000000 is assumed a negative delta, in this case the sample time does - // not need to be updated. - if (delta < 0x80000000) - { - if (delta < CSLPeriod) - { - FTDF_startCslSampleTime += CSLPeriod; + /* A delta larger than 0x80000000 is assumed a negative delta, in this case the sample time + * does not need to be updated. */ + if (delta < 0x80000000) { + if (delta < csl_period) { + ftdf_start_csl_sample_time += csl_period; - if (delta < 3) - { - // To avoid to set the CSL sample time to a time stamp in the past set it to a sample period later - // if the next sample would be within 3 symbols. - FTDF_startCslSampleTime += CSLPeriod; - } - } - else - { - FTDF_startCslSampleTime = FTDF_startCslSampleTime + ((delta / CSLPeriod) + 1) * CSLPeriod; + if (delta < 3) { + /* To avoid to set the CSL sample time to a time stamp in the past + * set it to a sample period later if the next sample would be + * within 3 symbols. */ + ftdf_start_csl_sample_time += csl_period; + } + + } else { + + ftdf_start_csl_sample_time = + ftdf_start_csl_sample_time + ((delta / csl_period) + 1) * csl_period; + } + + REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, ftdf_start_csl_sample_time); } - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME, FTDF_startCslSampleTime); - } - - FTDF_exitCritical(); + ftdf_exit_critical(); } #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ -FTDF_Time64 FTDF_getCurTime64(void) +ftdf_time64_t ftdf_get_cur_time64(void) { - FTDF_Time newTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t new_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - if (newTime < FTDF_curTime[ 0 ]) - { - FTDF_curTime[ 1 ]++; - } + if (new_time < ftdf_cur_time[0]) { + ftdf_cur_time[1]++; + } - FTDF_curTime[ 0 ] = newTime; + ftdf_cur_time[0] = new_time; - return *(FTDF_Time64 *)FTDF_curTime; + return *(ftdf_time64_t*)ftdf_cur_time; } -void FTDF_initCurTime64(void) +void ftdf_init_cur_time64(void) { - FTDF_curTime[ 0 ] = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_curTime[ 1 ] = 0; + ftdf_cur_time[0] = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + ftdf_cur_time[1] = 0; } -void FTDF_getExtAddress(void) +void ftdf_get_ext_address(void) { - uint32_t *extAddress = (uint32_t *) &FTDF_pib.extAddress; - extAddress[ 0 ] = FTDF_GET_FIELD(ON_OFF_REGMAP_AEXTENDEDADDRESS_L); - extAddress[ 1 ] = FTDF_GET_FIELD(ON_OFF_REGMAP_AEXTENDEDADDRESS_H); + uint32_t *ext_address = (uint32_t*)&ftdf_pib.ext_address; + + ext_address[0] = REG_GETF(FTDF, FTDF_GLOB_CONTROL_2_REG, AEXTENDEDADDRESS_L); + ext_address[1] = REG_GETF(FTDF, FTDF_GLOB_CONTROL_3_REG, AEXTENDEDADDRESS_H); } -void FTDF_setExtAddress(void) +void ftdf_set_ext_address(void) { - uint32_t *extAddress = (uint32_t *) &FTDF_pib.extAddress; - FTDF_SET_FIELD(ON_OFF_REGMAP_AEXTENDEDADDRESS_L, extAddress[ 0 ]); - FTDF_SET_FIELD(ON_OFF_REGMAP_AEXTENDEDADDRESS_H, extAddress[ 1 ]); + uint32_t *ext_address = (uint32_t*)&ftdf_pib.ext_address; + + REG_SETF(FTDF, FTDF_GLOB_CONTROL_2_REG, AEXTENDEDADDRESS_L, ext_address[0]); + REG_SETF(FTDF, FTDF_GLOB_CONTROL_3_REG, AEXTENDEDADDRESS_H, ext_address[1]); } -void FTDF_getAckWaitDuration(void) +void ftdf_get_ack_wait_duration(void) { - FTDF_pib.ackWaitDuration = FTDF_GET_FIELD(ON_OFF_REGMAP_MACACKWAITDURATION); + ftdf_pib.ack_wait_duration = REG_GETF(FTDF, FTDF_MACACKWAITDURATION_REG, MACACKWAITDURATION); } #ifndef FTDF_LITE -void FTDF_getEnhAckWaitDuration(void) +void ftdf_get_enh_ack_wait_duration(void) { - FTDF_pib.enhAckWaitDuration = FTDF_GET_FIELD(ON_OFF_REGMAP_MACENHACKWAITDURATION); + ftdf_pib.enh_ack_wait_duration = REG_GETF(FTDF, FTDF_MACENHACKWAITDURATION_REG, + MACENHACKWAITDURATION); } -void FTDF_setEnhAckWaitDuration(void) +void ftdf_set_enh_ack_wait_duration(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACENHACKWAITDURATION, FTDF_pib.enhAckWaitDuration); + REG_SETF(FTDF, FTDF_MACENHACKWAITDURATION_REG, MACENHACKWAITDURATION, + ftdf_pib.enh_ack_wait_duration); } -void FTDF_getImplicitBroadcast(void) +void ftdf_get_implicit_broadcast(void) { - FTDF_pib.implicitBroadcast = FTDF_GET_FIELD(ON_OFF_REGMAP_MACIMPLICITBROADCAST); + ftdf_pib.implicit_broadcast = REG_GETF(FTDF, FTDF_RX_CONTROL_0_REG, MACIMPLICITBROADCAST); } -void FTDF_setImplicitBroadcast(void) +void ftdf_set_implicit_broadcast(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACIMPLICITBROADCAST, FTDF_pib.implicitBroadcast); + REG_SETF(FTDF, FTDF_RX_CONTROL_0_REG, MACIMPLICITBROADCAST, ftdf_pib.implicit_broadcast); } #endif /* !FTDF_LITE */ -void FTDF_setShortAddress(void) +void ftdf_set_short_address(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACSHORTADDRESS, FTDF_pib.shortAddress); + REG_SETF(FTDF, FTDF_GLOB_CONTROL_1_REG, MACSHORTADDRESS, ftdf_pib.short_address); } #ifndef FTDF_LITE -void FTDF_setSimpleAddress(void) +void ftdf_set_simple_address(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACSIMPLEADDRESS, FTDF_pib.simpleAddress); + REG_SETF(FTDF, FTDF_GLOB_CONTROL_0_REG, MACSIMPLEADDRESS, ftdf_pib.simple_address); } #endif /* !FTDF_LITE */ -void FTDF_getRxOnWhenIdle(void) +void ftdf_get_rx_on_when_idle(void) { - FTDF_pib.rxOnWhenIdle = FTDF_GET_FIELD(ON_OFF_REGMAP_RXALWAYSON); + ftdf_pib.rx_on_when_idle = REG_GETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXALWAYSON); } -void FTDF_setRxOnWhenIdle(void) +void ftdf_set_rx_on_when_idle(void) { -#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI - /* We do not force decision here. It will be automatically made when FTDF begins - * transaction. - */ - hw_coex_update_ftdf_pti((hw_coex_pti_t) FTDF_getRxPti(), NULL, false); -#endif /* FTDF_USE_PTI && !FTDF_USE_AUTO_PTI */ - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_RXALWAYSON, FTDF_pib.rxOnWhenIdle); - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 1); +#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI + /* We do not force decision here. It will be automatically made when FTDF begins + * transaction. + */ + hw_coex_update_ftdf_pti((hw_coex_pti_t)ftdf_get_rx_pti(), NULL, false); +#endif /* dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI */ + ftdf_set_link_quality_mode(); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 0); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXALWAYSON, ftdf_pib.rx_on_when_idle); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 1); } -void FTDF_getPANId(void) +void ftdf_getpan_id(void) { - FTDF_pib.PANId = FTDF_GET_FIELD(ON_OFF_REGMAP_MACPANID); + ftdf_pib.pan_id = REG_GETF(FTDF, FTDF_GLOB_CONTROL_1_REG, MACPANID); } -void FTDF_setPANId(void) +void ftdf_setpan_id(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACPANID, FTDF_pib.PANId); + REG_SETF(FTDF, FTDF_GLOB_CONTROL_1_REG, MACPANID, ftdf_pib.pan_id); } -void FTDF_getCurrentChannel(void) +void ftdf_get_current_channel(void) { - FTDF_pib.currentChannel = ((FTDF_GET_FIELD(ON_OFF_REGMAP_PHYRXATTR) & 0x00f0) >> 4) + 11; + ftdf_pib.current_channel = (REG_GETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN)) + 11; } -void FTDF_setCurrentChannel(void) +void ftdf_set_current_channel(void) { - uint32_t phyAckAttr = 0x08 | ((FTDF_pib.currentChannel - 11) & 0xf) << 4 | (FTDF_pib.TXPower & 0x7) << 12; + uint32_t phy_ack_attr = 0; - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYRXATTR, (((FTDF_pib.currentChannel - 11) & 0xf) << 4)); - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYACKATTR, phyAckAttr); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN, (ftdf_pib.current_channel - 11)); + + ftdf_set_link_quality_mode(); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_DEM_PTI, phy_ack_attr, 0x08); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_CN, phy_ack_attr, + (ftdf_pib.current_channel - 11)); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_RF_GPIO_PINS, phy_ack_attr, + (ftdf_pib.tx_power & 0x07)); + + FTDF->FTDF_LMAC_CONTROL_4_REG = phy_ack_attr; } -void FTDF_setTXPower(void) +void ftdf_set_tx_power(void) { - /* Just like setCurrentChannel, this sets pyAckAttr */ - uint32_t phyAckAttr = 0x08 | ((FTDF_pib.currentChannel - 11) & 0xf) << 4 | (FTDF_pib.TXPower & 0x7) << 12; + /* Just like setCurrentChannel, this sets pyAckAttr */ + uint32_t phy_ack_attr = 0; - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYACKATTR, phyAckAttr); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_DEM_PTI, phy_ack_attr, 0x08); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_CN, phy_ack_attr, + (ftdf_pib.current_channel - 11)); + REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_RF_GPIO_PINS, phy_ack_attr, + (ftdf_pib.tx_power & 0x07)); + + FTDF->FTDF_LMAC_CONTROL_4_REG = phy_ack_attr; } -void FTDF_getMaxFrameTotalWaitTime(void) +void ftdf_get_max_frame_total_wait_time(void) { - FTDF_pib.maxFrameTotalWaitTime = FTDF_GET_FIELD(ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME); + ftdf_pib.max_frame_total_wait_time = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, MACMAXFRAMETOTALWAITTIME); } -void FTDF_setMaxFrameTotalWaitTime(void) +void ftdf_set_max_frame_total_wait_time(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME, FTDF_pib.maxFrameTotalWaitTime); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, MACMAXFRAMETOTALWAITTIME, ftdf_pib.max_frame_total_wait_time); } -void FTDF_setMaxCSMABackoffs(void) +void ftdf_set_max_csma_backoffs(void) { #ifndef FTDF_LITE - - if (FTDF_pib.leEnabled == FTDF_FALSE && FTDF_pib.tschEnabled == FTDF_FALSE) + if ((ftdf_pib.le_enabled == FTDF_FALSE) && (ftdf_pib.tsch_enabled == FTDF_FALSE)) #endif /* !FTDF_LITE */ - { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMAXCSMABACKOFFS, FTDF_pib.maxCSMABackoffs); - } + { + REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXCSMABACKOFFS, ftdf_pib.max_csma_backoffs); + } } -void FTDF_setMaxBE(void) +void ftdf_set_max_be(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMAXBE, FTDF_pib.maxBE); + REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXBE, ftdf_pib.max_be); } -void FTDF_setMinBE(void) +void ftdf_set_min_be(void) { #ifndef FTDF_LITE - - if (FTDF_pib.leEnabled == FTDF_FALSE && FTDF_pib.tschEnabled == FTDF_FALSE) + if ((ftdf_pib.le_enabled == FTDF_FALSE) && (ftdf_pib.tsch_enabled == FTDF_FALSE)) #endif /* !FTDF_LITE */ - { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMINBE, FTDF_pib.minBE); - } + { + REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMINBE, ftdf_pib.min_be); + } } #ifndef FTDF_LITE #ifndef FTDF_NO_CSL -void FTDF_setLeEnabled(void) +void ftdf_set_le_enabled(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSAMPLEPERIOD, 66); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLDATAPERIOD, 66); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLMARGINRZ, 1); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACCSLSAMPLEPERIOD, 66); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_9_REG, MACCSLDATAPERIOD, 66); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_10_REG, MACCSLMARGINRZ, 1); - if (FTDF_pib.leEnabled) - { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMAXCSMABACKOFFS, 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMINBE, 0); + if (ftdf_pib.le_enabled) { + REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXCSMABACKOFFS, 0); + REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMINBE, 0); - if (FTDF_oldLeEnabled == FTDF_FALSE) - { - if (FTDF_wakeUpEnableLe == FTDF_FALSE) - { - FTDF_startCslSampleTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_setCslSampleTime(); - } - else - { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME, FTDF_startCslSampleTime); - } + if (ftdf_old_le_enabled == FTDF_FALSE) { + + if (ftdf_wake_up_enable_le == FTDF_FALSE) { + ftdf_start_csl_sample_time = + REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + ftdf_set_csl_sample_time(); + + } else { + + REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, + ftdf_start_csl_sample_time); + } + } + + } else { + + REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXCSMABACKOFFS, ftdf_pib.max_csma_backoffs); + REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMINBE, ftdf_pib.min_be); } - } - else - { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMAXCSMABACKOFFS, FTDF_pib.maxCSMABackoffs); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACMINBE, FTDF_pib.minBE); - } - FTDF_SET_FIELD(ON_OFF_REGMAP_MACLEENABLED, FTDF_pib.leEnabled); + REG_SETF(FTDF, FTDF_GLOB_CONTROL_0_REG, MACLEENABLED, ftdf_pib.le_enabled); - FTDF_oldLeEnabled = FTDF_pib.leEnabled; + ftdf_old_le_enabled = ftdf_pib.le_enabled; } -void FTDF_getCslFramePendingWaitT(void) +void ftdf_get_csl_frame_pending_wait(void) { - FTDF_pib.CSLFramePendingWaitT = FTDF_GET_FIELD(ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT); + ftdf_pib.csl_frame_pending_wait = REG_GETF(FTDF, FTDF_LMAC_CONTROL_9_REG, MACCSLFRAMEPENDINGWAITT); } -void FTDF_setCslFramePendingWaitT(void) +void ftdf_set_csl_frame_pending_wait(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT, FTDF_pib.CSLFramePendingWaitT); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_9_REG, MACCSLFRAMEPENDINGWAITT, + ftdf_pib.csl_frame_pending_wait); } #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ -void FTDF_getLmacPmData(void) +void ftdf_get_lmac_pm_data(void) { - FTDF_pib.performanceMetrics.FCSErrorCount = FTDF_GET_FIELD(ON_OFF_REGMAP_MACFCSERRORCOUNT) + - FTDF_lmacCounters.fcsErrorCnt; + ftdf_pib.performance_metrics.fcs_error_count = + REG_GETF(FTDF, FTDF_MACFCSERRORCOUNT_REG, MACFCSERRORCOUNT) + + ftdf_lmac_counters.fcs_error_cnt; } -void FTDF_getLmacTrafficCounters(void) +void ftdf_get_lmac_traffic_counters(void) { - FTDF_pib.trafficCounters.txStdAckFrmCnt = FTDF_GET_FIELD(ON_OFF_REGMAP_MACTXSTDACKFRMCNT) + - FTDF_lmacCounters.txStdAckCnt; - FTDF_pib.trafficCounters.rxStdAckFrmOkCnt = FTDF_GET_FIELD(ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT) + - FTDF_lmacCounters.rxStdAckCnt; + ftdf_pib.traffic_counters.tx_std_ack_frm_cnt = + REG_GETF(FTDF, FTDF_MACTXSTDACKFRMCNT_REG, MACTXSTDACKFRMCNT) + + ftdf_lmac_counters.tx_std_ack_cnt; + + ftdf_pib.traffic_counters.rx_std_ack_frm_ok_cnt = + REG_GETF(FTDF, FTDF_MACRXSTDACKFRMOKCNT_REG, MACRXSTDACKFRMOKCNT) + + ftdf_lmac_counters.rx_std_ack_cnt; } -void FTDF_getKeepPhyEnabled(void) +void ftdf_get_keep_phy_enabled(void) { - FTDF_pib.keepPhyEnabled = FTDF_GET_FIELD(ON_OFF_REGMAP_KEEP_PHY_EN); + ftdf_pib.keep_phy_enabled = REG_GETF(FTDF, FTDF_LMAC_CONTROL_0_REG, KEEP_PHY_EN); } -void FTDF_setKeepPhyEnabled(void) +void ftdf_set_keep_phy_enabled(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_KEEP_PHY_EN, FTDF_pib.keepPhyEnabled); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, KEEP_PHY_EN, ftdf_pib.keep_phy_enabled); } -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -void FTDF_setBoIrqThreshold(void) +void ftdf_set_bo_irq_threshold(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD, FTDF_pib.boIrqThreshold); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_BO_THRESHOLD, ftdf_pib.bo_irq_threshold); } -void FTDF_getBoIrqThreshold(void) +void ftdf_get_bo_irq_threshold(void) { - FTDF_pib.boIrqThreshold = FTDF_GET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD); + ftdf_pib.bo_irq_threshold = REG_GETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_BO_THRESHOLD); } -void FTDF_setPtiConfig(void) +void ftdf_set_pti_config(void) { - FTDF_SET_FIELD_INDEXED(ON_OFF_REGMAP_PTI_TX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_TX], - FTDF_TX_DATA_BUFFER); - FTDF_SET_FIELD_INDEXED(ON_OFF_REGMAP_PTI_TX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_TX], - FTDF_TX_WAKEUP_BUFFER); - FTDF_SET_FIELD_INDEXED(ON_OFF_REGMAP_PTI_TX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_RX], - FTDF_TX_ACK_BUFFER); - FTDF_SET_FIELD(ON_OFF_REGMAP_PTI_RX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_RX]); + REG_SETF(FTDF, FTDF_TX_PRIORITY_0_REG, PTI_TX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_TX]); + REG_SETF(FTDF, FTDF_TX_PRIORITY_1_REG, PTI_TX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_TX]); + REG_SETF(FTDF, FTDF_TX_PRIORITY_2_REG, PTI_TX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_RX]); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, PTI_RX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_RX]); } -#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ #ifndef FTDF_LITE #ifndef FTDF_NO_TSCH -void FTDF_setTimeslotTemplate(void) +void ftdf_set_timeslot_template(void) { - FTDF_SET_FIELD(ON_OFF_REGMAP_MACTSTXACKDELAY, FTDF_pib.timeslotTemplate.tsTxAckDelay); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACTSRXWAIT, FTDF_pib.timeslotTemplate.tsRxWait); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACTSRXACKDELAY, FTDF_pib.timeslotTemplate.tsRxAckDelay); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACTSACKWAIT, FTDF_pib.timeslotTemplate.tsAckWait); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACTSRXTX, FTDF_pib.timeslotTemplate.tsRxTx - - FTDF_PHYTRXWAIT - FTDF_PHYTXSTARTUP - FTDF_PHYTXLATENCY); + REG_SETF(FTDF, FTDF_TSCH_CONTROL_0_REG, MACTSTXACKDELAY, + ftdf_pib.timeslot_template.ts_tx_ack_delay); + REG_SETF(FTDF, FTDF_TSCH_CONTROL_0_REG, MACTSRXWAIT, ftdf_pib.timeslot_template.ts_rx_wait); + REG_SETF(FTDF, FTDF_TSCH_CONTROL_2_REG, MACTSRXACKDELAY, + ftdf_pib.timeslot_template.ts_rx_ack_delay); + REG_SETF(FTDF, FTDF_TSCH_CONTROL_2_REG, MACTSACKWAIT, + ftdf_pib.timeslot_template.ts_ack_wait); + REG_SETF(FTDF, FTDF_TSCH_CONTROL_1_REG, MACTSRXTX, (ftdf_pib.timeslot_template.ts_rx_tx - + FTDF_PHYTRXWAIT - FTDF_PHYTXSTARTUP - FTDF_PHYTXLATENCY)); } #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO /************************************ FPPR common functions ***************************************/ #ifndef FTDF_LITE -FTDF_Boolean FTDF_fpFsmShortAddressNew(FTDF_PANId panId, FTDF_ShortAddress shortAddress) +ftdf_boolean_t ftdf_fp_fsm_short_address_new(ftdf_pan_id_t panId, ftdf_short_address_t short_address) { - uint8_t entry; - uint8_t shortAddrIdx; + uint8_t entry; + uint8_t short_addr_idx; - if (FTDF_fpprGetFreeShortAddress(&entry, &shortAddrIdx) == FTDF_FALSE) - { - return FTDF_FALSE; - } + if (ftdf_fppr_get_free_short_address(&entry, &short_addr_idx) == FTDF_FALSE) { + return FTDF_FALSE; + } - FTDF_fpprSetShortAddress(entry, shortAddrIdx, shortAddress); - FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_TRUE); + ftdf_fppr_set_short_address(entry, short_addr_idx, short_address); + ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_TRUE); - return FTDF_TRUE; + return FTDF_TRUE; } -FTDF_Boolean FTDF_fpFsmExtAddressNew(FTDF_PANId panId, FTDF_ExtAddress extAddress) +ftdf_boolean_t ftdf_fp_fsm_rxt_address_new(ftdf_pan_id_t panId, ftdf_ext_address_t ext_address) { - uint8_t entry; + uint8_t entry; - if (FTDF_fpprGetFreeExtAddress(&entry) == FTDF_FALSE) - { - return FTDF_FALSE; - } + if (ftdf_fppr_get_free_ext_address(&entry) == FTDF_FALSE) { + return FTDF_FALSE; + } - FTDF_fpprSetExtAddress(entry, extAddress); - FTDF_fpprSetExtAddressValid(entry, FTDF_TRUE); + ftdf_fppr_set_ext_address(entry, ext_address); + ftdf_fppr_set_ext_address_valid(entry, FTDF_TRUE); - return FTDF_TRUE; + return FTDF_TRUE; } -void FTDF_fpFsmShortAddressLastFramePending(FTDF_PANId PANId, FTDF_ShortAddress shortAddress) -{ +void ftdf_fp_fsm_short_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_short_address_t short_address) { #if FTDF_FPPR_DEFER_INVALIDATION - FTDF_fpprPending.addrMode = FTDF_SHORT_ADDRESS; - FTDF_fpprPending.PANId = PANId; - FTDF_fpprPending.addr.shortAddress = shortAddress; + ftdf_fppr_pending.addr_mode = FTDF_SHORT_ADDRESS; + ftdf_fppr_pending.pan_id = pan_id; + ftdf_fppr_pending.addr.short_address = short_address; #else /* FTDF_FPPR_DEFER_INVALIDATION */ - uint8_t entry; - uint8_t shortAddrIdx; - FTDF_Boolean found = FTDF_fpprLookupShortAddress(shortAddress, &entry, &shortAddrIdx); - ASSERT_WARNING(found); - FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); + uint8_t entry; + uint8_t short_addr_idx; + ftdf_boolean_t found = ftdf_fppr_lookup_short_address(short_address, &entry, &short_addr_idx); + ASSERT_WARNING(found); + ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_FALSE); #endif /* FTDF_FPPR_DEFER_INVALIDATION */ } -void FTDF_fpFsmExtAddressLastFramePending(FTDF_PANId PANId, FTDF_ExtAddress extAddress) -{ +void ftdf_fp_fsm_ext_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_ext_address_t ext_address) { #if FTDF_FPPR_DEFER_INVALIDATION - FTDF_fpprPending.addrMode = FTDF_EXTENDED_ADDRESS; - FTDF_fpprPending.PANId = PANId; - FTDF_fpprPending.addr.extAddress = extAddress; + ftdf_fppr_pending.addr_mode = FTDF_EXTENDED_ADDRESS; + ftdf_fppr_pending.pan_id = pan_id; + ftdf_fppr_pending.addr.ext_address = ext_address; #else /* FTDF_FPPR_DEFER_INVALIDATION */ - uint8_t entry; - FTDF_Boolean found = FTDF_fpprLookupExtAddress(extAddress, &entry); - ASSERT_WARNING(found); - FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); + uint8_t entry; + ftdf_boolean_t found = ftdf_fppr_lookup_ext_address(ext_address, &entry); + ASSERT_WARNING(found); + ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); #endif /* FTDF_FPPR_DEFER_INVALIDATION */ } -void FTDF_fpFsmClearPending(void) +void ftdf_fp_fsm_clear_pending(void) { #if FTDF_FPPR_DEFER_INVALIDATION - int n; - - if (FTDF_fpprPending.addrMode == FTDF_NO_ADDRESS) - { - return; - } - - if (FTDF_fpprPending.addrMode == FTDF_SHORT_ADDRESS) - { - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) - { - if (FTDF_txPendingList[ n ].addrMode == FTDF_SHORT_ADDRESS) - { - if ((FTDF_txPendingList[ n ].PANId == FTDF_fpprPending.PANId) && - (FTDF_txPendingList[ n ].addr.shortAddress == - FTDF_fpprPending.addr.shortAddress)) - { - return; - } - } + int n; + if (ftdf_fppr_pending.addr_mode == FTDF_NO_ADDRESS) { + return; } - - // Address not found. - uint8_t entry; - uint8_t shortAddrIdx; - FTDF_Boolean found = FTDF_fpprLookupShortAddress( - FTDF_fpprPending.addr.shortAddress, &entry, &shortAddrIdx); - ASSERT_WARNING(found); - FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); - } - else if (FTDF_fpprPending.addrMode == FTDF_EXTENDED_ADDRESS) - { - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) - { - if (FTDF_txPendingList[ n ].addrMode == FTDF_EXTENDED_ADDRESS) - { - if (FTDF_txPendingList[ n ].addr.extAddress == - FTDF_fpprPending.addr.extAddress) - { - return; + if (ftdf_fppr_pending.addr_mode == FTDF_SHORT_ADDRESS) { + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { + if (ftdf_tx_pending_list[n].addr_mode == FTDF_SHORT_ADDRESS) { + if ((ftdf_tx_pending_list[n].pan_id == ftdf_fppr_pending.pan_id) && + (ftdf_tx_pending_list[n].addr.short_address == + ftdf_fppr_pending.addr.short_address)) { + return; + } + } } - } + // Address not found. + uint8_t entry; + uint8_t short_addr_idx; + ftdf_boolean_t found = ftdf_fppr_lookup_short_address( + ftdf_fppr_pending.addr.short_address, &entry, &short_addr_idx); + ASSERT_WARNING(found); + ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_FALSE); + } else if (ftdf_fppr_pending.addr_mode == FTDF_EXTENDED_ADDRESS) { + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { + if (ftdf_tx_pending_list[n].addr_mode == FTDF_EXTENDED_ADDRESS) { + if (ftdf_tx_pending_list[n].addr.ext_address == + ftdf_fppr_pending.addr.ext_address) { + return; + } + } + } + // Address not found. + uint8_t entry; + ftdf_boolean_t found = ftdf_fppr_lookup_ext_address(ftdf_fppr_pending.addr.ext_address, + &entry); + ASSERT_WARNING(found); + ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); + } else { + } - - // Address not found. - uint8_t entry; - FTDF_Boolean found = FTDF_fpprLookupExtAddress(FTDF_fpprPending.addr.extAddress, - &entry); - ASSERT_WARNING(found); - FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); - } - else - { - - } - - FTDF_fpprPending.addrMode = FTDF_NO_ADDRESS; + ftdf_fppr_pending.addr_mode = FTDF_NO_ADDRESS; #endif /* FTDF_FPPR_DEFER_INVALIDATION */ } #endif /* #ifndef FTDF_LITE */ /*********************************** FPPR low-level access ****************************************/ -void FTDF_fpprReset(void) +void ftdf_fppr_reset(void) { - unsigned int i; - - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) - { - *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i) = 0; - } -} - -FTDF_ShortAddress FTDF_fpprGetShortAddress(uint8_t entry, uint8_t shortAddrIdx) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - - switch (shortAddrIdx) - { - case 0: - return (FTDF_ShortAddress) - * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) & - 0x0000ffff; - - case 1: - return (FTDF_ShortAddress) - (*FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) >> 16) & - 0x0000ffff; - - case 2: - return (FTDF_ShortAddress) - * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) & - 0x0000ffff; - - case 3: - return (FTDF_ShortAddress) - (*FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) >> 16) & - 0x0000ffff; - - default: - ASSERT_WARNING(0); - } -} - -void FTDF_fpprSetShortAddress(uint8_t entry, uint8_t shortAddrIdx, - FTDF_ShortAddress shortAddress) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - uint32_t val32; - - switch (shortAddrIdx) - { - case 0: - val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry); - val32 &= 0xffff0000; - val32 |= (shortAddress & 0x0000ffff); - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) = val32; - break; - - case 1: - val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry); - val32 &= 0x0000ffff; - val32 |= (shortAddress & 0x0000ffff) << 16; - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) = val32; - break; - - case 2: - val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry); - val32 &= 0xffff0000; - val32 |= (shortAddress & 0x0000ffff); - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) = val32; - break; - - case 3: - val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry); - val32 &= 0x0000ffff; - val32 |= (shortAddress & 0x0000ffff) << 16; - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) = val32; - break; - - default: - ASSERT_WARNING(0); - } -} - -FTDF_Boolean FTDF_fpprGetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - ASSERT_WARNING(shortAddrIdx < 4); - uint32_t val32; - val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry); - return ((val32 & (MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT | (1 << shortAddrIdx))) == - (MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT | (1 << shortAddrIdx))) ? - FTDF_TRUE : FTDF_FALSE; -} - -void FTDF_fpprSetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx, - FTDF_Boolean valid) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - ASSERT_WARNING(shortAddrIdx < 4); - uint32_t val32; - val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry); - - if (valid) - { - val32 |= MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT | (1 << shortAddrIdx); /* Also indicate short address. */ - } - else - { - val32 &= ~(1 << shortAddrIdx); - } - - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) = val32; -} - -FTDF_ExtAddress FTDF_fpprGetExtAddress(uint8_t entry) -{ - FTDF_ExtAddress extAddress; - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - extAddress = (FTDF_ExtAddress) * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, - entry) << 32; - extAddress |= (FTDF_ExtAddress) * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, - entry); - return extAddress; -} - -void FTDF_fpprSetExtAddress(uint8_t entry, FTDF_ExtAddress extAddress) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) = - (uint32_t)(extAddress); - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) = - (uint32_t)((extAddress >> 32)); -} - -FTDF_Boolean FTDF_fpprGetExtAddressValid(uint8_t entry) -{ - return (*FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) == 0x1) ? - FTDF_TRUE : FTDF_FALSE; -} - -void FTDF_fpprSetExtAddressValid(uint8_t entry, FTDF_Boolean valid) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - - if (valid) - { - /* Also indicate ext address. */ - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) = 0x1; - } - else - { - *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) = 0x0; - } -} - -FTDF_Boolean FTDF_fpprGetFreeShortAddress(uint8_t *entry, uint8_t *shortAddrIdx) -{ - int i, j; - uint32_t sizeAndVal; - int emptyEntry; - bool emptyFound = false, nonEmptyFound = false; - - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) - { - sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); - - if (sizeAndVal == 0x1) - { - /* Check if there is a valid extended address. */ - continue; + unsigned int i; + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { + *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i) = 0; } - else if ((sizeAndVal & MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT) == 0) - { - /* There is an invalid extended address, ignore SA valid bits */ - sizeAndVal = 0; - } - else - { - /* There is a SA. We are interested in bits V0 - V3. */ - sizeAndVal &= 0xf; +} + +ftdf_short_address_t ftdf_fppr_get_short_address(uint8_t entry, uint8_t short_addr_idx) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + switch (short_addr_idx) { + case 0: + return (ftdf_short_address_t) + *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry) & + 0x0000ffff; + case 1: + return (ftdf_short_address_t) + (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry) >> 16) & + 0x0000ffff; + case 2: + return (ftdf_short_address_t) + *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry) & + 0x0000ffff; + case 3: + return (ftdf_short_address_t) + (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry) >> 16) & + 0x0000ffff; + default: + ASSERT_WARNING(0); } +} - /* Check if entire entry is free. */ - if (sizeAndVal == 0) - { - /* We prefer to use partially full entries. Make note of this and - * continue. */ - if (!emptyFound) - { - emptyEntry = i; - emptyFound = true; - } - - continue; - } - - /* Check for free short address entries. */ - sizeAndVal = (~sizeAndVal) & 0xf; - j = 0; - - while (sizeAndVal) - { - if (sizeAndVal & 0x1) - { - nonEmptyFound = true; +void ftdf_fppr_set_short_address(uint8_t entry, uint8_t short_addr_idx, + ftdf_short_address_t short_address) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + uint32_t val32; + volatile uint32_t *long_addr_reg; + switch (short_addr_idx) { + case 0: + long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry); + val32 = *long_addr_reg; + val32 &= 0xffff0000; + val32 |= (short_address & 0x0000ffff); + *long_addr_reg = val32; break; - } - - sizeAndVal >>= 1; - j++; + case 1: + long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry); + val32 = *long_addr_reg; + val32 &= 0x0000ffff; + val32 |= (short_address & 0x0000ffff) << 16; + *long_addr_reg = val32; + break; + case 2: + long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry); + val32 = *long_addr_reg; + val32 &= 0xffff0000; + val32 |= (short_address & 0x0000ffff); + *long_addr_reg = val32; + break; + case 3: + long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry); + val32 = *long_addr_reg; + val32 &= 0x0000ffff; + val32 |= (short_address & 0x0000ffff) << 16; + *long_addr_reg = val32; + break; + default: + ASSERT_WARNING(0); } +} - if (nonEmptyFound) - { - break; +ftdf_boolean_t ftdf_fppr_get_short_address_valid(uint8_t entry, uint8_t short_addr_idx) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + ASSERT_WARNING(short_addr_idx < 4); + uint32_t val32 = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry); + return ((val32 & (REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT) | (1 << short_addr_idx))) == + (REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT) | (1 << short_addr_idx))) ? + FTDF_TRUE : FTDF_FALSE; +} + +void ftdf_fppr_set_short_address_valid(uint8_t entry, uint8_t short_addr_idx, + ftdf_boolean_t valid) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + ASSERT_WARNING(short_addr_idx < 4); + volatile uint32_t *reg_val = REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry); + if (valid) { + *reg_val |= REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT) | (1 << short_addr_idx); /* Also indicate short address. */ + } else { + *reg_val &= ~(1 << short_addr_idx); } - } +} - if (nonEmptyFound) - { - *entry = i; - *shortAddrIdx = j; - } - else if (emptyFound) - { - *entry = emptyEntry; - *shortAddrIdx = 0; - } - else - { +ftdf_ext_address_t ftdf_fppr_get_ext_address(uint8_t entry) +{ + ftdf_ext_address_t ext_address; + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + ext_address = (ftdf_ext_address_t) + (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry)) << 32; + ext_address |= (ftdf_ext_address_t) + (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry)); + + return ext_address; +} + +void ftdf_fppr_set_ext_address(uint8_t entry, ftdf_ext_address_t ext_address) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry) = (uint32_t) ext_address; + *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry) = (uint32_t) (ext_address >> 32); +} + +ftdf_boolean_t ftdf_fppr_get_ext_address_valid(uint8_t entry) +{ + return (REG_GETF_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, VALID_SA, 0x10, entry) == 0x1) ? + FTDF_TRUE : FTDF_FALSE; +} + +void ftdf_fppr_set_ext_address_valid(uint8_t entry, ftdf_boolean_t valid) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + if (valid) { + /* Also indicate ext address. */ + *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry) = 0x1; + } else { + *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry) = 0x0; + } +} + +ftdf_boolean_t ftdf_fppr_get_free_short_address(uint8_t *entry, uint8_t *short_addr_idx) +{ + int i, j; + uint32_t size_and_val; + int empty_entry; + bool empty_found = false, non_empty_found = false; + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { + size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); + if (size_and_val == 0x1) { + /* Check if there is a valid extended address. */ + continue; + } else if ((size_and_val & REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT)) == 0) { + /* There is an invalid extended address, ignore SA valid bits */ + size_and_val = 0; + } else { + /* There is a SA. We are interested in bits V0 - V3. */ + size_and_val &= 0xf; + } + + /* Check if entire entry is free. */ + if (size_and_val == 0) { + /* We prefer to use partially full entries. Make note of this and + * continue. */ + if (!empty_found) { + empty_entry = i; + empty_found = true; + } + continue; + } + /* Check for free short address entries. */ + size_and_val = (~size_and_val) & 0xf; + j = 0; + while (size_and_val) { + if (size_and_val & 0x1) { + non_empty_found = true; + break; + } + size_and_val >>= 1; + j++; + } + if (non_empty_found) { + break; + } + } + if (non_empty_found) { + *entry = i; + *short_addr_idx = j; + } else if (empty_found) { + *entry = empty_entry; + *short_addr_idx = 0; + } else { + return FTDF_FALSE; + } + return FTDF_TRUE; +} + +ftdf_boolean_t ftdf_fppr_get_free_ext_address(uint8_t * entry) +{ + int i; + uint32_t size_and_val; + bool found = false; + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { + size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); + /* Check if there is no valid extended or short address. */ + if (!size_and_val || (size_and_val == REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT))) { + found = true; + break; + } + } + if (found) { + *entry = i; + } else { + return FTDF_FALSE; + } + return FTDF_TRUE; +} + +ftdf_boolean_t ftdf_fppr_lookup_short_address(ftdf_short_address_t short_addr, uint8_t *entry, + uint8_t *short_addr_idx) +{ + uint8_t i; + uint32_t size_and_val; + uint32_t saPart; + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { + size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); + /* Check if there is a valid short address. */ + if (!(size_and_val & REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT)) || + !(size_and_val & REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, VALID_SA))) { + continue; + } + saPart = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, EXP_SA_L, 0x10, i); + if (size_and_val & 0x1) { + if (short_addr == (ftdf_short_address_t) (saPart & 0x0000ffff)) { + *entry = i; + *short_addr_idx = 0; + return FTDF_TRUE; + } + } + if (size_and_val & 0x2) { + if (short_addr == (ftdf_short_address_t) ((saPart >> 16) & 0x0000ffff)) { + *entry = i; + *short_addr_idx = 1; + return FTDF_TRUE; + } + } + saPart = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, EXP_SA_H, 0x10, i); + if (size_and_val & 0x4) { + if (short_addr == (ftdf_short_address_t) (saPart & 0x0000ffff)) { + *entry = i; + *short_addr_idx = 2; + return FTDF_TRUE; + } + } + if (size_and_val & 0x8) { + if (short_addr == ((ftdf_short_address_t) (saPart >> 16) & 0x0000ffff)) { + *entry = i; + *short_addr_idx = 3; + return FTDF_TRUE; + } + } + } return FTDF_FALSE; - } - - return FTDF_TRUE; } -FTDF_Boolean FTDF_fpprGetFreeExtAddress(uint8_t *entry) +ftdf_boolean_t ftdf_fppr_lookup_ext_address(ftdf_ext_address_t ext_addr, uint8_t *entry) { - int i; - uint32_t sizeAndVal; - bool found = false; - - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) - { - sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); - - /* Check if there is no valid extended or short address. */ - if (!sizeAndVal || (sizeAndVal == MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT)) - { - found = true; - break; + uint8_t i; + uint32_t size_and_val; + uint32_t ext_addr_hi, ext_addr_lo; + ext_addr_hi = (uint32_t) ((ext_addr >> 32) & 0xffffffff); + ext_addr_lo = (uint32_t) (ext_addr & 0xffffffff); + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { + size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); + /* Check if there is a valid extended address. */ + if (size_and_val != 0x1) { + continue; + } + if ((ext_addr_lo == REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, EXP_SA_L, 0x10, i)) && + (ext_addr_hi == REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, EXP_SA_H, 0x10, i))) { + *entry = i; + return FTDF_TRUE; + } } - } - - if (found) - { - *entry = i; - } - else - { return FTDF_FALSE; - } - - return FTDF_TRUE; -} - -FTDF_Boolean FTDF_fpprLookupShortAddress(FTDF_ShortAddress shortAddr, uint8_t *entry, - uint8_t *shortAddrIdx) -{ - uint8_t i; - uint32_t sizeAndVal; - uint32_t saPart; - - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) - { - sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); - - /* Check if there is a valid short address. */ - if (!(sizeAndVal & MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT) || - !(sizeAndVal & MSK_F_FTDF_FP_PROCESSING_RAM_VALID_SA)) - { - continue; - } - - saPart = FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, i); - - if (sizeAndVal & 0x1) - { - if (shortAddr == (FTDF_ShortAddress)(saPart & 0x0000ffff)) - { - *entry = i; - *shortAddrIdx = 0; - return FTDF_TRUE; - } - } - - if (sizeAndVal & 0x2) - { - if (shortAddr == (FTDF_ShortAddress)((saPart >> 16) & 0x0000ffff)) - { - *entry = i; - *shortAddrIdx = 1; - return FTDF_TRUE; - } - } - - saPart = FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, i); - - if (sizeAndVal & 0x4) - { - if (shortAddr == (FTDF_ShortAddress)(saPart & 0x0000ffff)) - { - *entry = i; - *shortAddrIdx = 2; - return FTDF_TRUE; - } - } - - if (sizeAndVal & 0x8) - { - if (shortAddr == ((FTDF_ShortAddress)(saPart >> 16) & 0x0000ffff)) - { - *entry = i; - *shortAddrIdx = 3; - return FTDF_TRUE; - } - } - } - - return FTDF_FALSE; -} - -FTDF_Boolean FTDF_fpprLookupExtAddress(FTDF_ExtAddress extAddr, uint8_t *entry) -{ - uint8_t i; - uint32_t sizeAndVal; - uint32_t extAddrHi, extAddrLo; - extAddrHi = (uint32_t)((extAddr >> 32) & 0xffffffff); - extAddrLo = (uint32_t)(extAddr & 0xffffffff); - - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) - { - sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); - - /* Check if there is a valid extended address. */ - if (sizeAndVal != 0x1) - { - continue; - } - - if ((extAddrLo == FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, i)) && - (extAddrHi == FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, i))) - { - *entry = i; - return FTDF_TRUE; - } - } - - return FTDF_FALSE; } #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ -void FTDF_fpprSetMode(FTDF_Boolean matchFp, FTDF_Boolean fpOverride, FTDF_Boolean fpForce) +void ftdf_fppr_set_mode(ftdf_boolean_t match_fp, ftdf_boolean_t fp_override, ftdf_boolean_t fp_force) { - FTDF_SET_FIELD(ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE, matchFp ? 1 : 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_FP_OVERRIDE, fpOverride ? 1 : 0); - FTDF_SET_FIELD(ON_OFF_REGMAP_FP_FORCE_VALUE, fpForce ? 1 : 0); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, ADDR_TAB_MATCH_FP_VALUE, match_fp ? 1 : 0); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_OVERRIDE,fp_override ? 1 : 0); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_FORCE_VALUE, fp_force ? 1 : 0); } #if FTDF_FP_BIT_TEST_MODE -void FTDF_fpprGetMode(FTDF_Boolean *matchFp, FTDF_Boolean *fpOverride, FTDF_Boolean *fpForce) +void ftdf_fppr_get_mode(ftdf_boolean_t *match_fp, ftdf_boolean_t *fp_override, ftdf_boolean_t *fp_force) { - *matchFp = FTDF_GET_FIELD(ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE) ? FTDF_TRUE : FTDF_FALSE; - *fpOverride = FTDF_GET_FIELD(ON_OFF_REGMAP_FP_OVERRIDE) ? FTDF_TRUE : FTDF_FALSE; - *fpForce = FTDF_GET_FIELD(ON_OFF_REGMAP_FP_FORCE_VALUE) ? FTDF_TRUE : FTDF_FALSE; + *match_fp = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, ADDR_TAB_MATCH_FP_VALUE) ? FTDF_TRUE : FTDF_FALSE; + *fp_override = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_OVERRIDE) ? FTDF_TRUE : FTDF_FALSE; + *fp_force = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_FORCE_VALUE) ? FTDF_TRUE : FTDF_FALSE; } #endif // FTDF_FP_BIT_TEST_MODE -void FTDF_lpdpEnable(FTDF_Boolean enable) +void ftdf_lpdp_enable(ftdf_boolean_t enable) { - FTDF_SET_FIELD(ON_OFF_REGMAP_FTDF_LPDP_ENABLE, enable ? 1 : 0); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FTDF_LPDP_ENABLE, enable ? 1 : 0); } #if FTDF_FP_BIT_TEST_MODE -FTDF_Boolean FTDF_lpdpIsEnabled(void) +ftdf_boolean_t ftdf_lpdp_is_enabled(void) { - return FTDF_GET_FIELD(ON_OFF_REGMAP_FTDF_LPDP_ENABLE) ? FTDF_TRUE : FTDF_FALSE; + return REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FTDF_LPDP_ENABLE) ? FTDF_TRUE : FTDF_FALSE; } #endif #if FTDF_USE_SLEEP_DURING_BACKOFF -static inline void FTDF_sdbSaveState(void) +static inline void ftdf_sdb_save_state(void) { - volatile uint32_t *txFifoPtr = FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO); - uint32_t *dstPtr = (uint32_t *) FTDF_sdb.buffer; - uint8_t word_length_rem; + volatile uint32_t *tx_fifo_ptr = &FTDF->FTDF_TX_FIFO_0_0_REG; + uint32_t * dstPtr = (uint32_t *) ftdf_sdb.buffer; + uint8_t word_length_rem; - FTDF_sdb.nrOfBackoffs = FTDF_GET_FIELD(ON_OFF_REGMAP_CSMA_CA_NB_STAT); + ftdf_sdb.nr_of_backoffs = REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, CSMA_CA_NB_STAT); - /* Read first 4 bytes. */ - *dstPtr++ = *txFifoPtr++; + /* Read first 4 bytes. */ + *dstPtr++ = *tx_fifo_ptr++; - ASSERT_WARNING((FTDF_sdb.buffer[0] >= 3) && (FTDF_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); - /* The length is the buffer length excluding the length byte itself */ - word_length_rem = (FTDF_sdb.buffer[0] + 4) / 4 - 1; /* 1 word we already read */ + ASSERT_WARNING((ftdf_sdb.buffer[0] >= 3) && (ftdf_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); + /* The length is the buffer length excluding the length byte itself */ + word_length_rem = (ftdf_sdb.buffer[0] + 4) / 4 - 1; /* 1 word we already read */ - while (word_length_rem--) - { - *dstPtr++ = *txFifoPtr++; - } - - FTDF_sdb.metadata0 = *FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, - FTDF_TX_DATA_BUFFER); - FTDF_sdb.metadata1 = *FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, - FTDF_TX_DATA_BUFFER); - FTDF_sdb.phyCsmaCaAttr = FTDF_GET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR); -} - -static inline void FTDF_sdbResume(void) -{ - volatile uint32_t *txFifoPtr = FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO); - volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); - uint32_t *srcPtr = (uint32_t *) FTDF_sdb.buffer; - - uint8_t word_length_rem; - - FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_NB_VAL, FTDF_sdb.nrOfBackoffs); - - FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_RESUME_SET, 1); - - ASSERT_WARNING((FTDF_sdb.buffer[0] >= 3) && (FTDF_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); - - /* The length is the buffer length excluding the length byte itself */ - word_length_rem = (FTDF_sdb.buffer[0] + 4) / 4; - - while (word_length_rem--) - { - *txFifoPtr++ = *srcPtr++; - } - - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR, FTDF_sdb.phyCsmaCaAttr); - - *FTDF_GET_REG_ADDR(RETENTION_RAM_TX_META_DATA_0) = FTDF_sdb.metadata0; - - *FTDF_GET_REG_ADDR(RETENTION_RAM_TX_META_DATA_1) = FTDF_sdb.metadata1; - - *txFlagSet |= (1 << FTDF_TX_DATA_BUFFER); -} - -static inline void FTDF_sdbReset(void) -{ - FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR, 1); -} - -static inline void FTDF_sdbSetCCARetryTime(void) -{ - FTDF_Time timestamp = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_Time boStat = FTDF_GET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_STAT) * - FTDF_UNIT_BACKOFF_PERIOD; - FTDF_sdb.ccaRetryTime = timestamp + boStat; -} - -void FTDF_sdbFsmReset(void) -{ - FTDF_sdbReset(); - FTDF_sdb.state = FTDF_SDB_STATE_INIT; -} - -void FTDF_sdbFsmBackoffIRQ(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - return; - } - -#endif - - switch (FTDF_sdb.state) - { - case FTDF_SDB_STATE_RESUMING: - FTDF_sdbReset(); - - case FTDF_SDB_STATE_INIT: - case FTDF_SDB_STATE_BACKING_OFF: - FTDF_sdbSetCCARetryTime(); - FTDF_sdb.state = FTDF_SDB_STATE_BACKING_OFF; - break; - - default: - ASSERT_WARNING(0); - } -} - -void FTDF_sdbFsmSleep(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - return; - } - -#endif - - switch (FTDF_sdb.state) - { - case FTDF_SDB_STATE_BACKING_OFF: - FTDF_sdbSaveState(); - FTDF_sdb.state = FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ; - break; - - case FTDF_SDB_STATE_INIT: - break; - - default: - ASSERT_WARNING(0); - } -} - -void FTDF_sdbFsmAbortSleep(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - return; - } - -#endif - - switch (FTDF_sdb.state) - { - case FTDF_SDB_STATE_BACKING_OFF: - FTDF_sdb.state = FTDF_SDB_STATE_INIT; - break; - - case FTDF_SDB_STATE_INIT: - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - case FTDF_SDB_STATE_RESUMING: - break; - - default: - ASSERT_WARNING(0); - } -} - -void FTDF_sdbFsmWakeUpIRQ(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - return; - } - -#endif - - switch (FTDF_sdb.state) - { - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - FTDF_sdb.state = FTDF_SDB_STATE_RESUMING; - break; - - case FTDF_SDB_STATE_INIT: - break; - - default: - ASSERT_WARNING(0); - } -} - -void FTDF_sdbFsmWakeUp(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - return; - } - -#endif - - switch (FTDF_sdb.state) - { - case FTDF_SDB_STATE_RESUMING: - FTDF_sdbResume(); - break; - - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - break; - - case FTDF_SDB_STATE_INIT: - break; - - default: - ASSERT_WARNING(0); - } -} - -void FTDF_sdbFsmTxIRQ(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - return; - } - -#endif - - switch (FTDF_sdb.state) - { - case FTDF_SDB_STATE_RESUMING: - FTDF_sdbReset(); - FTDF_sdb.state = FTDF_SDB_STATE_INIT; - break; - - case FTDF_SDB_STATE_BACKING_OFF: - FTDF_sdb.state = FTDF_SDB_STATE_INIT; - break; - - case FTDF_SDB_STATE_INIT: - break; - - default: - ASSERT_WARNING(0); - } -} - -FTDF_USec FTDF_sdbGetSleepTime(void) -{ - FTDF_USec sleepTime = ~((FTDF_USec) 0); -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - return sleepTime; - } - -#endif - - switch (FTDF_sdb.state) - { - case FTDF_SDB_STATE_INIT: - { - if ((FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) || FTDF_reqCurrent) - { - sleepTime = 0; - } - else - { - sleepTime = ~((FTDF_USec) 0); + while (word_length_rem--) { + *dstPtr++ = *tx_fifo_ptr++; } - break; - } + ftdf_sdb.metadata_0 = FTDF->FTDF_TX_META_DATA_0_0_REG; + ftdf_sdb.metadata_1 = FTDF->FTDF_TX_META_DATA_1_0_REG; - case FTDF_SDB_STATE_BACKING_OFF: - { - FTDF_Time currentTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + ftdf_sdb.phy_csma_ca_attr = FTDF->FTDF_LMAC_CONTROL_5_REG; +} - if (currentTime <= FTDF_sdb.ccaRetryTime) - { - sleepTime = (FTDF_sdb.ccaRetryTime - currentTime) * 16; - } - else - { - sleepTime = (1 << SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL - 1) - - (currentTime + FTDF_sdb.ccaRetryTime) * 16; +static inline void ftdf_sdb_resume(void) +{ + volatile uint32_t *tx_fifo_ptr = &FTDF->FTDF_TX_FIFO_0_0_REG; + uint32_t * src_ptr = (uint32_t *) ftdf_sdb.buffer; + + uint8_t word_length_rem; + + REG_SETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_NB_VAL, ftdf_sdb.nr_of_backoffs); + + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, CSMA_CA_RESUME_SET, 1); + + ASSERT_WARNING((ftdf_sdb.buffer[0] >= 3) && (ftdf_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); + + /* The length is the buffer length excluding the length byte itself */ + word_length_rem = (ftdf_sdb.buffer[0] + 4) / 4; + + while (word_length_rem--) { + *tx_fifo_ptr++ = *src_ptr++; } - if (sleepTime > 256 * FTDF_UNIT_BACKOFF_PERIOD * 16) - { - /* We have exceeded the CCA retry time. Abort sleep and wait for Tx IRQ. */ - sleepTime = 0; + REG_SET_MASKED(FTDF, FTDF_LMAC_CONTROL_5_REG, + (REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_DEM_PTI) | + REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CN) | + REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CALCAP) | + REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_RF_GPIO_PINS) | + REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_HSI)), ftdf_sdb.phy_csma_ca_attr); + + FTDF->FTDF_TX_META_DATA_0_0_REG = ftdf_sdb.metadata_0; + + FTDF->FTDF_TX_META_DATA_1_0_REG = ftdf_sdb.metadata_1; + + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, + (REG_GETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET) | (1 << FTDF_TX_DATA_BUFFER))); +} + +static inline void ftdf_sdb_reset(void) +{ + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, CSMA_CA_RESUME_CLEAR, 1); +} + +static inline void ftdf_sdb_set_cca_retry_time(void) +{ + ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t bo_stat = REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, CSMA_CA_BO_STAT) * + FTDF_UNIT_BACKOFF_PERIOD; + ftdf_sdb.cca_retry_time = timestamp + bo_stat; +} + +void ftdf_sdb_fsm_reset(void) { + ftdf_sdb_reset(); + ftdf_sdb.state = FTDF_SDB_STATE_INIT; +} + +void ftdf_sdb_fsm_backoff_irq(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + return; } +#endif + switch (ftdf_sdb.state) { + case FTDF_SDB_STATE_RESUMING: + ftdf_sdb_reset(); + case FTDF_SDB_STATE_INIT: + case FTDF_SDB_STATE_BACKING_OFF: + ftdf_sdb_set_cca_retry_time(); + ftdf_sdb.state = FTDF_SDB_STATE_BACKING_OFF; + break; + default: + ASSERT_WARNING(0); + } +} - break; - } +void ftdf_sdb_fsm_sleep(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + return; + } +#endif + switch (ftdf_sdb.state) { + case FTDF_SDB_STATE_BACKING_OFF: + ftdf_sdb_save_state(); + ftdf_sdb.state = FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ; + break; + case FTDF_SDB_STATE_INIT: + break; + default: + ASSERT_WARNING(0); + } +} - case FTDF_SDB_STATE_RESUMING: - sleepTime = 0; - break; +void ftdf_sdb_fsm_abort_sleep(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + return; + } +#endif + switch (ftdf_sdb.state) { + case FTDF_SDB_STATE_BACKING_OFF: + ftdf_sdb.state = FTDF_SDB_STATE_INIT; + break; + case FTDF_SDB_STATE_INIT: + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + case FTDF_SDB_STATE_RESUMING: + break; + default: + ASSERT_WARNING(0); + } +} - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - sleepTime = ~((FTDF_USec) 0); - break; +void ftdf_sdb_fsm_wake_up_irq(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + return; + } +#endif + switch (ftdf_sdb.state) { + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + ftdf_sdb.state = FTDF_SDB_STATE_RESUMING; + break; + case FTDF_SDB_STATE_INIT: + break; + default: + ASSERT_WARNING(0); + } +} - default: - ASSERT_WARNING(0); - } +void ftdf_sdb_fsm_wake_up(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + return; + } +#endif + switch (ftdf_sdb.state) { + case FTDF_SDB_STATE_RESUMING: + ftdf_sdb_resume(); + break; + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + break; + case FTDF_SDB_STATE_INIT: + break; + default: + ASSERT_WARNING(0); + } +} - return sleepTime; +void ftdf_sdb_fsm_tx_irq(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + return; + } +#endif + switch (ftdf_sdb.state) { + case FTDF_SDB_STATE_RESUMING: + ftdf_sdb_reset(); + ftdf_sdb.state = FTDF_SDB_STATE_INIT; + break; + case FTDF_SDB_STATE_BACKING_OFF: + ftdf_sdb.state = FTDF_SDB_STATE_INIT; + break; + case FTDF_SDB_STATE_INIT: + break; + default: + ASSERT_WARNING(0); + } +} + +ftdf_usec_t ftdf_sdb_get_sleep_time(void) +{ + ftdf_usec_t sleep_time = ~((ftdf_usec_t) 0); +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + return sleep_time; + } +#endif + switch (ftdf_sdb.state) { + case FTDF_SDB_STATE_INIT: + if ((REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) || ftdf_req_current) { + sleep_time = 0; + } else { + sleep_time = ~((ftdf_usec_t) 0); + } + break; + case FTDF_SDB_STATE_BACKING_OFF: + { + ftdf_time_t currentTime = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + if (currentTime <= ftdf_sdb.cca_retry_time) { + sleep_time = (ftdf_sdb.cca_retry_time - currentTime) * 16; + } else { + sleep_time = (1 << 31) - (currentTime + ftdf_sdb.cca_retry_time) * 16; + } + if (sleep_time > 256 * FTDF_UNIT_BACKOFF_PERIOD * 16) { + /* We have exceeded the CCA retry time. Abort sleep and wait for Tx IRQ. */ + sleep_time = 0; + } + break; + } + case FTDF_SDB_STATE_RESUMING: + sleep_time = 0; + break; + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + sleep_time = ~((ftdf_usec_t) 0); + break; + default: + ASSERT_WARNING(0); + } + return sleep_time; } #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ -#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ - #if dg_configUSE_FTDF_DDPHY == 1 -void FTDF_ddphySet(uint16_t ccaReg) +void ftdf_ddphy_set(uint16_t cca_reg) { - FTDF_criticalVar(); - FTDF_enterCritical(); - /* We use the critical section here as protection for the global variable and the HW sleep - * state. */ - FTDF_ddphyCcaReg = ccaReg; - - /* Apply immediately if block is up. */ - if (REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0) - { - FTDF_DPHY->DDPHY_CCA_REG = FTDF_ddphyCcaReg; - } - - FTDF_exitCritical(); -} - -void FTDF_ddphyRestore(void) -{ - if (FTDF_ddphyCcaReg) - { + ftdf_critical_var(); + ftdf_enter_critical(); + /* We use the critical section here as protection for the global variable and the HW sleep + * state. */ + ftdf_ddphy_cca_reg = cca_reg; /* Apply immediately if block is up. */ - FTDF_criticalVar(); - FTDF_enterCritical(); - ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); - FTDF_DPHY->DDPHY_CCA_REG = FTDF_ddphyCcaReg; - FTDF_exitCritical(); - } + if (REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0) { + FTDF_DPHY->DDPHY_CCA_REG = ftdf_ddphy_cca_reg; + } + ftdf_exit_critical(); } -void FTDF_ddphySave(void) +void ftdf_ddphy_restore(void) { - /* Apply immediately if block is up. */ - FTDF_criticalVar(); - FTDF_enterCritical(); - ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); - FTDF_ddphyCcaReg = FTDF_DPHY->DDPHY_CCA_REG; - FTDF_exitCritical(); + if (ftdf_ddphy_cca_reg) { + /* Apply immediately if block is up. */ + ftdf_critical_var(); + ftdf_enter_critical(); + ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); + FTDF_DPHY->DDPHY_CCA_REG = ftdf_ddphy_cca_reg; + ftdf_exit_critical(); + } +} + +void ftdf_ddphy_save(void) +{ + /* Apply immediately if block is up. */ + ftdf_critical_var(); + ftdf_enter_critical(); + ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); + ftdf_ddphy_cca_reg = FTDF_DPHY->DDPHY_CCA_REG; + ftdf_exit_critical(); } #endif +#endif /* CONFIG_USE_FTDF */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c index 3c638dad3..f9444241d 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c @@ -37,699 +37,585 @@ #include #include "internal.h" -#include "regmap.h" +#ifdef CONFIG_USE_FTDF #ifndef FTDF_LITE -void FTDF_processDataRequest(FTDF_DataRequest *dataRequest) +void ftdf_process_data_request(ftdf_data_request_t *data_request) { #ifndef FTDF_NO_TSCH + if (ftdf_pib.tsch_enabled && ftdf_tsch_slot_link->request != data_request) { + ftdf_status_t status; - if (FTDF_pib.tschEnabled && - FTDF_tschSlotLink->request != dataRequest) - { - FTDF_Status status; + if ((data_request->dst_addr_mode == FTDF_SHORT_ADDRESS) && !data_request->indirect_tx) { + status = ftdf_schedule_tsch((ftdf_msg_buffer_t*) data_request); - if (dataRequest->dstAddrMode == FTDF_SHORT_ADDRESS && - !dataRequest->indirectTX) - { - status = FTDF_scheduleTsch((FTDF_MsgBuffer *) dataRequest); + if (status == FTDF_SUCCESS) { + return; + } + + } else { + status = FTDF_INVALID_PARAMETER; + } + + ftdf_send_data_confirm(data_request, status, 0, 0, 0, NULL); - if (status == FTDF_SUCCESS) - { return; - } } - else - { - status = FTDF_INVALID_PARAMETER; - } - - FTDF_sendDataConfirm(dataRequest, - status, - 0, - 0, - 0, - NULL); - - return; - } - #endif /* FTDF_NO_TSCH */ - int queue; - FTDF_AddressMode dstAddrMode = dataRequest->dstAddrMode; - FTDF_PANId dstPANId = dataRequest->dstPANId; - FTDF_Address dstAddr = dataRequest->dstAddr; + int queue; + ftdf_address_mode_t dst_addr_mode = data_request->dst_addr_mode; + ftdf_pan_id_t dst_pan_id = data_request->dst_pan_id; + ftdf_address_t dst_addr = data_request->dst_addr; - // Search for an existing indirect queue - for (queue = 0; queue < FTDF_NR_OF_REQ_BUFFERS; queue++) - { - if (dstAddrMode == FTDF_SHORT_ADDRESS) - { - if (FTDF_txPendingList[ queue ].addrMode == dstAddrMode && - FTDF_txPendingList[ queue ].addr.shortAddress == dstAddr.shortAddress) - { - break; - } - } - else if (dstAddrMode == FTDF_EXTENDED_ADDRESS) - { - if (FTDF_txPendingList[ queue ].addrMode == dstAddrMode && - FTDF_txPendingList[ queue ].addr.extAddress == dstAddr.extAddress) - { - break; - } - } - } + /* Search for an existing indirect queue */ + for (queue = 0; queue < FTDF_NR_OF_REQ_BUFFERS; queue++) { - if (dataRequest->indirectTX) - { - FTDF_Status status = FTDF_SUCCESS; + if (dst_addr_mode == FTDF_SHORT_ADDRESS) { - if (queue < FTDF_NR_OF_REQ_BUFFERS) - { - // Queue request in existing queue - status = FTDF_queueReqHead((FTDF_MsgBuffer *) dataRequest, &FTDF_txPendingList[ queue ].queue); + if ((ftdf_tx_pending_list[queue].addr_mode == dst_addr_mode) && + (ftdf_tx_pending_list[queue].addr.short_address == dst_addr.short_address)) { + break; + } - if (status == FTDF_SUCCESS) - { - FTDF_addTxPendingTimer((FTDF_MsgBuffer *) dataRequest, - queue, - FTDF_pib.transactionPersistenceTime * FTDF_BASE_SUPERFRAME_DURATION, - FTDF_sendTransactionExpired); - return; - } + } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { + + if ((ftdf_tx_pending_list[queue].addr_mode == dst_addr_mode) && + (ftdf_tx_pending_list[queue].addr.ext_address == dst_addr.ext_address)) { + break; + } + } } - if (dstAddrMode != FTDF_EXTENDED_ADDRESS && - dstAddrMode != FTDF_SHORT_ADDRESS) - { - status = FTDF_INVALID_PARAMETER; - } + if (data_request->indirect_tx) { + ftdf_status_t status = FTDF_SUCCESS; - if (status != FTDF_SUCCESS) - { - // Queueing of indirect transfer was not successful - FTDF_sendDataConfirm(dataRequest, - status, - 0, - 0, - 0, - NULL); + if (queue < FTDF_NR_OF_REQ_BUFFERS) { + /* Queue request in existing queue */ + status = ftdf_queue_req_head((ftdf_msg_buffer_t*) data_request, + &ftdf_tx_pending_list[queue].queue); - return; - } + if (status == FTDF_SUCCESS) { + ftdf_add_tx_pending_timer((ftdf_msg_buffer_t*) data_request, queue, + (ftdf_pib.transaction_persistence_time * + FTDF_BASE_SUPERFRAME_DURATION), + ftdf_send_transaction_expired); + return; + } + } + if ((dst_addr_mode != FTDF_EXTENDED_ADDRESS) && (dst_addr_mode != FTDF_SHORT_ADDRESS)) { + status = FTDF_INVALID_PARAMETER; + } + + if (status != FTDF_SUCCESS) { + /* Queueing of indirect transfer was not successful */ + ftdf_send_data_confirm(data_request, status, 0, 0, 0, NULL); + + return; + } #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - uint8_t entry, shortAddrIdx; - - if (dstAddrMode == FTDF_SHORT_ADDRESS) - { - if (FTDF_fpprGetFreeShortAddress(&entry, &shortAddrIdx) == FTDF_FALSE) - { - goto transaction_overflow; - } - } - else if (dstAddrMode == FTDF_EXTENDED_ADDRESS) - { - if (FTDF_fpprGetFreeExtAddress(&entry) == FTDF_FALSE) - { - goto transaction_overflow; - } - } - else - { - status = FTDF_INVALID_PARAMETER; - } - + uint8_t entry, short_addr_idx; + if (dst_addr_mode == FTDF_SHORT_ADDRESS) { + if (ftdf_fppr_get_free_short_address(&entry, &short_addr_idx) == FTDF_FALSE) { + goto transaction_overflow; + } + } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { + if (ftdf_fppr_get_free_ext_address(&entry) == FTDF_FALSE) { + goto transaction_overflow; + } + } else { + status = FTDF_INVALID_PARAMETER; + } #endif + /* Search for an empty indirect queue */ + for (queue = 0; queue < FTDF_NR_OF_REQ_BUFFERS; queue++) { + if (ftdf_tx_pending_list[queue].addr_mode == FTDF_NO_ADDRESS) { + ftdf_tx_pending_list[queue].addr_mode = dst_addr_mode; + ftdf_tx_pending_list[queue].pan_id = dst_pan_id; + ftdf_tx_pending_list[queue].addr = dst_addr; - // Search for an empty indirect queue - for (queue = 0; queue < FTDF_NR_OF_REQ_BUFFERS; queue++) - { - if (FTDF_txPendingList[ queue ].addrMode == FTDF_NO_ADDRESS) - { - FTDF_txPendingList[ queue ].addrMode = dstAddrMode; - FTDF_txPendingList[ queue ].PANId = dstPANId; - FTDF_txPendingList[ queue ].addr = dstAddr; + status = ftdf_queue_req_head((ftdf_msg_buffer_t*) data_request, + &ftdf_tx_pending_list[queue].queue); - status = FTDF_queueReqHead((FTDF_MsgBuffer *) dataRequest, - &FTDF_txPendingList[ queue ].queue); - - if (status == FTDF_SUCCESS) - { + if (status == FTDF_SUCCESS) { #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - - if (dstAddrMode == FTDF_SHORT_ADDRESS) - { - FTDF_fpprSetShortAddress(entry, shortAddrIdx, dstAddr.shortAddress); - FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_TRUE); - } - else if (dstAddrMode == FTDF_EXTENDED_ADDRESS) - { - FTDF_fpprSetExtAddress(entry, dstAddr.shortAddress); - FTDF_fpprSetExtAddressValid(entry, FTDF_TRUE); - } - else - { - ASSERT_WARNING(0); - } - + if (dst_addr_mode == FTDF_SHORT_ADDRESS) { + ftdf_fppr_set_short_address(entry, short_addr_idx, dst_addr.short_address); + ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_TRUE); + } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { + ftdf_fppr_set_ext_address(entry, dst_addr.short_address); + ftdf_fppr_set_ext_address_valid(entry, FTDF_TRUE); + } else { + ASSERT_WARNING(0); + } #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - FTDF_addTxPendingTimer((FTDF_MsgBuffer *) dataRequest, - queue, - FTDF_pib.transactionPersistenceTime * FTDF_BASE_SUPERFRAME_DURATION, - FTDF_sendTransactionExpired); - return; - } - else - { - break; - } - } - } + ftdf_add_tx_pending_timer((ftdf_msg_buffer_t*) data_request, + queue, + (ftdf_pib.transaction_persistence_time * + FTDF_BASE_SUPERFRAME_DURATION), + ftdf_send_transaction_expired); - // Did not find an existing or an empty queue + return; + } else { + break; + } + } + } + + /* Did not find an existing or an empty queue */ #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO -transaction_overflow: + transaction_overflow: #endif - FTDF_sendDataConfirm(dataRequest, FTDF_TRANSACTION_OVERFLOW, - 0, - 0, - 0, - NULL); + ftdf_send_data_confirm(data_request, FTDF_TRANSACTION_OVERFLOW, 0, 0, 0, NULL); - return; - } - - if (FTDF_reqCurrent == NULL) - { - FTDF_reqCurrent = (FTDF_MsgBuffer *) dataRequest; - } - else - { - if (FTDF_queueReqHead((FTDF_MsgBuffer *) dataRequest, &FTDF_reqQueue) == FTDF_TRANSACTION_OVERFLOW) - { - FTDF_sendDataConfirm(dataRequest, FTDF_TRANSACTION_OVERFLOW, - 0, - 0, - 0, - NULL); + return; } - return; - } + if (ftdf_req_current == NULL) { + ftdf_req_current = (ftdf_msg_buffer_t*) data_request; + } else { + if (ftdf_queue_req_head((ftdf_msg_buffer_t*) data_request, &ftdf_req_queue) == + FTDF_TRANSACTION_OVERFLOW) { - FTDF_FrameHeader *frameHeader = &FTDF_fh; - FTDF_SecurityHeader *securityHeader = &FTDF_sh; + ftdf_send_data_confirm(data_request, FTDF_TRANSACTION_OVERFLOW, 0, 0, 0, NULL); + } - frameHeader->frameType = dataRequest->sendMultiPurpose ? FTDF_MULTIPURPOSE_FRAME : FTDF_DATA_FRAME; + return; + } - FTDF_Boolean framePending; + ftdf_frame_header_t *frame_header = &ftdf_fh; + ftdf_security_header *security_header = &ftdf_sh; - if (queue < FTDF_NR_OF_REQ_BUFFERS) - { - framePending = FTDF_TRUE; - } - else - { - framePending = FTDF_FALSE; - } + frame_header->frame_type = data_request->send_multi_purpose ? FTDF_MULTIPURPOSE_FRAME : FTDF_DATA_FRAME; - frameHeader->options = - (dataRequest->securityLevel > 0 ? FTDF_OPT_SECURITY_ENABLED : 0) | - (dataRequest->ackTX ? FTDF_OPT_ACK_REQUESTED : 0) | - (framePending ? FTDF_OPT_FRAME_PENDING : 0) | - ((dataRequest->frameControlOptions & FTDF_PAN_ID_PRESENT) ? FTDF_OPT_PAN_ID_PRESENT : 0) | - ((dataRequest->frameControlOptions & FTDF_IES_INCLUDED) ? FTDF_OPT_IES_PRESENT : 0) | - ((dataRequest->frameControlOptions & FTDF_SEQ_NR_SUPPRESSED) ? FTDF_OPT_SEQ_NR_SUPPRESSED : 0); + ftdf_boolean_t frame_pending; - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - frameHeader->options |= FTDF_OPT_ENHANCED; - } + if (queue < FTDF_NR_OF_REQ_BUFFERS) { + frame_pending = FTDF_TRUE; + } else { + frame_pending = FTDF_FALSE; + } - frameHeader->srcAddrMode = dataRequest->srcAddrMode; - frameHeader->srcPANId = FTDF_pib.PANId; - frameHeader->dstAddrMode = dataRequest->dstAddrMode; - frameHeader->dstPANId = dataRequest->dstPANId; - frameHeader->dstAddr = dataRequest->dstAddr; + frame_header->options = + (data_request->security_level > 0 ? FTDF_OPT_SECURITY_ENABLED : 0) | + (data_request->ack_tx ? FTDF_OPT_ACK_REQUESTED : 0) | + (frame_pending ? FTDF_OPT_FRAME_PENDING : 0) | + ((data_request->frame_control_options & FTDF_PAN_ID_PRESENT) ? FTDF_OPT_PAN_ID_PRESENT : 0) | + ((data_request->frame_control_options & FTDF_IES_INCLUDED) ? FTDF_OPT_IES_PRESENT : 0) | + ((data_request->frame_control_options & FTDF_SEQ_NR_SUPPRESSED) ? FTDF_OPT_SEQ_NR_SUPPRESSED : 0); - securityHeader->securityLevel = dataRequest->securityLevel; - securityHeader->keyIdMode = dataRequest->keyIdMode; - securityHeader->keyIndex = dataRequest->keyIndex; - securityHeader->keySource = dataRequest->keySource; - securityHeader->frameCounter = FTDF_pib.frameCounter; - securityHeader->frameCounterMode = FTDF_pib.frameCounterMode; + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + frame_header->options |= FTDF_OPT_ENHANCED; + } + + frame_header->src_addr_mode = data_request->src_addr_mode; + frame_header->src_pan_id = ftdf_pib.pan_id; + frame_header->dst_addr_mode = data_request->dst_addr_mode; + frame_header->dst_pan_id = data_request->dst_pan_id; + frame_header->dst_addr = data_request->dst_addr; + + security_header->security_level = data_request->security_level; + security_header->key_id_mode = data_request->key_id_mode; + security_header->key_index = data_request->key_index; + security_header->key_source = data_request->key_source; + security_header->frame_counter = ftdf_pib.frame_counter; + security_header->frame_counter_mode = ftdf_pib.frame_counter_mode; #ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { - frameHeader->SN = FTDF_processTschSN((FTDF_MsgBuffer *)dataRequest, - FTDF_pib.DSN, - &dataRequest->requestSN); - } - else + if (ftdf_pib.tsch_enabled) { + frame_header->sn = ftdf_process_tsch_sn((ftdf_msg_buffer_t*)data_request, + ftdf_pib.dsn, + &data_request->requestSN); + } else #endif /* FTDF_NO_TSCH */ - { - frameHeader->SN = FTDF_pib.DSN; - } + { + frame_header->sn = ftdf_pib.dsn; + } - FTDF_Octet *txPtr = (FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO) + - (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); + ftdf_octet_t *tx_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + + (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - // Skip PHY header (= MAC length) - txPtr++; + /* Skip PHY header (= MAC length) */ + tx_ptr++; - FTDF_DataLength msduLength = dataRequest->msduLength; + ftdf_data_length_t msdu_length = data_request->msdu_length; - txPtr = FTDF_addFrameHeader(txPtr, - frameHeader, - msduLength); + tx_ptr = ftdf_add_frame_header(tx_ptr, frame_header, msdu_length); - txPtr = FTDF_addSecurityHeader(txPtr, - securityHeader); + tx_ptr = ftdf_add_security_header(tx_ptr, security_header); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - if (dataRequest->frameControlOptions & FTDF_IES_INCLUDED) - { - txPtr = FTDF_addIes(txPtr, - dataRequest->headerIEList, - dataRequest->payloadIEList, - dataRequest->msduLength); - } - + if (data_request->frame_control_options & FTDF_IES_INCLUDED) { + tx_ptr = ftdf_add_ies(tx_ptr, + data_request->header_ie_list, + data_request->payload_ie_list, + data_request->msdu_length); + } #endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - FTDF_Status status = FTDF_sendFrame(FTDF_pib.currentChannel, - frameHeader, - securityHeader, - txPtr, - dataRequest->msduLength, - dataRequest->msdu); + ftdf_status_t status = ftdf_send_frame(ftdf_pib.current_channel, + frame_header, + security_header, + tx_ptr, + data_request->msdu_length, + data_request->msdu); - if (status != FTDF_SUCCESS) - { - FTDF_sendDataConfirm(dataRequest, status, - 0, - 0, - 0, - NULL); + if (status != FTDF_SUCCESS) { + ftdf_send_data_confirm(data_request, status, 0, 0, 0, NULL); + ftdf_req_current = NULL; - FTDF_reqCurrent = NULL; + return; + } - return; - } + ftdf_nr_of_retries = 0; - FTDF_nrOfRetries = 0; - - if (frameHeader->SN == FTDF_pib.DSN) - { - FTDF_pib.DSN++; - } + if (frame_header->sn == ftdf_pib.dsn) { + ftdf_pib.dsn++; + } } -void FTDF_sendDataConfirm(FTDF_DataRequest *dataRequest, - FTDF_Status status, - FTDF_Time timestamp, - FTDF_SN DSN, - FTDF_NumOfBackoffs numOfBackoffs, - FTDF_IEList *ackPayload) +void ftdf_send_data_confirm(ftdf_data_request_t *data_request, + ftdf_status_t status, + ftdf_time_t timestamp, + ftdf_sn_t dsn, + ftdf_num_of_backoffs_t num_of_backoffs, + ftdf_ie_list_t *ack_payload) { - FTDF_REL_DATA_BUFFER(dataRequest->msdu); + FTDF_REL_DATA_BUFFER(data_request->msdu); - FTDF_DataConfirm *dataConfirm = (FTDF_DataConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_DataConfirm)); + ftdf_data_confirm_t *data_confirm = + (ftdf_data_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_data_confirm_t)); - dataConfirm->msgId = FTDF_DATA_CONFIRM; - dataConfirm->msduHandle = dataRequest->msduHandle; - dataConfirm->status = status; - dataConfirm->timestamp = timestamp; - dataConfirm->numOfBackoffs = numOfBackoffs; - dataConfirm->DSN = DSN; - dataConfirm->ackPayload = ackPayload; + data_confirm->msg_id = FTDF_DATA_CONFIRM; + data_confirm->msdu_handle = data_request->msdu_handle; + data_confirm->status = status; + data_confirm->timestamp = timestamp; + data_confirm->num_of_backoffs = num_of_backoffs; + data_confirm->dsn = dsn; + data_confirm->ack_payload = ack_payload; - if (FTDF_reqCurrent == (FTDF_MsgBuffer *)dataRequest) - { - FTDF_reqCurrent = NULL; - } + if (ftdf_req_current == (ftdf_msg_buffer_t*)data_request) { + ftdf_req_current = NULL; + } - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) dataRequest); - FTDF_RCV_MSG((FTDF_MsgBuffer *) dataConfirm); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) data_request); + FTDF_RCV_MSG((ftdf_msg_buffer_t*) data_confirm); #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - FTDF_fpFsmClearPending(); + ftdf_fp_fsm_clear_pending(); #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - FTDF_processNextRequest(); + ftdf_process_next_request(); } -void FTDF_sendDataIndication(FTDF_FrameHeader *frameHeader, - FTDF_SecurityHeader *securityHeader, - FTDF_IEList *payloadIEList, - FTDF_DataLength msduLength, - FTDF_Octet *msdu, - FTDF_LinkQuality mpduLinkQuality, - FTDF_Time timestamp) +void ftdf_send_data_indication(ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header, + ftdf_ie_list_t *payload_ie_list, + ftdf_data_length_t msdu_length, + ftdf_octet_t *msdu, + ftdf_link_quality_t mpdu_link_quality, + ftdf_time_t timestamp) { - FTDF_DataIndication *dataIndication = (FTDF_DataIndication *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_DataIndication)); - FTDF_Octet *msduBuf = FTDF_GET_DATA_BUFFER(msduLength); - FTDF_Octet *bufPtr = msduBuf; + ftdf_data_indication_t *data_indication = + (ftdf_data_indication_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_data_indication_t)); - int n; + ftdf_octet_t *msdu_buf = FTDF_GET_DATA_BUFFER(msdu_length); + ftdf_octet_t *buf_ptr = msdu_buf; - for (n = 0; n < msduLength; n++) - { - *msduBuf++ = *msdu++; - } + int n; - dataIndication->msgId = FTDF_DATA_INDICATION; - dataIndication->srcAddrMode = frameHeader->srcAddrMode; - dataIndication->srcPANId = frameHeader->srcPANId; - dataIndication->srcAddr = frameHeader->srcAddr; - dataIndication->dstAddrMode = frameHeader->dstAddrMode; - dataIndication->dstPANId = frameHeader->dstPANId; - dataIndication->dstAddr = frameHeader->dstAddr; - dataIndication->msduLength = msduLength; - dataIndication->msdu = bufPtr; - dataIndication->mpduLinkQuality = mpduLinkQuality; - dataIndication->DSN = frameHeader->SN; - dataIndication->timestamp = timestamp; - dataIndication->securityLevel = securityHeader->securityLevel; - dataIndication->keyIdMode = securityHeader->keyIdMode; - dataIndication->keyIndex = securityHeader->keyIndex; - dataIndication->payloadIEList = payloadIEList; - - if (dataIndication->keyIdMode == 0x2) - { - for (n = 0; n < 4; n++) - { - dataIndication->keySource[ n ] = securityHeader->keySource[ n ]; - } - } - else if (dataIndication->keyIdMode == 0x3) - { - for (n = 0; n < 8; n++) - { - dataIndication->keySource[ n ] = securityHeader->keySource[ n ]; - } - } - - FTDF_RCV_MSG((FTDF_MsgBuffer *) dataIndication); -} - -void FTDF_processPollRequest(FTDF_PollRequest *pollRequest) -{ - if (FTDF_reqCurrent == NULL) - { - FTDF_reqCurrent = (FTDF_MsgBuffer *) pollRequest; - } - else - { - if (FTDF_queueReqHead((FTDF_MsgBuffer *) pollRequest, &FTDF_reqQueue) == FTDF_TRANSACTION_OVERFLOW) - { - FTDF_sendPollConfirm(pollRequest, FTDF_TRANSACTION_OVERFLOW); + for (n = 0; n < msdu_length; n++) { + *msdu_buf++ = *msdu++; } - return; - } + data_indication->msg_id = FTDF_DATA_INDICATION; + data_indication->src_addr_mode = frame_header->src_addr_mode; + data_indication->src_pan_id = frame_header->src_pan_id; + data_indication->src_addr = frame_header->src_addr; + data_indication->dst_addr_mode = frame_header->dst_addr_mode; + data_indication->dst_pan_id = frame_header->dst_pan_id; + data_indication->dst_addr = frame_header->dst_addr; + data_indication->msdu_length = msdu_length; + data_indication->msdu = buf_ptr; + data_indication->mpdu_link_quality = mpdu_link_quality; + data_indication->dsn = frame_header->sn; + data_indication->timestamp = timestamp; + data_indication->security_level = security_header->security_level; + data_indication->key_id_mode = security_header->key_id_mode; + data_indication->key_index = security_header->key_index; + data_indication->payload_ie_list = payload_ie_list; - FTDF_FrameHeader *frameHeader = &FTDF_fh; - FTDF_SecurityHeader *securityHeader = &FTDF_sh; + if (data_indication->key_id_mode == 0x2) { + for (n = 0; n < 4; n++) { + data_indication->key_source[n] = security_header->key_source[n]; + } + } else if (data_indication->key_id_mode == 0x3) { + for (n = 0; n < 8; n++) { + data_indication->key_source[n] = security_header->key_source[n]; + } + } - frameHeader->frameType = FTDF_MAC_COMMAND_FRAME; - frameHeader->options = - (pollRequest->securityLevel > 0 ? FTDF_OPT_SECURITY_ENABLED : 0) | FTDF_OPT_ACK_REQUESTED; - - if (FTDF_pib.shortAddress < 0xfffe) - { - frameHeader->srcAddrMode = FTDF_SHORT_ADDRESS; - frameHeader->srcAddr.shortAddress = FTDF_pib.shortAddress; - } - else - { - frameHeader->srcAddrMode = FTDF_EXTENDED_ADDRESS; - frameHeader->srcAddr.extAddress = FTDF_pib.extAddress; - } - - frameHeader->srcPANId = FTDF_pib.PANId; - frameHeader->dstAddrMode = pollRequest->coordAddrMode; - frameHeader->dstPANId = pollRequest->coordPANId; - frameHeader->dstAddr = pollRequest->coordAddr; - - securityHeader->securityLevel = pollRequest->securityLevel; - securityHeader->keyIdMode = pollRequest->keyIdMode; - securityHeader->keyIndex = pollRequest->keyIndex; - securityHeader->keySource = pollRequest->keySource; - securityHeader->frameCounter = FTDF_pib.frameCounter; - securityHeader->frameCounterMode = FTDF_pib.frameCounterMode; - - FTDF_Octet *txPtr = (FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO) + - (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - - // Skip PHY header (= MAC length) - txPtr++; - - frameHeader->SN = FTDF_pib.DSN; - - txPtr = FTDF_addFrameHeader(txPtr, - frameHeader, - 1); - - txPtr = FTDF_addSecurityHeader(txPtr, - securityHeader); - - *txPtr++ = FTDF_COMMAND_DATA_REQUEST; - - FTDF_Status status = FTDF_sendFrame(FTDF_pib.currentChannel, - frameHeader, - securityHeader, - txPtr, - 0, - NULL); - - if (status != FTDF_SUCCESS) - { - FTDF_sendPollConfirm(pollRequest, status); - - return; - } - - FTDF_nrOfRetries = 0; - FTDF_pib.DSN++; + FTDF_RCV_MSG((ftdf_msg_buffer_t*) data_indication); } -void FTDF_sendPollConfirm(FTDF_PollRequest *pollRequest, FTDF_Status status) +void ftdf_process_poll_request(ftdf_poll_request_t *poll_request) { - FTDF_PollConfirm *pollConfirm = (FTDF_PollConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_PollConfirm)); + if (ftdf_req_current == NULL) { + ftdf_req_current = (ftdf_msg_buffer_t*) poll_request; + } else { + if (ftdf_queue_req_head((ftdf_msg_buffer_t*) poll_request, &ftdf_req_queue) == + FTDF_TRANSACTION_OVERFLOW) { + ftdf_send_poll_confirm(poll_request, FTDF_TRANSACTION_OVERFLOW); + } - pollConfirm->msgId = FTDF_POLL_CONFIRM; - pollConfirm->status = status; + return; + } - if (FTDF_reqCurrent == (FTDF_MsgBuffer *)pollRequest) - { - FTDF_reqCurrent = NULL; - } + ftdf_frame_header_t *frame_header = &ftdf_fh; + ftdf_security_header *security_header = &ftdf_sh; - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) pollRequest); - FTDF_RCV_MSG((FTDF_MsgBuffer *) pollConfirm); + frame_header->frame_type = FTDF_MAC_COMMAND_FRAME; + frame_header->options = + (poll_request->security_level > 0 ? FTDF_OPT_SECURITY_ENABLED : 0) | FTDF_OPT_ACK_REQUESTED; - FTDF_processNextRequest(); + if (ftdf_pib.short_address < 0xfffe) { + frame_header->src_addr_mode = FTDF_SHORT_ADDRESS; + frame_header->src_addr.short_address = ftdf_pib.short_address; + } else { + frame_header->src_addr_mode = FTDF_EXTENDED_ADDRESS; + frame_header->src_addr.ext_address = ftdf_pib.ext_address; + } + + frame_header->src_pan_id = ftdf_pib.pan_id; + frame_header->dst_addr_mode = poll_request->coord_addr_mode; + frame_header->dst_pan_id = poll_request->coord_pan_id; + frame_header->dst_addr = poll_request->coord_addr; + + security_header->security_level = poll_request->security_level; + security_header->key_id_mode = poll_request->key_id_mode; + security_header->key_index = poll_request->key_index; + security_header->key_source = poll_request->key_source; + security_header->frame_counter = ftdf_pib.frame_counter; + security_header->frame_counter_mode = ftdf_pib.frame_counter_mode; + + ftdf_octet_t *tx_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); + + /* Skip PHY header (= MAC length) */ + tx_ptr++; + + frame_header->sn = ftdf_pib.dsn; + + tx_ptr = ftdf_add_frame_header(tx_ptr, frame_header, 1); + + tx_ptr = ftdf_add_security_header(tx_ptr, security_header); + + *tx_ptr++ = FTDF_COMMAND_DATA_REQUEST; + + ftdf_status_t status = ftdf_send_frame(ftdf_pib.current_channel, + frame_header, + security_header, + tx_ptr, + 0, + NULL); + + if (status != FTDF_SUCCESS) { + ftdf_send_poll_confirm(poll_request, status); + return; + } + + ftdf_nr_of_retries = 0; + ftdf_pib.dsn++; } -void FTDF_processPurgeRequest(FTDF_PurgeRequest *purgeRequest) +void ftdf_send_poll_confirm(ftdf_poll_request_t *poll_request, ftdf_status_t status) { - FTDF_Handle msduHandle = purgeRequest->msduHandle; - FTDF_Status status = FTDF_INVALID_HANDLE; + ftdf_poll_confirm_t *poll_confirm = (ftdf_poll_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_poll_confirm_t)); - int n; + poll_confirm->msg_id = FTDF_POLL_CONFIRM; + poll_confirm->status = status; - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) - { - FTDF_MsgBuffer *request = FTDF_dequeueByHandle(msduHandle, &FTDF_txPendingList[ n ].queue); + if (ftdf_req_current == (ftdf_msg_buffer_t*)poll_request) { + ftdf_req_current = NULL; + } - if (request) - { - FTDF_DataRequest *dataRequest = (FTDF_DataRequest *) request; + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) poll_request); + FTDF_RCV_MSG((ftdf_msg_buffer_t*) poll_confirm); - if (dataRequest->indirectTX == FTDF_TRUE) - { - FTDF_removeTxPendingTimer(request); + ftdf_process_next_request(); +} + +void ftdf_process_purge_request(ftdf_purge_request_t *purge_request) +{ + ftdf_handle_t msdu_handle = purge_request->msdu_handle; + ftdf_status_t status = FTDF_INVALID_HANDLE; + + int n; + + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { + ftdf_msg_buffer_t *request = + ftdf_dequeue_by_handle(msdu_handle, &ftdf_tx_pending_list[n].queue); + + if (request) { + ftdf_data_request_t *data_request = (ftdf_data_request_t*) request; + + if (data_request->indirect_tx == FTDF_TRUE) { + ftdf_remove_tx_pending_timer(request); #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - - if (FTDF_txPendingList[ n ].addrMode == FTDF_SHORT_ADDRESS) - { - uint8_t entry, shortAddrIdx; - FTDF_Boolean found = FTDF_fpprLookupShortAddress( - FTDF_txPendingList[ n ].addr.shortAddress, &entry, - &shortAddrIdx); - ASSERT_WARNING(found); - FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); - } - else if (FTDF_txPendingList[ n ].addrMode == FTDF_EXTENDED_ADDRESS) - { - uint8_t entry; - FTDF_Boolean found = FTDF_fpprLookupExtAddress( - FTDF_txPendingList[ n ].addr.extAddress, &entry); - ASSERT_WARNING(found); - FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); - } - else - { - ASSERT_WARNING(0); - } - + if (ftdf_tx_pending_list[n].addr_mode == FTDF_SHORT_ADDRESS) { + uint8_t entry, shortAddrIdx; + ftdf_boolean_t found = ftdf_fppr_lookup_short_address( + ftdf_tx_pending_list[n].addr.short_address, &entry, + &shortAddrIdx); + ASSERT_WARNING(found); + ftdf_fppr_set_short_address_valid(entry, shortAddrIdx, FTDF_FALSE); + } else if (ftdf_tx_pending_list[n].addr_mode == FTDF_EXTENDED_ADDRESS) { + uint8_t entry; + ftdf_boolean_t found = ftdf_fppr_lookup_ext_address( + ftdf_tx_pending_list[n].addr.ext_address, &entry); + ASSERT_WARNING(found); + ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); + } else { + ASSERT_WARNING(0); + } #endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ + if (ftdf_is_queue_empty(&ftdf_tx_pending_list[n].queue)) { + ftdf_tx_pending_list[n].addr_mode = FTDF_NO_ADDRESS; + } + } - if (FTDF_isQueueEmpty(&FTDF_txPendingList[ n ].queue)) - { - FTDF_txPendingList[ n ].addrMode = FTDF_NO_ADDRESS; + FTDF_REL_DATA_BUFFER(data_request->msdu); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) data_request); + + status = FTDF_SUCCESS; + + break; } - } - - FTDF_REL_DATA_BUFFER(dataRequest->msdu); - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) dataRequest); - - status = FTDF_SUCCESS; - - break; } - } - FTDF_PurgeConfirm *purgeConfirm = (FTDF_PurgeConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_PurgeConfirm)); + ftdf_purge_confirm_t *purge_confirm = + (ftdf_purge_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_purge_confirm_t)); - purgeConfirm->msgId = FTDF_PURGE_CONFIRM; - purgeConfirm->msduHandle = msduHandle; - purgeConfirm->status = status; + purge_confirm->msg_id = FTDF_PURGE_CONFIRM; + purge_confirm->msdu_handle = msdu_handle; + purge_confirm->status = status; - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) purgeRequest); - FTDF_RCV_MSG((FTDF_MsgBuffer *) purgeConfirm); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) purge_request); + FTDF_RCV_MSG((ftdf_msg_buffer_t*) purge_confirm); } #endif /* !FTDF_LITE */ #ifdef FTDF_PHY_API -FTDF_Status FTDF_sendFrameSimple(FTDF_DataLength frameLength, - FTDF_Octet *frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean csmaSuppress) +ftdf_status_t ftdf_send_frame_simple(ftdf_data_length_t frame_length, + ftdf_octet_t *frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t csma_suppress) { - FTDF_Octet *fp = frame; + ftdf_octet_t *fp = frame; - if (frameLength > 127 || - FTDF_transparentMode != FTDF_TRUE) - { - return FTDF_INVALID_PARAMETER; - } + if ((frame_length > 127) || (ftdf_transparent_mode != FTDF_TRUE)) { + return FTDF_INVALID_PARAMETER; + } - FTDF_Octet *txPtr = (FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO) + - (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); + ftdf_octet_t *tx_ptr = + (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - /* This data copy could/should be optimized using DMA */ - *txPtr++ = frameLength; + /* This data copy could/should be optimized using DMA */ + *tx_ptr++ = frame_length; - int n; + int n; - for (n = 0; n < frameLength; n++) - { - *txPtr++ = *fp++; - } + for (n = 0; n < frame_length; n++) { + *tx_ptr++ = *fp++; + } - FTDF_criticalVar(); - FTDF_enterCritical(); - FTDF_nrOfRetries = 0; - FTDF_exitCritical(); - FTDF_sendTransparentFrame(frameLength, - frame, - channel, - pti, - csmaSuppress); + ftdf_critical_var(); + ftdf_enter_critical(); + ftdf_nr_of_retries = 0; + ftdf_exit_critical(); + ftdf_send_transparent_frame(frame_length, + frame, + channel, + pti, + csma_suppress); - return FTDF_SUCCESS; + return FTDF_SUCCESS; } #else /* !FTDF_PHY_API */ -void FTDF_processTransparentRequest(FTDF_TransparentRequest *transparentRequest) +void ftdf_process_transparent_request(ftdf_transparent_request_t *transparent_request) { - FTDF_DataLength frameLength = transparentRequest->frameLength; + ftdf_data_length_t frame_length = transparent_request->frame_length; - if (frameLength > 127 || - FTDF_transparentMode != FTDF_TRUE) - { - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparentRequest->handle, - FTDF_INVALID_PARAMETER); + if ((frame_length > 127) || (ftdf_transparent_mode != FTDF_TRUE)) { + FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, + FTDF_INVALID_PARAMETER); - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) transparentRequest); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) transparent_request); - return; - } - - if (FTDF_reqCurrent == NULL) - { - FTDF_reqCurrent = (FTDF_MsgBuffer *) transparentRequest; - } - else - { -#ifndef FTDF_LITE - - if (FTDF_queueReqHead((FTDF_MsgBuffer *) transparentRequest, &FTDF_reqQueue) == FTDF_TRANSACTION_OVERFLOW) - { -#endif /* !FTDF_LITE */ - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparentRequest->handle, - FTDF_TRANSPARENT_OVERFLOW); - - FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) transparentRequest); -#ifndef FTDF_LITE + return; } + if (ftdf_req_current == NULL) { + ftdf_req_current = (ftdf_msg_buffer_t*) transparent_request; + } else { +#ifndef FTDF_LITE + if (ftdf_queue_req_head((ftdf_msg_buffer_t*) transparent_request, &ftdf_req_queue) == + FTDF_TRANSACTION_OVERFLOW) { #endif /* !FTDF_LITE */ - return; - } + FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, + FTDF_TRANSPARENT_OVERFLOW); - FTDF_Octet *txPtr = (FTDF_Octet *) FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO) + - (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); + FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) transparent_request); +#ifndef FTDF_LITE + } +#endif /* !FTDF_LITE */ + return; + } - *txPtr++ = frameLength; + ftdf_octet_t *tx_ptr = + (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - FTDF_Octet *frame = transparentRequest->frame; + *tx_ptr++ = frame_length; - int n; + ftdf_octet_t *frame = transparent_request->frame; - for (n = 0; n < frameLength; n++) - { - *txPtr++ = *frame++; - } + int n; - FTDF_sendTransparentFrame(frameLength, - transparentRequest->frame, - transparentRequest->channel, - transparentRequest->pti, - transparentRequest->cmsaSuppress); - FTDF_nrOfRetries = 0; + for (n = 0; n < frame_length; n++) { + *tx_ptr++ = *frame++; + } + + ftdf_send_transparent_frame(frame_length, + transparent_request->frame, + transparent_request->channel, + transparent_request->pti, + transparent_request->cmsa_suppress); + ftdf_nr_of_retries = 0; } - -void FTDF_sendFrameTransparent(FTDF_DataLength frameLength, - FTDF_Octet *frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean cmsaSuppress, - void *handle) +void ftdf_send_frame_transparent(ftdf_data_length_t frame_length, + ftdf_octet_t *frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t cmsa_suppress, + void *handle) { - FTDF_TransparentRequest *transparentRequest = - (FTDF_TransparentRequest *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_TransparentRequest)); + ftdf_transparent_request_t *transparent_request = + (ftdf_transparent_request_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_transparent_request_t)); - transparentRequest->msgId = FTDF_TRANSPARENT_REQUEST; - transparentRequest->frameLength = frameLength; - transparentRequest->frame = frame; - transparentRequest->channel = channel; - transparentRequest->pti = pti; - transparentRequest->cmsaSuppress = cmsaSuppress; - transparentRequest->handle = handle; + transparent_request->msg_id = FTDF_TRANSPARENT_REQUEST; + transparent_request->frame_length = frame_length; + transparent_request->frame = frame; + transparent_request->channel = channel; + transparent_request->pti = pti; + transparent_request->cmsa_suppress = cmsa_suppress; + transparent_request->handle = handle; - FTDF_processTransparentRequest(transparentRequest); + ftdf_process_transparent_request(transparent_request); } #endif /* FTDF_PHY_API */ +#endif /* CONFIG_USE_FTDF */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h index b8d0c1224..cc4831aa4 100755 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h @@ -9,7 +9,7 @@ #define FTDF_BRANCH_VERSION 0 #define FTDF_LOAD_VERSION 32 -const char* FTDF_getUmacRelName( void ); -const char* FTDF_getUmacBuildTime( void ); +const char *ftdf_get_umac_rel_name( void ); +const char *ftdf_get_umac_build_time( void ); #endif /* FTDFINFO_H_ */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h index a9e5d5276..028637857 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h @@ -67,6 +67,16 @@ #define FTDF_MSK_SYMBOL_TMR_CE 0x00000008 #define FTDF_MSK_TX_CE 0x00000010 +#define FTDF_TX_FLAG_CLEAR_M_0_REG_INTV 0x20 +#define FTDF_TX_FLAG_CLEAR_E_0_REG_INTV 0x20 +#define FTDF_TX_PRIORITY_0_REG_INTV 0x20 +#define FTDF_RX_META_1_0_REG_INTV 0x10 +#define FTDF_TX_FLAG_S_0_REG_INTV 0x20 +#define FTDF_TX_RETURN_STATUS_1_0_REG_INTV 0x10 +#define FTDF_TX_META_DATA_0_0_REG_INTV 0x10 +#define FTDF_TX_RETURN_STATUS_1_0_REG_INTV 0x10 +#define FTDF_TX_META_DATA_1_0_REG_INTV 0x10 + // The maximum time in symbols that is takes to process request. After succesful // processing a request the TX buffer is fully initialized and ready to be sent. #define FTDF_TSCH_MAX_PROCESS_REQUEST_TIME 35 @@ -75,280 +85,237 @@ // TX or RX needs to be done #define FTDF_TSCH_MAX_SCHEDULE_TIME 30 -#define FTDF_GET_FIELD_ADDR( fieldName ) ( (volatile uint32_t*) ( IND_F_FTDF_ ## fieldName ) ) -#define FTDF_GET_FIELD_ADDR_INDEXED( fieldName, index ) ( (volatile uint32_t*) ( IND_F_FTDF_ ## fieldName + \ - (intptr_t) index * \ - FTDF_ ## fieldName ## _INTVL ) ) -#define FTDF_GET_REG_ADDR( regName ) ( (volatile uint32_t*) ( IND_R_FTDF_ ## regName ) ) -#define FTDF_GET_REG_ADDR_INDEXED( regName, index ) ( (volatile uint32_t*) ( IND_R_FTDF_ ## regName + \ - (intptr_t) index * \ - FTDF_ ## regName ## _INTVL ) ) -#define FTDF_GET_FIELD( fieldName ) ( ( ( *(volatile uint32_t*) ( IND_F_FTDF_ ## fieldName ) ) & \ - MSK_F_FTDF_ ## fieldName ) >> OFF_F_FTDF_ ## fieldName ) -#define FTDF_GET_FIELD_INDEXED( fieldName, \ - index ) ( ( ( *FTDF_GET_FIELD_ADDR_INDEXED( fieldName, \ - index ) ) \ - & MSK_F_FTDF_ ## fieldName ) >> OFF_F_FTDF_ ## fieldName ) +#define ftdf_process_request ftdf_snd_msg -#define FTDF_SET_FIELD( fieldName, value ) do { \ - uint32_t tmp = *FTDF_GET_FIELD_ADDR( fieldName ) & ~MSK_F_FTDF_ ## fieldName; \ - *FTDF_GET_FIELD_ADDR( fieldName ) = tmp | \ - ( ( ( value ) << OFF_F_FTDF_ ## fieldName ) & MSK_F_FTDF_ ## fieldName ); \ -} \ - while ( 0 ) +typedef struct { + ftdf_ext_address_t ext_address; + ftdf_period_t ack_wait_duration; +#ifndef FTDF_LITE + ftdf_boolean_t associated_pan_coord; + ftdf_boolean_t association_permit; + ftdf_boolean_t auto_request; + ftdf_boolean_t batt_life_ext; + ftdf_num_of_backoffs_t batt_life_ext_periods; + ftdf_octet_t beacon_payload[FTDF_MAX_BEACON_PAYLOAD_LENGTH]; + ftdf_size_t beacon_payload_length; + ftdf_order_t beacon_order; + ftdf_time_t beacon_tx_time; + ftdf_sn_t bsn; + ftdf_ext_address_t coord_ext_address; + ftdf_short_address_t coord_short_address; + ftdf_sn_t dsn; + ftdf_boolean_t gts_permit; +#endif /* !FTDF_LITE */ + ftdf_be_exponent_t max_be; + ftdf_size_t max_csma_backoffs; + ftdf_period_t max_frame_total_wait_time; + ftdf_size_t max_frame_retries; + ftdf_be_exponent_t min_be; +#ifndef FTDF_LITE + ftdf_period_t lifs_period; + ftdf_period_t sifs_period; +#endif /* !FTDF_LITE */ + ftdf_pan_id_t pan_id; +#ifndef FTDF_LITE + ftdf_boolean_t promiscuous_mode; /* Not supported. Use transparent mode instead */ + ftdf_size_t response_wait_time; +#endif /* !FTDF_LITE */ + ftdf_boolean_t rx_on_when_idle; +#ifndef FTDF_LITE + ftdf_boolean_t security_enabled; +#endif /* !FTDF_LITE */ + ftdf_short_address_t short_address; +#ifndef FTDF_LITE + ftdf_size_t superframe_order; + ftdf_period_t sync_symbol_offset; + ftdf_boolean_t timestamp_supported; + ftdf_period_t transaction_persistence_time; + ftdf_period_t enh_ack_wait_duration; + ftdf_boolean_t implicit_broadcast; + ftdf_simple_address_t simple_address; + ftdf_period_t disconnect_time; + ftdf_priority_t join_priority; + ftdf_asn_t asn; + ftdf_boolean_t no_hl_buffers; + ftdf_slotframe_table_t slotframe_table; + FTDF_LinkTable link_table; + ftdf_timeslot_template_t timeslot_template; + ftdf_hopping_sequence_id_t hopping_sequence_id; + ftdf_channel_page_t channel_page; + ftdf_channel_number_t number_of_channels; + ftdf_bitmap32_t phy_configuration; + ftdf_bitmap8_t extended_bitmap; + ftdf_length_t hopping_sequence_length; + ftdf_channel_number_t hopping_sequence_list[FTDF_MAX_HOPPING_SEQUENCE_LENGTH]; + ftdf_length_t current_hop; + ftdf_period_t dwell_time; + ftdf_period_t csl_period; + ftdf_period_t csl_max_period; + ftdf_bitmap32_t csl_channel_mask; + ftdf_period_t csl_frame_pending_wait; + ftdf_boolean_t low_energy_superframe_supported; + ftdf_boolean_t low_energy_superframe_sync_interval; +#endif /* !FTDF_LITE */ + ftdf_performance_metrics_t performance_metrics; +#ifndef FTDF_LITE + ftdf_boolean_t use_enhanced_becaon; + ftdf_ie_list_t eb_ie_list; + ftdf_boolean_t eb_filtering_enabled; + ftdf_sn_t eb_sn; + ftdf_auto_sa_t eb_auto_sa; + ftdf_ie_list_t e_ack_ie_list; + ftdf_boolean_t tsch_enabled; + ftdf_boolean_t le_enabled; +#endif /* !FTDF_LITE */ + ftdf_channel_number_t current_channel; + ftdf_tx_power_tolerance_t tx_power_tolerance; + ftdf_dbm tx_power; + ftdf_cca_mode_t cca_mode; +#ifndef FTDF_LITE + ftdf_channel_page_t current_page; + ftdf_period_t max_frame_duration; + ftdf_period_t shr_duration; + ftdf_key_table_t key_table; + ftdf_device_table_t device_table; + ftdf_security_level_table_t security_level_table; + ftdf_frame_counter_t frame_counter; + ftdf_security_level_t mt_data_security_level; + ftdf_key_id_mode_t mt_data_key_id_mode; + ftdf_octet_t mt_data_key_source[8]; + ftdf_key_index_t mt_data_key_index; + ftdf_octet_t default_key_source[8]; + ftdf_ext_address_t pan_coord_ext_address; + ftdf_short_address_t pan_coord_short_address; + ftdf_frame_counter_mode_t frame_counter_mode; + ftdf_period_t csl_sync_tx_margin; + ftdf_period_t csl_max_age_remote_info; +#endif /* !FTDF_LITE */ + ftdf_traffic_counters_t traffic_counters; +#ifndef FTDF_LITE + ftdf_boolean_t le_capable; + ftdf_boolean_t ll_capable; + ftdf_boolean_t dsme_capable; + ftdf_boolean_t rfid_capable; + ftdf_boolean_t amca_capable; +#endif /* !FTDF_LITE */ + ftdf_boolean_t metrics_capable; +#ifndef FTDF_LITE + ftdf_boolean_t ranging_supported; +#endif /* !FTDF_LITE */ + ftdf_boolean_t keep_phy_enabled; + ftdf_boolean_t metrics_enabled; +#ifndef FTDF_LITE + ftdf_boolean_t beacon_auto_respond; + ftdf_boolean_t tsch_capable; + ftdf_period_t ts_sync_correct_threshold; +#endif /* !FTDF_LITE */ + ftdf_nr_backoff_periods_t bo_irq_threshold; + ftdf_pti_config_t pti_config; + ftdf_link_quality_mode_t link_quality_mode; +} ftdf_pib_t; - -#define FTDF_SET_FIELD_INDEXED( fieldName, value, index ) do { \ - uint32_t tmp = *FTDF_GET_FIELD_ADDR_INDEXED( fieldName, index ) & ~MSK_F_FTDF_ ## fieldName; \ - *FTDF_GET_FIELD_ADDR_INDEXED( fieldName, index ) = tmp | \ - ( ( ( value ) << OFF_F_FTDF_ ## fieldName ) & MSK_F_FTDF_ ## fieldName ); \ -} \ - while ( 0 ) - -#define FTDF_processRequest FTDF_sndMsg - -struct FTDF_Pib -{ - FTDF_ExtAddress extAddress; - FTDF_Period ackWaitDuration; -#ifndef FTDF_LITE - FTDF_Boolean associatedPANCoord; - FTDF_Boolean associationPermit; - FTDF_Boolean autoRequest; - FTDF_Boolean battLifeExt; - FTDF_NumOfBackoffs battLifeExtPeriods; - FTDF_Octet beaconPayload[ FTDF_MAX_BEACON_PAYLOAD_LENGTH ]; - FTDF_Size beaconPayloadLength; - FTDF_Order beaconOrder; - FTDF_Time beaconTxTime; - FTDF_SN BSN; - FTDF_ExtAddress coordExtAddress; - FTDF_ShortAddress coordShortAddress; - FTDF_SN DSN; - FTDF_Boolean GTSPermit; -#endif /* !FTDF_LITE */ - FTDF_BEExponent maxBE; - FTDF_Size maxCSMABackoffs; - FTDF_Period maxFrameTotalWaitTime; - FTDF_Size maxFrameRetries; - FTDF_BEExponent minBE; -#ifndef FTDF_LITE - FTDF_Period LIFSPeriod; - FTDF_Period SIFSPeriod; -#endif /* !FTDF_LITE */ - FTDF_PANId PANId; -#ifndef FTDF_LITE - FTDF_Boolean promiscuousMode; /* Not supported. Use transparent mode instead */ - FTDF_Size responseWaitTime; -#endif /* !FTDF_LITE */ - FTDF_Boolean rxOnWhenIdle; -#ifndef FTDF_LITE - FTDF_Boolean securityEnabled; -#endif /* !FTDF_LITE */ - FTDF_ShortAddress shortAddress; -#ifndef FTDF_LITE - FTDF_Size superframeOrder; - FTDF_Period syncSymbolOffset; - FTDF_Boolean timestampSupported; - FTDF_Period transactionPersistenceTime; - FTDF_Period enhAckWaitDuration; - FTDF_Boolean implicitBroadcast; - FTDF_SimpleAddress simpleAddress; - FTDF_Period disconnectTime; - FTDF_Priority joinPriority; - FTDF_ASN ASN; - FTDF_Boolean noHLBuffers; - FTDF_SlotframeTable slotframeTable; - FTDF_LinkTable linkTable; - FTDF_TimeslotTemplate timeslotTemplate; - FTDF_HoppingSequenceId HoppingSequenceId; - FTDF_ChannelPage channelPage; - FTDF_ChannelNumber numberOfChannels; - FTDF_Bitmap32 phyConfiguration; - FTDF_Bitmap8 extendedBitmap; - FTDF_Length hoppingSequenceLength; - FTDF_ChannelNumber hoppingSequenceList[ FTDF_MAX_HOPPING_SEQUENCE_LENGTH ]; - FTDF_Length currentHop; - FTDF_Period dwellTime; - FTDF_Period CSLPeriod; - FTDF_Period CSLMaxPeriod; - FTDF_Bitmap32 CSLChannelMask; - FTDF_Period CSLFramePendingWaitT; - FTDF_Boolean lowEnergySuperframeSupported; - FTDF_Boolean lowEnergySuperframeSyncInterval; -#endif /* !FTDF_LITE */ - FTDF_PerformanceMetrics performanceMetrics; -#ifndef FTDF_LITE - FTDF_Boolean useEnhancedBecaon; - FTDF_IEList EBIEList; - FTDF_Boolean EBFilteringEnabled; - FTDF_SN EBSN; - FTDF_AutoSA EBAutoSA; - FTDF_IEList EAckIEList; - FTDF_Boolean tschEnabled; - FTDF_Boolean leEnabled; -#endif /* !FTDF_LITE */ - FTDF_ChannelNumber currentChannel; - FTDF_TXPowerTolerance TXPowerTolerance; - FTDF_DBm TXPower; - FTDF_CCAMode CCAMode; -#ifndef FTDF_LITE - FTDF_ChannelPage currentPage; - FTDF_Period maxFrameDuration; - FTDF_Period SHRDuration; - FTDF_KeyTable keyTable; - FTDF_DeviceTable deviceTable; - FTDF_SecurityLevelTable securityLevelTable; - FTDF_FrameCounter frameCounter; - FTDF_SecurityLevel mtDataSecurityLevel; - FTDF_KeyIdMode mtDataKeyIdMode; - FTDF_Octet mtDataKeySource[ 8 ]; - FTDF_KeyIndex mtDataKeyIndex; - FTDF_Octet defaultKeySource[ 8 ]; - FTDF_ExtAddress PANCoordExtAddress; - FTDF_ShortAddress PANCoordShortAddress; - FTDF_FrameCounterMode frameCounterMode; - FTDF_Period CSLSyncTxMargin; - FTDF_Period CSLMaxAgeRemoteInfo; -#endif /* !FTDF_LITE */ - FTDF_TrafficCounters trafficCounters; -#ifndef FTDF_LITE - FTDF_Boolean LECapable; - FTDF_Boolean LLCapable; - FTDF_Boolean DSMECapable; - FTDF_Boolean RFIDCapable; - FTDF_Boolean AMCACapable; -#endif /* !FTDF_LITE */ - FTDF_Boolean metricsCapable; -#ifndef FTDF_LITE - FTDF_Boolean rangingSupported; -#endif /* !FTDF_LITE */ - FTDF_Boolean keepPhyEnabled; - FTDF_Boolean metricsEnabled; -#ifndef FTDF_LITE - FTDF_Boolean beaconAutoRespond; - FTDF_Boolean tschCapable; - FTDF_Period tsSyncCorrectThreshold; -#endif /* !FTDF_LITE */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - FTDF_NrBackoffPeriods boIrqThreshold; - FTDF_PtiConfig ptiConfig; -#endif -}; - -typedef uint8_t FTDF_FrameVersion; +typedef uint8_t ftdf_frame_version_t; #define FTDF_FRAME_VERSION_2003 0 #define FTDF_FRAME_VERSION_2011 1 #define FTDF_FRAME_VERSION_E 2 #define FTDF_FRAME_VERSION_NOT_SUPPORTED 3 -typedef struct -{ - FTDF_FrameType frameType; - FTDF_FrameVersion frameVersion; - FTDF_Bitmap8 options; - FTDF_SN SN; - FTDF_AddressMode srcAddrMode; - FTDF_PANId srcPANId; - FTDF_Address srcAddr; - FTDF_AddressMode dstAddrMode; - FTDF_PANId dstPANId; - FTDF_Address dstAddr; - FTDF_CommandFrameId commandFrameId; -} FTDF_FrameHeader; +typedef struct { + ftdf_frame_type_t frame_type; + ftdf_frame_version_t frame_version; + ftdf_bitmap8_t options; + ftdf_sn_t sn; + ftdf_address_mode_t src_addr_mode; + ftdf_pan_id_t src_pan_id; + ftdf_address_t src_addr; + ftdf_address_mode_t dst_addr_mode; + ftdf_pan_id_t dst_pan_id; + ftdf_address_t dst_addr; + ftdf_command_frame_id_t command_frame_id; +} ftdf_frame_header_t; -typedef struct -{ - FTDF_SecurityLevel securityLevel; - FTDF_KeyIdMode keyIdMode; - FTDF_KeyIndex keyIndex; - FTDF_FrameCounterMode frameCounterMode; - FTDF_Octet* keySource; - FTDF_FrameCounter frameCounter; -} FTDF_SecurityHeader; +typedef struct { + ftdf_security_level_t security_level; + ftdf_key_id_mode_t key_id_mode; + ftdf_key_index_t key_index; + ftdf_frame_counter_mode_t frame_counter_mode; + ftdf_octet_t *key_source; + ftdf_frame_counter_t frame_counter; +} ftdf_security_header; -typedef struct -{ - FTDF_Boolean fastA; - FTDF_Boolean dataR; -} FTDF_AssocAdmin; +typedef struct { + ftdf_boolean_t fast_a; + ftdf_boolean_t data_r; +} ftdf_assoc_admin_t; -typedef uint8_t FTDF_SNSel; +typedef uint8_t ftdf_sn_sel; #define FTDF_SN_SEL_DSN 0 #define FTDF_SN_SEL_BSN 1 #define FTDF_SN_SEL_EBSN 2 -typedef struct -{ - FTDF_AddressMode addrMode; - FTDF_Address addr; - FTDF_Time timestamp; - FTDF_Boolean dsnValid; - FTDF_SN dsn; - FTDF_Boolean bsnValid; - FTDF_SN bsn; - FTDF_Boolean ebsnValid; - FTDF_SN ebsn; -} FTDF_RxAddressAdmin; +typedef struct { + ftdf_address_mode_t addr_mode; + ftdf_address_t addr; + ftdf_time_t timestamp; + ftdf_boolean_t dsn_valid; + ftdf_sn_t dsn; + ftdf_boolean_t bsn_valid; + ftdf_sn_t bsn; + ftdf_boolean_t ebsn_valid; + ftdf_sn_t eb_sn; +} ftdf_rx_address_admin_t; -struct FTDF_Buffer_; +struct ftdf_buffer_; -typedef struct -{ - struct FTDF_Buffer_* next; - struct FTDF_Buffer_* prev; -} FTDF_BufferHeader; +typedef struct { + struct ftdf_buffer_ *next; + struct ftdf_buffer_ *prev; +} ftdf_buffer_header_t; -typedef struct FTDF_Buffer_ -{ - FTDF_BufferHeader header; - FTDF_MsgBuffer* request; -} FTDF_Buffer; +typedef struct ftdf_buffer_ { + ftdf_buffer_header_t header; + ftdf_msg_buffer_t *request; +} ftdf_buffer_t; -typedef struct -{ - FTDF_BufferHeader head; - FTDF_BufferHeader tail; -} FTDF_Queue; +typedef struct { + ftdf_buffer_header_t head; + ftdf_buffer_header_t tail; +} ftdf_queue_t; -typedef struct -{ - FTDF_Address addr; - FTDF_AddressMode addrMode; - FTDF_PANId PANId; - FTDF_Queue queue; -} FTDF_Pending; +typedef struct { + ftdf_address_t addr; + ftdf_address_mode_t addr_mode; + ftdf_pan_id_t pan_id; + ftdf_queue_t queue; +} ftdf_pending_t; -typedef struct _FTDF_PendingTL_ -{ - struct _FTDF_PendingTL_* next; - FTDF_Boolean free; - FTDF_MsgBuffer* request; - FTDF_Time delta; - uint8_t pendListNr; - void ( * func )( struct _FTDF_PendingTL_* ); -} FTDF_PendingTL; +typedef struct _ftdf_pending_tl_ { + struct _ftdf_pending_tl_ *next; + ftdf_boolean_t free; + ftdf_msg_buffer_t *request; + ftdf_time_t delta; + uint8_t pend_list_nr; + void (* func)(struct _ftdf_pending_tl_*); +} ftdf_pending_tl_t; -typedef uint8_t FTDF_RemoteId; +typedef uint8_t ftdf_remote_id; #define FTDF_REMOTE_DATA_REQUEST 0 #define FTDF_REMOTE_PAN_ID_CONFLICT_NOTIFICATION 1 #define FTDF_REMOTE_BEACON 2 #define FTDF_REMOTE_KEEP_ALIVE 3 -typedef struct -{ - FTDF_MsgId msgId; - FTDF_RemoteId remoteId; - FTDF_ShortAddress dstAddr; -} FTDF_RemoteRequest; +typedef struct { + ftdf_msg_id_t msg_id; + ftdf_remote_id remote_id; + ftdf_short_address_t dst_addr; +} ftdf_remote_request_t; #ifndef FTDF_NO_CSL -typedef struct -{ - FTDF_ShortAddress addr; - FTDF_Time time; - FTDF_Period period; -} FTDF_PeerCslTiming; +typedef struct { + ftdf_short_address_t addr; + ftdf_time_t time; + ftdf_period_t period; +} ftdf_peer_csl_timing_t; #endif /* FTDF_NO_CSL */ typedef uint8_t FTDF_State; @@ -359,343 +326,336 @@ typedef uint8_t FTDF_State; #define FTDF_STATE_SCANNING 4 #ifndef FTDF_NO_TSCH -typedef struct -{ - FTDF_ShortAddress nodeAddr; - FTDF_Size nrOfRetries; - FTDF_Size nrOfCcaRetries; - FTDF_BEExponent BE; -} FTDF_TschRetry; +typedef struct { + ftdf_short_address_t nodeAddr; + ftdf_size_t nr_of_retries; + ftdf_size_t nr_of_cca_retries; + ftdf_be_exponent_t BE; +} ftdf_tsch_retry_t; -typedef struct -{ - FTDF_ShortAddress dstAddr; - FTDF_KeepAlivePeriod period; - FTDF_RemoteRequest msg; +typedef struct { + ftdf_short_address_t dst_addr; + ftdf_keep_alive_period_t period; + ftdf_remote_request_t msg; } FTDF_NeighborEntry; #endif /* FTDF_NO_TSCH */ -typedef struct -{ - FTDF_Count fcsErrorCnt; - FTDF_Count txStdAckCnt; - FTDF_Count rxStdAckCnt; -} FTDF_LmacCounters; +typedef struct { + ftdf_count_t fcs_error_cnt; + ftdf_count_t tx_std_ack_cnt; + ftdf_count_t rx_std_ack_cnt; +} ftdf_lmac_counters_t; -extern struct FTDF_Pib FTDF_pib; -extern FTDF_State* FTDF_state; -extern FTDF_Boolean FTDF_transparentMode; -extern FTDF_Bitmap32 FTDF_transparentModeOptions; -extern FTDF_Queue FTDF_reqQueue; -extern FTDF_Queue FTDF_freeQueue; -extern FTDF_Pending FTDF_txPendingList[ FTDF_NR_OF_REQ_BUFFERS ]; -extern FTDF_PendingTL FTDF_txPendingTimerList[ FTDF_NR_OF_REQ_BUFFERS ]; -extern FTDF_PendingTL* FTDF_txPendingTimerHead; -extern FTDF_Time FTDF_txPendingTimerLT; -extern FTDF_Time FTDF_txPendingTimerTime; -extern FTDF_MsgBuffer* FTDF_reqCurrent; -extern FTDF_Size FTDF_nrOfRetries; -extern FTDF_Boolean FTDF_isPANCoordinator; -extern FTDF_SlotframeEntry FTDF_slotframeTable[ FTDF_MAX_SLOTFRAMES ]; -extern FTDF_LinkEntry FTDF_linkTable[ FTDF_MAX_LINKS ]; +extern ftdf_pib_t ftdf_pib; +extern FTDF_State *FTDF_state; +extern ftdf_boolean_t ftdf_transparent_mode; +extern ftdf_bitmap32_t ftdf_transparent_mode_options; +extern ftdf_queue_t ftdf_req_queue; +extern ftdf_queue_t ftdf_freeQueue; +extern ftdf_pending_t ftdf_tx_pending_list[FTDF_NR_OF_REQ_BUFFERS]; +extern ftdf_pending_tl_t ftdf_tx_pending_timer_list[FTDF_NR_OF_REQ_BUFFERS]; +extern ftdf_pending_tl_t *ftdf_tx_pending_timer_head; +extern ftdf_time_t ftdf_tx_pending_timer_lt; +extern ftdf_time_t ftdf_tx_pending_timer_time; +extern ftdf_msg_buffer_t *ftdf_req_current; +extern ftdf_size_t ftdf_nr_of_retries; +extern ftdf_boolean_t ftdf_is_pan_coordinator; +extern ftdf_slotframe_entry_t ftdf_slotframe_table[FTDF_MAX_SLOTFRAMES]; +extern ftdf_link_entry_t ftdf_link_table[FTDF_MAX_LINKS]; #ifndef FTDF_NO_TSCH -extern FTDF_LinkEntry* FTDF_startLinks[ FTDF_MAX_SLOTFRAMES ]; -extern FTDF_LinkEntry* FTDF_endLinks[ FTDF_MAX_SLOTFRAMES ]; -extern FTDF_NeighborEntry FTDF_neighborTable[ FTDF_NR_OF_NEIGHBORS ]; -extern FTDF_Boolean FTDF_wakeUpEnableTsch; +extern ftdf_link_entry_t *ftdf_start_links[FTDF_MAX_SLOTFRAMES]; +extern ftdf_link_entry_t *ftdf_end_links[FTDF_MAX_SLOTFRAMES]; +extern FTDF_NeighborEntry ftdf_neighbor_table[FTDF_NR_OF_NEIGHBORS]; +extern ftdf_boolean_t ftdf_wake_up_enable_tsch; #endif /* FTDF_NO_TSCH */ #ifndef FTDF_NO_CSL -extern FTDF_Boolean FTDF_wakeUpEnableLe; +extern ftdf_boolean_t ftdf_wake_up_enable_le; #endif /* FTDF_NO_CSL */ -extern FTDF_LmacCounters FTDF_lmacCounters; +extern ftdf_lmac_counters_t ftdf_lmac_counters; -extern FTDF_FrameHeader FTDF_fh; -extern FTDF_SecurityHeader FTDF_sh; -extern FTDF_AssocAdmin FTDF_aa; -extern FTDF_Boolean FTDF_txInProgress; +extern ftdf_frame_header_t ftdf_fh; +extern ftdf_security_header ftdf_sh; +extern ftdf_assoc_admin_t ftdf_aa; +extern ftdf_boolean_t ftdf_tx_in_progress; #ifndef FTDF_NO_CSL -extern FTDF_Time FTDF_rzTime; -extern FTDF_ShortAddress FTDF_sendFramePending; +extern ftdf_time_t ftdf_rz_time; +extern ftdf_short_address_t ftdf_send_frame_pending; #endif /* FTDF_NO_CSL */ -extern FTDF_Time FTDF_startCslSampleTime; +extern ftdf_time_t ftdf_start_csl_sample_time; #ifndef FTDF_NO_TSCH -extern FTDF_LinkEntry* FTDF_tschSlotLink; -extern FTDF_Time64 FTDF_tschSlotTime; -extern FTDF_ASN FTDF_tschSlotASN; +extern ftdf_link_entry_t *ftdf_tsch_slot_link; +extern ftdf_time64_t ftdf_tsch_slot_time; +extern ftdf_asn_t ftdf_tsch_slot_asn; #endif /* FTDF_NO_TSCH */ -void FTDF_processDataRequest( FTDF_DataRequest* req ); -void FTDF_processPurgeRequest( FTDF_PurgeRequest* req ); -void FTDF_processAssociateRequest( FTDF_AssociateRequest* req ); -void FTDF_processAssociateResponse( FTDF_AssociateResponse* req ); -void FTDF_processDisassociateRequest( FTDF_DisassociateRequest* req ); -void FTDF_processGetRequest( FTDF_GetRequest* req ); -void FTDF_processSetRequest( FTDF_SetRequest* req ); -void FTDF_processOrphanResponse( FTDF_OrphanResponse* req ); -void FTDF_processResetRequest( FTDF_ResetRequest* req ); -void FTDF_processRxEnableRequest( FTDF_RxEnableRequest* req ); -void FTDF_processScanRequest( FTDF_ScanRequest* req ); -void FTDF_processStartRequest( FTDF_StartRequest* req ); -void FTDF_processPollRequest( FTDF_PollRequest* req ); +void ftdf_process_data_request(ftdf_data_request_t *req); +void ftdf_process_purge_request(ftdf_purge_request_t *req); +void ftdf_process_associate_request(ftdf_associate_request_t *req); +void ftdf_process_associate_response(ftdf_associate_response_t *req); +void ftdf_process_disassociate_request(ftdf_disassociate_request_t *req); +void ftdf_process_get_request(ftdf_get_request_t *req); +void ftdf_process_set_request(ftdf_set_request_t *req); +void ftdf_process_orphan_response(ftdf_orphan_response_t *req); +void ftdf_process_reset_request(ftdf_reset_request_t *req); +void ftdf_process_rx_enable_request(ftdf_rx_enable_request_t *req); +void ftdf_process_scan_request(ftdf_scan_request_t *req); +void ftdf_process_start_request(ftdf_start_request_t *req); +void ftdf_process_poll_request(ftdf_poll_request_t *req); #ifndef FTDF_NO_TSCH -void FTDF_processSetSlotframeRequest( FTDF_SetSlotframeRequest* req ); -void FTDF_processSetLinkRequest( FTDF_SetLinkRequest* req ); -void FTDF_processTschModeRequest( FTDF_TschModeRequest* req ); -void FTDF_processKeepAliveRequest( FTDF_KeepAliveRequest* req ); +void ftdf_process_set_slotframe_request(ftdf_set_slotframe_request_t *req); +void ftdf_process_set_link_request(ftdf_set_link_request_t *req); +void ftdf_process_tsch_mode_request(ftdf_tsch_mode_request_t *req); +void ftdf_process_keep_alive_request(ftdf_keep_alive_request_t *req); #endif /* FTDF_NO_TSCH */ -void FTDF_processBeaconRequest( FTDF_BeaconRequest* req ); -void FTDF_processTransparentRequest( FTDF_TransparentRequest* req ); -void FTDF_processRemoteRequest( FTDF_RemoteRequest* req ); +void ftdf_process_beacon_request(ftdf_beacon_request_t *req); +void ftdf_process_transparent_request(ftdf_transparent_request_t *req); +void ftdf_process_remote_request(ftdf_remote_request_t *req); -void FTDF_processNextRequest( void ); -void FTDF_processRxEvent( void ); -void FTDF_processTxEvent( void ); -void FTDF_processSymbolTimerEvent( void ); +void ftdf_process_next_request(void); +void ftdf_process_rx_event(void); +void ftdf_process_tx_event(void); +void ftdf_process_symbol_timer_event(void); -void FTDF_sendDataConfirm( FTDF_DataRequest* dataRequest, - FTDF_Status status, - FTDF_Time timestamp, - FTDF_SN DSN, - FTDF_NumOfBackoffs numOfBackoffs, - FTDF_IEList* ackPayload ); +void ftdf_send_data_confirm(ftdf_data_request_t *data_request, + ftdf_status_t status, + ftdf_time_t timestamp, + ftdf_sn_t dsn, + ftdf_num_of_backoffs_t num_of_backoffs, + ftdf_ie_list_t *ack_payload); -void FTDF_sendDataIndication( FTDF_FrameHeader* frameHeader, - FTDF_SecurityHeader* securityHeader, - FTDF_IEList* payloadIEList, - FTDF_DataLength msduLength, - FTDF_Octet* msdu, - FTDF_LinkQuality mpduLinkQuality, - FTDF_Time timestamp ); +void ftdf_send_data_indication(ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header, + ftdf_ie_list_t *payload_ie_list, + ftdf_data_length_t msdu_length, + ftdf_octet_t *msdu, + ftdf_link_quality_t mpdu_link_quality, + ftdf_time_t timestamp); -void FTDF_sendPollConfirm( FTDF_PollRequest* pollRequest, FTDF_Status status ); +void ftdf_send_poll_confirm(ftdf_poll_request_t *poll_request, ftdf_status_t status); -void FTDF_sendScanConfirm( FTDF_ScanRequest* scanRequest, FTDF_Status status ); +void ftdf_send_scan_confirm(ftdf_scan_request_t *scan_request, ftdf_status_t status); -void FTDF_sendBeaconNotifyIndication( FTDF_PANDescriptor* PANDescriptor ); +void ftdf_send_beacon_notify_indication(ftdf_pan_descriptor_t *pan_descriptor); -void FTDF_sendBeaconConfirm( FTDF_BeaconRequest* beaconRequest, FTDF_Status status ); +void ftdf_send_beacon_confirm(ftdf_beacon_request_t *beacon_request, ftdf_status_t status); -void FTDF_sendAssociateConfirm( FTDF_AssociateRequest* associateRequest, - FTDF_Status status, - FTDF_ShortAddress assocShortAddr ); +void ftdf_send_associate_confirm(ftdf_associate_request_t *associate_request, + ftdf_status_t status, + ftdf_short_address_t assoc_short_addr); -void FTDF_sendAssociateDataRequest( void ); +void ftdf_send_associate_data_request(void); -void FTDF_sendDisassociateConfirm( FTDF_DisassociateRequest* disReq, FTDF_Status status ); +void ftdf_send_disassociate_confirm(ftdf_disassociate_request_t *dis_req, ftdf_status_t status); -void FTDF_sendSyncLossIndication( FTDF_LossReason lossReason, FTDF_SecurityHeader* securityHeader ); +void ftdf_send_sync_loss_indication(ftdf_loss_reason_t loss_reason, ftdf_security_header *security_header); -void FTDF_sendPANIdConflictNotification( FTDF_FrameHeader* frameHeader, FTDF_SecurityHeader* securityHeader ); +void ftdf_sendpan_id_conflict_notification(ftdf_frame_header_t *frame_header, ftdf_security_header *security_header); -void FTDF_sendCommStatusIndication( FTDF_MsgBuffer* request, - FTDF_Status status, - FTDF_PANId PANId, - FTDF_AddressMode srcAddrMode, - FTDF_Address srcAddr, - FTDF_AddressMode dstAddrMode, - FTDF_Address dstAddr, - FTDF_SecurityLevel securityLevel, - FTDF_KeyIdMode keyIdMode, - FTDF_Octet* keySource, - FTDF_KeyIndex keyIndex ); +void ftdf_send_comm_status_indication(ftdf_msg_buffer_t *request, + ftdf_status_t status, + ftdf_pan_id_t pan_Id, + ftdf_address_mode_t src_addr_mode, + ftdf_address_t src_addr, + ftdf_address_mode_t dst_addr_mode, + ftdf_address_t dst_addr, + ftdf_security_level_t security_level, + ftdf_key_id_mode_t key_id_mode, + ftdf_octet_t *key_source, + ftdf_key_index_t key_index); -void FTDF_startTimer( FTDF_Period period, - void ( * timerFunc )( void* params ), - void* params ); +void ftdf_start_timer(ftdf_period_t period, void (* timer_func)(void *params), void *params); -FTDF_Octet* FTDF_getTxBufPtr( FTDF_Buffer* txBuffer ); +ftdf_octet_t *ftdf_get_tx_buf_ptr(ftdf_buffer_t *tx_buffer); -void FTDF_setTxMetaData( FTDF_Buffer* txBuffer, - FTDF_DataLength frameLength, - FTDF_ChannelNumber channel, - FTDF_FrameType frameType, - FTDF_Boolean ackTX, - FTDF_SN SN ); +void ftdf_set_tx_meta_data(ftdf_buffer_t *tx_buffer, + ftdf_data_length_t frame_length, + ftdf_channel_number_t channel, + ftdf_frame_type_t frame_type, + ftdf_boolean_t ack_tx, + ftdf_sn_t sn); -FTDF_Status FTDF_sendFrame( FTDF_ChannelNumber channel, - FTDF_FrameHeader* frameHeader, - FTDF_SecurityHeader* securityHeader, - FTDF_Octet* txPtr, - FTDF_DataLength payloadSize, - FTDF_Octet* payload ); +ftdf_status_t ftdf_send_frame(ftdf_channel_number_t channel, + ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header, + ftdf_octet_t *tx_ptr, + ftdf_data_length_t payload_size, + ftdf_octet_t *payload); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -FTDF_Status FTDF_sendAckFrame( FTDF_FrameHeader* frameHeader, - FTDF_SecurityHeader* securityHeader, - FTDF_Octet* txPtr ); +ftdf_status_t ftdf_send_ack_frame(ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header, + ftdf_octet_t *tx_ptr); #endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ -void FTDF_sendTransparentFrame( FTDF_DataLength frameLength, - FTDF_Octet* frame, - FTDF_ChannelNumber channel, - FTDF_PTI pti, - FTDF_Boolean cmsaSuppress ); +void ftdf_send_transparent_frame(ftdf_data_length_t frame_length, + ftdf_octet_t *frame, + ftdf_channel_number_t channel, + ftdf_pti_t pti, + ftdf_boolean_t cmsa_suppress); -FTDF_Octet* FTDF_getRxBuffer( void ); +ftdf_octet_t *ftdf_get_rx_buffer(void); -void FTDF_processRxEvent( void ); +void ftdf_process_rx_event(void); -FTDF_Octet* FTDF_addFrameHeader( FTDF_Octet* txPtr, - FTDF_FrameHeader* frameHeader, - FTDF_DataLength msduLength ); +ftdf_octet_t *ftdf_add_frame_header(ftdf_octet_t *tx_ptr, + ftdf_frame_header_t *frame_header, + ftdf_data_length_t msdu_length); -FTDF_Octet* FTDF_getFrameHeader( FTDF_Octet* rxPtr, - FTDF_FrameHeader* frameHeader ); +ftdf_octet_t *ftdf_get_frame_header(ftdf_octet_t *rx_ptr, ftdf_frame_header_t *frame_header); -FTDF_DataLength FTDF_getMicLength( FTDF_SecurityLevel securityLevel ); +ftdf_data_length_t ftdf_get_mic_length(ftdf_security_level_t security_level); -FTDF_Octet* FTDF_getSecurityHeader( FTDF_Octet* rxPtr, - uint8_t frameVersion, - FTDF_SecurityHeader* securityHeader ); +ftdf_octet_t *ftdf_get_security_header(ftdf_octet_t *rx_ptr, + uint8_t frame_version, + ftdf_security_header *security_header); -FTDF_Octet* FTDF_addSecurityHeader( FTDF_Octet* txPtr, - FTDF_SecurityHeader* securityHeader ); +ftdf_octet_t *ftdf_add_security_header(ftdf_octet_t *tx_ptr, + ftdf_security_header *security_header); -FTDF_Status FTDF_secureFrame( FTDF_Octet* bufPtr, - FTDF_Octet* privPtr, - FTDF_FrameHeader* frameHeader, - FTDF_SecurityHeader* securityHeader ); +ftdf_status_t ftdf_secure_frame(ftdf_octet_t *buf_ptr, + ftdf_octet_t *priv_ptr, + ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header); -FTDF_Status FTDF_unsecureFrame( FTDF_Octet* bufPtr, - FTDF_Octet* privPtr, - FTDF_FrameHeader* frameHeader, - FTDF_SecurityHeader* securityHeader ); +ftdf_status_t ftdf_unsecure_frame(ftdf_octet_t *buf_ptr, + ftdf_octet_t *priv_ptr, + ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header); -FTDF_KeyDescriptor* FTDF_lookupKey( FTDF_AddressMode devAddrMode, - FTDF_PANId devPANId, - FTDF_Address devAddr, - FTDF_FrameType frameType, - FTDF_KeyIdMode keyIdMode, - FTDF_KeyIndex keyIndex, - FTDF_Octet* keySource ); +ftdf_key_descriptor_t *ftdf_lookup_key(ftdf_address_mode_t dev_addr_mode, + ftdf_pan_id_t dev_pan_id, + ftdf_address_t dev_addr, + ftdf_frame_type_t frame_type, + ftdf_key_id_mode_t key_id_mode, + ftdf_key_index_t key_index, + ftdf_octet_t *key_source); -FTDF_DeviceDescriptor* FTDF_lookupDevice( FTDF_Size nrOfDeviceDescriptorHandles, - FTDF_DeviceDescriptorHandle* deviceDescriptorHandles, - FTDF_AddressMode devAddrMode, - FTDF_PANId devPANId, - FTDF_Address devAddr ); +ftdf_device_descriptor_t *ftdf_lookup_device(ftdf_size_t nr_of_device_descriptor_handles, + ftdf_device_descriptor_handle_t *device_descriptor_handles, + ftdf_address_mode_t dev_addr_mode, + ftdf_pan_id_t dev_pan_id, + ftdf_address_t dev_addr); -FTDF_SecurityLevelDescriptor* FTDF_getSecurityLevelDescr( FTDF_FrameType frameType, - FTDF_CommandFrameId commandFrameId ); +ftdf_security_level_descriptor_t *ftdf_get_security_level_descr(ftdf_frame_type_t frame_type, + ftdf_command_frame_id_t command_frame_id); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -FTDF_Octet* FTDF_addIes( FTDF_Octet* txPtr, - FTDF_IEList* headerIEList, - FTDF_IEList* payloadIEList, - FTDF_Boolean withTerminationIE ); +ftdf_octet_t *ftdf_add_ies(ftdf_octet_t *tx_ptr, + ftdf_ie_list_t *header_ie_list, + ftdf_ie_list_t *payload_ie_list, + ftdf_boolean_t with_termination_ie); -FTDF_Octet* FTDF_getIes( FTDF_Octet* rxPtr, - FTDF_Octet* frameEndPtr, - FTDF_IEList** headerIEList, - FTDF_IEList** payloadIEList ); +ftdf_octet_t *ftdf_get_ies(ftdf_octet_t *rx_ptr, + ftdf_octet_t *frame_end_ptr, + ftdf_ie_list_t **header_ie_list, + ftdf_ie_list_t **payload_ie_list); #endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ #ifndef FTDF_NO_CSL -void FTDF_setPeerCslTiming( FTDF_IEList* headerIEList, - FTDF_Time timeStamp ); -void FTDF_setCslSampleTime( void ); -void FTDF_getWakeupParams( FTDF_ShortAddress dstAddr, - FTDF_Time* wakeupStartTime, - FTDF_Period* wakeupPeriod ); +void ftdf_set_peer_csl_timing(ftdf_ie_list_t *header_ie_list, ftdf_time_t timeStamp); +void ftdf_set_csl_sample_time(void); +void ftdf_get_wakeup_params(ftdf_short_address_t dst_addr, + ftdf_time_t *wakeup_start_time, + ftdf_period_t *wakeup_period); #endif /* FTDF_NO_CSL */ -void FTDF_getExtAddress( void ); -void FTDF_setExtAddress( void ); -void FTDF_getAckWaitDuration( void ); -void FTDF_getEnhAckWaitDuration( void ); -void FTDF_setEnhAckWaitDuration( void ); -void FTDF_getImplicitBroadcast( void ); -void FTDF_setImplicitBroadcast( void ); -void FTDF_setShortAddress( void ); -void FTDF_setSimpleAddress( void ); -void FTDF_getRxOnWhenIdle( void ); -void FTDF_setRxOnWhenIdle( void ); -void FTDF_getPANId( void ); -void FTDF_setPANId( void ); -void FTDF_getCurrentChannel( void ); -void FTDF_setCurrentChannel( void ); +void ftdf_get_ext_address(void); +void ftdf_set_ext_address(void); +void ftdf_get_ack_wait_duration(void); +void ftdf_get_enh_ack_wait_duration(void); +void ftdf_set_enh_ack_wait_duration(void); +void ftdf_get_implicit_broadcast(void); +void ftdf_set_implicit_broadcast(void); +void ftdf_set_short_address(void); +void ftdf_set_simple_address(void); +void ftdf_get_rx_on_when_idle(void); +void ftdf_set_rx_on_when_idle(void); +void ftdf_getpan_id(void); +void ftdf_setpan_id(void); +void ftdf_get_current_channel(void); +void ftdf_set_current_channel(void); void FTDF_setTXPower( void ); -void FTDF_getMaxFrameTotalWaitTime( void ); -void FTDF_setMaxFrameTotalWaitTime( void ); +void ftdf_get_max_frame_total_wait_time(void); +void ftdf_set_max_frame_total_wait_time(void); #ifndef FTDF_NO_CSL -void FTDF_setLeEnabled( void ); -void FTDF_getCslFramePendingWaitT( void ); -void FTDF_setCslFramePendingWaitT( void ); +void ftdf_set_le_enabled(void); +void ftdf_get_csl_frame_pending_wait(void); +void ftdf_set_csl_frame_pending_wait(void); #endif /* FTDF_NO_CSL */ -void FTDF_getLmacPmData( void ); -void FTDF_getLmacTrafficCounters( void ); -void FTDF_setMaxCSMABackoffs( void ); -void FTDF_setMaxBE( void ); -void FTDF_setMinBE( void ); -void FTDF_getKeepPhyEnabled( void ); -void FTDF_setKeepPhyEnabled( void ); -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -void FTDF_setBoIrqThreshold( void ); -void FTDF_getBoIrqThreshold( void ); -void FTDF_setPtiConfig( void ); -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ +void ftdf_get_lmac_pm_data(void); +void ftdf_get_lmac_traffic_counters(void); +void ftdf_set_max_csma_backoffs(void); +void ftdf_set_max_be(void); +void ftdf_set_min_be(void); +void ftdf_get_keep_phy_enabled(void); +void ftdf_set_keep_phy_enabled(void); +void ftdf_set_bo_irq_threshold(void); +void ftdf_get_bo_irq_threshold(void); +void ftdf_set_pti_config(void); #ifndef FTDF_NO_TSCH -void FTDF_setTimeslotTemplate( void ); +void ftdf_set_timeslot_template(void); #endif /* FTDF_NO_TSCH */ -void FTDF_initLmac( void ); -void FTDF_initQueues( void ); -void FTDF_initQueue( FTDF_Queue* queue ); -void FTDF_queueBufferHead( FTDF_Buffer* buffer, FTDF_Queue* queue ); -FTDF_Status FTDF_queueReqHead( FTDF_MsgBuffer* request, FTDF_Queue* queue ); -FTDF_Buffer* FTDF_dequeueBufferTail( FTDF_Queue* queue ); -FTDF_MsgBuffer* FTDF_dequeueReqTail( FTDF_Queue* queue ); -FTDF_MsgBuffer* FTDF_dequeueByHandle( FTDF_Handle handle, FTDF_Queue* queue ); -FTDF_Buffer* FTDF_dequeueByBuffer( FTDF_Buffer* buffer, FTDF_Queue* queue ); -FTDF_Boolean FTDF_isQueueEmpty( FTDF_Queue* queue ); -void FTDF_addTxPendingTimer( FTDF_MsgBuffer* request, uint8_t pendListNr, FTDF_Time delta, void ( * func )( - FTDF_PendingTL* ) ); -void FTDF_removeTxPendingTimer( FTDF_MsgBuffer* request ); -void FTDF_restoreTxPendingTimer( void ); -FTDF_Boolean FTDF_getTxPendingTimerHead( FTDF_Time* time ); -void FTDF_sendTransactionExpired( FTDF_PendingTL* ptr ); +void ftdf_init_lmac(void); +void ftdf_init_queues(void); +void ftdf_init_queue(ftdf_queue_t *queue); +void ftdf_queue_buffer_head(ftdf_buffer_t *buffer, ftdf_queue_t *queue); +ftdf_status_t ftdf_queue_req_head(ftdf_msg_buffer_t *request, ftdf_queue_t *queue); +ftdf_buffer_t *ftdf_dequeue_buffer_tail(ftdf_queue_t *queue); +ftdf_msg_buffer_t *ftdf_dequeue_req_tail(ftdf_queue_t *queue); +ftdf_msg_buffer_t *ftdf_dequeue_by_handle(ftdf_handle_t handle, ftdf_queue_t *queue); +ftdf_buffer_t *ftdf_dequeue_by_buffer(ftdf_buffer_t *buffer, ftdf_queue_t *queue); +ftdf_boolean_t ftdf_is_queue_empty(ftdf_queue_t *queue); + +void ftdf_add_tx_pending_timer(ftdf_msg_buffer_t *request, + uint8_t pend_list_nr, + ftdf_time_t delta, + void (* func)(ftdf_pending_tl_t*)); + +void ftdf_remove_tx_pending_timer(ftdf_msg_buffer_t *request); +void ftdf_restore_tx_pending_timer(void); +ftdf_boolean_t ftdf_get_tx_pending_timer_head(ftdf_time_t *time); +void ftdf_send_transaction_expired(ftdf_pending_tl_t *ptr); #ifndef FTDF_NO_TSCH -void FTDF_processKeepAliveTimerExp( FTDF_PendingTL* ptr ); -void FTDF_resetKeepAliveTimer( FTDF_ShortAddress dstAddr ); +void ftdf_process_keep_alive_timer_exp(ftdf_pending_tl_t *ptr); +void ftdf_reset_keep_alive_timer(ftdf_short_address_t dst_addr); #endif /* FTDF_NO_TSCH */ -void FTDF_processTxPending(FTDF_FrameHeader* frameHeader, - FTDF_SecurityHeader* securityHeader ); +void ftdf_process_tx_pending(ftdf_frame_header_t *frame_hader, ftdf_security_header *security_header); -void FTDF_processCommandFrame( FTDF_Octet* rxBuffer, - FTDF_FrameHeader* frameHeader, - FTDF_SecurityHeader* securityHeader, - FTDF_IEList* payloadIEList ); +void ftdf_process_command_frame(ftdf_octet_t *rx_buffer, + ftdf_frame_header_t *frame_header, + ftdf_security_header *security_header, + ftdf_ie_list_t *payload_ie_list); -void FTDF_scanReady( FTDF_ScanRequest* ); -void FTDF_addPANdescriptor( FTDF_PANDescriptor* ); -void FTDF_sendBeaconRequest( FTDF_ChannelNumber channel ); -void FTDF_sendBeaconRequestIndication( FTDF_FrameHeader* frameHeader, - FTDF_IEList* payloadIEList ); -void FTDF_sendOrphanNotification( FTDF_ChannelNumber channel ); +void ftdf_scan_ready(ftdf_scan_request_t*); +void ftdf_add_pan_descriptor(ftdf_pan_descriptor_t*); +void ftdf_send_beacon_request(ftdf_channel_number_t channel); +void ftdf_send_beacon_request_indication(ftdf_frame_header_t *frame_header, ftdf_ie_list_t *payload_ie_list); +void ftdf_send_orphan_notification(ftdf_channel_number_t channel); #ifndef FTDF_NO_TSCH -void FTDF_setTschEnabled( void ); -FTDF_Status FTDF_scheduleTsch( FTDF_MsgBuffer* request ); -void FTDF_tschProcessRequest( void ); -FTDF_Size FTDF_getTschSyncSubIe( void ); -FTDF_Octet* FTDF_addTschSyncSubIe( FTDF_Octet* txPtr ); -FTDF_ShortAddress FTDF_getRequestAddress( FTDF_MsgBuffer* request ); -FTDF_MsgBuffer* FTDF_tschGetPending( FTDF_MsgBuffer* request ); -FTDF_Octet* FTDF_addCorrTimeIE( FTDF_Octet* txPtr, FTDF_Time rxTimestamp ); -void FTDF_correctSlotTime( FTDF_Time rxTimestamp ); -void FTDF_correctSlotTimeFromAck( FTDF_IEList* headerIEList ); -void FTDF_initTschRetries( void ); -FTDF_TschRetry* FTDF_getTschRetry( FTDF_ShortAddress nodeAddr ); -FTDF_NumOfBackoffs FTDF_getNumOfBackoffs( FTDF_BEExponent BE ); -void FTDF_initBackoff( void ); -FTDF_SN FTDF_processTschSN( FTDF_MsgBuffer* msg, FTDF_SN sn, uint8_t* priv ); +void ftdf_set_tsch_enabled(void); +ftdf_status_t ftdf_schedule_tsch(ftdf_msg_buffer_t *request); +void ftdf_tsch_process_request(void); +ftdf_size_t ftdf_get_tsch_sync_sub_ie(void); +ftdf_octet_t *ftdf_add_tsch_sync_sub_ie(ftdf_octet_t *tx_ptr); +ftdf_short_address_t ftdf_get_request_address(ftdf_msg_buffer_t *request); +ftdf_msg_buffer_t *ftdf_tsch_get_pending(ftdf_msg_buffer_t *request); +ftdf_octet_t *ftdf_add_corr_time_ie(ftdf_octet_t *tx_ptr, ftdf_time_t rx_timestamp); +void ftdf_correct_slot_time(ftdf_time_t rx_timestamp); +void ftdf_correct_slot_time_from_ack(ftdf_ie_list_t *header_ie_list); +void ftdf_init_tsch_retries(void); +ftdf_tsch_retry_t *ftdf_get_tsch_retry(ftdf_short_address_t node_addr); +ftdf_num_of_backoffs_t ftdf_get_num_of_backoffs(ftdf_be_exponent_t be); +void ftdf_init_backoff(void); +ftdf_sn_t ftdf_process_tsch_sn(ftdf_msg_buffer_t *msg, ftdf_sn_t sn, uint8_t *priv); #endif /* FTDF_NO_TSCH */ -FTDF_Time64 FTDF_getCurTime64( void ); -void FTDF_initCurTime64( void ); +ftdf_time64_t ftdf_get_cur_time64(void); +void ftdf_init_cur_time64(void); #if FTDF_USE_SLEEP_DURING_BACKOFF typedef enum @@ -704,41 +664,60 @@ typedef enum FTDF_SDB_STATE_BACKING_OFF, FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ, FTDF_SDB_STATE_RESUMING, -} FTDF_SdbState; +} ftdf_sdb_state_t; typedef struct { - FTDF_SdbState state; - FTDF_Size nrOfBackoffs; - FTDF_Time ccaRetryTime; - FTDF_Octet buffer[FTDF_BUFFER_LENGTH]; - uint32_t metadata0; - uint32_t metadata1; - uint32_t phyCsmaCaAttr; -} FTDF_Sdb; + ftdf_sdb_state_t state; + ftdf_size_t nr_of_backoffs; + ftdf_time_t cca_retry_time; + ftdf_octet_t buffer[FTDF_BUFFER_LENGTH]; + uint32_t metadata_0; + uint32_t metadata_1; + uint32_t phy_csma_ca_attr; +} ftdf_sdb_t; -void FTDF_sdbFsmReset(void); +void ftdf_sdb_fsm_reset(void); -void FTDF_sdbFsmBackoffIRQ(void); +void ftdf_sdb_fsm_backoff_irq(void); -void FTDF_sdbFsmSleep(void); +void ftdf_sdb_fsm_sleep(void); -void FTDF_sdbFsmAbortSleep(void); +void ftdf_sdb_fsm_abort_sleep(void); -void FTDF_sdbFsmWakeUpIRQ(void); +void ftdf_sdb_fsm_wake_up_irq(void); -void FTDF_sdbFsmWakeUp(void); +void ftdf_sdb_fsm_wake_up(void); -void FTDF_sdbFsmTxIRQ(void); +void ftdf_sdb_fsm_tx_irq(void); -FTDF_USec FTDF_sdbGetSleepTime(void); +ftdf_usec_t ftdf_sdb_get_sleep_time(void); #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ -#if dg_configUSE_FTDF_DDPHY == 1 +static inline void ftdf_set_link_quality_mode(void) +{ +#ifdef FTDF_PIB_LINK_QUALITY_MODE + REG_SETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_DEM_PTI, + (ftdf_pib.link_quality_mode == FTDF_LINK_QUALITY_MODE_RSSI) ? 0x8 : 0); -void FTDF_ddphyRestore(void); + REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_SCALE, 0); -void FTDF_ddphySave(void); + if (ftdf_pib.link_quality_mode == FTDF_LINK_QUALITY_MODE_RSSI) { + REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_PREAMBLE_EN, 0); + REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_CORRTH_EN, 1); + } else { + REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_PREAMBLE_EN, 1); + REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_CORRTH_EN, 0); + } + +#endif +} + +#if dg_configUSE_FTDF_DDPHY == 1 + +void ftdf_ddphy_restore(void); + +void ftdf_ddphy_save(void); #endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c index f869f9183..35a7f66a4 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c @@ -37,295 +37,256 @@ #include #include "internal.h" -#include "regmap.h" #include "ftdfInfo.h" -void FTDF_getReleaseInfo(char **lmacRelName, char **lmacBuildTime, char **umacRelName, char **umacBuildTime) +void ftdf_get_release_info(char **lmac_rel_name, char **lmac_build_time, char **umac_rel_name, + char **umac_build_time) { - static char lrelName[ 16 ]; - static char lbldTime[ 16 ]; - static char urelName[ 16 ]; - static char ubldTime[ 16 ]; - uint8_t i; + static char lrel_name[16]; + static char lbld_time[16]; + static char urel_name[16]; + static char ubld_time[16]; + uint8_t i; - volatile uint32_t *ptr = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_REL_NAME); - uint32_t *chrPtr = (uint32_t *)lrelName; + volatile uint32_t *ptr = &FTDF->FTDF_REL_NAME_0_REG; + uint32_t *chr_ptr = (uint32_t*)lrel_name; - for (i = 0; i < FTDF_ON_OFF_REGMAP_REL_NAME_NUM; i++) - { - *chrPtr++ = *ptr++; - } - - ptr = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_BUILDTIME); - chrPtr = (uint32_t *)lbldTime; - - for (i = 0; i < FTDF_ON_OFF_REGMAP_BUILDTIME_NUM; i++) - { - *chrPtr++ = *ptr++; - } - - const char *umacVPtr = FTDF_getUmacRelName(); - - for (i = 0; i < 16; i++) - { - urelName[ i ] = umacVPtr[ i ]; - - if (umacVPtr[ i ] == '\0') - { - break; + for (i = 0; i < 4; i++) { + *chr_ptr++ = *ptr++; } - } - umacVPtr = FTDF_getUmacBuildTime(); + ptr = &FTDF->FTDF_BUILDTIME_0_REG; + chr_ptr = (uint32_t*)lbld_time; - for (i = 0; i < 16; i++) - { - ubldTime[ i ] = umacVPtr[ i ]; - - if (umacVPtr[ i ] == '\0') - { - break; + for (i = 0; i < 4; i++) { + *chr_ptr++ = *ptr++; } - } - lrelName[ 15 ] = '\0'; - lbldTime[ 15 ] = '\0'; - urelName[ 15 ] = '\0'; - ubldTime[ 15 ] = '\0'; + const char* umac_v_ptr = ftdf_get_umac_rel_name(); - *lmacRelName = lrelName; - *lmacBuildTime = lbldTime; - *umacRelName = urelName; - *umacBuildTime = ubldTime; + for (i = 0; i < 16; i++) { + urel_name[i] = umac_v_ptr[i]; + + if (umac_v_ptr[i] == '\0') { + break; + } + } + + umac_v_ptr = ftdf_get_umac_build_time(); + + for (i = 0; i < 16; i++) { + ubld_time[i] = umac_v_ptr[i]; + + if (umac_v_ptr[i] == '\0') { + break; + } + } + + lrel_name[15] = '\0'; + lbld_time[15] = '\0'; + urel_name[15] = '\0'; + ubld_time[15] = '\0'; + + *lmac_rel_name = lrel_name; + *lmac_build_time = lbld_time; + *umac_rel_name = urel_name; + *umac_build_time = ubld_time; } -void FTDF_confirmLmacInterrupt(void) +void ftdf_confirm_lmac_interrupt(void) { - volatile uint32_t *ftdfCm = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CM); - *ftdfCm = 0; + REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM, 0); } -void FTDF_eventHandler(void) +void ftdf_event_handler(void) { - volatile uint32_t ftdfCe = *FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CE); + volatile uint32_t ftdf_ce = FTDF->FTDF_FTDF_CE_REG; - if (ftdfCe & FTDF_MSK_RX_CE) - { - FTDF_processRxEvent(); - } + if (ftdf_ce & FTDF_MSK_RX_CE) { + ftdf_process_rx_event(); + } - if (ftdfCe & FTDF_MSK_TX_CE) - { - FTDF_processTxEvent(); - } + if (ftdf_ce & FTDF_MSK_TX_CE) { + ftdf_process_tx_event(); + } - if (ftdfCe & FTDF_MSK_SYMBOL_TMR_CE) - { - FTDF_processSymbolTimerEvent(); - } + if (ftdf_ce & FTDF_MSK_SYMBOL_TMR_CE) { + ftdf_process_symbol_timer_event(); + } #ifndef FTDF_LITE #ifndef FTDF_NO_CSL + if (ftdf_pib.le_enabled) { + ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, + SYMBOLTIMESNAPSHOTVAL); - if (FTDF_pib.leEnabled) - { - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_Time delta = curTime - FTDF_rzTime; + ftdf_time_t delta = cur_time - ftdf_rz_time; - if (delta < 0x80000000) - { - // RZ has passed check if a send frame is pending - if (FTDF_sendFramePending != 0xfffe) - { - FTDF_Time wakeupStartTime; - FTDF_Period wakeupPeriod; + if (delta < 0x80000000) { + /* RZ has passed check if a send frame is pending */ + if (ftdf_send_frame_pending != 0xfffe) { + ftdf_time_t wakeup_start_time; + ftdf_period_t wakeup_period; - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); - FTDF_getWakeupParams(FTDF_sendFramePending, &wakeupStartTime, &wakeupPeriod); + ftdf_get_wakeup_params(ftdf_send_frame_pending, &wakeup_start_time, + &wakeup_period); - FTDF_txInProgress = FTDF_TRUE; - FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME, wakeupStartTime); - FTDF_SET_FIELD(ON_OFF_REGMAP_MACWUPERIOD, wakeupPeriod); + ftdf_tx_in_progress = FTDF_TRUE; + REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, + wakeup_start_time); + REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACWUPERIOD, wakeup_period); - volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); - *txFlagSet |= ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER)); + REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, + ((1 << FTDF_TX_DATA_BUFFER) | + (1 << FTDF_TX_WAKEUP_BUFFER))); - FTDF_sendFramePending = 0xfffe; + ftdf_send_frame_pending = 0xfffe; - FTDF_exitCritical(); - } + ftdf_exit_critical(); + } - if (FTDF_txInProgress == FTDF_FALSE) - { - FTDF_setCslSampleTime(); - } + if (ftdf_tx_in_progress == FTDF_FALSE) { + ftdf_set_csl_sample_time(); + } + } } - } - #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ - volatile uint32_t *ftdfCm = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CM); - *ftdfCm = FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE; + REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM, + (FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE)); } #ifndef FTDF_PHY_API -void FTDF_sndMsg(FTDF_MsgBuffer *msgBuf) +void ftdf_snd_msg(ftdf_msg_buffer_t* msg_buf) { - switch (msgBuf->msgId) - { + switch (msg_buf->msg_id) { #ifndef FTDF_LITE - - case FTDF_DATA_REQUEST: - FTDF_processDataRequest((FTDF_DataRequest *) msgBuf); - break; - - case FTDF_PURGE_REQUEST: - FTDF_processPurgeRequest((FTDF_PurgeRequest *) msgBuf); - break; - - case FTDF_ASSOCIATE_REQUEST: - FTDF_processAssociateRequest((FTDF_AssociateRequest *) msgBuf); - break; - - case FTDF_ASSOCIATE_RESPONSE: - FTDF_processAssociateResponse((FTDF_AssociateResponse *) msgBuf); - break; - - case FTDF_DISASSOCIATE_REQUEST: - FTDF_processDisassociateRequest((FTDF_DisassociateRequest *) msgBuf); - break; + case FTDF_DATA_REQUEST: + ftdf_process_data_request((ftdf_data_request_t*)msg_buf); + break; + case FTDF_PURGE_REQUEST: + ftdf_process_purge_request((ftdf_purge_request_t*)msg_buf); + break; + case FTDF_ASSOCIATE_REQUEST: + ftdf_process_associate_request((ftdf_associate_request_t*)msg_buf); + break; + case FTDF_ASSOCIATE_RESPONSE: + ftdf_process_associate_response((ftdf_associate_response_t*)msg_buf); + break; + case FTDF_DISASSOCIATE_REQUEST: + ftdf_process_disassociate_request((ftdf_disassociate_request_t*)msg_buf); + break; #endif /* !FTDF_LITE */ - - case FTDF_GET_REQUEST: - FTDF_processGetRequest((FTDF_GetRequest *) msgBuf); - break; - - case FTDF_SET_REQUEST: - FTDF_processSetRequest((FTDF_SetRequest *) msgBuf); - break; + case FTDF_GET_REQUEST: + ftdf_process_get_request((ftdf_get_request_t*)msg_buf); + break; + case FTDF_SET_REQUEST: + ftdf_process_set_request((ftdf_set_request_t*)msg_buf); + break; #ifndef FTDF_LITE - - case FTDF_ORPHAN_RESPONSE: - FTDF_processOrphanResponse((FTDF_OrphanResponse *) msgBuf); - break; + case FTDF_ORPHAN_RESPONSE: + ftdf_process_orphan_response((ftdf_orphan_response_t*)msg_buf); + break; #endif /* !FTDF_LITE */ - - case FTDF_RESET_REQUEST: - FTDF_processResetRequest((FTDF_ResetRequest *) msgBuf); - break; - - case FTDF_RX_ENABLE_REQUEST: - FTDF_processRxEnableRequest((FTDF_RxEnableRequest *) msgBuf); - break; + case FTDF_RESET_REQUEST: + ftdf_process_reset_request((ftdf_reset_request_t*)msg_buf); + break; + case FTDF_RX_ENABLE_REQUEST: + ftdf_process_rx_enable_request((ftdf_rx_enable_request_t*)msg_buf); + break; #ifndef FTDF_LITE - - case FTDF_SCAN_REQUEST: - FTDF_processScanRequest((FTDF_ScanRequest *) msgBuf); - break; - - case FTDF_START_REQUEST: - FTDF_processStartRequest((FTDF_StartRequest *) msgBuf); - break; - - case FTDF_POLL_REQUEST: - FTDF_processPollRequest((FTDF_PollRequest *) msgBuf); - break; + case FTDF_SCAN_REQUEST: + ftdf_process_scan_request((ftdf_scan_request_t*)msg_buf); + break; + case FTDF_START_REQUEST: + ftdf_process_start_request((ftdf_start_request_t*)msg_buf); + break; + case FTDF_POLL_REQUEST: + ftdf_process_poll_request((ftdf_poll_request_t*)msg_buf); + break; #ifndef FTDF_NO_TSCH - - case FTDF_SET_SLOTFRAME_REQUEST: - FTDF_processSetSlotframeRequest((FTDF_SetSlotframeRequest *) msgBuf); - break; - - case FTDF_SET_LINK_REQUEST: - FTDF_processSetLinkRequest((FTDF_SetLinkRequest *) msgBuf); - break; - - case FTDF_TSCH_MODE_REQUEST: - FTDF_processTschModeRequest((FTDF_TschModeRequest *) msgBuf); - break; - - case FTDF_KEEP_ALIVE_REQUEST: - FTDF_processKeepAliveRequest((FTDF_KeepAliveRequest *) msgBuf); - break; + case FTDF_SET_SLOTFRAME_REQUEST: + ftdf_process_set_slotframe_request((ftdf_set_slotframe_request_t*)msg_buf); + break; + case FTDF_SET_LINK_REQUEST: + ftdf_process_set_link_request((ftdf_set_link_request_t*)msg_buf); + break; + case FTDF_TSCH_MODE_REQUEST: + ftdf_process_tsch_mode_request((ftdf_tsch_mode_request_t*)msg_buf); + break; + case FTDF_KEEP_ALIVE_REQUEST: + ftdf_process_keep_alive_request((ftdf_keep_alive_request_t*)msg_buf); + break; #endif /* FTDF_NO_TSCH */ - - case FTDF_BEACON_REQUEST: - FTDF_processBeaconRequest((FTDF_BeaconRequest *) msgBuf); - break; + case FTDF_BEACON_REQUEST: + ftdf_process_beacon_request((ftdf_beacon_request_t*)msg_buf); + break; #endif /* !FTDF_LITE */ - - case FTDF_TRANSPARENT_ENABLE_REQUEST: - FTDF_enableTransparentMode(((FTDF_TransparentEnableRequest *) msgBuf)->enable, - ((FTDF_TransparentEnableRequest *) msgBuf)->options); - FTDF_REL_MSG_BUFFER(msgBuf); - break; - - case FTDF_TRANSPARENT_REQUEST: - FTDF_processTransparentRequest((FTDF_TransparentRequest *) msgBuf); - break; - - case FTDF_SLEEP_REQUEST: - FTDF_SLEEP_CALLBACK(((FTDF_SleepRequest *)msgBuf)->sleepTime); - FTDF_REL_MSG_BUFFER(msgBuf); - break; + case FTDF_TRANSPARENT_ENABLE_REQUEST: + ftdf_enable_transparent_mode(((ftdf_transparent_enable_request_t*)msg_buf)->enable, + ((ftdf_transparent_enable_request_t*)msg_buf)->options); + FTDF_REL_MSG_BUFFER(msg_buf); + break; + case FTDF_TRANSPARENT_REQUEST: + ftdf_process_transparent_request((ftdf_transparent_request_t*)msg_buf); + break; + case FTDF_SLEEP_REQUEST: + FTDF_SLEEP_CALLBACK(((ftdf_sleep_request_t*)msg_buf)->sleep_time); + FTDF_REL_MSG_BUFFER(msg_buf); + break; #ifndef FTDF_LITE - - case FTDF_REMOTE_REQUEST: - FTDF_processRemoteRequest((FTDF_RemoteRequest *)msgBuf); - break; + case FTDF_REMOTE_REQUEST: + ftdf_process_remote_request((ftdf_remote_request_t*)msg_buf); + break; #endif /* !FTDF_LITE */ #if FTDF_DBG_BUS_ENABLE - - case FTDF_DBG_MODE_SET_REQUEST: - FTDF_setDbgMode(((FTDF_DbgModeSetRequest *) msgBuf)->dbgMode); - FTDF_REL_MSG_BUFFER(msgBuf); - break; + case FTDF_DBG_MODE_SET_REQUEST: + ftdf_set_dbg_mode(((ftdf_dbg_mode_set_request_t *) msg_buf)->dbg_mode); + FTDF_REL_MSG_BUFFER(msg_buf); + break; #endif /* FTDF_DBG_BUS_ENABLE */ -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - - case FTDF_FPPR_MODE_SET_REQUEST: - FTDF_fpprSetMode(((FTDF_FpprModeSetRequest *) msgBuf)->matchFp, - ((FTDF_FpprModeSetRequest *) msgBuf)->fpOverride, - ((FTDF_FpprModeSetRequest *) msgBuf)->fpForce); - FTDF_REL_MSG_BUFFER(msgBuf); - break; -#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ - - default: - // Silenty release the message buffer - FTDF_REL_MSG_BUFFER(msgBuf); - break; - } + case FTDF_FPPR_MODE_SET_REQUEST: + ftdf_fppr_set_mode(((ftdf_fppr_mode_set_request_t *) msg_buf)->match_fp, + ((ftdf_fppr_mode_set_request_t *) msg_buf)->fp_override, + ((ftdf_fppr_mode_set_request_t *) msg_buf)->fp_force); + FTDF_REL_MSG_BUFFER(msg_buf); + break; + default: + // Silenty release the message buffer + FTDF_REL_MSG_BUFFER(msg_buf); + break; + } } -void FTDF_sendFrameTransparentConfirm(void *handle, - FTDF_Bitmap32 status) +void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status) { - FTDF_TransparentConfirm *confirm = - (FTDF_TransparentConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_TransparentConfirm)); + ftdf_transparent_confirm_t* confirm = + (ftdf_transparent_confirm_t*) FTDF_GET_MSG_BUFFER( + sizeof(ftdf_transparent_confirm_t)); - confirm->msgId = FTDF_TRANSPARENT_CONFIRM; - confirm->handle = handle; - confirm->status = status; + confirm->msg_id = FTDF_TRANSPARENT_CONFIRM; + confirm->handle = handle; + confirm->status = status; - FTDF_RCV_MSG((FTDF_MsgBuffer *) confirm); + FTDF_RCV_MSG((ftdf_msg_buffer_t*)confirm); } -void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength, - FTDF_Octet *frame, - FTDF_Bitmap32 status) +void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length, ftdf_octet_t *frame, + ftdf_bitmap32_t status, ftdf_link_quality_t link_quality) { - FTDF_TransparentIndication *indication = - (FTDF_TransparentIndication *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_TransparentIndication)); + ftdf_transparent_indication_t *indication = + (ftdf_transparent_indication_t*) FTDF_GET_MSG_BUFFER( + sizeof(ftdf_transparent_indication_t)); - indication->msgId = FTDF_TRANSPARENT_INDICATION; - indication->frameLength = frameLength; - indication->status = status; - indication->frame = FTDF_GET_DATA_BUFFER(frameLength); - memcpy(indication->frame, frame, frameLength); + indication->msg_id = FTDF_TRANSPARENT_INDICATION; + indication->frame_length = frame_length; + indication->status = status; + indication->frame = FTDF_GET_DATA_BUFFER(frame_length); + memcpy(indication->frame, frame, frame_length); - FTDF_RCV_MSG((FTDF_MsgBuffer *) indication); + FTDF_RCV_MSG((ftdf_msg_buffer_t*)indication); } #endif /* !FTDF_PHY_API */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c index f93cf972c..4a70afdab 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c @@ -35,337 +35,293 @@ #include #include #include "internal.h" -#include "regmap.h" +#include "sdk_defs.h" -static FTDF_PSec FTDF_lowPowerClockCycle __attribute__((section(".retention"))); -static FTDF_PSec FTDF_wakeUpLatency __attribute__((section(".retention"))); +#ifdef CONFIG_USE_FTDF +static ftdf_psec_t ftdf_low_power_clock_cycle __attribute__ ((section(".retention"))); +static ftdf_psec_t ftdf_wake_up_latency __attribute__ ((section(".retention"))); /* Pre-calculated value for optimization. */ -static FTDF_USec FTDF_lowPowerClockCycleUSec __attribute__((section(".retention"))); +static ftdf_usec_t ftdf_low_power_clock_cycle_u_sec __attribute__ ((section(".retention"))); /* Pre-calculated value for optimization. */ -static FTDF_USec FTDF_wakeUpLatencyUSec __attribute__((section(".retention"))); +static ftdf_usec_t ftdf_wake_up_latency_u_sec __attribute__ ((section(".retention"))); /* Pre-calculated value for optimization. */ -static FTDF_NrLowPowerClockCycles FTDF_csmacaWakeupThr __attribute__((section(".retention"))); +static ftdf_nr_low_power_clock_cycles_t ftdf_csmaca_wakeup_thr __attribute__ ((section(".retention"))); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -static uint32_t FTDF_eventCurrVal __attribute__((section(".retention"))); -static uint32_t FTDF_timeStampCurrVal __attribute__((section(".retention"))); -static uint32_t FTDF_timeStampCurrPhaseVal __attribute__((section(".retention"))); +static uint32_t ftdf_event_curr_val __attribute__ ((section(".retention"))); +static uint32_t ftdf_time_stamp_curr_val __attribute__ ((section(".retention"))); +static uint32_t ftdf_time_stamp_curr_phase_val __attribute__ ((section(".retention"))); #endif #ifndef FTDF_NO_CSL -FTDF_Boolean FTDF_wakeUpEnableLe __attribute__((section(".retention"))); +ftdf_boolean_t ftdf_wake_up_enable_le __attribute__ ((section(".retention"))); #endif /* FTDF_NO_CSL */ #ifndef FTDF_NO_TSCH -FTDF_Boolean FTDF_wakeUpEnableTsch; +ftdf_boolean_t ftdf_wake_up_enable_tsch; #endif /* FTDF_NO_TSCH */ -void FTDF_setSleepAttributes(FTDF_PSec lowPowerClockCycle, - FTDF_NrLowPowerClockCycles wakeUpLatency) +void ftdf_set_sleep_attributes(ftdf_psec_t low_power_clock_cycle, + ftdf_nr_low_power_clock_cycles_t wake_up_latency) { - FTDF_lowPowerClockCycle = lowPowerClockCycle; - FTDF_wakeUpLatency = (uint64_t)wakeUpLatency * lowPowerClockCycle; - FTDF_lowPowerClockCycleUSec = FTDF_lowPowerClockCycle / 1000000; - FTDF_wakeUpLatencyUSec = FTDF_wakeUpLatency / 1000000; - FTDF_csmacaWakeupThr = (FTDF_NrLowPowerClockCycles) - (((FTDF_PSec) 0xffffffff * 1000000 - FTDF_wakeUpLatency) / FTDF_lowPowerClockCycle); + ftdf_low_power_clock_cycle = low_power_clock_cycle; + ftdf_wake_up_latency = (ftdf_psec_t)wake_up_latency * low_power_clock_cycle; + ftdf_low_power_clock_cycle_u_sec = ftdf_low_power_clock_cycle / 1000000; + ftdf_wake_up_latency_u_sec = ftdf_wake_up_latency / 1000000; + ftdf_csmaca_wakeup_thr = (ftdf_nr_low_power_clock_cycles_t) + (((ftdf_psec_t) 0xffffffff * 1000000 - ftdf_wake_up_latency) / ftdf_low_power_clock_cycle); } -FTDF_USec FTDF_canSleep(void) +ftdf_usec_t ftdf_can_sleep(void) { #ifdef FTDF_PHY_API - - if (FTDF_txInProgress || FTDF_pib.keepPhyEnabled) - { - return 0; - } - + if (ftdf_tx_in_progress || ftdf_pib.keep_phy_enabled) { + return 0; + } #else #if FTDF_USE_SLEEP_DURING_BACKOFF - - if (FTDF_pib.keepPhyEnabled) + if (ftdf_pib.keep_phy_enabled) #else - if (FTDF_reqCurrent || FTDF_pib.keepPhyEnabled) + if (ftdf_req_current || ftdf_pib.keep_phy_enabled) #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - { - return 0; - } - + { + return 0; + } #endif #if FTDF_USE_SLEEP_DURING_BACKOFF - - if (FTDF_GET_FIELD(ON_OFF_REGMAP_SECBUSY) == 1) + if (REG_GETF(FTDF, FTDF_SECURITY_STATUS_REG, SECBUSY) == 1) #else /* FTDF_USE_SLEEP_DURING_BACKOFF */ - if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0 || - FTDF_GET_FIELD(ON_OFF_REGMAP_SECBUSY) == 1) + if ((REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) || + (REG_GETF(FTDF, FTDF_SECURITY_STATUS_REG, SECBUSY) == 1)) #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - { - return 0; - } + { + + return 0; + } #ifndef FTDF_NO_CSL - - if (FTDF_pib.leEnabled) - { + if (ftdf_pib.le_enabled) { #if FTDF_USE_SLEEP_DURING_BACKOFF - - /* Abort sleep when LMAC is busy. */ - if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) - { - return 0; - } - + /* Abort sleep when LMAC is busy. */ + if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) { + return 0; + } #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + if (ftdf_tx_in_progress == FTDF_FALSE) { + ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, + SYMBOLTIMESNAPSHOTVAL); + ftdf_time_t delta = cur_time - ftdf_start_csl_sample_time; - if (FTDF_txInProgress == FTDF_FALSE) - { - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_Time delta = curTime - FTDF_startCslSampleTime; + /* A delta larger than 0x80000000 is assumed to be negative */ + /* Do not return a sleep value when CSL sample time is in the past */ + if (delta < 0x80000000) { + return 0; + } - // A delta larger than 0x80000000 is assumed to be negative - // Do not return a sleep value when CSL sample time is in the past - if (delta < 0x80000000) - { - return 0; - } - - return (FTDF_startCslSampleTime - curTime) * 16; + return (ftdf_start_csl_sample_time - cur_time) * 16; + } else { + return 0; + } } - else - { - return 0; - } - } - #endif /* FTDF_NO_CSL */ #ifndef FTDF_NO_TSCH - - if (FTDF_pib.tschEnabled) - { + if (ftdf_pib.tsch_enabled) { #if FTDF_USE_SLEEP_DURING_BACKOFF - - /* Abort sleep when LMAC is busy. */ - if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) - { - return 0; - } - + /* Abort sleep when LMAC is busy. */ + if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) { + return 0; + } #endif - FTDF_Time64 curTime64 = FTDF_getCurTime64(); - FTDF_Time64 delta = curTime64 - FTDF_tschSlotTime; + ftdf_time64_t curTime64 = ftdf_get_cur_time64(); + ftdf_time64_t delta = curTime64 - ftdf_tsch_slot_time; - // A delta larger than 0x8000000000000000 is assumed to be negative - // Do not return a sleep value when TSCH slot time is in the past - if (delta < 0x8000000000000000ULL) - { - return 0; + /* A delta larger than 0x8000000000000000 is assumed to be negative */ + /* Do not return a sleep value when TSCH slot time is in the past */ + if (delta < 0x8000000000000000ULL) { + return 0; + } + + ftdf_usec_t sleep_time = (ftdf_usec_t)(ftdf_tsch_slot_time - curTime64); + + ftdf_time_t pend_list_time; + ftdf_time_t curTime = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); + ftdf_boolean_t pending = ftdf_get_tx_pending_timer_head(&pend_list_time); + + if (pending) { + /* A delta larger than 0x80000000 is assumed to be negative */ + /* Do not return a sleep value when pending timer time is in the past */ + if (curTime - pend_list_time < 0x80000000) { + return 0; + } + + ftdf_usec_t tmp_sleep_time = (ftdf_usec_t)(pend_list_time - curTime); + + if (tmp_sleep_time < sleep_time) { + sleep_time = tmp_sleep_time; + } + } + + if (sleep_time < FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME) { + return 0; + } + + return (sleep_time - (FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME)) * 16; } - - FTDF_USec sleepTime = (FTDF_USec)(FTDF_tschSlotTime - curTime64); - - FTDF_Time pendListTime; - FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); - FTDF_Boolean pending = FTDF_getTxPendingTimerHead(&pendListTime); - - if (pending) - { - // A delta larger than 0x80000000 is assumed to be negative - // Do not return a sleep value when pending timer time is in the past - if (curTime - pendListTime < 0x80000000) - { - return 0; - } - - FTDF_USec tmpSleepTime = (FTDF_USec)(pendListTime - curTime); - - if (tmpSleepTime < sleepTime) - { - sleepTime = tmpSleepTime; - } - } - - if (sleepTime < FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME) - { - return 0; - } - - return (sleepTime - (FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME)) * 16; - } - #endif /* FTDF_NO_TSCH */ #ifndef FTDF_LITE - // Normal mode - int n; + /* Normal mode */ + int n; - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) - { - if (FTDF_txPendingList[ n ].addrMode != FTDF_NO_ADDRESS) - { - return 0; + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { + if (ftdf_tx_pending_list[n].addr_mode != FTDF_NO_ADDRESS) { + return 0; + } } - } - #endif /* !FTDF_LITE */ #if FTDF_USE_SLEEP_DURING_BACKOFF - return FTDF_sdbGetSleepTime(); + return ftdf_sdb_get_sleep_time(); #else /* FTDF_USE_SLEEP_DURING_BACKOFF */ - return 0xffffffff; + return 0xffffffff; #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - } -FTDF_Boolean FTDF_prepareForSleep(FTDF_USec sleepTime) +ftdf_boolean_t ftdf_prepare_for_sleep(ftdf_usec_t sleep_time) { #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + if (sleep_time < (2 * ftdf_low_power_clock_cycle_u_sec)) { + return FTDF_FALSE; + } - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - if (sleepTime < 2 * FTDF_lowPowerClockCycleUSec) - { - return FTDF_FALSE; + // Correct sleeptime with the inaccuracy of this function + sleep_time -= (2 * ftdf_low_power_clock_cycle_u_sec); + + if (sleep_time < (ftdf_wake_up_latency_u_sec + 500)) { + return FTDF_FALSE; + } } - // Correct sleeptime with the inaccuracy of this function - sleepTime -= 2 * FTDF_lowPowerClockCycleUSec; - - if (sleepTime < FTDF_wakeUpLatencyUSec + 500) - { - return FTDF_FALSE; - } - } - #endif - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - // Capture the current value of both the event generator and the timestamp generator - // and phase on the rising edge of LP_CLK - FTDF_SET_FIELD(ON_OFF_REGMAP_GETGENERATORVAL, 1); + /* Capture the current value of both the event generator and the timestamp generator + and phase on the rising edge of LP_CLK */ + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, GETGENERATORVAL, 1); #endif - // Save current LMAC PM counters - FTDF_lmacCounters.fcsErrorCnt += FTDF_GET_FIELD(ON_OFF_REGMAP_MACFCSERRORCOUNT); - FTDF_lmacCounters.txStdAckCnt += FTDF_GET_FIELD(ON_OFF_REGMAP_MACTXSTDACKFRMCNT); - FTDF_lmacCounters.rxStdAckCnt += FTDF_GET_FIELD(ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT); + /* Save current LMAC PM counters */ + ftdf_lmac_counters.fcs_error_cnt += REG_GETF(FTDF, FTDF_MACFCSERRORCOUNT_REG, MACFCSERRORCOUNT); + ftdf_lmac_counters.tx_std_ack_cnt += REG_GETF(FTDF, FTDF_MACTXSTDACKFRMCNT_REG, MACTXSTDACKFRMCNT); + ftdf_lmac_counters.rx_std_ack_cnt += REG_GETF(FTDF, FTDF_MACRXSTDACKFRMOKCNT_REG, MACRXSTDACKFRMOKCNT); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - volatile uint32_t *getGeneratorValE = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_GETGENERATORVAL_E); - // Wait until data is ready - while ((*getGeneratorValE & MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E) == 0) - { } + /* Wait until data is ready */ + while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E) == 0) {} - FTDF_eventCurrVal = FTDF_GET_FIELD(ON_OFF_REGMAP_EVENTCURRVAL); - FTDF_timeStampCurrVal = FTDF_GET_FIELD(ON_OFF_REGMAP_TIMESTAMPCURRVAL); - FTDF_timeStampCurrPhaseVal = FTDF_GET_FIELD(ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL); + ftdf_event_curr_val = REG_GETF(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL); + ftdf_time_stamp_curr_val = REG_GETF(FTDF, FTDF_TIMESTAMPCURRVAL_REG, TIMESTAMPCURRVAL); + ftdf_time_stamp_curr_phase_val = REG_GETF(FTDF, FTDF_TIMESTAMPCURRPHASEVAL_REG, TIMESTAMPCURRPHASEVAL); #ifdef SIMULATOR - *getGeneratorValE &= ~MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E; + REG_CLR_FIELD(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E, FTDF->FTDF_LMAC_CONTROL_DELTA_REG); #else - *getGeneratorValE = MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E; + FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E); #endif - uint64_t nextWakeUpThr; + uint64_t next_wake_up_thr; #if FTDF_USE_SLEEP_DURING_BACKOFF - uint64_t picoSleepTime = (uint64_t)sleepTime * 1000000; - nextWakeUpThr = (picoSleepTime - FTDF_wakeUpLatency) / FTDF_lowPowerClockCycle; + uint64_t pico_sleep_time = (uint64_t)sleep_time * 1000000; + next_wake_up_thr = ( pico_sleep_time - ftdf_wake_up_latency ) / ftdf_low_power_clock_cycle; #else /* FTDF_USE_SLEEP_DURING_BACKOFF */ - - if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) - { - uint64_t picoSleepTime = (uint64_t)sleepTime * 1000000; - nextWakeUpThr = (picoSleepTime - FTDF_wakeUpLatency) / FTDF_lowPowerClockCycle; - } - else - { - nextWakeUpThr = FTDF_csmacaWakeupThr; - } - + if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { + uint64_t picoSleepTime = (uint64_t)sleep_time * 1000000; + next_wake_up_thr = (picoSleepTime - ftdf_wake_up_latency) / ftdf_low_power_clock_cycle; + } else { + next_wake_up_thr = ftdf_csmaca_wakeup_thr; + } #endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - // Set wake up threshold - uint32_t wakeUpIntThr = FTDF_eventCurrVal + nextWakeUpThr; - // Note that for IC revs other than A the size of WAKEUPINTTHR is 25 bits. - FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPINTTHR, wakeUpIntThr); - FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPENABLE, 1); + /* Set wake up threshold */ + uint32_t wake_up_int_thr = ftdf_event_curr_val + next_wake_up_thr; + /* Note that for IC revs other than A the size of WAKEUPINTTHR is 25 bits. */ + REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPINTTHR, wake_up_int_thr); + REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPENABLE, 1); #endif - FTDF_exitCritical(); + ftdf_exit_critical(); - return FTDF_TRUE; + return FTDF_TRUE; } -void FTDF_wakeUp(void) +void ftdf_wakeup(void) { #ifndef FTDF_PHY_API - FTDF_criticalVar(); - FTDF_enterCritical(); + ftdf_critical_var(); + ftdf_enter_critical(); - FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPENABLE, 0); + REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPENABLE, 0); #if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - // Capture the current value of both the event generator and the timestamp generator - // and phase on the rising edge of LP_CLK - FTDF_SET_FIELD(ON_OFF_REGMAP_GETGENERATORVAL, 1); + /* Capture the current value of both the event generator and the timestamp generator + and phase on the rising edge of LP_CLK */ + REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, GETGENERATORVAL, 1); - volatile uint32_t *getGeneratorValE = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_GETGENERATORVAL_E); + /* Wait until data is ready */ + while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E) == 0) {} - // Wait until data is ready - while ((*getGeneratorValE & MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E) == 0) - { } - - uint32_t eventNewCurrVal = FTDF_GET_FIELD(ON_OFF_REGMAP_EVENTCURRVAL); + uint32_t event_new_curr_val = REG_GETF(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL); #ifdef SIMULATOR - *getGeneratorValE &= ~MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E; + REG_CLR_FIELD(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E); #else - *getGeneratorValE = MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E; + FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E); #endif - // Backward calculate the time slept - //FTDF_PSec sleepTime = ( (uint64_t)( eventNewCurrVal - FTDF_eventCurrVal ) * FTDF_lowPowerClockCycle ) + FTDF_wakeUpLatency; + /* Backward calculate the time slept */ + /* ftdf_psec_t sleep_time = ((uint64_t)(event_new_curr_val - ftdf_event_curr_val) * + ftdf_low_power_clock_cycle) + ftdf_wake_up_latency; */ - FTDF_PSec sleepTime; + ftdf_psec_t sleep_time; + if (event_new_curr_val >= ftdf_event_curr_val) { /* Check for wraps. */ + sleep_time = (event_new_curr_val - ftdf_event_curr_val) * ftdf_low_power_clock_cycle + + ftdf_wake_up_latency; + } else { + sleep_time = (event_new_curr_val + + (REG_MSK(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL) - ftdf_event_curr_val)) * + ftdf_low_power_clock_cycle + ftdf_wake_up_latency; + } + /* Calculate sync values */ + uint64_t new_sync_vals = ((uint64_t)ftdf_time_stamp_curr_val << 8) | + (ftdf_time_stamp_curr_phase_val & 0xff); - if (eventNewCurrVal >= FTDF_eventCurrVal) /* Check for wraps. */ - { - sleepTime = (eventNewCurrVal - FTDF_eventCurrVal) * FTDF_lowPowerClockCycle + - FTDF_wakeUpLatency; - } - else - { - sleepTime = (eventNewCurrVal + - (MSK_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL - FTDF_eventCurrVal)) * - FTDF_lowPowerClockCycle + FTDF_wakeUpLatency; - } + new_sync_vals += (sleep_time / 62500) + 1; - // Calculate sync values - uint64_t newSyncVals = ((uint64_t)FTDF_timeStampCurrVal << 8) | (FTDF_timeStampCurrPhaseVal & 0xff); - newSyncVals += (sleepTime / 62500) + 1; + uint32_t sync_timestamp_thr = ftdf_event_curr_val + (sleep_time / ftdf_low_power_clock_cycle); + uint32_t sync_timestamp_val = (new_sync_vals & 0xffffffff00) >> 8; + uint32_t sync_timestamp_phase_val = (new_sync_vals & 0xff); - uint32_t syncTimestampThr = FTDF_eventCurrVal + (sleepTime / FTDF_lowPowerClockCycle); - uint32_t syncTimestampVal = (newSyncVals & 0xffffffff00) >> 8; - uint32_t syncTimestampPhaseVal = (newSyncVals & 0xff); - - // Set values - FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPTHR, syncTimestampThr); - FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPVAL, syncTimestampVal); - FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL, syncTimestampPhaseVal); - FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPENA, 1); + /* Set values */ + REG_SETF(FTDF, FTDF_SYNCTIMESTAMPTHR_REG, SYNCTIMESTAMPTHR, sync_timestamp_thr); + REG_SETF(FTDF, FTDF_SYNCTIMESTAMPVAL_REG, SYNCTIMESTAMPVAL, sync_timestamp_val); + REG_SETF(FTDF, FTDF_SYNCTIMESTAMPPHASEVAL_REG, SYNCTIMESTAMPPHASEVAL, sync_timestamp_phase_val); + REG_SETF(FTDF, FTDF_TIMER_CONTROL_1_REG, SYNCTIMESTAMPENA, 1); #endif - FTDF_exitCritical(); + ftdf_exit_critical(); #ifndef FTDF_NO_CSL - FTDF_wakeUpEnableLe = FTDF_pib.leEnabled; - FTDF_pib.leEnabled = FTDF_FALSE; + ftdf_wake_up_enable_le = ftdf_pib.le_enabled; + ftdf_pib.le_enabled = FTDF_FALSE; #endif /* FTDF_NO_CSL */ #ifndef FTDF_NO_TSCH - FTDF_wakeUpEnableTsch = FTDF_pib.tschEnabled; - FTDF_pib.tschEnabled = FTDF_FALSE; + ftdf_wake_up_enable_tsch = ftdf_pib.tsch_enabled; + ftdf_pib.tsch_enabled = FTDF_FALSE; #endif /* FTDF_NO_TSCH */ #endif /* ! FTDF_PHY_API */ - // Init LMAC - FTDF_initLmac(); + /* Init LMAC */ + ftdf_init_lmac(); } +#endif /* CONFIG_USE_FTDF */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h deleted file mode 100644 index 5e4503f81..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h +++ /dev/null @@ -1,8609 +0,0 @@ -//------------------------------------------------------------------------------ -// Created at 25.11.2014, 12:42 by mkregmap -// release: v2_42 (build date Oct 9 2014) -// options: -i ftdf_src.rgm -hdr -all -//------------------------------------------------------------------------------ -#ifndef _ftdf -#define _ftdf - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -/* - * - * REGISTER: ftdf_retention_ram_tx_fifo - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - ************************************************************************************ - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************** - */ -#define IND_R_FTDF_RETENTION_RAM_TX_FIFO 0x40080000 -#define SIZE_R_FTDF_RETENTION_RAM_TX_FIFO 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_FIFO 0xffffffff -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_1D 0x4 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_1D 0x80 -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_2D 0x20 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_2D 0x4 -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_1D 0x4 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_1D 0x80 -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_2D 0x20 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_2D 0x4 - -/* - * - * Field: ftdf_retention_ram_tx_fifo - * - * Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. - */ -#define IND_F_FTDF_RETENTION_RAM_TX_FIFO IND_R_FTDF_RETENTION_RAM_TX_FIFO -#define MSK_F_FTDF_RETENTION_RAM_TX_FIFO 0xffffffff -#define OFF_F_FTDF_RETENTION_RAM_TX_FIFO 0 -#define SIZE_F_FTDF_RETENTION_RAM_TX_FIFO 32 - -/* - * - * REGISTER: ftdf_retention_ram_tx_meta_data_0 - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x40080200 -#define SIZE_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x57ffffff -#define FTDF_RETENTION_RAM_TX_META_DATA_0_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_META_DATA_0_INTVL 0x10 -#define FTDF_RETENTION_RAM_FRAME_LENGTH_NUM 0x4 -#define FTDF_RETENTION_RAM_FRAME_LENGTH_INTVL 0x10 -#define FTDF_RETENTION_RAM_PHYATTR_NUM 0x4 -#define FTDF_RETENTION_RAM_PHYATTR_INTVL 0x10 -#define FTDF_RETENTION_RAM_FRAMETYPE_NUM 0x4 -#define FTDF_RETENTION_RAM_FRAMETYPE_INTVL 0x10 -#define FTDF_RETENTION_RAM_CSMACA_ENA_NUM 0x4 -#define FTDF_RETENTION_RAM_CSMACA_ENA_INTVL 0x10 -#define FTDF_RETENTION_RAM_ACKREQUEST_NUM 0x4 -#define FTDF_RETENTION_RAM_ACKREQUEST_INTVL 0x10 -#define FTDF_RETENTION_RAM_CRC16_ENA_NUM 0x4 -#define FTDF_RETENTION_RAM_CRC16_ENA_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_frame_length - * - * Frame length - */ -#define IND_F_FTDF_RETENTION_RAM_FRAME_LENGTH IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH 0x7f -#define OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH 0 -#define SIZE_F_FTDF_RETENTION_RAM_FRAME_LENGTH 7 -/* - * - * Field: ftdf_retention_ram_phyAttr - * - * During the RX-ON phase, the control register phyRxAttr[16] sources the PHYATTR output signal to the DPHY. - * This is also applicable during a CCA or Energy detect scan phase. - */ -#define IND_F_FTDF_RETENTION_RAM_PHYATTR IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_PHYATTR 0x7fff80 -#define OFF_F_FTDF_RETENTION_RAM_PHYATTR 7 -#define SIZE_F_FTDF_RETENTION_RAM_PHYATTR 16 -/* - * - * Field: ftdf_retention_ram_frametype - * - * Data/Cmd/Ack etc. Also indicate wakeup frame - */ -#define IND_F_FTDF_RETENTION_RAM_FRAMETYPE IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_FRAMETYPE 0x3800000 -#define OFF_F_FTDF_RETENTION_RAM_FRAMETYPE 23 -#define SIZE_F_FTDF_RETENTION_RAM_FRAMETYPE 3 -/* - * - * Bit: ftdf_retention_ram_CsmaCa_ena - * - * Indicates whether a CSMA-CA is required for the transmission of this packet. - */ -#define IND_F_FTDF_RETENTION_RAM_CSMACA_ENA IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_CSMACA_ENA 0x4000000 -#define OFF_F_FTDF_RETENTION_RAM_CSMACA_ENA 26 -#define SIZE_F_FTDF_RETENTION_RAM_CSMACA_ENA 1 -/* - * - * Bit: ftdf_retention_ram_AckRequest - * - * Indicates whether an acknowledge is expected from the recipient of this packet. - */ -#define IND_F_FTDF_RETENTION_RAM_ACKREQUEST IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_ACKREQUEST 0x10000000 -#define OFF_F_FTDF_RETENTION_RAM_ACKREQUEST 28 -#define SIZE_F_FTDF_RETENTION_RAM_ACKREQUEST 1 -/* - * - * Bit: ftdf_retention_ram_CRC16_ena - * - * Indicates whether CRC16 insertion must be enabled or not. - * 0 : No hardware inserted CRC16 - * 1 : Hardware inserts CRC16 - */ -#define IND_F_FTDF_RETENTION_RAM_CRC16_ENA IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_CRC16_ENA 0x40000000 -#define OFF_F_FTDF_RETENTION_RAM_CRC16_ENA 30 -#define SIZE_F_FTDF_RETENTION_RAM_CRC16_ENA 1 - -/* - * - * REGISTER: ftdf_retention_ram_tx_meta_data_1 - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0x40080204 -#define SIZE_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0xff -#define FTDF_RETENTION_RAM_TX_META_DATA_1_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_META_DATA_1_INTVL 0x10 -#define FTDF_RETENTION_RAM_MACSN_NUM 0x4 -#define FTDF_RETENTION_RAM_MACSN_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_macSN - * - * Sequence Number of this packet. - */ -#define IND_F_FTDF_RETENTION_RAM_MACSN IND_R_FTDF_RETENTION_RAM_TX_META_DATA_1 -#define MSK_F_FTDF_RETENTION_RAM_MACSN 0xff -#define OFF_F_FTDF_RETENTION_RAM_MACSN 0 -#define SIZE_F_FTDF_RETENTION_RAM_MACSN 8 - -/* - * - * REGISTER: ftdf_retention_ram_tx_return_status_0 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0x40080240 -#define SIZE_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0xffffffff -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_0_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_0_INTVL 0x10 -#define FTDF_RETENTION_RAM_TXTIMESTAMP_NUM 0x4 -#define FTDF_RETENTION_RAM_TXTIMESTAMP_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_TxTimestamp - * - * Transmit Timestamp - * The TimeStamp of the transmitted packet. - */ -#define IND_F_FTDF_RETENTION_RAM_TXTIMESTAMP IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 -#define MSK_F_FTDF_RETENTION_RAM_TXTIMESTAMP 0xffffffff -#define OFF_F_FTDF_RETENTION_RAM_TXTIMESTAMP 0 -#define SIZE_F_FTDF_RETENTION_RAM_TXTIMESTAMP 32 - -/* - * - * REGISTER: ftdf_retention_ram_tx_return_status_1 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x40080244 -#define SIZE_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x1f -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_1_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_1_INTVL 0x10 -#define FTDF_RETENTION_RAM_ACKFAIL_NUM 0x4 -#define FTDF_RETENTION_RAM_ACKFAIL_INTVL 0x10 -#define FTDF_RETENTION_RAM_CSMACAFAIL_NUM 0x4 -#define FTDF_RETENTION_RAM_CSMACAFAIL_INTVL 0x10 -#define FTDF_RETENTION_RAM_CSMACANRRETRIES_NUM 0x4 -#define FTDF_RETENTION_RAM_CSMACANRRETRIES_INTVL 0x10 - -/* - * - * Bit: ftdf_retention_ram_AckFail - * - * Acknowledgement status - * 0 : SUCCESS - * 1 : FAIL - */ -#define IND_F_FTDF_RETENTION_RAM_ACKFAIL IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 -#define MSK_F_FTDF_RETENTION_RAM_ACKFAIL 0x1 -#define OFF_F_FTDF_RETENTION_RAM_ACKFAIL 0 -#define SIZE_F_FTDF_RETENTION_RAM_ACKFAIL 1 -/* - * - * Bit: ftdf_retention_ram_CsmaCaFail - * - * CSMA-CA status - * 0 : SUCCESS - * 1 : FAIL - */ -#define IND_F_FTDF_RETENTION_RAM_CSMACAFAIL IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 -#define MSK_F_FTDF_RETENTION_RAM_CSMACAFAIL 0x2 -#define OFF_F_FTDF_RETENTION_RAM_CSMACAFAIL 1 -#define SIZE_F_FTDF_RETENTION_RAM_CSMACAFAIL 1 -/* - * - * Field: ftdf_retention_ram_CsmaCaNrRetries - * - * Number of CSMA-CA retries - */ -#define IND_F_FTDF_RETENTION_RAM_CSMACANRRETRIES IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 -#define MSK_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 0x1c -#define OFF_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 2 -#define SIZE_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 3 - -/* - * - * REGISTER: ftdf_retention_ram_rx_meta_0 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_RX_META_0 0x40080280 -#define SIZE_R_FTDF_RETENTION_RAM_RX_META_0 0x4 -#define MSK_R_FTDF_RETENTION_RAM_RX_META_0 0xffffffff -#define FTDF_RETENTION_RAM_RX_META_0_NUM 0x8 -#define FTDF_RETENTION_RAM_RX_META_0_INTVL 0x10 -#define FTDF_RETENTION_RAM_RX_TIMESTAMP_NUM 0x8 -#define FTDF_RETENTION_RAM_RX_TIMESTAMP_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_rx_timestamp - * - * Timestamp taken when frame was received - */ -#define IND_F_FTDF_RETENTION_RAM_RX_TIMESTAMP IND_R_FTDF_RETENTION_RAM_RX_META_0 -#define MSK_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 0xffffffff -#define OFF_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 0 -#define SIZE_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 32 - -/* - * - * REGISTER: ftdf_retention_ram_rx_meta_1 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_RX_META_1 0x40080284 -#define SIZE_R_FTDF_RETENTION_RAM_RX_META_1 0x4 -#define MSK_R_FTDF_RETENTION_RAM_RX_META_1 0xfffd -#define FTDF_RETENTION_RAM_RX_META_1_NUM 0x8 -#define FTDF_RETENTION_RAM_RX_META_1_INTVL 0x10 -#define FTDF_RETENTION_RAM_CRC16_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_CRC16_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_DPANID_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_DPANID_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_DADDR_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_DADDR_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_SPANID_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_SPANID_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_ISPANID_COORD_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_ISPANID_COORD_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_QUALITY_INDICATOR_NUM 0x8 -#define FTDF_RETENTION_RAM_QUALITY_INDICATOR_INTVL 0x10 - -/* - * - * Bit: ftdf_retention_ram_crc16_error - * - * CRC error, applicable for transparent mode only - */ -#define IND_F_FTDF_RETENTION_RAM_CRC16_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_CRC16_ERROR 0x1 -#define OFF_F_FTDF_RETENTION_RAM_CRC16_ERROR 0 -#define SIZE_F_FTDF_RETENTION_RAM_CRC16_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_res_frm_type_error - * - * Not supported frame type error, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 0x4 -#define OFF_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 2 -#define SIZE_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_res_frm_version_error - * - * Not supported frame version error, applicable when frame is not discarded. - */ -#define IND_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 0x8 -#define OFF_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 3 -#define SIZE_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_dpanid_error - * - * D PAN ID error, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_DPANID_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_DPANID_ERROR 0x10 -#define OFF_F_FTDF_RETENTION_RAM_DPANID_ERROR 4 -#define SIZE_F_FTDF_RETENTION_RAM_DPANID_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_daddr_error - * - * D Address error, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_DADDR_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_DADDR_ERROR 0x20 -#define OFF_F_FTDF_RETENTION_RAM_DADDR_ERROR 5 -#define SIZE_F_FTDF_RETENTION_RAM_DADDR_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_spanid_error - * - * PAN ID error, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_SPANID_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_SPANID_ERROR 0x40 -#define OFF_F_FTDF_RETENTION_RAM_SPANID_ERROR 6 -#define SIZE_F_FTDF_RETENTION_RAM_SPANID_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_ispanid_coord_error - * - * Received frame not for PAN coordinator, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 0x80 -#define OFF_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 7 -#define SIZE_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 1 -/* - * - * Field: ftdf_retention_ram_quality_indicator - * - * Link Quality Indication - * - * # $software_scratch@retention_ram - * # TX ram not used by hardware, can be used by software as scratch ram with retention. - */ -#define IND_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 0xff00 -#define OFF_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 8 -#define SIZE_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 8 - -/* - * - * REGISTER: ftdf_rx_ram_rx_fifo - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_RX_RAM_RX_FIFO 0x40088000 -#define SIZE_R_FTDF_RX_RAM_RX_FIFO 0x4 -#define MSK_R_FTDF_RX_RAM_RX_FIFO 0xffffffff -#define FTDF_RX_RAM_RX_FIFO_NUM_1D 0x8 -#define FTDF_RX_RAM_RX_FIFO_INTVL_1D 0x80 -#define FTDF_RX_RAM_RX_FIFO_NUM_2D 0x20 -#define FTDF_RX_RAM_RX_FIFO_INTVL_2D 0x4 -#define FTDF_RX_RAM_RX_FIFO_NUM_1D 0x8 -#define FTDF_RX_RAM_RX_FIFO_INTVL_1D 0x80 -#define FTDF_RX_RAM_RX_FIFO_NUM_2D 0x20 -#define FTDF_RX_RAM_RX_FIFO_INTVL_2D 0x4 - -/* - * - * Field: ftdf_rx_ram_rx_fifo - * - * Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. - */ -#define IND_F_FTDF_RX_RAM_RX_FIFO IND_R_FTDF_RX_RAM_RX_FIFO -#define MSK_F_FTDF_RX_RAM_RX_FIFO 0xffffffff -#define OFF_F_FTDF_RX_RAM_RX_FIFO 0 -#define SIZE_F_FTDF_RX_RAM_RX_FIFO 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_Rel_Name - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_REL_NAME 0x40090000 -#define SIZE_R_FTDF_ON_OFF_REGMAP_REL_NAME 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_REL_NAME 0xffffffff -#define FTDF_ON_OFF_REGMAP_REL_NAME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_REL_NAME_INTVL 0x4 -#define FTDF_ON_OFF_REGMAP_REL_NAME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_REL_NAME_INTVL 0x4 - -/* - * - * Field: ftdf_on_off_regmap_Rel_Name - * - * Name of the release - */ -#define IND_F_FTDF_ON_OFF_REGMAP_REL_NAME IND_R_FTDF_ON_OFF_REGMAP_REL_NAME -#define MSK_F_FTDF_ON_OFF_REGMAP_REL_NAME 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_REL_NAME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_REL_NAME 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_BuildTime - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0x40090010 -#define SIZE_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0xffffffff -#define FTDF_ON_OFF_REGMAP_BUILDTIME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_BUILDTIME_INTVL 0x4 -#define FTDF_ON_OFF_REGMAP_BUILDTIME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_BUILDTIME_INTVL 0x4 - -/* - * - * Field: ftdf_on_off_regmap_BuildTime - * - * Build time of device - */ -#define IND_F_FTDF_ON_OFF_REGMAP_BUILDTIME IND_R_FTDF_ON_OFF_REGMAP_BUILDTIME -#define MSK_F_FTDF_ON_OFF_REGMAP_BUILDTIME 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_BUILDTIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_BUILDTIME 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_0 - * - * Initialization value: 0xff00 Initialization mask: 0x6ff0e - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x40090020 -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x6ff0e - -/* - * - * Bit: ftdf_on_off_regmap_IsPANCoordinator - * - * Enable/disable receiver check on address - * fields (0=enabled, 1=disabled) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_dma_req - * - * Source of the RX_DMA_REQ output of this block. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 1 -/* - * - * Bit: ftdf_on_off_regmap_tx_dma_req - * - * Source of the TX_DMA_REQ output of this block. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 1 -/* - * - * Field: ftdf_on_off_regmap_macSimpleAddress - * - * Simple address of the PAN coordinator - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 8 -/* - * - * Bit: ftdf_on_off_regmap_macLEenabled - * - * If set, Low Energy mode is enabled - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACLEENABLED IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 0x20000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 17 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 1 -/* - * - * Bit: ftdf_on_off_regmap_macTSCHenabled - * - * If set, TSCH mode is enabled - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 0x40000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 18 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_1 - * - * Initialization value: 0xffffffff Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0x40090024 -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macPANId - * - * The values 0xFFFF indicates that the device - * is not associated - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACPANID IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACPANID 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACPANID 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACPANID 16 -/* - * - * Field: ftdf_on_off_regmap_macShortAddress - * - * The values 0xFFFF and 0xFFFE indicate - * that no IEEE Short Address is available. - * The latter one is used if the device i - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_2 - * - * Initialization value: 0xffffffff Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0x40090028 -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_aExtendedAddress_l - * - * Unique device address, lower 32 bit - */ -#define IND_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_3 - * - * Initialization value: 0xffffffff Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0x4009002c -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_aExtendedAddress_h - * - * Unique device address, higher 16 bit - */ -#define IND_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_0 - * - * Initialization value: 0x0 Initialization mask: 0xfbfffffe - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0x40090030 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0xfbfffffe - -/* - * - * Field: ftdf_on_off_regmap_RxonDuration - * - * Time the Rx must be on - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXONDURATION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXONDURATION 0x1fffffe -#define OFF_F_FTDF_ON_OFF_REGMAP_RXONDURATION 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXONDURATION 24 -/* - * - * Bit: ftdf_on_off_regmap_RxAlwaysOn - * - * If set, the receiver shall be always on if - * RxEnable is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXALWAYSON IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 0x2000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 25 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 1 -/* - * - * Field: ftdf_on_off_regmap_pti - * - * Info to arbiter if phy_en is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PTI IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_PTI 0x78000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PTI 27 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PTI 4 -/* - * - * Bit: ftdf_on_off_regmap_keep_phy_en - * - * When the transmit or receive action is ready (LmacReady4Sleep will is set), the phy_en signal is cleared unless the control register keep_phy_en is set. - * When the control register keep_phy_en is set, the signal phy_en shall remain being set until the keep_phy_en is cleared. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 0x80000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 31 -#define SIZE_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_TxPipePropDelay - * - * Initialization value: 0x0 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0x40090034 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0xff - -/* - * - * Field: ftdf_on_off_regmap_TxPipePropDelay - * - * Prop delay of tx pipe, start to DPHY - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY IND_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY -#define MSK_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_MacAckWaitDuration - * - * Initialization value: 0x36 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0x40090038 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0xff - -/* - * - * Field: ftdf_on_off_regmap_MacAckWaitDuration - * - * Max time to wait for a (normal) ACK - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION IND_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION -#define MSK_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_MacEnhAckWaitDuration - * - * Initialization value: 0x360 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0x4009003c -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0xffff - -/* - * - * Field: ftdf_on_off_regmap_MacEnhAckWaitDuration - * - * The maximum time (in ??s) to wait for an - * enhanced acknowledgement frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION IND_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION -#define MSK_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_1 - * - * Initialization value: 0x0 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0x40090040 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0xffff - -/* - * - * Field: ftdf_on_off_regmap_phyRxAttr - * - * phyattr to DPHY during Rx operation - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffff01 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0x40090044 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0xffffff01 - -/* - * - * Bit: ftdf_on_off_regmap_EdScanEnable - * - * if set, Energy Detect scan will be done - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 1 -/* - * - * Field: ftdf_on_off_regmap_EdScanDuration - * - * Length of ED scan - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 0xffffff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 24 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_3 - * - * Initialization value: 0x4c4 Initialization mask: 0xffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0x40090048 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0xffffff - -/* - * - * Field: ftdf_on_off_regmap_macMaxFrameTotalWaitTime - * - * Max time to wait for a requested Data Frame or an announced broadcast frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 16 -/* - * - * Field: ftdf_on_off_regmap_CcaIdleWait - * - * Time to wait after CCA returned "medium idle" before starting TX-ON (in us). - * Note: not applicable in TSCH mode since there macTSRxTx shall be used. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_os - * - * Initialization value: 0x0 Initialization mask: 0x7 - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x40090050 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x7 - -/* - * - * Bit: ftdf_on_off_regmap_getGeneratorVal - * - * If set, the current values of WU gen and TS gen will be captured. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 1 -/* - * - * Bit: ftdf_on_off_regmap_RxEnable - * - * If set, receiving data may be done - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_RXENABLE 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXENABLE 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXENABLE 1 -/* - * - * Bit: ftdf_on_off_regmap_SingleCCA - * - * If set, a single CCA will be performed. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SINGLECCA IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_SINGLECCA 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_SINGLECCA 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SINGLECCA 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0x40090054 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0xff46 - -/* - * - * Bit: ftdf_on_off_regmap_LmacReady4sleep - * - * Indicates that the LMAC is ready to go to sleep. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 1 -/* - * - * Bit: ftdf_on_off_regmap_CCAStat - * - * Value single CCA when CCAstat_e is set. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT 1 -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus - * - * Status of WakeupTimerEnable after being clocked by LP_CLK (showing it's effective value). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 1 -/* - * - * Field: ftdf_on_off_regmap_EdScanValue - * - * Result of ED scan. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_EventCurrVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x40090058 -#define SIZE_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_EventCurrVal - * - * Value of captured Event generator - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL IND_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_TimeStampCurrVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0x4009005c -#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_TimeStampCurrVal - * - * Value of captured TS gen - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_TimeStampCurrPhaseVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0x40090074 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0xff - -/* - * - * Field: ftdf_on_off_regmap_TimeStampCurrPhaseVal - * - * Value of captured TS gen phase within a symbol - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_macTSTxAckDelayVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0x40090078 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0xffff - -/* - * - * Field: ftdf_on_off_regmap_macTSTxAckDelayVal - * - * The time in us left until the ack frame is sent by the lmac - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL IND_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_4 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0x40090060 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_phySleepWait - * - * Time between negate and assert PHY_EN - * When the signal phy_en is deasserted, it will not be asserted within the time phySleepWait. - * This time is indicated by the control register phySleepWait (resolution: ~s). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 8 -/* - * - * Field: ftdf_on_off_regmap_RxPipePropDelay - * - * The control register RxPipePropDelay indicates the propagation delay in ~s of the Rx pipeline between the last symbol being captured at the DPHY interface and the "data valid" indication to the LMAC controller. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 8 -/* - * - * Field: ftdf_on_off_regmap_phyAckAttr - * - * During transmission of an ACK frame, phyAckAttr is used as phyAttr on the DPHY interface. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYACKATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_5 - * - * Initialization value: 0x8c0 Initialization mask: 0xffff0fff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0x40090064 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0xffff0fff - -/* - * - * Field: ftdf_on_off_regmap_Ack_Response_Delay - * - * In order to have some flexibility the control register Ack_Response_Delay indicates the Acknowledge response time in ~s. - * The default value shall is 192 ~s (12 symbols). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 -#define MSK_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 8 -/* - * - * Field: ftdf_on_off_regmap_CcaStatWait - * - * The output CCASTAT is valid after 8 symbols + phyRxStartup. - * The 8 symbols are programmable by control registerCcaStatWait[4] in symbol timesl. - * Default value is 8d. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 4 -/* - * - * Field: ftdf_on_off_regmap_phyCsmaCaAttr - * - * The control register phyCsmaCaAttr is used to source PHYATT on the DPHY interface. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_6 - * - * Initialization value: 0xc0c28 Initialization mask: 0xffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0x40090068 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0xffffff - -/* - * - * Field: ftdf_on_off_regmap_LifsPeriod - * - * The LIFS period is programmable by LifsPeriod (in symbols). - * The default is 40 symbols (640 ~s), - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 -#define MSK_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 8 -/* - * - * Field: ftdf_on_off_regmap_SifsPeriod - * - * The SIFS period is programmable by SifsPeriod (in symbols). - * The default is 12 symbols (192 ~s). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 -#define MSK_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 8 -/* - * - * Field: ftdf_on_off_regmap_WUifsPeriod - * - * The WakeUp IFS period is programmable by WUifsPeriod (in symbols). - * The default is 12 symbols (192 ~s). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 -#define MSK_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_11 - * - * Initialization value: 0x0 Initialization mask: 0x1ffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0x4009006c -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0x1ffff - -/* - * - * Field: ftdf_on_off_regmap_macRxTotalCycleTime - * - * In order to make it easier to calculate if it is efficient to disable and enable the PHY Rx until the RZ time is reached, a control register indicates the time needed to disable and enable the PHY Rx: macRxTotalCycleTime (resolution in 10 sym) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 16 -/* - * - * Bit: ftdf_on_off_regmap_macDisCaRxOfftoRZ - * - * This switching off and on of the PHY Rx can be disabled whith the control register macDisCaRxOfftoRZ. - * 0 : Disabled - * 1 : Enabled - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 0x10000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_delta - * - * Initialization value: 0x0 Initialization mask: 0x7e - * Access mode: D-RCW (delta read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x40090070 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x7e - -/* - * - * Bit: ftdf_on_off_regmap_LmacReady4sleep_d - * - * Delta bit for register "LmacReady4sleep" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 1 -/* - * - * Bit: ftdf_on_off_regmap_SyncTimeStamp_e - * - * The SyncTimeStamp_e event is set when the TimeStampgenerator is loaded with SyncTimeStampVal. - * This occurs at the rising edge of lp_clk when SyncTimeStampEna is set and the value of the Event generator is equal to the value SyncTimestampThr. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTimeThr_e - * - * Event that symboltime counter matched SymbolTimeThr - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTime2Thr_e - * - * Event that symboltime counter matched SymbolTime2Thr - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 1 -/* - * - * Bit: ftdf_on_off_regmap_getGeneratorVal_e - * - * Event which indicates that WakeupTimerEnableStatus has changed - */ -#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 0x20 -#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 5 -#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 1 -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus_d - * - * Delta which indicates the getGeneratorVal request is completed - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_mask - * - * Initialization value: 0x0 Initialization mask: 0x7e - * Access mode: DM-RW (delta mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x40090080 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x7e - -/* - * - * Bit: ftdf_on_off_regmap_LmacReady4sleep_m - * - * Mask bit for delta bit "LmacReady4sleep_d" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 1 -/* - * - * Bit: ftdf_on_off_regmap_SyncTimeStamp_m - * - * Mask bit for event register SyncTimeStamp_e. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTimeThr_m - * - * Mask for SymbolTimeThr_e - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTime2Thr_m - * - * Mask for SymbolTime2Thr_e - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 1 -/* - * - * Bit: ftdf_on_off_regmap_getGeneratorVal_m - * - * Mask for getGeneratorVal_e - */ -#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 0x20 -#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 5 -#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 1 -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus_m - * - * Mask for WakeupTimerEnableStatus_d - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_event - * - * Initialization value: 0x0 Initialization mask: 0x7 - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0x40090090 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0x7 - -/* - * - * Bit: ftdf_on_off_regmap_EdScanReady_e - * - * The event EdScanReady_e is set to notify that the ED scan is ready. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 1 -/* - * - * Bit: ftdf_on_off_regmap_CCAstat_e - * - * If set, the single CCA is ready - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 1 -/* - * - * Bit: ftdf_on_off_regmap_RxTimerExpired_e - * - * Set if one of the timers enabling the RX-ON mode expires without having received any valid frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_mask - * - * Initialization value: 0x0 Initialization mask: 0x7 - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0x40090094 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0x7 - -/* - * - * Bit: ftdf_on_off_regmap_EdScanReady_m - * - * Mask bit for event "EdScanReady_e" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 1 -/* - * - * Bit: ftdf_on_off_regmap_CCAstat_m - * - * Mask bit for event "CCAstat_e" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 1 -/* - * - * Bit: ftdf_on_off_regmap_RxTimerExpired_m - * - * Mask bit for event "RxTimerExpired_e" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_manual_1 - * - * Initialization value: 0x0 Initialization mask: 0xffff0fff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0x400900a0 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0xffff0fff - -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_mode - * - * If the control register lmac_manual_mode is set, the LMAC controller control - * signals should be controlled by the lmac_manual_control registers - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_phy_en - * - * lmac_manual_phy_en controls the PHY_EN interface signal when lmac_manual_mode is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_tx_en - * - * lmac_manual_tx_en controls the TX_EN interface signal when lmac_manual_mode is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_rx_en - * - * lmac_manual_rx_en controls the RX_EN interface signal when lmac_manual_mode is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_rx_pipe_en - * - * lmac_manual_rx_pipe_en controls the rx_enable signal towards the rx pipeline when lmac_manual_mode is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_ed_request - * - * lmac_manual_ed_request controls the ED_REQUEST interface signal when lmac_manual_mode is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 0x20 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 5 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 1 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_tx_frm_nr - * - * lmac_manual_tx_frm_nr controls the entry in the tx buffer to be transmitted. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 0xc0 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 2 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_pti - * - * lmac_manual_pti controls the PTI interface signal when lmac_manual_mode is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 4 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_phy_attr - * - * lmac_manual_phy_attr controls the PHY_ATTR interface signal when lmac_manual_mode is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_manual_os - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x400900a4 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_tx_start - * - * One shot register which triggers the transmission of a frame from the tx buffer in lmac_manual_mode - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_manual_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0x400900a8 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0xff01 - -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_cca_stat - * - * lmac_manual_cca_stat shows the status of the CCA_STAT - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 1 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_ed_stat - * - * lmac_manual_ed_stat shows the status of the ED_STAT interface signal. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_7 - * - * Initialization value: 0x420000 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0x40090100 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macWUPeriod - * - * Wake-up duration in symbols. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 16 -/* - * - * Field: ftdf_on_off_regmap_macCSLsamplePeriod - * - * When performing a idle listening, the receiver is enabled for at least macCSLsamplePeriod (in symbols). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_8 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0x40090104 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macCSLstartSampleTime - * - * The control register macCSLstartSampleTime indicates the TimeStamp generator time (in symbols) when to start listening (called "idle listening"). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_9 - * - * Initialization value: 0x42 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0x40090108 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macCSLdataPeriod - * - * After the wake-up sequence a frame is expected, the receiver will be enabled for at least a period of macCSLdataPeriod (in symbols). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 16 -/* - * - * Field: ftdf_on_off_regmap_macCSLFramePendingWaitT - * - * If a non Wake-up frame with Frame Pending bit = '1' is received, the receiver is enabled for at least an extra period of macCSLFramePendingWaitT (in symbols) after the end of the received frame. - * The time the Enhanced ACK transmission lasts (if applicable) is included in this time. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_10 - * - * Initialization value: 0x20000000 Initialization mask: 0xf00f00ff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0x4009010c -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0xf00f00ff - -/* - * - * Field: ftdf_on_off_regmap_macRZzeroVal - * - * If the current RZtime is less or Equal to macRZzeroVal an RZtime with value zero is inserted in the wakeup frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 0xf0000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 28 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 4 -/* - * - * Field: ftdf_on_off_regmap_macCSLmarginRZ - * - * The UMAC can set the margin for the expected frame by control register macCSLmarginRZ (in 10 sym). - * So the LMAC will make sure the receiver is ready to receive data this amount of time earlier than to be expected by the received RZ time - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 0xf0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 4 -/* - * - * Field: ftdf_on_off_regmap_macWURZCorrection - * - * This register shall be used if the Wake-up frame to be transmitted is larger than 15 octets. - * It shall indicate the amount of extra data in a Wake-up frame after the RZ position in the frame (in 10 sym). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_0 - * - * Initialization value: 0x0 Initialization mask: 0xff7f0f02 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0x40090110 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0xff7f0f02 - -/* - * - * Bit: ftdf_on_off_regmap_secTxRxn - * - * See register "secEntry" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECTXRXN IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECTXRXN 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECTXRXN 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECTXRXN 1 -/* - * - * Field: ftdf_on_off_regmap_secEntry - * - * The UMAC shall indicate by control registers secEntry and secTxRxn which entry to use and if it's from the Tx or Rx buffer ('1' resp. '0'). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECENTRY IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECENTRY 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECENTRY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENTRY 4 -/* - * - * Field: ftdf_on_off_regmap_secAlength - * - * The length of the a_data is indicated by control register secAlength. - * The end of the a_data is the start point of the m_data. (So secAlength must also be set if security level==4) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECALENGTH IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECALENGTH 0x7f0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECALENGTH 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECALENGTH 7 -/* - * - * Field: ftdf_on_off_regmap_secMlength - * - * The length of the m_data is indicated by control register secMlength. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECMLENGTH IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 0x7f000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 7 -/* - * - * Bit: ftdf_on_off_regmap_secEncDecn - * - * The control register secEncDecn indicates whether to encrypt ('1') or decrypt ('0') the data. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECENCDECN IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECENCDECN 0x80000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECENCDECN 31 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENCDECN 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_1 - * - * Initialization value: 0x0 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0x40090114 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0xffff - -/* - * - * Field: ftdf_on_off_regmap_secAuthFlags - * - * Register secAuthFlags contains the authentication flags fields. - * bit[7] is '0' - * bit[6] is "A_data present" - * bit[5:3]: 3-bit security level of m_data - * bit[2:0]: 3-bit security level of a_data. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 8 -/* - * - * Field: ftdf_on_off_regmap_secEncrFlags - * - * Register secEncrFlags contain the encryption flags field. - * Bits [2:0] are the 3-bit encoding flags of a_data, the other bits msut be set to '0'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_0 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0x40090118 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_0 - * - * Registers secKey[0..3] contain the key to be used. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_0 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_0 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_0 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_1 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0x4009011c -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_1 - * - * See register "secKey_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_1 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_1 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_1 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_1 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0x40090120 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_2 - * - * See register "secKey_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_2 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_2 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_2 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_2 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_3 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0x40090124 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_3 - * - * See register "secKey_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_3 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_3 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_3 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_3 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_0 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0x40090128 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_0 - * - * Register secNonce[0..3] contains the Nonce to be used for encryption/decryption. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_1 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0x4009012c -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_1 - * - * See register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0x40090130 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_2 - * - * See register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_3 - * - * Initialization value: 0x0 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0x40090134 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0xff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_3 - * - * See register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_os - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x40090138 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_secAbort - * - * See register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECABORT IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECABORT 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECABORT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECABORT 1 -/* - * - * Bit: ftdf_on_off_regmap_secStart - * - * One_shot register to start the encryption, decryption and authentication support task. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECSTART IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECSTART 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECSTART 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECSTART 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x40090140 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_secBusy - * - * Register "secBusy" indicates if the encryption/decryption process is still running. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECBUSY IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECBUSY 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECBUSY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECBUSY 1 -/* - * - * Bit: ftdf_on_off_regmap_secAuthFail - * - * In case of decryption, the status bit secAuthFail will be set when the authentication has failed. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_event - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x40090150 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_secReady_e - * - * The Event bit secReady_e is set when the authentication process is ready (i.e. secBusy is cleared). - * This Event shall contribute to the gen_irq. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECREADY_E IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_SECREADY_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECREADY_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECREADY_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_eventmask - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x40090154 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_secReady_m - * - * Mask bit for event "secReady_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECREADY_M IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SECREADY_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECREADY_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECREADY_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tsch_control_0 - * - * Initialization value: 0x89803e8 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0x40090160 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macTSTxAckDelay - * - * End of Rx frame to start of Ack - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 16 -/* - * - * Field: ftdf_on_off_regmap_macTSRxWait - * - * The times to wait for start of frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_tsch_control_1 - * - * Initialization value: 0xc0 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0x40090164 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0xffff - -/* - * - * Field: ftdf_on_off_regmap_macTSRxTx - * - * The time between the CCA and the TX of a frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXTX IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_tsch_control_2 - * - * Initialization value: 0x1900320 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0x40090168 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macTSRxAckDelay - * - * End of frame to when the transmitter shall listen for Acknowledgement - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 16 -/* - * - * Field: ftdf_on_off_regmap_macTSAckWait - * - * The minimum time to wait for start of an Acknowledgement - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_0 - * - * Initialization value: 0x76543210 Initialization mask: 0x77777777 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x40090180 -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x77777777 - -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_0 - * - * Control rxBitPos(8)(3) controls the position that a bit should have at the DPHY interface. - * So the default values are rxBitPos_0 = 0, rxBitPos_1 = 1, rxBitPos_2 = 2, etc. - * - * Note1 that this is a conversion from rx DPHY interface to the internal data byte - * So - * for(n=7;n>=0;n--) - * rx_data(n) = dphy_bit(tx_BitPos(n)) - * endfor - * - * Note2 that rxBitPos and txBitPos must have inverse functions. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 0x7 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_1 - * - * See rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 0x70 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_2 - * - * See rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 0x700 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_3 - * - * See rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 0x7000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_4 - * - * See rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 0x70000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_5 - * - * See rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 0x700000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 20 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_6 - * - * See rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 0x7000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_7 - * - * See rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 0x70000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 28 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 3 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_1 - * - * Initialization value: 0x76543210 Initialization mask: 0x77777777 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x40090184 -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x77777777 - -/* - * - * Field: ftdf_on_off_regmap_txBitPos_0 - * - * Control txBitPos(8)(3) controls the position that a bit should have at the DPHY interface. - * So the default values are txBitPos_0 = 0, txBitPos_1 = 1, txBitPos_2 = 2, etc. - * - * Note1 that this is a conversion from internal data byte to the DPHY interface. - * So - * for(n=7;n>=0;n--) - * tx_dphy_bit(n) = tx_data(tx_BitPos(n)) - * endfor - * - * Note2 that txBitPos and rxBitPos must have inverse functions. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 0x7 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_1 - * - * See txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 0x70 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_2 - * - * See txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 0x700 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_3 - * - * See txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 0x7000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_4 - * - * See txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 0x70000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_5 - * - * See txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 0x700000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 20 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_6 - * - * See txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 0x7000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_7 - * - * See txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 0x70000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 28 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 3 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0x40090188 -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_phyTxStartup - * - * Phy wait time before transmission - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 8 -/* - * - * Field: ftdf_on_off_regmap_phyTxLatency - * - * Phy delay between DPHY i/f and air - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 8 -/* - * - * Field: ftdf_on_off_regmap_phyTxFinish - * - * Phy wait time before deasserting TX_EN - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 8 -/* - * - * Field: ftdf_on_off_regmap_phyTRxWait - * - * Phy wait time between TX_EN/RX_EN - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 0xff000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_3 - * - * Initialization value: 0x0 Initialization mask: 0xffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x4009018c -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0xffffff - -/* - * - * Field: ftdf_on_off_regmap_phyRxStartup - * - * Phy wait time before receiving - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 8 -/* - * - * Field: ftdf_on_off_regmap_phyRxLatency - * - * Phy delay between air and DPHY i/f - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 8 -/* - * - * Field: ftdf_on_off_regmap_phyEnable - * - * Asserting the DPHY interface signals TX_EN or RX_EN does not take place within the time phyEnable after asserting the signal phy_en. - * (resolution: ~s). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYENABLE IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYENABLE 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYENABLE 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYENABLE 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_control_0 - * - * Initialization value: 0x0 Initialization mask: 0xfffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0x40090200 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0xfffffff - -/* - * - * Bit: ftdf_on_off_regmap_DbgRxTransparentMode - * - * If set, Rx pipe is fully set in transparent mode (for debug purpose). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 1 -/* - * - * Bit: ftdf_on_off_regmap_RxBeaconOnly - * - * If set, only Beacons frames are accepted - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 1 -/* - * - * Bit: ftdf_on_off_regmap_RxCoordRealignOnly - * - * If set, only Coordinator Realignment frames are accepted - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 1 -/* - * - * Field: ftdf_on_off_regmap_rx_read_buf_ptr - * - * Indication where new data will be read - * All four bits shall be used when using these pointer values (0d - 15d). - * However, the Receive Packet buffer has a size of 8 entries. - * So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 0x78 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 4 -/* - * - * Bit: ftdf_on_off_regmap_DisRxFrmPendingca - * - * Whan the control register DisRxFrmPendingCa is set, the notification of the received FP bit to the LMAC Controller is disabled. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 0x80 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 7 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 1 -/* - * - * Bit: ftdf_on_off_regmap_DisRxAckRequestca - * - * When the control register DisRxAckRequestca is set all consequent actions for a received Acknowledge Request bit are disabled. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 0x100 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassCrcerror - * - * If set, a FCS error will not drop the frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 0x200 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 9 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 1 -/* - * - * Bit: ftdf_on_off_regmap_DisDataRequestca - * - * When the control register DisDataRequestCa is set, the notification of the received Data Request is disabled. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 0x400 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 10 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassResFrameVersion - * - * If set, a packet with a reserved FrameVersion shall not be dropped - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 0x800 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 11 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassWrongDPANId - * - * If register macAlwaysPassWrongDPANId is set, packet with a wrong Destiantion PanID will not be dropped. - * However, in case of an FCS error, the packet is dropped. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 0x1000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassWrongDAddr - * - * If set, a packet with a wrong DAddr is not dropped - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 0x2000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 13 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassBeaconWrongPANId - * - * If the control register macAlwaysPassBeaconWrongPANId is set, the frame is not dropped in case of a mismatch in PAN-ID, irrespective of the setting of RxBeaconOnly. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 0x4000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 14 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassToPanCoordinator - * - * When the control register macAlwaysPassToPanCoordinator is set, the frame is not dropped due to a span_coord_error. - * However, in case of an FCS error, the packet is dropped. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 0x8000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 15 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 1 -/* - * - * Field: ftdf_on_off_regmap_macAlwaysPassFrmType - * - * The control registers macAlwaysPassFrmType[7:0], shall control if this Frame Type shall be dropped. - * If a bit is set, the Frame Type corresponding with the bit position is not dropped, even in case of a CRC error. - * Example: if bit 1 is set, Frame Type 1 shall not be dropped. - * The error shall be reported in the Rx meta data - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 8 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassWakeUp - * - * If the control register macAlwaysPassWakeUp is set, received Wake- up frames for this device are put into the Rx packet buffer without notifying the LMAC Controller. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 0x1000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 1 -/* - * - * Bit: ftdf_on_off_regmap_macPassWakeUp - * - * If set, WakeUp frames will not be reported but will be put into the Rx buffer. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 0x2000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 25 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 1 -/* - * - * Bit: ftdf_on_off_regmap_macImplicitBroadcast - * - * If set, Frame Version 2 frames without Daddr or DPANId shall be accepted. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 0x4000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 26 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 1 -/* - * - * Bit: ftdf_on_off_regmap_DisRxAckReceivedca - * - * If set, the LMAC controller shall ignore all consequent actions upon a set AR bit in the transmitted frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 0x8000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 27 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_event - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: E-RCW2 (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0x40090204 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0xf - -/* - * - * Bit: ftdf_on_off_regmap_RxSof_e - * - * Set when RX_SOF has been detected. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXSOF_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXSOF_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXSOF_E 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_overflow_e - * - * Indicates that the Rx packet buffer has an - * overflowl - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_buf_avail_e - * - * Indicates that a new packet is received - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 1 -/* - * - * Bit: ftdf_on_off_regmap_rxbyte_e - * - * Indicates the first byte of a new packet is received - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBYTE_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_mask - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_MASK 0x40090208 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_MASK 0xf - -/* - * - * Bit: ftdf_on_off_regmap_RxSof_m - * - * Mask bit for event "RxSof_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXSOF_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXSOF_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXSOF_M 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_overflow_m - * - * Mask bit for event " rx_overflow_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_buf_avail_m - * - * Mask bit for event "rx_buf_avail_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 1 -/* - * - * Bit: ftdf_on_off_regmap_rxbyte_m - * - * Mask bit for event "rxbyte_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBYTE_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x4009020c -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x1f - -/* - * - * Bit: ftdf_on_off_regmap_rx_buff_is_full - * - * Indicates that the Rx packet buffer is full - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 1 -/* - * - * Field: ftdf_on_off_regmap_rx_write_buf_ptr - * - * Indication where new data will be written. - * All four bits shall be used when using these pointer values (0d - 15d). - * However, the Receive Packet buffer has a size of 8 entries. - * So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 0x1e -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 4 - -/* - * - * REGISTER: ftdf_on_off_regmap_SymbolTimeSnapshotVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0x40090210 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SymbolTimeSnapshotVal - * - * The Status register SymbolTimeSnapshotVal indicates the actual value of the TimeStamp generator. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_status_delta - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: D-RCW (delta read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x40090220 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_rx_buff_is_full_d - * - * Delta bit of status "rx_buff_is_full" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_status_mask - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: DM-RW (delta mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x40090224 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_rx_buff_is_full_m - * - * Mask bit of status "rx_buff_is_full" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_control_0 - * - * Initialization value: 0x4350 Initialization mask: 0x7ff1 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x40090240 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x7ff1 - -/* - * - * Bit: ftdf_on_off_regmap_DbgTxTransparentMode - * - * If 1, the MPDU octets pass transparently through the MAC in the transmit direction (for debug purpose). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 1 -/* - * - * Field: ftdf_on_off_regmap_macMaxBE - * - * Maximum Backoff Exponent (range 3-8) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXBE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXBE 0xf0 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXBE 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXBE 4 -/* - * - * Field: ftdf_on_off_regmap_macMinBE - * - * Minimum Backoff Exponent (range 0-macMaxBE) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMINBE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMINBE 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMINBE 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMINBE 4 -/* - * - * Field: ftdf_on_off_regmap_macMaxCSMABackoffs - * - * Maximum number of CSMA-CA backoffs - * (range 0-5) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 0x7000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 3 - -/* - * - * REGISTER: ftdf_on_off_regmap_ftdf_ce - * - * Initialization value: none. - * Access mode: EC-R (composite event) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x40090250 -#define SIZE_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x3f - -/* - * - * Field: ftdf_on_off_regmap_ftdf_ce - * - * Composite serveice request from ftdf macro (see FR0400 in v40.100.2.41.pdf) - * Bit 0 = unused - * Bit 1 = rx interrupts - * Bit 2 = tx interrupts - * Bit 3 = miscelaneous interrupts - * Bit 4 = tx interrupts from pages below (0x3 and 0x4) - * Bit 5 = Reserved - */ -#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_CE IND_R_FTDF_ON_OFF_REGMAP_FTDF_CE -#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_CE 0x3f -#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_CE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_CE 6 - -/* - * - * REGISTER: ftdf_on_off_regmap_ftdf_cm - * - * Initialization value: 0x0 Initialization mask: 0x3f - * Access mode: ECM-RW (composite event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x40090254 -#define SIZE_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x3f - -/* - * - * Field: ftdf_on_off_regmap_ftdf_cm - * - * mask bits for ftf_ce - */ -#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_CM IND_R_FTDF_ON_OFF_REGMAP_FTDF_CM -#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_CM 0x3f -#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_CM 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_CM 6 - -/* - * - * REGISTER: ftdf_on_off_regmap_SyncTimeStampThr - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x40090304 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SyncTimeStampThr - * - * Threshold for synchronize TS gen. - * Note that due to implementation this register may only be written once per two LP_CLK periods. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_SyncTimeStampVal - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0x40090308 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SyncTimeStampVal - * - * Value to sync TS gen with. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_SyncTimeStampPhaseVal - * - * Initialization value: 0x0 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0x40090320 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0xff - -/* - * - * Field: ftdf_on_off_regmap_SyncTimeStampPhaseVal - * - * Value to sync TS gen phase within a symbol with. - * Please note the +1 correction needed for most accurate result (+0.5 is than the average error, resulting is a just too fast clock). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_timer_control_1 - * - * Initialization value: 0x0 Initialization mask: 0x2 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x4009030c -#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x2 - -/* - * - * Bit: ftdf_on_off_regmap_SyncTimeStampEna - * - * If set, the TimeStampThr is enabled to generate a sync of the TS gen. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA IND_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_macTxStdAckFrmCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0x40090310 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macTxStdAckFrmCnt - * - * Standard Acknowledgment frames transmitted - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macRxStdAckFrmOkCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0x40090314 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macRxStdAckFrmOkCnt - * - * Standard Acknowledgment frames received - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macRxAddrFailFrmCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0x40090318 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macRxAddrFailFrmCnt - * - * Frames discarded due to incorrect address or PAN Id - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macRxUnsupFrmCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0x4009031c -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macRxUnsupFrmCnt - * - * Frames which do pass the checks but are not supported - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macFCSErrorCount - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0x40090340 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macFCSErrorCount - * - * The number of received frames that were discarded due to an incorrect FCS. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT IND_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_LmacReset - * - * Initialization value: 0x0 Initialization mask: 0x106df - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x40090360 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x106df - -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_control - * - * LmacReset_control: A '1' Resets LMAC Controller (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_rx - * - * LmacReset_rx: A '1' Resets LMAC rx pipeline (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_tx - * - * LmacReset_tx: A '1' Resets LMAC tx pipeline (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_ahb - * - * LmacReset_ahb: A '1' Resets LMAC ahb interface (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_oreg - * - * LmacReset_oreg: A '1' Resets LMAC on_off regmap (for debug and MLME-reset) - * - * #$LmacReset_areg@on_off_regmap - * #LmacReset_areg: A '1' Resets LMAC always_on regmap (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_tstim - * - * LmacReset_tstim: A '1' Resets LMAC timestamp timer (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_sec - * - * LmacReset_sec: A '1' Resets LMAC security (for debug and MLME-reset) - * - * #$LmacReset_wutim@on_off_regmap - * #LmacReset_wutim: A '1' Resets LMAC wake-up timer (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 0x80 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 7 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_count - * - * LmacReset_count: A '1' Resets LMAC mac counters (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 0x200 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 9 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_timctrl - * - * LmacReset_count: A '1' Resets LMAC timing control block (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 0x400 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 10 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacGlobReset_count - * - * If set, the LMAC performance and traffic counters will be reset. - * Use this register for functionally reset these counters. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 0x10000 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_SymbolTimeThr - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0x40090380 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SymbolTimeThr - * - * Symboltime Threshold to generate a general interrupt - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_SymbolTime2Thr - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0x40090384 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SymbolTime2Thr - * - * Symboltime 2 Threshold to generate a general interrupt - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_DebugControl - * - * Initialization value: 0x0 Initialization mask: 0x1ff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x40090390 -#define SIZE_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x1ff - -/* - * - * Bit: ftdf_on_off_regmap_dbg_rx_input - * - * If set, the Rx debug interface will be selected as input for the Rx pipeline. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL -#define MSK_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 0x100 -#define OFF_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 1 -/* - * - * Field: ftdf_on_off_regmap_dbg_control - * - * Control of the debug interface - * - * dbg_control 0x00 Not used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control 0x01 Legacy debug mode - * diagnose bus bit 7 = ed_request - * diagnose bus bit 6 = gen_irq - * diagnose bus bit 5 = tx_en - * diagnose bus bit 4 = rx_en - * diagnose bus bit 3 = phy_en - * diagnose bus bit 2 = tx_valid - * diagnose bus bit 1 = rx_sof - * diagnose bus bit 0 = rx_eof - * - * dbg_control 0x02 Clocks and reset - * diagnose bus bit 7-3 = "00000" - * diagnose bus bit 2 = lp_clk divide by 2 - * diagnose bus bit 1 = mac_clk divide by 2 - * diagnose bus bit 0 = hclk divided by 2 - * - * dbg_control in range 0x02 - 0x0f Not used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control in range 0x10 - 0x1f Debug rx pipeline - * - * 0x10 Rx phy signals - * diagnose_bus bit 7 = rx_enable towards the rx_pipeline - * diagnose bus bit 6 = rx_sof from phy - * diagnose bus bit 5-2 = rx_data from phy - * diagnose bus bit 1 = rx_eof to phy - * diagnose bus bit 0 = rx_sof event from rx_mac_timing block - * - * 0x11 Rx sof and length - * diagnose_bus bit 7 = rx_sof - * diagnose bus bit 6-0 = rx_mac_length from rx_mac_timing block - * - * 0x12 Rx mac timing output - * diagnose_bus bit 7 = Enable from rx_mac_timing block - * diagnose bus bit 6 = Sop from rx_mac_timing block - * diagnose bus bit 5 = Eop from rx_mac_timing block - * diagnose bus bit 4 = Crc from rx_mac_timing block - * diagnose bus bit 3 = Err from rx_mac_timing block - * diagnose bus bit 2 = Drop from rx_mac_timing block - * diagnose bus bit 1 = Forward from rx_mac_timing block - * diagnose bus bit 0 = rx_sof - * - * 0x13 Rx mac frame parser output - * diagnose_bus bit 7 = Enable from mac_frame_parser block - * diagnose bus bit 6 = Sop from mac_frame_parser block - * diagnose bus bit 5 = Eop from mac_frame_parser block - * diagnose bus bit 4 = Crc from mac_frame_parser block - * diagnose bus bit 3 = Err from mac_frame_parser block - * diagnose bus bit 2 = Drop from mac_frame_parser block - * diagnose bus bit 1 = Forward from mac_frame_parser block - * diagnose bus bit 0 = rx_sof - * - * 0x14 Rx status to Umac - * diagnose_bus bit 7 = rx_frame_stat_umac.crc16_error - * diagnose bus bit 6 = rx_frame_stat_umac.res_frm_type_error - * diagnose bus bit 5 = rx_frame_stat_umac.res_frm_version_error - * diagnose bus bit 4 = rx_frame_stat_umac.dpanid_error - * diagnose bus bit 3 = rx_frame_stat_umac.daddr_error - * diagnose bus bit 2 = rx_frame_stat_umac.spanid_error - * diagnose bus bit 1 = rx_frame_stat_umac.ispan_coord_error - * diagnose bus bit 0 = rx_sof - * - * 0x15 Rx status to lmac - * diagnose_bus bit 7 = rx_frame_stat.packet_valid - * diagnose bus bit 6 = rx_frame_stat.rx_sof_e - * diagnose bus bit 5 = rx_frame_stat.rx_eof_e - * diagnose bus bit 4 = rx_frame_stat.wakeup_frame - * diagnose bus bit 3-1 = rx_frame_stat.frame_type - * diagnose bus bit 0 = rx_frame_stat.rx_sqnr_valid - * - * 0x16 Rx buffer control - * diagnose_bus bit 7-4 = prov_from_swio.rx_read_buf_ptr - * diagnose bus bit 3-0 = stat_to_swio.rx_write_buf_ptr - * - * 0x17 Rx interrupts - * diagnose_bus bit 7 = stat_to_swio.rx_buf_avail_e - * diagnose bus bit 6 = stat_to_swio.rx_buf_full - * diagnose bus bit 5 = stat_to_swio.rx_buf_overflow_e - * diagnose bus bit 4 = stat_to_swio.rx_sof_e - * diagnose bus bit 3 = stat_to_swio.rxbyte_e - * diagnose bus bit 2 = rx_frame_ctrl.rx_enable - * diagnose bus bit 1 = rx_eof - * diagnose bus bit 0 = rx_sof - * - * 0x18 diagnose_bus bit 7-3 = - * Prt statements mac frame parser - * 0 Reset - * 1 Multipurpose frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped - * 2 Multipurpose frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped - * 3 RX unsupported frame type detected - * 4 RX non Beacon frame detected and dropped in RxBeaconOnly mode - * 5 RX frame passed due to macAlwaysPassFrmType set - * 6 RX unsupported da_mode = 01 for frame_version 0x0- detected - * 7 RX unsupported sa_mode = 01 for frame_version 0x0- detected - * 8 Data or command frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped - * 9 Data or command frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped - * 10 RX unsupported frame_version detected - * 11 Multipurpose frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped - * 12 Multipurpose frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped - * 13 RX unsupported frame_version detected - * 14 RX Destination PAN Id check failed - * 15 RX Destination address (1 byte) check failed - * 16 RX Destination address (2 byte) check failed - * 17 RX Destination address (8 byte) check failed - * 18 RX Source PAN Id check for Beacon frames failed - * 19 RX Source PAN Id check failed - * 20 Auxiliary Security Header security control word received - * 21 Auxiliary Security Header unsupported_legacy received frame_version 00 - * 22 Auxiliary Security Header unsupported_legacy security frame_version 11 - * 23 Auxiliary Security Header frame counter field received - * 24 Auxiliary Security Header Key identifier field received - * 25 Errored Destination Wakeup frame found send to Umac, not indicated towards lmac controller - * 26 MacAlwaysPassWakeUpFrames = 1, Wakeup frame found send to Umac, not indicated towards lmac controller - * 27 Wakeup frame found send to lmac controller and Umac - * 28 Wakeup frame found send to lmac controller, dropped towards Umac - * 29 Command frame with data_request command received - * 30 Coordinator realignment frame received - * 31 Not Used - * diagnose bus bit 2-0 = frame_type - * - * 0x19 diagnose_bus bit 7-4 = - * Framestates mac frame parser - * 0 idle_state - * 1 fr_ctrl_state - * 2 fr_ctrl_long_state - * 3 seq_nr_state - * 4 dest_pan_id_state - * 5 dest_addr_state - * 6 src_pan_id_state - * 7 src_addr_state - * 8 aux_sec_hdr_state - * 9 hdr_ie_state - * 10 pyld_ie_state - * 11 ignore_state - * 12-16 Not used - * diagnose bus bit 3 = rx_mac_sof_e - * diagnose bus bit 2-0 = frame_type - * - * 0x1a-0x1f Not Used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control in range 0x20 - 0x2f Debug tx pipeline - * 0x20 Top and bottom interfaces tx datapath - * diagnose_bus bit 7 = tx_mac_ld_strb - * diagnose bus bit 6 = tx_mac_drdy - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = symbol_ena - * - * 0x21 Control signals for tx datapath - * diagnose_bus bit 7 = TxTransparentMode - * diagnose bus bit 6 = ctrl_lmac_to_tx.CRC16_ena - * diagnose bus bit 5 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose bus bit 3 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 2-1 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose bus bit 0 = tx_valid - * - * 0x22 Control signals for wakeup frames - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 5-1 = ctrl_lmac_to_tx.gen_wu_RZ(4 DOWNTO 0) - * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero - * - * 0x23 Data signals for wakeup frame - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero - * - * 0x24 Data and control ack frame - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_ack - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = symbol_ena - * - * 0x25-0x2f Not Used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control in range 0x30 - 0x3f Debug lmac_controller - * 0x30 Phy signals - * diagnose_bus bit 7 = phy_en - * diagnose bus bit 6 = tx_en - * diagnose bus bit 5 = rx_en - * diagnose bus bit 4-1 = phyattr(3 downto 0) - * diagnose bus bit 0 = ed_request - * - * 0x31 Phy enable and detailed statemachine info - * diagnose_bus bit 7 = phy_en - * diagnose bus bit 6-0 = prt statements detailed statemachine info - * 0 Reset - * 1 MAIN_STATE_IDLE TX_ACKnowledgement frame skip CSMA_CA - * 2 MAIN_STATE_IDLE : Wake-Up frame resides in buffer no - * 3 MAIN_STATE_IDLE : TX frame in TSCH mode - * 4 MAIN_STATE_IDLE : TX frame - * 5 MAIN_STATE_IDLE : goto SINGLE_CCA - * 6 MAIN_STATE_IDLE : goto Energy Detection - * 7 MAIN_STATE_IDLE : goto RX - * 8 MAIN_STATE_IDLE de-assert phy_en wait for - * 9 MAIN_STATE_IDLE Start phy_en and assert phy_en wait for : - * 10 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA framenr : - * 11 MAIN_STATE_CSMA_CA framenr : - * 12 MAIN_STATE_CSMA_CA start CSMA_CA - * 14 MAIN_STATE_CSMA_CA skip CSMA_CA - * 15 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed for CSL mode - * 16 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed - * 17 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Success - * 18 MAIN_STATE_SINGLE_CCA cca failed - * 19 MAIN_STATE_SINGLE_CCA cca ok - * 20 MAIN_STATE_WAIT_ACK_DELAY wait time elapsed - * 21 MAIN_STATE_WAIT ACK_DELAY : Send Ack in TSCH mode - * 22 MAIN_STATE_WAIT ACK_DELAY : Ack not scheduled in time in TSCH mode - * 23 MAIN_STATE_TSCH_TX_FRAME macTSRxTx time elapsed - * 24 MAIN_STATE_TX_FRAME it is CSL mode, start the WU seq for macWUPeriod - * 25 MAIN_STATE_TX_FRAME1 - * 26 MAIN_STATE_TX_FRAME_W1 exit, waited for : - * 27 MAIN_STATE_TX_FRAME_W2 exit, waited for : - * 28 MAIN_STATE_TX_WAIT_LAST_SYMBOL exit - * 29 MAIN_STATE_TX_RAMPDOWN_W exit, waited for : - * 30 MAIN_STATE_TX_PHYTRXWAIT exit, waited for : - * 31 MAIN_STATE_GEN_IFS , Ack with frame pending received - * 32 MAIN_STATE_GEN_IFS , Ack requested but DisRXackReceivedca is set - * 33 MAIN_STATE_GEN_IFS , instead of generating an IFS, switch the rx-on for an ACK - * 34 MAIN_STATE_GEN_IFS , generating an SIFS (Short Inter Frame Space) - * 35 MAIN_STATE_GEN_IFS , generating an LIFS (Long Inter Frame Space) - * 36 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'cslperiod_timer_ready' is ready sent the data frame - * 37 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'Rendezvous zero time not yet transmitted sent another WU frame - * 38 MAIN_STATE_GEN_IFS_FINISH exit, corrected for : - * 39 MAIN_STATE_GEN_IFS_FINISH in CSL mode, rx_resume_after_tx is set - * 40 MAIN_STATE_SENT_STATUS CSLMode wu_sequence_done_flag : - * 41 MAIN_STATE_ADD_DELAY exit, goto RX for frame pending time - * 42 MAIN_STATE_ADD_DELAY exit, goto IDLE - * 43 MAIN_STATE_RX switch the RX from off to on - * 44 MAIN_STATE_RX_WAIT_PHYRXSTART waited for - * 45 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the MacAckDuration timer - * 46 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the ack wait timer - * 47 MAIN_STATE_RX_WAIT_PHYRXLATENCY NORMAL mode : start rx_duration - * 48 MAIN_STATE_RX_WAIT_PHYRXLATENCY TSCH mode : start macTSRxWait (macTSRxWait) timer - * 49 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration (macCSLsamplePeriod) timer - * 50 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration (macCSLdataPeriod) timer - * 51 MAIN_STATE_RX_CHK_EXPIRED 1 ackwait_timer_ready or ack_received_ind - * 52 MAIN_STATE_RX_CHK_EXPIRED 2 normal_mode. ACK with FP bit set, start frame pending timer - * 54 MAIN_STATE_RX_CHK_EXPIRED 4 RxAlwaysOn is set to 0 - * 55 MAIN_STATE_RX_CHK_EXPIRED 5 TSCH mode valid frame rxed - * 56 MAIN_STATE_RX_CHK_EXPIRED 6 TSCH mode macTSRxwait expired - * 57 MAIN_STATE_RX_CHK_EXPIRED 7 macCSLsamplePeriod timer ready - * 58 MAIN_STATE_RX_CHK_EXPIRED 8 csl_mode. Data frame recieved with FP bit set, increment RX duration time - * 59 MAIN_STATE_RX_CHK_EXPIRED 9 CSL mode : Received wu frame in data listening period restart macCSLdataPeriod timer - * 60 MAIN_STATE_RX_CHK_EXPIRED 10 csl_rx_duration_ready or csl data frame received: - * 61 MAIN_STATE_RX_CHK_EXPIRED 11 normal_mode. FP bit is set, start frame pending timer - * 62 MAIN_STATE_RX_CHK_EXPIRED 12 normal mode rx_duration_timer_ready and frame_pending_timer_ready - * 63 MAIN_STATE_RX_CHK_EXPIRED 13 acknowledge frame requested - * 64 MAIN_STATE_RX_CHK_EXPIRED 14 Interrupt to sent a frame. found_tx_packet - * 65 MAIN_STATE_CSL_RX_IDLE_END RZ time is far away, switch receiver Off and wait for csl_rx_rz_time before switching on - * 66 MAIN_STATE_CSL_RX_IDLE_END RZ time is not so far away, keep receiver On and wait for - * 67 MAIN_STATE_RX_START_PHYRXSTOP ack with fp received keep rx on - * 68 MAIN_STATE_RX_START_PHYRXSTOP switch the RX from on to off - * 69 MAIN_STATE_RX_WAIT_PHYRXSTOP acknowledge done : switch back to finish TX - * 70 MAIN_STATE_RX_WAIT_PHYRXSTOP switch the RX off - * 71 MAIN_STATE_ED switch the RX from off to on - * 72 MAIN_STATE_ED_WAIT_PHYRXSTART waited for phyRxStartup - * 73 MAIN_STATE_ED_WAIT_EDSCANDURATION waited for EdScanDuration - * 74 MAIN_STATE_ED_WAIT_PHYRXSTOP end of Energy Detection, got IDLE - * 75 - 127 Not used - * - * 0x32 RX enable and detailed statemachine info - * diagnose_bus bit 7 = rx_en - * diagnose bus bit 6-0 = detailed statemachine info see dbg_control = 0x31 - * - * 0x33 TX enable and detailed statemachine info - * diagnose_bus bit 7 = tx_en - * diagnose bus bit 6-0 = detailed statemachine info see dbg_control = 0x31 - * - * 0x34 Phy enable, TX enable and Rx enable and state machine states - * diagnose_bus bit 7 = phy_en - * diagnose_bus bit 6 = tx_en - * diagnose_bus bit 5 = rx_en - * diagnose bus bit 4-0 = State machine states - * 1 MAIN_STATE_IDLE - * 2 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA - * 3 MAIN_STATE_CSMA_CA - * 4 MAIN_STATE_WAIT_FOR_CSMA_CA_0 - * 5 MAIN_STATE_WAIT_FOR_CSMA_CA - * 6 MAIN_STATE_SINGLE_CCA - * 7 MAIN_STATE_WAIT_ACK_DELAY - * 8 MAIN_STATE_TSCH_TX_FRAME - * 9 MAIN_STATE_TX_FRAME - * 10 MAIN_STATE_TX_FRAME1 - * 11 MAIN_STATE_TX_FRAME_W1 - * 12 MAIN_STATE_TX_FRAME_W2 - * 13 MAIN_STATE_TX_WAIT_LAST_SYMBOL - * 14 MAIN_STATE_TX_RAMPDOWN - * 15 MAIN_STATE_TX_RAMPDOWN_W - * 16 MAIN_STATE_TX_PHYTRXWAIT - * 17 MAIN_STATE_GEN_IFS - * 18 MAIN_STATE_GEN_IFS_FINISH - * 19 MAIN_STATE_SENT_STATUS - * 20 MAIN_STATE_ADD_DELAY - * 21 MAIN_STATE_TSCH_RX_ACKDELAY - * 22 MAIN_STATE_RX - * 23 MAIN_STATE_RX_WAIT_PHYRXSTART - * 24 MAIN_STATE_RX_WAIT_PHYRXLATENCY - * 25 MAIN_STATE_RX_CHK_EXPIRED - * 26 MAIN_STATE_CSL_RX_IDLE_END - * 27 MAIN_STATE_RX_START_PHYRXSTOP - * 28 MAIN_STATE_RX_WAIT_PHYRXSTOP - * 29 MAIN_STATE_ED - * 30 MAIN_STATE_ED_WAIT_PHYRXSTART - * 31 MAIN_STATE_ED_WAIT_EDSCANDURATION - * - * 0x35 lmac controller to tx interface with wakeup - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen_wu - * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start - * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol - * - * 0x36 lmac controller to tx interface with frame pending - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen.fp_bit - * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start - * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol - * - * 0x37 rx pipepline to lmac controller interface - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_rx_to_lmac.rx_sof_e - * diagnose_bus bit 4 = ctrl_rx_to_lmac.rx_eof_e - * diagnose_bus bit 3 = ctrl_rx_to_lmac.packet_valid - * diagnose_bus bit 2 = ack_received_ind - * diagnose_bus bit 1 = ack_request_ind - * diagnose_bus bit 0 = ctrl_rx_to_lmac.data_request_frame - * - * 0x38 csl start - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = csl_start - * diagnose_bus bit 4-1 = swio_always_on_to_lmac_ctrl.tx_flag_stat - * diagnose_bus bit 0 = found_wu_packet; - * - * 0x39 Tsch TX ack timing - * diagnose_bus bit 7-4 = swio_always_on_to_lmac_ctrl.tx_flag_stat - * diagnose_bus bit 3 = tx_en - * diagnose_bus bit 2 = rx_en - * diagnose_bus bit 1 = ctrl_rx_to_lmac.packet_valid - * diagnose_bus bit 0 = one_us_timer_ready - * - * 0x3a-0x3f Not used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control in range 0x40 - 0x4f Debug security - * 0x40 Security control - * diagnose_bus bit 7 = swio_to_security.secStart - * diagnose_bus bit 6 = swio_to_security.secTxRxn - * diagnose_bus bit 5 = swio_to_security.secAbort - * diagnose_bus bit 4 = swio_to_security.secEncDecn - * diagnose_bus bit 3 = swio_from_security.secBusy - * diagnose_bus bit 2 = swio_from_security.secAuthFail - * diagnose_bus bit 1 = swio_from_security.secReady_e - * diagnose_bus bit 0 = '0' - * - * 0x41 Security ctlid access rx and tx - * diagnose_bus bit 7 = tx_sec_ci.ld_strb - * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = tx_sec_ci.selectp - * diagnose_bus bit 4 = tx_sec_co.d_rdy - * diagnose_bus bit 3 = rx_sec_ci.ld_strb - * diagnose_bus bit 2 = rx_sec_ci.ctlid_rw - * diagnose_bus bit 1 = rx_sec_ci.selectp - * diagnose_bus bit 0 = rx_sec_co.d_rdy - * - * 0x42 Security ctlid access tx with sec_wr_data_valid - * diagnose_bus bit 7 = tx_sec_ci.ld_strb - * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = tx_sec_ci.selectp - * diagnose_bus bit 4 = tx_sec_co.d_rdy - * diagnose_bus bit 3-0 = sec_wr_data_valid - * - * 0x43 Security ctlid access rx with sec_wr_data_valid - * diagnose_bus bit 7 = rx_sec_ci.ld_strb - * diagnose_bus bit 6 = rx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = rx_sec_ci.selectp - * diagnose_bus bit 4 = rx_sec_co.d_rdy - * diagnose_bus bit 3-0 = sec_wr_data_valid - * - * 0x44-0x4f Not used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control in range 0x50 - 0x5f AHB bus - * 0x50 ahb bus without hsize - * diagnose_bus bit 7 = hsel - * diagnose_bus bit 6-5 = htrans - * diagnose_bus bit 4 = hwrite - * diagnose_bus bit 3 = hready_in - * diagnose_bus bit 2 = hready_out - * diagnose_bus bit 1-0 = hresp - * - * 0x51 ahb bus without hwready_in and hresp(1) - * diagnose_bus bit 7 = hsel - * diagnose_bus bit 6-5 = htrans - * diagnose_bus bit 4 = hwrite - * diagnose_bus bit 3-2 = hhsize(1 downto 0) - * diagnose_bus bit 1 = hready_out - * diagnose_bus bit 0 = hresp(0) - * - * 0x52 Amba tx signals - * diagnose_bus bit 7 = ai_tx.penable - * diagnose_bus bit 6 = ai_tx.psel - * diagnose_bus bit 5 = ai_tx.pwrite - * diagnose_bus bit 4 = ao_tx.pready - * diagnose_bus bit 3 = ao_tx.pslverr - * diagnose_bus bit 2-1 = psize_tx - * diagnose_bus bit 0 = hready_out - * - * 0x53 Amba rx signals - * diagnose_bus bit 7 = ai_rx.penable - * diagnose_bus bit 6 = ai_rx.psel - * diagnose_bus bit 5 = ai_rx.pwrite - * diagnose_bus bit 4 = ao_rx.pready - * diagnose_bus bit 3 = ao_rx.pslverr - * diagnose_bus bit 2-1 = psize_rx - * diagnose_bus bit 0 = hready_out - * - * 0x54 Amba register map signals - * diagnose_bus bit 7 = ai_reg.penable - * diagnose_bus bit 6 = ai_reg.psel - * diagnose_bus bit 5 = ai_reg.pwrite - * diagnose_bus bit 4 = ao_reg.pready - * diagnose_bus bit 3 = ao_reg.pslverr - * diagnose_bus bit 2-1 = "00" - * diagnose_bus bit 0 = hready_out - * - * 0x55-0x5f Not used - * diagnose bus bit 7 - 0 = all '0' - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL -#define MSK_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_txbyte_e - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x40090394 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_txbyte_e - * - * Indicates the first byte of a frame is transmitted - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBYTE_E IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 1 -/* - * - * Bit: ftdf_on_off_regmap_tx_last_symbol_e - * - * Indicates the last symbol of a frame is transmitted - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_txbyte_m - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x40090398 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_txbyte_m - * - * Mask bit for event "txbyte_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBYTE_M IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 1 -/* - * - * Bit: ftdf_on_off_regmap_tx_last_symbol_m - * - * Mask bit for event "tx_last_symbol_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_flag_s - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x40090400 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x1 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_S_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_S_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_STAT_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_STAT_INTVL 0x20 - -/* - * - * Bit: ftdf_on_off_regmap_tx_flag_stat - * - * Packet is ready for transmission - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_flag_clear_e - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x40090404 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x1 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_INTVL 0x20 - -/* - * - * Bit: ftdf_on_off_regmap_tx_flag_clear_e - * - * When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_flag_clear_m - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x40090408 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x1 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_INTVL 0x20 - -/* - * - * Bit: ftdf_on_off_regmap_tx_flag_clear_m - * - * Mask bit for event "tx_flag_clear_e". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_priority - * - * Initialization value: 0x0 Initialization mask: 0x1f - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0x40090410 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0x1f -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_ISWAKEUP_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_ISWAKEUP_INTVL 0x20 - -/* - * - * Field: ftdf_on_off_regmap_tx_priority - * - * Priority of packet - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0xf -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 4 -/* - * - * Bit: ftdf_on_off_regmap_IsWakeUp - * - * A basic wake-up frame can be generated by the UMAC in the Tx buffer. - * The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_ISWAKEUP IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY -#define MSK_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_set_os - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0x40090480 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0xf - -/* - * - * Field: ftdf_on_off_regmap_tx_flag_set - * - * To set tx_flag_stat - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET IND_R_FTDF_ON_OFF_REGMAP_TX_SET_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 0xf -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 4 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_clear_os - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0x40090484 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0xf - -/* - * - * Field: ftdf_on_off_regmap_tx_flag_clear - * - * To clear tx_flag_stat - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR IND_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 0xf -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 4 - -/* - * - * REGISTER: ftdf_always_on_regmap_WakeUpIntThr - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0x40091000 -#define SIZE_R_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0x4 -#define MSK_R_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0xffffffff - -/* - * - * Field: ftdf_always_on_regmap_WakeUpIntThr - * - * Threshold for wake-up interrupt. - */ -#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR -#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0xffffffff -#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0 -#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 32 - -/* - * - * REGISTER: ftdf_always_on_regmap_wakeup_control - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0x40091004 -#define SIZE_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0x4 -#define MSK_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0x3 - -/* - * - * Bit: ftdf_always_on_regmap_WakeUpEnable - * - * If set, the WakeUpIntThr is enabled to generate an interrupt. - */ -#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL -#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 0x2 -#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 1 -#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 1 -/* - * - * Bit: ftdf_always_on_regmap_WakeupTimerEnable - * - * A '1' Enables the wakeup timer. - * Note that in on_off_regmap, the register WakeupTimerEnableStatus shows the status of this register after being clocked by LP_CLK. - * Checking this register can be used as indication for software that this bit is effective in the desing. - */ -#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL -#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE 0x1 -#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE 0 -#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE 1 -#else // dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -/* - * - * REGISTER: ftdf_retention_ram_tx_fifo - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_FIFO 0x40080000 -#define SIZE_R_FTDF_RETENTION_RAM_TX_FIFO 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_FIFO 0xffffffff -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_1D 0x4 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_1D 0x80 -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_2D 0x20 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_2D 0x4 -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_1D 0x4 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_1D 0x80 -#define FTDF_RETENTION_RAM_TX_FIFO_NUM_2D 0x20 -#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_2D 0x4 - -/* - * - * Field: ftdf_retention_ram_tx_fifo - * - * Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. - * Note that, despite the name, this fifo is NOT retained when the LMAC is put into deep-sleep! - */ -#define IND_F_FTDF_RETENTION_RAM_TX_FIFO IND_R_FTDF_RETENTION_RAM_TX_FIFO -#define MSK_F_FTDF_RETENTION_RAM_TX_FIFO 0xffffffff -#define OFF_F_FTDF_RETENTION_RAM_TX_FIFO 0 -#define SIZE_F_FTDF_RETENTION_RAM_TX_FIFO 32 - -/* - * - * REGISTER: ftdf_retention_ram_tx_meta_data_0 - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x40080200 -#define SIZE_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x57ffffff -#define FTDF_RETENTION_RAM_TX_META_DATA_0_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_META_DATA_0_INTVL 0x10 -#define FTDF_RETENTION_RAM_FRAME_LENGTH_NUM 0x4 -#define FTDF_RETENTION_RAM_FRAME_LENGTH_INTVL 0x10 -#define FTDF_RETENTION_RAM_PHYATTR_NUM 0x4 -#define FTDF_RETENTION_RAM_PHYATTR_INTVL 0x10 -#define FTDF_RETENTION_RAM_FRAMETYPE_NUM 0x4 -#define FTDF_RETENTION_RAM_FRAMETYPE_INTVL 0x10 -#define FTDF_RETENTION_RAM_CSMACA_ENA_NUM 0x4 -#define FTDF_RETENTION_RAM_CSMACA_ENA_INTVL 0x10 -#define FTDF_RETENTION_RAM_ACKREQUEST_NUM 0x4 -#define FTDF_RETENTION_RAM_ACKREQUEST_INTVL 0x10 -#define FTDF_RETENTION_RAM_CRC16_ENA_NUM 0x4 -#define FTDF_RETENTION_RAM_CRC16_ENA_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_frame_length - * - * Tx meta data per entry: Frame length (in bytes) - */ -#define IND_F_FTDF_RETENTION_RAM_FRAME_LENGTH IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH 0x7f -#define OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH 0 -#define SIZE_F_FTDF_RETENTION_RAM_FRAME_LENGTH 7 -/* - * - * Field: ftdf_retention_ram_phyAttr - * - * Tx meta data per entry: during the Tx-on phase, the control register phyRxAttr[16] sources the PHYATTR output signal to the DPHY. - */ -#define IND_F_FTDF_RETENTION_RAM_PHYATTR IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_PHYATTR 0x7fff80 -#define OFF_F_FTDF_RETENTION_RAM_PHYATTR 7 -#define SIZE_F_FTDF_RETENTION_RAM_PHYATTR 16 -/* - * - * Field: ftdf_retention_ram_frametype - * - * Tx meta data per entry: the frame type of the data to be transmitted (Data/Cmd/Ack/wakeup frame/etc.). - */ -#define IND_F_FTDF_RETENTION_RAM_FRAMETYPE IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_FRAMETYPE 0x3800000 -#define OFF_F_FTDF_RETENTION_RAM_FRAMETYPE 23 -#define SIZE_F_FTDF_RETENTION_RAM_FRAMETYPE 3 -/* - * - * Bit: ftdf_retention_ram_CsmaCa_ena - * - * Tx meta data per entry: '1' indicates that a CSMA-CA is required for the transmission of this packet. - */ -#define IND_F_FTDF_RETENTION_RAM_CSMACA_ENA IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_CSMACA_ENA 0x4000000 -#define OFF_F_FTDF_RETENTION_RAM_CSMACA_ENA 26 -#define SIZE_F_FTDF_RETENTION_RAM_CSMACA_ENA 1 -/* - * - * Bit: ftdf_retention_ram_AckRequest - * - * Tx meta data per entry: '1' indicates that an acknowledge is expected from the recipient of this packet. - */ -#define IND_F_FTDF_RETENTION_RAM_ACKREQUEST IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_ACKREQUEST 0x10000000 -#define OFF_F_FTDF_RETENTION_RAM_ACKREQUEST 28 -#define SIZE_F_FTDF_RETENTION_RAM_ACKREQUEST 1 -/* - * - * Bit: ftdf_retention_ram_CRC16_ena - * - * Tx meta data per entry: Indicates whether CRC16 insertion must be enabled or not. - * 0 : No hardware inserted CRC16 - * 1 : Hardware inserts CRC16 - */ -#define IND_F_FTDF_RETENTION_RAM_CRC16_ENA IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 -#define MSK_F_FTDF_RETENTION_RAM_CRC16_ENA 0x40000000 -#define OFF_F_FTDF_RETENTION_RAM_CRC16_ENA 30 -#define SIZE_F_FTDF_RETENTION_RAM_CRC16_ENA 1 - -/* - * - * REGISTER: ftdf_retention_ram_tx_meta_data_1 - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0x40080204 -#define SIZE_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0xff -#define FTDF_RETENTION_RAM_TX_META_DATA_1_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_META_DATA_1_INTVL 0x10 -#define FTDF_RETENTION_RAM_MACSN_NUM 0x4 -#define FTDF_RETENTION_RAM_MACSN_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_macSN - * - * Tx meta data per entry: Sequence Number of this packet. - */ -#define IND_F_FTDF_RETENTION_RAM_MACSN IND_R_FTDF_RETENTION_RAM_TX_META_DATA_1 -#define MSK_F_FTDF_RETENTION_RAM_MACSN 0xff -#define OFF_F_FTDF_RETENTION_RAM_MACSN 0 -#define SIZE_F_FTDF_RETENTION_RAM_MACSN 8 - -/* - * - * REGISTER: ftdf_retention_ram_tx_return_status_0 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0x40080240 -#define SIZE_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0xffffffff -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_0_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_0_INTVL 0x10 -#define FTDF_RETENTION_RAM_TXTIMESTAMP_NUM 0x4 -#define FTDF_RETENTION_RAM_TXTIMESTAMP_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_TxTimestamp - * - * Tx return status per entry: Transmit Timestamp - * The Timestamp of the transmitted packet. - */ -#define IND_F_FTDF_RETENTION_RAM_TXTIMESTAMP IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 -#define MSK_F_FTDF_RETENTION_RAM_TXTIMESTAMP 0xffffffff -#define OFF_F_FTDF_RETENTION_RAM_TXTIMESTAMP 0 -#define SIZE_F_FTDF_RETENTION_RAM_TXTIMESTAMP 32 - -/* - * - * REGISTER: ftdf_retention_ram_tx_return_status_1 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x40080244 -#define SIZE_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x4 -#define MSK_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x1f -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_1_NUM 0x4 -#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_1_INTVL 0x10 -#define FTDF_RETENTION_RAM_ACKFAIL_NUM 0x4 -#define FTDF_RETENTION_RAM_ACKFAIL_INTVL 0x10 -#define FTDF_RETENTION_RAM_CSMACAFAIL_NUM 0x4 -#define FTDF_RETENTION_RAM_CSMACAFAIL_INTVL 0x10 -#define FTDF_RETENTION_RAM_CSMACANRRETRIES_NUM 0x4 -#define FTDF_RETENTION_RAM_CSMACANRRETRIES_INTVL 0x10 - -/* - * - * Bit: ftdf_retention_ram_AckFail - * - * Tx return status per entry: Acknowledgement status - * 0 : SUCCESS - * 1 : FAIL - */ -#define IND_F_FTDF_RETENTION_RAM_ACKFAIL IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 -#define MSK_F_FTDF_RETENTION_RAM_ACKFAIL 0x1 -#define OFF_F_FTDF_RETENTION_RAM_ACKFAIL 0 -#define SIZE_F_FTDF_RETENTION_RAM_ACKFAIL 1 -/* - * - * Bit: ftdf_retention_ram_CsmaCaFail - * - * Tx return status per entry: CSMA-CA status - * 0 : SUCCESS - * 1 : FAIL - */ -#define IND_F_FTDF_RETENTION_RAM_CSMACAFAIL IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 -#define MSK_F_FTDF_RETENTION_RAM_CSMACAFAIL 0x2 -#define OFF_F_FTDF_RETENTION_RAM_CSMACAFAIL 1 -#define SIZE_F_FTDF_RETENTION_RAM_CSMACAFAIL 1 -/* - * - * Field: ftdf_retention_ram_CsmaCaNrRetries - * - * Tx return status per entry: Number of CSMA-CA retries before this frame has been transmitted - */ -#define IND_F_FTDF_RETENTION_RAM_CSMACANRRETRIES IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 -#define MSK_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 0x1c -#define OFF_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 2 -#define SIZE_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 3 - -/* - * - * REGISTER: ftdf_retention_ram_rx_meta_0 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_RX_META_0 0x40080280 -#define SIZE_R_FTDF_RETENTION_RAM_RX_META_0 0x4 -#define MSK_R_FTDF_RETENTION_RAM_RX_META_0 0xffffffff -#define FTDF_RETENTION_RAM_RX_META_0_NUM 0x8 -#define FTDF_RETENTION_RAM_RX_META_0_INTVL 0x10 -#define FTDF_RETENTION_RAM_RX_TIMESTAMP_NUM 0x8 -#define FTDF_RETENTION_RAM_RX_TIMESTAMP_INTVL 0x10 - -/* - * - * Field: ftdf_retention_ram_rx_timestamp - * - * Rx meta data per entry: Timestamp taken when frame was received - */ -#define IND_F_FTDF_RETENTION_RAM_RX_TIMESTAMP IND_R_FTDF_RETENTION_RAM_RX_META_0 -#define MSK_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 0xffffffff -#define OFF_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 0 -#define SIZE_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 32 - -/* - * - * REGISTER: ftdf_retention_ram_rx_meta_1 - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_RETENTION_RAM_RX_META_1 0x40080284 -#define SIZE_R_FTDF_RETENTION_RAM_RX_META_1 0x4 -#define MSK_R_FTDF_RETENTION_RAM_RX_META_1 0xfffd -#define FTDF_RETENTION_RAM_RX_META_1_NUM 0x8 -#define FTDF_RETENTION_RAM_RX_META_1_INTVL 0x10 -#define FTDF_RETENTION_RAM_CRC16_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_CRC16_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_DPANID_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_DPANID_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_DADDR_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_DADDR_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_SPANID_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_SPANID_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_ISPANID_COORD_ERROR_NUM 0x8 -#define FTDF_RETENTION_RAM_ISPANID_COORD_ERROR_INTVL 0x10 -#define FTDF_RETENTION_RAM_QUALITY_INDICATOR_NUM 0x8 -#define FTDF_RETENTION_RAM_QUALITY_INDICATOR_INTVL 0x10 - -/* - * - * Bit: ftdf_retention_ram_crc16_error - * - * Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only - */ -#define IND_F_FTDF_RETENTION_RAM_CRC16_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_CRC16_ERROR 0x1 -#define OFF_F_FTDF_RETENTION_RAM_CRC16_ERROR 0 -#define SIZE_F_FTDF_RETENTION_RAM_CRC16_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_res_frm_type_error - * - * Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 0x4 -#define OFF_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 2 -#define SIZE_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_res_frm_version_error - * - * Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded. - */ -#define IND_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 0x8 -#define OFF_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 3 -#define SIZE_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_dpanid_error - * - * Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_DPANID_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_DPANID_ERROR 0x10 -#define OFF_F_FTDF_RETENTION_RAM_DPANID_ERROR 4 -#define SIZE_F_FTDF_RETENTION_RAM_DPANID_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_daddr_error - * - * Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_DADDR_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_DADDR_ERROR 0x20 -#define OFF_F_FTDF_RETENTION_RAM_DADDR_ERROR 5 -#define SIZE_F_FTDF_RETENTION_RAM_DADDR_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_spanid_error - * - * Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_SPANID_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_SPANID_ERROR 0x40 -#define OFF_F_FTDF_RETENTION_RAM_SPANID_ERROR 6 -#define SIZE_F_FTDF_RETENTION_RAM_SPANID_ERROR 1 -/* - * - * Bit: ftdf_retention_ram_ispanid_coord_error - * - * Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded - */ -#define IND_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 0x80 -#define OFF_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 7 -#define SIZE_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 1 -/* - * - * Field: ftdf_retention_ram_quality_indicator - * - * Rx meta data per entry: the Link Quality Indication value during reception of this frame. - * - * # $software_scratch@retention_ram - * # TX ram not used by hardware, can be used by software as scratch ram with retention. - */ -#define IND_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR IND_R_FTDF_RETENTION_RAM_RX_META_1 -#define MSK_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 0xff00 -#define OFF_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 8 -#define SIZE_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 8 - -/* - * - * REGISTER: ftdf_rx_ram_rx_fifo - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_RX_RAM_RX_FIFO 0x40088000 -#define SIZE_R_FTDF_RX_RAM_RX_FIFO 0x4 -#define MSK_R_FTDF_RX_RAM_RX_FIFO 0xffffffff -#define FTDF_RX_RAM_RX_FIFO_NUM_1D 0x8 -#define FTDF_RX_RAM_RX_FIFO_INTVL_1D 0x80 -#define FTDF_RX_RAM_RX_FIFO_NUM_2D 0x20 -#define FTDF_RX_RAM_RX_FIFO_INTVL_2D 0x4 -#define FTDF_RX_RAM_RX_FIFO_NUM_1D 0x8 -#define FTDF_RX_RAM_RX_FIFO_INTVL_1D 0x80 -#define FTDF_RX_RAM_RX_FIFO_NUM_2D 0x20 -#define FTDF_RX_RAM_RX_FIFO_INTVL_2D 0x4 - -/* - * - * Field: ftdf_rx_ram_rx_fifo - * - * Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. - */ -#define IND_F_FTDF_RX_RAM_RX_FIFO IND_R_FTDF_RX_RAM_RX_FIFO -#define MSK_F_FTDF_RX_RAM_RX_FIFO 0xffffffff -#define OFF_F_FTDF_RX_RAM_RX_FIFO 0 -#define SIZE_F_FTDF_RX_RAM_RX_FIFO 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_Rel_Name - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_REL_NAME 0x40090000 -#define SIZE_R_FTDF_ON_OFF_REGMAP_REL_NAME 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_REL_NAME 0xffffffff -#define FTDF_ON_OFF_REGMAP_REL_NAME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_REL_NAME_INTVL 0x4 -#define FTDF_ON_OFF_REGMAP_REL_NAME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_REL_NAME_INTVL 0x4 - -/* - * - * Field: ftdf_on_off_regmap_Rel_Name - * - * A 4 words wide register, showing in ASCII the name of the release, eg. "ftdf_107". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_REL_NAME IND_R_FTDF_ON_OFF_REGMAP_REL_NAME -#define MSK_F_FTDF_ON_OFF_REGMAP_REL_NAME 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_REL_NAME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_REL_NAME 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_BuildTime - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0x40090010 -#define SIZE_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0xffffffff -#define FTDF_ON_OFF_REGMAP_BUILDTIME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_BUILDTIME_INTVL 0x4 -#define FTDF_ON_OFF_REGMAP_BUILDTIME_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_BUILDTIME_INTVL 0x4 - -/* - * - * Field: ftdf_on_off_regmap_BuildTime - * - * A 4 words wide register, showing in ASCII the build date (dd mmm yy) and time (hh:mm) of device, eg. "01 Dec 14 14:10 ". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_BUILDTIME IND_R_FTDF_ON_OFF_REGMAP_BUILDTIME -#define MSK_F_FTDF_ON_OFF_REGMAP_BUILDTIME 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_BUILDTIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_BUILDTIME 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_0 - * - * Initialization value: 0xff00 Initialization mask: 0x6ff0e - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x40090020 -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x6ff0e - -/* - * - * Bit: ftdf_on_off_regmap_IsPANCoordinator - * - * Enable/disable receiver check on address fields (0=enabled, 1=disabled) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_dma_req - * - * Source of the RX_DMA_REQ output pin of this block. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 1 -/* - * - * Bit: ftdf_on_off_regmap_tx_dma_req - * - * Source of the TX_DMA_REQ output pin of this block. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 1 -/* - * - * Field: ftdf_on_off_regmap_macSimpleAddress - * - * Simple address of the PAN coordinator - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 8 -/* - * - * Bit: ftdf_on_off_regmap_macLEenabled - * - * If set to '1', the Low Energy mode (also called CSL) is enabled - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACLEENABLED IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 0x20000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 17 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 1 -/* - * - * Bit: ftdf_on_off_regmap_macTSCHenabled - * - * If set to '1', the TSCH mode is enabled - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 0x40000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 18 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_1 - * - * Initialization value: 0xffffffff Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0x40090024 -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macPANId - * - * The PAN ID of this device. - * The value 0xFFFF indicates that the device is not associated to a PAN. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACPANID IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACPANID 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACPANID 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACPANID 16 -/* - * - * Field: ftdf_on_off_regmap_macShortAddress - * - * The short address of the device. The values 0xFFFF and 0xFFFE indicate that no IEEE Short Address is available. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_2 - * - * Initialization value: 0xffffffff Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0x40090028 -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_aExtendedAddress_l - * - * Unique device address, 48 bits wide, lowest 32 bit - */ -#define IND_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_glob_control_3 - * - * Initialization value: 0xffffffff Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0x4009002c -#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_aExtendedAddress_h - * - * Unique device address, 48 bits wide, highest 16 bit - */ -#define IND_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_0 - * - * Initialization value: 0x0 Initialization mask: 0xfbfffffe - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0x40090030 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0xfbfffffe - -/* - * - * Field: ftdf_on_off_regmap_RxonDuration - * - * The time (in symbol periods) the Rx must be on after setting RxEnable to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXONDURATION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXONDURATION 0x1fffffe -#define OFF_F_FTDF_ON_OFF_REGMAP_RXONDURATION 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXONDURATION 24 -/* - * - * Bit: ftdf_on_off_regmap_RxAlwaysOn - * - * If set to '1', the receiver shall be always on if RxEnable is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXALWAYSON IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 0x2000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 25 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 1 -/* - * - * Field: ftdf_on_off_regmap_pti_rx - * - * This value will be used during receiving frames, during the auto ACK (when the AR bit is set in the received frame, see [FR0655] and further), a single CCA and ED scan. - * In TSCH mode this register will be used during the time slot in which frames can be received and consequently an Enhanced ACK can be transmitted. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PTI_RX IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_PTI_RX 0x78000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PTI_RX 27 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PTI_RX 4 -/* - * - * Bit: ftdf_on_off_regmap_keep_phy_en - * - * When the transmit or receive action is ready (LmacReady4Sleep is set), the PHY_EN signal is cleared unless the control register keep_phy_en is set to '1'. - * When the control register keep_phy_en is set to '1', the signal PHY_EN shall remain being set until the keep_phy_en is cleared. - * This will help control the behavior of the arbiter between the LMAC and the DPHY. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 0x80000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 31 -#define SIZE_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_TxPipePropDelay - * - * Initialization value: 0x0 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0x40090034 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0xff - -/* - * - * Field: ftdf_on_off_regmap_TxPipePropDelay - * - * Propagation delay (in us) of the tx pipe, between start of transmission (indicated by setting tx_flag_status) to the DPHY. - * The reset value is 0 us, which is also the closest value to the real implementation figure. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY IND_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY -#define MSK_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_MacAckWaitDuration - * - * Initialization value: 0x36 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0x40090038 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0xff - -/* - * - * Field: ftdf_on_off_regmap_MacAckWaitDuration - * - * Maximum time (in symbol periods) to wait for an ACK response after transmitting a frame with the AR bit set to '1'. - * This value is used in the normal mode for the wait of an ACK response, irrespective if the ACK is a normal ACK or an Enhanced ACK. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION IND_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION -#define MSK_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_MacEnhAckWaitDuration - * - * Initialization value: 0x360 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0x4009003c -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0xffff - -/* - * - * Field: ftdf_on_off_regmap_MacEnhAckWaitDuration - * - * Maximum time (in us) to wait for an Enhanced ACK response after transmitting a frame with the AR bit set to '1'. - * This value is used in the LE/CSL mode for the wait of an ACK response (which is always an Enhanced ACK). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION IND_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION -#define MSK_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_1 - * - * Initialization value: 0x0 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0x40090040 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0xffff - -/* - * - * Field: ftdf_on_off_regmap_phyRxAttr - * - * Value of the PHYATTR bus to DPHY during Rx operation. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffff01 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0x40090044 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0xffffff01 - -/* - * - * Bit: ftdf_on_off_regmap_EdScanEnable - * - * If set to '1', the Energy Detect scan will be performed when RxEnable is set to '1' rather than starting a receive action. - * The length of this scan is defined by EdScanDuration. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 1 -/* - * - * Field: ftdf_on_off_regmap_EdScanDuration - * - * The length of ED scan in symbol periods. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 0xffffff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 24 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_3 - * - * Initialization value: 0x70004c4 Initialization mask: 0xfffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0x40090048 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0xfffffff - -/* - * - * Field: ftdf_on_off_regmap_macMaxFrameTotalWaitTime - * - * Max time to wait (in symbol periods) for a requested Data Frame or an announced broadcast frame, triggered by the FP bit in the received frame was set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 16 -/* - * - * Field: ftdf_on_off_regmap_CcaIdleWait - * - * Time to wait (in us) after CCA returned "medium idle" before starting TX-ON. - * Notes: - * 1) extra wait times are involved before a packet is really transmitted, see the relevant timing figures. - * 2) not applicable in TSCH mode since there macTSRxTx shall be used. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 8 -/* - * - * Bit: ftdf_on_off_regmap_Addr_tab_match_FP_value - * - * In case the received source address matches with one of the Exp_SA registers, the value of the control register Addr_tap_match_FP_value will be inserted on the position of the FP bit. - * In case there is no match found, the inverse value of Addr_tap_match_FP_value will be inserted. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE 0x1000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE 1 -/* - * - * Bit: ftdf_on_off_regmap_FP_override - * - * In case the control register FP_override is set, the value of the control register FP_force_value will always be the value of the FP bit in the automatic ACK response frame. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE 0x2000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE 25 -#define SIZE_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE 1 -/* - * - * Bit: ftdf_on_off_regmap_FP_force_value - * - * In case the control register FP_override is set, the value of the control register FP_force_value will always be the value of the FP bit in the automatic ACK response frame. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE 0x4000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE 26 -#define SIZE_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE 1 -/* - * - * Bit: ftdf_on_off_regmap_FTDF_LPDP_Enable - * - * If set, not only is FP_override and SA matching done on data_request frames but to all command and data frame types (in normal mode) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE 0x8000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE 27 -#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_os - * - * Initialization value: 0x0 Initialization mask: 0x1f - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x40090050 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x1f - -/* - * - * Bit: ftdf_on_off_regmap_getGeneratorVal - * - * If set to '1', the current values of the Wake-up (event) counter/generator (EventCurrVal) and Timestamp (symbol) counter/generator (TimeStampCurrVal and TimeStampCurrPhaseVal) will be captured. - * Note that this capture actually has been done when getGeneratorVal_e is set (assuming it was cleared in advance). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 1 -/* - * - * Bit: ftdf_on_off_regmap_RxEnable - * - * If set, receiving data may be done - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_RXENABLE 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXENABLE 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXENABLE 1 -/* - * - * Bit: ftdf_on_off_regmap_SingleCCA - * - * If set to '1', a single CCA will be performed. - * This can be used when e.g. the TSCH timing is not performed by the LMAC but completely by software. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SINGLECCA IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_SINGLECCA 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_SINGLECCA 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SINGLECCA 1 -/* - * - * Bit: ftdf_on_off_regmap_Csma_Ca_resume_set - * - * If set, Csma_Ca_resume_stat is set - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET 1 -/* - * - * Bit: ftdf_on_off_regmap_Csma_Ca_resume_clear - * - * If set, Csma_Ca_resume_stat is cleared - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0x40090054 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0xff0fff46 - -/* - * - * Bit: ftdf_on_off_regmap_LmacReady4sleep - * - * If set to '1' this register indicates that the LMAC is ready to go to sleep. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 1 -/* - * - * Bit: ftdf_on_off_regmap_CCAStat - * - * The value of a single CCA, valid when CCAstat_e is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT 1 -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus - * - * Status of WakeupTimerEnable after being clocked by LP_CLK (showing it's effective value). - * WakeupTimerEnableStatus can be set by setting the one-shot register WakeupTimerEnable_set and cleared by setting the one-shot register WakeupTimerEnable_clear. - * When WakeupTimerEnableStatus is set (after being cleared), the event counter will be reset to 0x0. - * - * This status can be used by software since WakeupTimerEnable is used in the slow LP_CLK area. - * Rather than waiting for a certain number of LP_CLK periods, simply scanning this status (or enable the interrupt created by WakeupTimerEnableStatus_e) will allow software to determine if this signal has been effected. - * Note that the rising edge of WakeupTimerEnable will reset the Wake-up (event) counter. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 1 -/* - * - * Field: ftdf_on_off_regmap_EdScanValue - * - * The result of an ED scan. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 8 -/* - * - * Field: ftdf_on_off_regmap_Csma_Ca_NB_stat - * - * Current status of the Number of Backoffs. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT 0x70000 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT 3 -/* - * - * Bit: ftdf_on_off_regmap_Csma_Ca_resume_stat - * - * In case Csma_Ca_resume_stat is set the LMAC will - * - use the value of Csma_Ca_NB_val in the CSMA-CA process rather than the initial value 0d. - * - immediately perform CCA after the sleep, not waiting for the backoff time. - * - reset Csma_Ca_resume_stat when it resumes CSMA-CA after the sleep. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT 0x80000 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT 19 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT 1 -/* - * - * Field: ftdf_on_off_regmap_Csma_Ca_BO_stat - * - * The value of the currently calculated BackOff value. To be used for the sleep time calculation in case of sleep during the BackOff time. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT 0xff000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_EventCurrVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x40090058 -#define SIZE_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x1ffffff - -/* - * - * Field: ftdf_on_off_regmap_EventCurrVal - * - * The value of the captured Event generator (Wake-up counter) (initiated by getGeneratorVal, valid when getGeneratorVal_e is set). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL IND_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x1ffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 25 - -/* - * - * REGISTER: ftdf_on_off_regmap_TimeStampCurrVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0x4009005c -#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_TimeStampCurrVal - * - * The value of captured timestamp generator (symbol counter) (initiated by getGeneratorVal, valid when getGeneratorVal_e is set) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_TimeStampCurrPhaseVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0x40090074 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0xff - -/* - * - * Field: ftdf_on_off_regmap_TimeStampCurrPhaseVal - * - * Value of captured timestamp generator phase within a symbol (initiated by getGeneratorVal, valid when getGeneratorVal_e is set) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_macTSTxAckDelayVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0x40090078 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0xffff - -/* - * - * Field: ftdf_on_off_regmap_macTSTxAckDelayVal - * - * The time (in us) left until the ack frame is sent by the lmac. - * This can be used by software to determine if there is enough time left to send the, by software created, Enhanced ACK frame. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL IND_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_4 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0x40090060 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_phySleepWait - * - * The minume time (in us) required between the clear to '0' and set to '1' of PHY_EN. - * When the signal PHY_EN is deasserted, it will not be asserted within the time phySleepWait. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 8 -/* - * - * Field: ftdf_on_off_regmap_RxPipePropDelay - * - * The control register RxPipePropDelay indicates the propagation delay in ~s of the Rx pipeline between the last symbol being captured at the DPHY interface and the "data valid" indication to the LMAC controller. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 8 -/* - * - * Field: ftdf_on_off_regmap_phyAckAttr - * - * During transmission of an ACK frame, phyAckAttr is used as PHYATTR on the DPHY interface. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYACKATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_5 - * - * Initialization value: 0x8c0 Initialization mask: 0xffff0fff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0x40090064 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0xffff0fff - -/* - * - * Field: ftdf_on_off_regmap_Ack_Response_Delay - * - * In order to have some flexibility the control register Ack_Response_Delay indicates the Acknowledge response time in ~s. - * The default value shall is 192 ~s (12 symbols). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 -#define MSK_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 8 -/* - * - * Field: ftdf_on_off_regmap_CcaStatWait - * - * The output CCASTAT is valid after 8 symbols + phyRxStartup. - * The 8 symbols are programmable by control registerCcaStatWait (in symbol periods). - * Default value is 8d. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 4 -/* - * - * Field: ftdf_on_off_regmap_phyCsmaCaAttr - * - * During CSMA-CA or CCA, the control register phyCsmaCaAttr is used to source PHYATT on the DPHY interface. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_6 - * - * Initialization value: 0xc0c28 Initialization mask: 0xffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0x40090068 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0xffffff - -/* - * - * Field: ftdf_on_off_regmap_LifsPeriod - * - * The Long IFS period is programmable by LifsPeriod (in symbols). - * The default is 40 symbols (640 us), - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 -#define MSK_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 8 -/* - * - * Field: ftdf_on_off_regmap_SifsPeriod - * - * The Short IFS period is programmable by SifsPeriod (in symbols). - * The default is 12 symbols (192 is). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 -#define MSK_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 8 -/* - * - * Field: ftdf_on_off_regmap_WUifsPeriod - * - * The WakeUp IFS period is programmable by WUifsPeriod (in symbols). - * The default is 12 symbols (192 us). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 -#define MSK_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_11 - * - * Initialization value: 0xff000000 Initialization mask: 0xff0fffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0x4009006c -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0xff0fffff - -/* - * - * Field: ftdf_on_off_regmap_macRxTotalCycleTime - * - * In CSL mode it can be decided to disable the PHY Rx (Rx-off) after reception of a Wake-up frame and enable the PHY Rx (Rx-on) when the data frame is to be expected, based on the received RZ time. - * In order to make it easier to calculate if it is efficient to switch to Rx-off and Rx-on again, a control register indicates the time needed to disable and enable the PHY Rx: macRxTotalCycleTime (resolution is 10 symbol periods) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 16 -/* - * - * Bit: ftdf_on_off_regmap_macDisCaRxOfftoRZ - * - * The switching off and on of the PHY Rx (see macRxTotalCycleTime) can be disabled whith the control register macDisCaRxOfftoRZ. - * 0 : Disabled - * 1 : Enabled - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 0x10000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 1 -/* - * - * Field: ftdf_on_off_regmap_Csma_Ca_NB_val - * - * Number of backoffs value in case of a CSMA-CA resume action. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL 0xe0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL 17 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL 3 -/* - * - * Field: ftdf_on_off_regmap_Csma_Ca_BO_threshold - * - * If the backoff time calculated in the CSMA-CA procedure as described in [FR3280] is equal to or higher than the control register Csma_Ca_BO_threshold[8] (resolution 320us, see [FR3290]) the event register Csma_Ca_BO_thr_e will be set and an interrupt. - * In case Csma_Ca_BO_threshold equals 0xFF no check will be performed and consequently Csma_Ca_BO_thr_e will not be set and no interrupt will be generated. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD 0xff000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_delta - * - * Initialization value: 0x0 Initialization mask: 0x7e - * Access mode: D-RCW (delta read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x40090070 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x7e - -/* - * - * Bit: ftdf_on_off_regmap_LmacReady4sleep_d - * - * Delta bit for register "LmacReady4sleep". - * This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[3]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 1 -/* - * - * Bit: ftdf_on_off_regmap_SyncTimeStamp_e - * - * The SyncTimeStamp_e event is set to '1' when the TimeStampgenerator is loaded with SyncTimeStampVal. - * This occurs at the rising edge of lp_clk when SyncTimeStampEna is set and the value of the Event generator is equal to the value SyncTimestampThr. - * This event bit contributes to ftdf_ce[3]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTimeThr_e - * - * Event, set to '1' when the symboltime counter matched SymbolTimeThr - * This event bit contributes to ftdf_ce[3]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTime2Thr_e - * - * Event, set to '1' when the symboltime counter matched SymbolTime2Thr - * This event bit contributes to ftdf_ce[3]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 1 -/* - * - * Bit: ftdf_on_off_regmap_getGeneratorVal_e - * - * Event, set to '1' to indicate that the the getGeneratorVal request is completed. - * This event bit contributes to ftdf_ce[3]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 0x20 -#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 5 -#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 1 -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus_d - * - * Delta which indicates that WakeupTimerEnableStatus has changed - * This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[3]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_mask - * - * Initialization value: 0x0 Initialization mask: 0x7e - * Access mode: DM-RW (delta mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x40090080 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x7e - -/* - * - * Bit: ftdf_on_off_regmap_LmacReady4sleep_m - * - * Mask bit for delta bit "LmacReady4sleep_d". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 1 -/* - * - * Bit: ftdf_on_off_regmap_SyncTimeStamp_m - * - * Mask bit for event register SyncTimeStamp_e. - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTimeThr_m - * - * Mask for SymbolTimeThr_e - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 1 -/* - * - * Bit: ftdf_on_off_regmap_SymbolTime2Thr_m - * - * Mask for SymbolTime2Thr_e - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 1 -/* - * - * Bit: ftdf_on_off_regmap_getGeneratorVal_m - * - * Mask for getGeneratorVal_e - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 0x20 -#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 5 -#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 1 -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus_m - * - * Mask for WakeupTimerEnableStatus_d - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_event - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0x40090090 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0xf - -/* - * - * Bit: ftdf_on_off_regmap_EdScanReady_e - * - * The event EdScanReady_e is set to '1' to notify that the ED scan is ready. - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 1 -/* - * - * Bit: ftdf_on_off_regmap_CCAstat_e - * - * If set to '1', the single CCA is ready - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 1 -/* - * - * Bit: ftdf_on_off_regmap_RxTimerExpired_e - * - * Set to '1' if one of the timers enabling the Rx-on mode expires without having received any valid frame. - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 1 -/* - * - * Bit: ftdf_on_off_regmap_Csma_Ca_BO_thr_e - * - * If set, the calculated backoff time is more than Csma_Ca_BO_threshold. - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_mask - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0x40090094 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0xf - -/* - * - * Bit: ftdf_on_off_regmap_EdScanReady_m - * - * Mask bit for event "EdScanReady_e" - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 1 -/* - * - * Bit: ftdf_on_off_regmap_CCAstat_m - * - * Mask bit for event "CCAstat_e" - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 1 -/* - * - * Bit: ftdf_on_off_regmap_RxTimerExpired_m - * - * Mask bit for event "RxTimerExpired_e" - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 1 -/* - * - * Bit: ftdf_on_off_regmap_Csma_Ca_BO_thr_m - * - * Mask bit for event "Csma_Ca_BO_thr_e" - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_manual_1 - * - * Initialization value: 0x0 Initialization mask: 0xffff0fff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0x400900a0 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0xffff0fff - -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_mode - * - * If the control register lmac_manual_mode is set to '1', the LMAC controller control signals should be controlled by the lmac_manual_control registers - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_phy_en - * - * lmac_manual_phy_en controls the PHY_EN interface signal when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_tx_en - * - * lmac_manual_tx_en controls the TX_EN interface signal when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_rx_en - * - * lmac_manual_rx_en controls the RX_EN interface signal when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_rx_pipe_en - * - * lmac_manual_rx_pipe_en controls the rx_enable signal towards the rx pipeline when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 1 -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_ed_request - * - * lmac_manual_ed_request controls the ED_REQUEST interface signal when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 0x20 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 5 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 1 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_tx_frm_nr - * - * lmac_manual_tx_frm_nr controls the entry in the tx buffer to be transmitted when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 0xc0 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 2 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_pti - * - * lmac_manual_pti controls the PTI interface signal when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 4 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_phy_attr - * - * lmac_manual_phy_attr controls the PHY_ATTR interface signal when lmac_manual_mode is set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_manual_os - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x400900a4 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_tx_start - * - * One shot register which triggers the transmission of a frame from the tx buffer in lmac_manual_mode to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_manual_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0x400900a8 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0xff01 - -/* - * - * Bit: ftdf_on_off_regmap_lmac_manual_cca_stat - * - * lmac_manual_cca_stat shows the status of the CCA_STAT DPHY interface signal. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 1 -/* - * - * Field: ftdf_on_off_regmap_lmac_manual_ed_stat - * - * lmac_manual_ed_stat shows the status of the ED_STAT DPHY interface signal. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_7 - * - * Initialization value: 0x420000 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0x40090100 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macWUPeriod - * - * In CSL mode, the Wake-up duration in symbol periods. During this period, Wake-up frames will be transmitted. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 16 -/* - * - * Field: ftdf_on_off_regmap_macCSLsamplePeriod - * - * In CSL mode, when performing a idle listening, the receiver is enabled for at least macCSLsamplePeriod (in symbol oeriods). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_8 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0x40090104 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macCSLstartSampleTime - * - * In CSL mode, the control register macCSLstartSampleTime indicates the TimeStamp generator time (in symbol periods) when to start listening (called "idle listening") or transmitting (when tx_flag_status is set). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_9 - * - * Initialization value: 0x42 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0x40090108 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macCSLdataPeriod - * - * In CSL mode, after the wake-up sequence a data frame is expected. The receiver will be enabled for at least a period of macCSLdataPeriod (in symbol periods). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 16 -/* - * - * Field: ftdf_on_off_regmap_macCSLFramePendingWaitT - * - * In CSL mode, if a non Wake-up frame with Frame Pending bit = '1' is received, the receiver is enabled for at least an extra period of macCSLFramePendingWaitT (in symbol periods) after the end of the received frame. - * The time the Enhanced ACK transmission lasts (if applicable) is included in this time. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_lmac_control_10 - * - * Initialization value: 0x20000000 Initialization mask: 0xf00f00ff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0x4009010c -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0xf00f00ff - -/* - * - * Field: ftdf_on_off_regmap_macRZzeroVal - * - * In CSL mode, if the current RZtime is less or Equal to macRZzeroVal an RZtime with value zero is inserted in the wakeup frame. So this is by default the last Wake-up frame of a Wake-up sequence. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 0xf0000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 28 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 4 -/* - * - * Field: ftdf_on_off_regmap_macCSLmarginRZ - * - * In CSL mode, the software can set the margin for the expected frame by control register macCSLmarginRZ (in 10 symbol periods). - * The LMAC will make sure that the receiver is ready to receive data this amount of time earlier than to be expected by the received RZ time. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 0xf0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 4 -/* - * - * Field: ftdf_on_off_regmap_macWURZCorrection - * - * In CSL mode, this register shall be used if the Wake-up frame to be transmitted is larger than 15 octets. - * It shall indicate the amount of extra data in a Wake-up frame after the RZ position in the frame (in 10 symbol periods). - * This correction is needed to make sure that the correct RZ time is filled in by the LMAC. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_0 - * - * Initialization value: 0x0 Initialization mask: 0xff7f0f02 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0x40090110 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0xff7f0f02 - -/* - * - * Bit: ftdf_on_off_regmap_secTxRxn - * - * Encryption/decryption mode: see register "secEntry". - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECTXRXN IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECTXRXN 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECTXRXN 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECTXRXN 1 -/* - * - * Field: ftdf_on_off_regmap_secEntry - * - * Encryption/decryption mode: the software indicates by the control registers secEntry and secTxRxn which entry to use and if it's from the Tx or Rx buffer ('1' resp. '0'). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECENTRY IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECENTRY 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECENTRY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENTRY 4 -/* - * - * Field: ftdf_on_off_regmap_secAlength - * - * Encryption/decryption mode: the length of the a_data is indicated by control register secAlength (in bytes). - * The end of the a_data is the start point of the m_data. So secAlength must also be set if security level==4. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECALENGTH IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECALENGTH 0x7f0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECALENGTH 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECALENGTH 7 -/* - * - * Field: ftdf_on_off_regmap_secMlength - * - * Encryption/decryption mode: the length of the m_data is indicated by control register secMlength (in bytes). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECMLENGTH IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 0x7f000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 7 -/* - * - * Bit: ftdf_on_off_regmap_secEncDecn - * - * Encryption/decryption mode: the control register secEncDecn indicates whether to encrypt ('1') or decrypt ('0') the data. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECENCDECN IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECENCDECN 0x80000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECENCDECN 31 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENCDECN 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_1 - * - * Initialization value: 0x0 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0x40090114 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0xffff - -/* - * - * Field: ftdf_on_off_regmap_secAuthFlags - * - * Encryption/decryption mode: register secAuthFlags contains the authentication flags fields. - * bit[7] is '0' - * bit[6] is "A_data present" - * bit[5:3]: 3-bit security level of m_data - * bit[2:0]: 3-bit security level of a_data. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 8 -/* - * - * Field: ftdf_on_off_regmap_secEncrFlags - * - * Encryption/decryption mode: register secEncrFlags contains the encryption flags field. - * Bits [2:0] are the 3-bit encoding flags of a_data, the other bits msut be set to '0'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_0 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0x40090118 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_0 - * - * Encryption/decryption mode: Registers secKey[0..3] contain the key to be used. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_0 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_0 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_0 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_1 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0x4009011c -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_1 - * - * Encryption/decryption mode: see register "secKey_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_1 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_1 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_1 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_1 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0x40090120 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_2 - * - * Encryption/decryption mode: see register "secKey_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_2 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_2 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_2 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_2 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secKey_3 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0x40090124 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secKey_3 - * - * Encryption/decryption mode: see register "secKey_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_3 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_3 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_3 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_3 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_0 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0x40090128 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_0 - * - * Encryption/decryption mode: register secNonce[0..3] contains the Nonce to be used for encryption/decryption. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_1 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0x4009012c -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_1 - * - * Encryption/decryption mode: see register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0x40090130 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_2 - * - * Encryption/decryption mode: see register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_secNonce_3 - * - * Initialization value: 0x0 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0x40090134 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0xff - -/* - * - * Field: ftdf_on_off_regmap_secNonce_3 - * - * Encryption/decryption mode: see register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_os - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x40090138 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_secAbort - * - * Encryption/decryption mode: see register "Nonce_0" - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECABORT IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECABORT 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECABORT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECABORT 1 -/* - * - * Bit: ftdf_on_off_regmap_secStart - * - * Encryption/decryption mode: one_shot register to start the encryption, decryption and authentication support task. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECSTART IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECSTART 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECSTART 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECSTART 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x40090140 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_secBusy - * - * Encryption/decryption mode: register "secBusy" indicates if the encryption/decryption process is still running. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECBUSY IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECBUSY 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECBUSY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECBUSY 1 -/* - * - * Bit: ftdf_on_off_regmap_secAuthFail - * - * Encryption/decryption mode: in case of decryption, the status bit secAuthFail will be set when the authentication has failed. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_event - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x40090150 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_secReady_e - * - * Encryption/decryption mode: the Event bit secReady_e is set to '1' when the authentication process is ready (i.e. secBusy is cleared). - * This event bit contributes to ftdf_ce[3]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECREADY_E IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_SECREADY_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECREADY_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECREADY_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_security_eventmask - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x40090154 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_secReady_m - * - * Mask bit for event "secReady_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SECREADY_M IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK -#define MSK_F_FTDF_ON_OFF_REGMAP_SECREADY_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_SECREADY_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SECREADY_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tsch_control_0 - * - * Initialization value: 0x89803e8 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0x40090160 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macTSTxAckDelay - * - * TSCH mode: the time between the end of a Rx frame and the start of an Enhanced Acknowlegde frame. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 16 -/* - * - * Field: ftdf_on_off_regmap_macTSRxWait - * - * TSCH mode: The times to wait for start of frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_tsch_control_1 - * - * Initialization value: 0xc0 Initialization mask: 0xffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0x40090164 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0xffff - -/* - * - * Field: ftdf_on_off_regmap_macTSRxTx - * - * TSCH mode: The time between the CCA and the TX of a frame - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXTX IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_tsch_control_2 - * - * Initialization value: 0x1900320 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0x40090168 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macTSRxAckDelay - * - * TSCH mode: End of frame to when the transmitter shall listen for Acknowledgement - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 0xffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 16 -/* - * - * Field: ftdf_on_off_regmap_macTSAckWait - * - * TSCH mode: The minimum time to wait for start of an Acknowledgement - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 0xffff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 16 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_0 - * - * Initialization value: 0x76543210 Initialization mask: 0x77777777 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x40090180 -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x77777777 - -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_0 - * - * DPHY interface: control rxBitPos(8)(3) controls the position that a bit should have at the DPHY interface. - * So the default values are rxBitPos_0 = 0, rxBitPos_1 = 1, rxBitPos_2 = 2, etc. - * - * Note1 that this is a conversion from rx DPHY interface to the internal data byte - * So - * for(n=7;n>=0;n--) - * rx_data(n) = dphy_bit(tx_BitPos(n)) - * endfor - * - * Note2 that rxBitPos and txBitPos must have inverse functions. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 0x7 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_1 - * - * DPHY interface: see rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 0x70 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_2 - * - * DPHY interface: see rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 0x700 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_3 - * - * DPHY interface: see rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 0x7000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_4 - * - * DPHY interface: see rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 0x70000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_5 - * - * DPHY interface: see rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 0x700000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 20 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_6 - * - * DPHY interface: see rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 0x7000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 3 -/* - * - * Field: ftdf_on_off_regmap_rxBitPos_7 - * - * DPHY interface: see rxBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 0x70000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 28 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 3 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_1 - * - * Initialization value: 0x76543210 Initialization mask: 0x77777777 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x40090184 -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x77777777 - -/* - * - * Field: ftdf_on_off_regmap_txBitPos_0 - * - * DPHY interface: control txBitPos(8)(3) controls the position that a bit should have at the DPHY interface. - * So the default values are txBitPos_0 = 0, txBitPos_1 = 1, txBitPos_2 = 2, etc. - * - * Note1 that this is a conversion from internal data byte to the DPHY interface. - * So - * for(n=7;n>=0;n--) - * tx_dphy_bit(n) = tx_data(tx_BitPos(n)) - * endfor - * - * Note2 that txBitPos and rxBitPos must have inverse functions. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 0x7 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_1 - * - * DPHY interface: see txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 0x70 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_2 - * - * DPHY interface: see txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 0x700 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_3 - * - * DPHY interface: see txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 0x7000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_4 - * - * DPHY interface: see txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 0x70000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_5 - * - * DPHY interface: see txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 0x700000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 20 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_6 - * - * DPHY interface: see txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 0x7000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 3 -/* - * - * Field: ftdf_on_off_regmap_txBitPos_7 - * - * DPHY interface: see txBitPos_0 - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 0x70000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 28 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 3 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_2 - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0x40090188 -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_phyTxStartup - * - * DPHY interface: the phy wait time (in us) before transmission of a frame may start. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 8 -/* - * - * Field: ftdf_on_off_regmap_phyTxLatency - * - * DPHY interface: phy delay (in us) between DPHY interface and air interface. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 8 -/* - * - * Field: ftdf_on_off_regmap_phyTxFinish - * - * DPHY interface: Phy wait time (in us) before deasserting TX_EN after deasserting TX_VALID. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 8 -/* - * - * Field: ftdf_on_off_regmap_phyTRxWait - * - * DPHY interface: Phy wait time (in us) between deassertion of TX_EN and assertion of RX_EN or vice versa. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 0xff000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_phy_parameters_3 - * - * Initialization value: 0x1000000 Initialization mask: 0x1ffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x4009018c -#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x1ffffff - -/* - * - * Field: ftdf_on_off_regmap_phyRxStartup - * - * DPHY interface: Phy wait time (in us) before receiving of a frame may start. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 8 -/* - * - * Field: ftdf_on_off_regmap_phyRxLatency - * - * DPHY interface: Phy delay (in us) between air and DPHY interface. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 0xff00 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 8 -/* - * - * Field: ftdf_on_off_regmap_phyEnable - * - * DPHY interface: Asserting the DPHY interface signals TX_EN or RX_EN does not take place within the time phyEnable after asserting the signal PHY_EN. - * (in us). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PHYENABLE IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_PHYENABLE 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_PHYENABLE 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYENABLE 8 -/* - * - * Bit: ftdf_on_off_regmap_use_legacy_phy_en - * - * If the control register use_legacy_phy_en is set (default), the output signal PHY_TRANSACTION will be sourced by PHY_EN rather than PHY_TRANSACTION. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 -#define MSK_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN 0x1000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_control_0 - * - * Initialization value: 0x0 Initialization mask: 0xfffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0x40090200 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0xfffffff - -/* - * - * Bit: ftdf_on_off_regmap_DbgRxTransparentMode - * - * If set yo '1', Rx pipe is fully set in transparent mode (for debug purpose). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 1 -/* - * - * Bit: ftdf_on_off_regmap_RxBeaconOnly - * - * If set to '1', only Beacons frames are accepted - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 1 -/* - * - * Bit: ftdf_on_off_regmap_RxCoordRealignOnly - * - * If set to '1', only Coordinator Realignment frames are accepted - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 1 -/* - * - * Field: ftdf_on_off_regmap_rx_read_buf_ptr - * - * Indication where new data will be read - * All four bits shall be used when using these pointer values (0d - 15d). - * However, the Receive Packet buffer has a size of 8 entries. - * So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 0x78 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 4 -/* - * - * Bit: ftdf_on_off_regmap_DisRxFrmPendingca - * - * Whan the control register DisRxFrmPendingCa is set to '1', the notification of the received FP bit to the LMAC Controller is disabled and thus no consequent actions will take place. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 0x80 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 7 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 1 -/* - * - * Bit: ftdf_on_off_regmap_DisRxAckRequestca - * - * When the control register DisRxAckRequestca is set to '1' all consequent actions for a received Acknowledge Request bit are disabled. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 0x100 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassCrcerror - * - * If set to '1', a FCS error will not drop the frame. However, an FCS error will be reported in the Rx meta data (crc16_error is set to '1'). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 0x200 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 9 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 1 -/* - * - * Bit: ftdf_on_off_regmap_DisDataRequestca - * - * When the control register DisDataRequestCa is set, the notification of the received Data Request is disabled. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 0x400 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 10 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassResFrameVersion - * - * If set to '1', a packet with a reserved FrameVersion shall not be dropped - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 0x800 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 11 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassWrongDPANId - * - * If register macAlwaysPassWrongDPANId is set to '1', packet with a wrong Destiantion PanID will not be dropped. - * However, in case of an FCS error, the packet is dropped. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 0x1000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassWrongDAddr - * - * If set to '1', a packet with a wrong DAddr is not dropped - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 0x2000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 13 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassBeaconWrongPANId - * - * If the control register macAlwaysPassBeaconWrongPANId is set, the frame is not dropped in case of a mismatch in PAN-ID, irrespective of the setting of RxBeaconOnly. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 0x4000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 14 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 1 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassToPanCoordinator - * - * When the control register macAlwaysPassToPanCoordinator is set to '1', the frame is not dropped due to a span_coord_error. - * However, in case of an FCS error, the packet is dropped. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 0x8000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 15 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 1 -/* - * - * Field: ftdf_on_off_regmap_macAlwaysPassFrmType - * - * The control registers macAlwaysPassFrmType[7:0], shall control if this Frame Type shall be dropped. - * If a bit is set to '1', the Frame Type corresponding with the bit position is not dropped, even in case of a CRC error. - * Example: - * if bit 3 is set to '1', Frame Type 3 shall not be dropped. - * If there is a FCS error, the error shall be reported in the Rx meta data (crc16_error is set to '1'). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 0xff0000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 8 -/* - * - * Bit: ftdf_on_off_regmap_macAlwaysPassWakeUp - * - * In CSL mode, if the control register macAlwaysPassWakeUp is set to '1', received Wake- up frames for this device are put into the Rx packet buffer without notifying the LMAC Controller (part of transparent mode control). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 0x1000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 24 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 1 -/* - * - * Bit: ftdf_on_off_regmap_macPassWakeUp - * - * In CSL mode, if set to '1', WakeUp frames will be put into the Rx buffer. - * This can be useful for software to parse the WakeUp frame. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 0x2000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 25 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 1 -/* - * - * Bit: ftdf_on_off_regmap_macImplicitBroadcast - * - * If set to '1', Frame Version 2 frames without Daddr or DPANId shall be accepted. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 0x4000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 26 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 1 -/* - * - * Bit: ftdf_on_off_regmap_DisRxAckReceivedca - * - * If set to '1', the LMAC controller shall ignore all consequent actions upon a set AR bit in the transmitted frame (e.g. enabling Rx-on mode after the transmission and wait for an ACK). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 0x8000000 -#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 27 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_event - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: E-RCW2 (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0x40090204 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0xf - -/* - * - * Bit: ftdf_on_off_regmap_RxSof_e - * - * Set to '1' when RX_SOF has been detected. - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXSOF_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXSOF_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXSOF_E 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_overflow_e - * - * If set to '1' it indicates that the Rx packet buffer has an overflow. - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_buf_avail_e - * - * If set to '1' it indicates that a new valid packet completely has been received - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 1 -/* - * - * Bit: ftdf_on_off_regmap_rxbyte_e - * - * If set to '1' it indicates that the first byte of a new packet has been received - * This event bit contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBYTE_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_mask - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_MASK 0x40090208 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_MASK 0xf - -/* - * - * Bit: ftdf_on_off_regmap_RxSof_m - * - * Mask bit for event "RxSof_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXSOF_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXSOF_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXSOF_M 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_overflow_m - * - * Mask bit for event " rx_overflow_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 1 -/* - * - * Bit: ftdf_on_off_regmap_rx_buf_avail_m - * - * Mask bit for event "rx_buf_avail_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 1 -/* - * - * Bit: ftdf_on_off_regmap_rxbyte_m - * - * Mask bit for event "rxbyte_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RXBYTE_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_status - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x4009020c -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x1f - -/* - * - * Bit: ftdf_on_off_regmap_rx_buff_is_full - * - * If set to '1', it indicates that the Rx packet buffer is full - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 1 -/* - * - * Field: ftdf_on_off_regmap_rx_write_buf_ptr - * - * Indication where new data will be written. - * All four bits shall be used when using these pointer values (0d - 15d). - * However, the Receive Packet buffer has a size of 8 entries. - * So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 0x1e -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 4 - -/* - * - * REGISTER: ftdf_on_off_regmap_SymbolTimeSnapshotVal - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0x40090210 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SymbolTimeSnapshotVal - * - * The Status register SymbolTimeSnapshotVal indicates the actual value of the TimeStamp generator. - * This can be useful for software to use e.g. in CSL mode at creating an Enhanced ACK to calculate the CSL phase and period. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_status_delta - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: D-RCW (delta read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x40090220 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_rx_buff_is_full_d - * - * Delta bit of status "rx_buff_is_full". - * This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[1]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_rx_status_mask - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: DM-RW (delta mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x40090224 -#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x1 - -/* - * - * Bit: ftdf_on_off_regmap_rx_buff_is_full_m - * - * Mask bit for delta bit "rx_buff_is_full_d". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK -#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_control_0 - * - * Initialization value: 0x4350 Initialization mask: 0x7ff1 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x40090240 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x7ff1 - -/* - * - * Bit: ftdf_on_off_regmap_DbgTxTransparentMode - * - * If set to '1', the MPDU octets pass transparently through the MAC in the transmit direction (for debug purpose). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 1 -/* - * - * Field: ftdf_on_off_regmap_macMaxBE - * - * CSMA-CA: Maximum Backoff Exponent (range 3-8) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXBE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXBE 0xf0 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXBE 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXBE 4 -/* - * - * Field: ftdf_on_off_regmap_macMinBE - * - * CSMA-CA: Minimum Backoff Exponent (range 0-macMaxBE) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMINBE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMINBE 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMINBE 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMINBE 4 -/* - * - * Field: ftdf_on_off_regmap_macMaxCSMABackoffs - * - * CSMA-CA: Maximum number of CSMA-CA backoffs (range 0-5) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 -#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 0x7000 -#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 12 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 3 - -/* - * - * REGISTER: ftdf_on_off_regmap_ftdf_ce - * - * Initialization value: none. - * Access mode: EC-R (composite event) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x40090250 -#define SIZE_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x3f - -/* - * - * Field: ftdf_on_off_regmap_ftdf_ce - * - * Composite service request from ftdf macro (see FR0400 in v40.100.2.41.pdf), set to '1' if the branch currently contributes to the interrupt. - * Bit 0 = unused - * Bit 1 = rx interrupts - * Bit 2 = unused - * Bit 3 = miscelaneous interrupts - * Bit 4 = tx interrupts - * Bit 5 = Reserved - * Upon an interrupt, using the ftdf_ce bits it can be checked which interrupt branch creates this interrupt. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_CE IND_R_FTDF_ON_OFF_REGMAP_FTDF_CE -#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_CE 0x3f -#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_CE 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_CE 6 - -/* - * - * REGISTER: ftdf_on_off_regmap_ftdf_cm - * - * Initialization value: 0x0 Initialization mask: 0x3f - * Access mode: ECM-RW (composite event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x40090254 -#define SIZE_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x3f - -/* - * - * Field: ftdf_on_off_regmap_ftdf_cm - * - * mask bits for ftf_ce. - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_CM IND_R_FTDF_ON_OFF_REGMAP_FTDF_CM -#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_CM 0x3f -#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_CM 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_CM 6 - -/* - * - * REGISTER: ftdf_on_off_regmap_SyncTimeStampThr - * - * Initialization value: 0x0 Initialization mask: 0x1ffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x40090304 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x1ffffff - -/* - * - * Field: ftdf_on_off_regmap_SyncTimeStampThr - * - * Threshold for synchronize the timestamp counter: at this value of the event counter the synchronization of the timestamp (symbol) counter is done (if SyncTimeStampEna is set to '1'). - * If SyncTimeStamp_e is set to '1' the synchronization has taken place. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x1ffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 25 - -/* - * - * REGISTER: ftdf_on_off_regmap_SyncTimeStampVal - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0x40090308 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SyncTimeStampVal - * - * Value to synchronize the timestamp counter with at the moment indicated by SyncTimeStampThr. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_SyncTimeStampPhaseVal - * - * Initialization value: 0x0 Initialization mask: 0xff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0x40090320 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0xff - -/* - * - * Field: ftdf_on_off_regmap_SyncTimeStampPhaseVal - * - * Value to synchronize the timestamp counter phase with at the moment indicated by SyncTimeStampThr. - * Please note the +1 correction needed for most accurate result (+0.5 is than the average error, resulting is a just too fast clock). - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_timer_control_1 - * - * Initialization value: 0x0 Initialization mask: 0x2 - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x4009030c -#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x2 - -/* - * - * Bit: ftdf_on_off_regmap_SyncTimeStampEna - * - * If set to '1', the synchronization of the timestamp counter after a deep-sleep cycle will be performed when SyncTimeStampThr matches the value of the event (wake-up) counter. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA IND_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 -#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_macTxStdAckFrmCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0x40090310 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macTxStdAckFrmCnt - * - * Traffic counter: the number of standard Acknowledgment frames transmitted after the last deep-sleep cycle. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macRxStdAckFrmOkCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0x40090314 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macRxStdAckFrmOkCnt - * - * Traffic counter: the number of Standard Acknowledgment frames received after the last deep-sleep cycle. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macRxAddrFailFrmCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0x40090318 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macRxAddrFailFrmCnt - * - * Traffic counter: the number of frames discarded due to incorrect address or PAN Id after the last deep-sleep cycle. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macRxUnsupFrmCnt - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0x4009031c -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macRxUnsupFrmCnt - * - * Traffic counter: the number of frames which do pass the checks but are not supported after the last deep-sleep cycle. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_macFCSErrorCount - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0x40090340 -#define SIZE_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_macFCSErrorCount - * - * metrics counter: the number of received frames that were discarded due to an incorrect FCS after the last deep-sleep cycle. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT IND_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT -#define MSK_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_LmacReset - * - * Initialization value: 0x0 Initialization mask: 0x106df - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x40090360 -#define SIZE_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x106df - -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_control - * - * LmacReset_control: A '1' resets LMAC Controller (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_rx - * - * LmacReset_rx: A '1' resets LMAC rx pipeline (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_tx - * - * LmacReset_tx: A '1' resets LMAC tx pipeline (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 0x4 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 2 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_ahb - * - * LmacReset_ahb: A '1' resets LMAC ahb interface (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 0x8 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 3 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_oreg - * - * LmacReset_oreg: A '1' resets LMAC on_off regmap (for debug and MLME-reset) - * - * #$LmacReset_areg@on_off_regmap - * #LmacReset_areg: A '1' Resets LMAC always_on regmap (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_tstim - * - * LmacReset_tstim: A '1' resets LMAC timestamp timer (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 0x40 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 6 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_sec - * - * LmacReset_sec: A '1' resets LMAC security (for debug and MLME-reset) - * - * #$LmacReset_wutim@on_off_regmap - * #LmacReset_wutim: A '1' Resets LMAC wake-up timer (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 0x80 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 7 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_count - * - * LmacReset_count: A '1' resets LMAC mac counters (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 0x200 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 9 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacReset_timctrl - * - * LmacReset_count: A '1' resets LMAC timing control block (for debug and MLME-reset) - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 0x400 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 10 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 1 -/* - * - * Bit: ftdf_on_off_regmap_LmacGlobReset_count - * - * If set, the LMAC performance and traffic counters will be reset. - * Use this register for functionally reset these counters. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT IND_R_FTDF_ON_OFF_REGMAP_LMACRESET -#define MSK_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 0x10000 -#define OFF_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 16 -#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_wakeup_control_os - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS 0x40090364 -#define SIZE_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnable_set - * - * If set, WakeupTimerEnableStatus will be set. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET IND_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET 1 -/* - * - * Bit: ftdf_on_off_regmap_WakeupTimerEnable_clear - * - * If set, WakeupTimerEnableStatus will be cleared. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR IND_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_SymbolTimeThr - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0x40090380 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SymbolTimeThr - * - * Symboltime Threshold to generate a general interrupt when this value matches the symbol counter value. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_SymbolTime2Thr - * - * Initialization value: 0x0 Initialization mask: 0xffffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0x40090384 -#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0xffffffff - -/* - * - * Field: ftdf_on_off_regmap_SymbolTime2Thr - * - * Symboltime 2 Threshold to generate a general interrupt when this value matches the symbol counter value. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR -#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0xffffffff -#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 32 - -/* - * - * REGISTER: ftdf_on_off_regmap_DebugControl - * - * Initialization value: 0x0 Initialization mask: 0x1ff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x40090390 -#define SIZE_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x1ff - -/* - * - * Bit: ftdf_on_off_regmap_dbg_rx_input - * - * If set to '1', the Rx debug interface will be selected as input for the Rx pipeline rather than the DPHY interface signals. - * Note that in this mode, DBG_RX_DATA[3:0] and DBG_RX_SOF are sourced by another source (outside the scope of the LMAC) while the other Rx inputs (CCA_STAT, LQI[7:0] and ED_STAT[7:0]) are forced to 0x00. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL -#define MSK_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 0x100 -#define OFF_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 1 -/* - * - * Field: ftdf_on_off_regmap_dbg_control - * - * Control of the debug interface: - * - * dbg_control 0x00 Not used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control 0x01 Legacy debug mode - * diagnose bus bit 7 = ed_request - * diagnose bus bit 6 = gen_irq - * diagnose bus bit 5 = tx_en - * diagnose bus bit 4 = rx_en - * diagnose bus bit 3 = phy_en - * diagnose bus bit 2 = tx_valid - * diagnose bus bit 1 = rx_sof - * diagnose bus bit 0 = rx_eof - * - * dbg_control 0x02 Clocks and reset - * diagnose bus bit 7-3 = "00000" - * diagnose bus bit 2 = lp_clk divide by 2 - * diagnose bus bit 1 = mac_clk divide by 2 - * diagnose bus bit 0 = hclk divided by 2 - * - * dbg_control in range 0x02 - 0x0f Not used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control in range 0x10 - 0x1f Debug rx pipeline - * - * 0x10 Rx phy signals - * diagnose_bus bit 7 = rx_enable towards the rx_pipeline - * diagnose bus bit 6 = rx_sof from phy - * diagnose bus bit 5-2 = rx_data from phy - * diagnose bus bit 1 = rx_eof to phy - * diagnose bus bit 0 = rx_sof event from rx_mac_timing block - * - * 0x11 Rx sof and length - * diagnose_bus bit 7 = rx_sof - * diagnose bus bit 6-0 = rx_mac_length from rx_mac_timing block - * - * 0x12 Rx mac timing output - * diagnose_bus bit 7 = Enable from rx_mac_timing block - * diagnose bus bit 6 = Sop from rx_mac_timing block - * diagnose bus bit 5 = Eop from rx_mac_timing block - * diagnose bus bit 4 = Crc from rx_mac_timing block - * diagnose bus bit 3 = Err from rx_mac_timing block - * diagnose bus bit 2 = Drop from rx_mac_timing block - * diagnose bus bit 1 = Forward from rx_mac_timing block - * diagnose bus bit 0 = rx_sof - * - * 0x13 Rx mac frame parser output - * diagnose_bus bit 7 = Enable from mac_frame_parser block - * diagnose bus bit 6 = Sop from mac_frame_parser block - * diagnose bus bit 5 = Eop from mac_frame_parser block - * diagnose bus bit 4 = Crc from mac_frame_parser block - * diagnose bus bit 3 = Err from mac_frame_parser block - * diagnose bus bit 2 = Drop from mac_frame_parser block - * diagnose bus bit 1 = Forward from mac_frame_parser block - * diagnose bus bit 0 = rx_sof - * - * 0x14 Rx status to Umac - * diagnose_bus bit 7 = rx_frame_stat_umac.crc16_error - * diagnose bus bit 6 = rx_frame_stat_umac.res_frm_type_error - * diagnose bus bit 5 = rx_frame_stat_umac.res_frm_version_error - * diagnose bus bit 4 = rx_frame_stat_umac.dpanid_error - * diagnose bus bit 3 = rx_frame_stat_umac.daddr_error - * diagnose bus bit 2 = rx_frame_stat_umac.spanid_error - * diagnose bus bit 1 = rx_frame_stat_umac.ispan_coord_error - * diagnose bus bit 0 = rx_sof - * - * 0x15 Rx status to lmac - * diagnose_bus bit 7 = rx_frame_stat.packet_valid - * diagnose bus bit 6 = rx_frame_stat.rx_sof_e - * diagnose bus bit 5 = rx_frame_stat.rx_eof_e - * diagnose bus bit 4 = rx_frame_stat.wakeup_frame - * diagnose bus bit 3-1 = rx_frame_stat.frame_type - * diagnose bus bit 0 = rx_frame_stat.rx_sqnr_valid - * - * 0x16 Rx buffer control - * diagnose_bus bit 7-4 = prov_from_swio.rx_read_buf_ptr - * diagnose bus bit 3-0 = stat_to_swio.rx_write_buf_ptr - * - * 0x17 Rx interrupts - * diagnose_bus bit 7 = stat_to_swio.rx_buf_avail_e - * diagnose bus bit 6 = stat_to_swio.rx_buf_full - * diagnose bus bit 5 = stat_to_swio.rx_buf_overflow_e - * diagnose bus bit 4 = stat_to_swio.rx_sof_e - * diagnose bus bit 3 = stat_to_swio.rxbyte_e - * diagnose bus bit 2 = rx_frame_ctrl.rx_enable - * diagnose bus bit 1 = rx_eof - * diagnose bus bit 0 = rx_sof - * - * 0x18 diagnose_bus bit 7-3 = - * Prt statements mac frame parser - * 0 Reset - * 1 Multipurpose frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped - * 2 Multipurpose frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped - * 3 RX unsupported frame type detected - * 4 RX non Beacon frame detected and dropped in RxBeaconOnly mode - * 5 RX frame passed due to macAlwaysPassFrmType set - * 6 RX unsupported da_mode = 01 for frame_version 0x0- detected - * 7 RX unsupported sa_mode = 01 for frame_version 0x0- detected - * 8 Data or command frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped - * 9 Data or command frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped - * 10 RX unsupported frame_version detected - * 11 Multipurpose frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped - * 12 Multipurpose frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped - * 13 RX unsupported frame_version detected - * 14 RX Destination PAN Id check failed - * 15 RX Destination address (1 byte) check failed - * 16 RX Destination address (2 byte) check failed - * 17 RX Destination address (8 byte) check failed - * 18 RX Source PAN Id check for Beacon frames failed - * 19 RX Source PAN Id check failed - * 20 Auxiliary Security Header security control word received - * 21 Auxiliary Security Header unsupported_legacy received frame_version 00 - * 22 Auxiliary Security Header unsupported_legacy security frame_version 11 - * 23 Auxiliary Security Header frame counter field received - * 24 Auxiliary Security Header Key identifier field received - * 25 Errored Destination Wakeup frame found send to Umac, not indicated towards lmac controller - * 26 MacAlwaysPassWakeUpFrames = 1, Wakeup frame found send to Umac, not indicated towards lmac controller - * 27 Wakeup frame found send to lmac controller and Umac - * 28 Wakeup frame found send to lmac controller, dropped towards Umac - * 29 Command frame with data_request command received - * 30 Coordinator realignment frame received - * 31 Not Used - * diagnose bus bit 2-0 = frame_type - * - * 0x19 diagnose_bus bit 7-4 = - * Framestates mac frame parser - * 0 idle_state - * 1 fr_ctrl_state - * 2 fr_ctrl_long_state - * 3 seq_nr_state - * 4 dest_pan_id_state - * 5 dest_addr_state - * 6 src_pan_id_state - * 7 src_addr_state - * 8 aux_sec_hdr_state - * 9 hdr_ie_state - * 10 pyld_ie_state - * 11 ignore_state - * 12-16 Not used - * diagnose bus bit 3 = rx_mac_sof_e - * diagnose bus bit 2-0 = frame_type - * - * 0x1a diagnose_bus bit 7 = execute_sa_match - * diagnose_bus bit 6 = sa_match_found (1 clk delayed) - * diagnose_bus bit 5 = prov_from_swio.FP_override - * diagnose_bus bit 4 = fp_mac_drdy - * diagnose_bus bit 3 = fp_mac_ld_strb - * diagnose_bus bit 2-1 = rx_frame_stat_lmac.rx_sa_mode - * diagnose_bus bit 0 = rx_mac_sof_e - * - * 0x1b diagnose_bus bit 7 = execute_sa_match - * diagnose_bus bit 6-2 = fp_mac_addr_cnt - * diagnose_bus bit 1 = fp_bit_decided - * diagnose_bus bit 0 = prov_from_swio.Addr_tab_match_FP_value - * - * 0x1c diagnose_bus bit 7 = execute_sa_match - * diagnose_bus bit 6 = sa_match_found (1 clk delayed) - * diagnose_bus bit 5 = fp_mac_rdata(68): Short_LongNot - * diagnose_bus bit 4-1 = fp_mac_rdata(67 DOWNTO 64): SA valid bits - * diagnose_bus bit 0 = fp_mac_rdata(0): least significant bit from FPPR - * - * 0x1d diagnose_bus bit 7 = execute_sa_match - * diagnose_bus bit 6 = sa_match_found (1 clk delayed) - * diagnose_bus bit 5-0 = fp_mac_rdata(5 DOWNTO 0): 6 least significant bits from FPPR - * - * 0x1e-0x1f Not Used - * diagnose bus bit 7-0 = all '0' - * - * dbg_control in range 0x20 - 0x2f Debug tx pipeline - * 0x20 Top and bottom interfaces tx datapath - * diagnose_bus bit 7 = tx_mac_ld_strb - * diagnose bus bit 6 = tx_mac_drdy - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = symbol_ena - * - * 0x21 Control signals for tx datapath - * diagnose_bus bit 7 = TxTransparentMode - * diagnose bus bit 6 = ctrl_lmac_to_tx.CRC16_ena - * diagnose bus bit 5 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose bus bit 3 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 2-1 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose bus bit 0 = tx_valid - * - * 0x22 Control signals for wakeup frames - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 5-1 = ctrl_lmac_to_tx.gen_wu_RZ(4 DOWNTO 0) - * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero - * - * 0x23 Data signals for wakeup frame - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero - * - * 0x24 Data and control ack frame - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_ack - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = symbol_ena - * - * 0x25 FP bit decision - * diagnose_bus bit 7 = fp_bit_decided - * diagnose bus bit 6 = execute_sa_match - * diagnose bus bit 5 = ctrl_lmac_to_tx.rx_fp_decided - * diagnose bus bit 4-3 = ctrl_lmac_to_tx.rx_sa_mode - * diagnose bus bit 2 = swio_to_lmac_tx.FP_override - * diagnose bus bit 1 = swio_to_lmac_tx.FP_force_value - * diagnose bus bit 0 = tx_valid - * - * 0x2a Event counter, 8 least significant bits, synchronized to mac_clk - * - * 0x2b symbol counter, 8 fore most least significant bits (15 downto 8) - * - * 0x2c symbol counter, 8 least significant bits (7 downto 0) - * - * - * dbg_control in range 0x2e - 0x3f Debug lmac_controller - * 0x2d Not Used - * diagnose bus bit 7-0 = all '0' - * - * 0x23 Phy_transaction last minute changes due to corner cases - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = symbol_timer_preset - * diagnose_bus bit 5 = symbol_timer_almost_ready - * diagnose_bus bit 4 = csl_idle_rx - * diagnose_bus bit 3 = csl_data_rx - * diagnose_bus bit 2 = rx_enable_os_capt - * diagnose_bus bit 1 = rx_enable_os_capt_done - * diagnose_bus bit 0 = phy_en_ready - * - * 0x2f Phy control in combination with arbiter state machine - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = arb_phy_trans_res_store - * diagnose_bus bit 5-0 = arb_debug_info - * - * 0x30 Phy signals - * diagnose_bus bit 7 = phy_en - * diagnose bus bit 6 = tx_en - * diagnose bus bit 5 = rx_en - * diagnose bus bit 4-1 = phyattr(3 downto 0) - * diagnose bus bit 0 = ed_request - * - * 0x31 Phy enable and detailed statemachine info - * diagnose_bus bit 7 = phy_en - * diagnose bus bit 6-0 = prt statements detailed statemachine info - * 0 Reset - * 1 MAIN_STATE_IDLE TX_ACKnowledgement frame skip CSMA_CA - * 2 MAIN_STATE_IDLE : Wake-Up frame resides in buffer no - * 3 MAIN_STATE_IDLE : TX frame in TSCH mode - * 4 MAIN_STATE_IDLE : TX frame - * 5 MAIN_STATE_IDLE : goto SINGLE_CCA - * 6 MAIN_STATE_IDLE : goto Energy Detection - * 7 MAIN_STATE_IDLE : goto RX - * 8 MAIN_STATE_IDLE de-assert phy_en wait for - * 9 MAIN_STATE_IDLE Start phy_en and assert phy_en wait for : - * 10 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA framenr : - * 11 MAIN_STATE_CSMA_CA framenr : - * 12 MAIN_STATE_CSMA_CA start CSMA_CA - * 14 MAIN_STATE_CSMA_CA skip CSMA_CA - * 15 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed for CSL mode - * 16 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed - * 17 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Success - * 18 MAIN_STATE_SINGLE_CCA cca failed - * 19 MAIN_STATE_SINGLE_CCA cca ok - * 20 MAIN_STATE_WAIT_ACK_DELAY wait time elapsed - * 21 MAIN_STATE_WAIT ACK_DELAY : Send Ack in TSCH mode - * 22 MAIN_STATE_WAIT ACK_DELAY : Ack not scheduled in time in TSCH mode - * 23 MAIN_STATE_TSCH_TX_FRAME macTSRxTx time elapsed - * 24 MAIN_STATE_TX_FRAME it is CSL mode, start the WU seq for macWUPeriod - * 25 MAIN_STATE_TX_FRAME1 - * 26 MAIN_STATE_TX_FRAME_W1 exit, waited for : - * 27 MAIN_STATE_TX_FRAME_W2 exit, waited for : - * 28 MAIN_STATE_TX_WAIT_LAST_SYMBOL exit - * 29 MAIN_STATE_TX_RAMPDOWN_W exit, waited for : - * 30 MAIN_STATE_TX_PHYTRXWAIT exit, waited for : - * 31 MAIN_STATE_GEN_IFS , Ack with frame pending received - * 32 MAIN_STATE_GEN_IFS , Ack requested but DisRXackReceivedca is set - * 33 MAIN_STATE_GEN_IFS , instead of generating an IFS, switch the rx-on for an ACK - * 34 MAIN_STATE_GEN_IFS , generating an SIFS (Short Inter Frame Space) - * 35 MAIN_STATE_GEN_IFS , generating an LIFS (Long Inter Frame Space) - * 36 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'cslperiod_timer_ready' is ready sent the data frame - * 37 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'Rendezvous zero time not yet transmitted sent another WU frame - * 38 MAIN_STATE_GEN_IFS_FINISH exit, corrected for : - * 39 MAIN_STATE_GEN_IFS_FINISH in CSL mode, rx_resume_after_tx is set - * 40 MAIN_STATE_SENT_STATUS CSLMode wu_sequence_done_flag : - * 41 MAIN_STATE_ADD_DELAY exit, goto RX for frame pending time - * 42 MAIN_STATE_ADD_DELAY exit, goto IDLE - * 43 MAIN_STATE_RX switch the RX from off to on - * 44 MAIN_STATE_RX_WAIT_PHYRXSTART waited for - * 45 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the MacAckDuration timer - * 46 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the ack wait timer - * 47 MAIN_STATE_RX_WAIT_PHYRXLATENCY NORMAL mode : start rx_duration - * 48 MAIN_STATE_RX_WAIT_PHYRXLATENCY TSCH mode : start macTSRxWait (macTSRxWait) timer - * 49 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration (macCSLsamplePeriod) timer - * 50 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration (macCSLdataPeriod) timer - * 51 MAIN_STATE_RX_CHK_EXPIRED 1 ackwait_timer_ready or ack_received_ind - * 52 MAIN_STATE_RX_CHK_EXPIRED 2 normal_mode. ACK with FP bit set, start frame pending timer - * 54 MAIN_STATE_RX_CHK_EXPIRED 4 RxAlwaysOn is set to 0 - * 55 MAIN_STATE_RX_CHK_EXPIRED 5 TSCH mode valid frame rxed - * 56 MAIN_STATE_RX_CHK_EXPIRED 6 TSCH mode macTSRxwait expired - * 57 MAIN_STATE_RX_CHK_EXPIRED 7 macCSLsamplePeriod timer ready - * 58 MAIN_STATE_RX_CHK_EXPIRED 8 csl_mode. Data frame recieved with FP bit set, increment RX duration time - * 59 MAIN_STATE_RX_CHK_EXPIRED 9 CSL mode : Received wu frame in data listening period restart macCSLdataPeriod timer - * 60 MAIN_STATE_RX_CHK_EXPIRED 10 csl_rx_duration_ready or csl data frame received: - * 61 MAIN_STATE_RX_CHK_EXPIRED 11 normal_mode. FP bit is set, start frame pending timer - * 62 MAIN_STATE_RX_CHK_EXPIRED 12 normal mode rx_duration_timer_ready and frame_pending_timer_ready - * 63 MAIN_STATE_RX_CHK_EXPIRED 13 acknowledge frame requested - * 64 MAIN_STATE_RX_CHK_EXPIRED 14 Interrupt to sent a frame. found_tx_packet - * 65 MAIN_STATE_CSL_RX_IDLE_END RZ time is far away, switch receiver Off and wait for csl_rx_rz_time before switching on - * 66 MAIN_STATE_CSL_RX_IDLE_END RZ time is not so far away, keep receiver On and wait for - * 67 MAIN_STATE_RX_START_PHYRXSTOP ack with fp received keep rx on - * 68 MAIN_STATE_RX_START_PHYRXSTOP switch the RX from on to off - * 69 MAIN_STATE_RX_WAIT_PHYRXSTOP acknowledge done : switch back to finish TX - * 70 MAIN_STATE_RX_WAIT_PHYRXSTOP switch the RX off - * 71 MAIN_STATE_ED switch the RX from off to on - * 72 MAIN_STATE_ED_WAIT_PHYRXSTART waited for phyRxStartup - * 73 MAIN_STATE_ED_WAIT_EDSCANDURATION waited for EdScanDuration - * 74 MAIN_STATE_ED_WAIT_PHYRXSTOP end of Energy Detection, got IDLE - * 75 MAIN_STATE_IDLE, use_legacy_phy_en = '0', rx_enable_os_capt detected and not yet 1 us 101 of PHY_EN done. - * 76 - 127 Not used - * - * 0x32 RX enable and detailed statemachine info - * diagnose_bus bit 7 = rx_en - * diagnose bus bit 6-0 = detailed statemachine info see dbg_control = 0x31 - * - * 0x33 TX enable and detailed statemachine info - * diagnose_bus bit 7 = tx_en - * diagnose bus bit 6-0 = detailed statemachine info see dbg_control = 0x31 - * - * 0x34 Phy enable, TX enable and Rx enable and state machine states - * diagnose_bus bit 7 = phy_en - * diagnose_bus bit 6 = tx_en - * diagnose_bus bit 5 = rx_en - * diagnose bus bit 4-0 = State machine states - * 1 MAIN_STATE_IDLE - * 2 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA - * 3 MAIN_STATE_CSMA_CA - * 4 MAIN_STATE_WAIT_FOR_CSMA_CA_0 - * 5 MAIN_STATE_WAIT_FOR_CSMA_CA - * 6 MAIN_STATE_SINGLE_CCA - * 7 MAIN_STATE_WAIT_ACK_DELAY - * 8 MAIN_STATE_TSCH_TX_FRAME - * 9 MAIN_STATE_TX_FRAME - * 10 MAIN_STATE_TX_FRAME1 - * 11 MAIN_STATE_TX_FRAME_W1 - * 12 MAIN_STATE_TX_FRAME_W2 - * 13 MAIN_STATE_TX_WAIT_LAST_SYMBOL - * 14 MAIN_STATE_TX_RAMPDOWN - * 15 MAIN_STATE_TX_RAMPDOWN_W - * 16 MAIN_STATE_TX_PHYTRXWAIT - * 17 MAIN_STATE_GEN_IFS - * 18 MAIN_STATE_GEN_IFS_FINISH - * 19 MAIN_STATE_SENT_STATUS - * 20 MAIN_STATE_ADD_DELAY - * 21 MAIN_STATE_TSCH_RX_ACKDELAY - * 22 MAIN_STATE_RX - * 23 MAIN_STATE_RX_WAIT_PHYRXSTART - * 24 MAIN_STATE_RX_WAIT_PHYRXLATENCY - * 25 MAIN_STATE_RX_CHK_EXPIRED - * 26 MAIN_STATE_CSL_RX_IDLE_END - * 27 MAIN_STATE_RX_START_PHYRXSTOP - * 28 MAIN_STATE_RX_WAIT_PHYRXSTOP - * 29 MAIN_STATE_ED - * 30 MAIN_STATE_ED_WAIT_PHYRXSTART - * 31 MAIN_STATE_ED_WAIT_EDSCANDURATION - * - * 0x35 lmac controller to tx interface with wakeup - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen_wu - * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start - * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol - * - * 0x36 lmac controller to tx interface with frame pending - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen.fp_bit - * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start - * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol - * - * 0x37 rx pipepline to lmac controller interface - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_rx_to_lmac.rx_sof_e - * diagnose_bus bit 4 = ctrl_rx_to_lmac.rx_eof_e - * diagnose_bus bit 3 = ctrl_rx_to_lmac.packet_valid - * diagnose_bus bit 2 = ack_received_ind - * diagnose_bus bit 1 = ack_request_ind - * diagnose_bus bit 0 = ctrl_rx_to_lmac.data_request_frame - * - * 0x38 csl start - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = csl_start - * diagnose_bus bit 4-1 = swio_always_on_to_lmac_ctrl.tx_flag_stat - * diagnose_bus bit 0 = found_wu_packet; - * - * 0x39 Tsch TX ack timing - * diagnose_bus bit 7-4 = swio_always_on_to_lmac_ctrl.tx_flag_stat - * diagnose_bus bit 3 = tx_en - * diagnose_bus bit 2 = rx_en - * diagnose_bus bit 1 = ctrl_rx_to_lmac.packet_valid - * diagnose_bus bit 0 = one_us_timer_ready - * - * 0x3a Phy control and Phy status - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = phy_en - * diagnose_bus bit 5 = rx_en - * diagnose_bus bit 4 = tx_en - * diagnose_bus bit 3 = cca_stat - * diagnose bus bit 2 = ed_request - * diagnose bus bit 1 = rx_enable_os_capt - * diagnose bus bit 0 = found_tx_packet - * - * 0x3b Phy control, incl old PHY_EN (to show the improvement using v2) - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = phy_en - * diagnose_bus bit 5 = rx_en - * diagnose_bus bit 4 = tx_en - * diagnose_bus bit 3-0 = pti - * - * 0x3c Control signals for arbiter control state machine - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = arb_phy_trans_set_store - * diagnose_bus bit 5 = arb_phy_trans_clr_store - * diagnose_bus bit 4 = arb_phy_trans_res_store - * diagnose_bus bit 3 = found_tx_packet - * diagnose bus bit 2 = found_tx_packet_next - * diagnose bus bit 1 = found_wu_packet - * diagnose bus bit 0 = req_for_ack_flag - * - * 0x3d Output of check which packet to send - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = LmacReady4sleep - * diagnose_bus bit 5-4 = found_tx_number - * diagnose_bus bit 3-2 = found_tx_number_next - * diagnose bus bit 1-0 = found_wu_number - * - * 0x3e CSMA_CA and timer control - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = Csma_ca_resume_stat - * diagnose_bus bit 5 = SingleCCA_os_capt - * diagnose_bus bit 4 = backoff_timer_preset - * diagnose_bus bit 3 = backoff_timer_almost_ready - * diagnose bus bit 2 = backoff_timer_ready - * diagnose bus bit 1 = arb_timer_preset - * diagnose bus bit 0 = arb_timer_ready - * - * 0x3f arbiter control state machine - * diagnose_bus bit 7 = phy_transaction - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = arb_phy_trans_set_store - * diagnose_bus bit 4 = arb_phy_trans_clr_store - * diagnose_bus bit 3 = arb_phy_trans_res_store - * diagnose bus bit 2-0 = arb_state_info - * - * - * dbg_control in range 0x40 - 0x4f Debug security - * 0x40 Security control - * diagnose_bus bit 7 = swio_to_security.secStart - * diagnose_bus bit 6 = swio_to_security.secTxRxn - * diagnose_bus bit 5 = swio_to_security.secAbort - * diagnose_bus bit 4 = swio_to_security.secEncDecn - * diagnose_bus bit 3 = swio_from_security.secBusy - * diagnose_bus bit 2 = swio_from_security.secAuthFail - * diagnose_bus bit 1 = swio_from_security.secReady_e - * diagnose_bus bit 0 = '0' - * - * 0x41 Security ctlid access rx and tx - * diagnose_bus bit 7 = tx_sec_ci.ld_strb - * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = tx_sec_ci.selectp - * diagnose_bus bit 4 = tx_sec_co.d_rdy - * diagnose_bus bit 3 = rx_sec_ci.ld_strb - * diagnose_bus bit 2 = rx_sec_ci.ctlid_rw - * diagnose_bus bit 1 = rx_sec_ci.selectp - * diagnose_bus bit 0 = rx_sec_co.d_rdy - * - * 0x42 Security ctlid access tx with sec_wr_data_valid - * diagnose_bus bit 7 = tx_sec_ci.ld_strb - * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = tx_sec_ci.selectp - * diagnose_bus bit 4 = tx_sec_co.d_rdy - * diagnose_bus bit 3-0 = sec_wr_data_valid - * - * 0x43 Security ctlid access rx with sec_wr_data_valid - * diagnose_bus bit 7 = rx_sec_ci.ld_strb - * diagnose_bus bit 6 = rx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = rx_sec_ci.selectp - * diagnose_bus bit 4 = rx_sec_co.d_rdy - * diagnose_bus bit 3-0 = sec_wr_data_valid - * - * 0x44-0x4f Not used - * diagnose bus bit 7 - 0 = all '0' - * - * dbg_control in range 0x50 - 0x5f AHB bus - * 0x50 ahb bus without hsize - * diagnose_bus bit 7 = hsel - * diagnose_bus bit 6-5 = htrans - * diagnose_bus bit 4 = hwrite - * diagnose_bus bit 3 = hready_in - * diagnose_bus bit 2 = hready_out - * diagnose_bus bit 1-0 = hresp - * - * 0x51 ahb bus without hwready_in and hresp(1) - * diagnose_bus bit 7 = hsel - * diagnose_bus bit 6-5 = htrans - * diagnose_bus bit 4 = hwrite - * diagnose_bus bit 3-2 = hhsize(1 downto 0) - * diagnose_bus bit 1 = hready_out - * diagnose_bus bit 0 = hresp(0) - * - * 0x52 Amba tx signals - * diagnose_bus bit 7 = ai_tx.penable - * diagnose_bus bit 6 = ai_tx.psel - * diagnose_bus bit 5 = ai_tx.pwrite - * diagnose_bus bit 4 = ao_tx.pready - * diagnose_bus bit 3 = ao_tx.pslverr - * diagnose_bus bit 2-1 = psize_tx - * diagnose_bus bit 0 = hready_out - * - * 0x53 Amba rx signals - * diagnose_bus bit 7 = ai_rx.penable - * diagnose_bus bit 6 = ai_rx.psel - * diagnose_bus bit 5 = ai_rx.pwrite - * diagnose_bus bit 4 = ao_rx.pready - * diagnose_bus bit 3 = ao_rx.pslverr - * diagnose_bus bit 2-1 = psize_rx - * diagnose_bus bit 0 = hready_out - * - * 0x54 Amba register map signals - * diagnose_bus bit 7 = ai_reg.penable - * diagnose_bus bit 6 = ai_reg.psel - * diagnose_bus bit 5 = ai_reg.pwrite - * diagnose_bus bit 4 = ao_reg.pready - * diagnose_bus bit 3 = ao_reg.pslverr - * diagnose_bus bit 2-1 = "00" - * diagnose_bus bit 0 = hready_out - * - * 0x55-0x5f Not used - * diagnose bus bit 7 - 0 = all '0' - */ -#define IND_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL -#define MSK_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 0xff -#define OFF_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 8 - -/* - * - * REGISTER: ftdf_on_off_regmap_txbyte_e - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x40090394 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_txbyte_e - * - * If set to '1', it indicates the first byte of a frame is transmitted - * This event bit contributes to ftdf_ce[4]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBYTE_E IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 1 -/* - * - * Bit: ftdf_on_off_regmap_tx_last_symbol_e - * - * If set to '1', it indicates the last symbol of a frame is transmitted - * This event bit contributes to ftdf_ce[4]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_txbyte_m - * - * Initialization value: 0x0 Initialization mask: 0x3 - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x40090398 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x3 - -/* - * - * Bit: ftdf_on_off_regmap_txbyte_m - * - * Mask bit for event "txbyte_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TXBYTE_M IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M -#define MSK_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 1 -/* - * - * Bit: ftdf_on_off_regmap_tx_last_symbol_m - * - * Mask bit for event "tx_last_symbol_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 0x2 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 1 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_flag_s - * - * Initialization value: none. - * Access mode: S-R (state - read) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x40090400 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x1 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_S_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_S_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_STAT_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_STAT_INTVL 0x20 - -/* - * - * Bit: ftdf_on_off_regmap_tx_flag_stat - * - * Tx meta data per entry: if set to '1', the packet is ready for transmission - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_flag_clear_e - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: E-RCW (event read/clear on write 1) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x40090404 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x1 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_INTVL 0x20 - -/* - * - * Bit: ftdf_on_off_regmap_tx_flag_clear_e - * - * Tx meta data per entry: if set to '1' the LMAC hardware has cleared the tx_flag_stat status. - * This event bit contributes to ftdf_ce[4]. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_flag_clear_m - * - * Initialization value: 0x0 Initialization mask: 0x1 - * Access mode: EM-RW (event mask) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x40090408 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x1 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_INTVL 0x20 - -/* - * - * Bit: ftdf_on_off_regmap_tx_flag_clear_m - * - * Tx meta data per entry: Mask bit for event "tx_flag_clear_e". - * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x1 -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 1 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_priority - * - * Initialization value: 0x0 Initialization mask: 0xf1f - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0x40090410 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0xf1f -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_ISWAKEUP_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_ISWAKEUP_INTVL 0x20 -#define FTDF_ON_OFF_REGMAP_PTI_TX_NUM 0x4 -#define FTDF_ON_OFF_REGMAP_PTI_TX_INTVL 0x20 - -/* - * - * Field: ftdf_on_off_regmap_tx_priority - * - * Tx meta data per entry: Priority of packet - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0xf -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 4 -/* - * - * Bit: ftdf_on_off_regmap_IsWakeUp - * - * Tx meta data per entry: A basic wake-up frame can be generated by the UMAC in the Tx buffer. - * The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_ISWAKEUP IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY -#define MSK_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 0x10 -#define OFF_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 4 -#define SIZE_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 1 -/* - * - * Field: ftdf_on_off_regmap_pti_tx - * - * This register has 4 entries, belonging to the entry of the Tx frame to send, to be used during transmitting frames and the CMSA-CA phase before (when requested). - * In TSCH mode this register shall be used during the time slot in which frames can be transmitted and consequently an Enhanced ACK can be received. - * Since pti_tx belongs to a certain frame to be transmitted, pti_tx can be considered as extra Tx meta data. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_PTI_TX IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY -#define MSK_F_FTDF_ON_OFF_REGMAP_PTI_TX 0xf00 -#define OFF_F_FTDF_ON_OFF_REGMAP_PTI_TX 8 -#define SIZE_F_FTDF_ON_OFF_REGMAP_PTI_TX 4 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_set_os - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0x40090480 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0xf - -/* - * - * Field: ftdf_on_off_regmap_tx_flag_set - * - * Tx meta data per entry: if set to '1', the tx_flag_stat will be set to '1'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET IND_R_FTDF_ON_OFF_REGMAP_TX_SET_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 0xf -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 4 - -/* - * - * REGISTER: ftdf_on_off_regmap_tx_clear_os - * - * Initialization value: 0x0 Initialization mask: 0xf - * Access mode: OS-W (one-shot - write) - */ -#define IND_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0x40090484 -#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0x4 -#define MSK_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0xf - -/* - * - * Field: ftdf_on_off_regmap_tx_flag_clear - * - * Tx meta data per entry: if set to '1', the tx_flag_stat will be cleared to '0'. - */ -#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR IND_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS -#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 0xf -#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 0 -#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 4 - -/* - * - * REGISTER: ftdf_always_on_regmap_wakeup_control - * - * Initialization value: 0x40000000 Initialization mask: 0xe1ffffff - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0x40091000 -#define SIZE_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0x4 -#define MSK_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0xe1ffffff - -/* - * - * Field: ftdf_always_on_regmap_WakeUpIntThr - * - * Threshold for wake-up interrupt. When WakeUpEnable is set to '1' and the Wake-up (event) counter matches this value, the interrupt WAKEUP_IRQ is set to '1' for the duration of one LP_CLK period. - */ -#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL -#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0x1ffffff -#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0 -#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 25 -/* - * - * Bit: ftdf_always_on_regmap_WakeUpEnable - * - * If set to '1', the WakeUpIntThr is enabled to generate an WAKEUP_IRQ interrupt. - */ -#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL -#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 0x20000000 -#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 29 -#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 1 -/* - * - * Field: ftdf_always_on_regmap_WakeUp_mode - * - * The Control register WakeUp_mode controls the behavior of the Event counter: - * 0d = off, 1d = free running (default), 2d = one shot with auto clear, 3d = configurable period (timer - * mode). - */ -#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL -#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE 0xc0000000 -#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE 30 -#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE 2 - -/* - * - * REGISTER: ftdf_fp_processing_ram_long_addr_0 - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 0x40092000 -#define SIZE_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 0x4 -#define MSK_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 0xffffffff -#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_0_NUM 0x18 -#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_0_INTVL 0x10 -#define FTDF_FP_PROCESSING_RAM_EXP_SA_L_NUM 0x18 -#define FTDF_FP_PROCESSING_RAM_EXP_SA_L_INTVL 0x10 - -/* - * - * Field: ftdf_fp_processing_ram_Exp_SA_l - * - * Lowest part of the 64 bits long source address or SA entry 1 resp. SA entry 0 in case of short source address. - */ -#define IND_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 -#define MSK_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L 0xffffffff -#define OFF_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L 0 -#define SIZE_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L 32 - -/* - * - * REGISTER: ftdf_fp_processing_ram_long_addr_1 - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 0x40092004 -#define SIZE_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 0x4 -#define MSK_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 0xffffffff -#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_1_NUM 0x18 -#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_1_INTVL 0x10 -#define FTDF_FP_PROCESSING_RAM_EXP_SA_H_NUM 0x18 -#define FTDF_FP_PROCESSING_RAM_EXP_SA_H_INTVL 0x10 - -/* - * - * Field: ftdf_fp_processing_ram_Exp_SA_h - * - * Highest part of the 64 bits long source address or SA entry 3 resp. SA entry 2 in case of short source address. - */ -#define IND_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 -#define MSK_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H 0xffffffff -#define OFF_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H 0 -#define SIZE_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H 32 - -/* - * - * REGISTER: ftdf_fp_processing_ram_size_and_val - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) - */ -#define IND_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL 0x40092008 -#define SIZE_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL 0x4 -#define MSK_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL 0x1f -#define FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL_NUM 0x18 -#define FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL_INTVL 0x10 -#define FTDF_FP_PROCESSING_RAM_VALID_SA_NUM 0x18 -#define FTDF_FP_PROCESSING_RAM_VALID_SA_INTVL 0x10 -#define FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT_NUM 0x18 -#define FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT_INTVL 0x10 - -/* - * - * Field: ftdf_fp_processing_ram_Valid_SA - * - * Indication which SA entry is valid (if set). In case of 4 short SA Valid bit 3 belongs to SA entry 3 etc. - * In case of a long SA Valid bit 0 is the valid indication. - */ -#define IND_F_FTDF_FP_PROCESSING_RAM_VALID_SA IND_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL -#define MSK_F_FTDF_FP_PROCESSING_RAM_VALID_SA 0xf -#define OFF_F_FTDF_FP_PROCESSING_RAM_VALID_SA 0 -#define SIZE_F_FTDF_FP_PROCESSING_RAM_VALID_SA 4 -/* - * - * Bit: ftdf_fp_processing_ram_Short_LongNot - * - * A '1' indicates that Exp_SA contains four short SA's, a '0' indicates one long SA. - */ -#define IND_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT IND_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL -#define MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT 0x10 -#define OFF_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT 4 -#define SIZE_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT 1 -#endif // dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -#endif // _ftdf diff --git a/third_party/dialog/DialogTools/cli_programmer b/third_party/dialog/DialogTools/cli_programmer index 379551d07..0db5c2e0c 100755 Binary files a/third_party/dialog/DialogTools/cli_programmer and b/third_party/dialog/DialogTools/cli_programmer differ