From 5b5a3f6d9ea4086235d2db77cd93f5189c975019 Mon Sep 17 00:00:00 2001 From: Jonathan Hui Date: Thu, 1 Apr 2021 08:12:12 -0700 Subject: [PATCH] [kw41z] move to openthread/ot-kw41z (#6386) --- configure.ac | 11 +- examples/Makefile-kw41z | 261 - examples/platforms/Makefile.am | 6 +- examples/platforms/Makefile.platform.am | 4 - examples/platforms/kw41z/CMakeLists.txt | 91 - examples/platforms/kw41z/MKW41Z512xxx4.ld | 242 - examples/platforms/kw41z/Makefile.am | 110 - examples/platforms/kw41z/Makefile.platform.am | 39 - examples/platforms/kw41z/README.md | 129 +- examples/platforms/kw41z/alarm.c | 103 - examples/platforms/kw41z/arm-none-eabi.cmake | 42 - examples/platforms/kw41z/diag.c | 84 - examples/platforms/kw41z/entropy.c | 74 - examples/platforms/kw41z/flash.c | 92 - examples/platforms/kw41z/logging.c | 47 - examples/platforms/kw41z/misc.c | 93 - .../openthread-core-kw41z-config-check.h | 36 - .../kw41z/openthread-core-kw41z-config.h | 105 - examples/platforms/kw41z/platform-kw41z.h | 84 - examples/platforms/kw41z/radio.c | 1033 -- examples/platforms/kw41z/system.c | 125 - examples/platforms/kw41z/uart.c | 206 - script/check-arm-build-autotools | 16 - script/check-arm-build-cmake | 7 - script/cmake-build | 4 +- third_party/CMakeLists.txt | 4 +- .../nxp/CMSIS/Include/arm_common_tables.h | 136 - .../nxp/CMSIS/Include/arm_const_structs.h | 79 - third_party/nxp/CMSIS/Include/arm_math.h | 7154 --------- third_party/nxp/CMSIS/Include/cmsis_armcc.h | 734 - .../nxp/CMSIS/Include/cmsis_armcc_V6.h | 1800 --- third_party/nxp/CMSIS/Include/cmsis_gcc.h | 1373 -- third_party/nxp/CMSIS/Include/core_cm0.h | 798 - third_party/nxp/CMSIS/Include/core_cm0plus.h | 914 -- third_party/nxp/CMSIS/Include/core_cm3.h | 1763 --- third_party/nxp/CMSIS/Include/core_cm4.h | 1937 --- third_party/nxp/CMSIS/Include/core_cm7.h | 2512 --- third_party/nxp/CMSIS/Include/core_cmFunc.h | 87 - third_party/nxp/CMSIS/Include/core_cmInstr.h | 87 - third_party/nxp/CMSIS/Include/core_cmSimd.h | 96 - third_party/nxp/CMSIS/Include/core_sc000.h | 926 -- third_party/nxp/CMSIS/Include/core_sc300.h | 1745 --- third_party/nxp/CMakeLists.txt | 86 - third_party/nxp/MKW41Z4/MKW41Z4.h | 13023 ---------------- third_party/nxp/MKW41Z4/MKW41Z4_features.h | 2020 --- .../MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.c | 212 - .../MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.h | 157 - .../cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c | 207 - .../cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c | 201 - .../cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c | 623 - .../fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c | 353 - .../fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c | 341 - .../fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c | 356 - .../fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c | 341 - .../fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c | 340 - .../fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c | 353 - .../fsl_xcvr_mode_datarate_config.c | 212 - .../cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c | 343 - .../cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c | 244 - .../nxp/MKW41Z4/XCVR/dbg_ram_capture.c | 160 - .../nxp/MKW41Z4/XCVR/dbg_ram_capture.h | 206 - third_party/nxp/MKW41Z4/XCVR/dma_capture.c | 273 - third_party/nxp/MKW41Z4/XCVR/dma_capture.h | 194 - third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.c | 2132 --- third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.h | 1236 -- third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.c | 995 -- third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.h | 132 - third_party/nxp/MKW41Z4/XCVR/ifr_radio.c | 532 - third_party/nxp/MKW41Z4/XCVR/ifr_radio.h | 199 - third_party/nxp/MKW41Z4/clock_config.c | 302 - third_party/nxp/MKW41Z4/clock_config.h | 77 - .../MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.c | 1696 -- .../MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.h | 71 - .../nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.c | 1996 --- .../nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.h | 79 - .../MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.c | 2970 ---- .../MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.h | 105 - third_party/nxp/MKW41Z4/drivers/fsl_adc16.c | 370 - third_party/nxp/MKW41Z4/drivers/fsl_adc16.h | 525 - third_party/nxp/MKW41Z4/drivers/fsl_clock.c | 1374 -- third_party/nxp/MKW41Z4/drivers/fsl_clock.h | 1191 -- third_party/nxp/MKW41Z4/drivers/fsl_cmp.c | 285 - third_party/nxp/MKW41Z4/drivers/fsl_cmp.h | 343 - third_party/nxp/MKW41Z4/drivers/fsl_cmt.c | 265 - third_party/nxp/MKW41Z4/drivers/fsl_cmt.h | 401 - third_party/nxp/MKW41Z4/drivers/fsl_common.c | 176 - third_party/nxp/MKW41Z4/drivers/fsl_common.h | 348 - third_party/nxp/MKW41Z4/drivers/fsl_cop.c | 77 - third_party/nxp/MKW41Z4/drivers/fsl_cop.h | 187 - third_party/nxp/MKW41Z4/drivers/fsl_dac.c | 220 - third_party/nxp/MKW41Z4/drivers/fsl_dac.h | 378 - third_party/nxp/MKW41Z4/drivers/fsl_dmamux.c | 93 - third_party/nxp/MKW41Z4/drivers/fsl_dmamux.h | 200 - third_party/nxp/MKW41Z4/drivers/fsl_dspi.c | 1669 -- third_party/nxp/MKW41Z4/drivers/fsl_dspi.h | 1180 -- .../nxp/MKW41Z4/drivers/fsl_dspi_edma.c | 1248 -- .../nxp/MKW41Z4/drivers/fsl_dspi_edma.h | 281 - .../nxp/MKW41Z4/drivers/fsl_dspi_freertos.c | 121 - .../nxp/MKW41Z4/drivers/fsl_dspi_freertos.h | 128 - third_party/nxp/MKW41Z4/drivers/fsl_edma.c | 1754 --- third_party/nxp/MKW41Z4/drivers/fsl_edma.h | 910 -- third_party/nxp/MKW41Z4/drivers/fsl_flash.c | 3539 ----- third_party/nxp/MKW41Z4/drivers/fsl_flash.h | 1387 -- third_party/nxp/MKW41Z4/drivers/fsl_gpio.c | 195 - third_party/nxp/MKW41Z4/drivers/fsl_gpio.h | 440 - third_party/nxp/MKW41Z4/drivers/fsl_i2c.c | 1757 --- third_party/nxp/MKW41Z4/drivers/fsl_i2c.h | 794 - .../nxp/MKW41Z4/drivers/fsl_i2c_edma.c | 568 - .../nxp/MKW41Z4/drivers/fsl_i2c_edma.h | 132 - .../nxp/MKW41Z4/drivers/fsl_i2c_freertos.c | 121 - .../nxp/MKW41Z4/drivers/fsl_i2c_freertos.h | 128 - third_party/nxp/MKW41Z4/drivers/fsl_llwu.c | 404 - third_party/nxp/MKW41Z4/drivers/fsl_llwu.h | 320 - third_party/nxp/MKW41Z4/drivers/fsl_lptmr.c | 143 - third_party/nxp/MKW41Z4/drivers/fsl_lptmr.h | 370 - third_party/nxp/MKW41Z4/drivers/fsl_lpuart.c | 1297 -- third_party/nxp/MKW41Z4/drivers/fsl_lpuart.h | 814 - .../nxp/MKW41Z4/drivers/fsl_lpuart_edma.c | 341 - .../nxp/MKW41Z4/drivers/fsl_lpuart_edma.h | 190 - .../nxp/MKW41Z4/drivers/fsl_lpuart_freertos.c | 331 - .../nxp/MKW41Z4/drivers/fsl_lpuart_freertos.h | 165 - third_party/nxp/MKW41Z4/drivers/fsl_ltc.c | 4316 ----- third_party/nxp/MKW41Z4/drivers/fsl_ltc.h | 1584 -- .../nxp/MKW41Z4/drivers/fsl_ltc_edma.c | 1247 -- .../nxp/MKW41Z4/drivers/fsl_ltc_edma.h | 850 - third_party/nxp/MKW41Z4/drivers/fsl_pit.c | 125 - third_party/nxp/MKW41Z4/drivers/fsl_pit.h | 354 - third_party/nxp/MKW41Z4/drivers/fsl_pmc.c | 93 - third_party/nxp/MKW41Z4/drivers/fsl_pmc.h | 421 - third_party/nxp/MKW41Z4/drivers/fsl_port.h | 431 - third_party/nxp/MKW41Z4/drivers/fsl_rcm.c | 65 - third_party/nxp/MKW41Z4/drivers/fsl_rcm.h | 431 - third_party/nxp/MKW41Z4/drivers/fsl_rtc.c | 381 - third_party/nxp/MKW41Z4/drivers/fsl_rtc.h | 414 - third_party/nxp/MKW41Z4/drivers/fsl_sim.c | 53 - third_party/nxp/MKW41Z4/drivers/fsl_sim.h | 127 - third_party/nxp/MKW41Z4/drivers/fsl_smc.c | 400 - third_party/nxp/MKW41Z4/drivers/fsl_smc.h | 456 - third_party/nxp/MKW41Z4/drivers/fsl_tpm.c | 766 - third_party/nxp/MKW41Z4/drivers/fsl_tpm.h | 629 - third_party/nxp/MKW41Z4/drivers/fsl_trng.c | 1650 -- third_party/nxp/MKW41Z4/drivers/fsl_trng.h | 239 - third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.c | 203 - third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.h | 706 - .../nxp/MKW41Z4/fsl_device_registers.h | 56 - third_party/nxp/MKW41Z4/startup_MKW41Z4.S | 365 - third_party/nxp/MKW41Z4/system_MKW41Z4.c | 186 - third_party/nxp/MKW41Z4/system_MKW41Z4.h | 134 - 148 files changed, 9 insertions(+), 101789 deletions(-) delete mode 100644 examples/Makefile-kw41z delete mode 100644 examples/platforms/kw41z/CMakeLists.txt delete mode 100644 examples/platforms/kw41z/MKW41Z512xxx4.ld delete mode 100644 examples/platforms/kw41z/Makefile.am delete mode 100644 examples/platforms/kw41z/Makefile.platform.am delete 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third_party/nxp/MKW41Z4/drivers/fsl_rcm.h delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_rtc.c delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_rtc.h delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_sim.c delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_sim.h delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_smc.c delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_smc.h delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_tpm.c delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_tpm.h delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_trng.c delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_trng.h delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.c delete mode 100644 third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.h delete mode 100644 third_party/nxp/MKW41Z4/fsl_device_registers.h delete mode 100644 third_party/nxp/MKW41Z4/startup_MKW41Z4.S delete mode 100644 third_party/nxp/MKW41Z4/system_MKW41Z4.c delete mode 100644 third_party/nxp/MKW41Z4/system_MKW41Z4.h diff --git a/configure.ac b/configure.ac index ede3b17d9..d8ffc7d91 100644 --- a/configure.ac +++ b/configure.ac @@ -781,14 +781,14 @@ AC_MSG_CHECKING([whether to build examples]) AC_ARG_WITH(examples, [AS_HELP_STRING([--with-examples=TARGET], [Build example applications for one of: simulation, cc1352, cc2538, cc2650, cc2652, efr32mg1, efr32mg12, efr32mg13, efr32mg21, - jn5189, k32w061, kw41z, nrf52811, nrf52833, nrf52840 @<:@default=no@:>@. + jn5189, k32w061, nrf52811, nrf52833, nrf52840 @<:@default=no@:>@. Note that building example applications also builds the associated OpenThread platform libraries and any third_party libraries needed to support the examples.])], [ case "${with_examples}" in no) ;; - simulation|cc1352|cc2538|cc2650|cc2652|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|k32w061|kw41z|nrf52811|nrf52833|nrf52840) + simulation|cc1352|cc2538|cc2650|cc2652|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|k32w061|nrf52811|nrf52833|nrf52840) ;; *) AC_MSG_RESULT(ERROR) @@ -811,7 +811,6 @@ AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG13], [test "${with_examples}" = "efr3 AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG21], [test "${with_examples}" = "efr32mg21"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_JN5189], [test "${with_examples}" = "jn5189"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_K32W061], [test "${with_examples}" = "k32w061"]) -AM_CONDITIONAL([OPENTHREAD_EXAMPLES_KW41Z], [test "${with_examples}" = "kw41z"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52811], [test "${with_examples}" = "nrf52811"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52833], [test "${with_examples}" = "nrf52833"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52840], [test "${with_examples}" = "nrf52840"]) @@ -839,11 +838,11 @@ AC_MSG_CHECKING([whether to build platform libraries]) AC_ARG_WITH(platform, [AS_HELP_STRING([--with-platform=TARGET], [Build OpenThread platform libraries for one of: cc1352, cc2538, cc2650, cc2652, - efr32mg1, efr32mg12, efr32mg13, efr32mg21, jn5189, kw41z, nrf52811, nrf52833, nrf52840, posix, simulation @<:@default=simulation@:>@.])], + efr32mg1, efr32mg12, efr32mg13, efr32mg21, jn5189, nrf52811, nrf52833, nrf52840, posix, simulation @<:@default=simulation@:>@.])], [ # Make sure the given target is valid. case "${with_platform}" in - no|cc1352|cc2538|cc2650|cc2652|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|kw41z|nrf52811|nrf52833|nrf52840|posix|simulation) + no|cc1352|cc2538|cc2650|cc2652|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|nrf52811|nrf52833|nrf52840|posix|simulation) ;; *) AC_MSG_RESULT(ERROR) @@ -883,7 +882,6 @@ AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG12], [test "${with_platform}" = "efr3 AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG13], [test "${with_platform}" = "efr32mg13"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG21], [test "${with_platform}" = "efr32mg21"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_JN5189], [test "${with_platform}" = "jn5189"]) -AM_CONDITIONAL([OPENTHREAD_PLATFORM_KW41Z], [test "${with_platform}" = "kw41z"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_NRF52811], [test "${with_platform}" = "nrf52811"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_NRF52833], [test "${with_platform}" = "nrf52833"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_NRF52840], [test "${with_platform}" = "nrf52840"]) @@ -1040,7 +1038,6 @@ examples/platforms/efr32/sleepy-demo/Makefile examples/platforms/efr32/sleepy-demo/sleepy-demo-mtd/Makefile examples/platforms/efr32/sleepy-demo/sleepy-demo-ftd/Makefile examples/platforms/k32w/Makefile -examples/platforms/kw41z/Makefile examples/platforms/nrf528xx/Makefile examples/platforms/simulation/Makefile examples/platforms/utils/Makefile diff --git a/examples/Makefile-kw41z b/examples/Makefile-kw41z deleted file mode 100644 index ed06b3a89..000000000 --- a/examples/Makefile-kw41z +++ /dev/null @@ -1,261 +0,0 @@ -# -# Copyright (c) 2017, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -.NOTPARALLEL: - -AR = arm-none-eabi-ar -CCAS = arm-none-eabi-as -CPP = arm-none-eabi-cpp -CC = arm-none-eabi-gcc -CXX = arm-none-eabi-g++ -LD = arm-none-eabi-ld -STRIP = arm-none-eabi-strip -NM = arm-none-eabi-nm -RANLIB = arm-none-eabi-ranlib -OBJCOPY = arm-none-eabi-objcopy - -BuildJobs ?= 10 - -configure_OPTIONS = \ - --enable-cli \ - --enable-ftd \ - --enable-mtd \ - --enable-ncp \ - --enable-radio-only \ - --enable-linker-map \ - --with-examples=kw41z \ - $(NULL) - -TopSourceDir := $(dir $(shell readlink $(firstword $(MAKEFILE_LIST)))).. -AbsTopSourceDir := $(dir $(realpath $(firstword $(MAKEFILE_LIST)))).. - -KW41Z_CONFIG_FILE_CPPFLAGS = -DOPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-kw41z-config.h\"' -KW41Z_CONFIG_FILE_CPPFLAGS += -DOPENTHREAD_CORE_CONFIG_PLATFORM_CHECK_FILE='\"openthread-core-kw41z-config-check.h\"' -KW41Z_CONFIG_FILE_CPPFLAGS += -I$(AbsTopSourceDir)/examples/platforms/kw41z/ - -COMMONCFLAGS := \ - -fdata-sections \ - -ffunction-sections \ - -Os \ - -g \ - $(KW41Z_CONFIG_FILE_CPPFLAGS) \ - $(NULL) - -include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/common-switches.mk - -CPPFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CPPFLAGS) \ - $(NULL) - -CFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CFLAGS) \ - $(NULL) - -CXXFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CXXFLAGS) \ - -fno-exceptions \ - -fno-rtti \ - $(NULL) - -LDFLAGS += \ - $(COMMONCFLAGS) \ - $(target_LDFLAGS) \ - -specs=nano.specs \ - -specs=nosys.specs \ - -Wl,--gc-sections \ - $(NULL) - -ECHO := @echo -MAKE := make -MKDIR_P := mkdir -p -LN_S := ln -s -RM_F := rm -f - -INSTALL := /usr/bin/install -INSTALLFLAGS := -p - -BuildPath = build -TopBuildDir = $(BuildPath) -AbsTopBuildDir = $(PWD)/$(TopBuildDir) - -ResultPath = output -TopResultDir = $(ResultPath) -AbsTopResultDir = $(PWD)/$(TopResultDir) - -TargetTuple = kw41z - -ARCHS = cortex-m0plus - -TopTargetLibDir = $(TopResultDir)/$(TargetTuple)/lib - -ifndef BuildJobs -BuildJobs := $(shell getconf _NPROCESSORS_ONLN) -endif -JOBSFLAG := -j$(BuildJobs) - -# -# configure-arch -# -# Configure OpenThread for the specified architecture. -# -# arch - The architecture to configure. -# -define configure-arch -$(ECHO) " CONFIG $(TargetTuple)..." -(cd $(BuildPath)/$(TargetTuple) && $(AbsTopSourceDir)/configure \ -INSTALL="$(INSTALL) $(INSTALLFLAGS)" \ -CPP="$(CPP)" CC="$(CC)" CXX="$(CXX)" OBJC="$(OBJC)" OBJCXX="$(OBJCXX)" AR="$(AR)" RANLIB="$(RANLIB)" NM="$(NM)" STRIP="$(STRIP)" CPPFLAGS="$(CPPFLAGS)" CFLAGS="$(CFLAGS)" CXXFLAGS="$(CXXFLAGS)" LDFLAGS="$(LDFLAGS)" \ ---host=arm-none-eabi \ ---prefix=/ \ ---exec-prefix=/$(TargetTuple) \ -$(configure_OPTIONS)) -endef # configure-arch - -# -# build-arch -# -# Build the OpenThread intermediate build products for the specified -# architecture. -# -# arch - The architecture to build. -# -define build-arch -$(ECHO) " BUILD $(TargetTuple)" -$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \ -all -endef # build-arch - -# -# stage-arch -# -# Stage (install) the OpenThread final build products for the specified -# architecture. -# -# arch - The architecture to stage. -# -define stage-arch -$(ECHO) " STAGE $(TargetTuple)" -$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \ -DESTDIR=$(AbsTopResultDir) \ -install -endef # stage-arch - -# -# ARCH_template -# -# Define macros, targets and rules to configure, build, and stage the -# OpenThread for a single architecture. -# -# arch - The architecture to instantiate the template for. -# -define ARCH_template -CONFIGURE_TARGETS += configure-$(1) -BUILD_TARGETS += do-build-$(1) -STAGE_TARGETS += stage-$(1) -BUILD_DIRS += $(BuildPath)/$(TargetTuple) -DIRECTORIES += $(BuildPath)/$(TargetTuple) - -configure-$(1): target_CPPFLAGS=$($(1)_target_CPPFLAGS) -configure-$(1): target_CFLAGS=$($(1)_target_CFLAGS) -configure-$(1): target_CXXFLAGS=$($(1)_target_CXXFLAGS) -configure-$(1): target_LDFLAGS=$($(1)_target_LDFLAGS) - -configure-$(1): $(BuildPath)/$(TargetTuple)/config.status - -$(BuildPath)/$(TargetTuple)/config.status: | $(BuildPath)/$(TargetTuple) - $$(call configure-arch,$(1)) - -do-build-$(1): configure-$(1) - -do-build-$(1): - +$$(call build-arch,$(1)) - -stage-$(1): do-build-$(1) - -stage-$(1): | $(TopResultDir) - $$(call stage-arch,$(1)) - -$(1): stage-$(1) -endef # ARCH_template - -.DEFAULT_GOAL := all - -all: stage - -# -# cortex-m0plus -# - -cortex-m0plus_target_ABI = cortex-m0plus -cortex-m0plus_target_CPPFLAGS = -mcpu=cortex-m0plus -mfloat-abi=soft -mthumb -cortex-m0plus_target_CFLAGS = -mcpu=cortex-m0plus -mfloat-abi=soft -mthumb -cortex-m0plus_target_CXXFLAGS = -mcpu=cortex-m0plus -mfloat-abi=soft -mthumb -cortex-m0plus_target_LDFLAGS = -mcpu=cortex-m0plus -mfloat-abi=soft -mthumb - -# Instantiate an architecture-specific build template for each target -# architecture. - -$(foreach arch,$(ARCHS),$(eval $(call ARCH_template,$(arch)))) - -# -# Common / Finalization -# - -configure: $(CONFIGURE_TARGETS) - -build: $(BUILD_TARGETS) - -stage: $(STAGE_TARGETS) - -DIRECTORIES = $(TopResultDir) $(TopResultDir)/$(TargetTuple)/lib $(BUILD_DIRS) - -CLEAN_DIRS = $(TopResultDir) $(BUILD_DIRS) - -all: stage - -$(DIRECTORIES): - $(ECHO) " MKDIR $@" - @$(MKDIR_P) "$@" - -clean: - $(ECHO) " CLEAN" - @$(RM_F) -r $(CLEAN_DIRS) - -help: - $(ECHO) "Simply type 'make -f $(firstword $(MAKEFILE_LIST))' to build OpenThread for the following " - $(ECHO) "architectures: " - $(ECHO) "" - $(ECHO) " $(ARCHS)" - $(ECHO) "" - $(ECHO) "To build only a particular architecture, specify: " - $(ECHO) "" - $(ECHO) " make -f $(firstword $(MAKEFILE_LIST)) " - $(ECHO) "" diff --git a/examples/platforms/Makefile.am b/examples/platforms/Makefile.am index 21af57e20..5bdebd4fe 100644 --- a/examples/platforms/Makefile.am +++ b/examples/platforms/Makefile.am @@ -30,6 +30,7 @@ include $(abs_top_nlbuild_autotools_dir)/automake/pre.am EXTRA_DIST = \ gp712 \ + kw41z \ qpg6095 \ qpg6100 \ qpg7015m \ @@ -45,7 +46,6 @@ DIST_SUBDIRS = \ cc2652 \ efr32 \ k32w \ - kw41z \ nrf528xx \ simulation \ utils \ @@ -81,10 +81,6 @@ if OPENTHREAD_PLATFORM_K32W SUBDIRS += k32w endif -if OPENTHREAD_PLATFORM_KW41Z -SUBDIRS += kw41z -endif - if OPENTHREAD_PLATFORM_NRF528XX SUBDIRS += nrf528xx endif diff --git a/examples/platforms/Makefile.platform.am b/examples/platforms/Makefile.platform.am index 06cfcd936..88d3ea177 100644 --- a/examples/platforms/Makefile.platform.am +++ b/examples/platforms/Makefile.platform.am @@ -69,10 +69,6 @@ if OPENTHREAD_EXAMPLES_K32W061 include $(top_srcdir)/examples/platforms/k32w/k32w061/Makefile.platform.am endif -if OPENTHREAD_EXAMPLES_KW41Z -include $(top_srcdir)/examples/platforms/kw41z/Makefile.platform.am -endif - if OPENTHREAD_EXAMPLES_NRF52811 include $(top_srcdir)/examples/platforms/nrf528xx/nrf52811/Makefile.platform.am endif diff --git a/examples/platforms/kw41z/CMakeLists.txt b/examples/platforms/kw41z/CMakeLists.txt deleted file mode 100644 index 12fb1c5fe..000000000 --- a/examples/platforms/kw41z/CMakeLists.txt +++ /dev/null @@ -1,91 +0,0 @@ -# -# Copyright (c) 2020, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -set(OT_PLATFORM_LIB "openthread-kw41z" PARENT_SCOPE) - -if(NOT OT_CONFIG) - set(OT_CONFIG "openthread-core-kw41z-config.h") - set(OT_CONFIG ${OT_CONFIG} PARENT_SCOPE) -endif() - -list(APPEND OT_PLATFORM_DEFINES - "OPENTHREAD_CORE_CONFIG_PLATFORM_CHECK_FILE=\"openthread-core-kw41z-config-check.h\"" -) -set(OT_PLATFORM_DEFINES ${OT_PLATFORM_DEFINES} PARENT_SCOPE) - -list(APPEND OT_PLATFORM_DEFINES "OPENTHREAD_PROJECT_CORE_CONFIG_FILE=\"${OT_CONFIG}\"") - -add_library(openthread-kw41z - alarm.c - diag.c - entropy.c - flash.c - logging.c - misc.c - radio.c - system.c - uart.c -) - -set_target_properties( - openthread-kw41z - PROPERTIES - C_STANDARD 99 - CXX_STANDARD 11 -) - -target_link_libraries(openthread-kw41z - PRIVATE - nxp-kw41z-driver - ot-config - PUBLIC - -T${PROJECT_SOURCE_DIR}/examples/platforms/kw41z/MKW41Z512xxx4.ld - -Wl,--gc-sections -Wl,-Map=$.map -) - -target_compile_definitions(openthread-kw41z - PUBLIC - ${OT_PLATFORM_DEFINES} -) - -target_compile_options(openthread-kw41z - PRIVATE - ${OT_CFLAGS} - -Wno-unknown-pragmas - -Wno-sign-compare - -Wno-unused-function - -Wno-unused-parameter - -Wno-empty-body -) - -target_include_directories(openthread-kw41z - PRIVATE - ${OT_PUBLIC_INCLUDES} - ${PROJECT_SOURCE_DIR}/examples/platforms - ${PROJECT_SOURCE_DIR}/src/core -) diff --git a/examples/platforms/kw41z/MKW41Z512xxx4.ld b/examples/platforms/kw41z/MKW41Z512xxx4.ld deleted file mode 100644 index f93cb8087..000000000 --- a/examples/platforms/kw41z/MKW41Z512xxx4.ld +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * GCC linker script for MKW41Z512xxx4. - */ - -GROUP ( - libm.a -) - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; -M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0200 : 0x0; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 - m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0 - m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00020000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal flash */ - .interrupts : - { - __VECTOR_TABLE = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - .flash_config : - { - . = ALIGN(4); - KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ - . = ALIGN(4); - } > m_flash_config - - /* The program code and other data goes into internal flash */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - /* reserve MTB memory at the beginning of m_data */ - .mtb : /* MTB buffer address as defined by the hardware */ - { - . = ALIGN(8); - _mtb_start = .; - KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */ - . = ALIGN(8); - _mtb_end = .; - } > m_data - - .interrupts_ram : - { - . = ALIGN(4); - __VECTOR_RAM__ = .; - __interrupts_ram_start__ = .; /* Create a global symbol at data start */ - *(.m_interrupts_ram) /* This is a user defined section */ - . += M_VECTOR_RAM_SIZE; - . = ALIGN(4); - __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data - - __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); - __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} diff --git a/examples/platforms/kw41z/Makefile.am b/examples/platforms/kw41z/Makefile.am deleted file mode 100644 index 3522d2b81..000000000 --- a/examples/platforms/kw41z/Makefile.am +++ /dev/null @@ -1,110 +0,0 @@ -# -# Copyright (c) 2017, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -include $(abs_top_nlbuild_autotools_dir)/automake/pre.am - -lib_LIBRARIES = libopenthread-kw41z.a - -# Do not enable -Wundef for this platform -override CFLAGS := $(filter-out -Wundef,$(CFLAGS)) -override CXXFLAGS := $(filter-out -Wundef,$(CXXFLAGS)) - -# Do not enable -Wcast-align for this platform -override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS)) -override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS)) - -libopenthread_kw41z_a_CPPFLAGS = \ - -DCPU_MKW41Z512VHT4 \ - -I$(top_srcdir)/include \ - -I$(top_srcdir)/examples/platforms \ - -I$(top_srcdir)/src/core \ - -I$(top_srcdir)/third_party/nxp \ - -I$(top_srcdir)/third_party/nxp/CMSIS/Include \ - -I$(top_srcdir)/third_party/nxp/MKW41Z4 \ - -I$(top_srcdir)/third_party/nxp/MKW41Z4/drivers \ - -I$(top_srcdir)/third_party/nxp/MKW41Z4/XCVR \ - -I$(top_srcdir)/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x \ - -Wno-unknown-pragmas \ - -Wno-sign-compare \ - -Wno-unused-function \ - -Wno-unused-parameter \ - -Wno-empty-body \ - $(NULL) - -PLATFORM_SOURCES = \ - alarm.c \ - diag.c \ - entropy.c \ - flash.c \ - logging.c \ - misc.c \ - openthread-core-kw41z-config.h \ - openthread-core-kw41z-config-check.h \ - platform-kw41z.h \ - radio.c \ - system.c \ - uart.c \ - $(NULL) - -libopenthread_kw41z_a_SOURCES = \ - @top_builddir@/third_party/nxp/MKW41Z4/startup_MKW41Z4.S \ - @top_builddir@/third_party/nxp/MKW41Z4/clock_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/system_MKW41Z4.c \ - @top_builddir@/third_party/nxp/MKW41Z4/drivers/fsl_clock.c \ - @top_builddir@/third_party/nxp/MKW41Z4/drivers/fsl_flash.c \ - @top_builddir@/third_party/nxp/MKW41Z4/drivers/fsl_lpuart.c \ - @top_builddir@/third_party/nxp/MKW41Z4/drivers/fsl_gpio.c \ - @top_builddir@/third_party/nxp/MKW41Z4/drivers/fsl_pit.c \ - @top_builddir@/third_party/nxp/MKW41Z4/drivers/fsl_trng.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/dbg_ram_capture.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/ifr_radio.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c \ - @top_builddir@/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c \ - $(NULL) - -libopenthread_kw41z_a_SOURCES += \ - $(PLATFORM_SOURCES) \ - $(NULL) - -Dash = - -libopenthread_kw41z_a_LIBADD = \ - $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o") - -include $(abs_top_nlbuild_autotools_dir)/automake/post.am diff --git a/examples/platforms/kw41z/Makefile.platform.am b/examples/platforms/kw41z/Makefile.platform.am deleted file mode 100644 index 0f3cc9200..000000000 --- a/examples/platforms/kw41z/Makefile.platform.am +++ /dev/null @@ -1,39 +0,0 @@ -# -# Copyright (c) 2017, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -# -# kw41z platform-specific Makefile -# - -LDADD_COMMON += \ - $(top_builddir)/examples/platforms/kw41z/libopenthread-kw41z.a \ - $(NULL) - -LDFLAGS_COMMON += \ - -T $(top_srcdir)/examples/platforms/kw41z/MKW41Z512xxx4.ld \ - $(NULL) diff --git a/examples/platforms/kw41z/README.md b/examples/platforms/kw41z/README.md index 75976994f..aa5ae1f8e 100644 --- a/examples/platforms/kw41z/README.md +++ b/examples/platforms/kw41z/README.md @@ -1,128 +1 @@ -# OpenThread on NXP(Freescale) Kinetis MKW41Z512 Example - -This directory contains example platform drivers for the [NXP(Freescale) Kinetis MKW41Z512][mkw41z512] based on [FRDM-KW41Z][frdm-kw41z] hardware platform. - -[mkw41z512]: http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/kinetis-cortex-m-mcus/w-series-wireless-m0-plus-m4/kinetis-kw41z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW41Z -[frdm-kw41z]: http://www.nxp.com/products/software-and-tools/hardware-development-tools/freedom-development-boards/nxp-freedom-development-kit-for-kinetis-kw41z-31z-21z-mcus:FRDM-KW41Z - -The example platform drivers are intended to present the minimal code necessary to support OpenThread. As a result, the example platform drivers do not necessarily highlight the platform's full capabilities. - -## Toolchain - -Download and install the [GNU toolchain for ARM Cortex-M][gnu-toolchain]. - -[gnu-toolchain]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm - -In a Bash terminal, follow these instructions to install the GNU toolchain and other dependencies. - -```bash -$ cd -$ ./script/bootstrap -``` - -## Build Examples - -```bash -$ cd -$ ./bootstrap -$ make -f examples/Makefile-kw41z -``` - -After a successful build, the `elf` files are found in `/output/kw41z/bin`. You can convert them to `bin` files using `arm-none-eabi-objcopy`: - -```bash -$ arm-none-eabi-objcopy -O binary ot-cli-ftd ot-cli-ftd.bin -``` - -## Flash Binaries - -Compiled binaries may be flashed onto the MKW41Z512 using drag-and-drop into the board's MSD Bootloader or the [NXP(Freescale) Test Tool][test-tool] or [JTAG interface][jtag]. The [NXP(Freescale) Test Tool][test-tool] provides a convenient method for flashing a MKW41Z512 via the [J-Link][jlink]. - -[test-tool]: http://www.nxp.com/webapp/sps/download/license.jsp?colCode=TESTTOOL_SETUP -[jtag]: https://en.wikipedia.org/wiki/JTAG -[jlink]: https://www.segger.com/jlink-software.html - -## Running the example - -1. Prepare two boards with the flashed `CLI Example` (as shown above). -2. The CLI example uses UART connection. To view raw UART output, start a terminal emulator like PuTTY and connect to the used COM port with the following UART settings: - - - Baud rate: 115200 - - 8 data bits - - 1 stop bit - - No parity - - No flow control - -3. Open a terminal connection on the first board and start a new Thread network. - - ```bash - > dataset init new - Done - > dataset - Active Timestamp: 1 - Channel: 13 - Channel Mask: 0x07fff800 - Ext PAN ID: d63e8e3e495ebbc3 - Mesh Local Prefix: fd3d:b50b:f96d:722d::/64 - Master Key: dfd34f0f05cad978ec4e32b0413038ff - Network Name: OpenThread-8f28 - PAN ID: 0x8f28 - PSKc: c23a76e98f1a6483639b1ac1271e2e27 - Security Policy: 0, onrcb - Done - > dataset commit active - Done - > ifconfig up - Done - > thread start - Done - ``` - -4. After a couple of seconds the node will become a Leader of the network. - - ```bash - > state - leader - ``` - -5. Open a terminal connection on the second board and attach a node to the network. - - ```bash - > dataset masterkey dfd34f0f05cad978ec4e32b0413038ff - Done - > dataset commit active - Done - > ifconfig up - Done - > thread start - Done - ``` - -6. After a couple of seconds the second node will attach and become a Child. - - ```bash - > state - child - ``` - -7. List all IPv6 addresses of the first board. - - ```bash - > ipaddr - fd3d:b50b:f96d:722d:0:ff:fe00:fc00 - fd3d:b50b:f96d:722d:0:ff:fe00:c00 - fd3d:b50b:f96d:722d:7a73:bff6:9093:9117 - fe80:0:0:0:6c41:9001:f3d6:4148 - Done - ``` - -8. Choose one of them and send an ICMPv6 ping from the second board. - - ```bash - > ping fd3d:b50b:f96d:722d:7a73:bff6:9093:9117 - 16 bytes from fd3d:b50b:f96d:722d:558:f56b:d688:799: icmp_seq=1 hlim=64 time=24ms - ``` - -For a list of all available commands, visit [OpenThread CLI Reference README.md][cli]. - -[cli]: https://github.com/openthread/openthread/blob/main/src/cli/README.md +The OpenThread on KW41Z example has moved to https://github.com/openthread/ot-kw41z diff --git a/examples/platforms/kw41z/alarm.c b/examples/platforms/kw41z/alarm.c deleted file mode 100644 index 91d349ea2..000000000 --- a/examples/platforms/kw41z/alarm.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file implements the OpenThread platform abstraction for the alarm. - * - */ - -#include "fsl_clock.h" -#include "fsl_device_registers.h" -#include "fsl_pit.h" -#include - -#include -#include - -static volatile uint32_t sTime = 0; -static uint32_t sAlarmTime = 0; - -void kw41zAlarmInit(void) -{ - pit_config_t config; - uint32_t count = (CLOCK_GetBusClkFreq() / 1000) - 1; - - PIT_GetDefaultConfig(&config); - PIT_Init(PIT, &config); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, count); - PIT_StartTimer(PIT, kPIT_Chnl_0); - - PIT_EnableInterrupts(PIT, kPIT_Chnl_0, kPIT_TimerInterruptEnable); - NVIC_ClearPendingIRQ(PIT_IRQn); - NVIC_EnableIRQ(PIT_IRQn); -} - -void kw41zAlarmProcess(otInstance *aInstance) -{ - if ((sAlarmTime != 0) && (sTime >= sAlarmTime)) - { - sAlarmTime = 0; -#if OPENTHREAD_CONFIG_DIAG_ENABLE - - if (otPlatDiagModeGet()) - { - otPlatDiagAlarmFired(aInstance); - } - else -#endif - { - otPlatAlarmMilliFired(aInstance); - } - } -} - -void otPlatAlarmMilliStartAt(otInstance *aInstance, uint32_t aT0, uint32_t aDt) -{ - OT_UNUSED_VARIABLE(aInstance); - - sAlarmTime = aT0 + aDt; -} - -void otPlatAlarmMilliStop(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - sAlarmTime = 0; -} - -uint32_t otPlatAlarmMilliGetNow(void) -{ - return sTime; -} - -void PIT_IRQHandler(void) -{ - PIT_ClearStatusFlags(PIT, kPIT_Chnl_0, kPIT_TimerFlag); - sTime++; -} diff --git a/examples/platforms/kw41z/arm-none-eabi.cmake b/examples/platforms/kw41z/arm-none-eabi.cmake deleted file mode 100644 index 7484ec9df..000000000 --- a/examples/platforms/kw41z/arm-none-eabi.cmake +++ /dev/null @@ -1,42 +0,0 @@ -# -# Copyright (c) 2020, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_SYSTEM_PROCESSOR ARM) - -set(CMAKE_C_COMPILER arm-none-eabi-gcc) -set(CMAKE_CXX_COMPILER arm-none-eabi-g++) -set(CMAKE_ASM_COMPILER arm-none-eabi-as) -set(CMAKE_RANLIB arm-none-eabi-ranlib) - -set(COMMON_C_FLAGS "-mthumb -fdata-sections -ffunction-sections -mcpu=cortex-m0plus -mfloat-abi=soft") - -set(CMAKE_C_FLAGS_INIT "${COMMON_C_FLAGS} -std=gnu99") -set(CMAKE_CXX_FLAGS_INIT "${COMMON_C_FLAGS} -fno-exceptions -fno-rtti") -set(CMAKE_ASM_FLAGS_INIT "${COMMON_C_FLAGS}") -set(CMAKE_EXE_LINKER_FLAGS_INIT "${COMMON_C_FLAGS} -specs=nano.specs -specs=nosys.specs") diff --git a/examples/platforms/kw41z/diag.c b/examples/platforms/kw41z/diag.c deleted file mode 100644 index 2796f52a8..000000000 --- a/examples/platforms/kw41z/diag.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file implements the OpenThread platform abstraction for the diagnostics. - * - */ - -#include "fsl_device_registers.h" -#include -#include -#include - -#include -#include -#include - -#if OPENTHREAD_CONFIG_DIAG_ENABLE - -/** - * Diagnostics mode variables. - * - */ -static bool sDiagMode = false; - -void otPlatDiagModeSet(bool aMode) -{ - sDiagMode = aMode; -} - -bool otPlatDiagModeGet() -{ - return sDiagMode; -} - -void otPlatDiagChannelSet(uint8_t aChannel) -{ - OT_UNUSED_VARIABLE(aChannel); -} - -void otPlatDiagTxPowerSet(int8_t aTxPower) -{ - OT_UNUSED_VARIABLE(aTxPower); -} - -void otPlatDiagRadioReceived(otInstance *aInstance, otRadioFrame *aFrame, otError aError) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aFrame); - OT_UNUSED_VARIABLE(aError); -} - -void otPlatDiagAlarmCallback(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); -} - -#endif // OPENTHREAD_CONFIG_DIAG_ENABLE diff --git a/examples/platforms/kw41z/entropy.c b/examples/platforms/kw41z/entropy.c deleted file mode 100644 index 14273674b..000000000 --- a/examples/platforms/kw41z/entropy.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2019, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file implements an entropy source based on TRNG. - * - */ - -#include - -#include "fsl_device_registers.h" -#include "fsl_trng.h" -#include -#include -#include - -void kw41zRandomInit(void) -{ - trng_config_t config; - uint32_t seed; - - TRNG_GetDefaultConfig(&config); - config.frequencyCountLimit.minimum = 0x00000100; - config.frequencyCountLimit.maximum = 0x000F0000; - config.ringOscDiv = kTRNG_RingOscDiv0; - config.entropyDelay = 1200; - - otEXPECT(TRNG_Init(TRNG0, &config) == kStatus_Success); - - otEXPECT(TRNG_GetRandomData(TRNG0, &seed, sizeof(seed)) == kStatus_Success); - - srand(seed); - -exit: - return; -} - -otError otPlatEntropyGet(uint8_t *aOutput, uint16_t aOutputLength) -{ - otError status = OT_ERROR_NONE; - - otEXPECT_ACTION((aOutput != NULL), status = OT_ERROR_INVALID_ARGS); - - otEXPECT_ACTION(TRNG_GetRandomData(TRNG0, aOutput, aOutputLength) == kStatus_Success, status = OT_ERROR_FAILED); - -exit: - return status; -} diff --git a/examples/platforms/kw41z/flash.c b/examples/platforms/kw41z/flash.c deleted file mode 100644 index 5b6679921..000000000 --- a/examples/platforms/kw41z/flash.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include - -#include "fsl_device_registers.h" -#include "fsl_flash.h" - -#define FLASH_BASE_ADDRESS 0x40000 -#define FLASH_PAGE_SIZE 0x800 -#define FLASH_PAGE_NUM 2 -#define FLASH_SWAP_SIZE (FLASH_PAGE_SIZE * (FLASH_PAGE_NUM / 2)) - -static flash_config_t sFlashConfig; - -static uint32_t mapAddress(uint8_t aSwapIndex, uint32_t aOffset) -{ - uint32_t address = FLASH_BASE_ADDRESS + aOffset; - - if (aSwapIndex) - { - address += FLASH_SWAP_SIZE; - } - - return address; -} - -void otPlatFlashInit(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - FLASH_Init(&sFlashConfig); -} - -uint32_t otPlatFlashGetSwapSize(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return FLASH_SWAP_SIZE; -} - -void otPlatFlashErase(otInstance *aInstance, uint32_t aSwapIndex) -{ - OT_UNUSED_VARIABLE(aInstance); - - FLASH_Erase(&sFlashConfig, mapAddress(aSwapIndex, 0), FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE, - kFLASH_ApiEraseKey); - while ((FTFA->FSTAT & FTFA_FSTAT_CCIF_MASK) == 0) - { - } -} - -void otPlatFlashWrite(otInstance *aInstance, uint8_t aSwapIndex, uint32_t aOffset, const void *aData, uint32_t aSize) -{ - OT_UNUSED_VARIABLE(aInstance); - - FLASH_Program(&sFlashConfig, mapAddress(aSwapIndex, aOffset), (uint32_t *)aData, aSize); -} - -void otPlatFlashRead(otInstance *aInstance, uint8_t aSwapIndex, uint32_t aOffset, void *aData, uint32_t aSize) -{ - OT_UNUSED_VARIABLE(aInstance); - - memcpy(aData, (void *)mapAddress(aSwapIndex, aOffset), aSize); -} diff --git a/examples/platforms/kw41z/logging.c b/examples/platforms/kw41z/logging.c deleted file mode 100644 index 82158aeed..000000000 --- a/examples/platforms/kw41z/logging.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file logging.c - * Platform abstraction for the logging - * - */ - -#include -#include -#include -#include - -#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED) -OT_TOOL_WEAK void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, ...) -{ - OT_UNUSED_VARIABLE(aLogLevel); - OT_UNUSED_VARIABLE(aLogRegion); - OT_UNUSED_VARIABLE(aFormat); -} -#endif diff --git a/examples/platforms/kw41z/misc.c b/examples/platforms/kw41z/misc.c deleted file mode 100644 index 9eab7d265..000000000 --- a/examples/platforms/kw41z/misc.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "openthread/platform/misc.h" -#include "fsl_device_registers.h" -#include - -void otPlatReset(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - NVIC_SystemReset(); - - while (1) - { - } -} - -otPlatResetReason otPlatGetResetReason(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - otPlatResetReason reason; - - if (RCM->SRS0 & RCM_SRS0_POR_MASK) - { - reason = OT_PLAT_RESET_REASON_POWER_ON; - } - else if (RCM->SRS1 & RCM_SRS1_SW_MASK) - { - reason = OT_PLAT_RESET_REASON_SOFTWARE; - } - else if (RCM->SRS0 & RCM_SRS0_WDOG_MASK) - { - reason = OT_PLAT_RESET_REASON_WATCHDOG; - } - else if (RCM->SRS0 & RCM_SRS0_PIN_MASK) - { - reason = OT_PLAT_RESET_REASON_EXTERNAL; - } - else if ((RCM->SRS0 & RCM_SRS0_LOC_MASK) || (RCM->SRS1 & RCM_SRS1_SACKERR_MASK) || - (RCM->SRS1 & RCM_SRS1_LOCKUP_MASK)) - { - reason = OT_PLAT_RESET_REASON_FAULT; - } - else if ((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) || (RCM->SRS0 & RCM_SRS0_LVD_MASK) || - (RCM->SRS1 & RCM_SRS1_MDM_AP_MASK)) - { - reason = OT_PLAT_RESET_REASON_ASSERT; - } - else - { - reason = OT_PLAT_RESET_REASON_OTHER; - } - - return reason; -} - -void otPlatAssertFail(const char *aFilename, int aLineNumber) -{ - OT_UNUSED_VARIABLE(aFilename); - OT_UNUSED_VARIABLE(aLineNumber); -} - -void otPlatWakeHost(void) -{ - // TODO: implement an operation to wake the host from sleep state. -} diff --git a/examples/platforms/kw41z/openthread-core-kw41z-config-check.h b/examples/platforms/kw41z/openthread-core-kw41z-config-check.h deleted file mode 100644 index 1f7540c70..000000000 --- a/examples/platforms/kw41z/openthread-core-kw41z-config-check.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2019, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef OPENTHREAD_CORE_KW41Z_CONFIG_CHECK_H_ -#define OPENTHREAD_CORE_KW41Z_CONFIG_CHECK_H_ - -#if OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT -#error "Platform kw41z doesn't support configuration option: OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT" -#endif - -#endif /* OPENTHREAD_CORE_KW41Z_CONFIG_CHECK_H_ */ diff --git a/examples/platforms/kw41z/openthread-core-kw41z-config.h b/examples/platforms/kw41z/openthread-core-kw41z-config.h deleted file mode 100644 index 7e24b8a7b..000000000 --- a/examples/platforms/kw41z/openthread-core-kw41z-config.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file includes kw41z compile-time configuration constants - * for OpenThread. - */ - -#ifndef OPENTHREAD_CORE_KW41Z_CONFIG_H_ -#define OPENTHREAD_CORE_KW41Z_CONFIG_H_ - -/** - * @def OPENTHREAD_CONFIG_LOG_OUTPUT - * - * The kw41z platform provides an otPlatLog() function. - */ -#ifndef OPENTHREAD_CONFIG_LOG_OUTPUT /* allow command line override */ -#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED -#endif - -/** - * @def OPENTHREAD_CONFIG_PLATFORM_INFO - * - * The platform-specific string to insert into the OpenThread version string. - * - */ -#define OPENTHREAD_CONFIG_PLATFORM_INFO "KW41Z" - -/** - * @def OPENTHREAD_CONFIG_PLATFORM_FLASH_API_ENABLE - * - * Define to 1 to enable otPlatFlash* APIs to support non-volatile storage. - * - * When defined to 1, the platform MUST implement the otPlatFlash* APIs instead of the otPlatSettings* APIs. - * - */ -#define OPENTHREAD_CONFIG_PLATFORM_FLASH_API_ENABLE 1 - -/** - * @def RADIO_CONFIG_SRC_MATCH_ENTRY_NUM - * - * The number of source address table entries. - * - */ -#define RADIO_CONFIG_SRC_MATCH_ENTRY_NUM 128 - -/** - * @def OPENTHREAD_CONFIG_MAC_SOFTWARE_RETRANSMIT_ENABLE - * - * Define to 1 if you want to enable software retransmission logic. - * - */ -#define OPENTHREAD_CONFIG_MAC_SOFTWARE_RETRANSMIT_ENABLE 1 - -/** - * @def OPENTHREAD_CONFIG_MAC_SOFTWARE_CSMA_BACKOFF_ENABLE - * - * Define to 1 if you want to enable software CSMA-CA backoff logic. - * - */ -#define OPENTHREAD_CONFIG_MAC_SOFTWARE_CSMA_BACKOFF_ENABLE 1 - -/** - * @def OPENTHREAD_CONFIG_MAC_SOFTWARE_TX_SECURITY_ENABLE - * - * Define to 1 if you want to enable software transmission security logic. - * - */ -#define OPENTHREAD_CONFIG_MAC_SOFTWARE_TX_SECURITY_ENABLE 0 - -/** - * @def OPENTHREAD_CONFIG_NCP_HDLC_ENABLE - * - * Define to 1 to enable NCP HDLC support. - * - */ -#define OPENTHREAD_CONFIG_NCP_HDLC_ENABLE 1 - -#endif // OPENTHREAD_CORE_KW41Z_CONFIG_H_ diff --git a/examples/platforms/kw41z/platform-kw41z.h b/examples/platforms/kw41z/platform-kw41z.h deleted file mode 100644 index b089b344f..000000000 --- a/examples/platforms/kw41z/platform-kw41z.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file includes the platform-specific initializers. - * - */ - -#ifndef PLATFORM_KW41Z_H_ -#define PLATFORM_KW41Z_H_ - -#include -#include - -#include - -#include - -/** - * This function initializes the alarm service used by OpenThread. - * - */ -void kw41zAlarmInit(void); - -/** - * This function performs alarm driver processing. - * - * @param[in] aInstance The OpenThread instance structure. - * - */ -void kw41zAlarmProcess(otInstance *aInstance); - -/** - * This function initializes the radio service used by OpenThread. - * - */ -void kw41zRadioInit(void); - -/** - * This function performs radio driver processing. - * - * @param[in] aInstance The OpenThread instance structure. - * - */ -void kw41zRadioProcess(otInstance *aInstance); - -/** - * This function initializes the random number service used by OpenThread. - * - */ -void kw41zRandomInit(void); - -/** - * This function performs UART driver processing. - * - */ -void kw41zUartProcess(void); -#endif // PLATFORM_KW41Z_H_ diff --git a/examples/platforms/kw41z/radio.c b/examples/platforms/kw41z/radio.c deleted file mode 100644 index ec4b3219f..000000000 --- a/examples/platforms/kw41z/radio.c +++ /dev/null @@ -1,1033 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file implements the OpenThread platform abstraction for radio communication. - * - */ - -#include "fsl_device_registers.h" -#include "fsl_xcvr.h" -#include "openthread-core-kw41z-config.h" -#include -#include - -#include -#include -#include -#include - -// clang-format off -#define DOUBLE_BUFFERING (1) -#define DEFAULT_CHANNEL (11) -#define DEFAULT_CCA_MODE (XCVR_CCA_MODE1_c) -#define IEEE802154_ACK_REQUEST (1 << 5) -#define IEEE802154_MAX_LENGTH (127) -#define IEEE802154_MIN_LENGTH (5) -#define IEEE802154_ACK_LENGTH (IEEE802154_MIN_LENGTH) -#define IEEE802154_FRM_CTL_LO_OFFSET (0) -#define IEEE802154_DSN_OFFSET (2) -#define IEEE802154_FRM_TYPE_MASK (0x7) -#define IEEE802154_FRM_TYPE_ACK (0x2) -#define IEEE802154_TURNAROUND_LEN (12) -#define IEEE802154_CCA_LEN (8) -#define IEEE802154_PHY_SHR_LEN (10) -#define IEEE802154_ACK_WAIT (54) -#define ZLL_IRQSTS_TMR_ALL_MSK_MASK (ZLL_IRQSTS_TMR1MSK_MASK | \ - ZLL_IRQSTS_TMR2MSK_MASK | \ - ZLL_IRQSTS_TMR3MSK_MASK | \ - ZLL_IRQSTS_TMR4MSK_MASK ) -#define ZLL_DEFAULT_RX_FILTERING (ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(3) | \ - ZLL_RX_FRAME_FILTER_CMD_FT_MASK | \ - ZLL_RX_FRAME_FILTER_DATA_FT_MASK | \ - ZLL_RX_FRAME_FILTER_ACK_FT_MASK | \ - ZLL_RX_FRAME_FILTER_BEACON_FT_MASK) -// clang-format on - -typedef enum xcvr_state_tag -{ - XCVR_Idle_c, - XCVR_RX_c, - XCVR_TX_c, - XCVR_CCA_c, - XCVR_TR_c, - XCVR_CCCA_c, -} xcvr_state_t; - -typedef enum xcvr_cca_type_tag -{ - XCVR_ED_c, /* energy detect - CCA bit not active, not to be used for T and CCCA sequences */ - XCVR_CCA_MODE1_c, /* energy detect - CCA bit ACTIVE */ - SCVR_CCA_MODE2_c, /* 802.15.4 compliant signal detect - CCA bit ACTIVE */ - XCVR_CCA_MODE3_c /* 802.15.4 compliant signal detect and energy detect - CCA bit ACTIVE */ -} xcvr_cca_type_t; - -static otRadioState sState = OT_RADIO_STATE_DISABLED; -static uint16_t sPanId; -static uint8_t sExtSrcAddrBitmap[(RADIO_CONFIG_SRC_MATCH_ENTRY_NUM + 7) / 8]; -static uint8_t sChannel; -static int8_t sMaxED; -static int8_t sAutoTxPwrLevel = 0; - -/* ISR Signaling Flags */ -static bool sTxDone = false; -static bool sRxDone = false; -static bool sEdScanDone = false; -static otError sTxStatus; - -static otRadioFrame sTxFrame; -static otRadioFrame sRxFrame; -static uint8_t sTxData[OT_RADIO_FRAME_MAX_SIZE]; -#if DOUBLE_BUFFERING -static uint8_t sRxData[OT_RADIO_FRAME_MAX_SIZE]; -#endif -static otInstance *sInstance = NULL; - -/* Private functions */ -static void rf_abort(void); -static xcvr_state_t rf_get_state(void); -static void rf_set_channel(uint8_t channel); -static void rf_set_tx_power(int8_t tx_power); -static uint8_t rf_lqi_adjust(uint8_t hwLqi); -static int8_t rf_lqi_to_rssi(uint8_t lqi); -static uint32_t rf_get_timestamp(void); -static void rf_set_timeout(uint32_t abs_timeout); -static uint16_t rf_get_addr_checksum(uint8_t *pAddr, bool ExtendedAddr, uint16_t PanId); -static otError rf_add_addr_table_entry(uint16_t checksum, bool extendedAddr); -static otError rf_remove_addr_table_entry(uint16_t checksum); -static otError rf_remove_addr_table_entry_index(uint8_t index); -static bool rf_process_rx_frame(void); - -otRadioState otPlatRadioGetState(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return sState; -} - -void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint32_t addrLo; - uint32_t addrHi; - - if ((RSIM->MAC_LSB == 0xffffffff) && (RSIM->MAC_MSB == 0xff)) - { - addrLo = SIM->UIDL; - addrHi = SIM->UIDML; - } - else - { - addrLo = RSIM->MAC_LSB; - addrHi = RSIM->MAC_MSB; - } - - memcpy(aIeeeEui64, &addrLo, sizeof(addrLo)); - memcpy(aIeeeEui64 + sizeof(addrLo), &addrHi, sizeof(addrHi)); -} - -void otPlatRadioSetPanId(otInstance *aInstance, uint16_t aPanId) -{ - OT_UNUSED_VARIABLE(aInstance); - - sPanId = aPanId; - ZLL->MACSHORTADDRS0 &= ~ZLL_MACSHORTADDRS0_MACPANID0_MASK; - ZLL->MACSHORTADDRS0 |= ZLL_MACSHORTADDRS0_MACPANID0(aPanId); -} - -void otPlatRadioSetExtendedAddress(otInstance *aInstance, const otExtAddress *aExtAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint32_t addrLo; - uint32_t addrHi; - - memcpy(&addrLo, aExtAddress->m8, sizeof(addrLo)); - memcpy(&addrHi, aExtAddress->m8 + sizeof(addrLo), sizeof(addrHi)); - - ZLL->MACLONGADDRS0_LSB = addrLo; - ZLL->MACLONGADDRS0_MSB = addrHi; -} - -void otPlatRadioSetShortAddress(otInstance *aInstance, uint16_t aShortAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - ZLL->MACSHORTADDRS0 &= ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK; - ZLL->MACSHORTADDRS0 |= ZLL_MACSHORTADDRS0_MACSHORTADDRS0(aShortAddress); -} - -otError otPlatRadioEnable(otInstance *aInstance) -{ - otEXPECT(!otPlatRadioIsEnabled(aInstance)); - - sInstance = aInstance; - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TRCV_MSK_MASK; - NVIC_ClearPendingIRQ(Radio_1_IRQn); - NVIC_EnableIRQ(Radio_1_IRQn); - - sState = OT_RADIO_STATE_SLEEP; - -exit: - return OT_ERROR_NONE; -} - -otError otPlatRadioDisable(otInstance *aInstance) -{ - otEXPECT(otPlatRadioIsEnabled(aInstance)); - - NVIC_DisableIRQ(Radio_1_IRQn); - rf_abort(); - sState = OT_RADIO_STATE_DISABLED; - -exit: - return OT_ERROR_NONE; -} - -bool otPlatRadioIsEnabled(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return sState != OT_RADIO_STATE_DISABLED; -} - -otError otPlatRadioSleep(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError status = OT_ERROR_NONE; - - otEXPECT_ACTION(((sState != OT_RADIO_STATE_TRANSMIT) && (sState != OT_RADIO_STATE_DISABLED)), - status = OT_ERROR_INVALID_STATE); - - rf_abort(); - sState = OT_RADIO_STATE_SLEEP; - -exit: - return status; -} - -otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError status = OT_ERROR_NONE; - - otEXPECT_ACTION(((sState != OT_RADIO_STATE_TRANSMIT) && (sState != OT_RADIO_STATE_DISABLED)), - status = OT_ERROR_INVALID_STATE); - - sState = OT_RADIO_STATE_RECEIVE; - - /* Check if the channel needs to be changed */ - if ((sChannel != aChannel) || (rf_get_state() != XCVR_RX_c)) - { - rf_abort(); - /* Set Power level for auto TX */ - rf_set_tx_power(sAutoTxPwrLevel); - rf_set_channel(aChannel); - sRxFrame.mChannel = aChannel; - - /* Filter ACK frames during RX sequence */ - ZLL->RX_FRAME_FILTER &= ~(ZLL_RX_FRAME_FILTER_ACK_FT_MASK); - /* Clear all IRQ flags */ - ZLL->IRQSTS = ZLL->IRQSTS; - /* Start the RX sequence */ - ZLL->PHY_CTRL |= XCVR_RX_c; - - /* Unmask SEQ interrupt */ - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_SEQMSK_MASK; - } - -exit: - return status; -} - -void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable) -{ - OT_UNUSED_VARIABLE(aInstance); - - if (aEnable) - { - ZLL->SAM_CTRL |= ZLL_SAM_CTRL_SAP0_EN_MASK; - } - else - { - ZLL->SAM_CTRL &= ~ZLL_SAM_CTRL_SAP0_EN_MASK; - } -} - -otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint16_t checksum = sPanId + aShortAddress; - - return rf_add_addr_table_entry(checksum, false); -} - -otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint16_t checksum = rf_get_addr_checksum((uint8_t *)aExtAddress->m8, true, sPanId); - - return rf_add_addr_table_entry(checksum, true); -} - -otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint16_t checksum = sPanId + aShortAddress; - - return rf_remove_addr_table_entry(checksum); -} - -otError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint16_t checksum = rf_get_addr_checksum((uint8_t *)aExtAddress->m8, true, sPanId); - - return rf_remove_addr_table_entry(checksum); -} - -void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint32_t i; - - for (i = 0; i < RADIO_CONFIG_SRC_MATCH_ENTRY_NUM; i++) - { - /* Optimization: sExtSrcAddrBitmap[i / 8] & (1 << (i % 8)) */ - if (!(sExtSrcAddrBitmap[i >> 3] & (1 << (i & 7)))) - { - rf_remove_addr_table_entry_index(i); - } - } -} - -void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - uint32_t i; - - for (i = 0; i < RADIO_CONFIG_SRC_MATCH_ENTRY_NUM; i++) - { - /* Optimization: sExtSrcAddrBitmap[i / 8] & (1 << (i % 8))*/ - if (sExtSrcAddrBitmap[i >> 3] & (1 << (i & 7))) - { - rf_remove_addr_table_entry_index(i); - } - } -} - -otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return &sTxFrame; -} - -otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) -{ - otError status = OT_ERROR_NONE; - uint32_t timeout; - - otEXPECT_ACTION(((sState != OT_RADIO_STATE_TRANSMIT) && (sState != OT_RADIO_STATE_DISABLED)), - status = OT_ERROR_INVALID_STATE); - - if (rf_get_state() != XCVR_Idle_c) - { - rf_abort(); - } - - rf_set_channel(aFrame->mChannel); - - *(uint8_t *)ZLL->PKT_BUFFER_TX = aFrame->mLength; - - /* MKW41Z Reference Manual Section 44.6.2.7 states: "The 802.15.4 - * Link Layer software prepares data to be transmitted, by loading - * the octets, in order, into the Packet Buffer." */ - for (int i = 0; i < aFrame->mLength - sizeof(uint16_t); i++) - { - ((uint8_t *)ZLL->PKT_BUFFER_TX)[1 + i] = sTxFrame.mPsdu[i]; - } - - /* Set CCA mode */ - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_CCATYPE_MASK; - ZLL->PHY_CTRL |= ZLL_PHY_CTRL_CCATYPE(DEFAULT_CCA_MODE); - - /* Clear all IRQ flags */ - ZLL->IRQSTS = ZLL->IRQSTS; - - /* Perform automatic reception of ACK frame, if required */ - if (aFrame->mPsdu[IEEE802154_FRM_CTL_LO_OFFSET] & IEEE802154_ACK_REQUEST) - { - /* Permit the reception of ACK frames during TR sequence */ - ZLL->RX_FRAME_FILTER |= (ZLL_RX_FRAME_FILTER_ACK_FT_MASK); - ZLL->PHY_CTRL |= XCVR_TR_c; - /* Set ACK wait time-out */ - timeout = rf_get_timestamp(); - timeout += (((XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT) >> - 4); - timeout += IEEE802154_CCA_LEN + IEEE802154_TURNAROUND_LEN + IEEE802154_PHY_SHR_LEN + - (1 + aFrame->mLength) * OT_RADIO_SYMBOLS_PER_OCTET + IEEE802154_ACK_WAIT; - rf_set_timeout(timeout); - } - else - { - ZLL->PHY_CTRL |= XCVR_TX_c; - } - - sTxStatus = OT_ERROR_NONE; - sState = OT_RADIO_STATE_TRANSMIT; - /* Unmask SEQ interrupt */ - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_SEQMSK_MASK; - - otPlatRadioTxStarted(aInstance, aFrame); - -exit: - return status; -} - -int8_t otPlatRadioGetRssi(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_RSSI_MASK) >> ZLL_LQI_AND_RSSI_RSSI_SHIFT; -} - -otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_ENERGY_SCAN; -} - -bool otPlatRadioGetPromiscuous(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return (ZLL->PHY_CTRL & ZLL_PHY_CTRL_PROMISCUOUS_MASK) == ZLL_PHY_CTRL_PROMISCUOUS_MASK; -} - -void otPlatRadioSetPromiscuous(otInstance *aInstance, bool aEnable) -{ - OT_UNUSED_VARIABLE(aInstance); - - if (aEnable) - { - ZLL->PHY_CTRL |= ZLL_PHY_CTRL_PROMISCUOUS_MASK; - /* FRM_VER[11:8] = b1111. Any FrameVersion accepted */ - ZLL->RX_FRAME_FILTER |= (ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK | ZLL_RX_FRAME_FILTER_NS_FT_MASK); - } - else - { - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_PROMISCUOUS_MASK; - /* FRM_VER[11:8] = b0011. Accept FrameVersion 0 and 1 packets, reject all others */ - ZLL->RX_FRAME_FILTER = ZLL_DEFAULT_RX_FILTERING; - } -} - -otError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint16_t aScanDuration) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError status = OT_ERROR_NONE; - uint32_t timeout; - - otEXPECT_ACTION(((sState != OT_RADIO_STATE_TRANSMIT) && (sState != OT_RADIO_STATE_DISABLED)), - status = OT_ERROR_INVALID_STATE); - - if (rf_get_state() != XCVR_Idle_c) - { - rf_abort(); - } - - sMaxED = -128; - rf_set_channel(aScanChannel); - /* Set CCA type to ED - Energy Detect */ - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_CCATYPE_MASK; - ZLL->PHY_CTRL |= ZLL_PHY_CTRL_CCATYPE(XCVR_ED_c); - /* Clear all IRQ flags */ - ZLL->IRQSTS = ZLL->IRQSTS; - /* Start ED sequence */ - ZLL->PHY_CTRL |= XCVR_CCA_c; - /* Unmask SEQ interrupt */ - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_SEQMSK_MASK; - /* Set Scan time-out */ - timeout = rf_get_timestamp(); - timeout += (aScanDuration * 1000) / OT_RADIO_SYMBOL_TIME; - rf_set_timeout(timeout); - -exit: - return status; -} - -otError otPlatRadioGetTransmitPower(otInstance *aInstance, int8_t *aPower) -{ - otError error = OT_ERROR_NONE; - - otEXPECT_ACTION(aPower != NULL, error = OT_ERROR_INVALID_ARGS); - *aPower = sAutoTxPwrLevel; - -exit: - return error; -} - -otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower) -{ - OT_UNUSED_VARIABLE(aInstance); - - sAutoTxPwrLevel = aPower; - - return OT_ERROR_NONE; -} - -otError otPlatRadioGetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t *aThreshold) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aThreshold); - - return OT_ERROR_NOT_IMPLEMENTED; -} - -otError otPlatRadioSetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t aThreshold) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aThreshold); - - return OT_ERROR_NOT_IMPLEMENTED; -} - -int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return -100; -} - -/*************************************************************************************************/ - -static void rf_abort(void) -{ - /* Mask SEQ interrupt */ - ZLL->PHY_CTRL |= ZLL_PHY_CTRL_SEQMSK_MASK; - - /* Disable timer trigger (for scheduled XCVSEQ) */ - if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_TMRTRIGEN_MASK) - { - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMRTRIGEN_MASK; - - /* give the FSM enough time to start if it was triggered */ - while ((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) == 0) - { - } - } - - /* If XCVR is not idle, abort current SEQ */ - if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) - { - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_XCVSEQ_MASK; - - /* wait for Sequence Idle (if not already) */ - while (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) - { - } - } - - /* Stop timers */ - ZLL->PHY_CTRL &= ~(ZLL_PHY_CTRL_TMR2CMP_EN_MASK | ZLL_PHY_CTRL_TMR3CMP_EN_MASK); - /* Clear all PP IRQ bits to avoid unexpected interrupts( do not change TMR1 and TMR4 IRQ status ) */ - ZLL->IRQSTS &= ~(ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK); -} - -static xcvr_state_t rf_get_state(void) -{ - return (xcvr_state_t)((ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT); -} - -static void rf_set_channel(uint8_t channel) -{ - if (sChannel != channel) - { - ZLL->CHANNEL_NUM0 = channel; - sChannel = channel; - } -} - -static void rf_set_tx_power(int8_t tx_power) -{ - if (tx_power > 2) - { - ZLL->PA_PWR = 30; - } - else if (tx_power > 1) - { - ZLL->PA_PWR = 24; - } - else if (tx_power > -1) - { - ZLL->PA_PWR = 18; - } - else if (tx_power > -3) - { - ZLL->PA_PWR = 14; - } - else if (tx_power > -4) - { - ZLL->PA_PWR = 12; - } - else if (tx_power > -6) - { - ZLL->PA_PWR = 10; - } - else if (tx_power > -8) - { - ZLL->PA_PWR = 8; - } - else if (tx_power > -11) - { - ZLL->PA_PWR = 6; - } - else if (tx_power > -14) - { - ZLL->PA_PWR = 4; - } - else if (tx_power > -20) - { - ZLL->PA_PWR = 2; - } - else - { - ZLL->PA_PWR = 0; - } -} - -static uint16_t rf_get_addr_checksum(uint8_t *pAddr, bool ExtendedAddr, uint16_t PanId) -{ - uint16_t checksum; - - /* Short address */ - checksum = PanId; - checksum += *pAddr++; - checksum += (uint16_t)(*pAddr++) << 8; - - if (ExtendedAddr) - { - /* Extended address */ - checksum += *pAddr++; - checksum += ((uint16_t)(*pAddr++)) << 8; - checksum += *pAddr++; - checksum += ((uint16_t)(*pAddr++)) << 8; - checksum += *pAddr++; - checksum += ((uint16_t)(*pAddr++)) << 8; - } - - return checksum; -} - -static otError rf_add_addr_table_entry(uint16_t checksum, bool extendedAddr) -{ - uint8_t index; - otError status; - - /* Find first free index */ - ZLL->SAM_TABLE = ZLL_SAM_TABLE_FIND_FREE_IDX_MASK; - - while (ZLL->SAM_TABLE & ZLL_SAM_TABLE_SAM_BUSY_MASK) - { - } - - index = (ZLL->SAM_FREE_IDX & ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK) >> ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT; - - otEXPECT_ACTION((index < RADIO_CONFIG_SRC_MATCH_ENTRY_NUM), status = OT_ERROR_NO_BUFS); - - /* Insert the checksum at the index found */ - ZLL->SAM_TABLE = ((uint32_t)index << ZLL_SAM_TABLE_SAM_INDEX_SHIFT) | - ((uint32_t)checksum << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT) | ZLL_SAM_TABLE_SAM_INDEX_WR_MASK | - ZLL_SAM_TABLE_SAM_INDEX_EN_MASK; - - if (extendedAddr) - { - /* Optimization: sExtSrcAddrBitmap[index / 8] |= 1 << (index % 8); */ - sExtSrcAddrBitmap[index >> 3] |= 1 << (index & 7); - } - - status = OT_ERROR_NONE; - -exit: - return status; -} - -static otError rf_remove_addr_table_entry(uint16_t checksum) -{ - otError status = OT_ERROR_NO_ADDRESS; - uint32_t i, temp; - - /* Search for an entry to match the provided checksum */ - for (i = 0; i < RADIO_CONFIG_SRC_MATCH_ENTRY_NUM; i++) - { - ZLL->SAM_TABLE = i << ZLL_SAM_TABLE_SAM_INDEX_SHIFT; - /* Read checksum located at the specified index */ - temp = (ZLL->SAM_TABLE & ZLL_SAM_TABLE_SAM_CHECKSUM_MASK) >> ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT; - - if (temp == checksum) - { - /* Remove the entry from the table */ - status = rf_remove_addr_table_entry_index(i); - break; - } - } - - return status; -} - -static otError rf_remove_addr_table_entry_index(uint8_t index) -{ - otError status = OT_ERROR_NONE; - - otEXPECT_ACTION(index < RADIO_CONFIG_SRC_MATCH_ENTRY_NUM, status = OT_ERROR_NO_ADDRESS); - - ZLL->SAM_TABLE = ((uint32_t)0xFFFF << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT) | - ((uint32_t)index << ZLL_SAM_TABLE_SAM_INDEX_SHIFT) | ZLL_SAM_TABLE_SAM_INDEX_INV_MASK | - ZLL_SAM_TABLE_SAM_INDEX_WR_MASK; - - /* Clear bitmap */ - /* Optimization: sExtSrcAddrBitmap[index / 8] &= ~(1 << (index % 8)); */ - sExtSrcAddrBitmap[index >> 3] &= ~(1 << (index & 7)); - -exit: - return status; -} - -static uint8_t rf_lqi_adjust(uint8_t hwLqi) -{ - if (hwLqi >= 220) - { - hwLqi = 255; - } - else - { - hwLqi = (51 * hwLqi) / 44; - } - - return hwLqi; -} - -static int8_t rf_lqi_to_rssi(uint8_t lqi) -{ - int32_t rssi = (36 * lqi - 9836) / 109; - - return (int8_t)rssi; -} - -static uint32_t rf_get_timestamp(void) -{ - return ZLL->EVENT_TMR >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT; -} - -static void rf_set_timeout(uint32_t abs_timeout) -{ - uint32_t irqSts; - - /* Disable TMR3 compare */ - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMR3CMP_EN_MASK; - /* Set time-out value */ - ZLL->T3CMP = abs_timeout; - /* Aknowledge and unmask TMR3 IRQ */ - irqSts = ZLL->IRQSTS & ZLL_IRQSTS_TMR_ALL_MSK_MASK; - irqSts &= ~ZLL_IRQSTS_TMR3MSK_MASK; - irqSts |= ZLL_IRQSTS_TMR3IRQ_MASK; - ZLL->IRQSTS = irqSts; - /* Enable TMR3 compare */ - ZLL->PHY_CTRL |= ZLL_PHY_CTRL_TMR3CMP_EN_MASK; -} - -static bool rf_process_rx_frame(void) -{ - uint8_t temp; - bool status = true; - - /* Get Rx length */ - temp = (ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT; - - /* Check if frame is valid */ - otEXPECT_ACTION((IEEE802154_MIN_LENGTH <= temp) && (temp <= IEEE802154_MAX_LENGTH), status = false); - -#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE -#error Time sync requires the timestamp of SFD rather than that of rx done! -#else - if (otPlatRadioGetPromiscuous(sInstance)) -#endif - { - // The current driver only supports milliseconds resolution. - sRxFrame.mInfo.mRxInfo.mTimestamp = otPlatAlarmMilliGetNow() * 1000; - } - - sRxFrame.mLength = temp; - temp = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >> ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT; - sRxFrame.mInfo.mRxInfo.mLqi = rf_lqi_adjust(temp); - sRxFrame.mInfo.mRxInfo.mRssi = rf_lqi_to_rssi(sRxFrame.mInfo.mRxInfo.mLqi); -#if DOUBLE_BUFFERING - - for (temp = 0; temp < sRxFrame.mLength - 2; temp++) - { - sRxData[temp] = ((uint8_t *)ZLL->PKT_BUFFER_RX)[temp]; - } - -#endif - -exit: - return status; -} - -void Radio_1_IRQHandler(void) -{ - xcvr_state_t state = rf_get_state(); - uint32_t irqStatus = ZLL->IRQSTS; - int8_t temp; - - ZLL->IRQSTS = irqStatus; - - /* TMR3 IRQ - time-out */ - if ((irqStatus & ZLL_IRQSTS_TMR3IRQ_MASK) && (!(irqStatus & ZLL_IRQSTS_TMR3MSK_MASK))) - { - /* Stop TMR3 */ - ZLL->IRQSTS = irqStatus | ZLL_IRQSTS_TMR3MSK_MASK; - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMR3CMP_EN_MASK; - - if (state == XCVR_CCA_c) - { - rf_abort(); - sEdScanDone = true; - } - else if ((state == XCVR_TR_c) && !(irqStatus & ZLL_IRQSTS_RXIRQ_MASK)) - { - rf_abort(); - sState = OT_RADIO_STATE_RECEIVE; - sTxStatus = OT_ERROR_NO_ACK; - sTxDone = true; - } - } - - /* Sequence done IRQ */ - if ((!(ZLL->PHY_CTRL & ZLL_PHY_CTRL_SEQMSK_MASK)) && (irqStatus & ZLL_IRQSTS_SEQIRQ_MASK)) - { - /* Cleanup */ - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_XCVSEQ_MASK; - ZLL->PHY_CTRL |= ZLL_PHY_CTRL_SEQMSK_MASK; - - switch (state) - { - case XCVR_RX_c: - sRxDone = rf_process_rx_frame(); - break; - - case XCVR_TR_c: - /* Stop TMR3 */ - ZLL->IRQSTS = irqStatus | ZLL_IRQSTS_TMR3MSK_MASK; - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMR3CMP_EN_MASK; - - if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) && (irqStatus & ZLL_IRQSTS_CCA_MASK)) - { - sTxStatus = OT_ERROR_CHANNEL_ACCESS_FAILURE; - } - else if (!(irqStatus & ZLL_IRQSTS_RXIRQ_MASK) || (rf_process_rx_frame() == false) || - (sRxFrame.mLength != IEEE802154_ACK_LENGTH) || - ((sRxFrame.mPsdu[IEEE802154_FRM_CTL_LO_OFFSET] & IEEE802154_FRM_TYPE_MASK) != - IEEE802154_FRM_TYPE_ACK) || - (sRxFrame.mPsdu[IEEE802154_DSN_OFFSET] != sTxFrame.mPsdu[IEEE802154_DSN_OFFSET])) - { - sTxStatus = OT_ERROR_NO_ACK; - } - - sState = OT_RADIO_STATE_RECEIVE; - sTxDone = true; - break; - - case XCVR_TX_c: - if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) && (irqStatus & ZLL_IRQSTS_CCA_MASK)) - { - sTxStatus = OT_ERROR_CHANNEL_ACCESS_FAILURE; - } - - sState = OT_RADIO_STATE_RECEIVE; - sTxDone = true; - break; - - case XCVR_CCA_c: - temp = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT; - - if (temp > sMaxED) - { - sMaxED = temp; - } - - if (!sEdScanDone) - { - /* Restart ED */ - while (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) - { - } - - ZLL->IRQSTS = (ZLL->IRQSTS & ZLL_IRQSTS_TMR_ALL_MSK_MASK) | ZLL_IRQSTS_SEQIRQ_MASK; - ZLL->PHY_CTRL |= XCVR_CCA_c; - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_SEQMSK_MASK; - } - - break; - - default: - rf_abort(); - break; - } - } - - if ((sState == OT_RADIO_STATE_RECEIVE) && (rf_get_state() == XCVR_Idle_c)) - { - /* Restart RX */ - while (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) - { - } - - /* Filter ACK frames during RX sequence*/ - ZLL->RX_FRAME_FILTER &= ~(ZLL_RX_FRAME_FILTER_ACK_FT_MASK); - ZLL->IRQSTS = ZLL->IRQSTS; - ZLL->PHY_CTRL |= XCVR_RX_c; - ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_SEQMSK_MASK; - } -} - -void kw41zRadioInit(void) -{ - XCVR_Init(ZIGBEE_MODE, DR_500KBPS); - - /* Disable all timers, enable AUTOACK and CCA before TX, mask all interrupts */ - ZLL->PHY_CTRL = ZLL_PHY_CTRL_CCATYPE(DEFAULT_CCA_MODE) | // - ZLL_PHY_CTRL_CCABFRTX_MASK | // - ZLL_PHY_CTRL_TSM_MSK_MASK | // - ZLL_PHY_CTRL_WAKE_MSK_MASK | // - ZLL_PHY_CTRL_CRC_MSK_MASK | // - ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK | // - ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK | // - ZLL_PHY_CTRL_RX_WMRK_MSK_MASK | // - ZLL_PHY_CTRL_CCAMSK_MASK | // - ZLL_PHY_CTRL_RXMSK_MASK | // - ZLL_PHY_CTRL_TXMSK_MASK | // - ZLL_PHY_CTRL_SEQMSK_MASK | // - ZLL_PHY_CTRL_AUTOACK_MASK | // - ZLL_PHY_CTRL_TRCV_MSK_MASK; - - /* Clear all IRQ flags and disable all timer interrupts */ - ZLL->IRQSTS = ZLL->IRQSTS; - - /* Frame Filtering - FRM_VER[7:6] = b11. Accept FrameVersion 0 and 1 packets, reject all others */ - ZLL->RX_FRAME_FILTER = ZLL_DEFAULT_RX_FILTERING; - - /* Set prescaller to obtain 1 symbol (16us) timebase */ - ZLL->TMR_PRESCALE = 0x05; - - /* Set CCA threshold to -75 dBm */ - ZLL->CCA_LQI_CTRL &= ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK; - ZLL->CCA_LQI_CTRL |= ZLL_CCA_LQI_CTRL_CCA1_THRESH(-75); - - /* Adjust LQI compensation */ - ZLL->CCA_LQI_CTRL &= ~ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK; - ZLL->CCA_LQI_CTRL |= ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(96); - - /* Adjust ACK delay to fulfill the 802.15.4 turnaround requirements */ - ZLL->ACKDELAY &= ~ZLL_ACKDELAY_ACKDELAY_MASK; - ZLL->ACKDELAY |= ZLL_ACKDELAY_ACKDELAY(-8); - - /* Clear HW indirect queue */ - ZLL->SAM_TABLE |= ZLL_SAM_TABLE_INVALIDATE_ALL_MASK; - - rf_set_channel(DEFAULT_CHANNEL); - rf_set_tx_power(0); - - sTxFrame.mLength = 0; - sTxFrame.mPsdu = sTxData; - sRxFrame.mLength = 0; -#if DOUBLE_BUFFERING - sRxFrame.mPsdu = sRxData; -#else - sRxFrame.mPsdu = (uint8_t *)ZLL->PKT_BUFFER_RX; -#endif -} - -void kw41zRadioProcess(otInstance *aInstance) -{ - if (sTxDone) - { - if (sTxFrame.mPsdu[IEEE802154_FRM_CTL_LO_OFFSET] & IEEE802154_ACK_REQUEST) - { - otPlatRadioTxDone(aInstance, &sTxFrame, &sRxFrame, sTxStatus); - } - else - { - otPlatRadioTxDone(aInstance, &sTxFrame, NULL, sTxStatus); - } - - sTxDone = false; - } - - if (sRxDone) - { - // TODO Set this flag only when the packet is really acknowledged with frame pending set. - // See https://github.com/openthread/openthread/pull/3785 - sRxFrame.mInfo.mRxInfo.mAckedWithFramePending = true; - -#if OPENTHREAD_CONFIG_DIAG_ENABLE - - if (otPlatDiagModeGet()) - { - otPlatDiagRadioReceiveDone(aInstance, &sRxFrame, OT_ERROR_NONE); - } - else -#endif - { - otPlatRadioReceiveDone(aInstance, &sRxFrame, OT_ERROR_NONE); - } - - sRxDone = false; - } - - if (sEdScanDone) - { - otPlatRadioEnergyScanDone(aInstance, sMaxED); - sEdScanDone = false; - } -} diff --git a/examples/platforms/kw41z/system.c b/examples/platforms/kw41z/system.c deleted file mode 100644 index 777bb38b7..000000000 --- a/examples/platforms/kw41z/system.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file includes the platform-specific initializers. - * - */ - -#include "clock_config.h" -#include "fsl_clock.h" -#include "fsl_device_registers.h" -#include "fsl_port.h" -#include "platform-kw41z.h" -#include - -#include "utils/uart.h" - -otInstance *sInstance; - -void otSysInit(int argc, char *argv[]) -{ - OT_UNUSED_VARIABLE(argc); - OT_UNUSED_VARIABLE(argv); - - uint32_t temp, tempTrim; - uint8_t revId; - - /* enable clock for PORTs */ - CLOCK_EnableClock(kCLOCK_PortA); - CLOCK_EnableClock(kCLOCK_PortB); - CLOCK_EnableClock(kCLOCK_PortC); - - SIM->SCGC6 |= (SIM_SCGC6_DMAMUX_MASK); /* Enable clock to DMA_MUX (SIM module) */ - SIM->SCGC7 |= (SIM_SCGC7_DMA_MASK); - - /* Obtain REV ID from SIM */ - revId = (uint8_t)((SIM->SDID & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT); - - if (revId == 0) - { - tempTrim = RSIM->ANA_TRIM; - RSIM->ANA_TRIM |= RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK; /* max trim for BB LDO for XO */ - } - - /* Turn on clocks for the XCVR */ - /* Enable RF OSC in RSIM and wait for ready */ - temp = RSIM->CONTROL; - temp &= ~RSIM_CONTROL_RF_OSC_EN_MASK; - RSIM->CONTROL = temp | RSIM_CONTROL_RF_OSC_EN(1); - /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */ - RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; - - /* wait for RF_OSC_READY */ - while ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) - { - } - - if (revId == 0) - { - SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; - XCVR_TSM->OVRD0 |= XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK | - XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK; /* Force ADC DAC LDO on to prevent BGAP failure */ - /* Reset LDO trim settings */ - RSIM->ANA_TRIM = tempTrim; - } /* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */ - - /* Init board clock */ - BOARD_BootClockRUN(); - - kw41zAlarmInit(); - kw41zRandomInit(); - kw41zRadioInit(); - - otPlatUartEnable(); -} - -bool otSysPseudoResetWasRequested(void) -{ - return false; -} - -void otSysDeinit(void) -{ -} - -void otSysProcessDrivers(otInstance *aInstance) -{ - sInstance = aInstance; - kw41zUartProcess(); - kw41zRadioProcess(aInstance); - kw41zAlarmProcess(aInstance); -} - -void NMI_Handler(void) -{ - /* Change NMI Pin MUX */ - CLOCK_EnableClock(kCLOCK_PortB); - PORT_SetPinMux(PORTB, 18, kPORT_MuxAlt2); -} diff --git a/examples/platforms/kw41z/uart.c b/examples/platforms/kw41z/uart.c deleted file mode 100644 index 9b59057a8..000000000 --- a/examples/platforms/kw41z/uart.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file implements the OpenThread platform abstraction for UART communication. - * - */ - -#include "fsl_device_registers.h" -#include -#include - -#include -#include - -#include "fsl_clock.h" -#include "fsl_lpuart.h" -#include "fsl_port.h" - -enum -{ - kPlatformClock = 32000000, - kBaudRate = 115200, - kReceiveBufferSize = 256, -}; - -static void processReceive(); -static void processTransmit(); - -static const uint8_t *sTransmitBuffer = NULL; -static uint16_t sTransmitLength = 0; -static bool sTransmitDone = false; - -typedef struct RecvBuffer -{ - // The data buffer - uint8_t mBuffer[kReceiveBufferSize]; - // The offset of the first item written to the list. - uint16_t mHead; - // The offset of the next item to be written to the list. - uint16_t mTail; -} RecvBuffer; - -static RecvBuffer sReceive; - -otError otPlatUartEnable(void) -{ - lpuart_config_t config; - - sReceive.mHead = 0; - sReceive.mTail = 0; - - /* Pin MUX */ - CLOCK_EnableClock(kCLOCK_PortC); - PORT_SetPinMux(PORTC, 6, kPORT_MuxAlt4); - PORT_SetPinMux(PORTC, 7, kPORT_MuxAlt4); - - /* Set OSCERCLK as LPUART Rx/Tx clock */ - CLOCK_SetLpuartClock(2); - - LPUART_GetDefaultConfig(&config); - config.enableRx = 1; - config.enableTx = 1; - config.baudRate_Bps = kBaudRate; - LPUART_Init(LPUART0, &config, kPlatformClock); - LPUART_EnableInterrupts(LPUART0, kLPUART_RxDataRegFullInterruptEnable); - - NVIC_ClearPendingIRQ(LPUART0_IRQn); - NVIC_EnableIRQ(LPUART0_IRQn); - - return OT_ERROR_NONE; -} - -otError otPlatUartDisable(void) -{ - NVIC_DisableIRQ(LPUART0_IRQn); - return OT_ERROR_NONE; -} - -otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength) -{ - otError error = OT_ERROR_NONE; - - otEXPECT_ACTION(sTransmitBuffer == NULL, error = OT_ERROR_BUSY); - - sTransmitBuffer = aBuf + 1; - sTransmitLength = aBufLength - 1; - sTransmitDone = false; - LPUART_WriteByte(LPUART0, *aBuf); - LPUART_ClearStatusFlags(LPUART0, kLPUART_TxDataRegEmptyFlag); - LPUART_EnableInterrupts(LPUART0, kLPUART_TxDataRegEmptyInterruptEnable); - -exit: - return error; -} - -otError otPlatUartFlush(void) -{ - return OT_ERROR_NOT_IMPLEMENTED; -} - -static void processTransmit(void) -{ - if (sTransmitBuffer && sTransmitDone) - { - sTransmitDone = false; - sTransmitBuffer = NULL; - otPlatUartSendDone(); - } - - return; -} - -void kw41zUartProcess(void) -{ - processReceive(); - processTransmit(); -} - -static void processReceive(void) -{ - // Copy tail to prevent multiple reads - uint16_t tail = sReceive.mTail; - - if (sReceive.mHead > tail) - { - otPlatUartReceived(sReceive.mBuffer + sReceive.mHead, kReceiveBufferSize - sReceive.mHead); - - // Reset the buffer mHead back to zero - sReceive.mHead = 0; - } - - if (sReceive.mHead != tail) - { - otPlatUartReceived(sReceive.mBuffer + sReceive.mHead, tail - sReceive.mHead); - - // Set mHead to the local tail we have cached - sReceive.mHead = tail; - } -} - -void LPUART0_IRQHandler(void) -{ - uint32_t interrupts = LPUART_GetEnabledInterrupts(LPUART0); - uint8_t rx_data; - - /* Check if data was received */ - while (LPUART_GetStatusFlags(LPUART0) & (kLPUART_RxDataRegFullFlag)) - { - rx_data = LPUART_ReadByte(LPUART0); - LPUART_ClearStatusFlags(LPUART0, kLPUART_RxDataRegFullFlag); - - if (sReceive.mHead != (sReceive.mTail + 1) % kReceiveBufferSize) - { - sReceive.mBuffer[sReceive.mTail] = rx_data; - sReceive.mTail = (sReceive.mTail + 1) % kReceiveBufferSize; - } - } - - /* Check if data Tx has end */ - if ((LPUART_GetStatusFlags(LPUART0) & kLPUART_TxDataRegEmptyFlag) && - (interrupts & kLPUART_TxDataRegEmptyInterruptEnable)) - { - if (sTransmitLength) - { - sTransmitLength--; - LPUART_WriteByte(LPUART0, *sTransmitBuffer++); - } - else if (!sTransmitDone) - { - sTransmitDone = true; - LPUART_DisableInterrupts(LPUART0, kLPUART_TxDataRegEmptyInterruptEnable); - } - } - - if (LPUART_GetStatusFlags(LPUART0) & kLPUART_RxOverrunFlag) - { - LPUART_ClearStatusFlags(LPUART0, kLPUART_RxOverrunFlag); - } -} diff --git a/script/check-arm-build-autotools b/script/check-arm-build-autotools index f69e37fce..9a47152b2 100755 --- a/script/check-arm-build-autotools +++ b/script/check-arm-build-autotools @@ -117,21 +117,6 @@ build_k32w061() make -f examples/Makefile-k32w061 "${options[@]}" } -build_kw41z() -{ - local options=( - "COMMISSIONER=1" - "DHCP6_CLIENT=1" - "DHCP6_SERVER=1" - "DNS_CLIENT=1" - "JOINER=1" - "SLAAC=1" - ) - - reset_source - make -f examples/Makefile-kw41z "${options[@]}" -} - build_nrf52811() { local options=( @@ -263,7 +248,6 @@ main() build_cc2652 build_jn5189 build_k32w061 - build_kw41z build_nrf52811 build_nrf52833 build_nrf52840 diff --git a/script/check-arm-build-cmake b/script/check-arm-build-cmake index 7531b32e7..6513d6d6f 100755 --- a/script/check-arm-build-cmake +++ b/script/check-arm-build-cmake @@ -77,12 +77,6 @@ build_cc2652() "$(dirname "$0")"/cmake-build cc2652 "${OT_COMMON_OPTIONS[@]}" "${OT_BASIC_CHECK_OPTIONS[@]}" } -build_kw41z() -{ - reset_source - "$(dirname "$0")"/cmake-build kw41z "${OT_COMMON_OPTIONS[@]}" "${OT_BASIC_CHECK_OPTIONS[@]}" -} - build_nrf52811() { reset_source @@ -110,7 +104,6 @@ main() build_cc2538 build_cc2650 build_cc2652 - build_kw41z # UART transport build_nrf52840 UART_trans # USB transport with bootloader e.g. to support PCA10059 dongle diff --git a/script/cmake-build b/script/cmake-build index b387d822c..20b69419e 100755 --- a/script/cmake-build +++ b/script/cmake-build @@ -79,7 +79,7 @@ set -euxo pipefail OT_CMAKE_NINJA_TARGET=${OT_CMAKE_NINJA_TARGET:-} readonly OT_SRCDIR="$(pwd)" -readonly OT_PLATFORMS=(cc1352 cc2538 cc2650 cc2652 efr32mg1 efr32mg12 efr32mg13 efr32mg21 kw41z nrf52811 nrf52833 nrf52840 simulation posix) +readonly OT_PLATFORMS=(cc1352 cc2538 cc2650 cc2652 efr32mg1 efr32mg12 efr32mg13 efr32mg21 nrf52811 nrf52833 nrf52840 simulation posix) readonly OT_NRF528XX_BUILD_TYPES=(UART_trans USB_trans_bl SPI_trans_NCP soft_crypto soft_crypto_threading) readonly OT_POSIX_SIM_COMMON_OPTIONS=( "-DOT_BORDER_AGENT=ON" @@ -232,7 +232,7 @@ main() OT_CMAKE_NINJA_TARGET=("ot-cli-mtd" "ot-ncp-mtd") options+=("-DCMAKE_TOOLCHAIN_FILE=examples/platforms/${platform}/arm-none-eabi.cmake" "-DCMAKE_BUILD_TYPE=MinSizeRel") ;; - cc1352 | cc2538 | cc2652 | kw41z) + cc1352 | cc2538 | cc2652) options+=("-DCMAKE_TOOLCHAIN_FILE=examples/platforms/${platform}/arm-none-eabi.cmake" "-DCMAKE_BUILD_TYPE=MinSizeRel") ;; efr32*) diff --git a/third_party/CMakeLists.txt b/third_party/CMakeLists.txt index 40fee388a..1a0a71a60 100644 --- a/third_party/CMakeLists.txt +++ b/third_party/CMakeLists.txt @@ -30,9 +30,7 @@ if(NOT OT_EXTERNAL_MBEDTLS) add_subdirectory(mbedtls) endif() -if(OT_PLATFORM STREQUAL "kw41z") - add_subdirectory(nxp) -elseif(OT_PLATFORM MATCHES "cc*") +if(OT_PLATFORM MATCHES "cc*") add_subdirectory(ti) elseif(OT_PLATFORM MATCHES "^nrf*") add_subdirectory(jlink) diff --git a/third_party/nxp/CMSIS/Include/arm_common_tables.h b/third_party/nxp/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 8742a5699..000000000 --- a/third_party/nxp/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/third_party/nxp/CMSIS/Include/arm_const_structs.h b/third_party/nxp/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 726d06eb6..000000000 --- a/third_party/nxp/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/third_party/nxp/CMSIS/Include/arm_math.h b/third_party/nxp/CMSIS/Include/arm_math.h deleted file mode 100644 index d33f8a9b3..000000000 --- a/third_party/nxp/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/third_party/nxp/CMSIS/Include/cmsis_armcc.h b/third_party/nxp/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 74c49c67d..000000000 --- a/third_party/nxp/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/third_party/nxp/CMSIS/Include/cmsis_armcc_V6.h b/third_party/nxp/CMSIS/Include/cmsis_armcc_V6.h deleted file mode 100644 index cd13240ce..000000000 --- a/third_party/nxp/CMSIS/Include/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/third_party/nxp/CMSIS/Include/cmsis_gcc.h b/third_party/nxp/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index bb89fbba9..000000000 --- a/third_party/nxp/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/third_party/nxp/CMSIS/Include/core_cm0.h b/third_party/nxp/CMSIS/Include/core_cm0.h deleted file mode 100644 index 711dad551..000000000 --- a/third_party/nxp/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/nxp/CMSIS/Include/core_cm0plus.h b/third_party/nxp/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index b04aa3905..000000000 --- a/third_party/nxp/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/nxp/CMSIS/Include/core_cm3.h b/third_party/nxp/CMSIS/Include/core_cm3.h deleted file mode 100644 index b4ac4c7b0..000000000 --- a/third_party/nxp/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1763 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/nxp/CMSIS/Include/core_cm4.h b/third_party/nxp/CMSIS/Include/core_cm4.h deleted file mode 100644 index dc840ebf2..000000000 --- a/third_party/nxp/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1937 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/nxp/CMSIS/Include/core_cm7.h b/third_party/nxp/CMSIS/Include/core_cm7.h deleted file mode 100644 index 3b7530ad5..000000000 --- a/third_party/nxp/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/nxp/CMSIS/Include/core_cmFunc.h b/third_party/nxp/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 652a48af0..000000000 --- a/third_party/nxp/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/third_party/nxp/CMSIS/Include/core_cmInstr.h b/third_party/nxp/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index f474b0e6f..000000000 --- a/third_party/nxp/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/third_party/nxp/CMSIS/Include/core_cmSimd.h b/third_party/nxp/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index 66bf5c2a7..000000000 --- a/third_party/nxp/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/third_party/nxp/CMSIS/Include/core_sc000.h b/third_party/nxp/CMSIS/Include/core_sc000.h deleted file mode 100644 index 514dbd81b..000000000 --- a/third_party/nxp/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,926 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/nxp/CMSIS/Include/core_sc300.h b/third_party/nxp/CMSIS/Include/core_sc300.h deleted file mode 100644 index 8bd18aa31..000000000 --- a/third_party/nxp/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1745 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/nxp/CMakeLists.txt b/third_party/nxp/CMakeLists.txt deleted file mode 100644 index 855843a6d..000000000 --- a/third_party/nxp/CMakeLists.txt +++ /dev/null @@ -1,86 +0,0 @@ -# -# Copyright (c) 2020, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if(OT_PLATFORM STREQUAL "kw41z") - set_property(SOURCE ${PROJECT_SOURCE_DIR}/third_party/nxp/MKW41Z4/startup_MKW41Z4.S PROPERTY LANGUAGE C) - - add_library(nxp-kw41z-driver - MKW41Z4/clock_config.c - MKW41Z4/drivers/fsl_clock.c - MKW41Z4/drivers/fsl_flash.c - MKW41Z4/drivers/fsl_lpuart.c - MKW41Z4/drivers/fsl_gpio.c - MKW41Z4/drivers/fsl_pit.c - MKW41Z4/drivers/fsl_trng.c - MKW41Z4/startup_MKW41Z4.S - MKW41Z4/system_MKW41Z4.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c - MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c - MKW41Z4/XCVR/dbg_ram_capture.c - MKW41Z4/XCVR/fsl_xcvr.c - MKW41Z4/XCVR/fsl_xcvr_trim.c - MKW41Z4/XCVR/ifr_radio.c - ) - - target_compile_definitions(nxp-kw41z-driver - PUBLIC - ${OT_PLATFORM_DEFINES} - -DCPU_MKW41Z512VHT4 - ) - - target_compile_options(nxp-kw41z-driver - PRIVATE - ${OT_CFLAGS} - -Wno-unknown-pragmas - -Wno-sign-compare - -Wno-unused-function - -Wno-unused-parameter - -Wno-empty-body - ) - - target_include_directories(nxp-kw41z-driver - PUBLIC - CMSIS/Include - MKW41Z4 - MKW41Z4/drivers - MKW41Z4/XCVR - MKW41Z4/XCVR/cfgs_kw4x_3x_2x - ) - - target_link_libraries(nxp-kw41z-driver PRIVATE ot-config) -endif() diff --git a/third_party/nxp/MKW41Z4/MKW41Z4.h b/third_party/nxp/MKW41Z4/MKW41Z4.h deleted file mode 100644 index 337105493..000000000 --- a/third_party/nxp/MKW41Z4/MKW41Z4.h +++ /dev/null @@ -1,13023 +0,0 @@ -/* -** ################################################################### -** Processors: MKW41Z256VHT4 -** MKW41Z512CAT4 -** MKW41Z512VHT4 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 -** Version: rev. 1.0, 2015-09-23 -** Build: b170213 -** -** Abstract: -** CMSIS Peripheral Access Layer for MKW41Z4 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2015-09-23) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file MKW41Z4.h - * @version 1.0 - * @date 2015-09-23 - * @brief CMSIS Peripheral Access Layer for MKW41Z4 - * - * CMSIS Peripheral Access Layer for MKW41Z4 - */ - -#ifndef _MKW41Z4_H_ -#define _MKW41Z4_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - -#if !defined(__IAR_SYSTEMS_ICC__) -#pragma GCC diagnostic ignored "-Wpedantic" -#pragma GCC diagnostic ignored "-Wmaybe-uninitialized" -#pragma GCC diagnostic ignored "-Wold-style-declaration" -#pragma GCC diagnostic ignored "-Woverride-init" -#pragma GCC diagnostic ignored "-Wmissing-field-initializers" -#endif - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ - DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ - DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ - DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ - Reserved20_IRQn = 4, /**< Reserved interrupt */ - FTFA_IRQn = 5, /**< Command complete and read collision */ - LVD_LVW_DCDC_IRQn = 6, /**< Low-voltage detect, low-voltage warning, DCDC */ - LLWU_IRQn = 7, /**< Low leakage wakeup Unit */ - I2C0_IRQn = 8, /**< I2C0 interrupt */ - I2C1_IRQn = 9, /**< I2C1 interrupt */ - SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ - TSI0_IRQn = 11, /**< TSI0 single interrupt vector for all sources */ - LPUART0_IRQn = 12, /**< LPUART0 status and error */ - TRNG0_IRQn = 13, /**< TRNG0 interrupt */ - CMT_IRQn = 14, /**< CMT interrupt */ - ADC0_IRQn = 15, /**< ADC0 interrupt */ - CMP0_IRQn = 16, /**< CMP0 interrupt */ - TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ - TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ - TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ - RTC_IRQn = 20, /**< RTC alarm */ - RTC_Seconds_IRQn = 21, /**< RTC seconds */ - PIT_IRQn = 22, /**< PIT interrupt */ - LTC0_IRQn = 23, /**< LTC0 interrupt */ - Radio_0_IRQn = 24, /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 0 */ - DAC0_IRQn = 25, /**< DAC0 interrupt */ - Radio_1_IRQn = 26, /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 1 */ - MCG_IRQn = 27, /**< MCG interrupt */ - LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ - SPI1_IRQn = 29, /**< SPI1 single interrupt vector for all sources */ - PORTA_IRQn = 30, /**< PORTA Pin detect */ - PORTB_PORTC_IRQn = 31 /**< PORTB and PORTC Pin detect */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M0 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ -#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_MKW41Z4.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup edma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the DMA hardware request - * - * Defines the structure for the DMA hardware request collections. The user can configure the - * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index - * of the hardware request varies according to the to SoC. - */ -typedef enum _dma_request_source -{ - kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ - kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ - kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ - kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ - kDmaRequestMux0Reserved4 = 4|0x100U, /**< Reserved4 */ - kDmaRequestMux0Reserved5 = 5|0x100U, /**< Reserved5 */ - kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */ - kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */ - kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ - kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ - kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ - kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ - kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ - kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ - kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ - kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ - kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ - kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ - kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ - kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ - kDmaRequestMux0LTC0InputFIFO = 20|0x100U, /**< LTC0 Input FIFO. */ - kDmaRequestMux0LTC0OutputFIFO = 21|0x100U, /**< LTC0 Output FIFO. */ - kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ - kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ - kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ - kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ - kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ - kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ - kDmaRequestMux0Reserved28 = 28|0x100U, /**< Reserved28 */ - kDmaRequestMux0Reserved29 = 29|0x100U, /**< Reserved29 */ - kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ - kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ - kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ - kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ - kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ - kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ - kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ - kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ - kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ - kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ - kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ - kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ - kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ - kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ - kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ - kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ - kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ - kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ - kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ - kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ - kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ - kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ - kDmaRequestMux0Reserved52 = 52|0x100U, /**< Reserved52 */ - kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ - kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ - kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ - kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ - kDmaRequestMux0TSI0 = 57|0x100U, /**< TSI0. */ - kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ - kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ - kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ - kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name SC1 - ADC Status and Control Registers 1 */ -#define ADC_SC1_ADCH_MASK (0x1FU) -#define ADC_SC1_ADCH_SHIFT (0U) -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) -#define ADC_SC1_DIFF_MASK (0x20U) -#define ADC_SC1_DIFF_SHIFT (5U) -#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) -#define ADC_SC1_AIEN_MASK (0x40U) -#define ADC_SC1_AIEN_SHIFT (6U) -#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) -#define ADC_SC1_COCO_MASK (0x80U) -#define ADC_SC1_COCO_SHIFT (7U) -#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) - -/* The count of ADC_SC1 */ -#define ADC_SC1_COUNT (2U) - -/*! @name CFG1 - ADC Configuration Register 1 */ -#define ADC_CFG1_ADICLK_MASK (0x3U) -#define ADC_CFG1_ADICLK_SHIFT (0U) -#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) -#define ADC_CFG1_MODE_MASK (0xCU) -#define ADC_CFG1_MODE_SHIFT (2U) -#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) -#define ADC_CFG1_ADLSMP_MASK (0x10U) -#define ADC_CFG1_ADLSMP_SHIFT (4U) -#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) -#define ADC_CFG1_ADIV_MASK (0x60U) -#define ADC_CFG1_ADIV_SHIFT (5U) -#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) -#define ADC_CFG1_ADLPC_MASK (0x80U) -#define ADC_CFG1_ADLPC_SHIFT (7U) -#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) - -/*! @name CFG2 - ADC Configuration Register 2 */ -#define ADC_CFG2_ADLSTS_MASK (0x3U) -#define ADC_CFG2_ADLSTS_SHIFT (0U) -#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) -#define ADC_CFG2_ADHSC_MASK (0x4U) -#define ADC_CFG2_ADHSC_SHIFT (2U) -#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) -#define ADC_CFG2_ADACKEN_MASK (0x8U) -#define ADC_CFG2_ADACKEN_SHIFT (3U) -#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) -#define ADC_CFG2_MUXSEL_MASK (0x10U) -#define ADC_CFG2_MUXSEL_SHIFT (4U) -#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) - -/*! @name R - ADC Data Result Register */ -#define ADC_R_D_MASK (0xFFFFU) -#define ADC_R_D_SHIFT (0U) -#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) - -/* The count of ADC_R */ -#define ADC_R_COUNT (2U) - -/*! @name CV1 - Compare Value Registers */ -#define ADC_CV1_CV_MASK (0xFFFFU) -#define ADC_CV1_CV_SHIFT (0U) -#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) - -/*! @name CV2 - Compare Value Registers */ -#define ADC_CV2_CV_MASK (0xFFFFU) -#define ADC_CV2_CV_SHIFT (0U) -#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) - -/*! @name SC2 - Status and Control Register 2 */ -#define ADC_SC2_REFSEL_MASK (0x3U) -#define ADC_SC2_REFSEL_SHIFT (0U) -#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) -#define ADC_SC2_DMAEN_MASK (0x4U) -#define ADC_SC2_DMAEN_SHIFT (2U) -#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) -#define ADC_SC2_ACREN_MASK (0x8U) -#define ADC_SC2_ACREN_SHIFT (3U) -#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) -#define ADC_SC2_ACFGT_MASK (0x10U) -#define ADC_SC2_ACFGT_SHIFT (4U) -#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) -#define ADC_SC2_ACFE_MASK (0x20U) -#define ADC_SC2_ACFE_SHIFT (5U) -#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) -#define ADC_SC2_ADTRG_MASK (0x40U) -#define ADC_SC2_ADTRG_SHIFT (6U) -#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) -#define ADC_SC2_ADACT_MASK (0x80U) -#define ADC_SC2_ADACT_SHIFT (7U) -#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) - -/*! @name SC3 - Status and Control Register 3 */ -#define ADC_SC3_AVGS_MASK (0x3U) -#define ADC_SC3_AVGS_SHIFT (0U) -#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) -#define ADC_SC3_AVGE_MASK (0x4U) -#define ADC_SC3_AVGE_SHIFT (2U) -#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) -#define ADC_SC3_ADCO_MASK (0x8U) -#define ADC_SC3_ADCO_SHIFT (3U) -#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) -#define ADC_SC3_CALF_MASK (0x40U) -#define ADC_SC3_CALF_SHIFT (6U) -#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) -#define ADC_SC3_CAL_MASK (0x80U) -#define ADC_SC3_CAL_SHIFT (7U) -#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) - -/*! @name OFS - ADC Offset Correction Register */ -#define ADC_OFS_OFS_MASK (0xFFFFU) -#define ADC_OFS_OFS_SHIFT (0U) -#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) - -/*! @name PG - ADC Plus-Side Gain Register */ -#define ADC_PG_PG_MASK (0xFFFFU) -#define ADC_PG_PG_SHIFT (0U) -#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) - -/*! @name MG - ADC Minus-Side Gain Register */ -#define ADC_MG_MG_MASK (0xFFFFU) -#define ADC_MG_MG_SHIFT (0U) -#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) - -/*! @name CLPD - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLPD_CLPD_MASK (0x3FU) -#define ADC_CLPD_CLPD_SHIFT (0U) -#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) - -/*! @name CLPS - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLPS_CLPS_MASK (0x3FU) -#define ADC_CLPS_CLPS_SHIFT (0U) -#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) - -/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP4_CLP4_MASK (0x3FFU) -#define ADC_CLP4_CLP4_SHIFT (0U) -#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) - -/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP3_CLP3_MASK (0x1FFU) -#define ADC_CLP3_CLP3_SHIFT (0U) -#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) - -/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP2_CLP2_MASK (0xFFU) -#define ADC_CLP2_CLP2_SHIFT (0U) -#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) - -/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP1_CLP1_MASK (0x7FU) -#define ADC_CLP1_CLP1_SHIFT (0U) -#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) - -/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ -#define ADC_CLP0_CLP0_MASK (0x3FU) -#define ADC_CLP0_CLP0_SHIFT (0U) -#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) - -/*! @name CLMD - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLMD_CLMD_MASK (0x3FU) -#define ADC_CLMD_CLMD_SHIFT (0U) -#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) - -/*! @name CLMS - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLMS_CLMS_MASK (0x3FU) -#define ADC_CLMS_CLMS_SHIFT (0U) -#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) - -/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM4_CLM4_MASK (0x3FFU) -#define ADC_CLM4_CLM4_SHIFT (0U) -#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) - -/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM3_CLM3_MASK (0x1FFU) -#define ADC_CLM3_CLM3_SHIFT (0U) -#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) - -/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM2_CLM2_MASK (0xFFU) -#define ADC_CLM2_CLM2_SHIFT (0U) -#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) - -/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM1_CLM1_MASK (0x7FU) -#define ADC_CLM1_CLM1_SHIFT (0U) -#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) - -/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ -#define ADC_CLM0_CLM0_MASK (0x3FU) -#define ADC_CLM0_CLM0_SHIFT (0U) -#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x4003B000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANT_Peripheral_Access_Layer ANT Peripheral Access Layer - * @{ - */ - -/** ANT - Register Layout Typedef */ -typedef struct { - __IO uint32_t IRQ_CTRL; /**< IRQ CONTROL, offset: 0x0 */ - __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x4 */ - __IO uint32_t T1_CMP; /**< T1 COMPARE, offset: 0x8 */ - __IO uint32_t T2_CMP; /**< T2 COMPARE, offset: 0xC */ - __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0x10 */ - __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x14 */ - __I uint32_t XCVR_STS; /**< TRANSCEIVER STATUS, offset: 0x18 */ - __IO uint32_t XCVR_CFG; /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */ - __IO uint32_t CHANNEL_NUM; /**< CHANNEL NUMBER, offset: 0x20 */ - __IO uint32_t TX_POWER; /**< TRANSMIT POWER, offset: 0x24 */ - __IO uint32_t NTW_ADR_CTRL; /**< NETWORK ADDRESS CONTROL, offset: 0x28 */ - __IO uint32_t NTW_ADR_0; /**< NETWORK ADDRESS 0, offset: 0x2C */ - __IO uint32_t NTW_ADR_1; /**< NETWORK ADDRESS 1, offset: 0x30 */ - __IO uint32_t NTW_ADR_2; /**< NETWORK ADDRESS 2, offset: 0x34 */ - __IO uint32_t NTW_ADR_3; /**< NETWORK ADDRESS 3, offset: 0x38 */ - __IO uint32_t RX_WATERMARK; /**< RX WATERMARK, offset: 0x3C */ - __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x40 */ - __I uint32_t PART_ID; /**< PART ID, offset: 0x44 */ - uint8_t RESERVED_0[184]; - __IO uint16_t PACKET_BUFFER[64]; /**< PACKET BUFFER, array offset: 0x100, array step: 0x2 */ -} ANT_Type; - -/* ---------------------------------------------------------------------------- - -- ANT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANT_Register_Masks ANT Register Masks - * @{ - */ - -/*! @name IRQ_CTRL - IRQ CONTROL */ -#define ANT_IRQ_CTRL_SEQ_END_IRQ_MASK (0x1U) -#define ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT (0U) -#define ANT_IRQ_CTRL_SEQ_END_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_MASK) -#define ANT_IRQ_CTRL_TX_IRQ_MASK (0x2U) -#define ANT_IRQ_CTRL_TX_IRQ_SHIFT (1U) -#define ANT_IRQ_CTRL_TX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_MASK) -#define ANT_IRQ_CTRL_RX_IRQ_MASK (0x4U) -#define ANT_IRQ_CTRL_RX_IRQ_SHIFT (2U) -#define ANT_IRQ_CTRL_RX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_MASK) -#define ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK (0x8U) -#define ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT (3U) -#define ANT_IRQ_CTRL_NTW_ADR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK) -#define ANT_IRQ_CTRL_T1_IRQ_MASK (0x10U) -#define ANT_IRQ_CTRL_T1_IRQ_SHIFT (4U) -#define ANT_IRQ_CTRL_T1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_MASK) -#define ANT_IRQ_CTRL_T2_IRQ_MASK (0x20U) -#define ANT_IRQ_CTRL_T2_IRQ_SHIFT (5U) -#define ANT_IRQ_CTRL_T2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_MASK) -#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK (0x40U) -#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT (6U) -#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK) -#define ANT_IRQ_CTRL_WAKE_IRQ_MASK (0x80U) -#define ANT_IRQ_CTRL_WAKE_IRQ_SHIFT (7U) -#define ANT_IRQ_CTRL_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_MASK) -#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK (0x100U) -#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT (8U) -#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK) -#define ANT_IRQ_CTRL_TSM_IRQ_MASK (0x200U) -#define ANT_IRQ_CTRL_TSM_IRQ_SHIFT (9U) -#define ANT_IRQ_CTRL_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_MASK) -#define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK (0x10000U) -#define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT (16U) -#define ANT_IRQ_CTRL_SEQ_END_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_TX_IRQ_EN_MASK (0x20000U) -#define ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT (17U) -#define ANT_IRQ_CTRL_TX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_RX_IRQ_EN_MASK (0x40000U) -#define ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT (18U) -#define ANT_IRQ_CTRL_RX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK (0x80000U) -#define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT (19U) -#define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_T1_IRQ_EN_MASK (0x100000U) -#define ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT (20U) -#define ANT_IRQ_CTRL_T1_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U) -#define ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT (21U) -#define ANT_IRQ_CTRL_T2_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK (0x400000U) -#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT (22U) -#define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK (0x800000U) -#define ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT (23U) -#define ANT_IRQ_CTRL_WAKE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U) -#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U) -#define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_TSM_IRQ_EN_MASK (0x2000000U) -#define ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT (25U) -#define ANT_IRQ_CTRL_TSM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_ANT_IRQ_EN_MASK (0x4000000U) -#define ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT (26U) -#define ANT_IRQ_CTRL_ANT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_ANT_IRQ_EN_MASK) -#define ANT_IRQ_CTRL_CRC_IGNORE_MASK (0x8000000U) -#define ANT_IRQ_CTRL_CRC_IGNORE_SHIFT (27U) -#define ANT_IRQ_CTRL_CRC_IGNORE(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_IGNORE_SHIFT)) & ANT_IRQ_CTRL_CRC_IGNORE_MASK) -#define ANT_IRQ_CTRL_CRC_VALID_MASK (0x80000000U) -#define ANT_IRQ_CTRL_CRC_VALID_SHIFT (31U) -#define ANT_IRQ_CTRL_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_VALID_SHIFT)) & ANT_IRQ_CTRL_CRC_VALID_MASK) - -/*! @name EVENT_TMR - EVENT TIMER */ -#define ANT_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFFU) -#define ANT_EVENT_TMR_EVENT_TMR_SHIFT (0U) -#define ANT_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_MASK) -#define ANT_EVENT_TMR_EVENT_TMR_LD_MASK (0x1000000U) -#define ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT (24U) -#define ANT_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_LD_MASK) -#define ANT_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2000000U) -#define ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT (25U) -#define ANT_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_ADD_MASK) - -/*! @name T1_CMP - T1 COMPARE */ -#define ANT_T1_CMP_T1_CMP_MASK (0xFFFFFFU) -#define ANT_T1_CMP_T1_CMP_SHIFT (0U) -#define ANT_T1_CMP_T1_CMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_SHIFT)) & ANT_T1_CMP_T1_CMP_MASK) -#define ANT_T1_CMP_T1_CMP_EN_MASK (0x1000000U) -#define ANT_T1_CMP_T1_CMP_EN_SHIFT (24U) -#define ANT_T1_CMP_T1_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_EN_SHIFT)) & ANT_T1_CMP_T1_CMP_EN_MASK) - -/*! @name T2_CMP - T2 COMPARE */ -#define ANT_T2_CMP_T2_CMP_MASK (0xFFFFFFU) -#define ANT_T2_CMP_T2_CMP_SHIFT (0U) -#define ANT_T2_CMP_T2_CMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_SHIFT)) & ANT_T2_CMP_T2_CMP_MASK) -#define ANT_T2_CMP_T2_CMP_EN_MASK (0x1000000U) -#define ANT_T2_CMP_T2_CMP_EN_SHIFT (24U) -#define ANT_T2_CMP_T2_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_EN_SHIFT)) & ANT_T2_CMP_T2_CMP_EN_MASK) - -/*! @name TIMESTAMP - TIMESTAMP */ -#define ANT_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU) -#define ANT_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define ANT_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_TIMESTAMP_TIMESTAMP_SHIFT)) & ANT_TIMESTAMP_TIMESTAMP_MASK) - -/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */ -#define ANT_XCVR_CTRL_SEQCMD_MASK (0xFU) -#define ANT_XCVR_CTRL_SEQCMD_SHIFT (0U) -#define ANT_XCVR_CTRL_SEQCMD(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_SEQCMD_SHIFT)) & ANT_XCVR_CTRL_SEQCMD_MASK) -#define ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK (0x3F00U) -#define ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT (8U) -#define ANT_XCVR_CTRL_TX_PKT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK) -#define ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK (0x3F0000U) -#define ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT (16U) -#define ANT_XCVR_CTRL_RX_PKT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK) -#define ANT_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U) -#define ANT_XCVR_CTRL_CMDDEC_CS_SHIFT (24U) -#define ANT_XCVR_CTRL_CMDDEC_CS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_CMDDEC_CS_SHIFT)) & ANT_XCVR_CTRL_CMDDEC_CS_MASK) -#define ANT_XCVR_CTRL_XCVR_BUSY_MASK (0x80000000U) -#define ANT_XCVR_CTRL_XCVR_BUSY_SHIFT (31U) -#define ANT_XCVR_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_XCVR_BUSY_SHIFT)) & ANT_XCVR_CTRL_XCVR_BUSY_MASK) - -/*! @name XCVR_STS - TRANSCEIVER STATUS */ -#define ANT_XCVR_STS_TX_START_T1_PEND_MASK (0x1U) -#define ANT_XCVR_STS_TX_START_T1_PEND_SHIFT (0U) -#define ANT_XCVR_STS_TX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T1_PEND_MASK) -#define ANT_XCVR_STS_TX_START_T2_PEND_MASK (0x2U) -#define ANT_XCVR_STS_TX_START_T2_PEND_SHIFT (1U) -#define ANT_XCVR_STS_TX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T2_PEND_MASK) -#define ANT_XCVR_STS_TX_IN_WARMUP_MASK (0x4U) -#define ANT_XCVR_STS_TX_IN_WARMUP_SHIFT (2U) -#define ANT_XCVR_STS_TX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMUP_MASK) -#define ANT_XCVR_STS_TX_IN_PROGRESS_MASK (0x8U) -#define ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT (3U) -#define ANT_XCVR_STS_TX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_TX_IN_PROGRESS_MASK) -#define ANT_XCVR_STS_TX_IN_WARMDN_MASK (0x10U) -#define ANT_XCVR_STS_TX_IN_WARMDN_SHIFT (4U) -#define ANT_XCVR_STS_TX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMDN_MASK) -#define ANT_XCVR_STS_RX_START_T1_PEND_MASK (0x20U) -#define ANT_XCVR_STS_RX_START_T1_PEND_SHIFT (5U) -#define ANT_XCVR_STS_RX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T1_PEND_MASK) -#define ANT_XCVR_STS_RX_START_T2_PEND_MASK (0x40U) -#define ANT_XCVR_STS_RX_START_T2_PEND_SHIFT (6U) -#define ANT_XCVR_STS_RX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T2_PEND_MASK) -#define ANT_XCVR_STS_RX_STOP_T1_PEND_MASK (0x80U) -#define ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT (7U) -#define ANT_XCVR_STS_RX_STOP_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T1_PEND_MASK) -#define ANT_XCVR_STS_RX_STOP_T2_PEND_MASK (0x100U) -#define ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT (8U) -#define ANT_XCVR_STS_RX_STOP_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T2_PEND_MASK) -#define ANT_XCVR_STS_RX_IN_WARMUP_MASK (0x200U) -#define ANT_XCVR_STS_RX_IN_WARMUP_SHIFT (9U) -#define ANT_XCVR_STS_RX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMUP_MASK) -#define ANT_XCVR_STS_RX_IN_SEARCH_MASK (0x400U) -#define ANT_XCVR_STS_RX_IN_SEARCH_SHIFT (10U) -#define ANT_XCVR_STS_RX_IN_SEARCH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_SEARCH_SHIFT)) & ANT_XCVR_STS_RX_IN_SEARCH_MASK) -#define ANT_XCVR_STS_RX_IN_PROGRESS_MASK (0x800U) -#define ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT (11U) -#define ANT_XCVR_STS_RX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_RX_IN_PROGRESS_MASK) -#define ANT_XCVR_STS_RX_IN_WARMDN_MASK (0x1000U) -#define ANT_XCVR_STS_RX_IN_WARMDN_SHIFT (12U) -#define ANT_XCVR_STS_RX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMDN_MASK) -#define ANT_XCVR_STS_CRC_VALID_MASK (0x8000U) -#define ANT_XCVR_STS_CRC_VALID_SHIFT (15U) -#define ANT_XCVR_STS_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_CRC_VALID_SHIFT)) & ANT_XCVR_STS_CRC_VALID_MASK) -#define ANT_XCVR_STS_RSSI_MASK (0xFF0000U) -#define ANT_XCVR_STS_RSSI_SHIFT (16U) -#define ANT_XCVR_STS_RSSI(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RSSI_SHIFT)) & ANT_XCVR_STS_RSSI_MASK) - -/*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */ -#define ANT_XCVR_CFG_TX_WHITEN_DIS_MASK (0x1U) -#define ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT (0U) -#define ANT_XCVR_CFG_TX_WHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_TX_WHITEN_DIS_MASK) -#define ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U) -#define ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT (1U) -#define ANT_XCVR_CFG_RX_DEWHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK) -#define ANT_XCVR_CFG_SW_CRC_EN_MASK (0x4U) -#define ANT_XCVR_CFG_SW_CRC_EN_SHIFT (2U) -#define ANT_XCVR_CFG_SW_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_SW_CRC_EN_SHIFT)) & ANT_XCVR_CFG_SW_CRC_EN_MASK) -#define ANT_XCVR_CFG_PREAMBLE_SZ_MASK (0x30U) -#define ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT (4U) -#define ANT_XCVR_CFG_PREAMBLE_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & ANT_XCVR_CFG_PREAMBLE_SZ_MASK) -#define ANT_XCVR_CFG_TX_WARMUP_MASK (0xFF00U) -#define ANT_XCVR_CFG_TX_WARMUP_SHIFT (8U) -#define ANT_XCVR_CFG_TX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WARMUP_SHIFT)) & ANT_XCVR_CFG_TX_WARMUP_MASK) -#define ANT_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U) -#define ANT_XCVR_CFG_RX_WARMUP_SHIFT (16U) -#define ANT_XCVR_CFG_RX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_WARMUP_SHIFT)) & ANT_XCVR_CFG_RX_WARMUP_MASK) - -/*! @name CHANNEL_NUM - CHANNEL NUMBER */ -#define ANT_CHANNEL_NUM_CHANNEL_NUM_MASK (0x7FU) -#define ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT (0U) -#define ANT_CHANNEL_NUM_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & ANT_CHANNEL_NUM_CHANNEL_NUM_MASK) - -/*! @name TX_POWER - TRANSMIT POWER */ -#define ANT_TX_POWER_TX_POWER_MASK (0x3FU) -#define ANT_TX_POWER_TX_POWER_SHIFT (0U) -#define ANT_TX_POWER_TX_POWER(x) (((uint32_t)(((uint32_t)(x)) << ANT_TX_POWER_TX_POWER_SHIFT)) & ANT_TX_POWER_TX_POWER_MASK) - -/*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */ -#define ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK (0xFU) -#define ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT (0U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK (0xF0U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT (4U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_MCH(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK (0x300U) -#define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT (8U) -#define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK (0xC00U) -#define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT (10U) -#define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK (0x3000U) -#define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT (12U) -#define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK (0xC000U) -#define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT (14U) -#define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK (0x70000U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT (16U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR0(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK (0x700000U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT (20U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR1(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK (0x7000000U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT (24U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR2(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK (0x70000000U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT (28U) -#define ANT_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK) - -/*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */ -#define ANT_NTW_ADR_0_NTW_ADR_0_MASK (0xFFFFFFFFU) -#define ANT_NTW_ADR_0_NTW_ADR_0_SHIFT (0U) -#define ANT_NTW_ADR_0_NTW_ADR_0(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_0_NTW_ADR_0_SHIFT)) & ANT_NTW_ADR_0_NTW_ADR_0_MASK) - -/*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */ -#define ANT_NTW_ADR_1_NTW_ADR_1_MASK (0xFFFFFFFFU) -#define ANT_NTW_ADR_1_NTW_ADR_1_SHIFT (0U) -#define ANT_NTW_ADR_1_NTW_ADR_1(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_1_NTW_ADR_1_SHIFT)) & ANT_NTW_ADR_1_NTW_ADR_1_MASK) - -/*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */ -#define ANT_NTW_ADR_2_NTW_ADR_2_MASK (0xFFFFFFFFU) -#define ANT_NTW_ADR_2_NTW_ADR_2_SHIFT (0U) -#define ANT_NTW_ADR_2_NTW_ADR_2(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_2_NTW_ADR_2_SHIFT)) & ANT_NTW_ADR_2_NTW_ADR_2_MASK) - -/*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */ -#define ANT_NTW_ADR_3_NTW_ADR_3_MASK (0xFFFFFFFFU) -#define ANT_NTW_ADR_3_NTW_ADR_3_SHIFT (0U) -#define ANT_NTW_ADR_3_NTW_ADR_3(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_3_NTW_ADR_3_SHIFT)) & ANT_NTW_ADR_3_NTW_ADR_3_MASK) - -/*! @name RX_WATERMARK - RX WATERMARK */ -#define ANT_RX_WATERMARK_RX_WATERMARK_MASK (0x7FU) -#define ANT_RX_WATERMARK_RX_WATERMARK_SHIFT (0U) -#define ANT_RX_WATERMARK_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_RX_WATERMARK_SHIFT)) & ANT_RX_WATERMARK_RX_WATERMARK_MASK) -#define ANT_RX_WATERMARK_BYTE_COUNTER_MASK (0x7F0000U) -#define ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT (16U) -#define ANT_RX_WATERMARK_BYTE_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & ANT_RX_WATERMARK_BYTE_COUNTER_MASK) - -/*! @name DSM_CTRL - DSM CONTROL */ -#define ANT_DSM_CTRL_ANT_SLEEP_EN_MASK (0x1U) -#define ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT (0U) -#define ANT_DSM_CTRL_ANT_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT)) & ANT_DSM_CTRL_ANT_SLEEP_EN_MASK) - -/*! @name PART_ID - PART ID */ -#define ANT_PART_ID_PART_ID_MASK (0xFFU) -#define ANT_PART_ID_PART_ID_SHIFT (0U) -#define ANT_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << ANT_PART_ID_PART_ID_SHIFT)) & ANT_PART_ID_PART_ID_MASK) - -/*! @name PACKET_BUFFER - PACKET BUFFER */ -#define ANT_PACKET_BUFFER_PACKET_BUFFER_MASK (0xFFFFU) -#define ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT (0U) -#define ANT_PACKET_BUFFER_PACKET_BUFFER(x) (((uint16_t)(((uint16_t)(x)) << ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT)) & ANT_PACKET_BUFFER_PACKET_BUFFER_MASK) - -/* The count of ANT_PACKET_BUFFER */ -#define ANT_PACKET_BUFFER_COUNT (64U) - - -/*! - * @} - */ /* end of group ANT_Register_Masks */ - - -/* ANT - Peripheral instance base addresses */ -/** Peripheral ANT base address */ -#define ANT_BASE (0x4005E000u) -/** Peripheral ANT base pointer */ -#define ANT ((ANT_Type *)ANT_BASE) -/** Array initializer of ANT peripheral base addresses */ -#define ANT_BASE_ADDRS { ANT_BASE } -/** Array initializer of ANT peripheral base pointers */ -#define ANT_BASE_PTRS { ANT } - -/*! - * @} - */ /* end of group ANT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- BTLE_RF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup BTLE_RF_Peripheral_Access_Layer BTLE_RF Peripheral Access Layer - * @{ - */ - -/** BTLE_RF - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1536]; - __I uint16_t BLE_PART_ID; /**< BLUETOOTH LOW ENERGY PART ID, offset: 0x600 */ - uint8_t RESERVED_1[2]; - __I uint16_t DSM_STATUS; /**< BLE DSM STATUS, offset: 0x604 */ - uint8_t RESERVED_2[2]; - __IO uint16_t MISC_CTRL; /**< BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL, offset: 0x608 */ -} BTLE_RF_Type; - -/* ---------------------------------------------------------------------------- - -- BTLE_RF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup BTLE_RF_Register_Masks BTLE_RF Register Masks - * @{ - */ - -/*! @name BLE_PART_ID - BLUETOOTH LOW ENERGY PART ID */ -#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK (0xFFFFU) -#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT (0U) -#define BTLE_RF_BLE_PART_ID_BLE_PART_ID(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT)) & BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK) - -/*! @name DSM_STATUS - BLE DSM STATUS */ -#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK (0x1U) -#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT (0U) -#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT)) & BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK) -#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK (0x2U) -#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT (1U) -#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT)) & BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK) -#define BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK (0x4U) -#define BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT (2U) -#define BTLE_RF_DSM_STATUS_XCVR_BUSY(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT)) & BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK) - -/*! @name MISC_CTRL - BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL */ -#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK (0x2U) -#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT (1U) -#define BTLE_RF_MISC_CTRL_TSM_INTR_EN(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT)) & BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK) - - -/*! - * @} - */ /* end of group BTLE_RF_Register_Masks */ - - -/* BTLE_RF - Peripheral instance base addresses */ -/** Peripheral BTLE_RF base address */ -#define BTLE_RF_BASE (0x4005B000u) -/** Peripheral BTLE_RF base pointer */ -#define BTLE_RF ((BTLE_RF_Type *)BTLE_RF_BASE) -/** Array initializer of BTLE_RF peripheral base addresses */ -#define BTLE_RF_BASE_ADDRS { BTLE_RF_BASE } -/** Array initializer of BTLE_RF peripheral base pointers */ -#define BTLE_RF_BASE_PTRS { BTLE_RF } - -/*! - * @} - */ /* end of group BTLE_RF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer - * @{ - */ - -/** CMP - Register Layout Typedef */ -typedef struct { - __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ - __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ - __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ - __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ - __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ - __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ -} CMP_Type; - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/*! @name CR0 - CMP Control Register 0 */ -#define CMP_CR0_HYSTCTR_MASK (0x3U) -#define CMP_CR0_HYSTCTR_SHIFT (0U) -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) -#define CMP_CR0_FILTER_CNT_MASK (0x70U) -#define CMP_CR0_FILTER_CNT_SHIFT (4U) -#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) - -/*! @name CR1 - CMP Control Register 1 */ -#define CMP_CR1_EN_MASK (0x1U) -#define CMP_CR1_EN_SHIFT (0U) -#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) -#define CMP_CR1_OPE_MASK (0x2U) -#define CMP_CR1_OPE_SHIFT (1U) -#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) -#define CMP_CR1_COS_MASK (0x4U) -#define CMP_CR1_COS_SHIFT (2U) -#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) -#define CMP_CR1_INV_MASK (0x8U) -#define CMP_CR1_INV_SHIFT (3U) -#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) -#define CMP_CR1_PMODE_MASK (0x10U) -#define CMP_CR1_PMODE_SHIFT (4U) -#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) -#define CMP_CR1_TRIGM_MASK (0x20U) -#define CMP_CR1_TRIGM_SHIFT (5U) -#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) -#define CMP_CR1_WE_MASK (0x40U) -#define CMP_CR1_WE_SHIFT (6U) -#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) -#define CMP_CR1_SE_MASK (0x80U) -#define CMP_CR1_SE_SHIFT (7U) -#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) - -/*! @name FPR - CMP Filter Period Register */ -#define CMP_FPR_FILT_PER_MASK (0xFFU) -#define CMP_FPR_FILT_PER_SHIFT (0U) -#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) - -/*! @name SCR - CMP Status and Control Register */ -#define CMP_SCR_COUT_MASK (0x1U) -#define CMP_SCR_COUT_SHIFT (0U) -#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) -#define CMP_SCR_CFF_MASK (0x2U) -#define CMP_SCR_CFF_SHIFT (1U) -#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) -#define CMP_SCR_CFR_MASK (0x4U) -#define CMP_SCR_CFR_SHIFT (2U) -#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) -#define CMP_SCR_IEF_MASK (0x8U) -#define CMP_SCR_IEF_SHIFT (3U) -#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) -#define CMP_SCR_IER_MASK (0x10U) -#define CMP_SCR_IER_SHIFT (4U) -#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) -#define CMP_SCR_DMAEN_MASK (0x40U) -#define CMP_SCR_DMAEN_SHIFT (6U) -#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) - -/*! @name DACCR - DAC Control Register */ -#define CMP_DACCR_VOSEL_MASK (0x3FU) -#define CMP_DACCR_VOSEL_SHIFT (0U) -#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) -#define CMP_DACCR_VRSEL_MASK (0x40U) -#define CMP_DACCR_VRSEL_SHIFT (6U) -#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) -#define CMP_DACCR_DACEN_MASK (0x80U) -#define CMP_DACCR_DACEN_SHIFT (7U) -#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) - -/*! @name MUXCR - MUX Control Register */ -#define CMP_MUXCR_MSEL_MASK (0x7U) -#define CMP_MUXCR_MSEL_SHIFT (0U) -#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) -#define CMP_MUXCR_PSEL_MASK (0x38U) -#define CMP_MUXCR_PSEL_SHIFT (3U) -#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) -#define CMP_MUXCR_PSTM_MASK (0x80U) -#define CMP_MUXCR_PSTM_SHIFT (7U) -#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) - - -/*! - * @} - */ /* end of group CMP_Register_Masks */ - - -/* CMP - Peripheral instance base addresses */ -/** Peripheral CMP0 base address */ -#define CMP0_BASE (0x40073000u) -/** Peripheral CMP0 base pointer */ -#define CMP0 ((CMP_Type *)CMP0_BASE) -/** Array initializer of CMP peripheral base addresses */ -#define CMP_BASE_ADDRS { CMP0_BASE } -/** Array initializer of CMP peripheral base pointers */ -#define CMP_BASE_PTRS { CMP0 } -/** Interrupt vectors for the CMP peripheral type */ -#define CMP_IRQS { CMP0_IRQn } - -/*! - * @} - */ /* end of group CMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CMT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer - * @{ - */ - -/** CMT - Register Layout Typedef */ -typedef struct { - __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ - __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ - __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ - __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ - __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ - __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ - __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ - __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ - __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ - __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ - __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ - __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ -} CMT_Type; - -/* ---------------------------------------------------------------------------- - -- CMT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMT_Register_Masks CMT Register Masks - * @{ - */ - -/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ -#define CMT_CGH1_PH_MASK (0xFFU) -#define CMT_CGH1_PH_SHIFT (0U) -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) - -/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ -#define CMT_CGL1_PL_MASK (0xFFU) -#define CMT_CGL1_PL_SHIFT (0U) -#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) - -/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ -#define CMT_CGH2_SH_MASK (0xFFU) -#define CMT_CGH2_SH_SHIFT (0U) -#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) - -/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ -#define CMT_CGL2_SL_MASK (0xFFU) -#define CMT_CGL2_SL_SHIFT (0U) -#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) - -/*! @name OC - CMT Output Control Register */ -#define CMT_OC_IROPEN_MASK (0x20U) -#define CMT_OC_IROPEN_SHIFT (5U) -#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) -#define CMT_OC_CMTPOL_MASK (0x40U) -#define CMT_OC_CMTPOL_SHIFT (6U) -#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) -#define CMT_OC_IROL_MASK (0x80U) -#define CMT_OC_IROL_SHIFT (7U) -#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) - -/*! @name MSC - CMT Modulator Status and Control Register */ -#define CMT_MSC_MCGEN_MASK (0x1U) -#define CMT_MSC_MCGEN_SHIFT (0U) -#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) -#define CMT_MSC_EOCIE_MASK (0x2U) -#define CMT_MSC_EOCIE_SHIFT (1U) -#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) -#define CMT_MSC_FSK_MASK (0x4U) -#define CMT_MSC_FSK_SHIFT (2U) -#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) -#define CMT_MSC_BASE_MASK (0x8U) -#define CMT_MSC_BASE_SHIFT (3U) -#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) -#define CMT_MSC_EXSPC_MASK (0x10U) -#define CMT_MSC_EXSPC_SHIFT (4U) -#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) -#define CMT_MSC_CMTDIV_MASK (0x60U) -#define CMT_MSC_CMTDIV_SHIFT (5U) -#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) -#define CMT_MSC_EOCF_MASK (0x80U) -#define CMT_MSC_EOCF_SHIFT (7U) -#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) - -/*! @name CMD1 - CMT Modulator Data Register Mark High */ -#define CMT_CMD1_MB_MASK (0xFFU) -#define CMT_CMD1_MB_SHIFT (0U) -#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) - -/*! @name CMD2 - CMT Modulator Data Register Mark Low */ -#define CMT_CMD2_MB_MASK (0xFFU) -#define CMT_CMD2_MB_SHIFT (0U) -#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) - -/*! @name CMD3 - CMT Modulator Data Register Space High */ -#define CMT_CMD3_SB_MASK (0xFFU) -#define CMT_CMD3_SB_SHIFT (0U) -#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) - -/*! @name CMD4 - CMT Modulator Data Register Space Low */ -#define CMT_CMD4_SB_MASK (0xFFU) -#define CMT_CMD4_SB_SHIFT (0U) -#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) - -/*! @name PPS - CMT Primary Prescaler Register */ -#define CMT_PPS_PPSDIV_MASK (0xFU) -#define CMT_PPS_PPSDIV_SHIFT (0U) -#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) - -/*! @name DMA - CMT Direct Memory Access Register */ -#define CMT_DMA_DMA_MASK (0x1U) -#define CMT_DMA_DMA_SHIFT (0U) -#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) - - -/*! - * @} - */ /* end of group CMT_Register_Masks */ - - -/* CMT - Peripheral instance base addresses */ -/** Peripheral CMT base address */ -#define CMT_BASE (0x40062000u) -/** Peripheral CMT base pointer */ -#define CMT ((CMT_Type *)CMT_BASE) -/** Array initializer of CMT peripheral base addresses */ -#define CMT_BASE_ADDRS { CMT_BASE } -/** Array initializer of CMT peripheral base pointers */ -#define CMT_BASE_PTRS { CMT } -/** Interrupt vectors for the CMT peripheral type */ -#define CMT_IRQS { CMT_IRQn } - -/*! - * @} - */ /* end of group CMT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DAC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer - * @{ - */ - -/** DAC - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x2 */ - __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ - __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ - } DAT[2]; - uint8_t RESERVED_0[28]; - __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ - __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ - __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ - __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ -} DAC_Type; - -/* ---------------------------------------------------------------------------- - -- DAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Register_Masks DAC Register Masks - * @{ - */ - -/*! @name DATL - DAC Data Low Register */ -#define DAC_DATL_DATA0_MASK (0xFFU) -#define DAC_DATL_DATA0_SHIFT (0U) -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) - -/* The count of DAC_DATL */ -#define DAC_DATL_COUNT (2U) - -/*! @name DATH - DAC Data High Register */ -#define DAC_DATH_DATA1_MASK (0xFU) -#define DAC_DATH_DATA1_SHIFT (0U) -#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) - -/* The count of DAC_DATH */ -#define DAC_DATH_COUNT (2U) - -/*! @name SR - DAC Status Register */ -#define DAC_SR_DACBFRPBF_MASK (0x1U) -#define DAC_SR_DACBFRPBF_SHIFT (0U) -#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) -#define DAC_SR_DACBFRPTF_MASK (0x2U) -#define DAC_SR_DACBFRPTF_SHIFT (1U) -#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) -#define DAC_SR_DACBFWMF_MASK (0x4U) -#define DAC_SR_DACBFWMF_SHIFT (2U) -#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) - -/*! @name C0 - DAC Control Register */ -#define DAC_C0_DACBBIEN_MASK (0x1U) -#define DAC_C0_DACBBIEN_SHIFT (0U) -#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) -#define DAC_C0_DACBTIEN_MASK (0x2U) -#define DAC_C0_DACBTIEN_SHIFT (1U) -#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) -#define DAC_C0_DACBWIEN_MASK (0x4U) -#define DAC_C0_DACBWIEN_SHIFT (2U) -#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) -#define DAC_C0_LPEN_MASK (0x8U) -#define DAC_C0_LPEN_SHIFT (3U) -#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) -#define DAC_C0_DACSWTRG_MASK (0x10U) -#define DAC_C0_DACSWTRG_SHIFT (4U) -#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) -#define DAC_C0_DACTRGSEL_MASK (0x20U) -#define DAC_C0_DACTRGSEL_SHIFT (5U) -#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) -#define DAC_C0_DACRFS_MASK (0x40U) -#define DAC_C0_DACRFS_SHIFT (6U) -#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) -#define DAC_C0_DACEN_MASK (0x80U) -#define DAC_C0_DACEN_SHIFT (7U) -#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) - -/*! @name C1 - DAC Control Register 1 */ -#define DAC_C1_DACBFEN_MASK (0x1U) -#define DAC_C1_DACBFEN_SHIFT (0U) -#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) -#define DAC_C1_DACBFMD_MASK (0x4U) -#define DAC_C1_DACBFMD_SHIFT (2U) -#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) -#define DAC_C1_DACBFWM_MASK (0x18U) -#define DAC_C1_DACBFWM_SHIFT (3U) -#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) -#define DAC_C1_DMAEN_MASK (0x80U) -#define DAC_C1_DMAEN_SHIFT (7U) -#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) - -/*! @name C2 - DAC Control Register 2 */ -#define DAC_C2_DACBFUP_MASK (0x1U) -#define DAC_C2_DACBFUP_SHIFT (0U) -#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) -#define DAC_C2_DACBFRP_MASK (0x10U) -#define DAC_C2_DACBFRP_SHIFT (4U) -#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) - - -/*! - * @} - */ /* end of group DAC_Register_Masks */ - - -/* DAC - Peripheral instance base addresses */ -/** Peripheral DAC0 base address */ -#define DAC0_BASE (0x4003F000u) -/** Peripheral DAC0 base pointer */ -#define DAC0 ((DAC_Type *)DAC0_BASE) -/** Array initializer of DAC peripheral base addresses */ -#define DAC_BASE_ADDRS { DAC0_BASE } -/** Array initializer of DAC peripheral base pointers */ -#define DAC_BASE_PTRS { DAC0 } -/** Interrupt vectors for the DAC peripheral type */ -#define DAC_IRQS { DAC0_IRQn } - -/*! - * @} - */ /* end of group DAC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DCDC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer - * @{ - */ - -/** DCDC - Register Layout Typedef */ -typedef struct { - __IO uint32_t REG0; /**< DCDC REGISTER 0, offset: 0x0 */ - __IO uint32_t REG1; /**< DCDC REGISTER 1, offset: 0x4 */ - __IO uint32_t REG2; /**< DCDC REGISTER 2, offset: 0x8 */ - __IO uint32_t REG3; /**< DCDC REGISTER 3, offset: 0xC */ - __IO uint32_t REG4; /**< DCDC REGISTER 4, offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t REG6; /**< DCDC REGISTER 6, offset: 0x18 */ - __IO uint32_t REG7; /**< DCDC REGISTER 7, offset: 0x1C */ -} DCDC_Type; - -/* ---------------------------------------------------------------------------- - -- DCDC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DCDC_Register_Masks DCDC Register Masks - * @{ - */ - -/*! @name REG0 - DCDC REGISTER 0 */ -#define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) -#define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) -#define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK) -#define DCDC_REG0_DCDC_SEL_CLK_MASK (0x4U) -#define DCDC_REG0_DCDC_SEL_CLK_SHIFT (2U) -#define DCDC_REG0_DCDC_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_SEL_CLK_SHIFT)) & DCDC_REG0_DCDC_SEL_CLK_MASK) -#define DCDC_REG0_DCDC_PWD_OSC_INT_MASK (0x8U) -#define DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT (3U) -#define DCDC_REG0_DCDC_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT)) & DCDC_REG0_DCDC_PWD_OSC_INT_MASK) -#define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK (0x200U) -#define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT (9U) -#define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT)) & DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK) -#define DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK (0xC00U) -#define DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT (10U) -#define DCDC_REG0_DCDC_VBAT_DIV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT)) & DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK) -#define DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK (0x60000U) -#define DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT (17U) -#define DCDC_REG0_DCDC_LP_STATE_HYS_L(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK) -#define DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK (0x180000U) -#define DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT (19U) -#define DCDC_REG0_DCDC_LP_STATE_HYS_H(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK) -#define DCDC_REG0_HYST_LP_COMP_ADJ_MASK (0x200000U) -#define DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT (21U) -#define DCDC_REG0_HYST_LP_COMP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT)) & DCDC_REG0_HYST_LP_COMP_ADJ_MASK) -#define DCDC_REG0_HYST_LP_CMP_DISABLE_MASK (0x400000U) -#define DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT (22U) -#define DCDC_REG0_HYST_LP_CMP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT)) & DCDC_REG0_HYST_LP_CMP_DISABLE_MASK) -#define DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK (0x800000U) -#define DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT (23U) -#define DCDC_REG0_OFFSET_RSNS_LP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK) -#define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK (0x1000000U) -#define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT (24U) -#define DCDC_REG0_OFFSET_RSNS_LP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK) -#define DCDC_REG0_DCDC_LESS_I_MASK (0x2000000U) -#define DCDC_REG0_DCDC_LESS_I_SHIFT (25U) -#define DCDC_REG0_DCDC_LESS_I(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LESS_I_SHIFT)) & DCDC_REG0_DCDC_LESS_I_MASK) -#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) -#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) -#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) -#define DCDC_REG0_DCDC_XTALOK_DISABLE_MASK (0x8000000U) -#define DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT (27U) -#define DCDC_REG0_DCDC_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_DCDC_XTALOK_DISABLE_MASK) -#define DCDC_REG0_PSWITCH_STATUS_MASK (0x10000000U) -#define DCDC_REG0_PSWITCH_STATUS_SHIFT (28U) -#define DCDC_REG0_PSWITCH_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PSWITCH_STATUS_SHIFT)) & DCDC_REG0_PSWITCH_STATUS_MASK) -#define DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK (0x20000000U) -#define DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT (29U) -#define DCDC_REG0_VLPS_CONFIG_DCDC_HP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT)) & DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK) -#define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK (0x40000000U) -#define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT (30U) -#define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT)) & DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK) -#define DCDC_REG0_DCDC_STS_DC_OK_MASK (0x80000000U) -#define DCDC_REG0_DCDC_STS_DC_OK_SHIFT (31U) -#define DCDC_REG0_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_STS_DC_OK_SHIFT)) & DCDC_REG0_DCDC_STS_DC_OK_MASK) - -/*! @name REG1 - DCDC REGISTER 1 */ -#define DCDC_REG1_POSLIMIT_BUCK_IN_MASK (0x7FU) -#define DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT (0U) -#define DCDC_REG1_POSLIMIT_BUCK_IN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)) & DCDC_REG1_POSLIMIT_BUCK_IN_MASK) -#define DCDC_REG1_POSLIMIT_BOOST_IN_MASK (0x3F80U) -#define DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT (7U) -#define DCDC_REG1_POSLIMIT_BOOST_IN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT)) & DCDC_REG1_POSLIMIT_BOOST_IN_MASK) -#define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK (0x200000U) -#define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT (21U) -#define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK) -#define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK (0x400000U) -#define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT (22U) -#define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK) -#define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK (0x800000U) -#define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT (23U) -#define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK) -#define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK (0x1000000U) -#define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT (24U) -#define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK) - -/*! @name REG2 - DCDC REGISTER 2 */ -#define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK (0x2000U) -#define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT (13U) -#define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK) -#define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U) -#define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT (15U) -#define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK) -#define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U) -#define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT (16U) -#define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK) - -/*! @name REG3 - DCDC REGISTER 3 */ -#define DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK (0x3FU) -#define DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT (0U) -#define DCDC_REG3_DCDC_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT)) & DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK) -#define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_MASK (0x7C0U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_SHIFT (6U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_MASK) -#define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_MASK (0xF800U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_SHIFT (11U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_MASK) -#define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_MASK (0x1E0000U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_SHIFT (17U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_MASK) -#define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_MASK (0x200000U) -#define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_SHIFT (21U) -#define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_MASK) -#define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_MASK (0x400000U) -#define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_SHIFT (22U) -#define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_MASK) -#define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_MASK (0x800000U) -#define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_SHIFT (23U) -#define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_MASK) -#define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U) -#define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT (24U) -#define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK) -#define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK (0x2000000U) -#define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT (25U) -#define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK) -#define DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK (0x4000000U) -#define DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT (26U) -#define DCDC_REG3_DCDC_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK) -#define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK (0x20000000U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_SHIFT (29U) -#define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK) -#define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) -#define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U) -#define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK) - -/*! @name REG4 - DCDC REGISTER 4 */ -#define DCDC_REG4_DCDC_SW_SHUTDOWN_MASK (0x1U) -#define DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT (0U) -#define DCDC_REG4_DCDC_SW_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT)) & DCDC_REG4_DCDC_SW_SHUTDOWN_MASK) -#define DCDC_REG4_UNLOCK_MASK (0xFFFF0000U) -#define DCDC_REG4_UNLOCK_SHIFT (16U) -#define DCDC_REG4_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_UNLOCK_SHIFT)) & DCDC_REG4_UNLOCK_MASK) - -/*! @name REG6 - DCDC REGISTER 6 */ -#define DCDC_REG6_PSWITCH_INT_RISE_EN_MASK (0x1U) -#define DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT (0U) -#define DCDC_REG6_PSWITCH_INT_RISE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT)) & DCDC_REG6_PSWITCH_INT_RISE_EN_MASK) -#define DCDC_REG6_PSWITCH_INT_FALL_EN_MASK (0x2U) -#define DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT (1U) -#define DCDC_REG6_PSWITCH_INT_FALL_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT)) & DCDC_REG6_PSWITCH_INT_FALL_EN_MASK) -#define DCDC_REG6_PSWITCH_INT_CLEAR_MASK (0x4U) -#define DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT (2U) -#define DCDC_REG6_PSWITCH_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT)) & DCDC_REG6_PSWITCH_INT_CLEAR_MASK) -#define DCDC_REG6_PSWITCH_INT_MUTE_MASK (0x8U) -#define DCDC_REG6_PSWITCH_INT_MUTE_SHIFT (3U) -#define DCDC_REG6_PSWITCH_INT_MUTE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_MUTE_SHIFT)) & DCDC_REG6_PSWITCH_INT_MUTE_MASK) -#define DCDC_REG6_PSWITCH_INT_STS_MASK (0x80000000U) -#define DCDC_REG6_PSWITCH_INT_STS_SHIFT (31U) -#define DCDC_REG6_PSWITCH_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_STS_SHIFT)) & DCDC_REG6_PSWITCH_INT_STS_MASK) - -/*! @name REG7 - DCDC REGISTER 7 */ -#define DCDC_REG7_INTEGRATOR_VALUE_MASK (0x7FFFFU) -#define DCDC_REG7_INTEGRATOR_VALUE_SHIFT (0U) -#define DCDC_REG7_INTEGRATOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_INTEGRATOR_VALUE_SHIFT)) & DCDC_REG7_INTEGRATOR_VALUE_MASK) -#define DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK (0x80000U) -#define DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT (19U) -#define DCDC_REG7_INTEGRATOR_VALUE_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT)) & DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK) -#define DCDC_REG7_PULSE_RUN_SPEEDUP_MASK (0x100000U) -#define DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT (20U) -#define DCDC_REG7_PULSE_RUN_SPEEDUP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT)) & DCDC_REG7_PULSE_RUN_SPEEDUP_MASK) - - -/*! - * @} - */ /* end of group DCDC_Register_Masks */ - - -/* DCDC - Peripheral instance base addresses */ -/** Peripheral DCDC base address */ -#define DCDC_BASE (0x4005A000u) -/** Peripheral DCDC base pointer */ -#define DCDC ((DCDC_Type *)DCDC_BASE) -/** Array initializer of DCDC peripheral base addresses */ -#define DCDC_BASE_ADDRS { DCDC_BASE } -/** Array initializer of DCDC peripheral base pointers */ -#define DCDC_BASE_PTRS { DCDC } - -/*! - * @} - */ /* end of group DCDC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ - uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ - __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ - __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ - __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ - __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ - __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ - __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ - __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ - __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ - uint8_t RESERVED_4[4]; - __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ - uint8_t RESERVED_5[12]; - __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ - uint8_t RESERVED_6[184]; - __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ - __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ - __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ - __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ - uint8_t RESERVED_7[3836]; - struct { /* offset: 0x1000, array step: 0x20 */ - __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ - __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ - __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ - union { /* offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ - }; - __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ - __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ - __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ - union { /* offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ - }; - __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ - __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ - union { /* offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ - }; - } TCD[4]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CR - Control Register */ -#define DMA_CR_EDBG_MASK (0x2U) -#define DMA_CR_EDBG_SHIFT (1U) -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) -#define DMA_CR_ERCA_MASK (0x4U) -#define DMA_CR_ERCA_SHIFT (2U) -#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) -#define DMA_CR_HOE_MASK (0x10U) -#define DMA_CR_HOE_SHIFT (4U) -#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) -#define DMA_CR_HALT_MASK (0x20U) -#define DMA_CR_HALT_SHIFT (5U) -#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) -#define DMA_CR_CLM_MASK (0x40U) -#define DMA_CR_CLM_SHIFT (6U) -#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) -#define DMA_CR_EMLM_MASK (0x80U) -#define DMA_CR_EMLM_SHIFT (7U) -#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) -#define DMA_CR_ECX_MASK (0x10000U) -#define DMA_CR_ECX_SHIFT (16U) -#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) -#define DMA_CR_CX_MASK (0x20000U) -#define DMA_CR_CX_SHIFT (17U) -#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) -#define DMA_CR_ACTIVE_MASK (0x80000000U) -#define DMA_CR_ACTIVE_SHIFT (31U) -#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) - -/*! @name ES - Error Status Register */ -#define DMA_ES_DBE_MASK (0x1U) -#define DMA_ES_DBE_SHIFT (0U) -#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) -#define DMA_ES_SBE_MASK (0x2U) -#define DMA_ES_SBE_SHIFT (1U) -#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) -#define DMA_ES_SGE_MASK (0x4U) -#define DMA_ES_SGE_SHIFT (2U) -#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) -#define DMA_ES_NCE_MASK (0x8U) -#define DMA_ES_NCE_SHIFT (3U) -#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) -#define DMA_ES_DOE_MASK (0x10U) -#define DMA_ES_DOE_SHIFT (4U) -#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) -#define DMA_ES_DAE_MASK (0x20U) -#define DMA_ES_DAE_SHIFT (5U) -#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) -#define DMA_ES_SOE_MASK (0x40U) -#define DMA_ES_SOE_SHIFT (6U) -#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) -#define DMA_ES_SAE_MASK (0x80U) -#define DMA_ES_SAE_SHIFT (7U) -#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) -#define DMA_ES_ERRCHN_MASK (0x300U) -#define DMA_ES_ERRCHN_SHIFT (8U) -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK (0x4000U) -#define DMA_ES_CPE_SHIFT (14U) -#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) -#define DMA_ES_ECX_MASK (0x10000U) -#define DMA_ES_ECX_SHIFT (16U) -#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) -#define DMA_ES_VLD_MASK (0x80000000U) -#define DMA_ES_VLD_SHIFT (31U) -#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) - -/*! @name ERQ - Enable Request Register */ -#define DMA_ERQ_ERQ0_MASK (0x1U) -#define DMA_ERQ_ERQ0_SHIFT (0U) -#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) -#define DMA_ERQ_ERQ1_MASK (0x2U) -#define DMA_ERQ_ERQ1_SHIFT (1U) -#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) -#define DMA_ERQ_ERQ2_MASK (0x4U) -#define DMA_ERQ_ERQ2_SHIFT (2U) -#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) -#define DMA_ERQ_ERQ3_MASK (0x8U) -#define DMA_ERQ_ERQ3_SHIFT (3U) -#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) - -/*! @name EEI - Enable Error Interrupt Register */ -#define DMA_EEI_EEI0_MASK (0x1U) -#define DMA_EEI_EEI0_SHIFT (0U) -#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) -#define DMA_EEI_EEI1_MASK (0x2U) -#define DMA_EEI_EEI1_SHIFT (1U) -#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) -#define DMA_EEI_EEI2_MASK (0x4U) -#define DMA_EEI_EEI2_SHIFT (2U) -#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) -#define DMA_EEI_EEI3_MASK (0x8U) -#define DMA_EEI_EEI3_SHIFT (3U) -#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) - -/*! @name CEEI - Clear Enable Error Interrupt Register */ -#define DMA_CEEI_CEEI_MASK (0x3U) -#define DMA_CEEI_CEEI_SHIFT (0U) -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK (0x40U) -#define DMA_CEEI_CAEE_SHIFT (6U) -#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) -#define DMA_CEEI_NOP_MASK (0x80U) -#define DMA_CEEI_NOP_SHIFT (7U) -#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) - -/*! @name SEEI - Set Enable Error Interrupt Register */ -#define DMA_SEEI_SEEI_MASK (0x3U) -#define DMA_SEEI_SEEI_SHIFT (0U) -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK (0x40U) -#define DMA_SEEI_SAEE_SHIFT (6U) -#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) -#define DMA_SEEI_NOP_MASK (0x80U) -#define DMA_SEEI_NOP_SHIFT (7U) -#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) - -/*! @name CERQ - Clear Enable Request Register */ -#define DMA_CERQ_CERQ_MASK (0x3U) -#define DMA_CERQ_CERQ_SHIFT (0U) -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK (0x40U) -#define DMA_CERQ_CAER_SHIFT (6U) -#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) -#define DMA_CERQ_NOP_MASK (0x80U) -#define DMA_CERQ_NOP_SHIFT (7U) -#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) - -/*! @name SERQ - Set Enable Request Register */ -#define DMA_SERQ_SERQ_MASK (0x3U) -#define DMA_SERQ_SERQ_SHIFT (0U) -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK (0x40U) -#define DMA_SERQ_SAER_SHIFT (6U) -#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) -#define DMA_SERQ_NOP_MASK (0x80U) -#define DMA_SERQ_NOP_SHIFT (7U) -#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) - -/*! @name CDNE - Clear DONE Status Bit Register */ -#define DMA_CDNE_CDNE_MASK (0x3U) -#define DMA_CDNE_CDNE_SHIFT (0U) -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK (0x40U) -#define DMA_CDNE_CADN_SHIFT (6U) -#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) -#define DMA_CDNE_NOP_MASK (0x80U) -#define DMA_CDNE_NOP_SHIFT (7U) -#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) - -/*! @name SSRT - Set START Bit Register */ -#define DMA_SSRT_SSRT_MASK (0x3U) -#define DMA_SSRT_SSRT_SHIFT (0U) -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK (0x40U) -#define DMA_SSRT_SAST_SHIFT (6U) -#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) -#define DMA_SSRT_NOP_MASK (0x80U) -#define DMA_SSRT_NOP_SHIFT (7U) -#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) - -/*! @name CERR - Clear Error Register */ -#define DMA_CERR_CERR_MASK (0x3U) -#define DMA_CERR_CERR_SHIFT (0U) -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK (0x40U) -#define DMA_CERR_CAEI_SHIFT (6U) -#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) -#define DMA_CERR_NOP_MASK (0x80U) -#define DMA_CERR_NOP_SHIFT (7U) -#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) - -/*! @name CINT - Clear Interrupt Request Register */ -#define DMA_CINT_CINT_MASK (0x3U) -#define DMA_CINT_CINT_SHIFT (0U) -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK (0x40U) -#define DMA_CINT_CAIR_SHIFT (6U) -#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) -#define DMA_CINT_NOP_MASK (0x80U) -#define DMA_CINT_NOP_SHIFT (7U) -#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) - -/*! @name INT - Interrupt Request Register */ -#define DMA_INT_INT0_MASK (0x1U) -#define DMA_INT_INT0_SHIFT (0U) -#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) -#define DMA_INT_INT1_MASK (0x2U) -#define DMA_INT_INT1_SHIFT (1U) -#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) -#define DMA_INT_INT2_MASK (0x4U) -#define DMA_INT_INT2_SHIFT (2U) -#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) -#define DMA_INT_INT3_MASK (0x8U) -#define DMA_INT_INT3_SHIFT (3U) -#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) - -/*! @name ERR - Error Register */ -#define DMA_ERR_ERR0_MASK (0x1U) -#define DMA_ERR_ERR0_SHIFT (0U) -#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) -#define DMA_ERR_ERR1_MASK (0x2U) -#define DMA_ERR_ERR1_SHIFT (1U) -#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) -#define DMA_ERR_ERR2_MASK (0x4U) -#define DMA_ERR_ERR2_SHIFT (2U) -#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) -#define DMA_ERR_ERR3_MASK (0x8U) -#define DMA_ERR_ERR3_SHIFT (3U) -#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) - -/*! @name HRS - Hardware Request Status Register */ -#define DMA_HRS_HRS0_MASK (0x1U) -#define DMA_HRS_HRS0_SHIFT (0U) -#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) -#define DMA_HRS_HRS1_MASK (0x2U) -#define DMA_HRS_HRS1_SHIFT (1U) -#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) -#define DMA_HRS_HRS2_MASK (0x4U) -#define DMA_HRS_HRS2_SHIFT (2U) -#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) -#define DMA_HRS_HRS3_MASK (0x8U) -#define DMA_HRS_HRS3_SHIFT (3U) -#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) - -/*! @name EARS - Enable Asynchronous Request in Stop Register */ -#define DMA_EARS_EDREQ_0_MASK (0x1U) -#define DMA_EARS_EDREQ_0_SHIFT (0U) -#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) -#define DMA_EARS_EDREQ_1_MASK (0x2U) -#define DMA_EARS_EDREQ_1_SHIFT (1U) -#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) -#define DMA_EARS_EDREQ_2_MASK (0x4U) -#define DMA_EARS_EDREQ_2_SHIFT (2U) -#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) -#define DMA_EARS_EDREQ_3_MASK (0x8U) -#define DMA_EARS_EDREQ_3_SHIFT (3U) -#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) - -/*! @name DCHPRI3 - Channel n Priority Register */ -#define DMA_DCHPRI3_CHPRI_MASK (0x3U) -#define DMA_DCHPRI3_CHPRI_SHIFT (0U) -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK (0x40U) -#define DMA_DCHPRI3_DPA_SHIFT (6U) -#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) -#define DMA_DCHPRI3_ECP_MASK (0x80U) -#define DMA_DCHPRI3_ECP_SHIFT (7U) -#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) - -/*! @name DCHPRI2 - Channel n Priority Register */ -#define DMA_DCHPRI2_CHPRI_MASK (0x3U) -#define DMA_DCHPRI2_CHPRI_SHIFT (0U) -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK (0x40U) -#define DMA_DCHPRI2_DPA_SHIFT (6U) -#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) -#define DMA_DCHPRI2_ECP_MASK (0x80U) -#define DMA_DCHPRI2_ECP_SHIFT (7U) -#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) - -/*! @name DCHPRI1 - Channel n Priority Register */ -#define DMA_DCHPRI1_CHPRI_MASK (0x3U) -#define DMA_DCHPRI1_CHPRI_SHIFT (0U) -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK (0x40U) -#define DMA_DCHPRI1_DPA_SHIFT (6U) -#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) -#define DMA_DCHPRI1_ECP_MASK (0x80U) -#define DMA_DCHPRI1_ECP_SHIFT (7U) -#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) - -/*! @name DCHPRI0 - Channel n Priority Register */ -#define DMA_DCHPRI0_CHPRI_MASK (0x3U) -#define DMA_DCHPRI0_CHPRI_SHIFT (0U) -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK (0x40U) -#define DMA_DCHPRI0_DPA_SHIFT (6U) -#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) -#define DMA_DCHPRI0_ECP_MASK (0x80U) -#define DMA_DCHPRI0_ECP_SHIFT (7U) -#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) - -/*! @name SADDR - TCD Source Address */ -#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) -#define DMA_SADDR_SADDR_SHIFT (0U) -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) - -/* The count of DMA_SADDR */ -#define DMA_SADDR_COUNT (4U) - -/*! @name SOFF - TCD Signed Source Address Offset */ -#define DMA_SOFF_SOFF_MASK (0xFFFFU) -#define DMA_SOFF_SOFF_SHIFT (0U) -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) - -/* The count of DMA_SOFF */ -#define DMA_SOFF_COUNT (4U) - -/*! @name ATTR - TCD Transfer Attributes */ -#define DMA_ATTR_DSIZE_MASK (0x7U) -#define DMA_ATTR_DSIZE_SHIFT (0U) -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK (0xF8U) -#define DMA_ATTR_DMOD_SHIFT (3U) -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK (0x700U) -#define DMA_ATTR_SSIZE_SHIFT (8U) -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK (0xF800U) -#define DMA_ATTR_SMOD_SHIFT (11U) -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) - -/* The count of DMA_ATTR */ -#define DMA_ATTR_COUNT (4U) - -/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ -#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) -#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) - -/* The count of DMA_NBYTES_MLNO */ -#define DMA_NBYTES_MLNO_COUNT (4U) - -/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) -#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) -#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) - -/* The count of DMA_NBYTES_MLOFFNO */ -#define DMA_NBYTES_MLOFFNO_COUNT (4U) - -/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) -#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) -#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) - -/* The count of DMA_NBYTES_MLOFFYES */ -#define DMA_NBYTES_MLOFFYES_COUNT (4U) - -/*! @name SLAST - TCD Last Source Address Adjustment */ -#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) -#define DMA_SLAST_SLAST_SHIFT (0U) -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) - -/* The count of DMA_SLAST */ -#define DMA_SLAST_COUNT (4U) - -/*! @name DADDR - TCD Destination Address */ -#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) -#define DMA_DADDR_DADDR_SHIFT (0U) -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) - -/* The count of DMA_DADDR */ -#define DMA_DADDR_COUNT (4U) - -/*! @name DOFF - TCD Signed Destination Address Offset */ -#define DMA_DOFF_DOFF_MASK (0xFFFFU) -#define DMA_DOFF_DOFF_SHIFT (0U) -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) - -/* The count of DMA_DOFF */ -#define DMA_DOFF_COUNT (4U) - -/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) -#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) - -/* The count of DMA_CITER_ELINKNO */ -#define DMA_CITER_ELINKNO_COUNT (4U) - -/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) -#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK (0x600U) -#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) - -/* The count of DMA_CITER_ELINKYES */ -#define DMA_CITER_ELINKYES_COUNT (4U) - -/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) -#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) - -/* The count of DMA_DLAST_SGA */ -#define DMA_DLAST_SGA_COUNT (4U) - -/*! @name CSR - TCD Control and Status */ -#define DMA_CSR_START_MASK (0x1U) -#define DMA_CSR_START_SHIFT (0U) -#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) -#define DMA_CSR_INTMAJOR_MASK (0x2U) -#define DMA_CSR_INTMAJOR_SHIFT (1U) -#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) -#define DMA_CSR_INTHALF_MASK (0x4U) -#define DMA_CSR_INTHALF_SHIFT (2U) -#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) -#define DMA_CSR_DREQ_MASK (0x8U) -#define DMA_CSR_DREQ_SHIFT (3U) -#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) -#define DMA_CSR_ESG_MASK (0x10U) -#define DMA_CSR_ESG_SHIFT (4U) -#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) -#define DMA_CSR_MAJORELINK_MASK (0x20U) -#define DMA_CSR_MAJORELINK_SHIFT (5U) -#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) -#define DMA_CSR_ACTIVE_MASK (0x40U) -#define DMA_CSR_ACTIVE_SHIFT (6U) -#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) -#define DMA_CSR_DONE_MASK (0x80U) -#define DMA_CSR_DONE_SHIFT (7U) -#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) -#define DMA_CSR_MAJORLINKCH_MASK (0x300U) -#define DMA_CSR_MAJORLINKCH_SHIFT (8U) -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK (0xC000U) -#define DMA_CSR_BWC_SHIFT (14U) -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) - -/* The count of DMA_CSR */ -#define DMA_CSR_COUNT (4U) - -/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) -#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) - -/* The count of DMA_BITER_ELINKNO */ -#define DMA_BITER_ELINKNO_COUNT (4U) - -/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) -#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK (0x600U) -#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) - -/* The count of DMA_BITER_ELINKYES */ -#define DMA_BITER_ELINKYES_COUNT (4U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA base address */ -#define DMA_BASE (0x40008000u) -/** Peripheral DMA base pointer */ -#define DMA0 ((DMA_Type *)DMA_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer - * @{ - */ - -/** DMAMUX - Register Layout Typedef */ -typedef struct { - __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ -} DMAMUX_Type; - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/*! @name CHCFG - Channel Configuration register */ -#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) -#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) -#define DMAMUX_CHCFG_TRIG_MASK (0x40U) -#define DMAMUX_CHCFG_TRIG_SHIFT (6U) -#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) -#define DMAMUX_CHCFG_ENBL_MASK (0x80U) -#define DMAMUX_CHCFG_ENBL_SHIFT (7U) -#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) - -/* The count of DMAMUX_CHCFG */ -#define DMAMUX_CHCFG_COUNT (4U) - - -/*! - * @} - */ /* end of group DMAMUX_Register_Masks */ - - -/* DMAMUX - Peripheral instance base addresses */ -/** Peripheral DMAMUX0 base address */ -#define DMAMUX0_BASE (0x40021000u) -/** Peripheral DMAMUX0 base pointer */ -#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) -/** Array initializer of DMAMUX peripheral base addresses */ -#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } -/** Array initializer of DMAMUX peripheral base pointers */ -#define DMAMUX_BASE_PTRS { DMAMUX0 } - -/*! - * @} - */ /* end of group DMAMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FGPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer - * @{ - */ - -/** FGPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ -} FGPIO_Type; - -/* ---------------------------------------------------------------------------- - -- FGPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FGPIO_Register_Masks FGPIO Register Masks - * @{ - */ - -/*! @name PDOR - Port Data Output Register */ -#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) -#define FGPIO_PDOR_PDO_SHIFT (0U) -#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) - -/*! @name PSOR - Port Set Output Register */ -#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) -#define FGPIO_PSOR_PTSO_SHIFT (0U) -#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) - -/*! @name PCOR - Port Clear Output Register */ -#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) -#define FGPIO_PCOR_PTCO_SHIFT (0U) -#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) - -/*! @name PTOR - Port Toggle Output Register */ -#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) -#define FGPIO_PTOR_PTTO_SHIFT (0U) -#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) - -/*! @name PDIR - Port Data Input Register */ -#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) -#define FGPIO_PDIR_PDI_SHIFT (0U) -#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) - -/*! @name PDDR - Port Data Direction Register */ -#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) -#define FGPIO_PDDR_PDD_SHIFT (0U) -#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) - - -/*! - * @} - */ /* end of group FGPIO_Register_Masks */ - - -/* FGPIO - Peripheral instance base addresses */ -/** Peripheral FGPIOA base address */ -#define FGPIOA_BASE (0xF8000000u) -/** Peripheral FGPIOA base pointer */ -#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) -/** Peripheral FGPIOB base address */ -#define FGPIOB_BASE (0xF8000040u) -/** Peripheral FGPIOB base pointer */ -#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) -/** Peripheral FGPIOC base address */ -#define FGPIOC_BASE (0xF8000080u) -/** Peripheral FGPIOC base pointer */ -#define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) -/** Array initializer of FGPIO peripheral base addresses */ -#define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE } -/** Array initializer of FGPIO peripheral base pointers */ -#define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC } - -/*! - * @} - */ /* end of group FGPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FTFA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer - * @{ - */ - -/** FTFA - Register Layout Typedef */ -typedef struct { - __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ - __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ - __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ - __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ - __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ - __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ - __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ - __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ - __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ - __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ - __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ - __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ - __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ - __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ - __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ - __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ - __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ - __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ - __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ - __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ - uint8_t RESERVED_0[4]; - __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */ - __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */ - __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */ - __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */ - __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */ - __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */ - __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */ - __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */ - __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */ - __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */ - __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */ - __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */ - __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */ - __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */ - __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */ - __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */ - __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */ - uint8_t RESERVED_1[2]; - __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */ -} FTFA_Type; - -/* ---------------------------------------------------------------------------- - -- FTFA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFA_Register_Masks FTFA Register Masks - * @{ - */ - -/*! @name FSTAT - Flash Status Register */ -#define FTFA_FSTAT_MGSTAT0_MASK (0x1U) -#define FTFA_FSTAT_MGSTAT0_SHIFT (0U) -#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) -#define FTFA_FSTAT_FPVIOL_MASK (0x10U) -#define FTFA_FSTAT_FPVIOL_SHIFT (4U) -#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) -#define FTFA_FSTAT_ACCERR_MASK (0x20U) -#define FTFA_FSTAT_ACCERR_SHIFT (5U) -#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) -#define FTFA_FSTAT_RDCOLERR_MASK (0x40U) -#define FTFA_FSTAT_RDCOLERR_SHIFT (6U) -#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) -#define FTFA_FSTAT_CCIF_MASK (0x80U) -#define FTFA_FSTAT_CCIF_SHIFT (7U) -#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) - -/*! @name FCNFG - Flash Configuration Register */ -#define FTFA_FCNFG_ERSSUSP_MASK (0x10U) -#define FTFA_FCNFG_ERSSUSP_SHIFT (4U) -#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) -#define FTFA_FCNFG_ERSAREQ_MASK (0x20U) -#define FTFA_FCNFG_ERSAREQ_SHIFT (5U) -#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) -#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) -#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) -#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) -#define FTFA_FCNFG_CCIE_MASK (0x80U) -#define FTFA_FCNFG_CCIE_SHIFT (7U) -#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) - -/*! @name FSEC - Flash Security Register */ -#define FTFA_FSEC_SEC_MASK (0x3U) -#define FTFA_FSEC_SEC_SHIFT (0U) -#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) -#define FTFA_FSEC_FSLACC_MASK (0xCU) -#define FTFA_FSEC_FSLACC_SHIFT (2U) -#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) -#define FTFA_FSEC_MEEN_MASK (0x30U) -#define FTFA_FSEC_MEEN_SHIFT (4U) -#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) -#define FTFA_FSEC_KEYEN_MASK (0xC0U) -#define FTFA_FSEC_KEYEN_SHIFT (6U) -#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) - -/*! @name FOPT - Flash Option Register */ -#define FTFA_FOPT_OPT_MASK (0xFFU) -#define FTFA_FOPT_OPT_SHIFT (0U) -#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) - -/*! @name FCCOB3 - Flash Common Command Object Registers */ -#define FTFA_FCCOB3_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB3_CCOBn_SHIFT (0U) -#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) - -/*! @name FCCOB2 - Flash Common Command Object Registers */ -#define FTFA_FCCOB2_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB2_CCOBn_SHIFT (0U) -#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) - -/*! @name FCCOB1 - Flash Common Command Object Registers */ -#define FTFA_FCCOB1_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB1_CCOBn_SHIFT (0U) -#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) - -/*! @name FCCOB0 - Flash Common Command Object Registers */ -#define FTFA_FCCOB0_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB0_CCOBn_SHIFT (0U) -#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) - -/*! @name FCCOB7 - Flash Common Command Object Registers */ -#define FTFA_FCCOB7_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB7_CCOBn_SHIFT (0U) -#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) - -/*! @name FCCOB6 - Flash Common Command Object Registers */ -#define FTFA_FCCOB6_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB6_CCOBn_SHIFT (0U) -#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) - -/*! @name FCCOB5 - Flash Common Command Object Registers */ -#define FTFA_FCCOB5_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB5_CCOBn_SHIFT (0U) -#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) - -/*! @name FCCOB4 - Flash Common Command Object Registers */ -#define FTFA_FCCOB4_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB4_CCOBn_SHIFT (0U) -#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) - -/*! @name FCCOBB - Flash Common Command Object Registers */ -#define FTFA_FCCOBB_CCOBn_MASK (0xFFU) -#define FTFA_FCCOBB_CCOBn_SHIFT (0U) -#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) - -/*! @name FCCOBA - Flash Common Command Object Registers */ -#define FTFA_FCCOBA_CCOBn_MASK (0xFFU) -#define FTFA_FCCOBA_CCOBn_SHIFT (0U) -#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) - -/*! @name FCCOB9 - Flash Common Command Object Registers */ -#define FTFA_FCCOB9_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB9_CCOBn_SHIFT (0U) -#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) - -/*! @name FCCOB8 - Flash Common Command Object Registers */ -#define FTFA_FCCOB8_CCOBn_MASK (0xFFU) -#define FTFA_FCCOB8_CCOBn_SHIFT (0U) -#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) - -/*! @name FPROT3 - Program Flash Protection Registers */ -#define FTFA_FPROT3_PROT_MASK (0xFFU) -#define FTFA_FPROT3_PROT_SHIFT (0U) -#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) - -/*! @name FPROT2 - Program Flash Protection Registers */ -#define FTFA_FPROT2_PROT_MASK (0xFFU) -#define FTFA_FPROT2_PROT_SHIFT (0U) -#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) - -/*! @name FPROT1 - Program Flash Protection Registers */ -#define FTFA_FPROT1_PROT_MASK (0xFFU) -#define FTFA_FPROT1_PROT_SHIFT (0U) -#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) - -/*! @name FPROT0 - Program Flash Protection Registers */ -#define FTFA_FPROT0_PROT_MASK (0xFFU) -#define FTFA_FPROT0_PROT_SHIFT (0U) -#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) - -/*! @name XACCH3 - Execute-only Access Registers */ -#define FTFA_XACCH3_XA_MASK (0xFFU) -#define FTFA_XACCH3_XA_SHIFT (0U) -#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK) - -/*! @name XACCH2 - Execute-only Access Registers */ -#define FTFA_XACCH2_XA_MASK (0xFFU) -#define FTFA_XACCH2_XA_SHIFT (0U) -#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK) - -/*! @name XACCH1 - Execute-only Access Registers */ -#define FTFA_XACCH1_XA_MASK (0xFFU) -#define FTFA_XACCH1_XA_SHIFT (0U) -#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK) - -/*! @name XACCH0 - Execute-only Access Registers */ -#define FTFA_XACCH0_XA_MASK (0xFFU) -#define FTFA_XACCH0_XA_SHIFT (0U) -#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK) - -/*! @name XACCL3 - Execute-only Access Registers */ -#define FTFA_XACCL3_XA_MASK (0xFFU) -#define FTFA_XACCL3_XA_SHIFT (0U) -#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK) - -/*! @name XACCL2 - Execute-only Access Registers */ -#define FTFA_XACCL2_XA_MASK (0xFFU) -#define FTFA_XACCL2_XA_SHIFT (0U) -#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK) - -/*! @name XACCL1 - Execute-only Access Registers */ -#define FTFA_XACCL1_XA_MASK (0xFFU) -#define FTFA_XACCL1_XA_SHIFT (0U) -#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK) - -/*! @name XACCL0 - Execute-only Access Registers */ -#define FTFA_XACCL0_XA_MASK (0xFFU) -#define FTFA_XACCL0_XA_SHIFT (0U) -#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK) - -/*! @name SACCH3 - Supervisor-only Access Registers */ -#define FTFA_SACCH3_SA_MASK (0xFFU) -#define FTFA_SACCH3_SA_SHIFT (0U) -#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK) - -/*! @name SACCH2 - Supervisor-only Access Registers */ -#define FTFA_SACCH2_SA_MASK (0xFFU) -#define FTFA_SACCH2_SA_SHIFT (0U) -#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK) - -/*! @name SACCH1 - Supervisor-only Access Registers */ -#define FTFA_SACCH1_SA_MASK (0xFFU) -#define FTFA_SACCH1_SA_SHIFT (0U) -#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK) - -/*! @name SACCH0 - Supervisor-only Access Registers */ -#define FTFA_SACCH0_SA_MASK (0xFFU) -#define FTFA_SACCH0_SA_SHIFT (0U) -#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK) - -/*! @name SACCL3 - Supervisor-only Access Registers */ -#define FTFA_SACCL3_SA_MASK (0xFFU) -#define FTFA_SACCL3_SA_SHIFT (0U) -#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK) - -/*! @name SACCL2 - Supervisor-only Access Registers */ -#define FTFA_SACCL2_SA_MASK (0xFFU) -#define FTFA_SACCL2_SA_SHIFT (0U) -#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK) - -/*! @name SACCL1 - Supervisor-only Access Registers */ -#define FTFA_SACCL1_SA_MASK (0xFFU) -#define FTFA_SACCL1_SA_SHIFT (0U) -#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK) - -/*! @name SACCL0 - Supervisor-only Access Registers */ -#define FTFA_SACCL0_SA_MASK (0xFFU) -#define FTFA_SACCL0_SA_SHIFT (0U) -#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK) - -/*! @name FACSS - Flash Access Segment Size Register */ -#define FTFA_FACSS_SGSIZE_MASK (0xFFU) -#define FTFA_FACSS_SGSIZE_SHIFT (0U) -#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK) - -/*! @name FACSN - Flash Access Segment Number Register */ -#define FTFA_FACSN_NUMSG_MASK (0xFFU) -#define FTFA_FACSN_NUMSG_SHIFT (0U) -#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK) - - -/*! - * @} - */ /* end of group FTFA_Register_Masks */ - - -/* FTFA - Peripheral instance base addresses */ -/** Peripheral FTFA base address */ -#define FTFA_BASE (0x40020000u) -/** Peripheral FTFA base pointer */ -#define FTFA ((FTFA_Type *)FTFA_BASE) -/** Array initializer of FTFA peripheral base addresses */ -#define FTFA_BASE_ADDRS { FTFA_BASE } -/** Array initializer of FTFA peripheral base pointers */ -#define FTFA_BASE_PTRS { FTFA } -/** Interrupt vectors for the FTFA peripheral type */ -#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } - -/*! - * @} - */ /* end of group FTFA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GENFSK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GENFSK_Peripheral_Access_Layer GENFSK Peripheral Access Layer - * @{ - */ - -/** GENFSK - Register Layout Typedef */ -typedef struct { - __IO uint32_t IRQ_CTRL; /**< IRQ CONTROL, offset: 0x0 */ - __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x4 */ - __IO uint32_t T1_CMP; /**< T1 COMPARE, offset: 0x8 */ - __IO uint32_t T2_CMP; /**< T2 COMPARE, offset: 0xC */ - __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0x10 */ - __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x14 */ - __I uint32_t XCVR_STS; /**< TRANSCEIVER STATUS, offset: 0x18 */ - __IO uint32_t XCVR_CFG; /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */ - __IO uint32_t CHANNEL_NUM; /**< CHANNEL NUMBER, offset: 0x20 */ - __IO uint32_t TX_POWER; /**< TRANSMIT POWER, offset: 0x24 */ - __IO uint32_t NTW_ADR_CTRL; /**< NETWORK ADDRESS CONTROL, offset: 0x28 */ - __IO uint32_t NTW_ADR_0; /**< NETWORK ADDRESS 0, offset: 0x2C */ - __IO uint32_t NTW_ADR_1; /**< NETWORK ADDRESS 1, offset: 0x30 */ - __IO uint32_t NTW_ADR_2; /**< NETWORK ADDRESS 2, offset: 0x34 */ - __IO uint32_t NTW_ADR_3; /**< NETWORK ADDRESS 3, offset: 0x38 */ - __IO uint32_t RX_WATERMARK; /**< RECEIVE WATERMARK, offset: 0x3C */ - __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x40 */ - __I uint32_t PART_ID; /**< PART ID, offset: 0x44 */ - uint8_t RESERVED_0[24]; - __IO uint32_t PACKET_CFG; /**< PACKET CONFIGURATION, offset: 0x60 */ - __IO uint32_t H0_CFG; /**< H0 CONFIGURATION, offset: 0x64 */ - __IO uint32_t H1_CFG; /**< H1 CONFIGURATION, offset: 0x68 */ - __IO uint32_t CRC_CFG; /**< CRC CONFIGURATION, offset: 0x6C */ - __IO uint32_t CRC_INIT; /**< CRC INITIALIZATION, offset: 0x70 */ - __IO uint32_t CRC_POLY; /**< CRC POLYNOMIAL, offset: 0x74 */ - __IO uint32_t CRC_XOR_OUT; /**< CRC XOR OUT, offset: 0x78 */ - __IO uint32_t WHITEN_CFG; /**< WHITENER CONFIGURATION, offset: 0x7C */ - __IO uint32_t WHITEN_POLY; /**< WHITENER POLYNOMIAL, offset: 0x80 */ - __IO uint32_t WHITEN_SZ_THR; /**< WHITENER SIZE THRESHOLD, offset: 0x84 */ - __IO uint32_t BITRATE; /**< BIT RATE, offset: 0x88 */ - __IO uint32_t PB_PARTITION; /**< PACKET BUFFER PARTITION POINT, offset: 0x8C */ -} GENFSK_Type; - -/* ---------------------------------------------------------------------------- - -- GENFSK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GENFSK_Register_Masks GENFSK Register Masks - * @{ - */ - -/*! @name IRQ_CTRL - IRQ CONTROL */ -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK (0x1U) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT (0U) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK) -#define GENFSK_IRQ_CTRL_TX_IRQ_MASK (0x2U) -#define GENFSK_IRQ_CTRL_TX_IRQ_SHIFT (1U) -#define GENFSK_IRQ_CTRL_TX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_MASK) -#define GENFSK_IRQ_CTRL_RX_IRQ_MASK (0x4U) -#define GENFSK_IRQ_CTRL_RX_IRQ_SHIFT (2U) -#define GENFSK_IRQ_CTRL_RX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_MASK) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK (0x8U) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT (3U) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK) -#define GENFSK_IRQ_CTRL_T1_IRQ_MASK (0x10U) -#define GENFSK_IRQ_CTRL_T1_IRQ_SHIFT (4U) -#define GENFSK_IRQ_CTRL_T1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_MASK) -#define GENFSK_IRQ_CTRL_T2_IRQ_MASK (0x20U) -#define GENFSK_IRQ_CTRL_T2_IRQ_SHIFT (5U) -#define GENFSK_IRQ_CTRL_T2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_MASK) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK (0x40U) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT (6U) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_MASK (0x80U) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT (7U) -#define GENFSK_IRQ_CTRL_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_MASK) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK (0x100U) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT (8U) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK) -#define GENFSK_IRQ_CTRL_TSM_IRQ_MASK (0x200U) -#define GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT (9U) -#define GENFSK_IRQ_CTRL_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_MASK) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK (0x10000U) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT (16U) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK (0x20000U) -#define GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT (17U) -#define GENFSK_IRQ_CTRL_TX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK (0x40000U) -#define GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT (18U) -#define GENFSK_IRQ_CTRL_RX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK (0x80000U) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT (19U) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK (0x100000U) -#define GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT (20U) -#define GENFSK_IRQ_CTRL_T1_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U) -#define GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT (21U) -#define GENFSK_IRQ_CTRL_T2_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK (0x400000U) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT (22U) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK (0x800000U) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT (23U) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK (0x2000000U) -#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT (25U) -#define GENFSK_IRQ_CTRL_TSM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK (0x4000000U) -#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT (26U) -#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_CRC_IGNORE_MASK (0x8000000U) -#define GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT (27U) -#define GENFSK_IRQ_CTRL_CRC_IGNORE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT)) & GENFSK_IRQ_CTRL_CRC_IGNORE_MASK) -#define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x80000000U) -#define GENFSK_IRQ_CTRL_CRC_VALID_SHIFT (31U) -#define GENFSK_IRQ_CTRL_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK) - -/*! @name EVENT_TMR - EVENT TIMER */ -#define GENFSK_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFFU) -#define GENFSK_EVENT_TMR_EVENT_TMR_SHIFT (0U) -#define GENFSK_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_MASK) -#define GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK (0x1000000U) -#define GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT (24U) -#define GENFSK_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK) -#define GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2000000U) -#define GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT (25U) -#define GENFSK_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK) - -/*! @name T1_CMP - T1 COMPARE */ -#define GENFSK_T1_CMP_T1_CMP_MASK (0xFFFFFFU) -#define GENFSK_T1_CMP_T1_CMP_SHIFT (0U) -#define GENFSK_T1_CMP_T1_CMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK) -#define GENFSK_T1_CMP_T1_CMP_EN_MASK (0x1000000U) -#define GENFSK_T1_CMP_T1_CMP_EN_SHIFT (24U) -#define GENFSK_T1_CMP_T1_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_EN_SHIFT)) & GENFSK_T1_CMP_T1_CMP_EN_MASK) - -/*! @name T2_CMP - T2 COMPARE */ -#define GENFSK_T2_CMP_T2_CMP_MASK (0xFFFFFFU) -#define GENFSK_T2_CMP_T2_CMP_SHIFT (0U) -#define GENFSK_T2_CMP_T2_CMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_SHIFT)) & GENFSK_T2_CMP_T2_CMP_MASK) -#define GENFSK_T2_CMP_T2_CMP_EN_MASK (0x1000000U) -#define GENFSK_T2_CMP_T2_CMP_EN_SHIFT (24U) -#define GENFSK_T2_CMP_T2_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_EN_SHIFT)) & GENFSK_T2_CMP_T2_CMP_EN_MASK) - -/*! @name TIMESTAMP - TIMESTAMP */ -#define GENFSK_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU) -#define GENFSK_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define GENFSK_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_TIMESTAMP_SHIFT)) & GENFSK_TIMESTAMP_TIMESTAMP_MASK) - -/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */ -#define GENFSK_XCVR_CTRL_SEQCMD_MASK (0xFU) -#define GENFSK_XCVR_CTRL_SEQCMD_SHIFT (0U) -#define GENFSK_XCVR_CTRL_SEQCMD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_SEQCMD_SHIFT)) & GENFSK_XCVR_CTRL_SEQCMD_MASK) -#define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U) -#define GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT (24U) -#define GENFSK_XCVR_CTRL_CMDDEC_CS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK) -#define GENFSK_XCVR_CTRL_XCVR_BUSY_MASK (0x80000000U) -#define GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT (31U) -#define GENFSK_XCVR_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT)) & GENFSK_XCVR_CTRL_XCVR_BUSY_MASK) - -/*! @name XCVR_STS - TRANSCEIVER STATUS */ -#define GENFSK_XCVR_STS_TX_START_T1_PEND_MASK (0x1U) -#define GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT (0U) -#define GENFSK_XCVR_STS_TX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T1_PEND_MASK) -#define GENFSK_XCVR_STS_TX_START_T2_PEND_MASK (0x2U) -#define GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT (1U) -#define GENFSK_XCVR_STS_TX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T2_PEND_MASK) -#define GENFSK_XCVR_STS_TX_IN_WARMUP_MASK (0x4U) -#define GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT (2U) -#define GENFSK_XCVR_STS_TX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMUP_MASK) -#define GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK (0x8U) -#define GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT (3U) -#define GENFSK_XCVR_STS_TX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK) -#define GENFSK_XCVR_STS_TX_IN_WARMDN_MASK (0x10U) -#define GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT (4U) -#define GENFSK_XCVR_STS_TX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMDN_MASK) -#define GENFSK_XCVR_STS_RX_START_T1_PEND_MASK (0x20U) -#define GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT (5U) -#define GENFSK_XCVR_STS_RX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T1_PEND_MASK) -#define GENFSK_XCVR_STS_RX_START_T2_PEND_MASK (0x40U) -#define GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT (6U) -#define GENFSK_XCVR_STS_RX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T2_PEND_MASK) -#define GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK (0x80U) -#define GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT (7U) -#define GENFSK_XCVR_STS_RX_STOP_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK) -#define GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK (0x100U) -#define GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT (8U) -#define GENFSK_XCVR_STS_RX_STOP_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK) -#define GENFSK_XCVR_STS_RX_IN_WARMUP_MASK (0x200U) -#define GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT (9U) -#define GENFSK_XCVR_STS_RX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMUP_MASK) -#define GENFSK_XCVR_STS_RX_IN_SEARCH_MASK (0x400U) -#define GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT (10U) -#define GENFSK_XCVR_STS_RX_IN_SEARCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT)) & GENFSK_XCVR_STS_RX_IN_SEARCH_MASK) -#define GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK (0x800U) -#define GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT (11U) -#define GENFSK_XCVR_STS_RX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK) -#define GENFSK_XCVR_STS_RX_IN_WARMDN_MASK (0x1000U) -#define GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT (12U) -#define GENFSK_XCVR_STS_RX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMDN_MASK) -#define GENFSK_XCVR_STS_LQI_VALID_MASK (0x4000U) -#define GENFSK_XCVR_STS_LQI_VALID_SHIFT (14U) -#define GENFSK_XCVR_STS_LQI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_VALID_SHIFT)) & GENFSK_XCVR_STS_LQI_VALID_MASK) -#define GENFSK_XCVR_STS_CRC_VALID_MASK (0x8000U) -#define GENFSK_XCVR_STS_CRC_VALID_SHIFT (15U) -#define GENFSK_XCVR_STS_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_CRC_VALID_SHIFT)) & GENFSK_XCVR_STS_CRC_VALID_MASK) -#define GENFSK_XCVR_STS_RSSI_MASK (0xFF0000U) -#define GENFSK_XCVR_STS_RSSI_SHIFT (16U) -#define GENFSK_XCVR_STS_RSSI(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RSSI_SHIFT)) & GENFSK_XCVR_STS_RSSI_MASK) -#define GENFSK_XCVR_STS_LQI_MASK (0xFF000000U) -#define GENFSK_XCVR_STS_LQI_SHIFT (24U) -#define GENFSK_XCVR_STS_LQI(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_SHIFT)) & GENFSK_XCVR_STS_LQI_MASK) - -/*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */ -#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK (0x1U) -#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT (0U) -#define GENFSK_XCVR_CFG_TX_WHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK) -#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U) -#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT (1U) -#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK) -#define GENFSK_XCVR_CFG_SW_CRC_EN_MASK (0x4U) -#define GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT (2U) -#define GENFSK_XCVR_CFG_SW_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT)) & GENFSK_XCVR_CFG_SW_CRC_EN_MASK) -#define GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK (0x70U) -#define GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT (4U) -#define GENFSK_XCVR_CFG_PREAMBLE_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK) -#define GENFSK_XCVR_CFG_TX_WARMUP_MASK (0xFF00U) -#define GENFSK_XCVR_CFG_TX_WARMUP_SHIFT (8U) -#define GENFSK_XCVR_CFG_TX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_TX_WARMUP_MASK) -#define GENFSK_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U) -#define GENFSK_XCVR_CFG_RX_WARMUP_SHIFT (16U) -#define GENFSK_XCVR_CFG_RX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_RX_WARMUP_MASK) - -/*! @name CHANNEL_NUM - CHANNEL NUMBER */ -#define GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK (0x7FU) -#define GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT (0U) -#define GENFSK_CHANNEL_NUM_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK) - -/*! @name TX_POWER - TRANSMIT POWER */ -#define GENFSK_TX_POWER_TX_POWER_MASK (0x3FU) -#define GENFSK_TX_POWER_TX_POWER_SHIFT (0U) -#define GENFSK_TX_POWER_TX_POWER(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TX_POWER_TX_POWER_SHIFT)) & GENFSK_TX_POWER_TX_POWER_MASK) - -/*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK (0xFU) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT (0U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK (0xF0U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT (4U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK (0x300U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT (8U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK (0xC00U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT (10U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK (0x3000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT (12U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK (0xC000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT (14U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK (0x70000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT (16U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK (0x700000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT (20U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK (0x7000000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT (24U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK (0x70000000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT (28U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK) - -/*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */ -#define GENFSK_NTW_ADR_0_NTW_ADR_0_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT (0U) -#define GENFSK_NTW_ADR_0_NTW_ADR_0(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT)) & GENFSK_NTW_ADR_0_NTW_ADR_0_MASK) - -/*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */ -#define GENFSK_NTW_ADR_1_NTW_ADR_1_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT (0U) -#define GENFSK_NTW_ADR_1_NTW_ADR_1(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT)) & GENFSK_NTW_ADR_1_NTW_ADR_1_MASK) - -/*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */ -#define GENFSK_NTW_ADR_2_NTW_ADR_2_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT (0U) -#define GENFSK_NTW_ADR_2_NTW_ADR_2(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT)) & GENFSK_NTW_ADR_2_NTW_ADR_2_MASK) - -/*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */ -#define GENFSK_NTW_ADR_3_NTW_ADR_3_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT (0U) -#define GENFSK_NTW_ADR_3_NTW_ADR_3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT)) & GENFSK_NTW_ADR_3_NTW_ADR_3_MASK) - -/*! @name RX_WATERMARK - RECEIVE WATERMARK */ -#define GENFSK_RX_WATERMARK_RX_WATERMARK_MASK (0x1FFFU) -#define GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT (0U) -#define GENFSK_RX_WATERMARK_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT)) & GENFSK_RX_WATERMARK_RX_WATERMARK_MASK) -#define GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK (0x1FFF0000U) -#define GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT (16U) -#define GENFSK_RX_WATERMARK_BYTE_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK) - -/*! @name DSM_CTRL - DSM CONTROL */ -#define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_MASK (0x1U) -#define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_SHIFT (0U) -#define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_SHIFT)) & GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_MASK) - -/*! @name PART_ID - PART ID */ -#define GENFSK_PART_ID_PART_ID_MASK (0xFFU) -#define GENFSK_PART_ID_PART_ID_SHIFT (0U) -#define GENFSK_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PART_ID_PART_ID_SHIFT)) & GENFSK_PART_ID_PART_ID_MASK) - -/*! @name PACKET_CFG - PACKET CONFIGURATION */ -#define GENFSK_PACKET_CFG_LENGTH_SZ_MASK (0x1FU) -#define GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT (0U) -#define GENFSK_PACKET_CFG_LENGTH_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_SZ_MASK) -#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK (0x20U) -#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT (5U) -#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK) -#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK (0xC0U) -#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT (6U) -#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK) -#define GENFSK_PACKET_CFG_LENGTH_ADJ_MASK (0x3F00U) -#define GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT (8U) -#define GENFSK_PACKET_CFG_LENGTH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_ADJ_MASK) -#define GENFSK_PACKET_CFG_LENGTH_FAIL_MASK (0x8000U) -#define GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT (15U) -#define GENFSK_PACKET_CFG_LENGTH_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_FAIL_MASK) -#define GENFSK_PACKET_CFG_H0_SZ_MASK (0x1F0000U) -#define GENFSK_PACKET_CFG_H0_SZ_SHIFT (16U) -#define GENFSK_PACKET_CFG_H0_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_SZ_SHIFT)) & GENFSK_PACKET_CFG_H0_SZ_MASK) -#define GENFSK_PACKET_CFG_H0_FAIL_MASK (0x800000U) -#define GENFSK_PACKET_CFG_H0_FAIL_SHIFT (23U) -#define GENFSK_PACKET_CFG_H0_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H0_FAIL_MASK) -#define GENFSK_PACKET_CFG_H1_SZ_MASK (0x1F000000U) -#define GENFSK_PACKET_CFG_H1_SZ_SHIFT (24U) -#define GENFSK_PACKET_CFG_H1_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_SZ_SHIFT)) & GENFSK_PACKET_CFG_H1_SZ_MASK) -#define GENFSK_PACKET_CFG_H1_FAIL_MASK (0x80000000U) -#define GENFSK_PACKET_CFG_H1_FAIL_SHIFT (31U) -#define GENFSK_PACKET_CFG_H1_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H1_FAIL_MASK) - -/*! @name H0_CFG - H0 CONFIGURATION */ -#define GENFSK_H0_CFG_H0_MATCH_MASK (0xFFFFU) -#define GENFSK_H0_CFG_H0_MATCH_SHIFT (0U) -#define GENFSK_H0_CFG_H0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MATCH_SHIFT)) & GENFSK_H0_CFG_H0_MATCH_MASK) -#define GENFSK_H0_CFG_H0_MASK_MASK (0xFFFF0000U) -#define GENFSK_H0_CFG_H0_MASK_SHIFT (16U) -#define GENFSK_H0_CFG_H0_MASK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MASK_SHIFT)) & GENFSK_H0_CFG_H0_MASK_MASK) - -/*! @name H1_CFG - H1 CONFIGURATION */ -#define GENFSK_H1_CFG_H1_MATCH_MASK (0xFFFFU) -#define GENFSK_H1_CFG_H1_MATCH_SHIFT (0U) -#define GENFSK_H1_CFG_H1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MATCH_SHIFT)) & GENFSK_H1_CFG_H1_MATCH_MASK) -#define GENFSK_H1_CFG_H1_MASK_MASK (0xFFFF0000U) -#define GENFSK_H1_CFG_H1_MASK_SHIFT (16U) -#define GENFSK_H1_CFG_H1_MASK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK) - -/*! @name CRC_CFG - CRC CONFIGURATION */ -#define GENFSK_CRC_CFG_CRC_SZ_MASK (0x7U) -#define GENFSK_CRC_CFG_CRC_SZ_SHIFT (0U) -#define GENFSK_CRC_CFG_CRC_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_SZ_SHIFT)) & GENFSK_CRC_CFG_CRC_SZ_MASK) -#define GENFSK_CRC_CFG_CRC_START_BYTE_MASK (0xF00U) -#define GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT (8U) -#define GENFSK_CRC_CFG_CRC_START_BYTE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT)) & GENFSK_CRC_CFG_CRC_START_BYTE_MASK) -#define GENFSK_CRC_CFG_CRC_REF_IN_MASK (0x10000U) -#define GENFSK_CRC_CFG_CRC_REF_IN_SHIFT (16U) -#define GENFSK_CRC_CFG_CRC_REF_IN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_IN_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_IN_MASK) -#define GENFSK_CRC_CFG_CRC_REF_OUT_MASK (0x20000U) -#define GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT (17U) -#define GENFSK_CRC_CFG_CRC_REF_OUT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_OUT_MASK) -#define GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK (0x40000U) -#define GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT (18U) -#define GENFSK_CRC_CFG_CRC_BYTE_ORD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT)) & GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK) - -/*! @name CRC_INIT - CRC INITIALIZATION */ -#define GENFSK_CRC_INIT_CRC_SEED_MASK (0xFFFFFFFFU) -#define GENFSK_CRC_INIT_CRC_SEED_SHIFT (0U) -#define GENFSK_CRC_INIT_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_INIT_CRC_SEED_SHIFT)) & GENFSK_CRC_INIT_CRC_SEED_MASK) - -/*! @name CRC_POLY - CRC POLYNOMIAL */ -#define GENFSK_CRC_POLY_CRC_POLY_MASK (0xFFFFFFFFU) -#define GENFSK_CRC_POLY_CRC_POLY_SHIFT (0U) -#define GENFSK_CRC_POLY_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_POLY_CRC_POLY_SHIFT)) & GENFSK_CRC_POLY_CRC_POLY_MASK) - -/*! @name CRC_XOR_OUT - CRC XOR OUT */ -#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK (0xFFFFFFFFU) -#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT (0U) -#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT)) & GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK) - -/*! @name WHITEN_CFG - WHITENER CONFIGURATION */ -#define GENFSK_WHITEN_CFG_WHITEN_START_MASK (0x3U) -#define GENFSK_WHITEN_CFG_WHITEN_START_SHIFT (0U) -#define GENFSK_WHITEN_CFG_WHITEN_START(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_START_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_START_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_END_MASK (0x4U) -#define GENFSK_WHITEN_CFG_WHITEN_END_SHIFT (2U) -#define GENFSK_WHITEN_CFG_WHITEN_END(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_END_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_END_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK (0x8U) -#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT (3U) -#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK (0x10U) -#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT (4U) -#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK (0x20U) -#define GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT (5U) -#define GENFSK_WHITEN_CFG_WHITEN_REF_IN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK (0x40U) -#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT (6U) -#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK (0xF00U) -#define GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT (8U) -#define GENFSK_WHITEN_CFG_WHITEN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK) -#define GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK (0x1000U) -#define GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT (12U) -#define GENFSK_WHITEN_CFG_MANCHESTER_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK) -#define GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK (0x2000U) -#define GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT (13U) -#define GENFSK_WHITEN_CFG_MANCHESTER_INV(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK) -#define GENFSK_WHITEN_CFG_MANCHESTER_START_MASK (0x4000U) -#define GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT (14U) -#define GENFSK_WHITEN_CFG_MANCHESTER_START(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_START_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_INIT_MASK (0x1FF0000U) -#define GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT (16U) -#define GENFSK_WHITEN_CFG_WHITEN_INIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_INIT_MASK) - -/*! @name WHITEN_POLY - WHITENER POLYNOMIAL */ -#define GENFSK_WHITEN_POLY_WHITEN_POLY_MASK (0x1FFU) -#define GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT (0U) -#define GENFSK_WHITEN_POLY_WHITEN_POLY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT)) & GENFSK_WHITEN_POLY_WHITEN_POLY_MASK) - -/*! @name WHITEN_SZ_THR - WHITENER SIZE THRESHOLD */ -#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK (0xFFFU) -#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT (0U) -#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT)) & GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK) -#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK (0x7F0000U) -#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT (16U) -#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT)) & GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK) -#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK (0x800000U) -#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT (23U) -#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT)) & GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK) - -/*! @name BITRATE - BIT RATE */ -#define GENFSK_BITRATE_BITRATE_MASK (0x3U) -#define GENFSK_BITRATE_BITRATE_SHIFT (0U) -#define GENFSK_BITRATE_BITRATE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_BITRATE_BITRATE_SHIFT)) & GENFSK_BITRATE_BITRATE_MASK) - -/*! @name PB_PARTITION - PACKET BUFFER PARTITION POINT */ -#define GENFSK_PB_PARTITION_PB_PARTITION_MASK (0x7FFU) -#define GENFSK_PB_PARTITION_PB_PARTITION_SHIFT (0U) -#define GENFSK_PB_PARTITION_PB_PARTITION(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PB_PARTITION_PB_PARTITION_SHIFT)) & GENFSK_PB_PARTITION_PB_PARTITION_MASK) - - -/*! - * @} - */ /* end of group GENFSK_Register_Masks */ - - -/* GENFSK - Peripheral instance base addresses */ -/** Peripheral GENFSK base address */ -#define GENFSK_BASE (0x4005F000u) -/** Peripheral GENFSK base pointer */ -#define GENFSK ((GENFSK_Type *)GENFSK_BASE) -/** Array initializer of GENFSK peripheral base addresses */ -#define GENFSK_BASE_ADDRS { GENFSK_BASE } -/** Array initializer of GENFSK peripheral base pointers */ -#define GENFSK_BASE_PTRS { GENFSK } - -/*! - * @} - */ /* end of group GENFSK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name PDOR - Port Data Output Register */ -#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) -#define GPIO_PDOR_PDO_SHIFT (0U) -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) - -/*! @name PSOR - Port Set Output Register */ -#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) -#define GPIO_PSOR_PTSO_SHIFT (0U) -#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) - -/*! @name PCOR - Port Clear Output Register */ -#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) -#define GPIO_PCOR_PTCO_SHIFT (0U) -#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) - -/*! @name PTOR - Port Toggle Output Register */ -#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) -#define GPIO_PTOR_PTTO_SHIFT (0U) -#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) - -/*! @name PDIR - Port Data Input Register */ -#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) -#define GPIO_PDIR_PDI_SHIFT (0U) -#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) - -/*! @name PDDR - Port Data Direction Register */ -#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) -#define GPIO_PDDR_PDD_SHIFT (0U) -#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIOA base address */ -#define GPIOA_BASE (0x400FF000u) -/** Peripheral GPIOA base pointer */ -#define GPIOA ((GPIO_Type *)GPIOA_BASE) -/** Peripheral GPIOB base address */ -#define GPIOB_BASE (0x400FF040u) -/** Peripheral GPIOB base pointer */ -#define GPIOB ((GPIO_Type *)GPIOB_BASE) -/** Peripheral GPIOC base address */ -#define GPIOC_BASE (0x400FF080u) -/** Peripheral GPIOC base pointer */ -#define GPIOC ((GPIO_Type *)GPIOC_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ - __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ - __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ - __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ - __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ - __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ - __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ - __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ - __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ - __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ - __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ - __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ - __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name A1 - I2C Address Register 1 */ -#define I2C_A1_AD_MASK (0xFEU) -#define I2C_A1_AD_SHIFT (1U) -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) - -/*! @name F - I2C Frequency Divider register */ -#define I2C_F_ICR_MASK (0x3FU) -#define I2C_F_ICR_SHIFT (0U) -#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) -#define I2C_F_MULT_MASK (0xC0U) -#define I2C_F_MULT_SHIFT (6U) -#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) - -/*! @name C1 - I2C Control Register 1 */ -#define I2C_C1_DMAEN_MASK (0x1U) -#define I2C_C1_DMAEN_SHIFT (0U) -#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) -#define I2C_C1_WUEN_MASK (0x2U) -#define I2C_C1_WUEN_SHIFT (1U) -#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) -#define I2C_C1_RSTA_MASK (0x4U) -#define I2C_C1_RSTA_SHIFT (2U) -#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) -#define I2C_C1_TXAK_MASK (0x8U) -#define I2C_C1_TXAK_SHIFT (3U) -#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) -#define I2C_C1_TX_MASK (0x10U) -#define I2C_C1_TX_SHIFT (4U) -#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) -#define I2C_C1_MST_MASK (0x20U) -#define I2C_C1_MST_SHIFT (5U) -#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) -#define I2C_C1_IICIE_MASK (0x40U) -#define I2C_C1_IICIE_SHIFT (6U) -#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) -#define I2C_C1_IICEN_MASK (0x80U) -#define I2C_C1_IICEN_SHIFT (7U) -#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) - -/*! @name S - I2C Status register */ -#define I2C_S_RXAK_MASK (0x1U) -#define I2C_S_RXAK_SHIFT (0U) -#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) -#define I2C_S_IICIF_MASK (0x2U) -#define I2C_S_IICIF_SHIFT (1U) -#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) -#define I2C_S_SRW_MASK (0x4U) -#define I2C_S_SRW_SHIFT (2U) -#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) -#define I2C_S_RAM_MASK (0x8U) -#define I2C_S_RAM_SHIFT (3U) -#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) -#define I2C_S_ARBL_MASK (0x10U) -#define I2C_S_ARBL_SHIFT (4U) -#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) -#define I2C_S_BUSY_MASK (0x20U) -#define I2C_S_BUSY_SHIFT (5U) -#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) -#define I2C_S_IAAS_MASK (0x40U) -#define I2C_S_IAAS_SHIFT (6U) -#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) -#define I2C_S_TCF_MASK (0x80U) -#define I2C_S_TCF_SHIFT (7U) -#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) - -/*! @name D - I2C Data I/O register */ -#define I2C_D_DATA_MASK (0xFFU) -#define I2C_D_DATA_SHIFT (0U) -#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) - -/*! @name C2 - I2C Control Register 2 */ -#define I2C_C2_AD_MASK (0x7U) -#define I2C_C2_AD_SHIFT (0U) -#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) -#define I2C_C2_RMEN_MASK (0x8U) -#define I2C_C2_RMEN_SHIFT (3U) -#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) -#define I2C_C2_SBRC_MASK (0x10U) -#define I2C_C2_SBRC_SHIFT (4U) -#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) -#define I2C_C2_HDRS_MASK (0x20U) -#define I2C_C2_HDRS_SHIFT (5U) -#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) -#define I2C_C2_ADEXT_MASK (0x40U) -#define I2C_C2_ADEXT_SHIFT (6U) -#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) -#define I2C_C2_GCAEN_MASK (0x80U) -#define I2C_C2_GCAEN_SHIFT (7U) -#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) - -/*! @name FLT - I2C Programmable Input Glitch Filter Register */ -#define I2C_FLT_FLT_MASK (0xFU) -#define I2C_FLT_FLT_SHIFT (0U) -#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) -#define I2C_FLT_STARTF_MASK (0x10U) -#define I2C_FLT_STARTF_SHIFT (4U) -#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) -#define I2C_FLT_SSIE_MASK (0x20U) -#define I2C_FLT_SSIE_SHIFT (5U) -#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) -#define I2C_FLT_STOPF_MASK (0x40U) -#define I2C_FLT_STOPF_SHIFT (6U) -#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) -#define I2C_FLT_SHEN_MASK (0x80U) -#define I2C_FLT_SHEN_SHIFT (7U) -#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) - -/*! @name RA - I2C Range Address register */ -#define I2C_RA_RAD_MASK (0xFEU) -#define I2C_RA_RAD_SHIFT (1U) -#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) - -/*! @name SMB - I2C SMBus Control and Status register */ -#define I2C_SMB_SHTF2IE_MASK (0x1U) -#define I2C_SMB_SHTF2IE_SHIFT (0U) -#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) -#define I2C_SMB_SHTF2_MASK (0x2U) -#define I2C_SMB_SHTF2_SHIFT (1U) -#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) -#define I2C_SMB_SHTF1_MASK (0x4U) -#define I2C_SMB_SHTF1_SHIFT (2U) -#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) -#define I2C_SMB_SLTF_MASK (0x8U) -#define I2C_SMB_SLTF_SHIFT (3U) -#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) -#define I2C_SMB_TCKSEL_MASK (0x10U) -#define I2C_SMB_TCKSEL_SHIFT (4U) -#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) -#define I2C_SMB_SIICAEN_MASK (0x20U) -#define I2C_SMB_SIICAEN_SHIFT (5U) -#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) -#define I2C_SMB_ALERTEN_MASK (0x40U) -#define I2C_SMB_ALERTEN_SHIFT (6U) -#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) -#define I2C_SMB_FACK_MASK (0x80U) -#define I2C_SMB_FACK_SHIFT (7U) -#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) - -/*! @name A2 - I2C Address Register 2 */ -#define I2C_A2_SAD_MASK (0xFEU) -#define I2C_A2_SAD_SHIFT (1U) -#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) - -/*! @name SLTH - I2C SCL Low Timeout Register High */ -#define I2C_SLTH_SSLT_MASK (0xFFU) -#define I2C_SLTH_SSLT_SHIFT (0U) -#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) - -/*! @name SLTL - I2C SCL Low Timeout Register Low */ -#define I2C_SLTL_SSLT_MASK (0xFFU) -#define I2C_SLTL_SSLT_SHIFT (0U) -#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) - -/*! @name S2 - I2C Status register 2 */ -#define I2C_S2_EMPTY_MASK (0x1U) -#define I2C_S2_EMPTY_SHIFT (0U) -#define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK) -#define I2C_S2_ERROR_MASK (0x2U) -#define I2C_S2_ERROR_SHIFT (1U) -#define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK) -#define I2C_S2_DFEN_MASK (0x4U) -#define I2C_S2_DFEN_SHIFT (2U) -#define I2C_S2_DFEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_DFEN_SHIFT)) & I2C_S2_DFEN_MASK) - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -/** Peripheral I2C0 base address */ -#define I2C0_BASE (0x40066000u) -/** Peripheral I2C0 base pointer */ -#define I2C0 ((I2C_Type *)I2C0_BASE) -/** Peripheral I2C1 base address */ -#define I2C1_BASE (0x40067000u) -/** Peripheral I2C1 base pointer */ -#define I2C1 ((I2C_Type *)I2C1_BASE) -/** Array initializer of I2C peripheral base addresses */ -#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } -/** Array initializer of I2C peripheral base pointers */ -#define I2C_BASE_PTRS { I2C0, I2C1 } -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer - * @{ - */ - -/** LLWU - Register Layout Typedef */ -typedef struct { - __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ - __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ - __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ - __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ - __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ - __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ - __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ - __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ - __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ - __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ -} LLWU_Type; - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/*! @name PE1 - LLWU Pin Enable 1 register */ -#define LLWU_PE1_WUPE0_MASK (0x3U) -#define LLWU_PE1_WUPE0_SHIFT (0U) -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) -#define LLWU_PE1_WUPE1_MASK (0xCU) -#define LLWU_PE1_WUPE1_SHIFT (2U) -#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) -#define LLWU_PE1_WUPE2_MASK (0x30U) -#define LLWU_PE1_WUPE2_SHIFT (4U) -#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) -#define LLWU_PE1_WUPE3_MASK (0xC0U) -#define LLWU_PE1_WUPE3_SHIFT (6U) -#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) - -/*! @name PE2 - LLWU Pin Enable 2 register */ -#define LLWU_PE2_WUPE4_MASK (0x3U) -#define LLWU_PE2_WUPE4_SHIFT (0U) -#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) -#define LLWU_PE2_WUPE5_MASK (0xCU) -#define LLWU_PE2_WUPE5_SHIFT (2U) -#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) -#define LLWU_PE2_WUPE6_MASK (0x30U) -#define LLWU_PE2_WUPE6_SHIFT (4U) -#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) -#define LLWU_PE2_WUPE7_MASK (0xC0U) -#define LLWU_PE2_WUPE7_SHIFT (6U) -#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) - -/*! @name PE3 - LLWU Pin Enable 3 register */ -#define LLWU_PE3_WUPE8_MASK (0x3U) -#define LLWU_PE3_WUPE8_SHIFT (0U) -#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) -#define LLWU_PE3_WUPE9_MASK (0xCU) -#define LLWU_PE3_WUPE9_SHIFT (2U) -#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) -#define LLWU_PE3_WUPE10_MASK (0x30U) -#define LLWU_PE3_WUPE10_SHIFT (4U) -#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) -#define LLWU_PE3_WUPE11_MASK (0xC0U) -#define LLWU_PE3_WUPE11_SHIFT (6U) -#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) - -/*! @name PE4 - LLWU Pin Enable 4 register */ -#define LLWU_PE4_WUPE12_MASK (0x3U) -#define LLWU_PE4_WUPE12_SHIFT (0U) -#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) -#define LLWU_PE4_WUPE13_MASK (0xCU) -#define LLWU_PE4_WUPE13_SHIFT (2U) -#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) -#define LLWU_PE4_WUPE14_MASK (0x30U) -#define LLWU_PE4_WUPE14_SHIFT (4U) -#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) -#define LLWU_PE4_WUPE15_MASK (0xC0U) -#define LLWU_PE4_WUPE15_SHIFT (6U) -#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) - -/*! @name ME - LLWU Module Enable register */ -#define LLWU_ME_WUME0_MASK (0x1U) -#define LLWU_ME_WUME0_SHIFT (0U) -#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) -#define LLWU_ME_WUME1_MASK (0x2U) -#define LLWU_ME_WUME1_SHIFT (1U) -#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) -#define LLWU_ME_WUME2_MASK (0x4U) -#define LLWU_ME_WUME2_SHIFT (2U) -#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) -#define LLWU_ME_WUME3_MASK (0x8U) -#define LLWU_ME_WUME3_SHIFT (3U) -#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) -#define LLWU_ME_WUME4_MASK (0x10U) -#define LLWU_ME_WUME4_SHIFT (4U) -#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) -#define LLWU_ME_WUME5_MASK (0x20U) -#define LLWU_ME_WUME5_SHIFT (5U) -#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) -#define LLWU_ME_WUME6_MASK (0x40U) -#define LLWU_ME_WUME6_SHIFT (6U) -#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) -#define LLWU_ME_WUME7_MASK (0x80U) -#define LLWU_ME_WUME7_SHIFT (7U) -#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) - -/*! @name F1 - LLWU Flag 1 register */ -#define LLWU_F1_WUF0_MASK (0x1U) -#define LLWU_F1_WUF0_SHIFT (0U) -#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) -#define LLWU_F1_WUF1_MASK (0x2U) -#define LLWU_F1_WUF1_SHIFT (1U) -#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) -#define LLWU_F1_WUF2_MASK (0x4U) -#define LLWU_F1_WUF2_SHIFT (2U) -#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) -#define LLWU_F1_WUF3_MASK (0x8U) -#define LLWU_F1_WUF3_SHIFT (3U) -#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) -#define LLWU_F1_WUF4_MASK (0x10U) -#define LLWU_F1_WUF4_SHIFT (4U) -#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) -#define LLWU_F1_WUF5_MASK (0x20U) -#define LLWU_F1_WUF5_SHIFT (5U) -#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) -#define LLWU_F1_WUF6_MASK (0x40U) -#define LLWU_F1_WUF6_SHIFT (6U) -#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) -#define LLWU_F1_WUF7_MASK (0x80U) -#define LLWU_F1_WUF7_SHIFT (7U) -#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) - -/*! @name F2 - LLWU Flag 2 register */ -#define LLWU_F2_WUF8_MASK (0x1U) -#define LLWU_F2_WUF8_SHIFT (0U) -#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) -#define LLWU_F2_WUF9_MASK (0x2U) -#define LLWU_F2_WUF9_SHIFT (1U) -#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) -#define LLWU_F2_WUF10_MASK (0x4U) -#define LLWU_F2_WUF10_SHIFT (2U) -#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) -#define LLWU_F2_WUF11_MASK (0x8U) -#define LLWU_F2_WUF11_SHIFT (3U) -#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) -#define LLWU_F2_WUF12_MASK (0x10U) -#define LLWU_F2_WUF12_SHIFT (4U) -#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) -#define LLWU_F2_WUF13_MASK (0x20U) -#define LLWU_F2_WUF13_SHIFT (5U) -#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) -#define LLWU_F2_WUF14_MASK (0x40U) -#define LLWU_F2_WUF14_SHIFT (6U) -#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) -#define LLWU_F2_WUF15_MASK (0x80U) -#define LLWU_F2_WUF15_SHIFT (7U) -#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) - -/*! @name F3 - LLWU Flag 3 register */ -#define LLWU_F3_MWUF0_MASK (0x1U) -#define LLWU_F3_MWUF0_SHIFT (0U) -#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) -#define LLWU_F3_MWUF1_MASK (0x2U) -#define LLWU_F3_MWUF1_SHIFT (1U) -#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) -#define LLWU_F3_MWUF2_MASK (0x4U) -#define LLWU_F3_MWUF2_SHIFT (2U) -#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) -#define LLWU_F3_MWUF3_MASK (0x8U) -#define LLWU_F3_MWUF3_SHIFT (3U) -#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) -#define LLWU_F3_MWUF4_MASK (0x10U) -#define LLWU_F3_MWUF4_SHIFT (4U) -#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) -#define LLWU_F3_MWUF5_MASK (0x20U) -#define LLWU_F3_MWUF5_SHIFT (5U) -#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) -#define LLWU_F3_MWUF6_MASK (0x40U) -#define LLWU_F3_MWUF6_SHIFT (6U) -#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) -#define LLWU_F3_MWUF7_MASK (0x80U) -#define LLWU_F3_MWUF7_SHIFT (7U) -#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) - -/*! @name FILT1 - LLWU Pin Filter 1 register */ -#define LLWU_FILT1_FILTSEL_MASK (0xFU) -#define LLWU_FILT1_FILTSEL_SHIFT (0U) -#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) -#define LLWU_FILT1_FILTE_MASK (0x60U) -#define LLWU_FILT1_FILTE_SHIFT (5U) -#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) -#define LLWU_FILT1_FILTF_MASK (0x80U) -#define LLWU_FILT1_FILTF_SHIFT (7U) -#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) - -/*! @name FILT2 - LLWU Pin Filter 2 register */ -#define LLWU_FILT2_FILTSEL_MASK (0xFU) -#define LLWU_FILT2_FILTSEL_SHIFT (0U) -#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) -#define LLWU_FILT2_FILTE_MASK (0x60U) -#define LLWU_FILT2_FILTE_SHIFT (5U) -#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) -#define LLWU_FILT2_FILTF_MASK (0x80U) -#define LLWU_FILT2_FILTF_SHIFT (7U) -#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) - - -/*! - * @} - */ /* end of group LLWU_Register_Masks */ - - -/* LLWU - Peripheral instance base addresses */ -/** Peripheral LLWU base address */ -#define LLWU_BASE (0x4007C000u) -/** Peripheral LLWU base pointer */ -#define LLWU ((LLWU_Type *)LLWU_BASE) -/** Array initializer of LLWU peripheral base addresses */ -#define LLWU_BASE_ADDRS { LLWU_BASE } -/** Array initializer of LLWU peripheral base pointers */ -#define LLWU_BASE_PTRS { LLWU } -/** Interrupt vectors for the LLWU peripheral type */ -#define LLWU_IRQS { LLWU_IRQn } - -/*! - * @} - */ /* end of group LLWU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer - * @{ - */ - -/** LPTMR - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ - __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ - __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ - __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ -} LPTMR_Type; - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/*! @name CSR - Low Power Timer Control Status Register */ -#define LPTMR_CSR_TEN_MASK (0x1U) -#define LPTMR_CSR_TEN_SHIFT (0U) -#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) -#define LPTMR_CSR_TMS_MASK (0x2U) -#define LPTMR_CSR_TMS_SHIFT (1U) -#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) -#define LPTMR_CSR_TFC_MASK (0x4U) -#define LPTMR_CSR_TFC_SHIFT (2U) -#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) -#define LPTMR_CSR_TPP_MASK (0x8U) -#define LPTMR_CSR_TPP_SHIFT (3U) -#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) -#define LPTMR_CSR_TPS_MASK (0x30U) -#define LPTMR_CSR_TPS_SHIFT (4U) -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) -#define LPTMR_CSR_TIE_MASK (0x40U) -#define LPTMR_CSR_TIE_SHIFT (6U) -#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) -#define LPTMR_CSR_TCF_MASK (0x80U) -#define LPTMR_CSR_TCF_SHIFT (7U) -#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) - -/*! @name PSR - Low Power Timer Prescale Register */ -#define LPTMR_PSR_PCS_MASK (0x3U) -#define LPTMR_PSR_PCS_SHIFT (0U) -#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) -#define LPTMR_PSR_PBYP_MASK (0x4U) -#define LPTMR_PSR_PBYP_SHIFT (2U) -#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) -#define LPTMR_PSR_PRESCALE_MASK (0x78U) -#define LPTMR_PSR_PRESCALE_SHIFT (3U) -#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) - -/*! @name CMR - Low Power Timer Compare Register */ -#define LPTMR_CMR_COMPARE_MASK (0xFFFFU) -#define LPTMR_CMR_COMPARE_SHIFT (0U) -#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) - -/*! @name CNR - Low Power Timer Counter Register */ -#define LPTMR_CNR_COUNTER_MASK (0xFFFFU) -#define LPTMR_CNR_COUNTER_SHIFT (0U) -#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) - - -/*! - * @} - */ /* end of group LPTMR_Register_Masks */ - - -/* LPTMR - Peripheral instance base addresses */ -/** Peripheral LPTMR0 base address */ -#define LPTMR0_BASE (0x40040000u) -/** Peripheral LPTMR0 base pointer */ -#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) -/** Array initializer of LPTMR peripheral base addresses */ -#define LPTMR_BASE_ADDRS { LPTMR0_BASE } -/** Array initializer of LPTMR peripheral base pointers */ -#define LPTMR_BASE_PTRS { LPTMR0 } -/** Interrupt vectors for the LPTMR peripheral type */ -#define LPTMR_IRQS { LPTMR0_IRQn } - -/*! - * @} - */ /* end of group LPTMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPUART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer - * @{ - */ - -/** LPUART - Register Layout Typedef */ -typedef struct { - __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ - __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ - __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ - __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ - __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ - __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */ -} LPUART_Type; - -/* ---------------------------------------------------------------------------- - -- LPUART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Register_Masks LPUART Register Masks - * @{ - */ - -/*! @name BAUD - LPUART Baud Rate Register */ -#define LPUART_BAUD_SBR_MASK (0x1FFFU) -#define LPUART_BAUD_SBR_SHIFT (0U) -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) -#define LPUART_BAUD_SBNS_MASK (0x2000U) -#define LPUART_BAUD_SBNS_SHIFT (13U) -#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) -#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) -#define LPUART_BAUD_RXEDGIE_SHIFT (14U) -#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) -#define LPUART_BAUD_LBKDIE_MASK (0x8000U) -#define LPUART_BAUD_LBKDIE_SHIFT (15U) -#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) -#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) -#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) -#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) -#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) -#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) -#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) -#define LPUART_BAUD_MATCFG_MASK (0xC0000U) -#define LPUART_BAUD_MATCFG_SHIFT (18U) -#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) -#define LPUART_BAUD_RDMAE_MASK (0x200000U) -#define LPUART_BAUD_RDMAE_SHIFT (21U) -#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) -#define LPUART_BAUD_TDMAE_MASK (0x800000U) -#define LPUART_BAUD_TDMAE_SHIFT (23U) -#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) -#define LPUART_BAUD_OSR_MASK (0x1F000000U) -#define LPUART_BAUD_OSR_SHIFT (24U) -#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) -#define LPUART_BAUD_M10_MASK (0x20000000U) -#define LPUART_BAUD_M10_SHIFT (29U) -#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) -#define LPUART_BAUD_MAEN2_MASK (0x40000000U) -#define LPUART_BAUD_MAEN2_SHIFT (30U) -#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) -#define LPUART_BAUD_MAEN1_MASK (0x80000000U) -#define LPUART_BAUD_MAEN1_SHIFT (31U) -#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) - -/*! @name STAT - LPUART Status Register */ -#define LPUART_STAT_MA2F_MASK (0x4000U) -#define LPUART_STAT_MA2F_SHIFT (14U) -#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) -#define LPUART_STAT_MA1F_MASK (0x8000U) -#define LPUART_STAT_MA1F_SHIFT (15U) -#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) -#define LPUART_STAT_PF_MASK (0x10000U) -#define LPUART_STAT_PF_SHIFT (16U) -#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) -#define LPUART_STAT_FE_MASK (0x20000U) -#define LPUART_STAT_FE_SHIFT (17U) -#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) -#define LPUART_STAT_NF_MASK (0x40000U) -#define LPUART_STAT_NF_SHIFT (18U) -#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) -#define LPUART_STAT_OR_MASK (0x80000U) -#define LPUART_STAT_OR_SHIFT (19U) -#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) -#define LPUART_STAT_IDLE_MASK (0x100000U) -#define LPUART_STAT_IDLE_SHIFT (20U) -#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) -#define LPUART_STAT_RDRF_MASK (0x200000U) -#define LPUART_STAT_RDRF_SHIFT (21U) -#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) -#define LPUART_STAT_TC_MASK (0x400000U) -#define LPUART_STAT_TC_SHIFT (22U) -#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) -#define LPUART_STAT_TDRE_MASK (0x800000U) -#define LPUART_STAT_TDRE_SHIFT (23U) -#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) -#define LPUART_STAT_RAF_MASK (0x1000000U) -#define LPUART_STAT_RAF_SHIFT (24U) -#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) -#define LPUART_STAT_LBKDE_MASK (0x2000000U) -#define LPUART_STAT_LBKDE_SHIFT (25U) -#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) -#define LPUART_STAT_BRK13_MASK (0x4000000U) -#define LPUART_STAT_BRK13_SHIFT (26U) -#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) -#define LPUART_STAT_RWUID_MASK (0x8000000U) -#define LPUART_STAT_RWUID_SHIFT (27U) -#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) -#define LPUART_STAT_RXINV_MASK (0x10000000U) -#define LPUART_STAT_RXINV_SHIFT (28U) -#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) -#define LPUART_STAT_MSBF_MASK (0x20000000U) -#define LPUART_STAT_MSBF_SHIFT (29U) -#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) -#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) -#define LPUART_STAT_RXEDGIF_SHIFT (30U) -#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) -#define LPUART_STAT_LBKDIF_MASK (0x80000000U) -#define LPUART_STAT_LBKDIF_SHIFT (31U) -#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) - -/*! @name CTRL - LPUART Control Register */ -#define LPUART_CTRL_PT_MASK (0x1U) -#define LPUART_CTRL_PT_SHIFT (0U) -#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) -#define LPUART_CTRL_PE_MASK (0x2U) -#define LPUART_CTRL_PE_SHIFT (1U) -#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) -#define LPUART_CTRL_ILT_MASK (0x4U) -#define LPUART_CTRL_ILT_SHIFT (2U) -#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) -#define LPUART_CTRL_WAKE_MASK (0x8U) -#define LPUART_CTRL_WAKE_SHIFT (3U) -#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) -#define LPUART_CTRL_M_MASK (0x10U) -#define LPUART_CTRL_M_SHIFT (4U) -#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) -#define LPUART_CTRL_RSRC_MASK (0x20U) -#define LPUART_CTRL_RSRC_SHIFT (5U) -#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) -#define LPUART_CTRL_DOZEEN_MASK (0x40U) -#define LPUART_CTRL_DOZEEN_SHIFT (6U) -#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) -#define LPUART_CTRL_LOOPS_MASK (0x80U) -#define LPUART_CTRL_LOOPS_SHIFT (7U) -#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) -#define LPUART_CTRL_IDLECFG_MASK (0x700U) -#define LPUART_CTRL_IDLECFG_SHIFT (8U) -#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) -#define LPUART_CTRL_MA2IE_MASK (0x4000U) -#define LPUART_CTRL_MA2IE_SHIFT (14U) -#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) -#define LPUART_CTRL_MA1IE_MASK (0x8000U) -#define LPUART_CTRL_MA1IE_SHIFT (15U) -#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) -#define LPUART_CTRL_SBK_MASK (0x10000U) -#define LPUART_CTRL_SBK_SHIFT (16U) -#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) -#define LPUART_CTRL_RWU_MASK (0x20000U) -#define LPUART_CTRL_RWU_SHIFT (17U) -#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) -#define LPUART_CTRL_RE_MASK (0x40000U) -#define LPUART_CTRL_RE_SHIFT (18U) -#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) -#define LPUART_CTRL_TE_MASK (0x80000U) -#define LPUART_CTRL_TE_SHIFT (19U) -#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) -#define LPUART_CTRL_ILIE_MASK (0x100000U) -#define LPUART_CTRL_ILIE_SHIFT (20U) -#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) -#define LPUART_CTRL_RIE_MASK (0x200000U) -#define LPUART_CTRL_RIE_SHIFT (21U) -#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) -#define LPUART_CTRL_TCIE_MASK (0x400000U) -#define LPUART_CTRL_TCIE_SHIFT (22U) -#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) -#define LPUART_CTRL_TIE_MASK (0x800000U) -#define LPUART_CTRL_TIE_SHIFT (23U) -#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) -#define LPUART_CTRL_PEIE_MASK (0x1000000U) -#define LPUART_CTRL_PEIE_SHIFT (24U) -#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) -#define LPUART_CTRL_FEIE_MASK (0x2000000U) -#define LPUART_CTRL_FEIE_SHIFT (25U) -#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) -#define LPUART_CTRL_NEIE_MASK (0x4000000U) -#define LPUART_CTRL_NEIE_SHIFT (26U) -#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) -#define LPUART_CTRL_ORIE_MASK (0x8000000U) -#define LPUART_CTRL_ORIE_SHIFT (27U) -#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) -#define LPUART_CTRL_TXINV_MASK (0x10000000U) -#define LPUART_CTRL_TXINV_SHIFT (28U) -#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) -#define LPUART_CTRL_TXDIR_MASK (0x20000000U) -#define LPUART_CTRL_TXDIR_SHIFT (29U) -#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) -#define LPUART_CTRL_R9T8_MASK (0x40000000U) -#define LPUART_CTRL_R9T8_SHIFT (30U) -#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) -#define LPUART_CTRL_R8T9_MASK (0x80000000U) -#define LPUART_CTRL_R8T9_SHIFT (31U) -#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) - -/*! @name DATA - LPUART Data Register */ -#define LPUART_DATA_R0T0_MASK (0x1U) -#define LPUART_DATA_R0T0_SHIFT (0U) -#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) -#define LPUART_DATA_R1T1_MASK (0x2U) -#define LPUART_DATA_R1T1_SHIFT (1U) -#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) -#define LPUART_DATA_R2T2_MASK (0x4U) -#define LPUART_DATA_R2T2_SHIFT (2U) -#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) -#define LPUART_DATA_R3T3_MASK (0x8U) -#define LPUART_DATA_R3T3_SHIFT (3U) -#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) -#define LPUART_DATA_R4T4_MASK (0x10U) -#define LPUART_DATA_R4T4_SHIFT (4U) -#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) -#define LPUART_DATA_R5T5_MASK (0x20U) -#define LPUART_DATA_R5T5_SHIFT (5U) -#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) -#define LPUART_DATA_R6T6_MASK (0x40U) -#define LPUART_DATA_R6T6_SHIFT (6U) -#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) -#define LPUART_DATA_R7T7_MASK (0x80U) -#define LPUART_DATA_R7T7_SHIFT (7U) -#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) -#define LPUART_DATA_R8T8_MASK (0x100U) -#define LPUART_DATA_R8T8_SHIFT (8U) -#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) -#define LPUART_DATA_R9T9_MASK (0x200U) -#define LPUART_DATA_R9T9_SHIFT (9U) -#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) -#define LPUART_DATA_IDLINE_MASK (0x800U) -#define LPUART_DATA_IDLINE_SHIFT (11U) -#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) -#define LPUART_DATA_RXEMPT_MASK (0x1000U) -#define LPUART_DATA_RXEMPT_SHIFT (12U) -#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) -#define LPUART_DATA_FRETSC_MASK (0x2000U) -#define LPUART_DATA_FRETSC_SHIFT (13U) -#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) -#define LPUART_DATA_PARITYE_MASK (0x4000U) -#define LPUART_DATA_PARITYE_SHIFT (14U) -#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) -#define LPUART_DATA_NOISY_MASK (0x8000U) -#define LPUART_DATA_NOISY_SHIFT (15U) -#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) - -/*! @name MATCH - LPUART Match Address Register */ -#define LPUART_MATCH_MA1_MASK (0x3FFU) -#define LPUART_MATCH_MA1_SHIFT (0U) -#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) -#define LPUART_MATCH_MA2_MASK (0x3FF0000U) -#define LPUART_MATCH_MA2_SHIFT (16U) -#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) - -/*! @name MODIR - LPUART Modem IrDA Register */ -#define LPUART_MODIR_TXCTSE_MASK (0x1U) -#define LPUART_MODIR_TXCTSE_SHIFT (0U) -#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) -#define LPUART_MODIR_TXRTSE_MASK (0x2U) -#define LPUART_MODIR_TXRTSE_SHIFT (1U) -#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) -#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) -#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) -#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) -#define LPUART_MODIR_RXRTSE_MASK (0x8U) -#define LPUART_MODIR_RXRTSE_SHIFT (3U) -#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) -#define LPUART_MODIR_TXCTSC_MASK (0x10U) -#define LPUART_MODIR_TXCTSC_SHIFT (4U) -#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) -#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) -#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) -#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) -#define LPUART_MODIR_TNP_MASK (0x30000U) -#define LPUART_MODIR_TNP_SHIFT (16U) -#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) -#define LPUART_MODIR_IREN_MASK (0x40000U) -#define LPUART_MODIR_IREN_SHIFT (18U) -#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) - - -/*! - * @} - */ /* end of group LPUART_Register_Masks */ - - -/* LPUART - Peripheral instance base addresses */ -/** Peripheral LPUART0 base address */ -#define LPUART0_BASE (0x40054000u) -/** Peripheral LPUART0 base pointer */ -#define LPUART0 ((LPUART_Type *)LPUART0_BASE) -/** Array initializer of LPUART peripheral base addresses */ -#define LPUART_BASE_ADDRS { LPUART0_BASE } -/** Array initializer of LPUART peripheral base pointers */ -#define LPUART_BASE_PTRS { LPUART0 } -/** Interrupt vectors for the LPUART peripheral type */ -#define LPUART_RX_TX_IRQS { LPUART0_IRQn } -#define LPUART_ERR_IRQS { LPUART0_IRQn } - -/*! - * @} - */ /* end of group LPUART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer - * @{ - */ - -/** LTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MD; /**< Mode Register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t KS; /**< Key Size Register, offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DS; /**< Data Size Register, offset: 0x10 */ - uint8_t RESERVED_2[4]; - __IO uint32_t ICVS; /**< ICV Size Register, offset: 0x18 */ - uint8_t RESERVED_3[20]; - __IO uint32_t COM; /**< Command Register, offset: 0x30 */ - __IO uint32_t CTL; /**< Control Register, offset: 0x34 */ - uint8_t RESERVED_4[8]; - __IO uint32_t CW; /**< Clear Written Register, offset: 0x40 */ - uint8_t RESERVED_5[4]; - __IO uint32_t STA; /**< Status Register, offset: 0x48 */ - __I uint32_t ESTA; /**< Error Status Register, offset: 0x4C */ - uint8_t RESERVED_6[8]; - __IO uint32_t AADSZ; /**< AAD Size Register, offset: 0x58 */ - uint8_t RESERVED_7[164]; - __IO uint32_t CTX[14]; /**< Context Register, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_8[200]; - __IO uint32_t KEY[4]; /**< Key Registers, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_9[736]; - __I uint32_t VID1; /**< Version ID Register, offset: 0x4F0 */ - __I uint32_t VID2; /**< Version ID 2 Register, offset: 0x4F4 */ - __I uint32_t CHAVID; /**< CHA Version ID Register, offset: 0x4F8 */ - uint8_t RESERVED_10[708]; - __I uint32_t FIFOSTA; /**< FIFO Status Register, offset: 0x7C0 */ - uint8_t RESERVED_11[28]; - __O uint32_t IFIFO; /**< Input Data FIFO, offset: 0x7E0 */ - uint8_t RESERVED_12[12]; - __I uint32_t OFIFO; /**< Output Data FIFO, offset: 0x7F0 */ -} LTC_Type; - -/* ---------------------------------------------------------------------------- - -- LTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LTC_Register_Masks LTC Register Masks - * @{ - */ - -/*! @name MD - Mode Register */ -#define LTC_MD_ENC_MASK (0x1U) -#define LTC_MD_ENC_SHIFT (0U) -#define LTC_MD_ENC(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK) -#define LTC_MD_ICV_TEST_MASK (0x2U) -#define LTC_MD_ICV_TEST_SHIFT (1U) -#define LTC_MD_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK) -#define LTC_MD_AS_MASK (0xCU) -#define LTC_MD_AS_SHIFT (2U) -#define LTC_MD_AS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK) -#define LTC_MD_AAI_MASK (0x1FF0U) -#define LTC_MD_AAI_SHIFT (4U) -#define LTC_MD_AAI(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK) -#define LTC_MD_ALG_MASK (0xFF0000U) -#define LTC_MD_ALG_SHIFT (16U) -#define LTC_MD_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK) - -/*! @name KS - Key Size Register */ -#define LTC_KS_KS_MASK (0x1FU) -#define LTC_KS_KS_SHIFT (0U) -#define LTC_KS_KS(x) (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK) - -/*! @name DS - Data Size Register */ -#define LTC_DS_DS_MASK (0xFFFU) -#define LTC_DS_DS_SHIFT (0U) -#define LTC_DS_DS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK) - -/*! @name ICVS - ICV Size Register */ -#define LTC_ICVS_ICVS_MASK (0x1FU) -#define LTC_ICVS_ICVS_SHIFT (0U) -#define LTC_ICVS_ICVS(x) (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK) - -/*! @name COM - Command Register */ -#define LTC_COM_ALL_MASK (0x1U) -#define LTC_COM_ALL_SHIFT (0U) -#define LTC_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK) -#define LTC_COM_AES_MASK (0x2U) -#define LTC_COM_AES_SHIFT (1U) -#define LTC_COM_AES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK) - -/*! @name CTL - Control Register */ -#define LTC_CTL_IM_MASK (0x1U) -#define LTC_CTL_IM_SHIFT (0U) -#define LTC_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK) -#define LTC_CTL_IFE_MASK (0x100U) -#define LTC_CTL_IFE_SHIFT (8U) -#define LTC_CTL_IFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK) -#define LTC_CTL_IFR_MASK (0x200U) -#define LTC_CTL_IFR_SHIFT (9U) -#define LTC_CTL_IFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK) -#define LTC_CTL_OFE_MASK (0x1000U) -#define LTC_CTL_OFE_SHIFT (12U) -#define LTC_CTL_OFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK) -#define LTC_CTL_OFR_MASK (0x2000U) -#define LTC_CTL_OFR_SHIFT (13U) -#define LTC_CTL_OFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK) -#define LTC_CTL_IFS_MASK (0x10000U) -#define LTC_CTL_IFS_SHIFT (16U) -#define LTC_CTL_IFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK) -#define LTC_CTL_OFS_MASK (0x20000U) -#define LTC_CTL_OFS_SHIFT (17U) -#define LTC_CTL_OFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK) -#define LTC_CTL_KIS_MASK (0x100000U) -#define LTC_CTL_KIS_SHIFT (20U) -#define LTC_CTL_KIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK) -#define LTC_CTL_KOS_MASK (0x200000U) -#define LTC_CTL_KOS_SHIFT (21U) -#define LTC_CTL_KOS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK) -#define LTC_CTL_CIS_MASK (0x400000U) -#define LTC_CTL_CIS_SHIFT (22U) -#define LTC_CTL_CIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK) -#define LTC_CTL_COS_MASK (0x800000U) -#define LTC_CTL_COS_SHIFT (23U) -#define LTC_CTL_COS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK) -#define LTC_CTL_KAL_MASK (0x80000000U) -#define LTC_CTL_KAL_SHIFT (31U) -#define LTC_CTL_KAL(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK) - -/*! @name CW - Clear Written Register */ -#define LTC_CW_CM_MASK (0x1U) -#define LTC_CW_CM_SHIFT (0U) -#define LTC_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK) -#define LTC_CW_CDS_MASK (0x4U) -#define LTC_CW_CDS_SHIFT (2U) -#define LTC_CW_CDS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK) -#define LTC_CW_CICV_MASK (0x8U) -#define LTC_CW_CICV_SHIFT (3U) -#define LTC_CW_CICV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK) -#define LTC_CW_CCR_MASK (0x20U) -#define LTC_CW_CCR_SHIFT (5U) -#define LTC_CW_CCR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK) -#define LTC_CW_CKR_MASK (0x40U) -#define LTC_CW_CKR_SHIFT (6U) -#define LTC_CW_CKR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK) -#define LTC_CW_COF_MASK (0x40000000U) -#define LTC_CW_COF_SHIFT (30U) -#define LTC_CW_COF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK) -#define LTC_CW_CIF_MASK (0x80000000U) -#define LTC_CW_CIF_SHIFT (31U) -#define LTC_CW_CIF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK) - -/*! @name STA - Status Register */ -#define LTC_STA_AB_MASK (0x2U) -#define LTC_STA_AB_SHIFT (1U) -#define LTC_STA_AB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK) -#define LTC_STA_DI_MASK (0x10000U) -#define LTC_STA_DI_SHIFT (16U) -#define LTC_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK) -#define LTC_STA_EI_MASK (0x100000U) -#define LTC_STA_EI_SHIFT (20U) -#define LTC_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK) - -/*! @name ESTA - Error Status Register */ -#define LTC_ESTA_ERRID1_MASK (0xFU) -#define LTC_ESTA_ERRID1_SHIFT (0U) -#define LTC_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK) -#define LTC_ESTA_CL1_MASK (0xF00U) -#define LTC_ESTA_CL1_SHIFT (8U) -#define LTC_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK) - -/*! @name AADSZ - AAD Size Register */ -#define LTC_AADSZ_AADSZ_MASK (0xFU) -#define LTC_AADSZ_AADSZ_SHIFT (0U) -#define LTC_AADSZ_AADSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK) -#define LTC_AADSZ_AL_MASK (0x80000000U) -#define LTC_AADSZ_AL_SHIFT (31U) -#define LTC_AADSZ_AL(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK) - -/*! @name CTX - Context Register */ -#define LTC_CTX_CTX_MASK (0xFFFFFFFFU) -#define LTC_CTX_CTX_SHIFT (0U) -#define LTC_CTX_CTX(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK) - -/* The count of LTC_CTX */ -#define LTC_CTX_COUNT (14U) - -/*! @name KEY - Key Registers */ -#define LTC_KEY_KEY_MASK (0xFFFFFFFFU) -#define LTC_KEY_KEY_SHIFT (0U) -#define LTC_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK) - -/* The count of LTC_KEY */ -#define LTC_KEY_COUNT (4U) - -/*! @name VID1 - Version ID Register */ -#define LTC_VID1_MIN_REV_MASK (0xFFU) -#define LTC_VID1_MIN_REV_SHIFT (0U) -#define LTC_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK) -#define LTC_VID1_MAJ_REV_MASK (0xFF00U) -#define LTC_VID1_MAJ_REV_SHIFT (8U) -#define LTC_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK) -#define LTC_VID1_IP_ID_MASK (0xFFFF0000U) -#define LTC_VID1_IP_ID_SHIFT (16U) -#define LTC_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK) - -/*! @name VID2 - Version ID 2 Register */ -#define LTC_VID2_ECO_REV_MASK (0xFFU) -#define LTC_VID2_ECO_REV_SHIFT (0U) -#define LTC_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ECO_REV_SHIFT)) & LTC_VID2_ECO_REV_MASK) -#define LTC_VID2_ARCH_ERA_MASK (0xFF00U) -#define LTC_VID2_ARCH_ERA_SHIFT (8U) -#define LTC_VID2_ARCH_ERA(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ARCH_ERA_SHIFT)) & LTC_VID2_ARCH_ERA_MASK) - -/*! @name CHAVID - CHA Version ID Register */ -#define LTC_CHAVID_AESREV_MASK (0xFU) -#define LTC_CHAVID_AESREV_SHIFT (0U) -#define LTC_CHAVID_AESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK) -#define LTC_CHAVID_AESVID_MASK (0xF0U) -#define LTC_CHAVID_AESVID_SHIFT (4U) -#define LTC_CHAVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK) - -/*! @name FIFOSTA - FIFO Status Register */ -#define LTC_FIFOSTA_IFL_MASK (0x7FU) -#define LTC_FIFOSTA_IFL_SHIFT (0U) -#define LTC_FIFOSTA_IFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK) -#define LTC_FIFOSTA_IFF_MASK (0x8000U) -#define LTC_FIFOSTA_IFF_SHIFT (15U) -#define LTC_FIFOSTA_IFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK) -#define LTC_FIFOSTA_OFL_MASK (0x7F0000U) -#define LTC_FIFOSTA_OFL_SHIFT (16U) -#define LTC_FIFOSTA_OFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK) -#define LTC_FIFOSTA_OFF_MASK (0x80000000U) -#define LTC_FIFOSTA_OFF_SHIFT (31U) -#define LTC_FIFOSTA_OFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK) - -/*! @name IFIFO - Input Data FIFO */ -#define LTC_IFIFO_IFIFO_MASK (0xFFFFFFFFU) -#define LTC_IFIFO_IFIFO_SHIFT (0U) -#define LTC_IFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK) - -/*! @name OFIFO - Output Data FIFO */ -#define LTC_OFIFO_OFIFO_MASK (0xFFFFFFFFU) -#define LTC_OFIFO_OFIFO_SHIFT (0U) -#define LTC_OFIFO_OFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK) - - -/*! - * @} - */ /* end of group LTC_Register_Masks */ - - -/* LTC - Peripheral instance base addresses */ -/** Peripheral LTC0 base address */ -#define LTC0_BASE (0x40058000u) -/** Peripheral LTC0 base pointer */ -#define LTC0 ((LTC_Type *)LTC0_BASE) -/** Array initializer of LTC peripheral base addresses */ -#define LTC_BASE_ADDRS { LTC0_BASE } -/** Array initializer of LTC peripheral base pointers */ -#define LTC_BASE_PTRS { LTC0 } -/** Interrupt vectors for the LTC peripheral type */ -#define LTC_IRQS { LTC0_IRQn } - -/*! - * @} - */ /* end of group LTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MCG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer - * @{ - */ - -/** MCG - Register Layout Typedef */ -typedef struct { - __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ - __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ - __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ - __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ - __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ - __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ - __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ - uint8_t RESERVED_0[1]; - __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ - uint8_t RESERVED_1[1]; - __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ - __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ - __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ - __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ -} MCG_Type; - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/*! @name C1 - MCG Control 1 Register */ -#define MCG_C1_IREFSTEN_MASK (0x1U) -#define MCG_C1_IREFSTEN_SHIFT (0U) -#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) -#define MCG_C1_IRCLKEN_MASK (0x2U) -#define MCG_C1_IRCLKEN_SHIFT (1U) -#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) -#define MCG_C1_IREFS_MASK (0x4U) -#define MCG_C1_IREFS_SHIFT (2U) -#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) -#define MCG_C1_FRDIV_MASK (0x38U) -#define MCG_C1_FRDIV_SHIFT (3U) -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) -#define MCG_C1_CLKS_MASK (0xC0U) -#define MCG_C1_CLKS_SHIFT (6U) -#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) - -/*! @name C2 - MCG Control 2 Register */ -#define MCG_C2_IRCS_MASK (0x1U) -#define MCG_C2_IRCS_SHIFT (0U) -#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) -#define MCG_C2_LP_MASK (0x2U) -#define MCG_C2_LP_SHIFT (1U) -#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) -#define MCG_C2_EREFS_MASK (0x4U) -#define MCG_C2_EREFS_SHIFT (2U) -#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) -#define MCG_C2_HGO_MASK (0x8U) -#define MCG_C2_HGO_SHIFT (3U) -#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) -#define MCG_C2_RANGE_MASK (0x30U) -#define MCG_C2_RANGE_SHIFT (4U) -#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) -#define MCG_C2_FCFTRIM_MASK (0x40U) -#define MCG_C2_FCFTRIM_SHIFT (6U) -#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) -#define MCG_C2_LOCRE0_MASK (0x80U) -#define MCG_C2_LOCRE0_SHIFT (7U) -#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) - -/*! @name C3 - MCG Control 3 Register */ -#define MCG_C3_SCTRIM_MASK (0xFFU) -#define MCG_C3_SCTRIM_SHIFT (0U) -#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) - -/*! @name C4 - MCG Control 4 Register */ -#define MCG_C4_SCFTRIM_MASK (0x1U) -#define MCG_C4_SCFTRIM_SHIFT (0U) -#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) -#define MCG_C4_FCTRIM_MASK (0x1EU) -#define MCG_C4_FCTRIM_SHIFT (1U) -#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) -#define MCG_C4_DRST_DRS_MASK (0x60U) -#define MCG_C4_DRST_DRS_SHIFT (5U) -#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) -#define MCG_C4_DMX32_MASK (0x80U) -#define MCG_C4_DMX32_SHIFT (7U) -#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) - -/*! @name C6 - MCG Control 6 Register */ -#define MCG_C6_CME0_MASK (0x20U) -#define MCG_C6_CME0_SHIFT (5U) -#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) - -/*! @name S - MCG Status Register */ -#define MCG_S_IRCST_MASK (0x1U) -#define MCG_S_IRCST_SHIFT (0U) -#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) -#define MCG_S_OSCINIT0_MASK (0x2U) -#define MCG_S_OSCINIT0_SHIFT (1U) -#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) -#define MCG_S_CLKST_MASK (0xCU) -#define MCG_S_CLKST_SHIFT (2U) -#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) -#define MCG_S_IREFST_MASK (0x10U) -#define MCG_S_IREFST_SHIFT (4U) -#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) - -/*! @name SC - MCG Status and Control Register */ -#define MCG_SC_LOCS0_MASK (0x1U) -#define MCG_SC_LOCS0_SHIFT (0U) -#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) -#define MCG_SC_FCRDIV_MASK (0xEU) -#define MCG_SC_FCRDIV_SHIFT (1U) -#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) -#define MCG_SC_FLTPRSRV_MASK (0x10U) -#define MCG_SC_FLTPRSRV_SHIFT (4U) -#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) -#define MCG_SC_ATMF_MASK (0x20U) -#define MCG_SC_ATMF_SHIFT (5U) -#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) -#define MCG_SC_ATMS_MASK (0x40U) -#define MCG_SC_ATMS_SHIFT (6U) -#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) -#define MCG_SC_ATME_MASK (0x80U) -#define MCG_SC_ATME_SHIFT (7U) -#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) - -/*! @name ATCVH - MCG Auto Trim Compare Value High Register */ -#define MCG_ATCVH_ATCVH_MASK (0xFFU) -#define MCG_ATCVH_ATCVH_SHIFT (0U) -#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) - -/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ -#define MCG_ATCVL_ATCVL_MASK (0xFFU) -#define MCG_ATCVL_ATCVL_SHIFT (0U) -#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) - -/*! @name C7 - MCG Control 7 Register */ -#define MCG_C7_OSCSEL_MASK (0x1U) -#define MCG_C7_OSCSEL_SHIFT (0U) -#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) - -/*! @name C8 - MCG Control 8 Register */ -#define MCG_C8_LOCS1_MASK (0x1U) -#define MCG_C8_LOCS1_SHIFT (0U) -#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) -#define MCG_C8_CME1_MASK (0x20U) -#define MCG_C8_CME1_SHIFT (5U) -#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) -#define MCG_C8_LOCRE1_MASK (0x80U) -#define MCG_C8_LOCRE1_SHIFT (7U) -#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) - - -/*! - * @} - */ /* end of group MCG_Register_Masks */ - - -/* MCG - Peripheral instance base addresses */ -/** Peripheral MCG base address */ -#define MCG_BASE (0x40064000u) -/** Peripheral MCG base pointer */ -#define MCG ((MCG_Type *)MCG_BASE) -/** Array initializer of MCG peripheral base addresses */ -#define MCG_BASE_ADDRS { MCG_BASE } -/** Array initializer of MCG peripheral base pointers */ -#define MCG_BASE_PTRS { MCG } -/** Interrupt vectors for the MCG peripheral type */ -#define MCG_IRQS { MCG_IRQn } - -/*! - * @} - */ /* end of group MCG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer - * @{ - */ - -/** MCM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[8]; - __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ - __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ - __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ - uint8_t RESERVED_1[48]; - __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ -} MCM_Type; - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ -#define MCM_PLASC_ASC_MASK (0xFFU) -#define MCM_PLASC_ASC_SHIFT (0U) -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) - -/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ -#define MCM_PLAMC_AMC_MASK (0xFFU) -#define MCM_PLAMC_AMC_SHIFT (0U) -#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) - -/*! @name PLACR - Platform Control Register */ -#define MCM_PLACR_ARB_MASK (0x200U) -#define MCM_PLACR_ARB_SHIFT (9U) -#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) -#define MCM_PLACR_CFCC_MASK (0x400U) -#define MCM_PLACR_CFCC_SHIFT (10U) -#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) -#define MCM_PLACR_DFCDA_MASK (0x800U) -#define MCM_PLACR_DFCDA_SHIFT (11U) -#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) -#define MCM_PLACR_DFCIC_MASK (0x1000U) -#define MCM_PLACR_DFCIC_SHIFT (12U) -#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) -#define MCM_PLACR_DFCC_MASK (0x2000U) -#define MCM_PLACR_DFCC_SHIFT (13U) -#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) -#define MCM_PLACR_EFDS_MASK (0x4000U) -#define MCM_PLACR_EFDS_SHIFT (14U) -#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) -#define MCM_PLACR_DFCS_MASK (0x8000U) -#define MCM_PLACR_DFCS_SHIFT (15U) -#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) -#define MCM_PLACR_ESFC_MASK (0x10000U) -#define MCM_PLACR_ESFC_SHIFT (16U) -#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) - -/*! @name CPO - Compute Operation Control Register */ -#define MCM_CPO_CPOREQ_MASK (0x1U) -#define MCM_CPO_CPOREQ_SHIFT (0U) -#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) -#define MCM_CPO_CPOACK_MASK (0x2U) -#define MCM_CPO_CPOACK_SHIFT (1U) -#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) -#define MCM_CPO_CPOWOI_MASK (0x4U) -#define MCM_CPO_CPOWOI_SHIFT (2U) -#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) - - -/*! - * @} - */ /* end of group MCM_Register_Masks */ - - -/* MCM - Peripheral instance base addresses */ -/** Peripheral MCM base address */ -#define MCM_BASE (0xF0003000u) -/** Peripheral MCM base pointer */ -#define MCM ((MCM_Type *)MCM_BASE) -/** Array initializer of MCM peripheral base addresses */ -#define MCM_BASE_ADDRS { MCM_BASE } -/** Array initializer of MCM peripheral base pointers */ -#define MCM_BASE_PTRS { MCM } - -/*! - * @} - */ /* end of group MCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MTB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer - * @{ - */ - -/** MTB - Register Layout Typedef */ -typedef struct { - __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ - __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ - __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ - __I uint32_t _BASE; /**< MTB Base Register, offset: 0xC */ - uint8_t RESERVED_0[3824]; - __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ - uint8_t RESERVED_1[156]; - __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ - __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ - uint8_t RESERVED_2[8]; - __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ - __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ - __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ - __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ - uint8_t RESERVED_3[8]; - __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ - __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ - __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ - __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ - __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ - __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ - __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ - __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ - __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ - __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ - __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ -} MTB_Type; - -/* ---------------------------------------------------------------------------- - -- MTB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTB_Register_Masks MTB Register Masks - * @{ - */ - -/*! @name POSITION - MTB Position Register */ -#define MTB_POSITION_WRAP_MASK (0x4U) -#define MTB_POSITION_WRAP_SHIFT (2U) -#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) -#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) -#define MTB_POSITION_POINTER_SHIFT (3U) -#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) - -/*! @name MASTER - MTB Master Register */ -#define MTB_MASTER_MASK_MASK (0x1FU) -#define MTB_MASTER_MASK_SHIFT (0U) -#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) -#define MTB_MASTER_TSTARTEN_MASK (0x20U) -#define MTB_MASTER_TSTARTEN_SHIFT (5U) -#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) -#define MTB_MASTER_TSTOPEN_MASK (0x40U) -#define MTB_MASTER_TSTOPEN_SHIFT (6U) -#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) -#define MTB_MASTER_SFRWPRIV_MASK (0x80U) -#define MTB_MASTER_SFRWPRIV_SHIFT (7U) -#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) -#define MTB_MASTER_RAMPRIV_MASK (0x100U) -#define MTB_MASTER_RAMPRIV_SHIFT (8U) -#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) -#define MTB_MASTER_HALTREQ_MASK (0x200U) -#define MTB_MASTER_HALTREQ_SHIFT (9U) -#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) -#define MTB_MASTER_EN_MASK (0x80000000U) -#define MTB_MASTER_EN_SHIFT (31U) -#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) - -/*! @name FLOW - MTB Flow Register */ -#define MTB_FLOW_AUTOSTOP_MASK (0x1U) -#define MTB_FLOW_AUTOSTOP_SHIFT (0U) -#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) -#define MTB_FLOW_AUTOHALT_MASK (0x2U) -#define MTB_FLOW_AUTOHALT_SHIFT (1U) -#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) -#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) -#define MTB_FLOW_WATERMARK_SHIFT (3U) -#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) - -/*! @name BASE - MTB Base Register */ -#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) -#define MTB_BASE_BASEADDR_SHIFT (0U) -#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) - -/*! @name MODECTRL - Integration Mode Control Register */ -#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) -#define MTB_MODECTRL_MODECTRL_SHIFT (0U) -#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) - -/*! @name TAGSET - Claim TAG Set Register */ -#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) -#define MTB_TAGSET_TAGSET_SHIFT (0U) -#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) - -/*! @name TAGCLEAR - Claim TAG Clear Register */ -#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) -#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) -#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) - -/*! @name LOCKACCESS - Lock Access Register */ -#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) -#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) -#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) - -/*! @name LOCKSTAT - Lock Status Register */ -#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) -#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) -#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) - -/*! @name AUTHSTAT - Authentication Status Register */ -#define MTB_AUTHSTAT_BIT0_MASK (0x1U) -#define MTB_AUTHSTAT_BIT0_SHIFT (0U) -#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) -#define MTB_AUTHSTAT_BIT1_MASK (0x2U) -#define MTB_AUTHSTAT_BIT1_SHIFT (1U) -#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) -#define MTB_AUTHSTAT_BIT2_MASK (0x4U) -#define MTB_AUTHSTAT_BIT2_SHIFT (2U) -#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) -#define MTB_AUTHSTAT_BIT3_MASK (0x8U) -#define MTB_AUTHSTAT_BIT3_SHIFT (3U) -#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) - -/*! @name DEVICEARCH - Device Architecture Register */ -#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) -#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) -#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) - -/*! @name DEVICECFG - Device Configuration Register */ -#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) -#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) -#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) - -/*! @name DEVICETYPID - Device Type Identifier Register */ -#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) -#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) -#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) - -/*! @name PERIPHID4 - Peripheral ID Register */ -#define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID4_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) - -/*! @name PERIPHID5 - Peripheral ID Register */ -#define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID5_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) - -/*! @name PERIPHID6 - Peripheral ID Register */ -#define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID6_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) - -/*! @name PERIPHID7 - Peripheral ID Register */ -#define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID7_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) - -/*! @name PERIPHID0 - Peripheral ID Register */ -#define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID0_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) - -/*! @name PERIPHID1 - Peripheral ID Register */ -#define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID1_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) - -/*! @name PERIPHID2 - Peripheral ID Register */ -#define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID2_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) - -/*! @name PERIPHID3 - Peripheral ID Register */ -#define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID3_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) - -/*! @name COMPID - Component ID Register */ -#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) -#define MTB_COMPID_COMPID_SHIFT (0U) -#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) - -/* The count of MTB_COMPID */ -#define MTB_COMPID_COUNT (4U) - - -/*! - * @} - */ /* end of group MTB_Register_Masks */ - - -/* MTB - Peripheral instance base addresses */ -/** Peripheral MTB base address */ -#define MTB_BASE (0xF0000000u) -/** Peripheral MTB base pointer */ -#define MTB ((MTB_Type *)MTB_BASE) -/** Array initializer of MTB peripheral base addresses */ -#define MTB_BASE_ADDRS { MTB_BASE } -/** Array initializer of MTB peripheral base pointers */ -#define MTB_BASE_PTRS { MTB } - -/*! - * @} - */ /* end of group MTB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MTBDWT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer - * @{ - */ - -/** MTBDWT - Register Layout Typedef */ -typedef struct { - __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - struct { /* offset: 0x20, array step: 0x10 */ - __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ - __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ - __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } COMPARATOR[2]; - uint8_t RESERVED_1[448]; - __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ - uint8_t RESERVED_2[3524]; - __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ - __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ - __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ - __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ - __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ - __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ - __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ - __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ - __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ - __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ - __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ -} MTBDWT_Type; - -/* ---------------------------------------------------------------------------- - -- MTBDWT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks - * @{ - */ - -/*! @name CTRL - MTB DWT Control Register */ -#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) -#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) -#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) -#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) -#define MTBDWT_CTRL_NUMCMP_SHIFT (28U) -#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) - -/*! @name COMP - MTB_DWT Comparator Register */ -#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) -#define MTBDWT_COMP_COMP_SHIFT (0U) -#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) - -/* The count of MTBDWT_COMP */ -#define MTBDWT_COMP_COUNT (2U) - -/*! @name MASK - MTB_DWT Comparator Mask Register */ -#define MTBDWT_MASK_MASK_MASK (0x1FU) -#define MTBDWT_MASK_MASK_SHIFT (0U) -#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) - -/* The count of MTBDWT_MASK */ -#define MTBDWT_MASK_COUNT (2U) - -/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ -#define MTBDWT_FCT_FUNCTION_MASK (0xFU) -#define MTBDWT_FCT_FUNCTION_SHIFT (0U) -#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) -#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) -#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) -#define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) -#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) -#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) -#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) -#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) -#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) -#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) -#define MTBDWT_FCT_MATCHED_MASK (0x1000000U) -#define MTBDWT_FCT_MATCHED_SHIFT (24U) -#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) - -/* The count of MTBDWT_FCT */ -#define MTBDWT_FCT_COUNT (2U) - -/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ -#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) -#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) -#define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) -#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) -#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) -#define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) -#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) -#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) -#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) - -/*! @name DEVICECFG - Device Configuration Register */ -#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) -#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) -#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) - -/*! @name DEVICETYPID - Device Type Identifier Register */ -#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) -#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) -#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) - -/*! @name PERIPHID4 - Peripheral ID Register */ -#define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) - -/*! @name PERIPHID5 - Peripheral ID Register */ -#define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) - -/*! @name PERIPHID6 - Peripheral ID Register */ -#define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) - -/*! @name PERIPHID7 - Peripheral ID Register */ -#define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) - -/*! @name PERIPHID0 - Peripheral ID Register */ -#define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) - -/*! @name PERIPHID1 - Peripheral ID Register */ -#define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) - -/*! @name PERIPHID2 - Peripheral ID Register */ -#define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) - -/*! @name PERIPHID3 - Peripheral ID Register */ -#define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) - -/*! @name COMPID - Component ID Register */ -#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) -#define MTBDWT_COMPID_COMPID_SHIFT (0U) -#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) - -/* The count of MTBDWT_COMPID */ -#define MTBDWT_COMPID_COUNT (4U) - - -/*! - * @} - */ /* end of group MTBDWT_Register_Masks */ - - -/* MTBDWT - Peripheral instance base addresses */ -/** Peripheral MTBDWT base address */ -#define MTBDWT_BASE (0xF0001000u) -/** Peripheral MTBDWT base pointer */ -#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) -/** Array initializer of MTBDWT peripheral base addresses */ -#define MTBDWT_BASE_ADDRS { MTBDWT_BASE } -/** Array initializer of MTBDWT peripheral base pointers */ -#define MTBDWT_BASE_PTRS { MTBDWT } - -/*! - * @} - */ /* end of group MTBDWT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- NV Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer - * @{ - */ - -/** NV - Register Layout Typedef */ -typedef struct { - __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ - __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ - __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ - __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ - __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ - __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ - __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ - __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ - __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ - __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ - __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ - __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ - __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ - __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ -} NV_Type; - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/*! @name BACKKEY3 - Backdoor Comparison Key 3. */ -#define NV_BACKKEY3_KEY_MASK (0xFFU) -#define NV_BACKKEY3_KEY_SHIFT (0U) -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) - -/*! @name BACKKEY2 - Backdoor Comparison Key 2. */ -#define NV_BACKKEY2_KEY_MASK (0xFFU) -#define NV_BACKKEY2_KEY_SHIFT (0U) -#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) - -/*! @name BACKKEY1 - Backdoor Comparison Key 1. */ -#define NV_BACKKEY1_KEY_MASK (0xFFU) -#define NV_BACKKEY1_KEY_SHIFT (0U) -#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) - -/*! @name BACKKEY0 - Backdoor Comparison Key 0. */ -#define NV_BACKKEY0_KEY_MASK (0xFFU) -#define NV_BACKKEY0_KEY_SHIFT (0U) -#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) - -/*! @name BACKKEY7 - Backdoor Comparison Key 7. */ -#define NV_BACKKEY7_KEY_MASK (0xFFU) -#define NV_BACKKEY7_KEY_SHIFT (0U) -#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) - -/*! @name BACKKEY6 - Backdoor Comparison Key 6. */ -#define NV_BACKKEY6_KEY_MASK (0xFFU) -#define NV_BACKKEY6_KEY_SHIFT (0U) -#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) - -/*! @name BACKKEY5 - Backdoor Comparison Key 5. */ -#define NV_BACKKEY5_KEY_MASK (0xFFU) -#define NV_BACKKEY5_KEY_SHIFT (0U) -#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) - -/*! @name BACKKEY4 - Backdoor Comparison Key 4. */ -#define NV_BACKKEY4_KEY_MASK (0xFFU) -#define NV_BACKKEY4_KEY_SHIFT (0U) -#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) - -/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ -#define NV_FPROT3_PROT_MASK (0xFFU) -#define NV_FPROT3_PROT_SHIFT (0U) -#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) - -/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ -#define NV_FPROT2_PROT_MASK (0xFFU) -#define NV_FPROT2_PROT_SHIFT (0U) -#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) - -/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ -#define NV_FPROT1_PROT_MASK (0xFFU) -#define NV_FPROT1_PROT_SHIFT (0U) -#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) - -/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ -#define NV_FPROT0_PROT_MASK (0xFFU) -#define NV_FPROT0_PROT_SHIFT (0U) -#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) - -/*! @name FSEC - Non-volatile Flash Security Register */ -#define NV_FSEC_SEC_MASK (0x3U) -#define NV_FSEC_SEC_SHIFT (0U) -#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) -#define NV_FSEC_FSLACC_MASK (0xCU) -#define NV_FSEC_FSLACC_SHIFT (2U) -#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) -#define NV_FSEC_MEEN_MASK (0x30U) -#define NV_FSEC_MEEN_SHIFT (4U) -#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) -#define NV_FSEC_KEYEN_MASK (0xC0U) -#define NV_FSEC_KEYEN_SHIFT (6U) -#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) - -/*! @name FOPT - Non-volatile Flash Option Register */ -#define NV_FOPT_LPBOOT0_MASK (0x1U) -#define NV_FOPT_LPBOOT0_SHIFT (0U) -#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK) -#define NV_FOPT_NMI_DIS_MASK (0x4U) -#define NV_FOPT_NMI_DIS_SHIFT (2U) -#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) -#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) -#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) -#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) -#define NV_FOPT_LPBOOT1_MASK (0x10U) -#define NV_FOPT_LPBOOT1_SHIFT (4U) -#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK) -#define NV_FOPT_FAST_INIT_MASK (0x20U) -#define NV_FOPT_FAST_INIT_SHIFT (5U) -#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) - - -/*! - * @} - */ /* end of group NV_Register_Masks */ - - -/* NV - Peripheral instance base addresses */ -/** Peripheral FTFA_FlashConfig base address */ -#define FTFA_FlashConfig_BASE (0x400u) -/** Peripheral FTFA_FlashConfig base pointer */ -#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) -/** Array initializer of NV peripheral base addresses */ -#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } -/** Array initializer of NV peripheral base pointers */ -#define NV_BASE_PTRS { FTFA_FlashConfig } - -/*! - * @} - */ /* end of group NV_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer - * @{ - */ - -/** PIT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ - uint8_t RESERVED_0[220]; - __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ - __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ - uint8_t RESERVED_1[24]; - struct { /* offset: 0x100, array step: 0x10 */ - __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ - __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ - __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ - __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ - } CHANNEL[2]; -} PIT_Type; - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/*! @name MCR - PIT Module Control Register */ -#define PIT_MCR_FRZ_MASK (0x1U) -#define PIT_MCR_FRZ_SHIFT (0U) -#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) -#define PIT_MCR_MDIS_MASK (0x2U) -#define PIT_MCR_MDIS_SHIFT (1U) -#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) - -/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ -#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) -#define PIT_LTMR64H_LTH_SHIFT (0U) -#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) - -/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ -#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) -#define PIT_LTMR64L_LTL_SHIFT (0U) -#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) - -/*! @name LDVAL - Timer Load Value Register */ -#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) -#define PIT_LDVAL_TSV_SHIFT (0U) -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) - -/* The count of PIT_LDVAL */ -#define PIT_LDVAL_COUNT (2U) - -/*! @name CVAL - Current Timer Value Register */ -#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) -#define PIT_CVAL_TVL_SHIFT (0U) -#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) - -/* The count of PIT_CVAL */ -#define PIT_CVAL_COUNT (2U) - -/*! @name TCTRL - Timer Control Register */ -#define PIT_TCTRL_TEN_MASK (0x1U) -#define PIT_TCTRL_TEN_SHIFT (0U) -#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) -#define PIT_TCTRL_TIE_MASK (0x2U) -#define PIT_TCTRL_TIE_SHIFT (1U) -#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) -#define PIT_TCTRL_CHN_MASK (0x4U) -#define PIT_TCTRL_CHN_SHIFT (2U) -#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) - -/* The count of PIT_TCTRL */ -#define PIT_TCTRL_COUNT (2U) - -/*! @name TFLG - Timer Flag Register */ -#define PIT_TFLG_TIF_MASK (0x1U) -#define PIT_TFLG_TIF_SHIFT (0U) -#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) - -/* The count of PIT_TFLG */ -#define PIT_TFLG_COUNT (2U) - - -/*! - * @} - */ /* end of group PIT_Register_Masks */ - - -/* PIT - Peripheral instance base addresses */ -/** Peripheral PIT base address */ -#define PIT_BASE (0x40037000u) -/** Peripheral PIT base pointer */ -#define PIT ((PIT_Type *)PIT_BASE) -/** Array initializer of PIT peripheral base addresses */ -#define PIT_BASE_ADDRS { PIT_BASE } -/** Array initializer of PIT peripheral base pointers */ -#define PIT_BASE_PTRS { PIT } -/** Interrupt vectors for the PIT peripheral type */ -#define PIT_IRQS { { PIT_IRQn, PIT_IRQn } } - -/*! - * @} - */ /* end of group PIT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ - __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ - __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ -#define PMC_LVDSC1_LVDV_MASK (0x3U) -#define PMC_LVDSC1_LVDV_SHIFT (0U) -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) -#define PMC_LVDSC1_LVDRE_MASK (0x10U) -#define PMC_LVDSC1_LVDRE_SHIFT (4U) -#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) -#define PMC_LVDSC1_LVDIE_MASK (0x20U) -#define PMC_LVDSC1_LVDIE_SHIFT (5U) -#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) -#define PMC_LVDSC1_LVDACK_MASK (0x40U) -#define PMC_LVDSC1_LVDACK_SHIFT (6U) -#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) -#define PMC_LVDSC1_LVDF_MASK (0x80U) -#define PMC_LVDSC1_LVDF_SHIFT (7U) -#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) - -/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ -#define PMC_LVDSC2_LVWV_MASK (0x3U) -#define PMC_LVDSC2_LVWV_SHIFT (0U) -#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) -#define PMC_LVDSC2_LVWIE_MASK (0x20U) -#define PMC_LVDSC2_LVWIE_SHIFT (5U) -#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) -#define PMC_LVDSC2_LVWACK_MASK (0x40U) -#define PMC_LVDSC2_LVWACK_SHIFT (6U) -#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) -#define PMC_LVDSC2_LVWF_MASK (0x80U) -#define PMC_LVDSC2_LVWF_SHIFT (7U) -#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) - -/*! @name REGSC - Regulator Status And Control register */ -#define PMC_REGSC_BGBE_MASK (0x1U) -#define PMC_REGSC_BGBE_SHIFT (0U) -#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) -#define PMC_REGSC_REGONS_MASK (0x4U) -#define PMC_REGSC_REGONS_SHIFT (2U) -#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) -#define PMC_REGSC_ACKISO_MASK (0x8U) -#define PMC_REGSC_ACKISO_SHIFT (3U) -#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) -#define PMC_REGSC_VLPO_MASK (0x40U) -#define PMC_REGSC_VLPO_SHIFT (6U) -#define PMC_REGSC_VLPO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK) - - -/*! - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -/** Peripheral PMC base address */ -#define PMC_BASE (0x4007D000u) -/** Peripheral PMC base pointer */ -#define PMC ((PMC_Type *)PMC_BASE) -/** Array initializer of PMC peripheral base addresses */ -#define PMC_BASE_ADDRS { PMC_BASE } -/** Array initializer of PMC peripheral base pointers */ -#define PMC_BASE_PTRS { PMC } -/** Interrupt vectors for the PMC peripheral type */ -#define PMC_IRQS { LVD_LVW_DCDC_IRQn } - -/*! - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PORT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer - * @{ - */ - -/** PORT - Register Layout Typedef */ -typedef struct { - __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ - __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ - __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ - uint8_t RESERVED_0[24]; - __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ -} PORT_Type; - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/*! @name PCR - Pin Control Register n */ -#define PORT_PCR_PS_MASK (0x1U) -#define PORT_PCR_PS_SHIFT (0U) -#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) -#define PORT_PCR_PE_MASK (0x2U) -#define PORT_PCR_PE_SHIFT (1U) -#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) -#define PORT_PCR_SRE_MASK (0x4U) -#define PORT_PCR_SRE_SHIFT (2U) -#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) -#define PORT_PCR_PFE_MASK (0x10U) -#define PORT_PCR_PFE_SHIFT (4U) -#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) -#define PORT_PCR_DSE_MASK (0x40U) -#define PORT_PCR_DSE_SHIFT (6U) -#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) -#define PORT_PCR_MUX_MASK (0x700U) -#define PORT_PCR_MUX_SHIFT (8U) -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) -#define PORT_PCR_IRQC_MASK (0xF0000U) -#define PORT_PCR_IRQC_SHIFT (16U) -#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) -#define PORT_PCR_ISF_MASK (0x1000000U) -#define PORT_PCR_ISF_SHIFT (24U) -#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) - -/* The count of PORT_PCR */ -#define PORT_PCR_COUNT (32U) - -/*! @name GPCLR - Global Pin Control Low Register */ -#define PORT_GPCLR_GPWD_MASK (0xFFFFU) -#define PORT_GPCLR_GPWD_SHIFT (0U) -#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) -#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCLR_GPWE_SHIFT (16U) -#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) - -/*! @name GPCHR - Global Pin Control High Register */ -#define PORT_GPCHR_GPWD_MASK (0xFFFFU) -#define PORT_GPCHR_GPWD_SHIFT (0U) -#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) -#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCHR_GPWE_SHIFT (16U) -#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) - -/*! @name ISFR - Interrupt Status Flag Register */ -#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) -#define PORT_ISFR_ISF_SHIFT (0U) -#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) - - -/*! - * @} - */ /* end of group PORT_Register_Masks */ - - -/* PORT - Peripheral instance base addresses */ -/** Peripheral PORTA base address */ -#define PORTA_BASE (0x40049000u) -/** Peripheral PORTA base pointer */ -#define PORTA ((PORT_Type *)PORTA_BASE) -/** Peripheral PORTB base address */ -#define PORTB_BASE (0x4004A000u) -/** Peripheral PORTB base pointer */ -#define PORTB ((PORT_Type *)PORTB_BASE) -/** Peripheral PORTC base address */ -#define PORTC_BASE (0x4004B000u) -/** Peripheral PORTC base pointer */ -#define PORTC ((PORT_Type *)PORTC_BASE) -/** Array initializer of PORT peripheral base addresses */ -#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE } -/** Array initializer of PORT peripheral base pointers */ -#define PORT_BASE_PTRS { PORTA, PORTB, PORTC } -/** Interrupt vectors for the PORT peripheral type */ -#define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn } - -/*! - * @} - */ /* end of group PORT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer - * @{ - */ - -/** RCM - Register Layout Typedef */ -typedef struct { - __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ - __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ - uint8_t RESERVED_0[2]; - __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ - __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ -} RCM_Type; - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/*! @name SRS0 - System Reset Status Register 0 */ -#define RCM_SRS0_WAKEUP_MASK (0x1U) -#define RCM_SRS0_WAKEUP_SHIFT (0U) -#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) -#define RCM_SRS0_LVD_MASK (0x2U) -#define RCM_SRS0_LVD_SHIFT (1U) -#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) -#define RCM_SRS0_LOC_MASK (0x4U) -#define RCM_SRS0_LOC_SHIFT (2U) -#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) -#define RCM_SRS0_WDOG_MASK (0x20U) -#define RCM_SRS0_WDOG_SHIFT (5U) -#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) -#define RCM_SRS0_PIN_MASK (0x40U) -#define RCM_SRS0_PIN_SHIFT (6U) -#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) -#define RCM_SRS0_POR_MASK (0x80U) -#define RCM_SRS0_POR_SHIFT (7U) -#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) - -/*! @name SRS1 - System Reset Status Register 1 */ -#define RCM_SRS1_LOCKUP_MASK (0x2U) -#define RCM_SRS1_LOCKUP_SHIFT (1U) -#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) -#define RCM_SRS1_SW_MASK (0x4U) -#define RCM_SRS1_SW_SHIFT (2U) -#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) -#define RCM_SRS1_MDM_AP_MASK (0x8U) -#define RCM_SRS1_MDM_AP_SHIFT (3U) -#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) -#define RCM_SRS1_SACKERR_MASK (0x20U) -#define RCM_SRS1_SACKERR_SHIFT (5U) -#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) - -/*! @name RPFC - Reset Pin Filter Control register */ -#define RCM_RPFC_RSTFLTSRW_MASK (0x3U) -#define RCM_RPFC_RSTFLTSRW_SHIFT (0U) -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) -#define RCM_RPFC_RSTFLTSS_MASK (0x4U) -#define RCM_RPFC_RSTFLTSS_SHIFT (2U) -#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) - -/*! @name RPFW - Reset Pin Filter Width register */ -#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) -#define RCM_RPFW_RSTFLTSEL_SHIFT (0U) -#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) - - -/*! - * @} - */ /* end of group RCM_Register_Masks */ - - -/* RCM - Peripheral instance base addresses */ -/** Peripheral RCM base address */ -#define RCM_BASE (0x4007F000u) -/** Peripheral RCM base pointer */ -#define RCM ((RCM_Type *)RCM_BASE) -/** Array initializer of RCM peripheral base addresses */ -#define RCM_BASE_ADDRS { RCM_BASE } -/** Array initializer of RCM peripheral base pointers */ -#define RCM_BASE_PTRS { RCM } - -/*! - * @} - */ /* end of group RCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer - * @{ - */ - -/** RFSYS - Register Layout Typedef */ -typedef struct { - __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ -} RFSYS_Type; - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/*! @name REG - Register file register */ -#define RFSYS_REG_LL_MASK (0xFFU) -#define RFSYS_REG_LL_SHIFT (0U) -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) -#define RFSYS_REG_LH_MASK (0xFF00U) -#define RFSYS_REG_LH_SHIFT (8U) -#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) -#define RFSYS_REG_HL_MASK (0xFF0000U) -#define RFSYS_REG_HL_SHIFT (16U) -#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) -#define RFSYS_REG_HH_MASK (0xFF000000U) -#define RFSYS_REG_HH_SHIFT (24U) -#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) - -/* The count of RFSYS_REG */ -#define RFSYS_REG_COUNT (8U) - - -/*! - * @} - */ /* end of group RFSYS_Register_Masks */ - - -/* RFSYS - Peripheral instance base addresses */ -/** Peripheral RFSYS base address */ -#define RFSYS_BASE (0x40041000u) -/** Peripheral RFSYS base pointer */ -#define RFSYS ((RFSYS_Type *)RFSYS_BASE) -/** Array initializer of RFSYS peripheral base addresses */ -#define RFSYS_BASE_ADDRS { RFSYS_BASE } -/** Array initializer of RFSYS peripheral base pointers */ -#define RFSYS_BASE_PTRS { RFSYS } - -/*! - * @} - */ /* end of group RFSYS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ROM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer - * @{ - */ - -/** ROM - Register Layout Typedef */ -typedef struct { - __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ - __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ - uint8_t RESERVED_0[4028]; - __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ - __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ - __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ - __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ - __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ - __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ - __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ - __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ - __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ - __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ -} ROM_Type; - -/* ---------------------------------------------------------------------------- - -- ROM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROM_Register_Masks ROM Register Masks - * @{ - */ - -/*! @name ENTRY - Entry */ -#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) -#define ROM_ENTRY_ENTRY_SHIFT (0U) -#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) - -/* The count of ROM_ENTRY */ -#define ROM_ENTRY_COUNT (3U) - -/*! @name TABLEMARK - End of Table Marker Register */ -#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) -#define ROM_TABLEMARK_MARK_SHIFT (0U) -#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) - -/*! @name SYSACCESS - System Access Register */ -#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) -#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) -#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) - -/*! @name PERIPHID4 - Peripheral ID Register */ -#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID4_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) - -/*! @name PERIPHID5 - Peripheral ID Register */ -#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID5_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) - -/*! @name PERIPHID6 - Peripheral ID Register */ -#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID6_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) - -/*! @name PERIPHID7 - Peripheral ID Register */ -#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID7_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) - -/*! @name PERIPHID0 - Peripheral ID Register */ -#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID0_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) - -/*! @name PERIPHID1 - Peripheral ID Register */ -#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID1_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) - -/*! @name PERIPHID2 - Peripheral ID Register */ -#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID2_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) - -/*! @name PERIPHID3 - Peripheral ID Register */ -#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID3_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) - -/*! @name COMPID - Component ID Register */ -#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) -#define ROM_COMPID_COMPID_SHIFT (0U) -#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) - -/* The count of ROM_COMPID */ -#define ROM_COMPID_COUNT (4U) - - -/*! - * @} - */ /* end of group ROM_Register_Masks */ - - -/* ROM - Peripheral instance base addresses */ -/** Peripheral ROM base address */ -#define ROM_BASE (0xF0002000u) -/** Peripheral ROM base pointer */ -#define ROM ((ROM_Type *)ROM_BASE) -/** Array initializer of ROM peripheral base addresses */ -#define ROM_BASE_ADDRS { ROM_BASE } -/** Array initializer of ROM peripheral base pointers */ -#define ROM_BASE_PTRS { ROM } - -/*! - * @} - */ /* end of group ROM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RSIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RSIM_Peripheral_Access_Layer RSIM Peripheral Access Layer - * @{ - */ - -/** RSIM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< Radio System Control, offset: 0x0 */ - __IO uint32_t ACTIVE_DELAY; /**< Radio Active Early Warning, offset: 0x4 */ - __I uint32_t MAC_MSB; /**< Radio MAC Address, offset: 0x8 */ - __I uint32_t MAC_LSB; /**< Radio MAC Address, offset: 0xC */ - __IO uint32_t MISC; /**< Radio Miscellaneous, offset: 0x10 */ - uint8_t RESERVED_0[236]; - __I uint32_t DSM_TIMER; /**< Deep Sleep Timer, offset: 0x100 */ - __IO uint32_t DSM_CONTROL; /**< Deep Sleep Timer Control, offset: 0x104 */ - __IO uint32_t DSM_OSC_OFFSET; /**< Deep Sleep Wakeup Time Offset, offset: 0x108 */ - __IO uint32_t ANT_SLEEP; /**< ANT Link Layer Sleep Time, offset: 0x10C */ - __IO uint32_t ANT_WAKE; /**< ANT Link Layer Wake Time, offset: 0x110 */ - __IO uint32_t ZIG_SLEEP; /**< 802.15.4 Link Layer Sleep Time, offset: 0x114 */ - __IO uint32_t ZIG_WAKE; /**< 802.15.4 Link Layer Wake Time, offset: 0x118 */ - __IO uint32_t GEN_SLEEP; /**< Generic FSK Link Layer Sleep Time, offset: 0x11C */ - __IO uint32_t GEN_WAKE; /**< Generic FSK Link Layer Wake Time, offset: 0x120 */ - __IO uint32_t RF_OSC_CTRL; /**< Radio Oscillator Control, offset: 0x124 */ - __IO uint32_t ANA_TEST; /**< Radio Analog Test Registers, offset: 0x128 */ - __IO uint32_t ANA_TRIM; /**< Radio Analog Trim Registers, offset: 0x12C */ -} RSIM_Type; - -/* ---------------------------------------------------------------------------- - -- RSIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RSIM_Register_Masks RSIM Register Masks - * @{ - */ - -/*! @name CONTROL - Radio System Control */ -#define RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK (0x1U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT (0U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_MASK (0x2U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT (1U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_MASK) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK (0x10U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT (4U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK (0x20U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT (5U) -#define RSIM_CONTROL_BLE_RF_OSC_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK) -#define RSIM_CONTROL_RF_OSC_EN_MASK (0xF00U) -#define RSIM_CONTROL_RF_OSC_EN_SHIFT (8U) -#define RSIM_CONTROL_RF_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK (0x1000U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT (12U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK (0x2000U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT (13U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK) -#define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_MASK (0x10000U) -#define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_SHIFT (16U) -#define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_SHIFT)) & RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_MASK) -#define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_MASK (0x20000U) -#define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_SHIFT (17U) -#define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_SHIFT)) & RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_MASK) -#define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_MASK (0x40000U) -#define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_SHIFT (18U) -#define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_MASK) -#define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_MASK (0x80000U) -#define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_SHIFT (19U) -#define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_MASK) -#define RSIM_CONTROL_RSIM_DSM_EXIT_MASK (0x100000U) -#define RSIM_CONTROL_RSIM_DSM_EXIT_SHIFT (20U) -#define RSIM_CONTROL_RSIM_DSM_EXIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_DSM_EXIT_SHIFT)) & RSIM_CONTROL_RSIM_DSM_EXIT_MASK) -#define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_MASK (0x400000U) -#define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_SHIFT (22U) -#define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_SHIFT)) & RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_MASK) -#define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_MASK (0x800000U) -#define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_SHIFT (23U) -#define RSIM_CONTROL_RSIM_STOP_ACK_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_STOP_ACK_OVRD_SHIFT)) & RSIM_CONTROL_RSIM_STOP_ACK_OVRD_MASK) -#define RSIM_CONTROL_RF_OSC_READY_MASK (0x1000000U) -#define RSIM_CONTROL_RF_OSC_READY_SHIFT (24U) -#define RSIM_CONTROL_RF_OSC_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_MASK) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK (0x2000000U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT (25U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_MASK (0x4000000U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT (26U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK) -#define RSIM_CONTROL_BLOCK_SOC_RESETS_MASK (0x10000000U) -#define RSIM_CONTROL_BLOCK_SOC_RESETS_SHIFT (28U) -#define RSIM_CONTROL_BLOCK_SOC_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLOCK_SOC_RESETS_SHIFT)) & RSIM_CONTROL_BLOCK_SOC_RESETS_MASK) -#define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK (0x20000000U) -#define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT (29U) -#define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT)) & RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK) -#define RSIM_CONTROL_ALLOW_DFT_RESETS_MASK (0x40000000U) -#define RSIM_CONTROL_ALLOW_DFT_RESETS_SHIFT (30U) -#define RSIM_CONTROL_ALLOW_DFT_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_ALLOW_DFT_RESETS_SHIFT)) & RSIM_CONTROL_ALLOW_DFT_RESETS_MASK) -#define RSIM_CONTROL_RADIO_RESET_BIT_MASK (0x80000000U) -#define RSIM_CONTROL_RADIO_RESET_BIT_SHIFT (31U) -#define RSIM_CONTROL_RADIO_RESET_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RESET_BIT_SHIFT)) & RSIM_CONTROL_RADIO_RESET_BIT_MASK) - -/*! @name ACTIVE_DELAY - Radio Active Early Warning */ -#define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_MASK (0x3FU) -#define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_SHIFT (0U) -#define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_SHIFT)) & RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_MASK) -#define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_MASK (0xF0000U) -#define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_SHIFT (16U) -#define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_SHIFT)) & RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_MASK) - -/*! @name MAC_MSB - Radio MAC Address */ -#define RSIM_MAC_MSB_MAC_ADDR_MSB_MASK (0xFFU) -#define RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT (0U) -#define RSIM_MAC_MSB_MAC_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT)) & RSIM_MAC_MSB_MAC_ADDR_MSB_MASK) - -/*! @name MAC_LSB - Radio MAC Address */ -#define RSIM_MAC_LSB_MAC_ADDR_LSB_MASK (0xFFFFFFFFU) -#define RSIM_MAC_LSB_MAC_ADDR_LSB_SHIFT (0U) -#define RSIM_MAC_LSB_MAC_ADDR_LSB(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAC_LSB_MAC_ADDR_LSB_SHIFT)) & RSIM_MAC_LSB_MAC_ADDR_LSB_MASK) - -/*! @name MISC - Radio Miscellaneous */ -#define RSIM_MISC_ANALOG_TEST_EN_MASK (0x1FU) -#define RSIM_MISC_ANALOG_TEST_EN_SHIFT (0U) -#define RSIM_MISC_ANALOG_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_ANALOG_TEST_EN_SHIFT)) & RSIM_MISC_ANALOG_TEST_EN_MASK) -#define RSIM_MISC_RADIO_VERSION_MASK (0xFF000000U) -#define RSIM_MISC_RADIO_VERSION_SHIFT (24U) -#define RSIM_MISC_RADIO_VERSION(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_RADIO_VERSION_SHIFT)) & RSIM_MISC_RADIO_VERSION_MASK) - -/*! @name DSM_TIMER - Deep Sleep Timer */ -#define RSIM_DSM_TIMER_DSM_TIMER_MASK (0xFFFFFFU) -#define RSIM_DSM_TIMER_DSM_TIMER_SHIFT (0U) -#define RSIM_DSM_TIMER_DSM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK) - -/*! @name DSM_CONTROL - Deep Sleep Timer Control */ -#define RSIM_DSM_CONTROL_DSM_ANT_READY_MASK (0x1U) -#define RSIM_DSM_CONTROL_DSM_ANT_READY_SHIFT (0U) -#define RSIM_DSM_CONTROL_DSM_ANT_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ANT_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_ANT_READY_MASK) -#define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_MASK (0x2U) -#define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_SHIFT (1U) -#define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_MASK) -#define RSIM_DSM_CONTROL_DSM_ANT_FINISHED_MASK (0x4U) -#define RSIM_DSM_CONTROL_DSM_ANT_FINISHED_SHIFT (2U) -#define RSIM_DSM_CONTROL_DSM_ANT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ANT_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_ANT_FINISHED_MASK) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_MASK (0x8U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_SHIFT (3U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_MASK) -#define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_MASK (0x10U) -#define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_SHIFT (4U) -#define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_MASK) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_MASK (0x20U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_SHIFT (5U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_MASK) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_MASK (0x40U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_SHIFT (6U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_MASK) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_MASK (0x80U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_SHIFT (7U) -#define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_MASK) -#define RSIM_DSM_CONTROL_DSM_GEN_READY_MASK (0x100U) -#define RSIM_DSM_CONTROL_DSM_GEN_READY_SHIFT (8U) -#define RSIM_DSM_CONTROL_DSM_GEN_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_GEN_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_GEN_READY_MASK) -#define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_MASK (0x200U) -#define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_SHIFT (9U) -#define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_MASK) -#define RSIM_DSM_CONTROL_DSM_GEN_FINISHED_MASK (0x400U) -#define RSIM_DSM_CONTROL_DSM_GEN_FINISHED_SHIFT (10U) -#define RSIM_DSM_CONTROL_DSM_GEN_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_GEN_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_GEN_FINISHED_MASK) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_MASK (0x800U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_SHIFT (11U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_MASK) -#define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_MASK (0x1000U) -#define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_SHIFT (12U) -#define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_MASK) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_MASK (0x2000U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_SHIFT (13U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_MASK) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_MASK (0x4000U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_SHIFT (14U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_MASK) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_MASK (0x8000U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_SHIFT (15U) -#define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_MASK) -#define RSIM_DSM_CONTROL_DSM_ZIG_READY_MASK (0x10000U) -#define RSIM_DSM_CONTROL_DSM_ZIG_READY_SHIFT (16U) -#define RSIM_DSM_CONTROL_DSM_ZIG_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ZIG_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_ZIG_READY_MASK) -#define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK (0x20000U) -#define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_SHIFT (17U) -#define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) -#define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK (0x40000U) -#define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_SHIFT (18U) -#define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK (0x80000U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_SHIFT (19U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK) -#define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_MASK (0x100000U) -#define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_SHIFT (20U) -#define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_MASK) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_MASK (0x200000U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_SHIFT (21U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_MASK) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_MASK (0x400000U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_SHIFT (22U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_MASK) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_MASK (0x800000U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_SHIFT (23U) -#define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_MASK) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK (0x8000000U) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT (27U) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK (0x80000000U) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT (31U) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK) - -/*! @name DSM_OSC_OFFSET - Deep Sleep Wakeup Time Offset */ -#define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_MASK (0x3FFU) -#define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_SHIFT (0U) -#define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_SHIFT)) & RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_MASK) - -/*! @name ANT_SLEEP - ANT Link Layer Sleep Time */ -#define RSIM_ANT_SLEEP_ANT_SLEEP_TIME_MASK (0xFFFFFFU) -#define RSIM_ANT_SLEEP_ANT_SLEEP_TIME_SHIFT (0U) -#define RSIM_ANT_SLEEP_ANT_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANT_SLEEP_ANT_SLEEP_TIME_SHIFT)) & RSIM_ANT_SLEEP_ANT_SLEEP_TIME_MASK) - -/*! @name ANT_WAKE - ANT Link Layer Wake Time */ -#define RSIM_ANT_WAKE_ANT_WAKE_TIME_MASK (0xFFFFFFU) -#define RSIM_ANT_WAKE_ANT_WAKE_TIME_SHIFT (0U) -#define RSIM_ANT_WAKE_ANT_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANT_WAKE_ANT_WAKE_TIME_SHIFT)) & RSIM_ANT_WAKE_ANT_WAKE_TIME_MASK) - -/*! @name ZIG_SLEEP - 802.15.4 Link Layer Sleep Time */ -#define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_MASK (0xFFFFFFU) -#define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_SHIFT (0U) -#define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_SHIFT)) & RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_MASK) - -/*! @name ZIG_WAKE - 802.15.4 Link Layer Wake Time */ -#define RSIM_ZIG_WAKE_ZIG_WAKE_TIME_MASK (0xFFFFFFU) -#define RSIM_ZIG_WAKE_ZIG_WAKE_TIME_SHIFT (0U) -#define RSIM_ZIG_WAKE_ZIG_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ZIG_WAKE_ZIG_WAKE_TIME_SHIFT)) & RSIM_ZIG_WAKE_ZIG_WAKE_TIME_MASK) - -/*! @name GEN_SLEEP - Generic FSK Link Layer Sleep Time */ -#define RSIM_GEN_SLEEP_GEN_SLEEP_TIME_MASK (0xFFFFFFU) -#define RSIM_GEN_SLEEP_GEN_SLEEP_TIME_SHIFT (0U) -#define RSIM_GEN_SLEEP_GEN_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_GEN_SLEEP_GEN_SLEEP_TIME_SHIFT)) & RSIM_GEN_SLEEP_GEN_SLEEP_TIME_MASK) - -/*! @name GEN_WAKE - Generic FSK Link Layer Wake Time */ -#define RSIM_GEN_WAKE_GEN_WAKE_TIME_MASK (0xFFFFFFU) -#define RSIM_GEN_WAKE_GEN_WAKE_TIME_SHIFT (0U) -#define RSIM_GEN_WAKE_GEN_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_GEN_WAKE_GEN_WAKE_TIME_SHIFT)) & RSIM_GEN_WAKE_GEN_WAKE_TIME_MASK) - -/*! @name RF_OSC_CTRL - Radio Oscillator Control */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK (0x3U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT (0U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK (0x4U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT (2U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK (0x8U) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT (3U) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK (0x1F0U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT (4U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK (0x200U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT (9U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK (0x400U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT (10U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK (0x800U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT (11U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK (0x1F000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT (12U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK (0x20000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT (17U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK (0x40000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT (18U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK (0x300000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT (20U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK (0x8000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT (27U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK (0x10000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT (28U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK (0x20000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT (29U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_MASK (0x40000000U) -#define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_SHIFT (30U) -#define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_MASK (0x80000000U) -#define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_SHIFT (31U) -#define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_MASK) - -/*! @name ANA_TEST - Radio Analog Test Registers */ -#define RSIM_ANA_TEST_BB_LDO_LS_BYP_MASK (0x1U) -#define RSIM_ANA_TEST_BB_LDO_LS_BYP_SHIFT (0U) -#define RSIM_ANA_TEST_BB_LDO_LS_BYP(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_LS_BYP_SHIFT)) & RSIM_ANA_TEST_BB_LDO_LS_BYP_MASK) -#define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_MASK (0x2U) -#define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_SHIFT (1U) -#define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_MASK) -#define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_MASK (0x4U) -#define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_SHIFT (2U) -#define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_SHIFT)) & RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_MASK) -#define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_MASK (0x8U) -#define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_SHIFT (3U) -#define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_MASK) -#define RSIM_ANA_TEST_BB_XTAL_TEST_MASK (0x10U) -#define RSIM_ANA_TEST_BB_XTAL_TEST_SHIFT (4U) -#define RSIM_ANA_TEST_BB_XTAL_TEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_XTAL_TEST_SHIFT)) & RSIM_ANA_TEST_BB_XTAL_TEST_MASK) -#define RSIM_ANA_TEST_BG_DIAGBUF_MASK (0x20U) -#define RSIM_ANA_TEST_BG_DIAGBUF_SHIFT (5U) -#define RSIM_ANA_TEST_BG_DIAGBUF(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_DIAGBUF_SHIFT)) & RSIM_ANA_TEST_BG_DIAGBUF_MASK) -#define RSIM_ANA_TEST_BG_DIAGSEL_MASK (0x40U) -#define RSIM_ANA_TEST_BG_DIAGSEL_SHIFT (6U) -#define RSIM_ANA_TEST_BG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BG_DIAGSEL_MASK) -#define RSIM_ANA_TEST_BG_STARTUPFORCE_MASK (0x80U) -#define RSIM_ANA_TEST_BG_STARTUPFORCE_SHIFT (7U) -#define RSIM_ANA_TEST_BG_STARTUPFORCE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_STARTUPFORCE_SHIFT)) & RSIM_ANA_TEST_BG_STARTUPFORCE_MASK) -#define RSIM_ANA_TEST_DIAG_1234_ON_MASK (0x100U) -#define RSIM_ANA_TEST_DIAG_1234_ON_SHIFT (8U) -#define RSIM_ANA_TEST_DIAG_1234_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG_1234_ON_SHIFT)) & RSIM_ANA_TEST_DIAG_1234_ON_MASK) -#define RSIM_ANA_TEST_DIAG2SOCADC_DEC_MASK (0x600U) -#define RSIM_ANA_TEST_DIAG2SOCADC_DEC_SHIFT (9U) -#define RSIM_ANA_TEST_DIAG2SOCADC_DEC(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG2SOCADC_DEC_SHIFT)) & RSIM_ANA_TEST_DIAG2SOCADC_DEC_MASK) -#define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_MASK (0x800U) -#define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_SHIFT (11U) -#define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_SHIFT)) & RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_MASK) -#define RSIM_ANA_TEST_DIAGCODE_MASK (0x7000U) -#define RSIM_ANA_TEST_DIAGCODE_SHIFT (12U) -#define RSIM_ANA_TEST_DIAGCODE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAGCODE_SHIFT)) & RSIM_ANA_TEST_DIAGCODE_MASK) - -/*! @name ANA_TRIM - Radio Analog Trim Registers */ -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK (0x3U) -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT (0U) -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK (0x38U) -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT (3U) -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK (0xC0U) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT (6U) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK (0x700U) -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT (8U) -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK (0xF800U) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT (11U) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK (0xFF0000U) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT (16U) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK) -#define RSIM_ANA_TRIM_BG_1V_TRIM_MASK (0xF000000U) -#define RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT (24U) -#define RSIM_ANA_TRIM_BG_1V_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_1V_TRIM_MASK) -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK (0xF0000000U) -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT (28U) -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK) - - -/*! - * @} - */ /* end of group RSIM_Register_Masks */ - - -/* RSIM - Peripheral instance base addresses */ -/** Peripheral RSIM base address */ -#define RSIM_BASE (0x40059000u) -/** Peripheral RSIM base pointer */ -#define RSIM ((RSIM_Type *)RSIM_BASE) -/** Array initializer of RSIM peripheral base addresses */ -#define RSIM_BASE_ADDRS { RSIM_BASE } -/** Array initializer of RSIM peripheral base pointers */ -#define RSIM_BASE_PTRS { RSIM } - -/*! - * @} - */ /* end of group RSIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ - __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ - __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ - __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ - __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ - __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ - __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name TSR - RTC Time Seconds Register */ -#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) -#define RTC_TSR_TSR_SHIFT (0U) -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) - -/*! @name TPR - RTC Time Prescaler Register */ -#define RTC_TPR_TPR_MASK (0xFFFFU) -#define RTC_TPR_TPR_SHIFT (0U) -#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) - -/*! @name TAR - RTC Time Alarm Register */ -#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) -#define RTC_TAR_TAR_SHIFT (0U) -#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) - -/*! @name TCR - RTC Time Compensation Register */ -#define RTC_TCR_TCR_MASK (0xFFU) -#define RTC_TCR_TCR_SHIFT (0U) -#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) -#define RTC_TCR_CIR_MASK (0xFF00U) -#define RTC_TCR_CIR_SHIFT (8U) -#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) -#define RTC_TCR_TCV_MASK (0xFF0000U) -#define RTC_TCR_TCV_SHIFT (16U) -#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) -#define RTC_TCR_CIC_MASK (0xFF000000U) -#define RTC_TCR_CIC_SHIFT (24U) -#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) - -/*! @name CR - RTC Control Register */ -#define RTC_CR_SWR_MASK (0x1U) -#define RTC_CR_SWR_SHIFT (0U) -#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) -#define RTC_CR_WPE_MASK (0x2U) -#define RTC_CR_WPE_SHIFT (1U) -#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) -#define RTC_CR_SUP_MASK (0x4U) -#define RTC_CR_SUP_SHIFT (2U) -#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) -#define RTC_CR_UM_MASK (0x8U) -#define RTC_CR_UM_SHIFT (3U) -#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) -#define RTC_CR_WPS_MASK (0x10U) -#define RTC_CR_WPS_SHIFT (4U) -#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) -#define RTC_CR_OSCE_MASK (0x100U) -#define RTC_CR_OSCE_SHIFT (8U) -#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) -#define RTC_CR_CLKO_MASK (0x200U) -#define RTC_CR_CLKO_SHIFT (9U) -#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) -#define RTC_CR_SC16P_MASK (0x400U) -#define RTC_CR_SC16P_SHIFT (10U) -#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) -#define RTC_CR_SC8P_MASK (0x800U) -#define RTC_CR_SC8P_SHIFT (11U) -#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) -#define RTC_CR_SC4P_MASK (0x1000U) -#define RTC_CR_SC4P_SHIFT (12U) -#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) -#define RTC_CR_SC2P_MASK (0x2000U) -#define RTC_CR_SC2P_SHIFT (13U) -#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) - -/*! @name SR - RTC Status Register */ -#define RTC_SR_TIF_MASK (0x1U) -#define RTC_SR_TIF_SHIFT (0U) -#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) -#define RTC_SR_TOF_MASK (0x2U) -#define RTC_SR_TOF_SHIFT (1U) -#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) -#define RTC_SR_TAF_MASK (0x4U) -#define RTC_SR_TAF_SHIFT (2U) -#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) -#define RTC_SR_TCE_MASK (0x10U) -#define RTC_SR_TCE_SHIFT (4U) -#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) - -/*! @name LR - RTC Lock Register */ -#define RTC_LR_TCL_MASK (0x8U) -#define RTC_LR_TCL_SHIFT (3U) -#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) -#define RTC_LR_CRL_MASK (0x10U) -#define RTC_LR_CRL_SHIFT (4U) -#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) -#define RTC_LR_SRL_MASK (0x20U) -#define RTC_LR_SRL_SHIFT (5U) -#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) -#define RTC_LR_LRL_MASK (0x40U) -#define RTC_LR_LRL_SHIFT (6U) -#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) - -/*! @name IER - RTC Interrupt Enable Register */ -#define RTC_IER_TIIE_MASK (0x1U) -#define RTC_IER_TIIE_SHIFT (0U) -#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) -#define RTC_IER_TOIE_MASK (0x2U) -#define RTC_IER_TOIE_SHIFT (1U) -#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) -#define RTC_IER_TAIE_MASK (0x4U) -#define RTC_IER_TAIE_SHIFT (2U) -#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) -#define RTC_IER_TSIE_MASK (0x10U) -#define RTC_IER_TSIE_SHIFT (4U) -#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) -#define RTC_IER_WPON_MASK (0x80U) -#define RTC_IER_WPON_SHIFT (7U) -#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x4003D000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } -#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer - * @{ - */ - -/** SIM - Register Layout Typedef */ -typedef struct { - __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ - uint8_t RESERVED_0[4096]; - __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ - __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ - uint8_t RESERVED_2[4]; - __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ - uint8_t RESERVED_3[8]; - __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ - uint8_t RESERVED_4[12]; - __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ - __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ - __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ - __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ - __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ - uint8_t RESERVED_5[4]; - __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ - __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ - uint8_t RESERVED_6[4]; - __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ - __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ - __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ - uint8_t RESERVED_7[156]; - __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ - __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */ -} SIM_Type; - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/*! @name SOPT1 - System Options Register 1 */ -#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U) -#define SIM_SOPT1_OSC32KOUT_SHIFT (16U) -#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK) -#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) -#define SIM_SOPT1_OSC32KSEL_SHIFT (18U) -#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) - -/*! @name SOPT2 - System Options Register 2 */ -#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) -#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) -#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) -#define SIM_SOPT2_TPMSRC_MASK (0x3000000U) -#define SIM_SOPT2_TPMSRC_SHIFT (24U) -#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) -#define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U) -#define SIM_SOPT2_LPUART0SRC_SHIFT (26U) -#define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK) - -/*! @name SOPT4 - System Options Register 4 */ -#define SIM_SOPT4_TPM1CH0SRC_MASK (0x40000U) -#define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U) -#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK) -#define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U) -#define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U) -#define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK) -#define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U) -#define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U) -#define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK) -#define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U) -#define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U) -#define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK) -#define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U) -#define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U) -#define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK) - -/*! @name SOPT5 - System Options Register 5 */ -#define SIM_SOPT5_LPUART0TXSRC_MASK (0x3U) -#define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U) -#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK) -#define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U) -#define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U) -#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK) -#define SIM_SOPT5_LPUART0ODE_MASK (0x10000U) -#define SIM_SOPT5_LPUART0ODE_SHIFT (16U) -#define SIM_SOPT5_LPUART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK) - -/*! @name SOPT7 - System Options Register 7 */ -#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) -#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) -#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) -#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) -#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) -#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) -#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) -#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) -#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) - -/*! @name SDID - System Device Identification Register */ -#define SIM_SDID_PINID_MASK (0xFU) -#define SIM_SDID_PINID_SHIFT (0U) -#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) -#define SIM_SDID_DIEID_MASK (0xF80U) -#define SIM_SDID_DIEID_SHIFT (7U) -#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) -#define SIM_SDID_REVID_MASK (0xF000U) -#define SIM_SDID_REVID_SHIFT (12U) -#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) -#define SIM_SDID_SRAMSIZE_MASK (0xF0000U) -#define SIM_SDID_SRAMSIZE_SHIFT (16U) -#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) -#define SIM_SDID_SERIESID_MASK (0xF00000U) -#define SIM_SDID_SERIESID_SHIFT (20U) -#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) -#define SIM_SDID_SUBFAMID_MASK (0x3000000U) -#define SIM_SDID_SUBFAMID_SHIFT (24U) -#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) -#define SIM_SDID_FAMID_MASK (0xF0000000U) -#define SIM_SDID_FAMID_SHIFT (28U) -#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) - -/*! @name SCGC4 - System Clock Gating Control Register 4 */ -#define SIM_SCGC4_CMT_MASK (0x4U) -#define SIM_SCGC4_CMT_SHIFT (2U) -#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) -#define SIM_SCGC4_I2C0_MASK (0x40U) -#define SIM_SCGC4_I2C0_SHIFT (6U) -#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) -#define SIM_SCGC4_I2C1_MASK (0x80U) -#define SIM_SCGC4_I2C1_SHIFT (7U) -#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) -#define SIM_SCGC4_CMP_MASK (0x80000U) -#define SIM_SCGC4_CMP_SHIFT (19U) -#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) -#define SIM_SCGC4_VREF_MASK (0x100000U) -#define SIM_SCGC4_VREF_SHIFT (20U) -#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) - -/*! @name SCGC5 - System Clock Gating Control Register 5 */ -#define SIM_SCGC5_LPTMR_MASK (0x1U) -#define SIM_SCGC5_LPTMR_SHIFT (0U) -#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) -#define SIM_SCGC5_TSI_MASK (0x20U) -#define SIM_SCGC5_TSI_SHIFT (5U) -#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK) -#define SIM_SCGC5_PORTA_MASK (0x200U) -#define SIM_SCGC5_PORTA_SHIFT (9U) -#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) -#define SIM_SCGC5_PORTB_MASK (0x400U) -#define SIM_SCGC5_PORTB_SHIFT (10U) -#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) -#define SIM_SCGC5_PORTC_MASK (0x800U) -#define SIM_SCGC5_PORTC_SHIFT (11U) -#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) -#define SIM_SCGC5_LPUART0_MASK (0x100000U) -#define SIM_SCGC5_LPUART0_SHIFT (20U) -#define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK) -#define SIM_SCGC5_LTC_MASK (0x1000000U) -#define SIM_SCGC5_LTC_SHIFT (24U) -#define SIM_SCGC5_LTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LTC_SHIFT)) & SIM_SCGC5_LTC_MASK) -#define SIM_SCGC5_RSIM_MASK (0x2000000U) -#define SIM_SCGC5_RSIM_SHIFT (25U) -#define SIM_SCGC5_RSIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_RSIM_SHIFT)) & SIM_SCGC5_RSIM_MASK) -#define SIM_SCGC5_DCDC_MASK (0x4000000U) -#define SIM_SCGC5_DCDC_SHIFT (26U) -#define SIM_SCGC5_DCDC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_DCDC_SHIFT)) & SIM_SCGC5_DCDC_MASK) -#define SIM_SCGC5_BTLL_MASK (0x8000000U) -#define SIM_SCGC5_BTLL_SHIFT (27U) -#define SIM_SCGC5_BTLL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_BTLL_SHIFT)) & SIM_SCGC5_BTLL_MASK) -#define SIM_SCGC5_PHYDIG_MASK (0x10000000U) -#define SIM_SCGC5_PHYDIG_SHIFT (28U) -#define SIM_SCGC5_PHYDIG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PHYDIG_SHIFT)) & SIM_SCGC5_PHYDIG_MASK) -#define SIM_SCGC5_ZigBee_MASK (0x20000000U) -#define SIM_SCGC5_ZigBee_SHIFT (29U) -#define SIM_SCGC5_ZigBee(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ZigBee_SHIFT)) & SIM_SCGC5_ZigBee_MASK) -#define SIM_SCGC5_ANT_MASK (0x40000000U) -#define SIM_SCGC5_ANT_SHIFT (30U) -#define SIM_SCGC5_ANT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ANT_SHIFT)) & SIM_SCGC5_ANT_MASK) -#define SIM_SCGC5_GEN_FSK_MASK (0x80000000U) -#define SIM_SCGC5_GEN_FSK_SHIFT (31U) -#define SIM_SCGC5_GEN_FSK(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_GEN_FSK_SHIFT)) & SIM_SCGC5_GEN_FSK_MASK) - -/*! @name SCGC6 - System Clock Gating Control Register 6 */ -#define SIM_SCGC6_FTF_MASK (0x1U) -#define SIM_SCGC6_FTF_SHIFT (0U) -#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) -#define SIM_SCGC6_DMAMUX_MASK (0x2U) -#define SIM_SCGC6_DMAMUX_SHIFT (1U) -#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) -#define SIM_SCGC6_TRNG_MASK (0x200U) -#define SIM_SCGC6_TRNG_SHIFT (9U) -#define SIM_SCGC6_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TRNG_SHIFT)) & SIM_SCGC6_TRNG_MASK) -#define SIM_SCGC6_SPI0_MASK (0x1000U) -#define SIM_SCGC6_SPI0_SHIFT (12U) -#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) -#define SIM_SCGC6_SPI1_MASK (0x2000U) -#define SIM_SCGC6_SPI1_SHIFT (13U) -#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) -#define SIM_SCGC6_PIT_MASK (0x800000U) -#define SIM_SCGC6_PIT_SHIFT (23U) -#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) -#define SIM_SCGC6_TPM0_MASK (0x1000000U) -#define SIM_SCGC6_TPM0_SHIFT (24U) -#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK) -#define SIM_SCGC6_TPM1_MASK (0x2000000U) -#define SIM_SCGC6_TPM1_SHIFT (25U) -#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK) -#define SIM_SCGC6_TPM2_MASK (0x4000000U) -#define SIM_SCGC6_TPM2_SHIFT (26U) -#define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK) -#define SIM_SCGC6_ADC0_MASK (0x8000000U) -#define SIM_SCGC6_ADC0_SHIFT (27U) -#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) -#define SIM_SCGC6_RTC_MASK (0x20000000U) -#define SIM_SCGC6_RTC_SHIFT (29U) -#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) -#define SIM_SCGC6_DAC0_MASK (0x80000000U) -#define SIM_SCGC6_DAC0_SHIFT (31U) -#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) - -/*! @name SCGC7 - System Clock Gating Control Register 7 */ -#define SIM_SCGC7_DMA_MASK (0x100U) -#define SIM_SCGC7_DMA_SHIFT (8U) -#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) - -/*! @name CLKDIV1 - System Clock Divider Register 1 */ -#define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U) -#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) -#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) -#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) -#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) -#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) - -/*! @name FCFG1 - Flash Configuration Register 1 */ -#define SIM_FCFG1_FLASHDIS_MASK (0x1U) -#define SIM_FCFG1_FLASHDIS_SHIFT (0U) -#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) -#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) -#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) -#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) -#define SIM_FCFG1_PFSIZE_MASK (0xF000000U) -#define SIM_FCFG1_PFSIZE_SHIFT (24U) -#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) - -/*! @name FCFG2 - Flash Configuration Register 2 */ -#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) -#define SIM_FCFG2_MAXADDR1_SHIFT (16U) -#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) -#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) -#define SIM_FCFG2_MAXADDR0_SHIFT (24U) -#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) - -/*! @name UIDMH - Unique Identification Register Mid-High */ -#define SIM_UIDMH_UID_MASK (0xFFFFU) -#define SIM_UIDMH_UID_SHIFT (0U) -#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) - -/*! @name UIDML - Unique Identification Register Mid Low */ -#define SIM_UIDML_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDML_UID_SHIFT (0U) -#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) - -/*! @name UIDL - Unique Identification Register Low */ -#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDL_UID_SHIFT (0U) -#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) - -/*! @name COPC - COP Control Register */ -#define SIM_COPC_COPW_MASK (0x1U) -#define SIM_COPC_COPW_SHIFT (0U) -#define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK) -#define SIM_COPC_COPCLKS_MASK (0x2U) -#define SIM_COPC_COPCLKS_SHIFT (1U) -#define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK) -#define SIM_COPC_COPT_MASK (0xCU) -#define SIM_COPC_COPT_SHIFT (2U) -#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK) -#define SIM_COPC_COPSTPEN_MASK (0x10U) -#define SIM_COPC_COPSTPEN_SHIFT (4U) -#define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK) -#define SIM_COPC_COPDBGEN_MASK (0x20U) -#define SIM_COPC_COPDBGEN_SHIFT (5U) -#define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK) -#define SIM_COPC_COPCLKSEL_MASK (0xC0U) -#define SIM_COPC_COPCLKSEL_SHIFT (6U) -#define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK) - -/*! @name SRVCOP - Service COP */ -#define SIM_SRVCOP_SRVCOP_MASK (0xFFU) -#define SIM_SRVCOP_SRVCOP_SHIFT (0U) -#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK) - - -/*! - * @} - */ /* end of group SIM_Register_Masks */ - - -/* SIM - Peripheral instance base addresses */ -/** Peripheral SIM base address */ -#define SIM_BASE (0x40047000u) -/** Peripheral SIM base pointer */ -#define SIM ((SIM_Type *)SIM_BASE) -/** Array initializer of SIM peripheral base addresses */ -#define SIM_BASE_ADDRS { SIM_BASE } -/** Array initializer of SIM peripheral base pointers */ -#define SIM_BASE_PTRS { SIM } - -/*! - * @} - */ /* end of group SIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer - * @{ - */ - -/** SMC - Register Layout Typedef */ -typedef struct { - __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ - __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ - __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ - __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ -} SMC_Type; - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/*! @name PMPROT - Power Mode Protection register */ -#define SMC_PMPROT_AVLLS_MASK (0x2U) -#define SMC_PMPROT_AVLLS_SHIFT (1U) -#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) -#define SMC_PMPROT_ALLS_MASK (0x8U) -#define SMC_PMPROT_ALLS_SHIFT (3U) -#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) -#define SMC_PMPROT_AVLP_MASK (0x20U) -#define SMC_PMPROT_AVLP_SHIFT (5U) -#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) - -/*! @name PMCTRL - Power Mode Control register */ -#define SMC_PMCTRL_STOPM_MASK (0x7U) -#define SMC_PMCTRL_STOPM_SHIFT (0U) -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) -#define SMC_PMCTRL_STOPA_MASK (0x8U) -#define SMC_PMCTRL_STOPA_SHIFT (3U) -#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) -#define SMC_PMCTRL_RUNM_MASK (0x60U) -#define SMC_PMCTRL_RUNM_SHIFT (5U) -#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) - -/*! @name STOPCTRL - Stop Control Register */ -#define SMC_STOPCTRL_LLSM_MASK (0x7U) -#define SMC_STOPCTRL_LLSM_SHIFT (0U) -#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK) -#define SMC_STOPCTRL_RAM2PO_MASK (0x10U) -#define SMC_STOPCTRL_RAM2PO_SHIFT (4U) -#define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK) -#define SMC_STOPCTRL_PORPO_MASK (0x20U) -#define SMC_STOPCTRL_PORPO_SHIFT (5U) -#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) -#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) -#define SMC_STOPCTRL_PSTOPO_SHIFT (6U) -#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) - -/*! @name PMSTAT - Power Mode Status register */ -#define SMC_PMSTAT_PMSTAT_MASK (0xFFU) -#define SMC_PMSTAT_PMSTAT_SHIFT (0U) -#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) - - -/*! - * @} - */ /* end of group SMC_Register_Masks */ - - -/* SMC - Peripheral instance base addresses */ -/** Peripheral SMC base address */ -#define SMC_BASE (0x4007E000u) -/** Peripheral SMC base pointer */ -#define SMC ((SMC_Type *)SMC_BASE) -/** Array initializer of SMC peripheral base addresses */ -#define SMC_BASE_ADDRS { SMC_BASE } -/** Array initializer of SMC peripheral base pointers */ -#define SMC_BASE_PTRS { SMC } - -/*! - * @} - */ /* end of group SMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ - __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ - }; - uint8_t RESERVED_1[24]; - __IO uint32_t SR; /**< Status Register, offset: 0x2C */ - __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ - union { /* offset: 0x34 */ - __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ - __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ - }; - __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ - __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ - __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ - __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ - __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ - uint8_t RESERVED_2[48]; - __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ - __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ - __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ - __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name MCR - Module Configuration Register */ -#define SPI_MCR_HALT_MASK (0x1U) -#define SPI_MCR_HALT_SHIFT (0U) -#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) -#define SPI_MCR_SMPL_PT_MASK (0x300U) -#define SPI_MCR_SMPL_PT_SHIFT (8U) -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) -#define SPI_MCR_CLR_RXF_MASK (0x400U) -#define SPI_MCR_CLR_RXF_SHIFT (10U) -#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) -#define SPI_MCR_CLR_TXF_MASK (0x800U) -#define SPI_MCR_CLR_TXF_SHIFT (11U) -#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) -#define SPI_MCR_DIS_RXF_MASK (0x1000U) -#define SPI_MCR_DIS_RXF_SHIFT (12U) -#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) -#define SPI_MCR_DIS_TXF_MASK (0x2000U) -#define SPI_MCR_DIS_TXF_SHIFT (13U) -#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) -#define SPI_MCR_MDIS_MASK (0x4000U) -#define SPI_MCR_MDIS_SHIFT (14U) -#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) -#define SPI_MCR_DOZE_MASK (0x8000U) -#define SPI_MCR_DOZE_SHIFT (15U) -#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) -#define SPI_MCR_PCSIS_MASK (0xF0000U) -#define SPI_MCR_PCSIS_SHIFT (16U) -#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) -#define SPI_MCR_ROOE_MASK (0x1000000U) -#define SPI_MCR_ROOE_SHIFT (24U) -#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) -#define SPI_MCR_MTFE_MASK (0x4000000U) -#define SPI_MCR_MTFE_SHIFT (26U) -#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) -#define SPI_MCR_FRZ_MASK (0x8000000U) -#define SPI_MCR_FRZ_SHIFT (27U) -#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) -#define SPI_MCR_DCONF_MASK (0x30000000U) -#define SPI_MCR_DCONF_SHIFT (28U) -#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) -#define SPI_MCR_CONT_SCKE_MASK (0x40000000U) -#define SPI_MCR_CONT_SCKE_SHIFT (30U) -#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) -#define SPI_MCR_MSTR_MASK (0x80000000U) -#define SPI_MCR_MSTR_SHIFT (31U) -#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) - -/*! @name TCR - Transfer Count Register */ -#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) -#define SPI_TCR_SPI_TCNT_SHIFT (16U) -#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) - -/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ -#define SPI_CTAR_BR_MASK (0xFU) -#define SPI_CTAR_BR_SHIFT (0U) -#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) -#define SPI_CTAR_DT_MASK (0xF0U) -#define SPI_CTAR_DT_SHIFT (4U) -#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) -#define SPI_CTAR_ASC_MASK (0xF00U) -#define SPI_CTAR_ASC_SHIFT (8U) -#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) -#define SPI_CTAR_CSSCK_MASK (0xF000U) -#define SPI_CTAR_CSSCK_SHIFT (12U) -#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) -#define SPI_CTAR_PBR_MASK (0x30000U) -#define SPI_CTAR_PBR_SHIFT (16U) -#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) -#define SPI_CTAR_PDT_MASK (0xC0000U) -#define SPI_CTAR_PDT_SHIFT (18U) -#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) -#define SPI_CTAR_PASC_MASK (0x300000U) -#define SPI_CTAR_PASC_SHIFT (20U) -#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) -#define SPI_CTAR_PCSSCK_MASK (0xC00000U) -#define SPI_CTAR_PCSSCK_SHIFT (22U) -#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) -#define SPI_CTAR_LSBFE_MASK (0x1000000U) -#define SPI_CTAR_LSBFE_SHIFT (24U) -#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) -#define SPI_CTAR_CPHA_MASK (0x2000000U) -#define SPI_CTAR_CPHA_SHIFT (25U) -#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) -#define SPI_CTAR_CPOL_MASK (0x4000000U) -#define SPI_CTAR_CPOL_SHIFT (26U) -#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) -#define SPI_CTAR_FMSZ_MASK (0x78000000U) -#define SPI_CTAR_FMSZ_SHIFT (27U) -#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) -#define SPI_CTAR_DBR_MASK (0x80000000U) -#define SPI_CTAR_DBR_SHIFT (31U) -#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) - -/* The count of SPI_CTAR */ -#define SPI_CTAR_COUNT (2U) - -/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ -#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) -#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) -#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) -#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) -#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) -#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) -#define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U) -#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) -#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) - -/* The count of SPI_CTAR_SLAVE */ -#define SPI_CTAR_SLAVE_COUNT (1U) - -/*! @name SR - Status Register */ -#define SPI_SR_POPNXTPTR_MASK (0xFU) -#define SPI_SR_POPNXTPTR_SHIFT (0U) -#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) -#define SPI_SR_RXCTR_MASK (0xF0U) -#define SPI_SR_RXCTR_SHIFT (4U) -#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) -#define SPI_SR_TXNXTPTR_MASK (0xF00U) -#define SPI_SR_TXNXTPTR_SHIFT (8U) -#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) -#define SPI_SR_TXCTR_MASK (0xF000U) -#define SPI_SR_TXCTR_SHIFT (12U) -#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) -#define SPI_SR_RFDF_MASK (0x20000U) -#define SPI_SR_RFDF_SHIFT (17U) -#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) -#define SPI_SR_RFOF_MASK (0x80000U) -#define SPI_SR_RFOF_SHIFT (19U) -#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) -#define SPI_SR_TFFF_MASK (0x2000000U) -#define SPI_SR_TFFF_SHIFT (25U) -#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) -#define SPI_SR_TFUF_MASK (0x8000000U) -#define SPI_SR_TFUF_SHIFT (27U) -#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) -#define SPI_SR_EOQF_MASK (0x10000000U) -#define SPI_SR_EOQF_SHIFT (28U) -#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) -#define SPI_SR_TXRXS_MASK (0x40000000U) -#define SPI_SR_TXRXS_SHIFT (30U) -#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) -#define SPI_SR_TCF_MASK (0x80000000U) -#define SPI_SR_TCF_SHIFT (31U) -#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) - -/*! @name RSER - DMA/Interrupt Request Select and Enable Register */ -#define SPI_RSER_RFDF_DIRS_MASK (0x10000U) -#define SPI_RSER_RFDF_DIRS_SHIFT (16U) -#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) -#define SPI_RSER_RFDF_RE_MASK (0x20000U) -#define SPI_RSER_RFDF_RE_SHIFT (17U) -#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) -#define SPI_RSER_RFOF_RE_MASK (0x80000U) -#define SPI_RSER_RFOF_RE_SHIFT (19U) -#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) -#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) -#define SPI_RSER_TFFF_DIRS_SHIFT (24U) -#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) -#define SPI_RSER_TFFF_RE_MASK (0x2000000U) -#define SPI_RSER_TFFF_RE_SHIFT (25U) -#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) -#define SPI_RSER_TFUF_RE_MASK (0x8000000U) -#define SPI_RSER_TFUF_RE_SHIFT (27U) -#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) -#define SPI_RSER_EOQF_RE_MASK (0x10000000U) -#define SPI_RSER_EOQF_RE_SHIFT (28U) -#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) -#define SPI_RSER_TCF_RE_MASK (0x80000000U) -#define SPI_RSER_TCF_RE_SHIFT (31U) -#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) - -/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ -#define SPI_PUSHR_TXDATA_MASK (0xFFFFU) -#define SPI_PUSHR_TXDATA_SHIFT (0U) -#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) -#define SPI_PUSHR_PCS_MASK (0xF0000U) -#define SPI_PUSHR_PCS_SHIFT (16U) -#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) -#define SPI_PUSHR_CTCNT_MASK (0x4000000U) -#define SPI_PUSHR_CTCNT_SHIFT (26U) -#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) -#define SPI_PUSHR_EOQ_MASK (0x8000000U) -#define SPI_PUSHR_EOQ_SHIFT (27U) -#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) -#define SPI_PUSHR_CTAS_MASK (0x70000000U) -#define SPI_PUSHR_CTAS_SHIFT (28U) -#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) -#define SPI_PUSHR_CONT_MASK (0x80000000U) -#define SPI_PUSHR_CONT_SHIFT (31U) -#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) - -/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ -#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU) -#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) -#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) - -/*! @name POPR - POP RX FIFO Register */ -#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_POPR_RXDATA_SHIFT (0U) -#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) - -/*! @name TXFR0 - Transmit FIFO Registers */ -#define SPI_TXFR0_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR0_TXDATA_SHIFT (0U) -#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) -#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) - -/*! @name TXFR1 - Transmit FIFO Registers */ -#define SPI_TXFR1_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR1_TXDATA_SHIFT (0U) -#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) -#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) - -/*! @name TXFR2 - Transmit FIFO Registers */ -#define SPI_TXFR2_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR2_TXDATA_SHIFT (0U) -#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) -#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) - -/*! @name TXFR3 - Transmit FIFO Registers */ -#define SPI_TXFR3_TXDATA_MASK (0xFFFFU) -#define SPI_TXFR3_TXDATA_SHIFT (0U) -#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) -#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) -#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) -#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) - -/*! @name RXFR0 - Receive FIFO Registers */ -#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR0_RXDATA_SHIFT (0U) -#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) - -/*! @name RXFR1 - Receive FIFO Registers */ -#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR1_RXDATA_SHIFT (0U) -#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) - -/*! @name RXFR2 - Receive FIFO Registers */ -#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR2_RXDATA_SHIFT (0U) -#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) - -/*! @name RXFR3 - Receive FIFO Registers */ -#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) -#define SPI_RXFR3_RXDATA_SHIFT (0U) -#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -/** Peripheral SPI0 base address */ -#define SPI0_BASE (0x4002C000u) -/** Peripheral SPI0 base pointer */ -#define SPI0 ((SPI_Type *)SPI0_BASE) -/** Peripheral SPI1 base address */ -#define SPI1_BASE (0x4002D000u) -/** Peripheral SPI1 base pointer */ -#define SPI1 ((SPI_Type *)SPI1_BASE) -/** Array initializer of SPI peripheral base addresses */ -#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } -/** Array initializer of SPI peripheral base pointers */ -#define SPI_BASE_PTRS { SPI0, SPI1 } -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TPM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer - * @{ - */ - -/** TPM - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ - __IO uint32_t CNT; /**< Counter, offset: 0x4 */ - __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ - struct { /* offset: 0xC, array step: 0x8 */ - __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ - __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ - } CONTROLS[4]; - uint8_t RESERVED_0[36]; - __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ - uint8_t RESERVED_1[16]; - __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */ - uint8_t RESERVED_2[8]; - __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ - uint8_t RESERVED_4[4]; - __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ - __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ -} TPM_Type; - -/* ---------------------------------------------------------------------------- - -- TPM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TPM_Register_Masks TPM Register Masks - * @{ - */ - -/*! @name SC - Status and Control */ -#define TPM_SC_PS_MASK (0x7U) -#define TPM_SC_PS_SHIFT (0U) -#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) -#define TPM_SC_CMOD_MASK (0x18U) -#define TPM_SC_CMOD_SHIFT (3U) -#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) -#define TPM_SC_CPWMS_MASK (0x20U) -#define TPM_SC_CPWMS_SHIFT (5U) -#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) -#define TPM_SC_TOIE_MASK (0x40U) -#define TPM_SC_TOIE_SHIFT (6U) -#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) -#define TPM_SC_TOF_MASK (0x80U) -#define TPM_SC_TOF_SHIFT (7U) -#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) -#define TPM_SC_DMA_MASK (0x100U) -#define TPM_SC_DMA_SHIFT (8U) -#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) - -/*! @name CNT - Counter */ -#define TPM_CNT_COUNT_MASK (0xFFFFU) -#define TPM_CNT_COUNT_SHIFT (0U) -#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) - -/*! @name MOD - Modulo */ -#define TPM_MOD_MOD_MASK (0xFFFFU) -#define TPM_MOD_MOD_SHIFT (0U) -#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) - -/*! @name CnSC - Channel (n) Status and Control */ -#define TPM_CnSC_DMA_MASK (0x1U) -#define TPM_CnSC_DMA_SHIFT (0U) -#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) -#define TPM_CnSC_ELSA_MASK (0x4U) -#define TPM_CnSC_ELSA_SHIFT (2U) -#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) -#define TPM_CnSC_ELSB_MASK (0x8U) -#define TPM_CnSC_ELSB_SHIFT (3U) -#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) -#define TPM_CnSC_MSA_MASK (0x10U) -#define TPM_CnSC_MSA_SHIFT (4U) -#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) -#define TPM_CnSC_MSB_MASK (0x20U) -#define TPM_CnSC_MSB_SHIFT (5U) -#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) -#define TPM_CnSC_CHIE_MASK (0x40U) -#define TPM_CnSC_CHIE_SHIFT (6U) -#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) -#define TPM_CnSC_CHF_MASK (0x80U) -#define TPM_CnSC_CHF_SHIFT (7U) -#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) - -/* The count of TPM_CnSC */ -#define TPM_CnSC_COUNT (4U) - -/*! @name CnV - Channel (n) Value */ -#define TPM_CnV_VAL_MASK (0xFFFFU) -#define TPM_CnV_VAL_SHIFT (0U) -#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) - -/* The count of TPM_CnV */ -#define TPM_CnV_COUNT (4U) - -/*! @name STATUS - Capture and Compare Status */ -#define TPM_STATUS_CH0F_MASK (0x1U) -#define TPM_STATUS_CH0F_SHIFT (0U) -#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) -#define TPM_STATUS_CH1F_MASK (0x2U) -#define TPM_STATUS_CH1F_SHIFT (1U) -#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) -#define TPM_STATUS_CH2F_MASK (0x4U) -#define TPM_STATUS_CH2F_SHIFT (2U) -#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) -#define TPM_STATUS_CH3F_MASK (0x8U) -#define TPM_STATUS_CH3F_SHIFT (3U) -#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) -#define TPM_STATUS_TOF_MASK (0x100U) -#define TPM_STATUS_TOF_SHIFT (8U) -#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) - -/*! @name COMBINE - Combine Channel Register */ -#define TPM_COMBINE_COMBINE0_MASK (0x1U) -#define TPM_COMBINE_COMBINE0_SHIFT (0U) -#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) -#define TPM_COMBINE_COMSWAP0_MASK (0x2U) -#define TPM_COMBINE_COMSWAP0_SHIFT (1U) -#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) -#define TPM_COMBINE_COMBINE1_MASK (0x100U) -#define TPM_COMBINE_COMBINE1_SHIFT (8U) -#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) -#define TPM_COMBINE_COMSWAP1_MASK (0x200U) -#define TPM_COMBINE_COMSWAP1_SHIFT (9U) -#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) - -/*! @name POL - Channel Polarity */ -#define TPM_POL_POL0_MASK (0x1U) -#define TPM_POL_POL0_SHIFT (0U) -#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) -#define TPM_POL_POL1_MASK (0x2U) -#define TPM_POL_POL1_SHIFT (1U) -#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) -#define TPM_POL_POL2_MASK (0x4U) -#define TPM_POL_POL2_SHIFT (2U) -#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) -#define TPM_POL_POL3_MASK (0x8U) -#define TPM_POL_POL3_SHIFT (3U) -#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) - -/*! @name FILTER - Filter Control */ -#define TPM_FILTER_CH0FVAL_MASK (0xFU) -#define TPM_FILTER_CH0FVAL_SHIFT (0U) -#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) -#define TPM_FILTER_CH1FVAL_MASK (0xF0U) -#define TPM_FILTER_CH1FVAL_SHIFT (4U) -#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) -#define TPM_FILTER_CH2FVAL_MASK (0xF00U) -#define TPM_FILTER_CH2FVAL_SHIFT (8U) -#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) -#define TPM_FILTER_CH3FVAL_MASK (0xF000U) -#define TPM_FILTER_CH3FVAL_SHIFT (12U) -#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) - -/*! @name QDCTRL - Quadrature Decoder Control and Status */ -#define TPM_QDCTRL_QUADEN_MASK (0x1U) -#define TPM_QDCTRL_QUADEN_SHIFT (0U) -#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) -#define TPM_QDCTRL_TOFDIR_MASK (0x2U) -#define TPM_QDCTRL_TOFDIR_SHIFT (1U) -#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) -#define TPM_QDCTRL_QUADIR_MASK (0x4U) -#define TPM_QDCTRL_QUADIR_SHIFT (2U) -#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) -#define TPM_QDCTRL_QUADMODE_MASK (0x8U) -#define TPM_QDCTRL_QUADMODE_SHIFT (3U) -#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) - -/*! @name CONF - Configuration */ -#define TPM_CONF_DOZEEN_MASK (0x20U) -#define TPM_CONF_DOZEEN_SHIFT (5U) -#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) -#define TPM_CONF_DBGMODE_MASK (0xC0U) -#define TPM_CONF_DBGMODE_SHIFT (6U) -#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) -#define TPM_CONF_GTBSYNC_MASK (0x100U) -#define TPM_CONF_GTBSYNC_SHIFT (8U) -#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) -#define TPM_CONF_GTBEEN_MASK (0x200U) -#define TPM_CONF_GTBEEN_SHIFT (9U) -#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) -#define TPM_CONF_CSOT_MASK (0x10000U) -#define TPM_CONF_CSOT_SHIFT (16U) -#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) -#define TPM_CONF_CSOO_MASK (0x20000U) -#define TPM_CONF_CSOO_SHIFT (17U) -#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) -#define TPM_CONF_CROT_MASK (0x40000U) -#define TPM_CONF_CROT_SHIFT (18U) -#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) -#define TPM_CONF_CPOT_MASK (0x80000U) -#define TPM_CONF_CPOT_SHIFT (19U) -#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) -#define TPM_CONF_TRGPOL_MASK (0x400000U) -#define TPM_CONF_TRGPOL_SHIFT (22U) -#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) -#define TPM_CONF_TRGSRC_MASK (0x800000U) -#define TPM_CONF_TRGSRC_SHIFT (23U) -#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) -#define TPM_CONF_TRGSEL_MASK (0xF000000U) -#define TPM_CONF_TRGSEL_SHIFT (24U) -#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) - - -/*! - * @} - */ /* end of group TPM_Register_Masks */ - - -/* TPM - Peripheral instance base addresses */ -/** Peripheral TPM0 base address */ -#define TPM0_BASE (0x40038000u) -/** Peripheral TPM0 base pointer */ -#define TPM0 ((TPM_Type *)TPM0_BASE) -/** Peripheral TPM1 base address */ -#define TPM1_BASE (0x40039000u) -/** Peripheral TPM1 base pointer */ -#define TPM1 ((TPM_Type *)TPM1_BASE) -/** Peripheral TPM2 base address */ -#define TPM2_BASE (0x4003A000u) -/** Peripheral TPM2 base pointer */ -#define TPM2 ((TPM_Type *)TPM2_BASE) -/** Array initializer of TPM peripheral base addresses */ -#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } -/** Array initializer of TPM peripheral base pointers */ -#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } -/** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } - -/*! - * @} - */ /* end of group TPM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TRNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer - * @{ - */ - -/** TRNG - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ - __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ - __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ - __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ - }; - __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ - union { /* offset: 0x14 */ - __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ - __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ - }; - __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ - union { /* offset: 0x1C */ - __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ - __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ - }; - union { /* offset: 0x20 */ - __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ - __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ - }; - union { /* offset: 0x24 */ - __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ - __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ - }; - union { /* offset: 0x28 */ - __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ - __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ - }; - union { /* offset: 0x2C */ - __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ - __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ - }; - union { /* offset: 0x30 */ - __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ - __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ - }; - union { /* offset: 0x34 */ - __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ - __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ - }; - union { /* offset: 0x38 */ - __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ - __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ - }; - __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ - __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ - __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ - __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ - __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ - __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ - __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ - __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ - __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ - __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ - uint8_t RESERVED_0[16]; - __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xB0 */ - __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xB4 */ - __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */ - __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xBC */ - uint8_t RESERVED_1[48]; - __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ - __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ -} TRNG_Type; - -/* ---------------------------------------------------------------------------- - -- TRNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Register_Masks TRNG Register Masks - * @{ - */ - -/*! @name MCTL - Miscellaneous Control Register */ -#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) -#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) -#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) -#define TRNG_MCTL_OSC_DIV_MASK (0xCU) -#define TRNG_MCTL_OSC_DIV_SHIFT (2U) -#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) -#define TRNG_MCTL_UNUSED_MASK (0x10U) -#define TRNG_MCTL_UNUSED_SHIFT (4U) -#define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK) -#define TRNG_MCTL_TRNG_ACC_MASK (0x20U) -#define TRNG_MCTL_TRNG_ACC_SHIFT (5U) -#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) -#define TRNG_MCTL_RST_DEF_MASK (0x40U) -#define TRNG_MCTL_RST_DEF_SHIFT (6U) -#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) -#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) -#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) -#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) -#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) -#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) -#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) -#define TRNG_MCTL_FCT_VAL_MASK (0x200U) -#define TRNG_MCTL_FCT_VAL_SHIFT (9U) -#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) -#define TRNG_MCTL_ENT_VAL_MASK (0x400U) -#define TRNG_MCTL_ENT_VAL_SHIFT (10U) -#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) -#define TRNG_MCTL_TST_OUT_MASK (0x800U) -#define TRNG_MCTL_TST_OUT_SHIFT (11U) -#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) -#define TRNG_MCTL_ERR_MASK (0x1000U) -#define TRNG_MCTL_ERR_SHIFT (12U) -#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) -#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) -#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) -#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) -#define TRNG_MCTL_PRGM_MASK (0x10000U) -#define TRNG_MCTL_PRGM_SHIFT (16U) -#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) - -/*! @name SCMISC - Statistical Check Miscellaneous Register */ -#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) -#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) -#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) -#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) -#define TRNG_SCMISC_RTY_CT_SHIFT (16U) -#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) - -/*! @name PKRRNG - Poker Range Register */ -#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) -#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) -#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) - -/*! @name PKRMAX - Poker Maximum Limit Register */ -#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) -#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) -#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) - -/*! @name PKRSQ - Poker Square Calculation Result Register */ -#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) -#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) -#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) - -/*! @name SDCTL - Seed Control Register */ -#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) -#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) -#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) -#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) -#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) -#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) - -/*! @name SBLIM - Sparse Bit Limit Register */ -#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) -#define TRNG_SBLIM_SB_LIM_SHIFT (0U) -#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) - -/*! @name TOTSAM - Total Samples Register */ -#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) -#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) -#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) - -/*! @name FRQMIN - Frequency Count Minimum Limit Register */ -#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) -#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) -#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) - -/*! @name FRQCNT - Frequency Count Register */ -#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) -#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) - -/*! @name FRQMAX - Frequency Count Maximum Limit Register */ -#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) -#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) -#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) - -/*! @name SCMC - Statistical Check Monobit Count Register */ -#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) -#define TRNG_SCMC_MONO_CT_SHIFT (0U) -#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) - -/*! @name SCML - Statistical Check Monobit Limit Register */ -#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) -#define TRNG_SCML_MONO_MAX_SHIFT (0U) -#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) -#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) -#define TRNG_SCML_MONO_RNG_SHIFT (16U) -#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) - -/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ -#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) -#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) -#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) -#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) -#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) -#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) - -/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ -#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) -#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) -#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) -#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) -#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) -#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) - -/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ -#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) -#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) -#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) -#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) -#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) -#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) - -/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ -#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) -#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) -#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) -#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) -#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) -#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) - -/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ -#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) -#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) -#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) -#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) -#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) -#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) - -/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ -#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) -#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) -#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) -#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) -#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) -#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) - -/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ -#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) -#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) -#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) -#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) -#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) -#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) - -/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ -#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) -#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) -#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) -#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) -#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) -#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) - -/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ -#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) -#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) -#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) -#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) -#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) - -/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ -#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) -#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) -#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) -#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) -#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) -#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) - -/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ -#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) -#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) -#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) -#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) -#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) - -/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ -#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) -#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) -#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) -#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) -#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) -#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) - -/*! @name STATUS - Status Register */ -#define TRNG_STATUS_TF1BR0_MASK (0x1U) -#define TRNG_STATUS_TF1BR0_SHIFT (0U) -#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) -#define TRNG_STATUS_TF1BR1_MASK (0x2U) -#define TRNG_STATUS_TF1BR1_SHIFT (1U) -#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) -#define TRNG_STATUS_TF2BR0_MASK (0x4U) -#define TRNG_STATUS_TF2BR0_SHIFT (2U) -#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) -#define TRNG_STATUS_TF2BR1_MASK (0x8U) -#define TRNG_STATUS_TF2BR1_SHIFT (3U) -#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) -#define TRNG_STATUS_TF3BR0_MASK (0x10U) -#define TRNG_STATUS_TF3BR0_SHIFT (4U) -#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) -#define TRNG_STATUS_TF3BR1_MASK (0x20U) -#define TRNG_STATUS_TF3BR1_SHIFT (5U) -#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) -#define TRNG_STATUS_TF4BR0_MASK (0x40U) -#define TRNG_STATUS_TF4BR0_SHIFT (6U) -#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) -#define TRNG_STATUS_TF4BR1_MASK (0x80U) -#define TRNG_STATUS_TF4BR1_SHIFT (7U) -#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) -#define TRNG_STATUS_TF5BR0_MASK (0x100U) -#define TRNG_STATUS_TF5BR0_SHIFT (8U) -#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) -#define TRNG_STATUS_TF5BR1_MASK (0x200U) -#define TRNG_STATUS_TF5BR1_SHIFT (9U) -#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) -#define TRNG_STATUS_TF6PBR0_MASK (0x400U) -#define TRNG_STATUS_TF6PBR0_SHIFT (10U) -#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) -#define TRNG_STATUS_TF6PBR1_MASK (0x800U) -#define TRNG_STATUS_TF6PBR1_SHIFT (11U) -#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) -#define TRNG_STATUS_TFSB_MASK (0x1000U) -#define TRNG_STATUS_TFSB_SHIFT (12U) -#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) -#define TRNG_STATUS_TFLR_MASK (0x2000U) -#define TRNG_STATUS_TFLR_SHIFT (13U) -#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) -#define TRNG_STATUS_TFP_MASK (0x4000U) -#define TRNG_STATUS_TFP_SHIFT (14U) -#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) -#define TRNG_STATUS_TFMB_MASK (0x8000U) -#define TRNG_STATUS_TFMB_SHIFT (15U) -#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) -#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) -#define TRNG_STATUS_RETRY_CT_SHIFT (16U) -#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) - -/*! @name ENT - Entropy Read Register */ -#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) -#define TRNG_ENT_ENT_SHIFT (0U) -#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) - -/* The count of TRNG_ENT */ -#define TRNG_ENT_COUNT (16U) - -/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ -#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) -#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) -#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) -#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) - -/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ -#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) -#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) -#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) -#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) - -/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ -#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) -#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) -#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) -#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) - -/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ -#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) -#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) -#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) -#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) - -/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ -#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) -#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) -#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) -#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) - -/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ -#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) -#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) -#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) -#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) - -/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ -#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) -#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) -#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) -#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) - -/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ -#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) -#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) -#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) -#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) - -/*! @name SEC_CFG - Security Configuration Register */ -#define TRNG_SEC_CFG_SH0_MASK (0x1U) -#define TRNG_SEC_CFG_SH0_SHIFT (0U) -#define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK) -#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) -#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) -#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) -#define TRNG_SEC_CFG_SK_VAL_MASK (0x4U) -#define TRNG_SEC_CFG_SK_VAL_SHIFT (2U) -#define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK) - -/*! @name INT_CTRL - Interrupt Control Register */ -#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) -#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) -#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) -#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) -#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) -#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) -#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) -#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) -#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) - -/*! @name INT_MASK - Mask Register */ -#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) -#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) -#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) -#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) -#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) -#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) -#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) -#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) - -/*! @name INT_STATUS - Interrupt Status Register */ -#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) -#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) -#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) -#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) -#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) -#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) - -/*! @name VID1 - Version ID Register (MS) */ -#define TRNG_VID1_MIN_REV_MASK (0xFFU) -#define TRNG_VID1_MIN_REV_SHIFT (0U) -#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) -#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) -#define TRNG_VID1_MAJ_REV_SHIFT (8U) -#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) -#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) -#define TRNG_VID1_IP_ID_SHIFT (16U) -#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) - -/*! @name VID2 - Version ID Register (LS) */ -#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) -#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) -#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) -#define TRNG_VID2_ECO_REV_MASK (0xFF00U) -#define TRNG_VID2_ECO_REV_SHIFT (8U) -#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) -#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) -#define TRNG_VID2_INTG_OPT_SHIFT (16U) -#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) -#define TRNG_VID2_ERA_MASK (0xFF000000U) -#define TRNG_VID2_ERA_SHIFT (24U) -#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) - - -/*! - * @} - */ /* end of group TRNG_Register_Masks */ - - -/* TRNG - Peripheral instance base addresses */ -/** Peripheral TRNG0 base address */ -#define TRNG0_BASE (0x40029000u) -/** Peripheral TRNG0 base pointer */ -#define TRNG0 ((TRNG_Type *)TRNG0_BASE) -/** Array initializer of TRNG peripheral base addresses */ -#define TRNG_BASE_ADDRS { TRNG0_BASE } -/** Array initializer of TRNG peripheral base pointers */ -#define TRNG_BASE_PTRS { TRNG0 } -/** Interrupt vectors for the TRNG peripheral type */ -#define TRNG_IRQS { TRNG0_IRQn } - -/*! - * @} - */ /* end of group TRNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TSI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer - * @{ - */ - -/** TSI - Register Layout Typedef */ -typedef struct { - __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ - __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ - __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ -} TSI_Type; - -/* ---------------------------------------------------------------------------- - -- TSI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSI_Register_Masks TSI Register Masks - * @{ - */ - -/*! @name GENCS - TSI General Control and Status Register */ -#define TSI_GENCS_CURSW_MASK (0x2U) -#define TSI_GENCS_CURSW_SHIFT (1U) -#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK) -#define TSI_GENCS_EOSF_MASK (0x4U) -#define TSI_GENCS_EOSF_SHIFT (2U) -#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) -#define TSI_GENCS_SCNIP_MASK (0x8U) -#define TSI_GENCS_SCNIP_SHIFT (3U) -#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) -#define TSI_GENCS_STM_MASK (0x10U) -#define TSI_GENCS_STM_SHIFT (4U) -#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) -#define TSI_GENCS_STPE_MASK (0x20U) -#define TSI_GENCS_STPE_SHIFT (5U) -#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) -#define TSI_GENCS_TSIIEN_MASK (0x40U) -#define TSI_GENCS_TSIIEN_SHIFT (6U) -#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK) -#define TSI_GENCS_TSIEN_MASK (0x80U) -#define TSI_GENCS_TSIEN_SHIFT (7U) -#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) -#define TSI_GENCS_NSCN_MASK (0x1F00U) -#define TSI_GENCS_NSCN_SHIFT (8U) -#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK) -#define TSI_GENCS_PS_MASK (0xE000U) -#define TSI_GENCS_PS_SHIFT (13U) -#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK) -#define TSI_GENCS_EXTCHRG_MASK (0x70000U) -#define TSI_GENCS_EXTCHRG_SHIFT (16U) -#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK) -#define TSI_GENCS_DVOLT_MASK (0x180000U) -#define TSI_GENCS_DVOLT_SHIFT (19U) -#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) -#define TSI_GENCS_REFCHRG_MASK (0xE00000U) -#define TSI_GENCS_REFCHRG_SHIFT (21U) -#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK) -#define TSI_GENCS_MODE_MASK (0xF000000U) -#define TSI_GENCS_MODE_SHIFT (24U) -#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK) -#define TSI_GENCS_ESOR_MASK (0x10000000U) -#define TSI_GENCS_ESOR_SHIFT (28U) -#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) -#define TSI_GENCS_OUTRGF_MASK (0x80000000U) -#define TSI_GENCS_OUTRGF_SHIFT (31U) -#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) - -/*! @name DATA - TSI DATA Register */ -#define TSI_DATA_TSICNT_MASK (0xFFFFU) -#define TSI_DATA_TSICNT_SHIFT (0U) -#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) -#define TSI_DATA_SWTS_MASK (0x400000U) -#define TSI_DATA_SWTS_SHIFT (22U) -#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK) -#define TSI_DATA_DMAEN_MASK (0x800000U) -#define TSI_DATA_DMAEN_SHIFT (23U) -#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK) -#define TSI_DATA_TSICH_MASK (0xF0000000U) -#define TSI_DATA_TSICH_SHIFT (28U) -#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK) - -/*! @name TSHD - TSI Threshold Register */ -#define TSI_TSHD_THRESL_MASK (0xFFFFU) -#define TSI_TSHD_THRESL_SHIFT (0U) -#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) -#define TSI_TSHD_THRESH_MASK (0xFFFF0000U) -#define TSI_TSHD_THRESH_SHIFT (16U) -#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) - - -/*! - * @} - */ /* end of group TSI_Register_Masks */ - - -/* TSI - Peripheral instance base addresses */ -/** Peripheral TSI0 base address */ -#define TSI0_BASE (0x40045000u) -/** Peripheral TSI0 base pointer */ -#define TSI0 ((TSI_Type *)TSI0_BASE) -/** Array initializer of TSI peripheral base addresses */ -#define TSI_BASE_ADDRS { TSI0_BASE } -/** Array initializer of TSI peripheral base pointers */ -#define TSI_BASE_PTRS { TSI0 } -/** Interrupt vectors for the TSI peripheral type */ -#define TSI_IRQS { TSI0_IRQn } - -/*! - * @} - */ /* end of group TSI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- VREF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer - * @{ - */ - -/** VREF - Register Layout Typedef */ -typedef struct { - __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ - __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ -} VREF_Type; - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/*! @name TRM - VREF Trim Register */ -#define VREF_TRM_TRIM_MASK (0x3FU) -#define VREF_TRM_TRIM_SHIFT (0U) -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) -#define VREF_TRM_CHOPEN_MASK (0x40U) -#define VREF_TRM_CHOPEN_SHIFT (6U) -#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) - -/*! @name SC - VREF Status and Control Register */ -#define VREF_SC_MODE_LV_MASK (0x3U) -#define VREF_SC_MODE_LV_SHIFT (0U) -#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) -#define VREF_SC_VREFST_MASK (0x4U) -#define VREF_SC_VREFST_SHIFT (2U) -#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) -#define VREF_SC_ICOMPEN_MASK (0x20U) -#define VREF_SC_ICOMPEN_SHIFT (5U) -#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) -#define VREF_SC_REGEN_MASK (0x40U) -#define VREF_SC_REGEN_SHIFT (6U) -#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) -#define VREF_SC_VREFEN_MASK (0x80U) -#define VREF_SC_VREFEN_SHIFT (7U) -#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) - - -/*! - * @} - */ /* end of group VREF_Register_Masks */ - - -/* VREF - Peripheral instance base addresses */ -/** Peripheral VREF base address */ -#define VREF_BASE (0x40074000u) -/** Peripheral VREF base pointer */ -#define VREF ((VREF_Type *)VREF_BASE) -/** Array initializer of VREF peripheral base addresses */ -#define VREF_BASE_ADDRS { VREF_BASE } -/** Array initializer of VREF peripheral base pointers */ -#define VREF_BASE_PTRS { VREF } - -/*! - * @} - */ /* end of group VREF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_ANALOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ANALOG_Peripheral_Access_Layer XCVR_ANALOG Peripheral Access Layer - * @{ - */ - -/** XCVR_ANALOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t BB_LDO_1; /**< RF Analog Baseband LDO Control 1, offset: 0x0 */ - __IO uint32_t BB_LDO_2; /**< RF Analog Baseband LDO Control 2, offset: 0x4 */ - __IO uint32_t RX_ADC; /**< RF Analog ADC Control, offset: 0x8 */ - __IO uint32_t RX_BBA; /**< RF Analog BBA Control, offset: 0xC */ - __IO uint32_t RX_LNA; /**< RF Analog LNA Control, offset: 0x10 */ - __IO uint32_t RX_TZA; /**< RF Analog TZA Control, offset: 0x14 */ - __IO uint32_t RX_AUXPLL; /**< RF Analog Aux PLL Control, offset: 0x18 */ - __IO uint32_t SY_CTRL_1; /**< RF Analog Synthesizer Control 1, offset: 0x1C */ - __IO uint32_t SY_CTRL_2; /**< RF Analog Synthesizer Control 2, offset: 0x20 */ - __IO uint32_t TX_DAC_PA; /**< RF Analog TX HPM DAC and PA Control, offset: 0x24 */ - __IO uint32_t BALUN_TX; /**< RF Analog Balun TX Mode Control, offset: 0x28 */ - __IO uint32_t BALUN_RX; /**< RF Analog Balun RX Mode Control, offset: 0x2C */ - __I uint32_t DFT_OBSV_1; /**< RF Analog DFT Observation Register 1, offset: 0x30 */ - __IO uint32_t DFT_OBSV_2; /**< RF Analog DFT Observation Register 2, offset: 0x34 */ -} XCVR_ANALOG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_ANALOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ANALOG_Register_Masks XCVR_ANALOG Register Masks - * @{ - */ - -/*! @name BB_LDO_1 - RF Analog Baseband LDO Control 1 */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK (0x1U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT (0U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK (0x2U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT (1U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK (0xCU) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT (2U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK (0x70U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT (4U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK (0x100U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT (8U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK (0x200U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT (9U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK (0xC00U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT (10U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK (0x7000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT (12U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK (0x10000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT (16U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK (0x20000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT (17U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK (0xC0000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT (18U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK (0x700000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT (20U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK (0x1000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT (24U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK (0x2000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT (25U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK (0xC000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT (26U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK (0x70000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT (28U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK) - -/*! @name BB_LDO_2 - RF Analog Baseband LDO Control 2 */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK (0x1U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT (0U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK (0x2U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT (1U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK (0xCU) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT (2U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK (0x70U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT (4U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK (0x300U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT (8U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK (0x400U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT (10U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK (0x800U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT (11U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK (0x7000U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT (12U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK (0x10000U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT (16U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK (0x60000U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT (17U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK) - -/*! @name RX_ADC - RF Analog ADC Control */ -#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK (0xFFU) -#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT (0U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK (0x300U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT (8U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK (0x400U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT (10U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK (0x800U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT (11U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK (0xF000U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT (12U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK) - -/*! @name RX_BBA - RF Analog BBA Control */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK (0x7U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT (0U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK (0x8U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT (3U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK (0x10U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT (4U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK (0x20U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT (5U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK (0x40U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT (6U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK (0x80U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT (7U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK (0x3F0000U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT (16U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK (0x7000000U) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT (24U) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK (0x70000000U) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT (28U) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK) - -/*! @name RX_LNA - RF Analog LNA Control */ -#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK (0xFU) -#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT (0U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK (0x10U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT (4U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK (0x20U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT (5U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK (0x40U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT (6U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK (0x300U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT (8U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK (0xF0000U) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT (16U) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK (0x100000U) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT (20U) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK) - -/*! @name RX_TZA - RF Analog TZA Control */ -#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK (0x7U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT (0U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK (0x8U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT (3U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK (0x10U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT (4U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK (0x3F0000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT (16U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK (0x1000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT (24U) -#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK (0x2000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT (25U) -#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK (0x4000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT (26U) -#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK (0x8000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT (27U) -#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK) - -/*! @name RX_AUXPLL - RF Analog Aux PLL Control */ -#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK (0x7U) -#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT (0U) -#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK (0x8U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT (3U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK (0x10U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT (4U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK) -#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK (0xE0U) -#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT (5U) -#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK) -#define XCVR_ANALOG_RX_AUXPLL_SPARE_MASK (0xF00U) -#define XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT (8U) -#define XCVR_ANALOG_RX_AUXPLL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_SPARE_MASK) -#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK (0xF000U) -#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT (12U) -#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK) -#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK (0x10000U) -#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT (16U) -#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK (0x300000U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT (20U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK (0x7000000U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT (24U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK (0x10000000U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT (28U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK) - -/*! @name SY_CTRL_1 - RF Analog Synthesizer Control 1 */ -#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK (0x1U) -#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT (0U) -#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK (0x2U) -#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT (1U) -#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK (0x30U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT (4U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK (0xC0U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT (6U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK (0x300U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT (8U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK (0x400U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT (10U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK (0x7000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT (12U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK (0x70000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT (16U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK (0x80000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT (19U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK (0x100000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT (20U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK (0x600000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT (21U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK (0x800000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT (23U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK (0x3000000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT (24U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_MASK (0x10000000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_SHIFT (28U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_MASK) - -/*! @name SY_CTRL_2 - RF Analog Synthesizer Control 2 */ -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK (0x7U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT (0U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK (0x8U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT (3U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK (0x70U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT (4U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK (0x700U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT (8U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK (0x1000U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT (12U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK (0x1C000U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT (14U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK) - -/*! @name TX_DAC_PA - RF Analog TX HPM DAC and PA Control */ -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK (0x3U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT (0U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK (0x18U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT (3U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK (0xC0U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT (6U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK (0x200U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT (9U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK (0x400U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT (10U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK (0x800U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT (11U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK (0xE000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT (13U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK (0xE0000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT (17U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK (0x200000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT (21U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK (0x3800000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT (23U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK) - -/*! @name BALUN_TX - RF Analog Balun TX Mode Control */ -#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK (0xFFFFFFU) -#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT (0U) -#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK) - -/*! @name BALUN_RX - RF Analog Balun RX Mode Control */ -#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK (0xFFFFFFU) -#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT (0U) -#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK) - -/*! @name DFT_OBSV_1 - RF Analog DFT Observation Register 1 */ -#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK (0x7FFFFU) -#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT (0U) -#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK) -#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK (0xFF00000U) -#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT (20U) -#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK) - -/*! @name DFT_OBSV_2 - RF Analog DFT Observation Register 2 */ -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK (0x1FFFFU) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT (0U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK (0x7F000000U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT (24U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK (0x80000000U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT (31U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK) - - -/*! - * @} - */ /* end of group XCVR_ANALOG_Register_Masks */ - - -/* XCVR_ANALOG - Peripheral instance base addresses */ -/** Peripheral XCVR_ANA base address */ -#define XCVR_ANA_BASE (0x4005C500u) -/** Peripheral XCVR_ANA base pointer */ -#define XCVR_ANA ((XCVR_ANALOG_Type *)XCVR_ANA_BASE) -/** Array initializer of XCVR_ANALOG peripheral base addresses */ -#define XCVR_ANALOG_BASE_ADDRS { XCVR_ANA_BASE } -/** Array initializer of XCVR_ANALOG peripheral base pointers */ -#define XCVR_ANALOG_BASE_PTRS { XCVR_ANA } - -/*! - * @} - */ /* end of group XCVR_ANALOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_CTRL_Peripheral_Access_Layer XCVR_CTRL Peripheral Access Layer - * @{ - */ - -/** XCVR_CTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x0 */ - __IO uint32_t XCVR_STATUS; /**< TRANSCEIVER STATUS, offset: 0x4 */ - __IO uint32_t BLE_ARB_CTRL; /**< BLE ARBITRATION CONTROL, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t OVERWRITE_VER; /**< OVERWRITE VERSION, offset: 0x10 */ - __IO uint32_t DMA_CTRL; /**< TRANSCEIVER DMA CONTROL, offset: 0x14 */ - __I uint32_t DMA_DATA; /**< TRANSCEIVER DMA DATA, offset: 0x18 */ - __IO uint32_t DTEST_CTRL; /**< DIGITAL TEST MUX CONTROL, offset: 0x1C */ - __IO uint32_t PACKET_RAM_CTRL; /**< PACKET RAM CONTROL, offset: 0x20 */ - __IO uint32_t FAD_CTRL; /**< FAD CONTROL, offset: 0x24 */ - __IO uint32_t LPPS_CTRL; /**< LOW POWER PREAMBLE SEARCH CONTROL, offset: 0x28 */ - __IO uint32_t RF_NOT_ALLOWED_CTRL; /**< WIFI COEXISTENCE CONTROL, offset: 0x2C */ - __IO uint32_t CRCW_CFG; /**< CRC/WHITENER CONTROL, offset: 0x30 */ - __I uint32_t CRC_EC_MASK; /**< CRC ERROR CORRECTION MASK, offset: 0x34 */ - __I uint32_t CRC_RES_OUT; /**< CRC RESULT, offset: 0x38 */ -} XCVR_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_CTRL_Register_Masks XCVR_CTRL Register Masks - * @{ - */ - -/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */ -#define XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK (0xFU) -#define XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT (0U) -#define XCVR_CTRL_XCVR_CTRL_PROTOCOL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK) -#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK (0x70U) -#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT (4U) -#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT)) & XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK) -#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK (0x300U) -#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT (8U) -#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT)) & XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK) -#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK (0x800U) -#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT (11U) -#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT)) & XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK) -#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK (0x3000U) -#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT (12U) -#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK) -#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK (0x70000U) -#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT (16U) -#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK) -#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK (0x700000U) -#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT (20U) -#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK) - -/*! @name XCVR_STATUS - TRANSCEIVER STATUS */ -#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK (0xFFU) -#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT (0U) -#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) -#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK (0xF00U) -#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT (8U) -#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK) -#define XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK (0x1000U) -#define XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT (12U) -#define XCVR_CTRL_XCVR_STATUS_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK) -#define XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK (0x2000U) -#define XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT (13U) -#define XCVR_CTRL_XCVR_STATUS_TX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK) -#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK (0x10000U) -#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT (16U) -#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT)) & XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK) -#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK (0x20000U) -#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT (17U) -#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK) -#define XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK (0x40000U) -#define XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT (18U) -#define XCVR_CTRL_XCVR_STATUS_XTAL_READY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT)) & XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK) -#define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_MASK (0x80000U) -#define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT (19U) -#define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT)) & XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_MASK) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK (0x1000000U) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT (24U) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK (0x2000000U) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT (25U) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK) - -/*! @name BLE_ARB_CTRL - BLE ARBITRATION CONTROL */ -#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK (0x1U) -#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT (0U) -#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK) -#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK (0x2U) -#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT (1U) -#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK) - -/*! @name OVERWRITE_VER - OVERWRITE VERSION */ -#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK (0xFFU) -#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT (0U) -#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT)) & XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK) - -/*! @name DMA_CTRL - TRANSCEIVER DMA CONTROL */ -#define XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK (0xFU) -#define XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT (0U) -#define XCVR_CTRL_DMA_CTRL_DMA_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK) -#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK (0x10U) -#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT (4U) -#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT)) & XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK) -#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK (0x20U) -#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT (5U) -#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT)) & XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_MASK (0x40U) -#define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_SHIFT (6U) -#define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK (0x80U) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT (7U) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK (0xF00U) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT (8U) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK) - -/*! @name DMA_DATA - TRANSCEIVER DMA DATA */ -#define XCVR_CTRL_DMA_DATA_DMA_DATA_MASK (0xFFFFFFFFU) -#define XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT (0U) -#define XCVR_CTRL_DMA_DATA_DMA_DATA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT)) & XCVR_CTRL_DMA_DATA_DMA_DATA_MASK) - -/*! @name DTEST_CTRL - DIGITAL TEST MUX CONTROL */ -#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK (0x3FU) -#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT (0U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK) -#define XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK (0x80U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT (7U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK) -#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK (0xF00U) -#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT (8U) -#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK) -#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK (0xF000U) -#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT (12U) -#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK) -#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK (0x30000U) -#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT (16U) -#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT)) & XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK) -#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK (0x7000000U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT (24U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK (0x10000000U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT (28U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK (0x20000000U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT (29U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK) - -/*! @name PACKET_RAM_CTRL - PACKET RAM CONTROL */ -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK (0xFU) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT (0U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK (0x10U) -#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT (4U) -#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK (0x20U) -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT (5U) -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK (0x40U) -#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT (6U) -#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_MASK (0x80U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_SHIFT (7U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK (0x300U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT (8U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK (0x400U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT (10U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK (0x800U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT (11U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK (0x1000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT (12U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK (0x2000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT (13U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK (0x4000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT (14U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK (0x8000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT (15U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK (0x10000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT (16U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK (0x20000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT (17U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK) - -/*! @name FAD_CTRL - FAD CONTROL */ -#define XCVR_CTRL_FAD_CTRL_FAD_EN_MASK (0x1U) -#define XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT (0U) -#define XCVR_CTRL_FAD_CTRL_FAD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_EN_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_MASK (0x2U) -#define XCVR_CTRL_FAD_CTRL_ANTX_SHIFT (1U) -#define XCVR_CTRL_FAD_CTRL_ANTX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK (0x30U) -#define XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT (4U) -#define XCVR_CTRL_FAD_CTRL_ANTX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK (0x40U) -#define XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT (6U) -#define XCVR_CTRL_FAD_CTRL_ANTX_HZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK (0x80U) -#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT (7U) -#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK (0xF00U) -#define XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT (8U) -#define XCVR_CTRL_FAD_CTRL_ANTX_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK) -#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK (0xF000U) -#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT (12U) -#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK) - -/*! @name LPPS_CTRL - LOW POWER PREAMBLE SEARCH CONTROL */ -#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK (0x1U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT (0U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK (0x2U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT (1U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK (0x4U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT (2U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK (0x8U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT (3U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK (0x10U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT (4U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK (0x20U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT (5U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK (0x40U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT (6U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK (0x80U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT (7U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK (0x100U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT (8U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK (0x200U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT (9U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK (0xFF0000U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT (16U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK (0xFF000000U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT (24U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK) - -/*! @name RF_NOT_ALLOWED_CTRL - WIFI COEXISTENCE CONTROL */ -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_MASK (0x1U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT (0U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_MASK) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_MASK (0x2U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT (1U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_MASK) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK (0x4U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT (2U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK (0x8U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT (3U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK (0x10U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT (4U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_MASK (0x20U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_SHIFT (5U) -#define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_MASK) - -/*! @name CRCW_CFG - CRC/WHITENER CONTROL */ -#define XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK (0x1U) -#define XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT (0U) -#define XCVR_CTRL_CRCW_CFG_CRCW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK (0x2U) -#define XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT (1U) -#define XCVR_CTRL_CRCW_CFG_CRC_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK (0x4U) -#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT (2U) -#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK (0x8U) -#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT (3U) -#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK (0x7FF0000U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT (16U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK (0x10000000U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT (28U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK (0x20000000U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT (29U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK) - -/*! @name CRC_EC_MASK - CRC ERROR CORRECTION MASK */ -#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK (0xFFFFFFFFU) -#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT (0U) -#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT)) & XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK) - -/*! @name CRC_RES_OUT - CRC RESULT */ -#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK (0xFFFFFFFFU) -#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT (0U) -#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT)) & XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK) - - -/*! - * @} - */ /* end of group XCVR_CTRL_Register_Masks */ - - -/* XCVR_CTRL - Peripheral instance base addresses */ -/** Peripheral XCVR_MISC base address */ -#define XCVR_MISC_BASE (0x4005C280u) -/** Peripheral XCVR_MISC base pointer */ -#define XCVR_MISC ((XCVR_CTRL_Type *)XCVR_MISC_BASE) -/** Array initializer of XCVR_CTRL peripheral base addresses */ -#define XCVR_CTRL_BASE_ADDRS { XCVR_MISC_BASE } -/** Array initializer of XCVR_CTRL peripheral base pointers */ -#define XCVR_CTRL_BASE_PTRS { XCVR_MISC } - -/*! - * @} - */ /* end of group XCVR_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_PHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PHY_Peripheral_Access_Layer XCVR_PHY Peripheral Access Layer - * @{ - */ - -/** XCVR_PHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PHY_PRE_REF0; /**< PREAMBLE REFERENCE WAVEFORM 0, offset: 0x0 */ - __IO uint32_t PRE_REF1; /**< PREAMBLE REFERENCE WAVEFORM 1, offset: 0x4 */ - __IO uint32_t PRE_REF2; /**< PREAMBLE REFERENCE WAVEFORM 2, offset: 0x8 */ - uint8_t RESERVED_0[20]; - __IO uint32_t CFG1; /**< PHY CONFIGURATION REGISTER 1, offset: 0x20 */ - __IO uint32_t CFG2; /**< PHY CONFIGURATION REGISTER 2, offset: 0x24 */ - __IO uint32_t EL_CFG; /**< PHY EARLY/LATE CONFIGURATION REGISTER, offset: 0x28 */ - __IO uint32_t NTW_ADR_BSM; /**< PHY NETWORK ADDRESS FOR BSM, offset: 0x2C */ - __I uint32_t STATUS; /**< PHY STATUS REGISTER, offset: 0x30 */ -} XCVR_PHY_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_PHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PHY_Register_Masks XCVR_PHY Register Masks - * @{ - */ - -/*! @name PHY_PRE_REF0 - PREAMBLE REFERENCE WAVEFORM 0 */ -#define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_MASK (0xFFFFFFFFU) -#define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_SHIFT (0U) -#define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_SHIFT)) & XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_MASK) - -/*! @name PRE_REF1 - PREAMBLE REFERENCE WAVEFORM 1 */ -#define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_MASK (0xFFFFFFFFU) -#define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_SHIFT (0U) -#define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_SHIFT)) & XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_MASK) - -/*! @name PRE_REF2 - PREAMBLE REFERENCE WAVEFORM 2 */ -#define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_MASK (0xFFFFU) -#define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_SHIFT (0U) -#define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_SHIFT)) & XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_MASK) - -/*! @name CFG1 - PHY CONFIGURATION REGISTER 1 */ -#define XCVR_PHY_CFG1_AA_PLAYBACK_MASK (0x2U) -#define XCVR_PHY_CFG1_AA_PLAYBACK_SHIFT (1U) -#define XCVR_PHY_CFG1_AA_PLAYBACK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_AA_PLAYBACK_SHIFT)) & XCVR_PHY_CFG1_AA_PLAYBACK_MASK) -#define XCVR_PHY_CFG1_AA_OUTPUT_SEL_MASK (0x4U) -#define XCVR_PHY_CFG1_AA_OUTPUT_SEL_SHIFT (2U) -#define XCVR_PHY_CFG1_AA_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_AA_OUTPUT_SEL_SHIFT)) & XCVR_PHY_CFG1_AA_OUTPUT_SEL_MASK) -#define XCVR_PHY_CFG1_FSK_BIT_INVERT_MASK (0x8U) -#define XCVR_PHY_CFG1_FSK_BIT_INVERT_SHIFT (3U) -#define XCVR_PHY_CFG1_FSK_BIT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_FSK_BIT_INVERT_SHIFT)) & XCVR_PHY_CFG1_FSK_BIT_INVERT_MASK) -#define XCVR_PHY_CFG1_RFU00_MASK (0x10U) -#define XCVR_PHY_CFG1_RFU00_SHIFT (4U) -#define XCVR_PHY_CFG1_RFU00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU00_SHIFT)) & XCVR_PHY_CFG1_RFU00_MASK) -#define XCVR_PHY_CFG1_BSM_EN_BLE_MASK (0x20U) -#define XCVR_PHY_CFG1_BSM_EN_BLE_SHIFT (5U) -#define XCVR_PHY_CFG1_BSM_EN_BLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_BSM_EN_BLE_SHIFT)) & XCVR_PHY_CFG1_BSM_EN_BLE_MASK) -#define XCVR_PHY_CFG1_DEMOD_CLK_MODE_MASK (0xC0U) -#define XCVR_PHY_CFG1_DEMOD_CLK_MODE_SHIFT (6U) -#define XCVR_PHY_CFG1_DEMOD_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_DEMOD_CLK_MODE_SHIFT)) & XCVR_PHY_CFG1_DEMOD_CLK_MODE_MASK) -#define XCVR_PHY_CFG1_CTS_THRESH_MASK (0xFF00U) -#define XCVR_PHY_CFG1_CTS_THRESH_SHIFT (8U) -#define XCVR_PHY_CFG1_CTS_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_CTS_THRESH_SHIFT)) & XCVR_PHY_CFG1_CTS_THRESH_MASK) -#define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_MASK (0x700000U) -#define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_SHIFT (20U) -#define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_SHIFT)) & XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_MASK) -#define XCVR_PHY_CFG1_RFU01_MASK (0x1000000U) -#define XCVR_PHY_CFG1_RFU01_SHIFT (24U) -#define XCVR_PHY_CFG1_RFU01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU01_SHIFT)) & XCVR_PHY_CFG1_RFU01_MASK) -#define XCVR_PHY_CFG1_RFU02_MASK (0x2000000U) -#define XCVR_PHY_CFG1_RFU02_SHIFT (25U) -#define XCVR_PHY_CFG1_RFU02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU02_SHIFT)) & XCVR_PHY_CFG1_RFU02_MASK) -#define XCVR_PHY_CFG1_BLE_NTW_ADR_THR_MASK (0x70000000U) -#define XCVR_PHY_CFG1_BLE_NTW_ADR_THR_SHIFT (28U) -#define XCVR_PHY_CFG1_BLE_NTW_ADR_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_BLE_NTW_ADR_THR_SHIFT)) & XCVR_PHY_CFG1_BLE_NTW_ADR_THR_MASK) - -/*! @name CFG2 - PHY CONFIGURATION REGISTER 2 */ -#define XCVR_PHY_CFG2_PHY_FIFO_PRECHG_MASK (0xFU) -#define XCVR_PHY_CFG2_PHY_FIFO_PRECHG_SHIFT (0U) -#define XCVR_PHY_CFG2_PHY_FIFO_PRECHG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_PHY_FIFO_PRECHG_SHIFT)) & XCVR_PHY_CFG2_PHY_FIFO_PRECHG_MASK) -#define XCVR_PHY_CFG2_RFU03_MASK (0x10U) -#define XCVR_PHY_CFG2_RFU03_SHIFT (4U) -#define XCVR_PHY_CFG2_RFU03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU03_SHIFT)) & XCVR_PHY_CFG2_RFU03_MASK) -#define XCVR_PHY_CFG2_RFU04_MASK (0x20U) -#define XCVR_PHY_CFG2_RFU04_SHIFT (5U) -#define XCVR_PHY_CFG2_RFU04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU04_SHIFT)) & XCVR_PHY_CFG2_RFU04_MASK) -#define XCVR_PHY_CFG2_RFU05_MASK (0x40U) -#define XCVR_PHY_CFG2_RFU05_SHIFT (6U) -#define XCVR_PHY_CFG2_RFU05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU05_SHIFT)) & XCVR_PHY_CFG2_RFU05_MASK) -#define XCVR_PHY_CFG2_RFU06_MASK (0x80U) -#define XCVR_PHY_CFG2_RFU06_SHIFT (7U) -#define XCVR_PHY_CFG2_RFU06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU06_SHIFT)) & XCVR_PHY_CFG2_RFU06_MASK) -#define XCVR_PHY_CFG2_X2_DEMOD_GAIN_MASK (0xF00U) -#define XCVR_PHY_CFG2_X2_DEMOD_GAIN_SHIFT (8U) -#define XCVR_PHY_CFG2_X2_DEMOD_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_X2_DEMOD_GAIN_SHIFT)) & XCVR_PHY_CFG2_X2_DEMOD_GAIN_MASK) -#define XCVR_PHY_CFG2_RFU07_MASK (0x10000U) -#define XCVR_PHY_CFG2_RFU07_SHIFT (16U) -#define XCVR_PHY_CFG2_RFU07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU07_SHIFT)) & XCVR_PHY_CFG2_RFU07_MASK) -#define XCVR_PHY_CFG2_RFU08_MASK (0x20000U) -#define XCVR_PHY_CFG2_RFU08_SHIFT (17U) -#define XCVR_PHY_CFG2_RFU08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU08_SHIFT)) & XCVR_PHY_CFG2_RFU08_MASK) -#define XCVR_PHY_CFG2_RFU09_MASK (0x40000U) -#define XCVR_PHY_CFG2_RFU09_SHIFT (18U) -#define XCVR_PHY_CFG2_RFU09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU09_SHIFT)) & XCVR_PHY_CFG2_RFU09_MASK) -#define XCVR_PHY_CFG2_RFU10_MASK (0x80000U) -#define XCVR_PHY_CFG2_RFU10_SHIFT (19U) -#define XCVR_PHY_CFG2_RFU10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU10_SHIFT)) & XCVR_PHY_CFG2_RFU10_MASK) -#define XCVR_PHY_CFG2_RFU11_MASK (0x100000U) -#define XCVR_PHY_CFG2_RFU11_SHIFT (20U) -#define XCVR_PHY_CFG2_RFU11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU11_SHIFT)) & XCVR_PHY_CFG2_RFU11_MASK) -#define XCVR_PHY_CFG2_RFU12_MASK (0x200000U) -#define XCVR_PHY_CFG2_RFU12_SHIFT (21U) -#define XCVR_PHY_CFG2_RFU12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU12_SHIFT)) & XCVR_PHY_CFG2_RFU12_MASK) -#define XCVR_PHY_CFG2_RFU13_MASK (0x400000U) -#define XCVR_PHY_CFG2_RFU13_SHIFT (22U) -#define XCVR_PHY_CFG2_RFU13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU13_SHIFT)) & XCVR_PHY_CFG2_RFU13_MASK) -#define XCVR_PHY_CFG2_RFU14_MASK (0x800000U) -#define XCVR_PHY_CFG2_RFU14_SHIFT (23U) -#define XCVR_PHY_CFG2_RFU14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU14_SHIFT)) & XCVR_PHY_CFG2_RFU14_MASK) -#define XCVR_PHY_CFG2_RFU15_MASK (0x1000000U) -#define XCVR_PHY_CFG2_RFU15_SHIFT (24U) -#define XCVR_PHY_CFG2_RFU15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU15_SHIFT)) & XCVR_PHY_CFG2_RFU15_MASK) -#define XCVR_PHY_CFG2_RFU16_MASK (0x2000000U) -#define XCVR_PHY_CFG2_RFU16_SHIFT (25U) -#define XCVR_PHY_CFG2_RFU16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU16_SHIFT)) & XCVR_PHY_CFG2_RFU16_MASK) -#define XCVR_PHY_CFG2_PHY_CLK_ON_MASK (0x80000000U) -#define XCVR_PHY_CFG2_PHY_CLK_ON_SHIFT (31U) -#define XCVR_PHY_CFG2_PHY_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_PHY_CLK_ON_SHIFT)) & XCVR_PHY_CFG2_PHY_CLK_ON_MASK) - -/*! @name EL_CFG - PHY EARLY/LATE CONFIGURATION REGISTER */ -#define XCVR_PHY_EL_CFG_EL_ENABLE_MASK (0x1U) -#define XCVR_PHY_EL_CFG_EL_ENABLE_SHIFT (0U) -#define XCVR_PHY_EL_CFG_EL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ENABLE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ENABLE_MASK) -#define XCVR_PHY_EL_CFG_EL_ZB_ENABLE_MASK (0x2U) -#define XCVR_PHY_EL_CFG_EL_ZB_ENABLE_SHIFT (1U) -#define XCVR_PHY_EL_CFG_EL_ZB_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ZB_ENABLE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ZB_ENABLE_MASK) -#define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_MASK (0x4U) -#define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_SHIFT (2U) -#define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_MASK) -#define XCVR_PHY_EL_CFG_EL_WIN_SIZE_MASK (0xF00U) -#define XCVR_PHY_EL_CFG_EL_WIN_SIZE_SHIFT (8U) -#define XCVR_PHY_EL_CFG_EL_WIN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_WIN_SIZE_SHIFT)) & XCVR_PHY_EL_CFG_EL_WIN_SIZE_MASK) -#define XCVR_PHY_EL_CFG_EL_INTERVAL_MASK (0x3F0000U) -#define XCVR_PHY_EL_CFG_EL_INTERVAL_SHIFT (16U) -#define XCVR_PHY_EL_CFG_EL_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_INTERVAL_SHIFT)) & XCVR_PHY_EL_CFG_EL_INTERVAL_MASK) - -/*! @name NTW_ADR_BSM - PHY NETWORK ADDRESS FOR BSM */ -#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK (0xFFFFFFFFU) -#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT (0U) -#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT)) & XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK) - -/*! @name STATUS - PHY STATUS REGISTER */ -#define XCVR_PHY_STATUS_PREAMBLE_FOUND_MASK (0x1U) -#define XCVR_PHY_STATUS_PREAMBLE_FOUND_SHIFT (0U) -#define XCVR_PHY_STATUS_PREAMBLE_FOUND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_PREAMBLE_FOUND_SHIFT)) & XCVR_PHY_STATUS_PREAMBLE_FOUND_MASK) -#define XCVR_PHY_STATUS_AA_SFD_MATCHED_MASK (0x2U) -#define XCVR_PHY_STATUS_AA_SFD_MATCHED_SHIFT (1U) -#define XCVR_PHY_STATUS_AA_SFD_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_AA_SFD_MATCHED_SHIFT)) & XCVR_PHY_STATUS_AA_SFD_MATCHED_MASK) -#define XCVR_PHY_STATUS_AA_MATCHED_MASK (0xF0U) -#define XCVR_PHY_STATUS_AA_MATCHED_SHIFT (4U) -#define XCVR_PHY_STATUS_AA_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_AA_MATCHED_SHIFT)) & XCVR_PHY_STATUS_AA_MATCHED_MASK) -#define XCVR_PHY_STATUS_HAMMING_DISTANCE_MASK (0x700U) -#define XCVR_PHY_STATUS_HAMMING_DISTANCE_SHIFT (8U) -#define XCVR_PHY_STATUS_HAMMING_DISTANCE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_HAMMING_DISTANCE_SHIFT)) & XCVR_PHY_STATUS_HAMMING_DISTANCE_MASK) -#define XCVR_PHY_STATUS_DATA_FIFO_DEPTH_MASK (0xF000U) -#define XCVR_PHY_STATUS_DATA_FIFO_DEPTH_SHIFT (12U) -#define XCVR_PHY_STATUS_DATA_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_DATA_FIFO_DEPTH_SHIFT)) & XCVR_PHY_STATUS_DATA_FIFO_DEPTH_MASK) -#define XCVR_PHY_STATUS_CFO_ESTIMATE_MASK (0xFF0000U) -#define XCVR_PHY_STATUS_CFO_ESTIMATE_SHIFT (16U) -#define XCVR_PHY_STATUS_CFO_ESTIMATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_CFO_ESTIMATE_SHIFT)) & XCVR_PHY_STATUS_CFO_ESTIMATE_MASK) - - -/*! - * @} - */ /* end of group XCVR_PHY_Register_Masks */ - - -/* XCVR_PHY - Peripheral instance base addresses */ -/** Peripheral XCVR_PHY base address */ -#define XCVR_PHY_BASE (0x4005C400u) -/** Peripheral XCVR_PHY base pointer */ -#define XCVR_PHY ((XCVR_PHY_Type *)XCVR_PHY_BASE) -/** Array initializer of XCVR_PHY peripheral base addresses */ -#define XCVR_PHY_BASE_ADDRS { XCVR_PHY_BASE } -/** Array initializer of XCVR_PHY peripheral base pointers */ -#define XCVR_PHY_BASE_PTRS { XCVR_PHY } - -/*! - * @} - */ /* end of group XCVR_PHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_PKT_RAM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PKT_RAM_Peripheral_Access_Layer XCVR_PKT_RAM Peripheral Access Layer - * @{ - */ - -/** XCVR_PKT_RAM - Register Layout Typedef */ -typedef struct { - __IO uint16_t PACKET_RAM_0[544]; /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x0, array step: 0x2 */ - __IO uint16_t PACKET_RAM_1[544]; /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x440, array step: 0x2 */ -} XCVR_PKT_RAM_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_PKT_RAM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PKT_RAM_Register_Masks XCVR_PKT_RAM Register Masks - * @{ - */ - -/*! @name PACKET_RAM_0 - Shared Packet RAM for multiple Link Layer usage. */ -#define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_MASK (0xFFU) -#define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_SHIFT (0U) -#define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_MASK) -#define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_MASK (0xFF00U) -#define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_SHIFT (8U) -#define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_MASK) - -/* The count of XCVR_PKT_RAM_PACKET_RAM_0 */ -#define XCVR_PKT_RAM_PACKET_RAM_0_COUNT (544U) - -/*! @name PACKET_RAM_1 - Shared Packet RAM for multiple Link Layer usage. */ -#define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_MASK (0xFFU) -#define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_SHIFT (0U) -#define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_MASK) -#define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_MASK (0xFF00U) -#define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_SHIFT (8U) -#define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_MASK) - -/* The count of XCVR_PKT_RAM_PACKET_RAM_1 */ -#define XCVR_PKT_RAM_PACKET_RAM_1_COUNT (544U) - - -/*! - * @} - */ /* end of group XCVR_PKT_RAM_Register_Masks */ - - -/* XCVR_PKT_RAM - Peripheral instance base addresses */ -/** Peripheral XCVR_PKT_RAM base address */ -#define XCVR_PKT_RAM_BASE (0x4005C700u) -/** Peripheral XCVR_PKT_RAM base pointer */ -#define XCVR_PKT_RAM ((XCVR_PKT_RAM_Type *)XCVR_PKT_RAM_BASE) -/** Array initializer of XCVR_PKT_RAM peripheral base addresses */ -#define XCVR_PKT_RAM_BASE_ADDRS { XCVR_PKT_RAM_BASE } -/** Array initializer of XCVR_PKT_RAM peripheral base pointers */ -#define XCVR_PKT_RAM_BASE_PTRS { XCVR_PKT_RAM } - -/*! - * @} - */ /* end of group XCVR_PKT_RAM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_PLL_DIG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PLL_DIG_Peripheral_Access_Layer XCVR_PLL_DIG Peripheral Access Layer - * @{ - */ - -/** XCVR_PLL_DIG - Register Layout Typedef */ -typedef struct { - __IO uint32_t HPM_BUMP; /**< PLL HPM Analog Bump Control, offset: 0x0 */ - __IO uint32_t MOD_CTRL; /**< PLL Modulation Control, offset: 0x4 */ - __IO uint32_t CHAN_MAP; /**< PLL Channel Mapping, offset: 0x8 */ - __IO uint32_t LOCK_DETECT; /**< PLL Lock Detect Control, offset: 0xC */ - __IO uint32_t HPM_CTRL; /**< PLL High Port Modulator Control, offset: 0x10 */ - __IO uint32_t HPMCAL_CTRL; /**< PLL High Port Calibration Control, offset: 0x14 */ - __IO uint32_t HPM_CAL1; /**< PLL High Port Calibration Result 1, offset: 0x18 */ - __IO uint32_t HPM_CAL2; /**< PLL High Port Calibration Result 2, offset: 0x1C */ - __IO uint32_t HPM_SDM_RES; /**< PLL High Port Sigma Delta Results, offset: 0x20 */ - __IO uint32_t LPM_CTRL; /**< PLL Low Port Modulator Control, offset: 0x24 */ - __IO uint32_t LPM_SDM_CTRL1; /**< PLL Low Port Sigma Delta Control 1, offset: 0x28 */ - __IO uint32_t LPM_SDM_CTRL2; /**< PLL Low Port Sigma Delta Control 2, offset: 0x2C */ - __IO uint32_t LPM_SDM_CTRL3; /**< PLL Low Port Sigma Delta Control 3, offset: 0x30 */ - __I uint32_t LPM_SDM_RES1; /**< PLL Low Port Sigma Delta Result 1, offset: 0x34 */ - __I uint32_t LPM_SDM_RES2; /**< PLL Low Port Sigma Delta Result 2, offset: 0x38 */ - __IO uint32_t DELAY_MATCH; /**< PLL Delay Matching, offset: 0x3C */ - __IO uint32_t CTUNE_CTRL; /**< PLL Coarse Tune Control, offset: 0x40 */ - __I uint32_t CTUNE_CNT6; /**< PLL Coarse Tune Count 6, offset: 0x44 */ - __I uint32_t CTUNE_CNT5_4; /**< PLL Coarse Tune Counts 5 and 4, offset: 0x48 */ - __I uint32_t CTUNE_CNT3_2; /**< PLL Coarse Tune Counts 3 and 2, offset: 0x4C */ - __I uint32_t CTUNE_CNT1_0; /**< PLL Coarse Tune Counts 1 and 0, offset: 0x50 */ - __I uint32_t CTUNE_RES; /**< PLL Coarse Tune Results, offset: 0x54 */ -} XCVR_PLL_DIG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_PLL_DIG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PLL_DIG_Register_Masks XCVR_PLL_DIG Register Masks - * @{ - */ - -/*! @name HPM_BUMP - PLL HPM Analog Bump Control */ -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK (0x7U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT (0U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK (0x70U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT (4U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK (0x300U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT (8U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK (0x3000U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT (12U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK) - -/*! @name MOD_CTRL - PLL Modulation Control */ -#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK (0x1FFFU) -#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK (0xFF0000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT (16U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK (0x8000000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT (27U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK (0x30000000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT (28U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK (0x80000000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT (31U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK) - -/*! @name CHAN_MAP - PLL Channel Mapping */ -#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK (0x7FU) -#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT (0U) -#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_BOC_MASK (0x100U) -#define XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT (8U) -#define XCVR_PLL_DIG_CHAN_MAP_BOC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BOC_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_BMR_MASK (0x200U) -#define XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT (9U) -#define XCVR_PLL_DIG_CHAN_MAP_BMR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BMR_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK (0x400U) -#define XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT (10U) -#define XCVR_PLL_DIG_CHAN_MAP_ZOC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK) - -/*! @name LOCK_DETECT - PLL Lock Detect Control */ -#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK (0x1U) -#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT (0U) -#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK (0x2U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT (1U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK (0x4U) -#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT (2U) -#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK (0x8U) -#define XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT (3U) -#define XCVR_PLL_DIG_LOCK_DETECT_CSFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK (0x10U) -#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT (4U) -#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK (0x20U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT (5U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK (0x80U) -#define XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT (7U) -#define XCVR_PLL_DIG_LOCK_DETECT_TAFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK (0xF00U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT (8U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK (0x3F000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT (12U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK (0x80000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT (19U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK (0x3F00000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT (20U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK (0x8000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT (27U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK (0x10000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT (28U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK (0x20000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT (29U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK (0xC0000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT (30U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK) - -/*! @name HPM_CTRL - PLL High Port Modulator Control */ -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK (0x3FFU) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK (0x2000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT (13U) -#define XCVR_PLL_DIG_HPM_CTRL_HPFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK (0x4000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT (14U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK (0x70000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT (16U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK (0x100000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT (20U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK (0x800000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT (23U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK (0x3000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT (24U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK (0x8000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT (27U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK (0x10000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT (28U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK (0x80000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT (31U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK) - -/*! @name HPMCAL_CTRL - PLL High Port Calibration Control */ -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK (0x1FFFU) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT (0U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_MASK (0x2000U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_SHIFT (13U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_MASK) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK (0x4000U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT (14U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK (0x1FFF0000U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT (16U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK (0x40000000U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT (30U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_MASK (0x80000000U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_SHIFT (31U) -#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_MASK) - -/*! @name HPM_CAL1 - PLL High Port Calibration Result 1 */ -#define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK (0x7FFFFU) -#define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT (0U) -#define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK) -#define XCVR_PLL_DIG_HPM_CAL1_CS_WT_MASK (0x700000U) -#define XCVR_PLL_DIG_HPM_CAL1_CS_WT_SHIFT (20U) -#define XCVR_PLL_DIG_HPM_CAL1_CS_WT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_WT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_WT_MASK) -#define XCVR_PLL_DIG_HPM_CAL1_CS_FW_MASK (0x7000000U) -#define XCVR_PLL_DIG_HPM_CAL1_CS_FW_SHIFT (24U) -#define XCVR_PLL_DIG_HPM_CAL1_CS_FW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_FW_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_FW_MASK) -#define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_MASK (0xF0000000U) -#define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_SHIFT (28U) -#define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_MASK) - -/*! @name HPM_CAL2 - PLL High Port Calibration Result 2 */ -#define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK (0x7FFFFU) -#define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT (0U) -#define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK) -#define XCVR_PLL_DIG_HPM_CAL2_CS_RC_MASK (0x100000U) -#define XCVR_PLL_DIG_HPM_CAL2_CS_RC_SHIFT (20U) -#define XCVR_PLL_DIG_HPM_CAL2_CS_RC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_CS_RC_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_CS_RC_MASK) -#define XCVR_PLL_DIG_HPM_CAL2_CS_FT_MASK (0x1F000000U) -#define XCVR_PLL_DIG_HPM_CAL2_CS_FT_SHIFT (24U) -#define XCVR_PLL_DIG_HPM_CAL2_CS_FT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_CS_FT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_CS_FT_MASK) - -/*! @name HPM_SDM_RES - PLL High Port Sigma Delta Results */ -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK (0x3FFU) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK (0x3FF0000U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT (16U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK (0xF0000000U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT (28U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK) - -/*! @name LPM_CTRL - PLL Low Port Modulator Control */ -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK (0x3FU) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK (0x800U) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT (11U) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK (0x2000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT (13U) -#define XCVR_PLL_DIG_LPM_CTRL_LPFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK (0x4000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT (14U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK (0xF0000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT (16U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK (0x400000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT (22U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK (0x800000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT (23U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK (0xF000000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT (24U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK (0x80000000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT (31U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK) - -/*! @name LPM_SDM_CTRL1 - PLL Low Port Sigma Delta Control 1 */ -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK (0x7FU) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK (0x7F00U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT (8U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK (0x7F0000U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT (16U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK (0x80000000U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT (31U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) - -/*! @name LPM_SDM_CTRL2 - PLL Low Port Sigma Delta Control 2 */ -#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK) - -/*! @name LPM_SDM_CTRL3 - PLL Low Port Sigma Delta Control 3 */ -#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK) - -/*! @name LPM_SDM_RES1 - PLL Low Port Sigma Delta Result 1 */ -#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK) - -/*! @name LPM_SDM_RES2 - PLL Low Port Sigma Delta Result 2 */ -#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK) - -/*! @name DELAY_MATCH - PLL Delay Matching */ -#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK (0xFU) -#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT (0U) -#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK (0xF00U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT (8U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK (0xF0000U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT (16U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK) - -/*! @name CTUNE_CTRL - PLL Coarse Tune Control */ -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK (0xFFFU) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK (0xF0000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT (16U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK (0x7F000000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT (24U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK (0x80000000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT (31U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK) - -/*! @name CTUNE_CNT6 - PLL Coarse Tune Count 6 */ -#define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_MASK (0x1FFFU) -#define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_MASK) - -/*! @name CTUNE_CNT5_4 - PLL Coarse Tune Counts 5 and 4 */ -#define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_MASK (0x1FFFU) -#define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_MASK) -#define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_MASK (0x1FFF0000U) -#define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT (16U) -#define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_MASK) - -/*! @name CTUNE_CNT3_2 - PLL Coarse Tune Counts 3 and 2 */ -#define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_MASK (0x1FFFU) -#define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_MASK) -#define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_MASK (0x1FFF0000U) -#define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT (16U) -#define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_MASK) - -/*! @name CTUNE_CNT1_0 - PLL Coarse Tune Counts 1 and 0 */ -#define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_MASK (0x1FFFU) -#define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_MASK) -#define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_MASK (0x1FFF0000U) -#define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT (16U) -#define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_MASK) - -/*! @name CTUNE_RES - PLL Coarse Tune Results */ -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK (0x7FU) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK (0xFF00U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT (8U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK (0xFFF0000U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT (16U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK) - - -/*! - * @} - */ /* end of group XCVR_PLL_DIG_Register_Masks */ - - -/* XCVR_PLL_DIG - Peripheral instance base addresses */ -/** Peripheral XCVR_PLL_DIG base address */ -#define XCVR_PLL_DIG_BASE (0x4005C224u) -/** Peripheral XCVR_PLL_DIG base pointer */ -#define XCVR_PLL_DIG ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE) -/** Array initializer of XCVR_PLL_DIG peripheral base addresses */ -#define XCVR_PLL_DIG_BASE_ADDRS { XCVR_PLL_DIG_BASE } -/** Array initializer of XCVR_PLL_DIG peripheral base pointers */ -#define XCVR_PLL_DIG_BASE_PTRS { XCVR_PLL_DIG } - -/*! - * @} - */ /* end of group XCVR_PLL_DIG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_RX_DIG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_RX_DIG_Peripheral_Access_Layer XCVR_RX_DIG Peripheral Access Layer - * @{ - */ - -/** XCVR_RX_DIG - Register Layout Typedef */ -typedef struct { - __IO uint32_t RX_DIG_CTRL; /**< RX Digital Control, offset: 0x0 */ - __IO uint32_t AGC_CTRL_0; /**< AGC Control 0, offset: 0x4 */ - __IO uint32_t AGC_CTRL_1; /**< AGC Control 1, offset: 0x8 */ - __IO uint32_t AGC_CTRL_2; /**< AGC Control 2, offset: 0xC */ - __IO uint32_t AGC_CTRL_3; /**< AGC Control 3, offset: 0x10 */ - __I uint32_t AGC_STAT; /**< AGC Status, offset: 0x14 */ - __IO uint32_t RSSI_CTRL_0; /**< RSSI Control 0, offset: 0x18 */ - __I uint32_t RSSI_CTRL_1; /**< RSSI Control 1, offset: 0x1C */ - __I uint32_t RSSI_DFT; /**< RSSI DFT, offset: 0x20 */ - __IO uint32_t DCOC_CTRL_0; /**< DCOC Control 0, offset: 0x24 */ - __IO uint32_t DCOC_CTRL_1; /**< DCOC Control 1, offset: 0x28 */ - __IO uint32_t DCOC_DAC_INIT; /**< DCOC DAC Initialization, offset: 0x2C */ - __IO uint32_t DCOC_DIG_MAN; /**< DCOC Digital Correction Manual Override, offset: 0x30 */ - __IO uint32_t DCOC_CAL_GAIN; /**< DCOC Calibration Gain, offset: 0x34 */ - __I uint32_t DCOC_STAT; /**< DCOC Status, offset: 0x38 */ - __I uint32_t DCOC_DC_EST; /**< DCOC DC Estimate, offset: 0x3C */ - __IO uint32_t DCOC_CAL_RCP; /**< DCOC Calibration Reciprocals, offset: 0x40 */ - uint8_t RESERVED_0[4]; - __IO uint32_t IQMC_CTRL; /**< IQMC Control, offset: 0x48 */ - __IO uint32_t IQMC_CAL; /**< IQMC Calibration, offset: 0x4C */ - __IO uint32_t LNA_GAIN_VAL_3_0; /**< LNA_GAIN Step Values 3..0, offset: 0x50 */ - __IO uint32_t LNA_GAIN_VAL_7_4; /**< LNA_GAIN Step Values 7..4, offset: 0x54 */ - __IO uint32_t LNA_GAIN_VAL_8; /**< LNA_GAIN Step Values 8, offset: 0x58 */ - __IO uint32_t BBA_RES_TUNE_VAL_7_0; /**< BBA Resistor Tune Values 7..0, offset: 0x5C */ - __IO uint32_t BBA_RES_TUNE_VAL_10_8; /**< BBA Resistor Tune Values 10..8, offset: 0x60 */ - __IO uint32_t LNA_GAIN_LIN_VAL_2_0; /**< LNA Linear Gain Values 2..0, offset: 0x64 */ - __IO uint32_t LNA_GAIN_LIN_VAL_5_3; /**< LNA Linear Gain Values 5..3, offset: 0x68 */ - __IO uint32_t LNA_GAIN_LIN_VAL_8_6; /**< LNA Linear Gain Values 8..6, offset: 0x6C */ - __IO uint32_t LNA_GAIN_LIN_VAL_9; /**< LNA Linear Gain Values 9, offset: 0x70 */ - __IO uint32_t BBA_RES_TUNE_LIN_VAL_3_0; /**< BBA Resistor Tune Values 3..0, offset: 0x74 */ - __IO uint32_t BBA_RES_TUNE_LIN_VAL_7_4; /**< BBA Resistor Tune Values 7..4, offset: 0x78 */ - __IO uint32_t BBA_RES_TUNE_LIN_VAL_10_8; /**< BBA Resistor Tune Values 10..8, offset: 0x7C */ - __IO uint32_t AGC_GAIN_TBL_03_00; /**< AGC Gain Tables Step 03..00, offset: 0x80 */ - __IO uint32_t AGC_GAIN_TBL_07_04; /**< AGC Gain Tables Step 07..04, offset: 0x84 */ - __IO uint32_t AGC_GAIN_TBL_11_08; /**< AGC Gain Tables Step 11..08, offset: 0x88 */ - __IO uint32_t AGC_GAIN_TBL_15_12; /**< AGC Gain Tables Step 15..12, offset: 0x8C */ - __IO uint32_t AGC_GAIN_TBL_19_16; /**< AGC Gain Tables Step 19..16, offset: 0x90 */ - __IO uint32_t AGC_GAIN_TBL_23_20; /**< AGC Gain Tables Step 23..20, offset: 0x94 */ - __IO uint32_t AGC_GAIN_TBL_26_24; /**< AGC Gain Tables Step 26..24, offset: 0x98 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DCOC_OFFSET[27]; /**< DCOC Offset, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t DCOC_BBA_STEP; /**< DCOC BBA DAC Step, offset: 0x10C */ - __IO uint32_t DCOC_TZA_STEP_0; /**< DCOC TZA DAC Step 0, offset: 0x110 */ - __IO uint32_t DCOC_TZA_STEP_1; /**< DCOC TZA DAC Step 1, offset: 0x114 */ - __IO uint32_t DCOC_TZA_STEP_2; /**< DCOC TZA DAC Step 2, offset: 0x118 */ - __IO uint32_t DCOC_TZA_STEP_3; /**< DCOC TZA DAC Step 3, offset: 0x11C */ - __IO uint32_t DCOC_TZA_STEP_4; /**< DCOC TZA DAC Step 4, offset: 0x120 */ - __IO uint32_t DCOC_TZA_STEP_5; /**< DCOC TZA DAC Step 5, offset: 0x124 */ - __IO uint32_t DCOC_TZA_STEP_6; /**< DCOC TZA DAC Step 6, offset: 0x128 */ - __IO uint32_t DCOC_TZA_STEP_7; /**< DCOC TZA DAC Step 7, offset: 0x12C */ - __IO uint32_t DCOC_TZA_STEP_8; /**< DCOC TZA DAC Step 5, offset: 0x130 */ - __IO uint32_t DCOC_TZA_STEP_9; /**< DCOC TZA DAC Step 9, offset: 0x134 */ - __IO uint32_t DCOC_TZA_STEP_10; /**< DCOC TZA DAC Step 10, offset: 0x138 */ - uint8_t RESERVED_2[44]; - __I uint32_t DCOC_CAL_ALPHA; /**< DCOC Calibration Alpha, offset: 0x168 */ - __I uint32_t DCOC_CAL_BETA_Q; /**< DCOC Calibration Beta Q, offset: 0x16C */ - __I uint32_t DCOC_CAL_BETA_I; /**< DCOC Calibration Beta I, offset: 0x170 */ - __I uint32_t DCOC_CAL_GAMMA; /**< DCOC Calibration Gamma, offset: 0x174 */ - __IO uint32_t DCOC_CAL_IIR; /**< DCOC Calibration IIR, offset: 0x178 */ - uint8_t RESERVED_3[4]; - __I uint32_t DCOC_CAL[3]; /**< DCOC Calibration Result, array offset: 0x180, array step: 0x4 */ - uint8_t RESERVED_4[4]; - __IO uint32_t CCA_ED_LQI_CTRL_0; /**< RX_DIG CCA ED LQI Control Register 0, offset: 0x190 */ - __IO uint32_t CCA_ED_LQI_CTRL_1; /**< RX_DIG CCA ED LQI Control Register 1, offset: 0x194 */ - __I uint32_t CCA_ED_LQI_STAT_0; /**< RX_DIG CCA ED LQI Status Register 0, offset: 0x198 */ - uint8_t RESERVED_5[4]; - __IO uint32_t RX_CHF_COEF_0; /**< Receive Channel Filter Coefficient 0, offset: 0x1A0 */ - __IO uint32_t RX_CHF_COEF_1; /**< Receive Channel Filter Coefficient 1, offset: 0x1A4 */ - __IO uint32_t RX_CHF_COEF_2; /**< Receive Channel Filter Coefficient 2, offset: 0x1A8 */ - __IO uint32_t RX_CHF_COEF_3; /**< Receive Channel Filter Coefficient 3, offset: 0x1AC */ - __IO uint32_t RX_CHF_COEF_4; /**< Receive Channel Filter Coefficient 4, offset: 0x1B0 */ - __IO uint32_t RX_CHF_COEF_5; /**< Receive Channel Filter Coefficient 5, offset: 0x1B4 */ - __IO uint32_t RX_CHF_COEF_6; /**< Receive Channel Filter Coefficient 6, offset: 0x1B8 */ - __IO uint32_t RX_CHF_COEF_7; /**< Receive Channel Filter Coefficient 7, offset: 0x1BC */ - __IO uint32_t RX_CHF_COEF_8; /**< Receive Channel Filter Coefficient 8, offset: 0x1C0 */ - __IO uint32_t RX_CHF_COEF_9; /**< Receive Channel Filter Coefficient 9, offset: 0x1C4 */ - __IO uint32_t RX_CHF_COEF_10; /**< Receive Channel Filter Coefficient 10, offset: 0x1C8 */ - __IO uint32_t RX_CHF_COEF_11; /**< Receive Channel Filter Coefficient 11, offset: 0x1CC */ - __IO uint32_t AGC_MAN_AGC_IDX; /**< AGC Manual AGC Index, offset: 0x1D0 */ - __IO uint32_t DC_RESID_CTRL; /**< DC Residual Control, offset: 0x1D4 */ - __I uint32_t DC_RESID_EST; /**< DC Residual Estimate, offset: 0x1D8 */ - __IO uint32_t RX_RCCAL_CTRL0; /**< RX RC Calibration Control0, offset: 0x1DC */ - __IO uint32_t RX_RCCAL_CTRL1; /**< RX RC Calibration Control1, offset: 0x1E0 */ - __I uint32_t RX_RCCAL_STAT; /**< RX RC Calibration Status, offset: 0x1E4 */ - __IO uint32_t AUXPLL_FCAL_CTRL; /**< Aux PLL Frequency Calibration Control, offset: 0x1E8 */ - __I uint32_t AUXPLL_FCAL_CNT6; /**< Aux PLL Frequency Calibration Count 6, offset: 0x1EC */ - __I uint32_t AUXPLL_FCAL_CNT5_4; /**< Aux PLL Frequency Calibration Count 5 and 4, offset: 0x1F0 */ - __I uint32_t AUXPLL_FCAL_CNT3_2; /**< Aux PLL Frequency Calibration Count 3 and 2, offset: 0x1F4 */ - __I uint32_t AUXPLL_FCAL_CNT1_0; /**< Aux PLL Frequency Calibration Count 1 and 0, offset: 0x1F8 */ - __IO uint32_t RXDIG_DFT; /**< RXDIG DFT, offset: 0x1FC */ -} XCVR_RX_DIG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_RX_DIG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_RX_DIG_Register_Masks XCVR_RX_DIG Register Masks - * @{ - */ - -/*! @name RX_DIG_CTRL - RX Digital Control */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK (0x1U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT (0U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK (0x2U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT (1U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK (0x4U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT (2U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK (0x8U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT (3U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK (0x70U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT (4U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK (0x100U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT (8U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_MASK (0x200U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_SHIFT (9U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK (0x400U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT (10U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK (0x800U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT (11U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK (0x1000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT (12U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK (0x2000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT (13U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK (0x4000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT (14U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK (0x8000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT (15U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK (0x10000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT (16U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK (0x20000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT (17U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK (0x40000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT (18U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK (0x1F00000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT (20U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK (0x2000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT (25U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK (0x10000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT (28U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK (0x20000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT (29U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK (0x40000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT (30U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK (0x80000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT (31U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK) - -/*! @name AGC_CTRL_0 - AGC Control 0 */ -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK (0x1U) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK (0x6U) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT (1U) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK (0x8U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT (3U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_MASK (0x10U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_SHIFT (4U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK (0x40U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT (6U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK (0x80U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT (7U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT (8U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT (12U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK (0xFF0000U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT (16U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK (0xFF000000U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT (24U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK) - -/*! @name AGC_CTRL_1 - AGC Control 1 */ -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_MASK (0xFU) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_MASK (0xFF0U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_SHIFT (4U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT (12U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT (16U) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK (0x100000U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT (20U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK (0x200000U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT (21U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK (0x400000U) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT (22U) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK (0xFF000000U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT (24U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK) - -/*! @name AGC_CTRL_2 - AGC Control 2 */ -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK (0x1U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK (0x2U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT (1U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK (0x4U) -#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT (2U) -#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK (0xFF0U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT (4U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK (0x7000U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT (12U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK (0x38000U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT (15U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK (0x1C0000U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT (18U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK (0xE00000U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT (21U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK (0x3F000000U) -#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT (24U) -#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK (0x40000000U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT (30U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK (0x80000000U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT (31U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK) - -/*! @name AGC_CTRL_3 - AGC Control 3 */ -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK (0x1FFFU) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK (0xE000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT (13U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK (0x7F0000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT (16U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK (0xF800000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT (23U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT (28U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK) - -/*! @name AGC_STAT - AGC Status */ -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK (0x1U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT (0U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK (0x2U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT (1U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK (0x4U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT (2U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK (0x8U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT (3U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK (0x1F0U) -#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT (4U) -#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT)) & XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK) -#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK (0x200U) -#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT (9U) -#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT)) & XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK) -#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK (0xFF0000U) -#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT (16U) -#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT)) & XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK) - -/*! @name RSSI_CTRL_0 - RSSI Control 0 */ -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK (0x1U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT (0U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK (0x6U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT (1U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK (0x8U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT (3U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK (0x60U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT (5U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK (0x300U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_SHIFT (8U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK (0xFC00U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT (10U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK (0xF0000U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT (16U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK (0x700000U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT (20U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK (0xFF000000U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT (24U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) - -/*! @name RSSI_CTRL_1 - RSSI Control 1 */ -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK (0xFF000000U) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT (24U) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) - -/*! @name RSSI_DFT - RSSI DFT */ -#define XCVR_RX_DIG_RSSI_DFT_DFT_MAG_MASK (0x1FFFU) -#define XCVR_RX_DIG_RSSI_DFT_DFT_MAG_SHIFT (0U) -#define XCVR_RX_DIG_RSSI_DFT_DFT_MAG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_DFT_DFT_MAG_SHIFT)) & XCVR_RX_DIG_RSSI_DFT_DFT_MAG_MASK) -#define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_MASK (0x1FFF0000U) -#define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_SHIFT (16U) -#define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_SHIFT)) & XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_MASK) - -/*! @name DCOC_CTRL_0 - DCOC Control 0 */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK (0x1U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK (0x2U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT (1U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK (0x4U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT (2U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK (0x8U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT (3U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK (0x10U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT (4U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK (0x20U) -#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT (5U) -#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK (0x40U) -#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT (6U) -#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK (0x80U) -#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT (7U) -#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK (0x1F00U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK (0x1F0000U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK (0x7F000000U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK) - -/*! @name DCOC_CTRL_1 - DCOC Control 1 */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK (0x3U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK (0x1CU) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT (2U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK (0xE0U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT (5U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK (0x7000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT (12U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK (0x30000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK (0x1C0000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT (18U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK (0xE00000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT (21U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK (0x1F000000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK) - -/*! @name DCOC_DAC_INIT - DCOC DAC Initialization */ -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK (0x3FU) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK (0x3F00U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK (0xFF0000U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK (0xFF000000U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK) - -/*! @name DCOC_DIG_MAN - DCOC Digital Correction Manual Override */ -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK (0xFFFU) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK) - -/*! @name DCOC_CAL_GAIN - DCOC Calibration Gain */ -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK (0xF00U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK (0xF000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT (12U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK (0xF0000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK (0xF00000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT (20U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK (0xF000000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK (0xF0000000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT (28U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK) - -/*! @name DCOC_STAT - DCOC Status */ -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK (0x3FU) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK (0x3F00U) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK (0xFF0000U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK (0xFF000000U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK) - -/*! @name DCOC_DC_EST - DCOC DC Estimate */ -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK (0xFFFU) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) - -/*! @name DCOC_CAL_RCP - DCOC Calibration Reciprocals */ -#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK (0x7FFU) -#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK) -#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK (0x7FF0000U) -#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK) - -/*! @name IQMC_CTRL - IQMC Control */ -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK (0x1U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT (0U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK (0xFF00U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT (8U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK (0x7FF0000U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT (16U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK) - -/*! @name IQMC_CAL - IQMC Calibration */ -#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK (0x7FFU) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT (0U) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK (0xFFF0000U) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT (16U) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK) - -/*! @name LNA_GAIN_VAL_3_0 - LNA_GAIN Step Values 3..0 */ -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK (0xFFU) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK (0xFF00U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT (8U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK (0xFF0000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT (16U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK (0xFF000000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT (24U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK) - -/*! @name LNA_GAIN_VAL_7_4 - LNA_GAIN Step Values 7..4 */ -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK (0xFFU) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK (0xFF00U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT (8U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK (0xFF0000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT (16U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK (0xFF000000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT (24U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK) - -/*! @name LNA_GAIN_VAL_8 - LNA_GAIN Step Values 8 */ -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK (0xFFU) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK (0xFF00U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT (8U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK) - -/*! @name BBA_RES_TUNE_VAL_7_0 - BBA Resistor Tune Values 7..0 */ -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK (0xFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK (0xF0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT (4U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK (0xF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK (0xF000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT (12U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK (0xF0000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT (16U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK (0xF00000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT (20U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK (0xF000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT (24U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK (0xF0000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT (28U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK) - -/*! @name BBA_RES_TUNE_VAL_10_8 - BBA Resistor Tune Values 10..8 */ -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK (0xFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK (0xF0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT (4U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK (0xF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK) - -/*! @name LNA_GAIN_LIN_VAL_2_0 - LNA Linear Gain Values 2..0 */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK (0xFFC00U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT (10U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK (0x3FF00000U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT (20U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK) - -/*! @name LNA_GAIN_LIN_VAL_5_3 - LNA Linear Gain Values 5..3 */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK (0xFFC00U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT (10U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK (0x3FF00000U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT (20U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK) - -/*! @name LNA_GAIN_LIN_VAL_8_6 - LNA Linear Gain Values 8..6 */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK (0xFFC00U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT (10U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK (0x3FF00000U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT (20U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK) - -/*! @name LNA_GAIN_LIN_VAL_9 - LNA Linear Gain Values 9 */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK) - -/*! @name BBA_RES_TUNE_LIN_VAL_3_0 - BBA Resistor Tune Values 3..0 */ -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK (0xFFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK (0xFF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK (0xFF0000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT (16U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK (0xFF000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT (24U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK) - -/*! @name BBA_RES_TUNE_LIN_VAL_7_4 - BBA Resistor Tune Values 7..4 */ -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK (0xFFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK (0xFF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK (0xFF0000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT (16U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK (0xFF000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT (24U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK) - -/*! @name BBA_RES_TUNE_LIN_VAL_10_8 - BBA Resistor Tune Values 10..8 */ -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK (0x3FFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK (0xFFC00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT (10U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK (0x3FF00000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT (20U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK) - -/*! @name AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00 */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK) - -/*! @name AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04 */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK) - -/*! @name AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08 */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK) - -/*! @name AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12 */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK) - -/*! @name AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16 */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK) - -/*! @name AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20 */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK) - -/*! @name AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24 */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK) - -/*! @name DCOC_OFFSET - DCOC Offset */ -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK (0x3FU) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK (0x3F00U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK (0xFF0000U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK (0xFF000000U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK) - -/* The count of XCVR_RX_DIG_DCOC_OFFSET */ -#define XCVR_RX_DIG_DCOC_OFFSET_COUNT (27U) - -/*! @name DCOC_BBA_STEP - DCOC BBA DAC Step */ -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK (0x1FF0000U) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK) - -/*! @name DCOC_TZA_STEP_0 - DCOC TZA DAC Step 0 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK) - -/*! @name DCOC_TZA_STEP_1 - DCOC TZA DAC Step 1 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK) - -/*! @name DCOC_TZA_STEP_2 - DCOC TZA DAC Step 2 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK) - -/*! @name DCOC_TZA_STEP_3 - DCOC TZA DAC Step 3 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK) - -/*! @name DCOC_TZA_STEP_4 - DCOC TZA DAC Step 4 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK) - -/*! @name DCOC_TZA_STEP_5 - DCOC TZA DAC Step 5 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK) - -/*! @name DCOC_TZA_STEP_6 - DCOC TZA DAC Step 6 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK) - -/*! @name DCOC_TZA_STEP_7 - DCOC TZA DAC Step 7 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK (0x1FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK) - -/*! @name DCOC_TZA_STEP_8 - DCOC TZA DAC Step 5 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK (0x1FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK) - -/*! @name DCOC_TZA_STEP_9 - DCOC TZA DAC Step 9 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK (0x3FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK) - -/*! @name DCOC_TZA_STEP_10 - DCOC TZA DAC Step 10 */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK (0x3FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK) - -/*! @name DCOC_CAL_ALPHA - DCOC Calibration Alpha */ -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK (0x7FFU) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK (0x7FF0000U) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK) - -/*! @name DCOC_CAL_BETA_Q - DCOC Calibration Beta Q */ -#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK (0x1FFFFU) -#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK) - -/*! @name DCOC_CAL_BETA_I - DCOC Calibration Beta I */ -#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK (0x1FFFFU) -#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK) - -/*! @name DCOC_CAL_GAMMA - DCOC Calibration Gamma */ -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK (0xFFFFU) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK (0xFFFF0000U) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK) - -/*! @name DCOC_CAL_IIR - DCOC Calibration IIR */ -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK (0x3U) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK (0xCU) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT (2U) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK (0x30U) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT (4U) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK) - -/*! @name DCOC_CAL - DCOC Calibration Result */ -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK (0xFFFU) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK) - -/* The count of XCVR_RX_DIG_DCOC_CAL */ -#define XCVR_RX_DIG_DCOC_CAL_COUNT (3U) - -/*! @name CCA_ED_LQI_CTRL_0 - RX_DIG CCA ED LQI Control Register 0 */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK (0xFFU) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT (0U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK (0xFF00U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT (8U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK (0xFF0000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT (16U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK (0x3F000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT (24U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK) - -/*! @name CCA_ED_LQI_CTRL_1 - RX_DIG CCA ED LQI Control Register 1 */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK (0x3FU) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT (0U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK (0x1C0U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT (6U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK (0xE00U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT (9U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK (0xF000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT (12U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK (0x10000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT (16U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK (0x20000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT (17U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK (0x40000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT (18U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK (0x80000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT (19U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK (0x100000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT (20U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_MASK (0x200000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_SHIFT (21U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK (0xF000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT (24U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK (0xF0000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT (28U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK) - -/*! @name CCA_ED_LQI_STAT_0 - RX_DIG CCA ED LQI Status Register 0 */ -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK (0xFFU) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT (0U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK (0xFF00U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT (8U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK (0xFF0000U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT (16U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK (0x1000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT (24U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK (0x2000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT (25U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK) - -/*! @name RX_CHF_COEF_0 - Receive Channel Filter Coefficient 0 */ -#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK (0x3FU) -#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK) - -/*! @name RX_CHF_COEF_1 - Receive Channel Filter Coefficient 1 */ -#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK (0x3FU) -#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK) - -/*! @name RX_CHF_COEF_2 - Receive Channel Filter Coefficient 2 */ -#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK) - -/*! @name RX_CHF_COEF_3 - Receive Channel Filter Coefficient 3 */ -#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK) - -/*! @name RX_CHF_COEF_4 - Receive Channel Filter Coefficient 4 */ -#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK) - -/*! @name RX_CHF_COEF_5 - Receive Channel Filter Coefficient 5 */ -#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK) - -/*! @name RX_CHF_COEF_6 - Receive Channel Filter Coefficient 6 */ -#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK (0xFFU) -#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK) - -/*! @name RX_CHF_COEF_7 - Receive Channel Filter Coefficient 7 */ -#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK (0xFFU) -#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK) - -/*! @name RX_CHF_COEF_8 - Receive Channel Filter Coefficient 8 */ -#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK (0x1FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK) - -/*! @name RX_CHF_COEF_9 - Receive Channel Filter Coefficient 9 */ -#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK (0x1FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK) - -/*! @name RX_CHF_COEF_10 - Receive Channel Filter Coefficient 10 */ -#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK (0x3FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK) - -/*! @name RX_CHF_COEF_11 - Receive Channel Filter Coefficient 11 */ -#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK (0x3FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK) - -/*! @name AGC_MAN_AGC_IDX - AGC Manual AGC Index */ -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK (0x1F0000U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT (16U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK (0x1000000U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT (24U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK (0x2000000U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT (25U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK) - -/*! @name DC_RESID_CTRL - DC Residual Control */ -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK (0x7FU) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT (0U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK (0xF00U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT (8U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK (0x7000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT (12U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK (0x70000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT (16U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK (0x100000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT (20U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK (0x1F000000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT (24U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK) - -/*! @name DC_RESID_EST - DC Residual Estimate */ -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK (0x1FFFU) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT (0U) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK (0x1FFF0000U) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT (16U) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK) - -/*! @name RX_RCCAL_CTRL0 - RX RC Calibration Control0 */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK (0xFU) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT (0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK (0x1F0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT (4U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK (0x200U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT (9U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK (0x3000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT (12U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK (0x8000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT (15U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK (0xF0000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT (16U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK (0x1F00000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT (20U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK (0x2000000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT (25U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK) - -/*! @name RX_RCCAL_CTRL1 - RX RC Calibration Control1 */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK (0xFU) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT (0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK (0x1F0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT (4U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK (0x200U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT (9U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK (0xF0000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT (16U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK (0x1F00000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT (20U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK (0x2000000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT (25U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK) - -/*! @name RX_RCCAL_STAT - RX RC Calibration Status */ -#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK (0x1FU) -#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT (0U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK (0x3E0U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT (5U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK (0x7C00U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT (10U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK (0x1F0000U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT (16U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK (0x3E00000U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT (21U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK) - -/*! @name AUXPLL_FCAL_CTRL - Aux PLL Frequency Calibration Control */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK (0x7FU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK (0x80U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT (7U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK (0x100U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT (8U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK (0x200U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT (9U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK (0xC00U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT (10U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK (0x7F0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK) - -/*! @name AUXPLL_FCAL_CNT6 - Aux PLL Frequency Calibration Count 6 */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK) - -/*! @name AUXPLL_FCAL_CNT5_4 - Aux PLL Frequency Calibration Count 5 and 4 */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK) - -/*! @name AUXPLL_FCAL_CNT3_2 - Aux PLL Frequency Calibration Count 3 and 2 */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK) - -/*! @name AUXPLL_FCAL_CNT1_0 - Aux PLL Frequency Calibration Count 1 and 0 */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK) - -/*! @name RXDIG_DFT - RXDIG DFT */ -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_MASK (0x7U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_SHIFT (0U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_MASK) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_MASK (0x8U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_SHIFT (3U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_MASK) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_MASK (0x10U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_SHIFT (4U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_MASK) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_MASK (0x20U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_SHIFT (5U) -#define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_MASK) - - -/*! - * @} - */ /* end of group XCVR_RX_DIG_Register_Masks */ - - -/* XCVR_RX_DIG - Peripheral instance base addresses */ -/** Peripheral XCVR_RX_DIG base address */ -#define XCVR_RX_DIG_BASE (0x4005C000u) -/** Peripheral XCVR_RX_DIG base pointer */ -#define XCVR_RX_DIG ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE) -/** Array initializer of XCVR_RX_DIG peripheral base addresses */ -#define XCVR_RX_DIG_BASE_ADDRS { XCVR_RX_DIG_BASE } -/** Array initializer of XCVR_RX_DIG peripheral base pointers */ -#define XCVR_RX_DIG_BASE_PTRS { XCVR_RX_DIG } - -/*! - * @} - */ /* end of group XCVR_RX_DIG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_TSM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TSM_Peripheral_Access_Layer XCVR_TSM Peripheral Access Layer - * @{ - */ - -/** XCVR_TSM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< TRANSCEIVER SEQUENCE MANAGER CONTROL, offset: 0x0 */ - __IO uint32_t END_OF_SEQ; /**< TSM END OF SEQUENCE, offset: 0x4 */ - __IO uint32_t OVRD0; /**< TSM OVERRIDE REGISTER 0, offset: 0x8 */ - __IO uint32_t OVRD1; /**< TSM OVERRIDE REGISTER 1, offset: 0xC */ - __IO uint32_t OVRD2; /**< TSM OVERRIDE REGISTER 2, offset: 0x10 */ - __IO uint32_t OVRD3; /**< TSM OVERRIDE REGISTER 3, offset: 0x14 */ - __IO uint32_t PA_POWER; /**< PA POWER, offset: 0x18 */ - __IO uint32_t PA_RAMP_TBL0; /**< PA RAMP TABLE 0, offset: 0x1C */ - __IO uint32_t PA_RAMP_TBL1; /**< PA RAMP TABLE 1, offset: 0x20 */ - __IO uint32_t RECYCLE_COUNT; /**< TSM RECYCLE COUNT, offset: 0x24 */ - __IO uint32_t FAST_CTRL1; /**< TSM FAST WARMUP CONTROL REGISTER 1, offset: 0x28 */ - __IO uint32_t FAST_CTRL2; /**< TSM FAST WARMUP CONTROL REGISTER 2, offset: 0x2C */ - __IO uint32_t TIMING00; /**< TSM_TIMING00, offset: 0x30 */ - __IO uint32_t TIMING01; /**< TSM_TIMING01, offset: 0x34 */ - __IO uint32_t TIMING02; /**< TSM_TIMING02, offset: 0x38 */ - __IO uint32_t TIMING03; /**< TSM_TIMING03, offset: 0x3C */ - __IO uint32_t TIMING04; /**< TSM_TIMING04, offset: 0x40 */ - __IO uint32_t TIMING05; /**< TSM_TIMING05, offset: 0x44 */ - __IO uint32_t TIMING06; /**< TSM_TIMING06, offset: 0x48 */ - __IO uint32_t TIMING07; /**< TSM_TIMING07, offset: 0x4C */ - __IO uint32_t TIMING08; /**< TSM_TIMING08, offset: 0x50 */ - __IO uint32_t TIMING09; /**< TSM_TIMING09, offset: 0x54 */ - __IO uint32_t TIMING10; /**< TSM_TIMING10, offset: 0x58 */ - __IO uint32_t TIMING11; /**< TSM_TIMING11, offset: 0x5C */ - __IO uint32_t TIMING12; /**< TSM_TIMING12, offset: 0x60 */ - __IO uint32_t TIMING13; /**< TSM_TIMING13, offset: 0x64 */ - __IO uint32_t TIMING14; /**< TSM_TIMING14, offset: 0x68 */ - __IO uint32_t TIMING15; /**< TSM_TIMING15, offset: 0x6C */ - __IO uint32_t TIMING16; /**< TSM_TIMING16, offset: 0x70 */ - __IO uint32_t TIMING17; /**< TSM_TIMING17, offset: 0x74 */ - __IO uint32_t TIMING18; /**< TSM_TIMING18, offset: 0x78 */ - __IO uint32_t TIMING19; /**< TSM_TIMING19, offset: 0x7C */ - __IO uint32_t TIMING20; /**< TSM_TIMING20, offset: 0x80 */ - __IO uint32_t TIMING21; /**< TSM_TIMING21, offset: 0x84 */ - __IO uint32_t TIMING22; /**< TSM_TIMING22, offset: 0x88 */ - __IO uint32_t TIMING23; /**< TSM_TIMING23, offset: 0x8C */ - __IO uint32_t TIMING24; /**< TSM_TIMING24, offset: 0x90 */ - __IO uint32_t TIMING25; /**< TSM_TIMING25, offset: 0x94 */ - __IO uint32_t TIMING26; /**< TSM_TIMING26, offset: 0x98 */ - __IO uint32_t TIMING27; /**< TSM_TIMING27, offset: 0x9C */ - __IO uint32_t TIMING28; /**< TSM_TIMING28, offset: 0xA0 */ - __IO uint32_t TIMING29; /**< TSM_TIMING29, offset: 0xA4 */ - __IO uint32_t TIMING30; /**< TSM_TIMING30, offset: 0xA8 */ - __IO uint32_t TIMING31; /**< TSM_TIMING31, offset: 0xAC */ - __IO uint32_t TIMING32; /**< TSM_TIMING32, offset: 0xB0 */ - __IO uint32_t TIMING33; /**< TSM_TIMING33, offset: 0xB4 */ - __IO uint32_t TIMING34; /**< TSM_TIMING34, offset: 0xB8 */ - __IO uint32_t TIMING35; /**< TSM_TIMING35, offset: 0xBC */ - __IO uint32_t TIMING36; /**< TSM_TIMING36, offset: 0xC0 */ - __IO uint32_t TIMING37; /**< TSM_TIMING37, offset: 0xC4 */ - __IO uint32_t TIMING38; /**< TSM_TIMING38, offset: 0xC8 */ - __IO uint32_t TIMING39; /**< TSM_TIMING39, offset: 0xCC */ - __IO uint32_t TIMING40; /**< TSM_TIMING40, offset: 0xD0 */ - __IO uint32_t TIMING41; /**< TSM_TIMING41, offset: 0xD4 */ - __IO uint32_t TIMING42; /**< TSM_TIMING42, offset: 0xD8 */ - __IO uint32_t TIMING43; /**< TSM_TIMING43, offset: 0xDC */ - __IO uint32_t TIMING44; /**< TSM_TIMING44, offset: 0xE0 */ - __IO uint32_t TIMING45; /**< TSM_TIMING45, offset: 0xE4 */ - __IO uint32_t TIMING46; /**< TSM_TIMING46, offset: 0xE8 */ - __IO uint32_t TIMING47; /**< TSM_TIMING47, offset: 0xEC */ - __IO uint32_t TIMING48; /**< TSM_TIMING48, offset: 0xF0 */ - __IO uint32_t TIMING49; /**< TSM_TIMING49, offset: 0xF4 */ - __IO uint32_t TIMING50; /**< TSM_TIMING50, offset: 0xF8 */ - __IO uint32_t TIMING51; /**< TSM_TIMING51, offset: 0xFC */ - __IO uint32_t TIMING52; /**< TSM_TIMING52, offset: 0x100 */ - __IO uint32_t TIMING53; /**< TSM_TIMING53, offset: 0x104 */ - __IO uint32_t TIMING54; /**< TSM_TIMING54, offset: 0x108 */ - __IO uint32_t TIMING55; /**< TSM_TIMING55, offset: 0x10C */ - __IO uint32_t TIMING56; /**< TSM_TIMING56, offset: 0x110 */ - __IO uint32_t TIMING57; /**< TSM_TIMING57, offset: 0x114 */ - __IO uint32_t TIMING58; /**< TSM_TIMING58, offset: 0x118 */ -} XCVR_TSM_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_TSM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TSM_Register_Masks XCVR_TSM Register Masks - * @{ - */ - -/*! @name CTRL - TRANSCEIVER SEQUENCE MANAGER CONTROL */ -#define XCVR_TSM_CTRL_FORCE_TX_EN_MASK (0x4U) -#define XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT (2U) -#define XCVR_TSM_CTRL_FORCE_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK) -#define XCVR_TSM_CTRL_FORCE_RX_EN_MASK (0x8U) -#define XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT (3U) -#define XCVR_TSM_CTRL_FORCE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_RX_EN_MASK) -#define XCVR_TSM_CTRL_PA_RAMP_SEL_MASK (0x30U) -#define XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT (4U) -#define XCVR_TSM_CTRL_PA_RAMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT)) & XCVR_TSM_CTRL_PA_RAMP_SEL_MASK) -#define XCVR_TSM_CTRL_DATA_PADDING_EN_MASK (0xC0U) -#define XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT (6U) -#define XCVR_TSM_CTRL_DATA_PADDING_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT)) & XCVR_TSM_CTRL_DATA_PADDING_EN_MASK) -#define XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK (0x100U) -#define XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT (8U) -#define XCVR_TSM_CTRL_TSM_IRQ0_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK) -#define XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK (0x200U) -#define XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT (9U) -#define XCVR_TSM_CTRL_TSM_IRQ1_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK) -#define XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK (0xF000U) -#define XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT (12U) -#define XCVR_TSM_CTRL_RAMP_DN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT)) & XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK) -#define XCVR_TSM_CTRL_TX_ABORT_DIS_MASK (0x10000U) -#define XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT (16U) -#define XCVR_TSM_CTRL_TX_ABORT_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_TX_ABORT_DIS_MASK) -#define XCVR_TSM_CTRL_RX_ABORT_DIS_MASK (0x20000U) -#define XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT (17U) -#define XCVR_TSM_CTRL_RX_ABORT_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_RX_ABORT_DIS_MASK) -#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK (0x40000U) -#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT (18U) -#define XCVR_TSM_CTRL_ABORT_ON_CTUNE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK) -#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK (0x80000U) -#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT (19U) -#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK) -#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK (0x100000U) -#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT (20U) -#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK) -#define XCVR_TSM_CTRL_BKPT_MASK (0xFF000000U) -#define XCVR_TSM_CTRL_BKPT_SHIFT (24U) -#define XCVR_TSM_CTRL_BKPT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_BKPT_SHIFT)) & XCVR_TSM_CTRL_BKPT_MASK) - -/*! @name END_OF_SEQ - TSM END OF SEQUENCE */ -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK (0xFFU) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT (0U) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK (0xFF00U) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT (8U) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK (0xFF0000U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT (16U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK (0xFF000000U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT (24U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK) - -/*! @name OVRD0 - TSM OVERRIDE REGISTER 0 */ -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT (0U) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT (2U) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT (4U) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT (6U) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT (8U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT (10U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT (12U) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT (13U) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT (14U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT (16U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT (18U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT (20U) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT (22U) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT (24U) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT (26U) -#define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT (28U) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT (30U) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK) - -/*! @name OVRD1 - TSM OVERRIDE REGISTER 1 */ -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT (0U) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT (2U) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT (4U) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT (6U) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT (8U) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT (10U) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT (12U) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT (13U) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT (14U) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT (16U) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT (18U) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT (20U) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT (22U) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT (24U) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT (26U) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT (28U) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT (30U) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK) - -/*! @name OVRD2 - TSM OVERRIDE REGISTER 2 */ -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT (0U) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT (2U) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT (4U) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT (6U) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT (8U) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT (10U) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT (12U) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT (13U) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT (14U) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT (16U) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT (18U) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT (20U) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT (22U) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT (24U) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT (26U) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT (28U) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT (30U) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK) - -/*! @name OVRD3 - TSM OVERRIDE REGISTER 3 */ -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT (0U) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT (2U) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT (4U) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT (6U) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT (8U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT (10U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT (12U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT (13U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT (14U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT (16U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT (18U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT (20U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT (22U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT (24U) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT (26U) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT (28U) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT (30U) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK) - -/*! @name PA_POWER - PA POWER */ -#define XCVR_TSM_PA_POWER_PA_POWER_MASK (0x3FU) -#define XCVR_TSM_PA_POWER_PA_POWER_SHIFT (0U) -#define XCVR_TSM_PA_POWER_PA_POWER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_POWER_PA_POWER_SHIFT)) & XCVR_TSM_PA_POWER_PA_POWER_MASK) - -/*! @name PA_RAMP_TBL0 - PA RAMP TABLE 0 */ -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK (0x3FU) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT (0U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK (0x3F00U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT (8U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK (0x3F0000U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT (16U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK (0x3F000000U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT (24U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK) - -/*! @name PA_RAMP_TBL1 - PA RAMP TABLE 1 */ -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK (0x3FU) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT (0U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK (0x3F00U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT (8U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK (0x3F0000U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT (16U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK (0x3F000000U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT (24U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK) - -/*! @name RECYCLE_COUNT - TSM RECYCLE COUNT */ -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK (0xFFU) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT (0U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK (0xFF00U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT (8U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK (0xFF0000U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT (16U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK) - -/*! @name FAST_CTRL1 - TSM FAST WARMUP CONTROL REGISTER 1 */ -#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK (0x1U) -#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT (0U) -#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK (0x2U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT (1U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK (0x4U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT (2U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK (0x8U) -#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT (3U) -#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK (0xFF00U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT (8U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK) - -/*! @name FAST_CTRL2 - TSM FAST WARMUP CONTROL REGISTER 2 */ -#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK (0xFFU) -#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT (0U) -#define XCVR_TSM_FAST_CTRL2_FAST_START_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK (0xFF00U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT (8U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK) -#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK (0xFF0000U) -#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT (16U) -#define XCVR_TSM_FAST_CTRL2_FAST_START_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK (0xFF000000U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT (24U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK) - -/*! @name TIMING00 - TSM_TIMING00 */ -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK) - -/*! @name TIMING01 - TSM_TIMING01 */ -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK) - -/*! @name TIMING02 - TSM_TIMING02 */ -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK) - -/*! @name TIMING03 - TSM_TIMING03 */ -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK) - -/*! @name TIMING04 - TSM_TIMING04 */ -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK) - -/*! @name TIMING05 - TSM_TIMING05 */ -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK) - -/*! @name TIMING06 - TSM_TIMING06 */ -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK) - -/*! @name TIMING07 - TSM_TIMING07 */ -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK) - -/*! @name TIMING08 - TSM_TIMING08 */ -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK) - -/*! @name TIMING09 - TSM_TIMING09 */ -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK) - -/*! @name TIMING10 - TSM_TIMING10 */ -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK) - -/*! @name TIMING11 - TSM_TIMING11 */ -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK) - -/*! @name TIMING12 - TSM_TIMING12 */ -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK) - -/*! @name TIMING13 - TSM_TIMING13 */ -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_MASK) - -/*! @name TIMING14 - TSM_TIMING14 */ -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK) - -/*! @name TIMING15 - TSM_TIMING15 */ -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK) - -/*! @name TIMING16 - TSM_TIMING16 */ -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK) - -/*! @name TIMING17 - TSM_TIMING17 */ -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK) - -/*! @name TIMING18 - TSM_TIMING18 */ -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK) - -/*! @name TIMING19 - TSM_TIMING19 */ -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK) - -/*! @name TIMING20 - TSM_TIMING20 */ -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK) - -/*! @name TIMING21 - TSM_TIMING21 */ -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK) - -/*! @name TIMING22 - TSM_TIMING22 */ -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK) - -/*! @name TIMING23 - TSM_TIMING23 */ -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK) - -/*! @name TIMING24 - TSM_TIMING24 */ -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK) - -/*! @name TIMING25 - TSM_TIMING25 */ -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK) - -/*! @name TIMING26 - TSM_TIMING26 */ -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK) - -/*! @name TIMING27 - TSM_TIMING27 */ -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK) - -/*! @name TIMING28 - TSM_TIMING28 */ -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK) - -/*! @name TIMING29 - TSM_TIMING29 */ -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK) - -/*! @name TIMING30 - TSM_TIMING30 */ -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK) - -/*! @name TIMING31 - TSM_TIMING31 */ -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK) - -/*! @name TIMING32 - TSM_TIMING32 */ -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK) - -/*! @name TIMING33 - TSM_TIMING33 */ -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK) - -/*! @name TIMING34 - TSM_TIMING34 */ -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK) - -/*! @name TIMING35 - TSM_TIMING35 */ -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK) - -/*! @name TIMING36 - TSM_TIMING36 */ -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK) - -/*! @name TIMING37 - TSM_TIMING37 */ -#define XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK) -#define XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK) - -/*! @name TIMING38 - TSM_TIMING38 */ -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK) - -/*! @name TIMING39 - TSM_TIMING39 */ -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK) - -/*! @name TIMING40 - TSM_TIMING40 */ -#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK) - -/*! @name TIMING41 - TSM_TIMING41 */ -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK) - -/*! @name TIMING42 - TSM_TIMING42 */ -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK) - -/*! @name TIMING43 - TSM_TIMING43 */ -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK) - -/*! @name TIMING44 - TSM_TIMING44 */ -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK) - -/*! @name TIMING45 - TSM_TIMING45 */ -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK) - -/*! @name TIMING46 - TSM_TIMING46 */ -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK) - -/*! @name TIMING47 - TSM_TIMING47 */ -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK) - -/*! @name TIMING48 - TSM_TIMING48 */ -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK) - -/*! @name TIMING49 - TSM_TIMING49 */ -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK) - -/*! @name TIMING50 - TSM_TIMING50 */ -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK) - -/*! @name TIMING51 - TSM_TIMING51 */ -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK) - -/*! @name TIMING52 - TSM_TIMING52 */ -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK) - -/*! @name TIMING53 - TSM_TIMING53 */ -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK) - -/*! @name TIMING54 - TSM_TIMING54 */ -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK) - -/*! @name TIMING55 - TSM_TIMING55 */ -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK) - -/*! @name TIMING56 - TSM_TIMING56 */ -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK) - -/*! @name TIMING57 - TSM_TIMING57 */ -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK) - -/*! @name TIMING58 - TSM_TIMING58 */ -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK) - - -/*! - * @} - */ /* end of group XCVR_TSM_Register_Masks */ - - -/* XCVR_TSM - Peripheral instance base addresses */ -/** Peripheral XCVR_TSM base address */ -#define XCVR_TSM_BASE (0x4005C2C0u) -/** Peripheral XCVR_TSM base pointer */ -#define XCVR_TSM ((XCVR_TSM_Type *)XCVR_TSM_BASE) -/** Array initializer of XCVR_TSM peripheral base addresses */ -#define XCVR_TSM_BASE_ADDRS { XCVR_TSM_BASE } -/** Array initializer of XCVR_TSM peripheral base pointers */ -#define XCVR_TSM_BASE_PTRS { XCVR_TSM } - -/*! - * @} - */ /* end of group XCVR_TSM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_TX_DIG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TX_DIG_Peripheral_Access_Layer XCVR_TX_DIG Peripheral Access Layer - * @{ - */ - -/** XCVR_TX_DIG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< TX Digital Control, offset: 0x0 */ - __IO uint32_t DATA_PADDING; /**< TX Data Padding, offset: 0x4 */ - __IO uint32_t GFSK_CTRL; /**< TX GFSK Modulator Control, offset: 0x8 */ - __IO uint32_t GFSK_COEFF2; /**< TX GFSK Filter Coefficients 2, offset: 0xC */ - __IO uint32_t GFSK_COEFF1; /**< TX GFSK Filter Coefficients 1, offset: 0x10 */ - __IO uint32_t FSK_SCALE; /**< TX FSK Modulation Levels, offset: 0x14 */ - __IO uint32_t DFT_PATTERN; /**< TX DFT Modulation Pattern, offset: 0x18 */ - __IO uint32_t RF_DFT_BIST_1; /**< TX DFT Control 1, offset: 0x1C */ - __IO uint32_t RF_DFT_BIST_2; /**< TX DFT Control 2, offset: 0x20 */ -} XCVR_TX_DIG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_TX_DIG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TX_DIG_Register_Masks XCVR_TX_DIG Register Masks - * @{ - */ - -/*! @name CTRL - TX Digital Control */ -#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK (0xFU) -#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT (0U) -#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT)) & XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK) -#define XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK (0x70U) -#define XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT (4U) -#define XCVR_TX_DIG_CTRL_LFSR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK) -#define XCVR_TX_DIG_CTRL_LFSR_EN_MASK (0x80U) -#define XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT (7U) -#define XCVR_TX_DIG_CTRL_LFSR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_EN_MASK) -#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK (0x700U) -#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT (8U) -#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK) -#define XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK (0x800U) -#define XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT (11U) -#define XCVR_TX_DIG_CTRL_TX_DFT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT)) & XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK) -#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK (0x3000U) -#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT (12U) -#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK) -#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK (0x10000U) -#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT (16U) -#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT)) & XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK) -#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK (0xFFC00000U) -#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT (22U) -#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT)) & XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK) - -/*! @name DATA_PADDING - TX Data Padding */ -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK (0xFFU) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT (0U) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK (0xFF00U) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT (8U) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK) -#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK (0x7FFF0000U) -#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT (16U) -#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK) -#define XCVR_TX_DIG_DATA_PADDING_LRM_MASK (0x80000000U) -#define XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT (31U) -#define XCVR_TX_DIG_DATA_PADDING_LRM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_LRM_MASK) - -/*! @name GFSK_CTRL - TX GFSK Modulator Control */ -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK (0xFFFFU) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT (0U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK (0x30000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT (16U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK (0x100000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT (20U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK (0x200000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT (21U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK (0x7000000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT (24U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK (0x10000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT (28U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK (0x20000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT (29U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK (0x40000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT (30U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK (0x80000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT (31U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK) - -/*! @name GFSK_COEFF2 - TX GFSK Filter Coefficients 2 */ -#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK (0xFFFFFFFFU) -#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT (0U) -#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK) - -/*! @name GFSK_COEFF1 - TX GFSK Filter Coefficients 1 */ -#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK (0xFFFFFFFFU) -#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT (0U) -#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK) - -/*! @name FSK_SCALE - TX FSK Modulation Levels */ -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK (0x1FFFU) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT (0U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK (0x1FFF0000U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT (16U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK) - -/*! @name DFT_PATTERN - TX DFT Modulation Pattern */ -#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK (0xFFFFFFFFU) -#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT (0U) -#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT)) & XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK) - -/*! @name RF_DFT_BIST_1 - TX DFT Control 1 */ -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_MASK (0x1U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_SHIFT (0U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_MASK (0x2U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_SHIFT (1U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_MASK (0x4U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_SHIFT (2U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_MASK (0xF0U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_SHIFT (4U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_MASK (0xFF00U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_SHIFT (8U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_MASK (0x7F0000U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_SHIFT (16U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_MASK (0x7000000U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_SHIFT (24U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_MASK (0x70000000U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_SHIFT (28U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_MASK (0x80000000U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_SHIFT (31U) -#define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_MASK) - -/*! @name RF_DFT_BIST_2 - TX DFT Control 2 */ -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_MASK (0x1U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_SHIFT (0U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_MASK (0x2U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_SHIFT (1U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_MASK (0x4U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_SHIFT (2U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_MASK (0x8U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_SHIFT (3U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_MASK (0xFF0U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_SHIFT (4U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_MASK (0x1000U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_SHIFT (12U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_MASK (0x2000U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_SHIFT (13U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_MASK (0x4000U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_SHIFT (14U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_MASK (0x10000U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_SHIFT (16U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_MASK (0x20000U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_SHIFT (17U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_MASK (0x40000U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_SHIFT (18U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_MASK) -#define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_MASK (0x1FF00000U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_SHIFT (20U) -#define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_MASK) - - -/*! - * @} - */ /* end of group XCVR_TX_DIG_Register_Masks */ - - -/* XCVR_TX_DIG - Peripheral instance base addresses */ -/** Peripheral XCVR_TX_DIG base address */ -#define XCVR_TX_DIG_BASE (0x4005C200u) -/** Peripheral XCVR_TX_DIG base pointer */ -#define XCVR_TX_DIG ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE) -/** Array initializer of XCVR_TX_DIG peripheral base addresses */ -#define XCVR_TX_DIG_BASE_ADDRS { XCVR_TX_DIG_BASE } -/** Array initializer of XCVR_TX_DIG peripheral base pointers */ -#define XCVR_TX_DIG_BASE_PTRS { XCVR_TX_DIG } - -/*! - * @} - */ /* end of group XCVR_TX_DIG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_ZBDEM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ZBDEM_Peripheral_Access_Layer XCVR_ZBDEM Peripheral Access Layer - * @{ - */ - -/** XCVR_ZBDEM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CORR_CTRL; /**< 802.15.4 DEMOD CORRELLATOR CONTROL, offset: 0x0 */ - __IO uint32_t PN_TYPE; /**< 802.15.4 DEMOD PN TYPE, offset: 0x4 */ - __IO uint32_t PN_CODE; /**< 802.15.4 DEMOD PN CODE, offset: 0x8 */ - __IO uint32_t SYNC_CTRL; /**< 802.15.4 DEMOD SYMBOL SYNC CONTROL, offset: 0xC */ - __IO uint32_t CCA_LQI_SRC; /**< 802.15.4 CCA/LQI SOURCE, offset: 0x10 */ - __IO uint32_t FAD_THR; /**< FAD CORRELATOR THRESHOLD, offset: 0x14 */ - __IO uint32_t ZBDEM_AFC; /**< 802.15.4 AFC STATUS, offset: 0x18 */ -} XCVR_ZBDEM_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_ZBDEM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ZBDEM_Register_Masks XCVR_ZBDEM Register Masks - * @{ - */ - -/*! @name CORR_CTRL - 802.15.4 DEMOD CORRELLATOR CONTROL */ -#define XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK (0xFFU) -#define XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT (0U) -#define XCVR_ZBDEM_CORR_CTRL_CORR_VT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK) -#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK (0x700U) -#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT (8U) -#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK) -#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK (0x800U) -#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT (11U) -#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK) -#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK (0x8000U) -#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT (15U) -#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK (0xFF0000U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT (16U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK (0xFF000000U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT (24U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK) - -/*! @name PN_TYPE - 802.15.4 DEMOD PN TYPE */ -#define XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK (0x1U) -#define XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT (0U) -#define XCVR_ZBDEM_PN_TYPE_PN_TYPE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT)) & XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK) -#define XCVR_ZBDEM_PN_TYPE_TX_INV_MASK (0x2U) -#define XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT (1U) -#define XCVR_ZBDEM_PN_TYPE_TX_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT)) & XCVR_ZBDEM_PN_TYPE_TX_INV_MASK) - -/*! @name PN_CODE - 802.15.4 DEMOD PN CODE */ -#define XCVR_ZBDEM_PN_CODE_PN_LSB_MASK (0xFFFFU) -#define XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT (0U) -#define XCVR_ZBDEM_PN_CODE_PN_LSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_LSB_MASK) -#define XCVR_ZBDEM_PN_CODE_PN_MSB_MASK (0xFFFF0000U) -#define XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT (16U) -#define XCVR_ZBDEM_PN_CODE_PN_MSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_MSB_MASK) - -/*! @name SYNC_CTRL - 802.15.4 DEMOD SYMBOL SYNC CONTROL */ -#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK (0x7U) -#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT (0U) -#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK) -#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK (0x8U) -#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT (3U) -#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK) - -/*! @name CCA_LQI_SRC - 802.15.4 CCA/LQI SOURCE */ -#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK (0x1U) -#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT (0U) -#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK (0x2U) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT (1U) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK (0x4U) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT (2U) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK) - -/*! @name FAD_THR - FAD CORRELATOR THRESHOLD */ -#define XCVR_ZBDEM_FAD_THR_FAD_THR_MASK (0xFFU) -#define XCVR_ZBDEM_FAD_THR_FAD_THR_SHIFT (0U) -#define XCVR_ZBDEM_FAD_THR_FAD_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_THR_FAD_THR_SHIFT)) & XCVR_ZBDEM_FAD_THR_FAD_THR_MASK) - -/*! @name ZBDEM_AFC - 802.15.4 AFC STATUS */ -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK (0x1U) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT (0U) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK) -#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK (0x2U) -#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT (1U) -#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK (0x1F00U) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT (8U) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK) - - -/*! - * @} - */ /* end of group XCVR_ZBDEM_Register_Masks */ - - -/* XCVR_ZBDEM - Peripheral instance base addresses */ -/** Peripheral XCVR_ZBDEM base address */ -#define XCVR_ZBDEM_BASE (0x4005C480u) -/** Peripheral XCVR_ZBDEM base pointer */ -#define XCVR_ZBDEM ((XCVR_ZBDEM_Type *)XCVR_ZBDEM_BASE) -/** Array initializer of XCVR_ZBDEM peripheral base addresses */ -#define XCVR_ZBDEM_BASE_ADDRS { XCVR_ZBDEM_BASE } -/** Array initializer of XCVR_ZBDEM peripheral base pointers */ -#define XCVR_ZBDEM_BASE_PTRS { XCVR_ZBDEM } - -/*! - * @} - */ /* end of group XCVR_ZBDEM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ZLL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ZLL_Peripheral_Access_Layer ZLL Peripheral Access Layer - * @{ - */ - -/** ZLL - Register Layout Typedef */ -typedef struct { - __IO uint32_t IRQSTS; /**< INTERRUPT REQUEST STATUS, offset: 0x0 */ - __IO uint32_t PHY_CTRL; /**< PHY CONTROL, offset: 0x4 */ - __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x8 */ - __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0xC */ - __IO uint32_t T1CMP; /**< T1 COMPARE, offset: 0x10 */ - __IO uint32_t T2CMP; /**< T2 COMPARE, offset: 0x14 */ - __IO uint32_t T2PRIMECMP; /**< T2 PRIME COMPARE, offset: 0x18 */ - __IO uint32_t T3CMP; /**< T3 COMPARE, offset: 0x1C */ - __IO uint32_t T4CMP; /**< T4 COMPARE, offset: 0x20 */ - __IO uint32_t PA_PWR; /**< PA POWER, offset: 0x24 */ - __IO uint32_t CHANNEL_NUM0; /**< CHANNEL NUMBER 0, offset: 0x28 */ - __I uint32_t LQI_AND_RSSI; /**< LQI AND RSSI, offset: 0x2C */ - __IO uint32_t MACSHORTADDRS0; /**< MAC SHORT ADDRESS 0, offset: 0x30 */ - __IO uint32_t MACLONGADDRS0_LSB; /**< MAC LONG ADDRESS 0 LSB, offset: 0x34 */ - __IO uint32_t MACLONGADDRS0_MSB; /**< MAC LONG ADDRESS 0 MSB, offset: 0x38 */ - __IO uint32_t RX_FRAME_FILTER; /**< RECEIVE FRAME FILTER, offset: 0x3C */ - __IO uint32_t CCA_LQI_CTRL; /**< CCA AND LQI CONTROL, offset: 0x40 */ - __IO uint32_t CCA2_CTRL; /**< CCA2 CONTROL, offset: 0x44 */ - uint8_t RESERVED_0[4]; - __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x4C */ - __IO uint32_t BSM_CTRL; /**< BSM CONTROL, offset: 0x50 */ - __IO uint32_t MACSHORTADDRS1; /**< MAC SHORT ADDRESS FOR PAN1, offset: 0x54 */ - __IO uint32_t MACLONGADDRS1_LSB; /**< MAC LONG ADDRESS 1 LSB, offset: 0x58 */ - __IO uint32_t MACLONGADDRS1_MSB; /**< MAC LONG ADDRESS 1 MSB, offset: 0x5C */ - __IO uint32_t DUAL_PAN_CTRL; /**< DUAL PAN CONTROL, offset: 0x60 */ - __IO uint32_t CHANNEL_NUM1; /**< CHANNEL NUMBER 1, offset: 0x64 */ - __IO uint32_t SAM_CTRL; /**< SAM CONTROL, offset: 0x68 */ - __IO uint32_t SAM_TABLE; /**< SOURCE ADDRESS MANAGEMENT TABLE, offset: 0x6C */ - __I uint32_t SAM_MATCH; /**< SOURCE ADDRESS MANAGEMENT MATCH, offset: 0x70 */ - __I uint32_t SAM_FREE_IDX; /**< SAM FREE INDEX, offset: 0x74 */ - __IO uint32_t SEQ_CTRL_STS; /**< SEQUENCE CONTROL AND STATUS, offset: 0x78 */ - __IO uint32_t ACKDELAY; /**< ACK DELAY, offset: 0x7C */ - __IO uint32_t FILTERFAIL_CODE; /**< FILTER FAIL CODE, offset: 0x80 */ - __IO uint32_t RX_WTR_MARK; /**< RECEIVE WATER MARK, offset: 0x84 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SLOT_PRELOAD; /**< SLOT PRELOAD, offset: 0x8C */ - __I uint32_t SEQ_STATE; /**< 802.15.4 SEQUENCE STATE, offset: 0x90 */ - __IO uint32_t TMR_PRESCALE; /**< TIMER PRESCALER, offset: 0x94 */ - __IO uint32_t LENIENCY_LSB; /**< LENIENCY LSB, offset: 0x98 */ - __IO uint32_t LENIENCY_MSB; /**< LENIENCY MSB, offset: 0x9C */ - __I uint32_t PART_ID; /**< PART ID, offset: 0xA0 */ - uint8_t RESERVED_2[92]; - __IO uint16_t PKT_BUFFER_TX[64]; /**< Packet Buffer TX, array offset: 0x100, array step: 0x2 */ - __IO uint16_t PKT_BUFFER_RX[64]; /**< Packet Buffer RX, array offset: 0x180, array step: 0x2 */ -} ZLL_Type; - -/* ---------------------------------------------------------------------------- - -- ZLL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ZLL_Register_Masks ZLL Register Masks - * @{ - */ - -/*! @name IRQSTS - INTERRUPT REQUEST STATUS */ -#define ZLL_IRQSTS_SEQIRQ_MASK (0x1U) -#define ZLL_IRQSTS_SEQIRQ_SHIFT (0U) -#define ZLL_IRQSTS_SEQIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SEQIRQ_SHIFT)) & ZLL_IRQSTS_SEQIRQ_MASK) -#define ZLL_IRQSTS_TXIRQ_MASK (0x2U) -#define ZLL_IRQSTS_TXIRQ_SHIFT (1U) -#define ZLL_IRQSTS_TXIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TXIRQ_SHIFT)) & ZLL_IRQSTS_TXIRQ_MASK) -#define ZLL_IRQSTS_RXIRQ_MASK (0x4U) -#define ZLL_IRQSTS_RXIRQ_SHIFT (2U) -#define ZLL_IRQSTS_RXIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXIRQ_SHIFT)) & ZLL_IRQSTS_RXIRQ_MASK) -#define ZLL_IRQSTS_CCAIRQ_MASK (0x8U) -#define ZLL_IRQSTS_CCAIRQ_SHIFT (3U) -#define ZLL_IRQSTS_CCAIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCAIRQ_SHIFT)) & ZLL_IRQSTS_CCAIRQ_MASK) -#define ZLL_IRQSTS_RXWTRMRKIRQ_MASK (0x10U) -#define ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT (4U) -#define ZLL_IRQSTS_RXWTRMRKIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT)) & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) -#define ZLL_IRQSTS_FILTERFAIL_IRQ_MASK (0x20U) -#define ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT (5U) -#define ZLL_IRQSTS_FILTERFAIL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT)) & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) -#define ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK (0x40U) -#define ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT (6U) -#define ZLL_IRQSTS_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT)) & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK) -#define ZLL_IRQSTS_RX_FRM_PEND_MASK (0x80U) -#define ZLL_IRQSTS_RX_FRM_PEND_SHIFT (7U) -#define ZLL_IRQSTS_RX_FRM_PEND(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRM_PEND_SHIFT)) & ZLL_IRQSTS_RX_FRM_PEND_MASK) -#define ZLL_IRQSTS_WAKE_IRQ_MASK (0x100U) -#define ZLL_IRQSTS_WAKE_IRQ_SHIFT (8U) -#define ZLL_IRQSTS_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_WAKE_IRQ_SHIFT)) & ZLL_IRQSTS_WAKE_IRQ_MASK) -#define ZLL_IRQSTS_TSM_IRQ_MASK (0x400U) -#define ZLL_IRQSTS_TSM_IRQ_SHIFT (10U) -#define ZLL_IRQSTS_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TSM_IRQ_SHIFT)) & ZLL_IRQSTS_TSM_IRQ_MASK) -#define ZLL_IRQSTS_ENH_PKT_STATUS_MASK (0x800U) -#define ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT (11U) -#define ZLL_IRQSTS_ENH_PKT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT)) & ZLL_IRQSTS_ENH_PKT_STATUS_MASK) -#define ZLL_IRQSTS_PI_MASK (0x1000U) -#define ZLL_IRQSTS_PI_SHIFT (12U) -#define ZLL_IRQSTS_PI(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PI_SHIFT)) & ZLL_IRQSTS_PI_MASK) -#define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) -#define ZLL_IRQSTS_SRCADDR_SHIFT (13U) -#define ZLL_IRQSTS_SRCADDR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK) -#define ZLL_IRQSTS_CCA_MASK (0x4000U) -#define ZLL_IRQSTS_CCA_SHIFT (14U) -#define ZLL_IRQSTS_CCA(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCA_SHIFT)) & ZLL_IRQSTS_CCA_MASK) -#define ZLL_IRQSTS_CRCVALID_MASK (0x8000U) -#define ZLL_IRQSTS_CRCVALID_SHIFT (15U) -#define ZLL_IRQSTS_CRCVALID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CRCVALID_SHIFT)) & ZLL_IRQSTS_CRCVALID_MASK) -#define ZLL_IRQSTS_TMR1IRQ_MASK (0x10000U) -#define ZLL_IRQSTS_TMR1IRQ_SHIFT (16U) -#define ZLL_IRQSTS_TMR1IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1IRQ_SHIFT)) & ZLL_IRQSTS_TMR1IRQ_MASK) -#define ZLL_IRQSTS_TMR2IRQ_MASK (0x20000U) -#define ZLL_IRQSTS_TMR2IRQ_SHIFT (17U) -#define ZLL_IRQSTS_TMR2IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2IRQ_SHIFT)) & ZLL_IRQSTS_TMR2IRQ_MASK) -#define ZLL_IRQSTS_TMR3IRQ_MASK (0x40000U) -#define ZLL_IRQSTS_TMR3IRQ_SHIFT (18U) -#define ZLL_IRQSTS_TMR3IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3IRQ_SHIFT)) & ZLL_IRQSTS_TMR3IRQ_MASK) -#define ZLL_IRQSTS_TMR4IRQ_MASK (0x80000U) -#define ZLL_IRQSTS_TMR4IRQ_SHIFT (19U) -#define ZLL_IRQSTS_TMR4IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4IRQ_SHIFT)) & ZLL_IRQSTS_TMR4IRQ_MASK) -#define ZLL_IRQSTS_TMR1MSK_MASK (0x100000U) -#define ZLL_IRQSTS_TMR1MSK_SHIFT (20U) -#define ZLL_IRQSTS_TMR1MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1MSK_SHIFT)) & ZLL_IRQSTS_TMR1MSK_MASK) -#define ZLL_IRQSTS_TMR2MSK_MASK (0x200000U) -#define ZLL_IRQSTS_TMR2MSK_SHIFT (21U) -#define ZLL_IRQSTS_TMR2MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2MSK_SHIFT)) & ZLL_IRQSTS_TMR2MSK_MASK) -#define ZLL_IRQSTS_TMR3MSK_MASK (0x400000U) -#define ZLL_IRQSTS_TMR3MSK_SHIFT (22U) -#define ZLL_IRQSTS_TMR3MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3MSK_SHIFT)) & ZLL_IRQSTS_TMR3MSK_MASK) -#define ZLL_IRQSTS_TMR4MSK_MASK (0x800000U) -#define ZLL_IRQSTS_TMR4MSK_SHIFT (23U) -#define ZLL_IRQSTS_TMR4MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4MSK_SHIFT)) & ZLL_IRQSTS_TMR4MSK_MASK) -#define ZLL_IRQSTS_RX_FRAME_LENGTH_MASK (0x7F000000U) -#define ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT (24U) -#define ZLL_IRQSTS_RX_FRAME_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)) & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) - -/*! @name PHY_CTRL - PHY CONTROL */ -#define ZLL_PHY_CTRL_XCVSEQ_MASK (0x7U) -#define ZLL_PHY_CTRL_XCVSEQ_SHIFT (0U) -#define ZLL_PHY_CTRL_XCVSEQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_XCVSEQ_SHIFT)) & ZLL_PHY_CTRL_XCVSEQ_MASK) -#define ZLL_PHY_CTRL_AUTOACK_MASK (0x8U) -#define ZLL_PHY_CTRL_AUTOACK_SHIFT (3U) -#define ZLL_PHY_CTRL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_AUTOACK_SHIFT)) & ZLL_PHY_CTRL_AUTOACK_MASK) -#define ZLL_PHY_CTRL_RXACKRQD_MASK (0x10U) -#define ZLL_PHY_CTRL_RXACKRQD_SHIFT (4U) -#define ZLL_PHY_CTRL_RXACKRQD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXACKRQD_SHIFT)) & ZLL_PHY_CTRL_RXACKRQD_MASK) -#define ZLL_PHY_CTRL_CCABFRTX_MASK (0x20U) -#define ZLL_PHY_CTRL_CCABFRTX_SHIFT (5U) -#define ZLL_PHY_CTRL_CCABFRTX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCABFRTX_SHIFT)) & ZLL_PHY_CTRL_CCABFRTX_MASK) -#define ZLL_PHY_CTRL_SLOTTED_MASK (0x40U) -#define ZLL_PHY_CTRL_SLOTTED_SHIFT (6U) -#define ZLL_PHY_CTRL_SLOTTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SLOTTED_SHIFT)) & ZLL_PHY_CTRL_SLOTTED_MASK) -#define ZLL_PHY_CTRL_TMRTRIGEN_MASK (0x80U) -#define ZLL_PHY_CTRL_TMRTRIGEN_SHIFT (7U) -#define ZLL_PHY_CTRL_TMRTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMRTRIGEN_SHIFT)) & ZLL_PHY_CTRL_TMRTRIGEN_MASK) -#define ZLL_PHY_CTRL_SEQMSK_MASK (0x100U) -#define ZLL_PHY_CTRL_SEQMSK_SHIFT (8U) -#define ZLL_PHY_CTRL_SEQMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SEQMSK_SHIFT)) & ZLL_PHY_CTRL_SEQMSK_MASK) -#define ZLL_PHY_CTRL_TXMSK_MASK (0x200U) -#define ZLL_PHY_CTRL_TXMSK_SHIFT (9U) -#define ZLL_PHY_CTRL_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TXMSK_SHIFT)) & ZLL_PHY_CTRL_TXMSK_MASK) -#define ZLL_PHY_CTRL_RXMSK_MASK (0x400U) -#define ZLL_PHY_CTRL_RXMSK_SHIFT (10U) -#define ZLL_PHY_CTRL_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXMSK_SHIFT)) & ZLL_PHY_CTRL_RXMSK_MASK) -#define ZLL_PHY_CTRL_CCAMSK_MASK (0x800U) -#define ZLL_PHY_CTRL_CCAMSK_SHIFT (11U) -#define ZLL_PHY_CTRL_CCAMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCAMSK_SHIFT)) & ZLL_PHY_CTRL_CCAMSK_MASK) -#define ZLL_PHY_CTRL_RX_WMRK_MSK_MASK (0x1000U) -#define ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT (12U) -#define ZLL_PHY_CTRL_RX_WMRK_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT)) & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK) -#define ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK (0x2000U) -#define ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT (13U) -#define ZLL_PHY_CTRL_FILTERFAIL_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT)) & ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK) -#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK (0x4000U) -#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT (14U) -#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT)) & ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK) -#define ZLL_PHY_CTRL_CRC_MSK_MASK (0x8000U) -#define ZLL_PHY_CTRL_CRC_MSK_SHIFT (15U) -#define ZLL_PHY_CTRL_CRC_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CRC_MSK_SHIFT)) & ZLL_PHY_CTRL_CRC_MSK_MASK) -#define ZLL_PHY_CTRL_WAKE_MSK_MASK (0x10000U) -#define ZLL_PHY_CTRL_WAKE_MSK_SHIFT (16U) -#define ZLL_PHY_CTRL_WAKE_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_WAKE_MSK_SHIFT)) & ZLL_PHY_CTRL_WAKE_MSK_MASK) -#define ZLL_PHY_CTRL_TSM_MSK_MASK (0x40000U) -#define ZLL_PHY_CTRL_TSM_MSK_SHIFT (18U) -#define ZLL_PHY_CTRL_TSM_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TSM_MSK_SHIFT)) & ZLL_PHY_CTRL_TSM_MSK_MASK) -#define ZLL_PHY_CTRL_TMR1CMP_EN_MASK (0x100000U) -#define ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT (20U) -#define ZLL_PHY_CTRL_TMR1CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR1CMP_EN_MASK) -#define ZLL_PHY_CTRL_TMR2CMP_EN_MASK (0x200000U) -#define ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT (21U) -#define ZLL_PHY_CTRL_TMR2CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR2CMP_EN_MASK) -#define ZLL_PHY_CTRL_TMR3CMP_EN_MASK (0x400000U) -#define ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT (22U) -#define ZLL_PHY_CTRL_TMR3CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR3CMP_EN_MASK) -#define ZLL_PHY_CTRL_TMR4CMP_EN_MASK (0x800000U) -#define ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT (23U) -#define ZLL_PHY_CTRL_TMR4CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR4CMP_EN_MASK) -#define ZLL_PHY_CTRL_TC2PRIME_EN_MASK (0x1000000U) -#define ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT (24U) -#define ZLL_PHY_CTRL_TC2PRIME_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT)) & ZLL_PHY_CTRL_TC2PRIME_EN_MASK) -#define ZLL_PHY_CTRL_PROMISCUOUS_MASK (0x2000000U) -#define ZLL_PHY_CTRL_PROMISCUOUS_SHIFT (25U) -#define ZLL_PHY_CTRL_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PROMISCUOUS_SHIFT)) & ZLL_PHY_CTRL_PROMISCUOUS_MASK) -#define ZLL_PHY_CTRL_CCATYPE_MASK (0x18000000U) -#define ZLL_PHY_CTRL_CCATYPE_SHIFT (27U) -#define ZLL_PHY_CTRL_CCATYPE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCATYPE_SHIFT)) & ZLL_PHY_CTRL_CCATYPE_MASK) -#define ZLL_PHY_CTRL_PANCORDNTR0_MASK (0x20000000U) -#define ZLL_PHY_CTRL_PANCORDNTR0_SHIFT (29U) -#define ZLL_PHY_CTRL_PANCORDNTR0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PANCORDNTR0_SHIFT)) & ZLL_PHY_CTRL_PANCORDNTR0_MASK) -#define ZLL_PHY_CTRL_TC3TMOUT_MASK (0x40000000U) -#define ZLL_PHY_CTRL_TC3TMOUT_SHIFT (30U) -#define ZLL_PHY_CTRL_TC3TMOUT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC3TMOUT_SHIFT)) & ZLL_PHY_CTRL_TC3TMOUT_MASK) -#define ZLL_PHY_CTRL_TRCV_MSK_MASK (0x80000000U) -#define ZLL_PHY_CTRL_TRCV_MSK_SHIFT (31U) -#define ZLL_PHY_CTRL_TRCV_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TRCV_MSK_SHIFT)) & ZLL_PHY_CTRL_TRCV_MSK_MASK) - -/*! @name EVENT_TMR - EVENT TIMER */ -#define ZLL_EVENT_TMR_EVENT_TMR_LD_MASK (0x1U) -#define ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT (0U) -#define ZLL_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_LD_MASK) -#define ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2U) -#define ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT (1U) -#define ZLL_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK) -#define ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK (0xF0U) -#define ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT (4U) -#define ZLL_EVENT_TMR_EVENT_TMR_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK) -#define ZLL_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFF00U) -#define ZLL_EVENT_TMR_EVENT_TMR_SHIFT (8U) -#define ZLL_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_MASK) - -/*! @name TIMESTAMP - TIMESTAMP */ -#define ZLL_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU) -#define ZLL_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define ZLL_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_TIMESTAMP_TIMESTAMP_SHIFT)) & ZLL_TIMESTAMP_TIMESTAMP_MASK) - -/*! @name T1CMP - T1 COMPARE */ -#define ZLL_T1CMP_T1CMP_MASK (0xFFFFFFU) -#define ZLL_T1CMP_T1CMP_SHIFT (0U) -#define ZLL_T1CMP_T1CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T1CMP_T1CMP_SHIFT)) & ZLL_T1CMP_T1CMP_MASK) - -/*! @name T2CMP - T2 COMPARE */ -#define ZLL_T2CMP_T2CMP_MASK (0xFFFFFFU) -#define ZLL_T2CMP_T2CMP_SHIFT (0U) -#define ZLL_T2CMP_T2CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T2CMP_T2CMP_SHIFT)) & ZLL_T2CMP_T2CMP_MASK) - -/*! @name T2PRIMECMP - T2 PRIME COMPARE */ -#define ZLL_T2PRIMECMP_T2PRIMECMP_MASK (0xFFFFU) -#define ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT (0U) -#define ZLL_T2PRIMECMP_T2PRIMECMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT)) & ZLL_T2PRIMECMP_T2PRIMECMP_MASK) - -/*! @name T3CMP - T3 COMPARE */ -#define ZLL_T3CMP_T3CMP_MASK (0xFFFFFFU) -#define ZLL_T3CMP_T3CMP_SHIFT (0U) -#define ZLL_T3CMP_T3CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T3CMP_T3CMP_SHIFT)) & ZLL_T3CMP_T3CMP_MASK) - -/*! @name T4CMP - T4 COMPARE */ -#define ZLL_T4CMP_T4CMP_MASK (0xFFFFFFU) -#define ZLL_T4CMP_T4CMP_SHIFT (0U) -#define ZLL_T4CMP_T4CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T4CMP_T4CMP_SHIFT)) & ZLL_T4CMP_T4CMP_MASK) - -/*! @name PA_PWR - PA POWER */ -#define ZLL_PA_PWR_PA_PWR_MASK (0x3FU) -#define ZLL_PA_PWR_PA_PWR_SHIFT (0U) -#define ZLL_PA_PWR_PA_PWR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PA_PWR_PA_PWR_SHIFT)) & ZLL_PA_PWR_PA_PWR_MASK) - -/*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */ -#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK (0x7FU) -#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT (0U) -#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT)) & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK) - -/*! @name LQI_AND_RSSI - LQI AND RSSI */ -#define ZLL_LQI_AND_RSSI_LQI_VALUE_MASK (0xFFU) -#define ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT (0U) -#define ZLL_LQI_AND_RSSI_LQI_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT)) & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) -#define ZLL_LQI_AND_RSSI_RSSI_MASK (0xFF00U) -#define ZLL_LQI_AND_RSSI_RSSI_SHIFT (8U) -#define ZLL_LQI_AND_RSSI_RSSI(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_RSSI_SHIFT)) & ZLL_LQI_AND_RSSI_RSSI_MASK) -#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK (0xFF0000U) -#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT (16U) -#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)) & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) - -/*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */ -#define ZLL_MACSHORTADDRS0_MACPANID0_MASK (0xFFFFU) -#define ZLL_MACSHORTADDRS0_MACPANID0_SHIFT (0U) -#define ZLL_MACSHORTADDRS0_MACPANID0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACPANID0_SHIFT)) & ZLL_MACSHORTADDRS0_MACPANID0_MASK) -#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK (0xFFFF0000U) -#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT (16U) -#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT)) & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) - -/*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */ -#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT (0U) -#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT)) & ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK) - -/*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */ -#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT (0U) -#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT)) & ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK) - -/*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */ -#define ZLL_RX_FRAME_FILTER_BEACON_FT_MASK (0x1U) -#define ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT (0U) -#define ZLL_RX_FRAME_FILTER_BEACON_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_BEACON_FT_MASK) -#define ZLL_RX_FRAME_FILTER_DATA_FT_MASK (0x2U) -#define ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT (1U) -#define ZLL_RX_FRAME_FILTER_DATA_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_DATA_FT_MASK) -#define ZLL_RX_FRAME_FILTER_ACK_FT_MASK (0x4U) -#define ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT (2U) -#define ZLL_RX_FRAME_FILTER_ACK_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_ACK_FT_MASK) -#define ZLL_RX_FRAME_FILTER_CMD_FT_MASK (0x8U) -#define ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT (3U) -#define ZLL_RX_FRAME_FILTER_CMD_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_CMD_FT_MASK) -#define ZLL_RX_FRAME_FILTER_LLDN_FT_MASK (0x10U) -#define ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT (4U) -#define ZLL_RX_FRAME_FILTER_LLDN_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_FT_MASK) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK (0x20U) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT (5U) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK) -#define ZLL_RX_FRAME_FILTER_NS_FT_MASK (0x40U) -#define ZLL_RX_FRAME_FILTER_NS_FT_SHIFT (6U) -#define ZLL_RX_FRAME_FILTER_NS_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_NS_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_NS_FT_MASK) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK (0x80U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT (7U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK) -#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK (0xF00U) -#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT (8U) -#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT)) & ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK) -#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK (0x4000U) -#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT (14U) -#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT)) & ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK (0x8000U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT (15U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK (0x10000U) -#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT (16U) -#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK (0x20000U) -#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT (17U) -#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK (0x40000U) -#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT (18U) -#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK (0x80000U) -#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT (19U) -#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK (0x100000U) -#define ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT (20U) -#define ZLL_RX_FRAME_FILTER_LLDN_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK (0x200000U) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT (21U) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK (0x800000U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT (23U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK) - -/*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */ -#define ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK (0xFFU) -#define ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT (0U) -#define ZLL_CCA_LQI_CTRL_CCA1_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) -#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK (0xFF0000U) -#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT (16U) -#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT)) & ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK) -#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK (0x8000000U) -#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT (27U) -#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK) - -/*! @name CCA2_CTRL - CCA2 CONTROL */ -#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK (0xFU) -#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT (0U) -#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT)) & ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK) -#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK (0x70U) -#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT (4U) -#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK) -#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK (0xFF00U) -#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT (8U) -#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK) - -/*! @name DSM_CTRL - DSM CONTROL */ -#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK (0x1U) -#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT (0U) -#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT)) & ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK) - -/*! @name BSM_CTRL - BSM CONTROL */ -#define ZLL_BSM_CTRL_BSM_EN_MASK (0x1U) -#define ZLL_BSM_CTRL_BSM_EN_SHIFT (0U) -#define ZLL_BSM_CTRL_BSM_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_BSM_CTRL_BSM_EN_SHIFT)) & ZLL_BSM_CTRL_BSM_EN_MASK) - -/*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */ -#define ZLL_MACSHORTADDRS1_MACPANID1_MASK (0xFFFFU) -#define ZLL_MACSHORTADDRS1_MACPANID1_SHIFT (0U) -#define ZLL_MACSHORTADDRS1_MACPANID1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACPANID1_SHIFT)) & ZLL_MACSHORTADDRS1_MACPANID1_MASK) -#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK (0xFFFF0000U) -#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT (16U) -#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT)) & ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK) - -/*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */ -#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT (0U) -#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT)) & ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK) - -/*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */ -#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT (0U) -#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT)) & ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK) - -/*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */ -#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK (0x1U) -#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT (0U) -#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK (0x2U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT (1U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK) -#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK (0x4U) -#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT (2U) -#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT)) & ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK) -#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK (0x8U) -#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT (3U) -#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK (0x10U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT (4U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK (0x20U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT (5U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK (0xFF00U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT (8U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK (0x3F0000U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT (16U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK (0x400000U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT (22U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK (0x800000U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT (23U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK) - -/*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */ -#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK (0x7FU) -#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT (0U) -#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT)) & ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK) - -/*! @name SAM_CTRL - SAM CONTROL */ -#define ZLL_SAM_CTRL_SAP0_EN_MASK (0x1U) -#define ZLL_SAM_CTRL_SAP0_EN_SHIFT (0U) -#define ZLL_SAM_CTRL_SAP0_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP0_EN_SHIFT)) & ZLL_SAM_CTRL_SAP0_EN_MASK) -#define ZLL_SAM_CTRL_SAA0_EN_MASK (0x2U) -#define ZLL_SAM_CTRL_SAA0_EN_SHIFT (1U) -#define ZLL_SAM_CTRL_SAA0_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_EN_SHIFT)) & ZLL_SAM_CTRL_SAA0_EN_MASK) -#define ZLL_SAM_CTRL_SAP1_EN_MASK (0x4U) -#define ZLL_SAM_CTRL_SAP1_EN_SHIFT (2U) -#define ZLL_SAM_CTRL_SAP1_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_EN_SHIFT)) & ZLL_SAM_CTRL_SAP1_EN_MASK) -#define ZLL_SAM_CTRL_SAA1_EN_MASK (0x8U) -#define ZLL_SAM_CTRL_SAA1_EN_SHIFT (3U) -#define ZLL_SAM_CTRL_SAA1_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_EN_SHIFT)) & ZLL_SAM_CTRL_SAA1_EN_MASK) -#define ZLL_SAM_CTRL_SAA0_START_MASK (0xFF00U) -#define ZLL_SAM_CTRL_SAA0_START_SHIFT (8U) -#define ZLL_SAM_CTRL_SAA0_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_START_SHIFT)) & ZLL_SAM_CTRL_SAA0_START_MASK) -#define ZLL_SAM_CTRL_SAP1_START_MASK (0xFF0000U) -#define ZLL_SAM_CTRL_SAP1_START_SHIFT (16U) -#define ZLL_SAM_CTRL_SAP1_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_START_SHIFT)) & ZLL_SAM_CTRL_SAP1_START_MASK) -#define ZLL_SAM_CTRL_SAA1_START_MASK (0xFF000000U) -#define ZLL_SAM_CTRL_SAA1_START_SHIFT (24U) -#define ZLL_SAM_CTRL_SAA1_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_START_SHIFT)) & ZLL_SAM_CTRL_SAA1_START_MASK) - -/*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */ -#define ZLL_SAM_TABLE_SAM_INDEX_MASK (0x7FU) -#define ZLL_SAM_TABLE_SAM_INDEX_SHIFT (0U) -#define ZLL_SAM_TABLE_SAM_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_MASK) -#define ZLL_SAM_TABLE_SAM_INDEX_WR_MASK (0x80U) -#define ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT (7U) -#define ZLL_SAM_TABLE_SAM_INDEX_WR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_WR_MASK) -#define ZLL_SAM_TABLE_SAM_CHECKSUM_MASK (0xFFFF00U) -#define ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT (8U) -#define ZLL_SAM_TABLE_SAM_CHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT)) & ZLL_SAM_TABLE_SAM_CHECKSUM_MASK) -#define ZLL_SAM_TABLE_SAM_INDEX_INV_MASK (0x1000000U) -#define ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT (24U) -#define ZLL_SAM_TABLE_SAM_INDEX_INV(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_INV_MASK) -#define ZLL_SAM_TABLE_SAM_INDEX_EN_MASK (0x2000000U) -#define ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT (25U) -#define ZLL_SAM_TABLE_SAM_INDEX_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_EN_MASK) -#define ZLL_SAM_TABLE_ACK_FRM_PND_MASK (0x4000000U) -#define ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT (26U) -#define ZLL_SAM_TABLE_ACK_FRM_PND(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_MASK) -#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK (0x8000000U) -#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT (27U) -#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK) -#define ZLL_SAM_TABLE_FIND_FREE_IDX_MASK (0x10000000U) -#define ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT (28U) -#define ZLL_SAM_TABLE_FIND_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT)) & ZLL_SAM_TABLE_FIND_FREE_IDX_MASK) -#define ZLL_SAM_TABLE_INVALIDATE_ALL_MASK (0x20000000U) -#define ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT (29U) -#define ZLL_SAM_TABLE_INVALIDATE_ALL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT)) & ZLL_SAM_TABLE_INVALIDATE_ALL_MASK) -#define ZLL_SAM_TABLE_SAM_BUSY_MASK (0x80000000U) -#define ZLL_SAM_TABLE_SAM_BUSY_SHIFT (31U) -#define ZLL_SAM_TABLE_SAM_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_BUSY_SHIFT)) & ZLL_SAM_TABLE_SAM_BUSY_MASK) - -/*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */ -#define ZLL_SAM_MATCH_SAP0_MATCH_MASK (0x7FU) -#define ZLL_SAM_MATCH_SAP0_MATCH_SHIFT (0U) -#define ZLL_SAM_MATCH_SAP0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP0_MATCH_MASK) -#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK (0x80U) -#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT (7U) -#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK) -#define ZLL_SAM_MATCH_SAA0_MATCH_MASK (0x7F00U) -#define ZLL_SAM_MATCH_SAA0_MATCH_SHIFT (8U) -#define ZLL_SAM_MATCH_SAA0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA0_MATCH_MASK) -#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK (0x8000U) -#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT (15U) -#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK) -#define ZLL_SAM_MATCH_SAP1_MATCH_MASK (0x7F0000U) -#define ZLL_SAM_MATCH_SAP1_MATCH_SHIFT (16U) -#define ZLL_SAM_MATCH_SAP1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP1_MATCH_MASK) -#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK (0x800000U) -#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT (23U) -#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK) -#define ZLL_SAM_MATCH_SAA1_MATCH_MASK (0x7F000000U) -#define ZLL_SAM_MATCH_SAA1_MATCH_SHIFT (24U) -#define ZLL_SAM_MATCH_SAA1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA1_MATCH_MASK) -#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK (0x80000000U) -#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT (31U) -#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK) - -/*! @name SAM_FREE_IDX - SAM FREE INDEX */ -#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK (0xFFU) -#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT (0U) -#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK) -#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK (0xFF00U) -#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT (8U) -#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK) -#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK (0xFF0000U) -#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT (16U) -#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK) -#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK (0xFF000000U) -#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT (24U) -#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK) - -/*! @name SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS */ -#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK (0x4U) -#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT (2U) -#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK) -#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK (0x8U) -#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT (3U) -#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT)) & ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK) -#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK (0x10U) -#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT (4U) -#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT)) & ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK) -#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK (0x20U) -#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT (5U) -#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT)) & ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK) -#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK (0x40U) -#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT (6U) -#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT)) & ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK) -#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK (0x80U) -#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT (7U) -#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT)) & ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK) -#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK (0x700U) -#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT (8U) -#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT)) & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) -#define ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK (0x800U) -#define ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT (11U) -#define ZLL_SEQ_CTRL_STS_SEQ_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) -#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK (0x1000U) -#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT (12U) -#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK) -#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK (0x2000U) -#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT (13U) -#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK) -#define ZLL_SEQ_CTRL_STS_RX_MODE_MASK (0x4000U) -#define ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT (14U) -#define ZLL_SEQ_CTRL_STS_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_MODE_MASK) -#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK (0x8000U) -#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT (15U) -#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT)) & ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK) -#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK (0x3F0000U) -#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT (16U) -#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK) -#define ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK (0x1000000U) -#define ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT (24U) -#define ZLL_SEQ_CTRL_STS_SW_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) -#define ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK (0x2000000U) -#define ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT (25U) -#define ZLL_SEQ_CTRL_STS_TC3_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) -#define ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK (0x4000000U) -#define ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT (26U) -#define ZLL_SEQ_CTRL_STS_PLL_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) - -/*! @name ACKDELAY - ACK DELAY */ -#define ZLL_ACKDELAY_ACKDELAY_MASK (0x3FU) -#define ZLL_ACKDELAY_ACKDELAY_SHIFT (0U) -#define ZLL_ACKDELAY_ACKDELAY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_ACKDELAY_SHIFT)) & ZLL_ACKDELAY_ACKDELAY_MASK) -#define ZLL_ACKDELAY_TXDELAY_MASK (0x3F00U) -#define ZLL_ACKDELAY_TXDELAY_SHIFT (8U) -#define ZLL_ACKDELAY_TXDELAY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_TXDELAY_SHIFT)) & ZLL_ACKDELAY_TXDELAY_MASK) - -/*! @name FILTERFAIL_CODE - FILTER FAIL CODE */ -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK (0x3FFU) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT (0U) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK (0x8000U) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT (15U) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK) - -/*! @name RX_WTR_MARK - RECEIVE WATER MARK */ -#define ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK (0xFFU) -#define ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT (0U) -#define ZLL_RX_WTR_MARK_RX_WTR_MARK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT)) & ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK) - -/*! @name SLOT_PRELOAD - SLOT PRELOAD */ -#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK (0xFFU) -#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT (0U) -#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT)) & ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK) - -/*! @name SEQ_STATE - 802.15.4 SEQUENCE STATE */ -#define ZLL_SEQ_STATE_SEQ_STATE_MASK (0x1FU) -#define ZLL_SEQ_STATE_SEQ_STATE_SHIFT (0U) -#define ZLL_SEQ_STATE_SEQ_STATE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SEQ_STATE_SHIFT)) & ZLL_SEQ_STATE_SEQ_STATE_MASK) -#define ZLL_SEQ_STATE_PREAMBLE_DET_MASK (0x100U) -#define ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT (8U) -#define ZLL_SEQ_STATE_PREAMBLE_DET(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT)) & ZLL_SEQ_STATE_PREAMBLE_DET_MASK) -#define ZLL_SEQ_STATE_SFD_DET_MASK (0x200U) -#define ZLL_SEQ_STATE_SFD_DET_SHIFT (9U) -#define ZLL_SEQ_STATE_SFD_DET(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SFD_DET_SHIFT)) & ZLL_SEQ_STATE_SFD_DET_MASK) -#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK (0x400U) -#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT (10U) -#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT)) & ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK) -#define ZLL_SEQ_STATE_CRCVALID_MASK (0x800U) -#define ZLL_SEQ_STATE_CRCVALID_SHIFT (11U) -#define ZLL_SEQ_STATE_CRCVALID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CRCVALID_SHIFT)) & ZLL_SEQ_STATE_CRCVALID_MASK) -#define ZLL_SEQ_STATE_PLL_ABORT_MASK (0x1000U) -#define ZLL_SEQ_STATE_PLL_ABORT_SHIFT (12U) -#define ZLL_SEQ_STATE_PLL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORT_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORT_MASK) -#define ZLL_SEQ_STATE_PLL_ABORTED_MASK (0x2000U) -#define ZLL_SEQ_STATE_PLL_ABORTED_SHIFT (13U) -#define ZLL_SEQ_STATE_PLL_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORTED_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORTED_MASK) -#define ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK (0xFF0000U) -#define ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT (16U) -#define ZLL_SEQ_STATE_RX_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT)) & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK) -#define ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK (0x3F000000U) -#define ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT (24U) -#define ZLL_SEQ_STATE_CCCA_BUSY_CNT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT)) & ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK) - -/*! @name TMR_PRESCALE - TIMER PRESCALER */ -#define ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK (0x7U) -#define ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT (0U) -#define ZLL_TMR_PRESCALE_TMR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT)) & ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK) - -/*! @name LENIENCY_LSB - LENIENCY LSB */ -#define ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK (0xFFFFFFFFU) -#define ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT (0U) -#define ZLL_LENIENCY_LSB_LENIENCY_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT)) & ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK) - -/*! @name LENIENCY_MSB - LENIENCY MSB */ -#define ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK (0xFFU) -#define ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT (0U) -#define ZLL_LENIENCY_MSB_LENIENCY_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT)) & ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK) - -/*! @name PART_ID - PART ID */ -#define ZLL_PART_ID_PART_ID_MASK (0xFFU) -#define ZLL_PART_ID_PART_ID_SHIFT (0U) -#define ZLL_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PART_ID_PART_ID_SHIFT)) & ZLL_PART_ID_PART_ID_MASK) - -/*! @name PKT_BUFFER_TX - Packet Buffer TX */ -#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK (0xFFFFU) -#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT (0U) -#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX(x) (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT)) & ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK) - -/* The count of ZLL_PKT_BUFFER_TX */ -#define ZLL_PKT_BUFFER_TX_COUNT (64U) - -/*! @name PKT_BUFFER_RX - Packet Buffer RX */ -#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK (0xFFFFU) -#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT (0U) -#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX(x) (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT)) & ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK) - -/* The count of ZLL_PKT_BUFFER_RX */ -#define ZLL_PKT_BUFFER_RX_COUNT (64U) - - -/*! - * @} - */ /* end of group ZLL_Register_Masks */ - - -/* ZLL - Peripheral instance base addresses */ -/** Peripheral ZLL base address */ -#define ZLL_BASE (0x4005D000u) -/** Peripheral ZLL base pointer */ -#define ZLL ((ZLL_Type *)ZLL_BASE) -/** Array initializer of ZLL peripheral base addresses */ -#define ZLL_BASE_ADDRS { ZLL_BASE } -/** Array initializer of ZLL peripheral base pointers */ -#define ZLL_BASE_PTRS { ZLL } - -/*! - * @} - */ /* end of group ZLL_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -#define DSPI0 SPI0 -#define DSPI1 SPI1 - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _MKW41Z4_H_ */ - diff --git a/third_party/nxp/MKW41Z4/MKW41Z4_features.h b/third_party/nxp/MKW41Z4/MKW41Z4_features.h deleted file mode 100644 index 7e7fee364..000000000 --- a/third_party/nxp/MKW41Z4/MKW41Z4_features.h +++ /dev/null @@ -1,2020 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2015-09-23 -** Build: b170228 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2015-09-23) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _MKW41Z4_FEATURES_H_ -#define _MKW41Z4_FEATURES_H_ - -/* SOC module features */ - -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (1) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) -/* @brief AOI availability on the SoC. */ -#define FSL_FEATURE_SOC_AOI_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief FLEXCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief CMP availability on the SoC. */ -#define FSL_FEATURE_SOC_CMP_COUNT (1) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (1) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (0) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (1) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) -/* @brief DCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_DCDC_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (2) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (0) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_ENET_COUNT (0) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (0) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (3) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (0) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (1) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (3) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (2) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (0) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (1) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (0) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (0) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (1) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (1) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (1) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (1) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (1) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief SYSMPU availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (1) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIT availability on the SoC. */ -#define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (3) -/* @brief PWM availability on the SoC. */ -#define FSL_FEATURE_SOC_PWM_COUNT (0) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (1) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (1) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (0) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (1) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief TMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TMR_COUNT (0) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (3) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (1) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (0) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) -/* @brief USBHS availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHS_COUNT (0) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (1) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (0) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) -/* @brief XBARA availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARA_COUNT (0) -/* @brief XBARB availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARB_COUNT (0) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (1) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (1) - -/* ADC16 module features */ - -/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ -#define FSL_FEATURE_ADC16_HAS_PGA (0) -/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) -/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) -/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ -#define FSL_FEATURE_ADC16_HAS_DMA (1) -/* @brief Has differential mode (bitfield SC1x[DIFF]). */ -#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) -/* @brief Has FIFO (bit SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_HAS_FIFO (0) -/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_FIFO_SIZE (0) -/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ -#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) -/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ -#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) -/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ -#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) -/* @brief Has HW averaging (bit SC3[AVGE]). */ -#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) -/* @brief Has offset correction (register OFS). */ -#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) -/* @brief Maximum ADC resolution. */ -#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) -/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ -#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) - -/* BTLE_RF module features */ - -/* No feature definitions */ - -/* CMP module features */ - -/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ -#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) -/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ -#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) -/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ -#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) -/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ -#define FSL_FEATURE_CMP_HAS_DMA (1) -/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ -#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) -/* @brief Has DAC Test function in CMP (register DACTEST). */ -#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) - -/* COP module features */ - -/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ -#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) -/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ -#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) -/* @brief Has more clock sources like MCGIRC */ -#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) -/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ -#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) - -/* DAC module features */ - -/* @brief Define the size of hardware buffer */ -#define FSL_FEATURE_DAC_BUFFER_SIZE (2) -/* @brief Define whether the buffer supports watermark event detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) -/* @brief Define whether the buffer supports watermark selection detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) -/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) -/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) -/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) -/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) -/* @brief Define whether FIFO buffer mode is available or not. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) -/* @brief Define whether swing buffer mode is available or not.. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) - -/* DCDC module features */ - -/* @brief Has VDD1P5 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) -/* @brief Has VDD1P45 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) - -/* FLASH module features */ - -#if defined(CPU_MKW41Z256VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#elif defined(CPU_MKW41Z512CAT4) || defined(CPU_MKW41Z512VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#endif /* defined(CPU_MKW41Z256VHT4) */ - -/* GENFSK module features */ - -/* No feature definitions */ - -/* GPIO module features */ - -/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ -#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) -/* @brief Has port input disable register (PIDR). */ -#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) - -/* I2C module features */ - -/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ -#define FSL_FEATURE_I2C_HAS_SMBUS (1) -/* @brief Maximum supported baud rate in kilobit per second. */ -#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) -/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ -#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) -/* @brief Has DMA support (register bit C1[DMAEN]). */ -#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) -/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) -/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) -/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ -#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) -/* @brief Maximum width of the glitch filter in number of bus clocks. */ -#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) -/* @brief Has control of the drive capability of the I2C pins. */ -#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) -/* @brief Has double buffering support (register S2). */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) -/* @brief Has double buffer enable. */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) - -/* LLWU module features */ - -#if defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) - /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Has pins 8-15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has MF register. */ - #define FSL_FEATURE_LLWU_HAS_MF (0) - /* @brief Has PF register. */ - #define FSL_FEATURE_LLWU_HAS_PF (0) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) - /* @brief Has no internal module wakeup flag register. */ - #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) - /* @brief Has external pin 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) - /* @brief Has external pin 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) - /* @brief Has external pin 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) - /* @brief Has external pin 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) - /* @brief Has external pin 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) - /* @brief Has external pin 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) - /* @brief Has external pin 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) - /* @brief Has external pin 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) - /* @brief Has external pin 8 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) - /* @brief Has external pin 9 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) - /* @brief Has external pin 10 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) - /* @brief Has external pin 11 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) - /* @brief Has external pin 12 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) - /* @brief Has external pin 13 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) - /* @brief Has external pin 14 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) - /* @brief Has external pin 15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) - /* @brief Has external pin 16 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) - /* @brief Has external pin 17 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) - /* @brief Has external pin 18 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) - /* @brief Has external pin 19 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) - /* @brief Has external pin 20 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) - /* @brief Has external pin 21 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) - /* @brief Has external pin 22 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) - /* @brief Has external pin 23 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) - /* @brief Has external pin 24 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) - /* @brief Has external pin 25 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) - /* @brief Has external pin 26 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) - /* @brief Has external pin 27 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) - /* @brief Has external pin 28 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) - /* @brief Has external pin 29 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) - /* @brief Has external pin 30 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) - /* @brief Has external pin 31 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) - /* @brief Has internal module 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) - /* @brief Has internal module 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) - /* @brief Has internal module 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) - /* @brief Has internal module 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) - /* @brief Has internal module 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) - /* @brief Has internal module 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) - /* @brief Has internal module 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) - /* @brief Has internal module 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) - /* @brief Has Version ID Register (LLWU_VERID). */ - #define FSL_FEATURE_LLWU_HAS_VERID (0) - /* @brief Has Parameter Register (LLWU_PARAM). */ - #define FSL_FEATURE_LLWU_HAS_PARAM (0) - /* @brief Width of registers of the LLWU. */ - #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) - /* @brief Has DMA Enable register (LLWU_DE). */ - #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) -#elif defined(CPU_MKW41Z512CAT4) - /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Has pins 8-15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has MF register. */ - #define FSL_FEATURE_LLWU_HAS_MF (0) - /* @brief Has PF register. */ - #define FSL_FEATURE_LLWU_HAS_PF (0) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) - /* @brief Has no internal module wakeup flag register. */ - #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) - /* @brief Has external pin 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) - /* @brief Has external pin 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) - /* @brief Has external pin 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) - /* @brief Has external pin 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) - /* @brief Has external pin 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) - /* @brief Has external pin 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) - /* @brief Has external pin 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) - /* @brief Has external pin 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) - /* @brief Has external pin 8 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) - /* @brief Has external pin 9 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) - /* @brief Has external pin 10 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) - /* @brief Has external pin 11 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) - /* @brief Has external pin 12 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) - /* @brief Has external pin 13 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) - /* @brief Has external pin 14 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) - /* @brief Has external pin 15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) - /* @brief Has external pin 16 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) - /* @brief Has external pin 17 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) - /* @brief Has external pin 18 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) - /* @brief Has external pin 19 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) - /* @brief Has external pin 20 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) - /* @brief Has external pin 21 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) - /* @brief Has external pin 22 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) - /* @brief Has external pin 23 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) - /* @brief Has external pin 24 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) - /* @brief Has external pin 25 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) - /* @brief Has external pin 26 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) - /* @brief Has external pin 27 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) - /* @brief Has external pin 28 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) - /* @brief Has external pin 29 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) - /* @brief Has external pin 30 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) - /* @brief Has external pin 31 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) - /* @brief Has internal module 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) - /* @brief Has internal module 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) - /* @brief Has internal module 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) - /* @brief Has internal module 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) - /* @brief Has internal module 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) - /* @brief Has internal module 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) - /* @brief Has internal module 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) - /* @brief Has internal module 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) - /* @brief Has Version ID Register (LLWU_VERID). */ - #define FSL_FEATURE_LLWU_HAS_VERID (0) - /* @brief Has Parameter Register (LLWU_PARAM). */ - #define FSL_FEATURE_LLWU_HAS_PARAM (0) - /* @brief Width of registers of the LLWU. */ - #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) - /* @brief Has DMA Enable register (LLWU_DE). */ - #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) -#endif /* defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) */ - -/* LPTMR module features */ - -/* @brief Has shared interrupt handler with another LPTMR module. */ -#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) -/* @brief Whether LPTMR counter is 32 bits width. */ -#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) -/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ -#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) - -/* LPUART module features */ - -/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ -#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) -/* @brief Has 32-bit register MODIR */ -#define FSL_FEATURE_LPUART_HAS_MODIR (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief If 7-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) -/* @brief Peripheral type. */ -#define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ -#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has separate RX and TX interrupts. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) -/* @brief Has LPAURT_PARAM. */ -#define FSL_FEATURE_LPUART_HAS_PARAM (0) -/* @brief Has LPUART_VERID. */ -#define FSL_FEATURE_LPUART_HAS_VERID (0) -/* @brief Has LPUART_GLOBAL. */ -#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) -/* @brief Has LPUART_PINCFG. */ -#define FSL_FEATURE_LPUART_HAS_PINCFG (0) - -/* LTC module features */ - -/* @brief LTC module supports DES algorithm. */ -#define FSL_FEATURE_LTC_HAS_DES (0) -/* @brief LTC module supports PKHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_PKHA (0) -/* @brief LTC module supports SHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_SHA (0) -/* @brief LTC module supports AES GCM mode. */ -#define FSL_FEATURE_LTC_HAS_GCM (0) -/* @brief LTC module supports DPAMS registers. */ -#define FSL_FEATURE_LTC_HAS_DPAMS (0) -/* @brief LTC module supports AES with 24 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES192 (0) -/* @brief LTC module supports AES with 32 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES256 (0) - -/* MCG module features */ - -/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) -/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) -/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) -/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MIN (0) -/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MAX (0) -/* @brief The PLL clock is divided by 2 before VCO divider. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) -/* @brief FRDIV supports 1280. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) -/* @brief FRDIV supports 1536. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) -/* @brief MCGFFCLK divider. */ -#define FSL_FEATURE_MCG_FFCLK_DIV (1) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ -#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) -/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ -#define FSL_FEATURE_MCG_HAS_RTC_32K (1) -/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_PLL1 (0) -/* @brief Has 48MHz internal oscillator. */ -#define FSL_FEATURE_MCG_HAS_IRC_48M (0) -/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_OSC1 (0) -/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ -#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) -/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ -#define FSL_FEATURE_MCG_HAS_LOLRE (0) -/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ -#define FSL_FEATURE_MCG_USE_OSCSEL (1) -/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ -#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) -/* @brief TBD */ -#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) -/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ -#define FSL_FEATURE_MCG_HAS_PLL (0) -/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) -/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) -/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ -#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) -/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ -#define FSL_FEATURE_MCG_HAS_FLL (1) -/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) -/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ -#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) -/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) -/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) -/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ -#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) -/* @brief Has external clock monitor (register bit C6[CME]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) -/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ -#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) -/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ -#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -/* @brief Has PEI mode or PBI mode. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) -/* @brief Reset clock mode is BLPI. */ -#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) - -/* PIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_PIT_TIMER_COUNT (2) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) - -/* PMC module features */ - -/* @brief Has Bandgap Enable In VLPx Operation support. */ -#define FSL_FEATURE_PMC_HAS_BGEN (0) -/* @brief Has Bandgap Buffer Enable. */ -#define FSL_FEATURE_PMC_HAS_BGBE (1) -/* @brief Has Bandgap Buffer Drive Select. */ -#define FSL_FEATURE_PMC_HAS_BGBDS (0) -/* @brief Has Low-Voltage Detect Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVDV (1) -/* @brief Has Low-Voltage Warning Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVWV (1) -/* @brief Has LPO. */ -#define FSL_FEATURE_PMC_HAS_LPO (0) -/* @brief Has VLPx option PMC_REGSC[VLPO]. */ -#define FSL_FEATURE_PMC_HAS_VLPO (1) -/* @brief Has acknowledge isolation support. */ -#define FSL_FEATURE_PMC_HAS_ACKISO (1) -/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ -#define FSL_FEATURE_PMC_HAS_REGFPM (0) -/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ -#define FSL_FEATURE_PMC_HAS_REGONS (1) -/* @brief Has PMC_HVDSC1. */ -#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) -/* @brief Has PMC_PARAM. */ -#define FSL_FEATURE_PMC_HAS_PARAM (0) -/* @brief Has PMC_VERID. */ -#define FSL_FEATURE_PMC_HAS_VERID (0) - -/* PORT module features */ - -/* @brief Has control lock (register bit PCR[LK]). */ -#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) -/* @brief Has open drain control (register bit PCR[ODE]). */ -#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) -/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ -#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) -/* @brief Has DMA request (register bit field PCR[IRQC] values). */ -#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) -/* @brief Has pull resistor selection available. */ -#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) -/* @brief Has pull resistor enable (register bit PCR[PE]). */ -#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) -/* @brief Has slew rate control (register bit PCR[SRE]). */ -#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) -/* @brief Has passive filter (register bit field PCR[PFE]). */ -#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) -/* @brief Has drive strength control (register bit PCR[DSE]). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) -/* @brief Has separate drive strength register (HDRVE). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) -/* @brief Has glitch filter (register IOFLT). */ -#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -/* @brief Defines width of PCR[MUX] field. */ -#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) -/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ -#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) -/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) -/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) - -/* RADIO module features */ - -/* @brief Zigbee availability. */ -#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) -/* @brief Bluetooth availability. */ -#define FSL_FEATURE_RADIO_HAS_BLE (1) -/* @brief ANT availability */ -#define FSL_FEATURE_RADIO_HAS_ANT (1) -/* @brief Generic FSK module availability */ -#define FSL_FEATURE_RADIO_HAS_GENFSK (1) -/* @brief Major version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) -/* @brief Minor version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MINOR (0) - -/* RCM module features */ - -/* @brief Has Loss-of-Lock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOL (0) -/* @brief Has Loss-of-Clock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOC (1) -/* @brief Has JTAG generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_JTAG (0) -/* @brief Has EzPort generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_EZPORT (0) -/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ -#define FSL_FEATURE_RCM_HAS_EZPMS (0) -/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ -#define FSL_FEATURE_RCM_HAS_BOOTROM (0) -/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ -#define FSL_FEATURE_RCM_HAS_SSRS (0) -/* @brief Has Version ID Register (RCM_VERID). */ -#define FSL_FEATURE_RCM_HAS_VERID (0) -/* @brief Has Parameter Register (RCM_PARAM). */ -#define FSL_FEATURE_RCM_HAS_PARAM (0) -/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ -#define FSL_FEATURE_RCM_HAS_SRIE (0) -/* @brief Width of registers of the RCM. */ -#define FSL_FEATURE_RCM_REG_WIDTH (8) -/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ -#define FSL_FEATURE_RCM_HAS_CORE1 (0) -/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ -#define FSL_FEATURE_RCM_HAS_MDM_AP (1) -/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ -#define FSL_FEATURE_RCM_HAS_WAKEUP (1) - -/* RSIM module features */ - -/* No feature definitions */ - -/* RTC module features */ - -/* @brief Has wakeup pin. */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) -/* @brief Has wakeup pin selection (bit field CR[WPS]). */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) -/* @brief Has low power features (registers MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) -/* @brief Has read/write access control (registers WAR and RAR). */ -#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) -/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_SECURITY (0) -/* @brief Has RTC_CLKIN available. */ -#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) -/* @brief Has prescaler adjust for LPO. */ -#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) -/* @brief Has Clock Pin Enable field. */ -#define FSL_FEATURE_RTC_HAS_CPE (0) -/* @brief Has Timer Seconds Interrupt Configuration field. */ -#define FSL_FEATURE_RTC_HAS_TSIC (0) -/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ -#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) - -/* SIM module features */ - -/* @brief Has USB FS divider. */ -#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ -#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) -/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) -/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) -/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) -/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) -/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) -/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) -/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) -/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) -/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) -/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) -/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) -/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ -#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) -/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ -#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) -/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ -#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) -/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) -/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) -/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) -/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) -/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) -/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) -/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) -/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) -/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) -/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) -/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) -/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) -/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) -/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) -/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) -/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) -/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) -/* @brief Has FTM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) -/* @brief Number of FTM modules. */ -#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) -/* @brief Number of FTM triggers with selectable source. */ -#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) -/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) -/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) -/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) -/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) -/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) -/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) -/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) -/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) -/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) -/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) -/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) -/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) -/* @brief Has TPM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) -/* @brief The highest TPM module index. */ -#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) -/* @brief Has TPM module with index 0. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) -/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) -/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) -/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) -/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) -/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) -/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) -/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) -/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) -/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) -/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) -/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) -/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) -/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) -/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) -/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) -/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) -/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) -/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) -/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) -/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) -/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) -/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) -/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) -/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) -/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) -/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) -/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) -/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) -/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) -/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) -/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) -/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) -/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) -/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) -/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) -/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) -/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) -/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) -/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) -/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) -/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) -/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) -/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) -/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) -/* @brief Has device die ID (register bit field SDID[DIEID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) -/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) -/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) -/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) -/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) -/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) -/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) -/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) -/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) -/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) -/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) -/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) -/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) -/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) -/* @brief Has miscellanious control register (register MCR). */ -#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) -/* @brief Has COP watchdog (registers COPC and SRVCOP). */ -#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) -/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ -#define FSL_FEATURE_SIM_HAS_COP_STOP (1) -/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ -#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) - -/* SMC module features */ - -/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ -#define FSL_FEATURE_SMC_HAS_PSTOPO (1) -/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ -#define FSL_FEATURE_SMC_HAS_LPOPO (0) -/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ -#define FSL_FEATURE_SMC_HAS_PORPO (1) -/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ -#define FSL_FEATURE_SMC_HAS_LPWUI (0) -/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ -#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) -/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) -/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) -/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ -#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) -/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ -#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) -/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ -#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ -#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has stop submode. */ -#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) -/* @brief Has stop submode 0(VLLS0). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) -/* @brief Has stop submode 2(VLLS2). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) -/* @brief Has SMC_PARAM. */ -#define FSL_FEATURE_SMC_HAS_PARAM (0) -/* @brief Has SMC_VERID. */ -#define FSL_FEATURE_SMC_HAS_VERID (0) -/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ -#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) -/* @brief Has tamper reset (register bit SRS[TAMPER]). */ -#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) -/* @brief Has security violation reset (register bit SRS[SECVIO]). */ -#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) - -/* DSPI module features */ - -/* @brief Receive/transmit FIFO size in number of items. */ -#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) -/* @brief Maximum transfer data width in bits. */ -#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) -/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ -#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) -/* @brief Number of chip select pins. */ -#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) -/* @brief Has chip select strobe capability on the PCS5 pin. */ -#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) -/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) -/* @brief Has 16-bit data transfer support. */ -#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) - -/* TPM module features */ - -/* @brief Bus clock is the source clock for the module. */ -#define FSL_FEATURE_TPM_BUS_CLOCK (0) -/* @brief Number of channels. */ -#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ - ((x) == TPM0 ? (4) : \ - ((x) == TPM1 ? (2) : \ - ((x) == TPM2 ? (2) : (-1)))) -/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ -#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -/* @brief Has TPM_PARAM. */ -#define FSL_FEATURE_TPM_HAS_PARAM (0) -/* @brief Has TPM_VERID. */ -#define FSL_FEATURE_TPM_HAS_VERID (0) -/* @brief Has TPM_GLOBAL. */ -#define FSL_FEATURE_TPM_HAS_GLOBAL (0) -/* @brief Has TPM_TRIG. */ -#define FSL_FEATURE_TPM_HAS_TRIG (0) -/* @brief Has counter pause on trigger. */ -#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) -/* @brief Has external trigger selection. */ -#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) -/* @brief Has TPM_COMBINE register. */ -#define FSL_FEATURE_TPM_HAS_COMBINE (1) -/* @brief Whether COMBINE register has effect. */ -#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_POL. */ -#define FSL_FEATURE_TPM_HAS_POL (1) -/* @brief Has TPM_FILTER register. */ -#define FSL_FEATURE_TPM_HAS_FILTER (1) -/* @brief Whether FILTER register has effect. */ -#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_QDCTRL register. */ -#define FSL_FEATURE_TPM_HAS_QDCTRL (1) -/* @brief Whether QDCTRL register has effect. */ -#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) - -/* TRNG module features */ - -/* No feature definitions */ - -/* TSI module features */ - -/* @brief TSI module version. */ -#define FSL_FEATURE_TSI_VERSION (4) -/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ -#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) -/* @brief Number of TSI channels. */ -#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) - -/* VREF module features */ - -/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ -#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) -/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ -#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) -/* @brief If high/low buffer mode supported */ -#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) -/* @brief Module has also low reference (registers VREFL/VREFH) */ -#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) -/* @brief Has VREF_TRM4. */ -#define FSL_FEATURE_VREF_HAS_TRM4 (0) - -/* XCVR_ANALOG module features */ - -/* No feature definitions */ - -/* XCVR_PHY module features */ - -/* No feature definitions */ - -/* ZLL module features */ - -/* No feature definitions */ - -#endif /* _MKW41Z4_FEATURES_H_ */ - diff --git a/third_party/nxp/MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.c b/third_party/nxp/MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.c deleted file mode 100644 index 7a5c118ce..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.c +++ /dev/null @@ -1,212 +0,0 @@ -/*! -* Copyright 2016-2017 NXP -* -* \file -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" -#include "xcvr_test_fsk.h" - -/*! ********************************************************************************* -************************************************************************************* -* Private type definitions -************************************************************************************* -********************************************************************************** */ -enum { - gDftNormal_c = 0, - gDftTxNoMod_Carrier_c = 1, - gDftTxPattern_c = 2, - gDftTxRandom_c = 3, -}; - -/*! ********************************************************************************* -************************************************************************************* -* Private memory declarations -************************************************************************************* -********************************************************************************** */ - -/*! ********************************************************************************* -************************************************************************************* -* Public prototypes -************************************************************************************* -********************************************************************************** */ -void XcvrFskModTx(void); -void XcvrFskNoModTx(void); -void XcvrFskIdle(void); -void XcvrFskTxRand(void); -void XcvrFskLoadPattern(uint32_t u32Pattern); -void XcvrFskSetTxPower(uint8_t u8TxPow); -void XcvrFskSetTxChannel(uint8_t u8TxChan); -void XcvrFskRestoreTXControl(void); -uint8_t XcvrFskGetInstantRssi(void); - -/*! ********************************************************************************* -* XcvrFskModTx -***********************************************************************************/ -void XcvrFskModTx(void) -{ - XcvrFskIdle(); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); - XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxPattern_c) | - XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK; - XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskNoModTx -***********************************************************************************/ -void XcvrFskNoModTx(void) -{ - XcvrFskIdle(); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); - XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxNoMod_Carrier_c); - XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskIdle -***********************************************************************************/ -void XcvrFskIdle(void) -{ - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | - XCVR_TX_DIG_CTRL_LFSR_EN_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; - XCVR_MISC->DTEST_CTRL &= ~XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskTxRand -***********************************************************************************/ -void XcvrFskTxRand(void) -{ - XcvrFskIdle(); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | - XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK); - XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxRandom_c) | - XCVR_TX_DIG_CTRL_LFSR_LENGTH(0) | /* length 9 */ - XCVR_TX_DIG_CTRL_LFSR_EN_MASK; - XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskLoadPattern -***********************************************************************************/ -void XcvrFskLoadPattern(uint32_t u32Pattern) -{ - XCVR_TX_DIG->DFT_PATTERN = u32Pattern; -} - -/*! ********************************************************************************* -* XcvrFskGetInstantRssi -***********************************************************************************/ -uint8_t XcvrFskGetInstantRssi(void) -{ - uint8_t u8Rssi; - uint32_t t1,t2,t3; - t1 = XCVR_RX_DIG->RX_DIG_CTRL; - t2 = XCVR_RX_DIG->RSSI_CTRL_0; - t3 = XCVR_PHY->CFG1; - XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | /* 1=OSR8, 2=OSR16, 4=OSR32 */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0) | /* Source Rate 0 is default */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(22) | /* Dec filt gain for SRC rate == 0 */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1) ; - - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK; - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(0x5); - - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK; - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(0x3); - - uint32_t temp = XCVR_PHY->CFG1; - temp &= ~XCVR_PHY_CFG1_CTS_THRESH_MASK; - temp |= XCVR_PHY_CFG1_CTS_THRESH(0xFF); - XCVR_PHY->CFG1 = temp; - - XCVR_ForceRxWu(); - for(uint32_t i = 0; i < 10000; i++) - { - __asm("nop"); - } - u8Rssi = (uint8_t)((XCVR_RX_DIG->RSSI_CTRL_1 & - XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) >> - XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT); - XCVR_ForceRxWd(); - - XCVR_RX_DIG->RX_DIG_CTRL = t1; - XCVR_RX_DIG->RSSI_CTRL_0 = t2; - XCVR_PHY->CFG1 = t3; - return u8Rssi; -} - -/*! ********************************************************************************* -* XcvrFskSetTxPower -***********************************************************************************/ -void XcvrFskSetTxPower(uint8_t u8TxPow) -{ - return; -} - -/*! ********************************************************************************* -* XcvrFskSetTxChannel -***********************************************************************************/ -void XcvrFskSetTxChannel(uint8_t u8TxChan) -{ - return; -} - -/*! ********************************************************************************* -* XcvrFskRestoreTXControl -* After calling this function user should switch to -* previous protocol and set the protocol channel to default -***********************************************************************************/ -void XcvrFskRestoreTXControl(void) -{ - return; -} - diff --git a/third_party/nxp/MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.h b/third_party/nxp/MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.h deleted file mode 100644 index a3be92c53..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/XCVR_Test/xcvr_test_fsk.h +++ /dev/null @@ -1,157 +0,0 @@ -/*! -* Copyright 2016-2017 NXP -* -* \file -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef __XCVR_TEST_FSK_H__ -#define __XCVR_TEST_FSK_H__ - -/*! ********************************************************************************* -************************************************************************************* -* Public type definitions -************************************************************************************* -********************************************************************************** */ - -/*! ********************************************************************************* -************************************************************************************* -* Public prototypes -************************************************************************************* -********************************************************************************** */ -/*! ********************************************************************************* -* \brief This function returns instant RSSI value and returns it as unsigned byte. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details Initialization of the xcvr is necessary prior to calling this function -* -***********************************************************************************/ -extern uint8_t XcvrFskGetInstantRssi(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into continuous modulated transmission. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details Initialization of the xcvr and calling XcvrFskLoadPattern are necessary -* prior to calling this function -* -***********************************************************************************/ -extern void XcvrFskModTx(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into continuous unmodulated transmission. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskNoModTx(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into idle. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskIdle(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into continuous modulated transmission. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details The modulation used is a pseudo-random pattern generated using a LFSR. -* -***********************************************************************************/ -extern void XcvrFskTxRand(void); - -/*! ********************************************************************************* -* \brief This function loads a 32 bit value into the pattern register used by XcvrFskModTx. -* -* \param[in] u32Pattern The pattern to be loaded. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskLoadPattern(uint32_t u32Pattern); - -/*! ********************************************************************************* -* \brief This function gives tx power control to xcvr and sets the power to u8TxPow. -* -* \param[in] u8TxPow Values should be between 0x00 and 0x0F. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskSetTxPower(uint8_t u8TxPow); - -/*! ********************************************************************************* -* \brief This function gives tx channel control to xcvr and sets the channel to u8TxChan. -* -* \param[in] u8TxChan Values should be between 0 and 39. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskSetTxChannel(uint8_t u8TxChan); - -/*! ********************************************************************************* -* \brief This function gives tx channel control and power to the upper layer. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details Call this function only if XcvrFskSetTxChannel or XcvrFskSetTxPower were called -* previously. -* -***********************************************************************************/ -extern void XcvrFskRestoreTXControl(void); - -#endif - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c deleted file mode 100644 index 319a104a0..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -const xcvr_mode_config_t ant_mode_config = -{ - .radio_mode = ANT_MODE, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK -#if !RADIO_IS_GEN_2P1 - | SIM_SCGC5_ANT_MASK -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = RW0PS(0, 0x1B) | - RW0PS(1, 0x1CU) | - RW0PS(2, 0x1CU) | - RW0PS(3, 0x1CU) | - RW0PS(4, 0x1DU) | - RW0PS(5, 0x1DU) | - RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/ - .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift */ - RW1PS(7, 0x1EU) | - RW1PS(8, 0x1EU) | - RW1PS(9, 0x1EU) | - RW1PS(10, 0x1EU) | - RW1PS(11, 0x1DU) | - RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */ - .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */ - RW2PS(13, 0x1CU) | - RW2PS(14, 0x1CU) | - RW2PS(15, 0x1CU), - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xF8) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = -{ - .radio_mode = ANT_MODE, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, - - /* ANT 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c deleted file mode 100644 index 054b0ccfe..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -const xcvr_mode_config_t ble_mode_config = -{ - .radio_mode = BLE_MODE, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = RW0PS(0, 0x19) | - RW0PS(1, 0x19U) | - RW0PS(2, 0x1AU) | - RW0PS(3, 0x1BU) | - RW0PS(4, 0x1CU) | - RW0PS(5, 0x1CU) | - RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ - .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ - RW1PS(7, 0x1EU) | - RW1PS(8, 0x1EU) | - RW1PS(9, 0x1EU) | - RW1PS(10, 0x1DU) | - RW1PS(11, 0x1CU) | - RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ - .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ - RW2PS(13, 0x1BU) | - RW2PS(14, 0x1AU) | - RW2PS(15, 0x19U), - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(220) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */ -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = -{ - .radio_mode = BLE_MODE, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* BLE 26MHz Channel Filter */ - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, - - /* BLE 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c deleted file mode 100644 index 4277d3a1f..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -const xcvr_common_config_t xcvr_common_config = -{ - /* XCVR_ANA configs */ - .ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK, - .ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */ - -#define hpm_vcm_tx 0 -#define hpm_vcm_cal 1 -#define hpm_fdb_res_tx 0 -#define hpm_fdb_res_cal 1 -#define modulation_word_manual 0 -#define mod_disable 0 -#define hpm_mod_manual 0 -#define hpm_mod_disable 0 -#define hpm_sdm_out_manual 0 -#define hpm_sdm_out_disable 0 -#define channel_num 0 -#define boc 0 -#define bmr 1 -#define zoc 0 -#define ctune_ldf_lev 8 -#define ftf_rx_thrsh 33 -#define ftw_rx 0 -#define ftf_tx_thrsh 6 -#define ftw_tx 0 -#define freq_count_go 0 -#define freq_count_time 0 -#define hpm_sdm_in_manual 0 -#define hpm_sdm_out_invert 0 -#define hpm_sdm_in_disable 0 -#define hpm_lfsr_size 4 -#define hpm_dth_scl 0 -#define hpm_dth_en 1 -#define hpm_integer_scale 0 -#define hpm_integer_invert 0 -#define hpm_cal_invert 1 -#define hpm_mod_in_invert 1 -#define hpm_cal_not_bumped 0 -#define hpm_cal_count_scale 0 -#define hp_cal_disable 0 -#define hpm_cal_factor_manual 0 -#define hpm_cal_array_size 1 -#define hpm_cal_time 0 -#define hpm_sdm_denom 256 -#define hpm_count_adjust 0 -#define pll_ld_manual 0 -#define pll_ld_disable 0 -#define lpm_sdm_inv 0 -#define lpm_disable 0 -#define lpm_dth_scl 8 -#define lpm_d_ctrl 1 -#define lpm_d_ovrd 1 -#define lpm_scale 8 -#define lpm_sdm_use_neg 0 -#define hpm_array_bias 0 -#define lpm_intg 38 -#define sdm_map_disable 0 -#define lpm_sdm_delay 4 -#define hpm_sdm_delay 0 -#define hpm_integer_delay 0 -#define ctune_target_manual 0 -#define ctune_target_disable 0 -#define ctune_adjust 0 -#define ctune_manual 0 -#define ctune_disable 0 - -/*-------------------------------------------------------------------------------------------------*/ - - .pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) | - XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) | - XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) | - XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx), - -/*-------------------------------------------------------------------------------------------------*/ - - .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) | - XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | - XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) | - XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) | - XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) | - XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual), - -/*-------------------------------------------------------------------------------------------------*/ - - .pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) | - XCVR_PLL_DIG_CHAN_MAP_BOC(boc) | - XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num) -#if !RADIO_IS_GEN_2P1 - | XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc) -#endif /* !RADIO_IS_GEN_2P1 */ - , - -/*-------------------------------------------------------------------------------------------------*/ - - .pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) | - XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) | - XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) | - XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) | - XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) | - XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) | - XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx), - -/*-------------------------------------------------------------------------------------------------*/ - - .pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) | - XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) | - XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) | - XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) | - XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) | - XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) | - XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) | - XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) | - XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) | - XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert), -/*-------------------------------------------------------------------------------------------------*/ -#if !RADIO_IS_GEN_2P1 - .pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) | - XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) | - XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) | - XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) | - XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) | - XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time), -#endif /* !RADIO_IS_GEN_2P1 */ -/*-------------------------------------------------------------------------------------------------*/ - .pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) | - XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom), -/*-------------------------------------------------------------------------------------------------*/ - .pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) | - XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) | - XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) | - XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) | - XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) | - XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) | - XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) | - XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) | - XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual), -/*-------------------------------------------------------------------------------------------------*/ - .pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) | - XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) | - XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable), -/*-------------------------------------------------------------------------------------------------*/ - .pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) | - XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) | - XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay), -/*-------------------------------------------------------------------------------------------------*/ - .pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) | - XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) | - XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) | - XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) | - XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual), -/*-------------------------------------------------------------------------------------------------*/ - - /* XCVR_RX_DIG configs */ - /* NOTE: Clock specific settings are embedded in the mode dependent configs */ - .rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) | -#if !RADIO_IS_GEN_2P1 - XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1), - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) | - XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) | - XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) | - XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) | - XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) | - XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7), - - .agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) | - XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) | - XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) | - XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) | - XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2), - - /* DCOC configs */ - .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ -#if (RADIO_IS_GEN_2P1) - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | -#endif /* (RADIO_IS_GEN_2P1) */ - XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | - XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | - XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), - .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ -#if (RADIO_IS_GEN_2P1) - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | -#endif /* (RADIO_IS_GEN_2P1) */ - XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | - XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | - XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), - - .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26), - - .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(4) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26), - - .dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) | - XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) | - XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) | - XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) | - XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) | - XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) , - - .dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) | - XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711), - - .lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) | - XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) | - XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) | - XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U), - - .lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) | - XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) | - XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) | - XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU), - .lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) | - XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U), - - .bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF), - .bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) | - XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2), - - .lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) | - XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) | - XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1), - - .lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) | - XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) | - XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7), - - .lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) | - XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) | - XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50), - - .lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91), - - .bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22), - - .bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */ - - .bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) | - XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288), - - .dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) | - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279), - - .dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) | - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404), - .dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) | - XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439), - .dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) | - XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691), - .dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) | - XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192), - .dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) | - XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835), - .dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) | - XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601), - .dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) | - XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427), - .dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) | - XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310), - .dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) | - XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209), - .dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) | - XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145), - .dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) | - XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99), -#if (RADIO_IS_GEN_2P1) - .dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) | - XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10), - .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) | - XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2), -#endif /* (RADIO_IS_GEN_2P1) */ - /* AGC Configs */ - .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2), - - .agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) | - XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) | - XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) | - XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) | - XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) | - XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) | - XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) | - XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2), - - .agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) | - XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) | - XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) | - XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) | - XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) | - XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) | - XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) | - XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4), - - .agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) | - XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) | - XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) | - XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) | - XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) | - XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5), - - .agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) | - XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) | - XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) | - XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7), - - .agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) | - XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) | - XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) | - XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) | - XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) | - XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) | - XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7), - - .agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) | - XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) | - XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) | - XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) | - XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) | - XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10), - - .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) | - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) | - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) | - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) | -#if !RADIO_IS_GEN_2P1 - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) | -#else - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) | -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) | - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) | - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) | - XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) , - - .cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0), - - .cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) | -#if !RADIO_IS_GEN_2P1 - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) | -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) | - XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2), - - /* XCVR_TSM configs */ - .tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) | - XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) | - XCVR_TSM_CTRL_TSM_IRQ0_EN(0) | - XCVR_TSM_CTRL_TSM_IRQ1_EN(0) | - XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) | - XCVR_TSM_CTRL_TX_ABORT_DIS(0) | - XCVR_TSM_CTRL_RX_ABORT_DIS(0) | - XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) | - XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) | - XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) | - XCVR_TSM_CTRL_BKPT(0xFF) , - - .tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK, - .end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), - .end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), - -#if !RADIO_IS_GEN_2P1 - .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0), -#endif /* !RADIO_IS_GEN_2P1 */ - - .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8), - .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8), - - .pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) | - XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3), - .pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) | - XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7), - - .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ), - .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66), - - .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */ - .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */ - .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */ - .tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */ - .tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */ - .tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */ - .tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */ - .tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */ - .tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */ - .tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */ - - .tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */ - .tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */ - .tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */ - .tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */ - .tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */ - .tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), - .tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */ - .tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */ - .tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */ - .tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */ - .tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */ - - .tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */ - .tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */ - .tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_en */ - .tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en */ - .tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */ - .tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */ - .tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */ - .tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */ - .tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */ - .tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */ - .tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - - .tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */ - .tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */ - .tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */ - .tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */ - .tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */ - .tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */ - .tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */ - .tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */ - .tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */ - .tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */ - .tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - - .tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */ - .tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */ - .tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */ - .tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */ - .tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */ - .tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */ - .tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */ - .tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */ - .tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), - .tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en */ - .tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */ - -/* XCVR_TX_DIG configs */ -#define radio_dft_mode 0 -#define lfsr_length 4 -#define lfsr_en 0 -#define dft_clk_sel 4 -#define tx_dft_en 0 -#define soc_test_sel 0 -#define tx_capture_pol 0 -#define freq_word_adj 0 -#define lrm 0 -#define data_padding_pat_1 0x55 -#define data_padding_pat_0 0xAA -#define gfsk_multiply_table_manual 0 -#define gfsk_mi 1 -#define gfsk_mld 0 -#define gfsk_fld 0 -#define gfsk_mod_index_scaling 0 -#define tx_image_filter_ovrd_en 0 -#define tx_image_filter_0_ovrd 0 -#define tx_image_filter_1_ovrd 0 -#define tx_image_filter_2_ovrd 0 -#define gfsk_filter_coeff_manual2 0xC0630401 -#define gfsk_filter_coeff_manual1 0xBB29960D -#define fsk_modulation_scale_0 0x1800 -#define fsk_modulation_scale_1 0x0800 -#define dft_mod_patternval 0 -#define ctune_bist_go 0 -#define ctune_bist_thrshld 0 -#define pa_am_mod_freq 0 -#define pa_am_mod_entries 0 -#define pa_am_mod_en 0 -#define syn_bist_go 0 -#define syn_bist_all_channels 0 -#define freq_count_threshold 0 -#define hpm_inl_bist_go 0 -#define hpm_dnl_bist_go 0 -#define dft_max_ram_size 0 - - .tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) | - XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | - XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) | - XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | - XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) | - XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) | - XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) | - XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj), -/*-------------------------------------------------------------------------------------------------*/ - .tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) | - XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) | - XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0), -/*-------------------------------------------------------------------------------------------------*/ - .tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval), -#if !RADIO_IS_GEN_2P1 -/*-------------------------------------------------------------------------------------------------*/ - .rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) | - XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) | - XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) | - XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) | - XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en), -/*-------------------------------------------------------------------------------------------------*/ - .rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) | - XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) | - XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) | - XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) | - XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) | - XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size), -#endif /* !RADIO_IS_GEN_2P1 */ -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c deleted file mode 100644 index 8bb5e3637..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x7BCDEB39, - .phy_pre_ref1_init = 0xCEF7DEF7, - .phy_pre_ref2_init = 0x0000CEB7, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xda) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */ - (164U) << 7 | /* coeff 6/9 */ - (125U) << 16 | /* coef 3/12 */ - (169U) << 23, /* coeff 7/8 */ - .tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */ - (90U) << 8 | /* coeff 1/14 */ - (141U) << 16 | /* coeff 4/11 */ - (155U) << 24, /* coeff 5/10 */ - .tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */ - (216U) << 7 | /* coeff 6/9 */ - (105U) << 16 | /* coef 3/12 */ - (233U) << 23, /* coeff 7/8 */ - .tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */ - (44U) << 8 | /* coeff 1/14 */ - (145U) << 16 | /* coeff 4/11 */ - (184U) << 24, /* coeff 5/10 */ -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1), - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c deleted file mode 100644 index 55366cf74..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0xBBDE739B, - .phy_pre_ref1_init = 0xDEFBDEF7, - .phy_pre_ref2_init = 0x0000E739, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xF0) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0025, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0043, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x006B, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFE, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF6, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0020, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0044, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0064, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0077, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c deleted file mode 100644 index d57d0696e..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - .phy_pre_ref0_init = RW0PS(0, 0x19) | - RW0PS(1, 0x19U) | - RW0PS(2, 0x1AU) | - RW0PS(3, 0x1BU) | - RW0PS(4, 0x1CU) | - RW0PS(5, 0x1CU) | - RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ - .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ - RW1PS(7, 0x1EU) | - RW1PS(8, 0x1EU) | - RW1PS(9, 0x1EU) | - RW1PS(10, 0x1DU) | - RW1PS(11, 0x1CU) | - RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ - .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ - RW2PS(13, 0x1BU) | - RW2PS(14, 0x1AU) | - RW2PS(15, 0x19U), - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(205) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* BLE 26MHz Channel Filter */ - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, - - /* BLE 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079, - - /* 32MHz */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c deleted file mode 100644 index cc680b610..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x37ACE2F7, - .phy_pre_ref1_init = 0xADF3BDEF, - .phy_pre_ref2_init = 0x0000BE33, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xCD) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x000C, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003D, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008F, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0006, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFDF, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE3, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c deleted file mode 100644 index 49c6dc75c..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0xF38B5273, - .phy_pre_ref1_init = 0x8CEF9CE6, - .phy_pre_ref2_init = 0x00009D2D, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xb0) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(3) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEB, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE9, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0008, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003A, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0090, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE1, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0034, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009A, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0021, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x0013, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFC9, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x005E, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFE1, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEE, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0034, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFB7, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x003B, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x004F, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFF5B, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0xFFB5, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x018B, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x000C, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0011, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000B, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE0, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x000F, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0019, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x000C, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFCD, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFD7, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0017, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0075, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00BB, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c deleted file mode 100644 index 46f6c8508..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x79CDEB39, - .phy_pre_ref1_init = 0xCE77DEF7, - .phy_pre_ref2_init = 0x0000CEB7, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xb0) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */ - (276U) << 7 | /* Coeff 6/9 */ - (62U) << 16 | /* Coef 3/12 */ - (326U) << 23, /* Coeff 7/8 */ - .tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */ - (10U) << 8 | /* Coeff 1/14 */ - (121U) << 16 | /* Coeff 4/11 */ - (198U) << 24, /* Coeff 5/10 */ - .tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */ - (330U) << 7 | /* Coeff 6/9 */ - (7U) << 16 | /* Coef 3/12 */ - (510U) << 23, /* Coeff 7/8 */ - .tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */ - (0U) << 8 | /* Coeff 1/14 */ - (37U) << 16 | /* Coeff 4/11 */ - (138U) << 24, /* Coeff 5/10 */ -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c deleted file mode 100644 index dcfc95747..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* ========================= DATA RATE ONLY settings ===============*/ -/*! - * @brief XCVR 1Mbps DATA RATE specific configure structure - */ -const xcvr_datarate_config_t xcvr_1mbps_config = -{ - .data_rate = DR_1MBPS, - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0xF) | -#if !RADIO_IS_GEN_2P1 - XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_PHY_EL_CFG_EL_INTERVAL(0x20) , - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - - .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - - .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(10) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(21), - .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(12) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(26), - - .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), - - .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), - - .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), - .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(3) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), - - .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(33) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(6), - .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(7), -}; - -/*! - * @brief XCVR 500K bps DATA RATE specific configure structure - */ -const xcvr_datarate_config_t xcvr_500kbps_config = -{ - .data_rate = DR_500KBPS, - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | -#if !RADIO_IS_GEN_2P1 - XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_PHY_EL_CFG_EL_INTERVAL(0x10), - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - - .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - - .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), - .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(36), - - .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), - - .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), - - .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), - .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), - - .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), - .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), -}; - -/*! - * @brief XCVR 250K bps DATA RATE specific configure structure - */ -const xcvr_datarate_config_t xcvr_250kbps_config = -{ - .data_rate = DR_250KBPS, - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x4) | -#if !RADIO_IS_GEN_2P1 - XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_PHY_EL_CFG_EL_INTERVAL(0x8) , - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(4) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - - .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - - .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(34), - .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(20) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(42), - - .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), - - .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), - - .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), - .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), - - .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(13) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), - .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c deleted file mode 100644 index 44eb38c1f..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t msk_mode_config = -{ - .radio_mode = MSK, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x79CDEB38, - .phy_pre_ref1_init = 0xCE77DFF7, - .phy_pre_ref2_init = 0x0000CEB7, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(208U) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = -{ - .radio_mode = MSK, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - /* MSK 1MBPS channel filter @ 26MHz RF OSC */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, - - /* MSK 1MBPS channel filter @ 32MHz RF OSC */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = -{ - .radio_mode = MSK, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - /* MSK 500KBPS channel filter @ 26MHz RF OSC */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092, - - /* MSK 500KBPS channel filter @ 32MHz RF OSC */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = -{ - .radio_mode = MSK, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, - - /* MSK 250KBPS channel filter @ 32MHz RF OSC */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c b/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c deleted file mode 100644 index 47d6f5f05..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -const xcvr_mode_config_t zgbe_mode_config = -{ - .radio_mode = ZIGBEE_MODE, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x0, /* Not used in Zigbee */ - .phy_pre_ref1_init = 0x0, /* Not used in Zigbee */ - .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */ - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xC0) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_PLL_DIG configs */ - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ -#else - .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) , - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config = -{ - .radio_mode = ZIGBEE_MODE, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ - - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2, - - /* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -/* CUSTOM datarate dependent config structure for ONLY 802.15.4 */ -/*! - * @brief XCVR 500K bps DATA RATE specific configure structure - */ -const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config = -{ - .data_rate = DR_500KBPS, - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | - XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | - XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) , - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), - - .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | - XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), - - .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), - .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47), - - .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), - - .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | - XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), - - .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), - .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | - XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), - - .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), - .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) | - XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0), -}; - diff --git a/third_party/nxp/MKW41Z4/XCVR/dbg_ram_capture.c b/third_party/nxp/MKW41Z4/XCVR/dbg_ram_capture.c deleted file mode 100644 index b119a82d4..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/dbg_ram_capture.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_device_registers.h" -#include "fsl_xcvr.h" -#include "dbg_ram_capture.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#if RADIO_IS_GEN_3P0 -#define PKT_RAM_SIZE_16B_WORDS (1152) /* Number of 16bit entries in each Packet RAM bank */ -#else -#define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM bank */ -#endif /* RADIO_IS_GEN_3P0 */ -#define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0)) -#define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0)) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -void dbg_ram_init(void) -{ - XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns on clocking to DMA/DBG blocks */ - XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to just XCVR */ - - /* Some external code must perform the RX warmup request. */ -} - - -dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer) -{ - dbgRamStatus_t status = DBG_RAM_SUCCESS; - uint32_t temp; - volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1; - uint8_t * output_ptr; - uint16_t i; - - /* Some external code must perform the RX warmup request after the dbg_ram_init() call */ - - if (result_buffer == NULL) - { - status = DBG_RAM_FAIL_NULL_POINTER; - } - else - { - if (buffer_sz_bytes > (544*2*2)) - { - status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT; - } - else - { - temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; - switch (dbg_page) - { - case DBG_PAGE_RXDIGIQ: - case DBG_PAGE_RAWADCIQ: - case DBG_PAGE_DCESTIQ: - XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); - - while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) - { - /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ - } - /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ - output_ptr = result_buffer; -#if !RADIO_IS_GEN_2P1 - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); - pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]); -#else - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); - pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */ -#endif /* !RADIO_IS_GEN_2P1 */ - /* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */ - for (i = 0; i < buffer_sz_bytes / 4; i++) - { - *output_ptr++ = *pkt_ram_ptr0++; - *output_ptr++ = *pkt_ram_ptr0++; - *output_ptr++ = *pkt_ram_ptr1++; - *output_ptr++ = *pkt_ram_ptr1++; - } - - break; - case DBG_PAGE_RXINPH: - case DBG_PAGE_DEMOD_HARD: - case DBG_PAGE_DEMOD_SOFT: - case DBG_PAGE_DEMOD_DATA: - case DBG_PAGE_DEMOD_CFO_PH: - XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); - while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) - { - /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ - } - /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ - output_ptr = result_buffer; -#if !RADIO_IS_GEN_2P1 - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); -#else - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); -#endif /* !RADIO_IS_GEN_2P1 */ - /* This is for non I/Q */ - for (i = 0; i < buffer_sz_bytes; i++) - { - *output_ptr = *pkt_ram_ptr0; - pkt_ram_ptr0++; - output_ptr++; - } - break; - case DBG_PAGE_IDLE: - default: - status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */ - break; - } - } - } - - XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */ - - /* Process the samples and copy to output pointer */ - - XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */ - XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */ - - return status; -} - diff --git a/third_party/nxp/MKW41Z4/XCVR/dbg_ram_capture.h b/third_party/nxp/MKW41Z4/XCVR/dbg_ram_capture.h deleted file mode 100644 index fabba7dae..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/dbg_ram_capture.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _DBG_RAM_CAPTURE_H_ -/* clang-format off */ -#define _DBG_RAM_CAPTURE_H_ -/* clang-format on */ - -#include "fsl_common.h" -#include "fsl_device_registers.h" - -/*! - * @addtogroup xcvr - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Page definitions */ -#define DBG_PAGE_IDLE (0x00) -#define DBG_PAGE_RXDIGIQ (0x01) -#define DBG_PAGE_RAWADCIQ (0x04) -#define DBG_PAGE_DCESTIQ (0x07) -#define DBG_PAGE_RXINPH (0x0A) -#define DBG_PAGE_DEMOD_HARD (0x0B) -#define DBG_PAGE_DEMOD_SOFT (0x0C) -#define DBG_PAGE_DEMOD_DATA (0x0D) -#define DBG_PAGE_DEMOD_CFO_PH (0x0E) - -typedef enum _dbgRamStatus -{ - DBG_RAM_SUCCESS = 0, - DBG_RAM_FAIL_SAMPLE_NUM_LIMIT = 1, - DBG_RAM_FAIL_PAGE_ERROR = 2, - DBG_RAM_FAIL_NULL_POINTER = 3, - DBG_RAM_INVALID_TRIG_SETTING = 4, - DBG_RAM_FAIL_NOT_ENOUGH_SAMPLES = 5, - DBG_RAM_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling */ -} dbgRamStatus_t; - -#if RADIO_IS_GEN_3P0 -typedef enum _dbgRamStartTriggerType -{ - NO_START_TRIG = 0, - START_ON_FSK_PREAMBLE_FOUND = 1, - START_ON_FSK_AA_MATCH = 2, - START_ON_ZBDEMOD_PREAMBLE_FOUND = 3, - START_ON_ZBDEMOD_SFD_MATCH = 4, - START_ON_AGC_DCOC_GAIN_CHG = 5, - START_ON_TSM_RX_DIG_EN = 6, - START_ON_TSM_SPARE2_EN = 7, - INVALID_START_TRIG = 8 -} dbgRamStartTriggerType; - -typedef enum _dbgRamStopTriggerType -{ - NO_STOP_TRIG = 0, - STOP_ON_FSK_PREAMBLE_FOUND = 1, - STOP_ON_FSK_AA_MATCH = 2, - STOP_ON_ZBDEMOD_PREAMBLE_FOUND = 3, - STOP_ON_ZBDEMOD_SFD_MATCH = 4, - STOP_ON_AGC_DCOC_GAIN_CHG = 5, - STOP_ON_TSM_RX_DIG_EN = 6, - STOP_ON_TSM_SPARE3_EN = 7, - STOP_ON_TSM_PLL_UNLOCK = 8, - STOP_ON_BLE_CRC_ERROR_INC = 9, - STOP_ON_CRC_FAIL_ZGBE_GENFSK = 10, - STOP_ON_GENFSK_HEADER_FAIL = 11, - INVALID_STOP_TRIG = 12 -} dbgRamStopTriggerType; -#endif /* RADIO_IS_GEN_3P0 */ - -/*! ********************************************************************************* - * \brief This function prepares for sample capture to packet RAM. - * - * \return None. - * - * \details - * This routine assumes that some other functions in the calling routine both set - * the channel and force RX warmup before calling ::dbg_ram_capture(). - ***********************************************************************************/ -void dbg_ram_init(void); - -/*! ********************************************************************************* - * \brief This function performs any state restoration at the completion of PKT RAM capture. - * - * \details - * Any clocks enabled to the packet RAM capture circuitry are disabled. - ***********************************************************************************/ -void dbg_ram_release(void); - -#if RADIO_IS_GEN_3P0 -/*! ********************************************************************************* - * \brief This function initiates the capture of transceiver data to the transceiver packet RAM. - * - * \param[in] dbg_page - The page selector (DBG_PAGE). - * \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled). - * \param[in] dbg_stop_trigger - The trigger to stop acquisition (must be "no trigger" if a start trigger is enabled). - * - * \return Status of the request. - * - * \details - * This function starts the process of capturing data to the packet RAM. Depending upon the start and stop trigger - * settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to - * perform a blocking wait for completion or allow polling for completion of the capture. - * After any capture has completed, a separate routine must be called to postprocess the capture and copy all - * data out of the packet RAM into a normal RAM buffer. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_start_capture(uint8_t dbg_page, dbgRamStartTriggerType start_trig, dbgRamStopTriggerType stop_trig); - -/*! ********************************************************************************* - * \brief This function performs a blocking wait for completion of the capture of transceiver data to the transceiver packet RAM. - * - * \return Status of the request, DBG_RAM_SUCCESS if capture is complete. - * - * \details - * This function performs a wait loop for capture completion and may take an indeterminate amount of time for - * some capture trigger types. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_wait_for_complete(void); /* Blocking wait for capture completion, no matter what trigger type */ - -/*! ********************************************************************************* - * \brief This function polls the state of the capture of transceiver data to the transceiver packet RAM. - * - * \return Status of the request, DBG_RAM_SUCCESS if capture is complete, DBG_RAM_CAPTURE_NOT_COMPLETE if not complete. - * - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_poll_capture_status(void); /* Non-blocking completion check, just reads the current status of the capure */ - -/*! ********************************************************************************* - * \brief This function processes the captured data into a usable order and copies from packet RAM to normal RAM. - * - * \param[in] dbg_page - The page selector (DBG_PAGE). - * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) - * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. - * - * \return None. - * - * \details - * Data is copied from packet RAM in bytes to ensure no access problems. Data is unpacked from packet RAM - * (either sequentially captured or simultaneously captured) into a linear RAM buffer in system RAM. - * If a start trigger is enabled then the first buffer_sz_bytes that are captured are copied out. - * If a stop trigger is enabled then the last buffer_sz_bytes that are captured are copied out. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_postproc_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); /* postprocess a capture to unpack data */ - -#else -/*! ********************************************************************************* - * \brief This function captures transceiver data to the transceiver packet RAM. - * - * \param[in] dbg_page - The page selector (DBG_PAGE). - * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) - * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. - * - * \return None. - * - * \details - * The capture to packet RAM always captures a full PKT_RAM worth of samples. The samples will be - * copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have - * been copied. Data will be copied - * NOTE: This routine has a slight hazard of getting stuck waiting for debug RAM to fill up when RX has - * not been enabled or RX ends before the RAM fills up (such as when capturing packet data ). It is - * intended to be used with manually triggered RX where RX data will continue as long as needed. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); -#endif /* RADIO_IS_GEN_3P0 */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _DBG_RAM_CAPTURE_H_ */ - diff --git a/third_party/nxp/MKW41Z4/XCVR/dma_capture.c b/third_party/nxp/MKW41Z4/XCVR/dma_capture.c deleted file mode 100644 index 2feffff55..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/dma_capture.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "MKW41Z4.h" -#include "fsl_xcvr.h" -#include "fsl_edma.h" -#include "fsl_dmamux.h" -#include "dma_capture.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM */ -#define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0)) -#define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0)) - -const dma_capture_lut_t dma_table [DMA_PAGE_MAX] = -{ - /* DMA_PAGE OSR */ - {DMA_PAGE_IDLE, 0xF}, - {DMA_PAGE_RXDIGIQ, 0x4}, - {DMA_PAGE_RXDIGI, 0x2}, - {DMA_PAGE_RXDIGQ, 0x2}, - {DMA_PAGE_RAWADCIQ, 0x2}, - {DMA_PAGE_RAWADCI, 0x1}, - {DMA_PAGE_RAWADCQ, 0x1}, - {DMA_PAGE_DCESTIQ, 0x4}, - {DMA_PAGE_DCESTI, 0x2}, - {DMA_PAGE_DCESTQ, 0x2}, - {DMA_PAGE_RXINPH, 0x1}, - {DMA_PAGE_DEMOD_HARD, 0xF}, - {DMA_PAGE_DEMOD_SOFT, 0xF}, - {DMA_PAGE_DEMOD_DATA, 0xF}, - {DMA_PAGE_DEMOD_CFO_PH, 0xF}, -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Initialize to an invalid value. */ -uint8_t osr_temp = 0xF; -edma_handle_t g_EDMA_Handle; -volatile bool g_Transfer_Done = false; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* User callback function for EDMA transfer. */ -void EDMA_Callback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - if (transferDone) - { - g_Transfer_Done = true; - } -} - -/******************************************************************************* - * Code - ******************************************************************************/ -void dma_init(void) -{ - edma_config_t dmaConfig; - - /* Configure DMAMUX */ - DMAMUX_Init(DMAMUX0); - DMAMUX_SetSource(DMAMUX0, 0, 11); - DMAMUX_EnableChannel(DMAMUX0, 0); - - /* Configure EDMA transfer */ - EDMA_GetDefaultConfig(&dmaConfig); - EDMA_Init(DMA0, &dmaConfig); - EDMA_CreateHandle(&g_EDMA_Handle, DMA0, 0); - EDMA_SetCallback(&g_EDMA_Handle, EDMA_Callback, NULL); - - /* Turns on clocking to DMA/DBG blocks */ - XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; - /* Save current osr config */ - osr_temp = (XCVR_RX_DIG->RX_DIG_CTRL & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK) >> XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT; - - /* Some external code must perform the RX warmup request */ -} - -dmaStatus_t dma_wait_for_complete(void) -{ - dmaStatus_t status = DMA_SUCCESS; - - /* Wait for EDMA transfer finish */ - while (g_Transfer_Done != true) - { - /* Timeout */ - if (XCVR_MISC->DMA_CTRL & XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK) - { - /* Clear flag */ - XCVR_MISC->DMA_CTRL |= XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK; - - /* Capture error */ - status = DMA_CAPTURE_NOT_COMPLETE; - - break; - } - } - - /* Release DMA module */ - dma_release(); - - return status; -} - -dmaStatus_t dma_poll_capture_status(void) -{ - dmaStatus_t status = DMA_SUCCESS; - - if (g_Transfer_Done != true) - { - /* Timeout */ - if (XCVR_MISC->DMA_CTRL & XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK) - { - /* Clear flag */ - XCVR_MISC->DMA_CTRL |= XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK; - /* Release DMA module */ - dma_release(); - /* Capture error */ - status = DMA_CAPTURE_NOT_COMPLETE; - } - } - - return status; -} - -void dma_release(void) -{ - /* Restart flag */ - g_Transfer_Done = false; - - /* Disable DMA */ - XCVR_MISC->DMA_CTRL &= ~XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK; - - /* Gasket bypass disable */ - RSIM->CONTROL &= ~(RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK | - RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK); - - /* Restore previous osr config (if any) */ - if (osr_temp != 0xF) - { - XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK; - XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(osr_temp); - osr_temp = 0xF; - } -} - -#if RADIO_IS_GEN_3P0 -dmaStatus_t dma_start_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer, dmaStartTriggerType start_trig) -{ - -} -#else -dmaStatus_t dma_capture(uint8_t dma_page, uint16_t buffer_sz_bytes, uint32_t * result_buffer) -{ - dmaStatus_t status = DMA_SUCCESS; - - /* Some external code must perform the RX warmup request after the d_init() call. */ - if (result_buffer == NULL) - { - status = DMA_FAIL_NULL_POINTER; - } - else - { - if (buffer_sz_bytes > (4096)) - { - status = DMA_FAIL_SAMPLE_NUM_LIMIT; - } - else - { - uint32_t temp = XCVR_MISC->DMA_CTRL & ~XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK; - edma_transfer_config_t transferConfig; - - /* Wait for Network Address Match to start capturing */ -// while (!((XCVR_MISC->DMA_CTRL & XCVR_CTRL_D MA_CTRL_DMA_TRIGGERRED_MASK))); - - switch (dma_page) - { - case DMA_PAGE_RXDIGIQ: - case DMA_PAGE_RAWADCIQ: - case DMA_PAGE_DCESTIQ: - case DMA_PAGE_RXINPH: - case DMA_PAGE_DEMOD_CFO_PH: - - /* Set OSR */ - XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK; - XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(dma_table[dma_page].osr); - - /* Single request mode */ - XCVR_MISC->DMA_CTRL |= XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK; - XCVR_MISC->DMA_CTRL &= ~XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK; - - /* Gasket bypass disable */ - RSIM->CONTROL &= ~(RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK | - RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK); - break; - - case DMA_PAGE_DEMOD_HARD: - case DMA_PAGE_DEMOD_SOFT: - case DMA_PAGE_DEMOD_DATA: - /* Data rate is too low to use Single Req mode */ - - /* Request per sample mode */ - XCVR_MISC->DMA_CTRL &= XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK; - XCVR_MISC->DMA_CTRL |= XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK; - - /* Gasket bypass enable */ - RSIM->CONTROL |= (RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK | - RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK); - break; - - case DMA_PAGE_IDLE: - default: - /* Illegal capture page request */ - status = DMA_FAIL_PAGE_ERROR; - break; - } - - if (status == DMA_SUCCESS) - { - /* Select DMA_page */ - XCVR_MISC->DMA_CTRL = temp | XCVR_CTRL_DMA_CTRL_DMA_PAGE(dma_page); - - /* EDMA transfer config */ - EDMA_PrepareTransfer(&transferConfig, /* Config */ - (uint32_t *)&XCVR_MISC->DMA_DATA, /* Source address */ - sizeof(uint32_t), /* Source address width(bytes) */ - result_buffer, /* Destination address */ - sizeof(*result_buffer), /* Destination address width */ - sizeof(uint32_t), /* Transfer bytes per channel request */ - buffer_sz_bytes, /* Bytes to be transferred */ - kEDMA_PeripheralToMemory); /* Transfer type */ - - EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig); - EDMA_StartTransfer(&g_EDMA_Handle); - } - } - } - - return status; -} -#endif /* RADIO_IS_GEN_3P0 */ diff --git a/third_party/nxp/MKW41Z4/XCVR/dma_capture.h b/third_party/nxp/MKW41Z4/XCVR/dma_capture.h deleted file mode 100644 index 5a8634b19..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/dma_capture.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _DMA_CAPTURE_H_ -#define _DMA_CAPTURE_H_ - -#include "fsl_common.h" - -#if RADIO_IS_GEN_3P0 -#include "K32W042S1M2_M0P.h" -#else -#include "fsl_device_registers.h" -#endif /* RADIO_IS_GEN_3P0 */ - -/*! - * @addtogroup xcvr - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Page definitions */ -#define DMA_PAGE_IDLE (0x00) -#define DMA_PAGE_RXDIGIQ (0x01) -#define DMA_PAGE_RXDIGI (0x02) -#define DMA_PAGE_RXDIGQ (0x03) -#define DMA_PAGE_RAWADCIQ (0x04) -#define DMA_PAGE_RAWADCI (0x05) -#define DMA_PAGE_RAWADCQ (0x06) -#define DMA_PAGE_DCESTIQ (0x07) -#define DMA_PAGE_DCESTI (0x08) -#define DMA_PAGE_DCESTQ (0x09) -#define DMA_PAGE_RXINPH (0x0A) -#define DMA_PAGE_DEMOD_HARD (0x0B) -#define DMA_PAGE_DEMOD_SOFT (0x0C) -#define DMA_PAGE_DEMOD_DATA (0x0D) -#define DMA_PAGE_DEMOD_CFO_PH (0x0E) - -#define DMA_PAGE_MAX (0x0F) - -typedef struct -{ - uint8_t dma_page; - uint8_t osr; -} dma_capture_lut_t; - -typedef enum _dmaStatus -{ - DMA_SUCCESS = 0, - DMA_FAIL_SAMPLE_NUM_LIMIT = 1, - DMA_FAIL_PAGE_ERROR = 2, - DMA_FAIL_NULL_POINTER = 3, - DMA_INVALID_TRIG_SETTING = 4, - DMA_FAIL_NOT_ENOUGH_SAMPLES = 5, - DMA_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling. */ -} dmaStatus_t; - -#if RADIO_IS_GEN_3P0 -typedef enum dmaStartTriggerType -{ - NO_DMA_START_TRIG = 0, - START_DMA_ON_FSK_PREAMBLE_FOUND = 1, - START_DMA_ON_FSK_AA_MATCH = 2, - START_DMA_ON_ZBDEMOD_PREAMBLE_FOUND = 3, - START_DMA_ON_ZBDEMOD_SFD_MATCH = 4, - START_DMA_ON_AGC_DCOC_GAIN_CHG = 5, - START_DMA_ON_TSM_RX_DIG_EN = 6, - START_ODMA_N_TSM_SPARE2_EN = 7, - INVALID_DMA_START_TRIG = 8 -} dmaStartTriggerType; -#endif /* RADIO_IS_GEN_3P0 */ - -/*! ********************************************************************************* -* \brief This function prepares for sample capture to system RAM using DMA. -* -* \return None. -* -* \details -* This routine assumes that some other functions in the calling routine both set -* the channel and force RX warmup before calling the appropriate capture routine. -* This routine may corrupt the OSR value of the system but restores it in the ::dma_release() routine. -***********************************************************************************/ -void dma_init(void); - -/*! ********************************************************************************* -* \brief This function performs a blocking wait for completion of the capture of transceiver data to the system RAM. -* -* \return Status of the request, DMA_SUCCESS if capture is complete. -* -* \details -* This function performs a wait loop for capture completion and may take an indeterminate amount of time for -* some capture trigger types. -* Blocking wait for capture completion, no matter what trigger type. -***********************************************************************************/ -dmaStatus_t dma_wait_for_complete(void); - -/*! ********************************************************************************* -* \brief This function polls the state of the capture of transceiver data to the transceiver packet RAM. -* -* \return Status of the request, DMA_SUCCESS if capture is complete, DMA_CAPTURE_NOT_COMPLETE if not complete. -* -* \details -* Non-blocking completion check, just reads the current status of the capure. -***********************************************************************************/ -dmaStatus_t dma_poll_capture_status(void); - -/*! ********************************************************************************* -* \brief This function performs any state restoration at the completion of DMA capture to system RAM. -* -* \details -* Because DMA capture only works at specific OSR values the DMA capture routines must force the OSR to the -* supported value when capturing data. This forced OSR value must be restored after DMA operations are complete. -***********************************************************************************/ -void dma_release(void); - -#if RADIO_IS_GEN_3P0 -/*! ********************************************************************************* -* \brief This function initiates the capture of transceiver data to the system RAM. -* -* \param[in] dbg_page - The page selector (DBG_PAGE). -* \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) -* \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. -* \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled). -* -* \return Status of the request. -* -* \details -* This function starts the process of capturing data to the system RAM. Depending upon the start trigger -* settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to -* perform a blocking wait for completion or allow polling for completion of the capture. -* After any capture has completed, data will be left in system RAM. -***********************************************************************************/ -dmaStatus_t dma_start_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer, dmaStartTriggerType start_trig); - -#else /* Gen 2.0 version */ -/*! ********************************************************************************* -* \brief This function captures transceiver data to the transceiver packet RAM. -* -* \param[in] dma_page - The page selector (DBG_PAGE). -* \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) -* \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. -* -* \return None. -* -* \details -* The capture to system RAM . The samples will be -* copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have -* been copied. Data will be copied -* NOTE: This routine has a slight hazard of getting stuck waiting for the specified number of butes when RX has -* not been enabled or RX ends before the specified byte count is achieved (such as when capturing packet data ). It is -* intended to be used with manually triggered RX where RX data will continue as long as needed. -***********************************************************************************/ -dmaStatus_t dma_capture(uint8_t dma_page, uint16_t buffer_sz_bytes, uint32_t * result_buffer); -#endif /* RADIO_IS_GEN_3P0 */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _DMA_CAPTURE_H_ */ - - diff --git a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.c b/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.c deleted file mode 100644 index cbc1531c1..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.c +++ /dev/null @@ -1,2132 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_xcvr.h" -#include "fsl_xcvr_trim.h" -#include -#include "ifr_radio.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define channelMapTableSize (128U) -#define gPllDenom_c 0x02000000U /* Denominator is a constant value */ -#define ABS(x) ((x) > 0 ? (x) : -(x)) - -#ifndef TRUE -#define TRUE (true) -#endif - -#ifndef FALSE -#define FALSE (false) -#endif -#define RF_OSCILLATOR_STAYS_ON (false) /* Control whether RF_OSC can be left on all the time. */ -#define RF_OSCILLATOR_READY ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U) - -#ifndef EXTERNAL_CLOCK_GEN -#define EXTERNAL_CLOCK_GEN 0 -#endif - -#define ANT_A 1 -#define ANT_B 0 - -#ifndef XCVR_COEX_RF_ACTIVE_PIN -#define XCVR_COEX_RF_ACTIVE_PIN ANT_B -#endif /* XCVR_COEX_RF_ACTIVE_PIN */ - -typedef struct xcvr_pllChannel_tag -{ - unsigned int integer; - unsigned int numerator; -} xcvr_pllChannel_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address); -void rf_osc_startup(void); -void rf_osc_shutdown(void); -extern double trunc (double); -extern double round (double); - -/******************************************************************************* - * Variables - ******************************************************************************/ -static panic_fptr s_PanicFunctionPtr = NULL; -const xcvr_pllChannel_t mapTable [channelMapTableSize] = -{ - {0x00000025, 0x07C00000}, /* 0 */ - {0x00000025, 0x07C80000}, /* 1 */ - {0x00000025, 0x07D00000}, /* 2 */ - {0x00000025, 0x07D80000}, /* 3 */ - {0x00000025, 0x07E00000}, /* 4 */ - {0x00000025, 0x07E80000}, /* 5 */ - {0x00000025, 0x07F00000}, /* 6 */ - {0x00000025, 0x07F80000}, /* 7 */ - {0x00000025, 0x00000000}, /* 8 */ - {0x00000025, 0x00080000}, /* 9 */ - {0x00000025, 0x00100000}, /* 10 */ - {0x00000025, 0x00180000}, /* 11 */ - {0x00000025, 0x00200000}, /* 12 */ - {0x00000025, 0x00280000}, /* 13 */ - {0x00000025, 0x00300000}, /* 14 */ - {0x00000025, 0x00380000}, /* 15 */ - {0x00000025, 0x00400000}, /* 16 */ - {0x00000025, 0x00480000}, /* 17 */ - {0x00000025, 0x00500000}, /* 18 */ - {0x00000025, 0x00580000}, /* 19 */ - {0x00000025, 0x00600000}, /* 20 */ - {0x00000025, 0x00680000}, /* 21 */ - {0x00000025, 0x00700000}, /* 22 */ - {0x00000025, 0x00780000}, /* 23 */ - {0x00000025, 0x00800000}, /* 24 */ - {0x00000025, 0x00880000}, /* 25 */ - {0x00000025, 0x00900000}, /* 26 */ - {0x00000025, 0x00980000}, /* 27 */ - {0x00000025, 0x00A00000}, /* 28 */ - {0x00000025, 0x00A80000}, /* 29 */ - {0x00000025, 0x00B00000}, /* 30 */ - {0x00000025, 0x00B80000}, /* 31 */ - {0x00000025, 0x00C00000}, /* 32 */ - {0x00000025, 0x00C80000}, /* 33 */ - {0x00000025, 0x00D00000}, /* 34 */ - {0x00000025, 0x00D80000}, /* 35 */ - {0x00000025, 0x00E00000}, /* 36 */ - {0x00000025, 0x00E80000}, /* 37 */ - {0x00000025, 0x00F00000}, /* 38 */ - {0x00000025, 0x00F80000}, /* 39 */ - {0x00000025, 0x01000000}, /* 40 */ - {0x00000026, 0x07080000}, /* 41 */ - {0x00000026, 0x07100000}, /* 42 */ - {0x00000026, 0x07180000}, /* 43 */ - {0x00000026, 0x07200000}, /* 44 */ - {0x00000026, 0x07280000}, /* 45 */ - {0x00000026, 0x07300000}, /* 46 */ - {0x00000026, 0x07380000}, /* 47 */ - {0x00000026, 0x07400000}, /* 48 */ - {0x00000026, 0x07480000}, /* 49 */ - {0x00000026, 0x07500000}, /* 50 */ - {0x00000026, 0x07580000}, /* 51 */ - {0x00000026, 0x07600000}, /* 52 */ - {0x00000026, 0x07680000}, /* 53 */ - {0x00000026, 0x07700000}, /* 54 */ - {0x00000026, 0x07780000}, /* 55 */ - {0x00000026, 0x07800000}, /* 56 */ - {0x00000026, 0x07880000}, /* 57 */ - {0x00000026, 0x07900000}, /* 58 */ - {0x00000026, 0x07980000}, /* 59 */ - {0x00000026, 0x07A00000}, /* 60 */ - {0x00000026, 0x07A80000}, /* 61 */ - {0x00000026, 0x07B00000}, /* 62 */ - {0x00000026, 0x07B80000}, /* 63 */ - {0x00000026, 0x07C00000}, /* 64 */ - {0x00000026, 0x07C80000}, /* 65 */ - {0x00000026, 0x07D00000}, /* 66 */ - {0x00000026, 0x07D80000}, /* 67 */ - {0x00000026, 0x07E00000}, /* 68 */ - {0x00000026, 0x07E80000}, /* 69 */ - {0x00000026, 0x07F00000}, /* 70 */ - {0x00000026, 0x07F80000}, /* 71 */ - {0x00000026, 0x00000000}, /* 72 */ - {0x00000026, 0x00080000}, /* 73 */ - {0x00000026, 0x00100000}, /* 74 */ - {0x00000026, 0x00180000}, /* 75 */ - {0x00000026, 0x00200000}, /* 76 */ - {0x00000026, 0x00280000}, /* 77 */ - {0x00000026, 0x00300000}, /* 78 */ - {0x00000026, 0x00380000}, /* 79 */ - {0x00000026, 0x00400000}, /* 80 */ - {0x00000026, 0x00480000}, /* 81 */ - {0x00000026, 0x00500000}, /* 82 */ - {0x00000026, 0x00580000}, /* 83 */ - {0x00000026, 0x00600000}, /* 84 */ - {0x00000026, 0x00680000}, /* 85 */ - {0x00000026, 0x00700000}, /* 86 */ - {0x00000026, 0x00780000}, /* 87 */ - {0x00000026, 0x00800000}, /* 88 */ - {0x00000026, 0x00880000}, /* 89 */ - {0x00000026, 0x00900000}, /* 90 */ - {0x00000026, 0x00980000}, /* 91 */ - {0x00000026, 0x00A00000}, /* 92 */ - {0x00000026, 0x00A80000}, /* 93 */ - {0x00000026, 0x00B00000}, /* 94 */ - {0x00000026, 0x00B80000}, /* 95 */ - {0x00000026, 0x00C00000}, /* 96 */ - {0x00000026, 0x00C80000}, /* 97 */ - {0x00000026, 0x00D00000}, /* 98 */ - {0x00000026, 0x00D80000}, /* 99 */ - {0x00000026, 0x00E00000}, /* 100 */ - {0x00000026, 0x00E80000}, /* 101 */ - {0x00000026, 0x00F00000}, /* 102 */ - {0x00000026, 0x00F80000}, /* 103 */ - {0x00000026, 0x01000000}, /* 104 */ - {0x00000027, 0x07080000}, /* 105 */ - {0x00000027, 0x07100000}, /* 106 */ - {0x00000027, 0x07180000}, /* 107 */ - {0x00000027, 0x07200000}, /* 108 */ - {0x00000027, 0x07280000}, /* 109 */ - {0x00000027, 0x07300000}, /* 110 */ - {0x00000027, 0x07380000}, /* 111 */ - {0x00000027, 0x07400000}, /* 112 */ - {0x00000027, 0x07480000}, /* 113 */ - {0x00000027, 0x07500000}, /* 114 */ - {0x00000027, 0x07580000}, /* 115 */ - {0x00000027, 0x07600000}, /* 116 */ - {0x00000027, 0x07680000}, /* 117 */ - {0x00000027, 0x07700000}, /* 118 */ - {0x00000027, 0x07780000}, /* 119 */ - {0x00000027, 0x07800000}, /* 120 */ - {0x00000027, 0x07880000}, /* 121 */ - {0x00000027, 0x07900000}, /* 122 */ - {0x00000027, 0x07980000}, /* 123 */ - {0x00000027, 0x07A00000}, /* 124 */ - {0x00000027, 0x07A80000}, /* 125 */ - {0x00000027, 0x07B00000}, /* 126 */ - {0x00000027, 0x07B80000} /* 127 */ -}; - -/* Registers for timing of TX & RX */ -#if RADIO_IS_GEN_3P0 -uint16_t tx_rx_on_delay = TX_RX_ON_DELinit; -uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init; -#else -#if RF_OSC_26MHZ == 1 -uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ; -#else -uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL; -#endif /* RF_OSC_26MHZ == 1 */ -uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL; -#endif /* RADIO_IS_GEN_3P0 */ - -/* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */ -#if RADIO_IS_GEN_3P0 -const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] = -{ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config, - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config, - &xcvr_MSK_2mbps_config, -}; -#endif /* RADIO_IS_GEN_3P0 */ - -const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] = -{ - &xcvr_BLE_1mbps_config, -#if RADIO_IS_GEN_2P1 - NULL, - NULL, -#else - &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ - &xcvr_ANT_1mbps_config, -#endif /* RADIO_IS_GEN_2P1 */ - &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config, - &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config, - &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config, - &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config, - &xcvr_MSK_1mbps_config, -}; - -const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] = -{ - &xcvr_BLE_1mbps_config, /* Invalid option */ -#if RADIO_IS_GEN_2P1 - NULL, - NULL, -#else - &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */ - &xcvr_ANT_1mbps_config, /* Invalid option */ -#endif /* RADIO_IS_GEN_2P1 */ - &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config, - &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config, - &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config, - &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config, - &xcvr_MSK_500kbps_config, -}; -const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] = -{ - &xcvr_BLE_1mbps_config, /* Invalid option */ -#if RADIO_IS_GEN_2P1 - NULL, - NULL, -#else - &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ - &xcvr_ANT_1mbps_config, /* Invalid option */ -#endif /* RADIO_IS_GEN_2P1 */ - &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config, - &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config, - &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config, - &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config, - &xcvr_MSK_250kbps_config, -}; - -static xcvr_currConfig_t current_xcvr_config; - -void rf_osc_startup(void) -{ - if (!RF_OSCILLATOR_READY) - { - RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; - } - while (!RF_OSCILLATOR_READY) - { - /* Wait for RF_OSC_READY to be asserted before continuing */ - } -} - -void rf_osc_shutdown(void) -{ - if (!RF_OSCILLATOR_STAYS_ON) - { - RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK; - } -} - -/******************************************************************************* - * Code - ******************************************************************************/ -xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) -{ - const xcvr_mode_datarate_config_t * mode_datarate_config; - const xcvr_datarate_config_t * datarate_config ; - const xcvr_mode_config_t * radio_mode_cfg; - const xcvr_common_config_t * radio_common_config; - - xcvrStatus_t status; - - IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = - { - {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/ - {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/ - }; - const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T); - -#ifndef SIMULATION - -#if (EXTERNAL_CLOCK_GEN) - RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */ -#endif /* EXTERNAL_CLOCK_GEN */ - -#if RADIO_IS_GEN_2P0 - RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */ - RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ -#endif /* RADIO_IS_GEN_2P0 */ - - /* Check that this is the proper radio version */ - { - uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT); - - if ( -#if RADIO_IS_GEN_3P0 - (radio_id != 0x5) /* KW3 Gen3 */ -#elif RADIO_IS_GEN_2P1 - (radio_id != 0x5) /* KW35 Gen2.1 */ -#else - (radio_id != 0x3) && /* KW41/31/21 v1 */ - (radio_id != 0xB) /* KW41/31/21 v1.1 */ -#endif /* RADIO_IS_GEN_3P0 */ - ) - { - XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init); - } - } - -#if RADIO_IS_GEN_3P0 - /* Assert Radio Run Request and wait for ack from SPM. */ - RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK; - while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0) - { - } - RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; - rf_osc_startup(); /* Start RF_OSC to allow radio registers access */ -#else - SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; - - /* Load IFR trim values */ - handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES); -#endif /* RADIO_IS_GEN_3P0 */ - -#endif /* ifndef SIMULATION */ - - /* Perform the desired XCVR initialization and configuration */ - status = XCVR_GetDefaultConfig(radio_mode, data_rate, - (const xcvr_common_config_t **)&radio_common_config, - (const xcvr_mode_config_t **)&radio_mode_cfg, - (const xcvr_mode_datarate_config_t **)&mode_datarate_config, - (const xcvr_datarate_config_t **)&datarate_config); - - if (status == gXcvrSuccess_c) - { - status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, - (const xcvr_mode_config_t *)radio_mode_cfg, - (const xcvr_mode_datarate_config_t *)mode_datarate_config, - (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT); - current_xcvr_config.radio_mode = radio_mode; - current_xcvr_config.data_rate = data_rate; - } - - return status; -} - -void XCVR_Deinit(void) -{ -#if RADIO_IS_GEN_3P0 - rf_osc_shutdown(); - RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */ - RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */ -#else - -#endif /* RADIO_IS_GEN_3P0 */ -} - -xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, - data_rate_t data_rate, - const xcvr_common_config_t ** com_config, - const xcvr_mode_config_t ** mode_config, - const xcvr_mode_datarate_config_t ** mode_datarate_config, - const xcvr_datarate_config_t ** datarate_config) -{ - xcvrStatus_t status = gXcvrSuccess_c; - /* Common configuration pointer */ - *com_config = (const xcvr_common_config_t *)&xcvr_common_config; - - /* Mode dependent configuration pointer */ - switch (radio_mode) - { -#if !RADIO_IS_GEN_2P1 - case ZIGBEE_MODE: - *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */ - break; - case ANT_MODE: - *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */ - break; -#endif /* !RADIO_IS_GEN_2P1 */ - case BLE_MODE: - *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */ - break; - case GFSK_BT_0p5_h_0p5: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */ - break; - case GFSK_BT_0p5_h_0p32: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */ - break; - case GFSK_BT_0p5_h_0p7: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */ - break; - case GFSK_BT_0p5_h_1p0: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */ - break; - case GFSK_BT_0p3_h_0p5: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */ - break; - case GFSK_BT_0p7_h_0p5: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */ - break; - case MSK: - *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */ - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - - /* Data rate dependent and modeXdatarate dependent configuration pointers */ - if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ - { - switch (data_rate) - { -#if RADIO_IS_GEN_3P0 - case DR_2MBPS: - if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE)) - { - status = gXcvrInvalidParameters_c; - } - else - { - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */ - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode]; - } - break; -#endif /* RADIO_IS_GEN_3P0 */ - case DR_1MBPS: - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */ - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode]; - break; - case DR_500KBPS: - if (radio_mode == ZIGBEE_MODE) - { - /* See fsl_xcvr_zgbe_config.c for settings */ -#if !RADIO_IS_GEN_2P1 - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */ -#endif /* !RADIO_IS_GEN_2P1 */ - } - else - { - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */ - } - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode]; - break; - case DR_250KBPS: - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */ - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode]; - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - } - - return status; -} - -xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, - const xcvr_mode_config_t *mode_config, - const xcvr_mode_datarate_config_t *mode_datarate_config, - const xcvr_datarate_config_t *datarate_config, - int16_t tempDegC, - XCVR_INIT_MODE_CHG_T first_init) -{ - xcvrStatus_t config_status = gXcvrSuccess_c; - uint32_t temp; - - /* Turn on the module clocks before doing anything */ -#if RADIO_IS_GEN_3P0 - RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */ -#else - SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits; -#endif /* RADIO_IS_GEN_3P0 */ - - /*******************************************************************************/ - /* XCVR_ANA configs */ - /*******************************************************************************/ - - /* Configure PLL Loop Filter */ - if (first_init) - { - XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask; - XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init; - } - - /* Configure VCO KVM */ - XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask; - XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init; - - /* Configure analog filter bandwidth */ - XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask; - XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init; - XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask; - XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init; - -#if RADIO_IS_GEN_2P0 - if (first_init) - { - temp = XCVR_ANA->TX_DAC_PA; - temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK; - temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4); - XCVR_ANA->TX_DAC_PA = temp; - - temp = XCVR_ANA->BB_LDO_2; - temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK; - temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0); - XCVR_ANA->BB_LDO_2 = temp; - - temp = XCVR_ANA->RX_LNA; - temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK; - temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1); - XCVR_ANA->RX_LNA = temp; - - temp = XCVR_ANA->BB_LDO_1; - temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK; - temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1); - XCVR_ANA->BB_LDO_1 = temp; - } -#endif /* RADIO_IS_GEN_2P0 */ - - /*******************************************************************************/ - /* XCVR_MISC configs */ - /*******************************************************************************/ - temp = XCVR_MISC->XCVR_CTRL; - temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK); - temp |= mode_config->xcvr_ctrl.init; - -#if RF_OSC_26MHZ == 1 - { - temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1); - } -#endif /* RF_OSC_26MHZ == 1 */ - - XCVR_MISC->XCVR_CTRL = temp; - -#if RADIO_IS_GEN_2P1 - XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK; -#endif /* RADIO_IS_GEN_2P1 */ - - /*******************************************************************************/ - /* XCVR_PHY configs */ - /*******************************************************************************/ -#if RADIO_IS_GEN_3P0 - XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0; - XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1; - XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg; - XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate; - XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl; -#else - XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init; - XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init; - XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init; - XCVR_PHY->CFG1 = mode_config->phy_cfg1_init; - XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init; - XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */ -#endif /* RADIO_IS_GEN_3P0 */ - - /*******************************************************************************/ - /* XCVR_PLL_DIG configs */ - /*******************************************************************************/ - if (first_init) - { - XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump; - XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl; - XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map; - XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect; - XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl; -#if !RADIO_IS_GEN_2P1 - XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl; -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res; - XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl; - XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1; - XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match; - XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl; - } - - /*******************************************************************************/ - /* XCVR_RX_DIG configs */ - /*******************************************************************************/ - - /* Configure RF Aux PLL for proper operation based on external clock frequency */ - if (first_init) - { - temp = XCVR_ANA->RX_AUXPLL; - temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK; -#if RF_OSC_26MHZ == 1 - { - temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4); - } -#else - { - temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7); - } -#endif /* RF_OSC_26MHZ == 1 */ - XCVR_ANA->RX_AUXPLL = temp; - } - - /* Configure RX_DIG_CTRL */ -#if RF_OSC_26MHZ == 1 - { - temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ - mode_config->rx_dig_ctrl_init_26mhz | /* Mode specific portion of RX_DIG_CTRL init */ - datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */ - } -#else - { - temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ - mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */ - datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */ - 0; /* Always disable the sample rate converter for 32MHz */ - } -#endif /* RF_OSC_26MHZ == 1 */ - - temp |= com_config->rx_dig_ctrl_init; /* Common portion of RX_DIG_CTRL init */ - XCVR_RX_DIG->RX_DIG_CTRL = temp; - - /* DCOC_CAL_IIR */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz; - } -#else - { - XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - /* DC_RESID_CTRL */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz; - } -#else - { - XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - /* DCOC_CTRL_0 & _1 */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ -#if RADIO_IS_GEN_3P0 - XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz; -#endif /* RADIO_IS_GEN_3P0 */ - - } -#else - { - XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ -#if RADIO_IS_GEN_3P0 - XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz; -#endif /* RADIO_IS_GEN_3P0 */ - } -#endif /* RF_OSC_26MHZ == 1 */ - if (first_init) - { - /* DCOC_CAL_GAIN */ - XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init; - - /* DCOC_CAL_RCP */ - XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init; - XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0; - XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4; - XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8; - XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0; - XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8; - - /* LNA_GAIN_LIN_VAL */ - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init; - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init; - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init; - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init; - - /* BBA_RES_TUNE_LIN_VAL */ - XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init; - XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init; - XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init; - - /* BBA_STEP */ - XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init; - - /* DCOC_TZA_STEP */ - XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init; - XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init; - XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init; - XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init; - XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init; - XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init; - XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init; - XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init; - XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init; - XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init; - XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init; - -#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) - /* DCOC_CAL_FAIL and DCOC_CAL_PASS */ - XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init; - XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init; -#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ - } - - /* AGC_CTRL_0 .. _3 */ - XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init; - -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz; - } -#else - { - XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - if (first_init) - { - XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init; - - /* AGC_GAIN_TBL_** */ - XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init; - XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init; - XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init; - XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init; - XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init; - XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init; - XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init; - - /* RSSI_CTRL_0 */ - XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init; - -#if RADIO_IS_GEN_3P0 - XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init; -#endif /* RADIO_IS_GEN_3P0 */ - - /* CCA_ED_LQI_0 and _1 */ - XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init; - XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init; - } - - /* Channel filter coefficients */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0; - XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1; - XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2; - XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3; - XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4; - XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5; - XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6; - XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7; - XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8; - XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9; - XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10; - XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11; - } -#else - { - XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0; - XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1; - XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2; - XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3; - XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4; - XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5; - XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6; - XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7; - XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8; - XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9; - XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10; - XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11; - } -#endif /* RF_OSC_26MHZ == 1 */ - - XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0; - XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1; - - /*******************************************************************************/ - /* XCVR_TSM configs */ - /*******************************************************************************/ - XCVR_TSM->CTRL = com_config->tsm_ctrl; - -#if RADIO_IS_GEN_2P0 - if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE)) - { - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK; - } -#endif /* RADIO_IS_GEN_2P0 */ - - if (first_init) - { -#if !RADIO_IS_GEN_2P1 - XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */ -#endif /* !RADIO_IS_GEN_2P1 */ - - XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init; - /* TSM registers and timings - dependent upon clock frequency */ -#if RF_OSC_26MHZ == 1 - { - XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz; - XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz; - XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz; - XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz; - XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz; - XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz; - XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz; - XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz; - XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz; - XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz; - XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz; - XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz; - XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz; - XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz; - XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz; - XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz; - XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz; - XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz; - XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz; - XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz; - XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz; - XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz; - } -#else - { - XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz; - XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz; - XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz; - XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz; - XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz; - XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz; - XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz; - XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz; - XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz; - XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz; - XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz; - XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz; - XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz; - XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz; - XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz; - XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz; - XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz; - XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz; - XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz; - XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz; - XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz; - XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - /* TSM timings independent of clock frequency */ - XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init; - XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init; - XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init; - XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init; - XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init; - XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init; - XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init; - XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init; - XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init; - XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init; - XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init; - XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init; - XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init; - XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init; - XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init; - XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init; - XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init; - XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init; - XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init; - XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; - XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init; - XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init; - XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init; - XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init; - XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init; - XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init; - XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init; - XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init; - XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init; - XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init; - XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init; - -#if RF_OSC_26MHZ == 1 - { - XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | - XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ); - } -#else - { - XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | - XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD); - } -#endif /* RF_OSC_26MHZ == 1 */ - - XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init; - XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init; - -#if RADIO_IS_GEN_3P0 - XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init; - XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init; - - /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */ -#if (PA_RAMP_TIME == 4) - XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */ - XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */ - XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */ - XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */ - XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */ - XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */ - XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */ - XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */ - XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */ - XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */ - XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */ - XCVR_TSM->TIMING20 += B1(2); /* (sy_pd_en) */ - XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */ - XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */ - XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ - XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */ - XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */ - XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */ - XCVR_TSM->TIMING58 += B1(2) /* (tx_hpm_dac_en) */ - temp = XCVR_TSM->TIMING14; - temp &= 0xFFFF0000; - temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */ - XCVR_TSM->TIMING14 = temp; -#endif /* (PA_RAMP_TIME == 4) */ -#endif /* RADIO_IS_GEN_3P0 */ - } - -#if RADIO_IS_GEN_3P0 - if (mode_config->radio_mode == ZIGBEE_MODE) - { - temp = XCVR_TSM->TIMING35; - temp &= ~(B0(0xFF)); - if (DATA_PADDING_EN == 1) - { - temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */ - } - else - { - temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */ - } - XCVR_TSM->TIMING35 = temp; - } -#else - - if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS))) - { - /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */ - XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */ - } - else - { - XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */ - } -#endif /* RADIO_IS_GEN_3P0 */ - - /*******************************************************************************/ - /* XCVR_TX_DIG configs */ - /*******************************************************************************/ -#if RF_OSC_26MHZ == 1 - { - XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ - XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz; - XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz; - } -#else - { - XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ - XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz; - XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - if (first_init) - { - XCVR_TX_DIG->CTRL = com_config->tx_ctrl; - XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding; - XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern; - -#if !RADIO_IS_GEN_2P1 - XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1; - XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2; -#endif /* !RADIO_IS_GEN_2P1 */ - } - - XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl; - -#ifndef SIMULATION -#if (TRIM_BBA_DCOC_DAC_AT_INIT) - /* PortC 17 for function observability */ - PORTC->PCR[17] &= ~PORT_PCR_MUX_MASK; - PORTC->PCR[17] |= PORT_PCR_MUX(1); /* PTC17 to alt 1 - GPIO */ - GPIOC->PDDR |= (1<<17); /* Set PC17 GPIO to output direction */ - GPIOC->PCOR = (1<<17); /* Set PC17 GPIO to LOW */ - if (first_init) - { - uint32_t end_of_rx_wu = 0; - XCVR_ForceRxWu(); - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - GPIOC->PSOR = (1 << 17); /* Set PC17 GPIO to HIGH */ -// if (!rx_bba_dcoc_dac_trim_shortIQ()) - if (!rx_bba_dcoc_dac_trim_DCest()) - { - config_status = gXcvrTrimFailure_c; - } - GPIOC->PCOR = (1 << 17); /* Set PC17 GPIO to LOW */ - XCVR_ForceRxWd(); - GPIOC->PSOR = (1 << 17); /* Set PC17 GPIO to HIGH */ - DCOC_DAC_INIT_Cal(1); - GPIOC->PCOR = (1 << 17); /* Set PC17 GPIO to LOW */ - } -#endif /* TRIM_BBA_DCOC_DAC_AT_INIT */ -#endif /* ifndef SIMULATION */ - return config_status; -} - -void XCVR_Reset(void) -{ -#if RADIO_IS_GEN_3P0 -#else - RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */ - RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */ - RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */ -#endif /* RADIO_IS_GEN_3P0 */ -} - -xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */ -{ - xcvrStatus_t status; - const xcvr_mode_datarate_config_t * mode_datarate_config; - const xcvr_datarate_config_t * datarate_config ; - const xcvr_mode_config_t * radio_mode_cfg; - const xcvr_common_config_t * radio_common_config; - - status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config ); - - if (status == gXcvrSuccess_c) - { - status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, - (const xcvr_mode_config_t *)radio_mode_cfg, - (const xcvr_mode_datarate_config_t *)mode_datarate_config, - (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE); - current_xcvr_config.radio_mode = new_radio_mode; - current_xcvr_config.data_rate = new_data_rate; - } - - return status; -} - -void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable ) -{ - if (IIRnbEnable) - { - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; - } - else - { - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; - } -} - -xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) -{ - double integer_used_in_Hz, - integer_used_in_LSB, - numerator_fraction, - numerator_in_Hz, - numerator_in_LSB, - numerator_unrounded, - real_int_and_fraction, - real_fraction, - requested_freq_in_LSB, - sdm_lsb; - uint32_t temp; - static uint32_t integer_truncated, - integer_to_use; - static int32_t numerator_rounded; - - /* Configure for Coarse Tune */ - uint32_t coarse_tune_target = freq / 1000000; - - temp = XCVR_PLL_DIG->CTUNE_CTRL; - temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK; - temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target); - XCVR_PLL_DIG->CTUNE_CTRL = temp; - - /* Calculate the Low Port values */ - sdm_lsb = refOsc / 131072.0; - - real_int_and_fraction = freq / (refOsc * 2.0); - - integer_truncated = (uint32_t) trunc(real_int_and_fraction); - - real_fraction = real_int_and_fraction - integer_truncated; - - if (real_fraction > 0.5) - { - integer_to_use = integer_truncated + 1; - } - else - { - integer_to_use = integer_truncated; - } - - numerator_fraction = real_int_and_fraction - integer_to_use; - - integer_used_in_Hz = integer_to_use * refOsc * 2; - integer_used_in_LSB = integer_used_in_Hz / sdm_lsb; - - numerator_in_Hz = numerator_fraction * refOsc * 2; - numerator_in_LSB = numerator_in_Hz / sdm_lsb; - - requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB; - - numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256; - - numerator_rounded = (int32_t)round(numerator_unrounded); - - /* Write the Low Port Integer and Numerator */ - temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; - temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; - temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | - XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK); - XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; - - XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded; - - return gXcvrSuccess_c; -} - -void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */ -{ - s_PanicFunctionPtr = fptr; -} - -void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address) -{ - if ( s_PanicFunctionPtr != NULL) - { - s_PanicFunctionPtr(panic_id, panic_address, 0, 0); - } - else - { - uint8_t dummy; - - while(1) - { - dummy = dummy; - } - } -} - -healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */ -{ - return (healthStatus_t)NO_ERRORS; -} - -void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control) -{ - -} - -/* Helper function to map radio mode to LL usage */ -link_layer_t map_mode_to_ll(radio_mode_t mode) -{ - link_layer_t llret; - switch (mode) - { - case BLE_MODE: - llret = BLE_LL; - break; - case ZIGBEE_MODE: - llret = ZIGBEE_LL; - break; - case ANT_MODE: - llret = ANT_LL; - break; - case GFSK_BT_0p5_h_0p5: - case GFSK_BT_0p5_h_0p32: - case GFSK_BT_0p5_h_0p7: - case GFSK_BT_0p5_h_1p0: - case GFSK_BT_0p3_h_0p5: - case GFSK_BT_0p7_h_0p5: - case MSK: - llret = GENFSK_LL; - break; - default: - llret = UNASSIGNED_LL; - break; - } - return llret; -} - -#if RADIO_IS_GEN_3P0 -void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address) -{ - XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address; -} - -uint32_t XCVR_GetBSM_NTW_Address(void) -{ - return XCVR_PHY->NTW_ADR_BSM; -} -#endif /* RADIO_IS_GEN_3P0 */ - -/* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */ -xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping) -{ - link_layer_t int0 = map_mode_to_ll(irq0_mapping); - link_layer_t int1 = map_mode_to_ll(irq1_mapping); - xcvrStatus_t statusret; - /* Make sure the two LL's requested aren't the same */ - if (int0 == int1) - { - statusret = gXcvrInvalidParameters_c; - } - else - { - uint32_t temp; - temp = XCVR_MISC->XCVR_CTRL; - temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK); - temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1)); - XCVR_MISC->XCVR_CTRL = temp; - statusret = gXcvrSuccess_c; - } - return statusret; -} - -/* Get current state of IRQ mapping for either radio INT0 or INT1 */ -link_layer_t XCVR_GetIRQMapping(uint8_t int_num) -{ - if (int_num == 0) - { - return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT); - } - else - { - return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT); - } -} - -/* Get current state of radio mode and data rate */ -xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config) -{ - xcvrStatus_t status = gXcvrInvalidParameters_c; - if (curr_config != NULL) - { - curr_config->radio_mode = current_xcvr_config.radio_mode; - curr_config->data_rate = current_xcvr_config.data_rate; - status = gXcvrSuccess_c; - } - return status; -} - -/* Customer level trim functions */ -xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim) -{ - xcvrStatus_t status = gXcvrInvalidParameters_c; - - if ((xtalTrim & 0x80) == 0) - { - uint32_t temp; - temp = RSIM->ANA_TRIM; - temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK; - RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim); - status = gXcvrSuccess_c; - } - return status; -} - -uint8_t XCVR_GetXtalTrim(void) -{ - uint8_t temp_xtal; - temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT); - return temp_xtal; -} - -/* RSSI adjustment */ -xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj) -{ - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK; - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj); - return gXcvrSuccess_c; -} - -int8_t XCVR_GetRssiAdjustment(void) -{ - int8_t adj; - adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT; - return adj; -} - -/* Radio debug functions */ -xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) -{ - uint32_t temp; - - if (channel == 0xFF) - { - /* Clear all of the overrides and restore to LL channel control */ - temp = XCVR_PLL_DIG->CHAN_MAP; - temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK -#if !RADIO_IS_GEN_2P1 - | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK -#endif /* !RADIO_IS_GEN_2P1 */ -#if RADIO_IS_GEN_3P0 - | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK -#endif /* RADIO_IS_GEN_3P0 */ - ); - - XCVR_PLL_DIG->CHAN_MAP = temp; - - /* Stop using the manual frequency setting */ - XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; - - return gXcvrSuccess_c; - } - - if (channel >= 128) - { - return gXcvrInvalidParameters_c; - } - - if (useMappedChannel) - { - temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */ - - switch (temp) - { -#if !RADIO_IS_GEN_2P1 - case 0x3: /* ANT protocol */ - ANT->CHANNEL_NUM = channel; - break; -#endif /* !RADIO_IS_GEN_2P1 */ - case 0x8: /* GENFSK protocol */ - case 0x9: /* MSK protocol */ - GENFSK->CHANNEL_NUM = channel; - break; - default: /* All other protocols */ - temp = XCVR_PLL_DIG->CHAN_MAP; - temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK -#if RADIO_IS_GEN_3P0 - | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK -#endif /* RADIO_IS_GEN_3P0 */ - ); - temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK -#if !RADIO_IS_GEN_2P1 - | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK -#endif /* !RADIO_IS_GEN_2P1 */ - ); - XCVR_PLL_DIG->CHAN_MAP = temp; - break; - } - } - else - { - XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK -#if !RADIO_IS_GEN_2P1 - | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK -#endif /* !RADIO_IS_GEN_2P1 */ - ); - - XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c); - XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator); - - temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; - temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; - temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer); - XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; - - /* Stop using the LL channel map and use the manual frequency setting */ - XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; - } - - return gXcvrSuccess_c; -} - -uint32_t XCVR_GetFreq ( void ) -{ - uint32_t pll_int; - uint32_t pll_num_unsigned; - int32_t pll_num; - uint32_t pll_denom; - float freq_float; - - if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */ - { - pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >> - XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT; - - pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2; - pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3; - } - else - { - /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */ - pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >> - XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT; - - pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1; - pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2; - } - - uint32_t freq = 0; - -#if RF_OSC_26MHZ == 1 - uint32_t ref_clk = 26U; -#else - uint32_t ref_clk = 32U; -#endif /* RF_OSC_26MHZ == 1 */ - - /* Check if sign bit is asserted */ - if (pll_num_unsigned & 0x04000000U) - { - /* Sign extend the numerator */ - pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; - - /* Calculate the frequency in MHz */ - freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); - } - else - { - /* Calculate the frequency in MHz */ - pll_num = pll_num_unsigned; - freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); - } - - freq = (uint32_t)freq_float; - - return freq; -} - -void XCVR_ForceRxWu(void) -{ - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK; -} - -void XCVR_ForceRxWd(void) -{ - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK; -} - -void XCVR_ForceTxWu(void) -{ - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -void XCVR_ForceTxWd(void) -{ - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol) -{ - uint32_t temp; - if ((protocol != 6) && (protocol != 7)) - { - return gXcvrInvalidParameters_c; /* Failure */ - } - - if ((rf_channel_freq < 2360) || (rf_channel_freq >2487)) - { - return gXcvrInvalidParameters_c; /* failure */ - } - - /* Set the DFT Mode */ - temp = XCVR_TX_DIG->CTRL; - temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK; - temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1); - XCVR_TX_DIG->CTRL = temp; - - /* Choose Protocol 6 or 7 if using the Channel Number register */ - temp = XCVR_MISC->XCVR_CTRL; - temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK; - temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol); - XCVR_MISC->XCVR_CTRL = temp; - - /* Select the RF Channel, using the Channel Number register */ - XCVR_OverrideChannel(rf_channel_freq-2360,1); - - /* Warm-up the Radio */ - XCVR_ForceTxWu(); - - return gXcvrSuccess_c; /* Success */ -} - -xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern) -{ - uint32_t temp; - uint8_t dft_mode = 0; - uint8_t dft_clk_sel = 0; - xcvrStatus_t status = gXcvrSuccess_c; - - XCVR_ChangeMode(radio_mode, data_rate); - - /* Select the RF Channel, using the Channel Number register */ - XCVR_OverrideChannel(channel_num, 1); - - switch (radio_mode) - { - case ZIGBEE_MODE: - dft_mode = 6; /* OQPSK configuration */ - break; - case ANT_MODE: - case BLE_MODE: - case GFSK_BT_0p5_h_0p5: - case GFSK_BT_0p5_h_0p32: - case GFSK_BT_0p5_h_0p7: - case GFSK_BT_0p5_h_1p0: - case GFSK_BT_0p3_h_0p5: - case GFSK_BT_0p7_h_0p5: - dft_mode = 2; /* GFSK configuration */ - break; - case MSK: - dft_mode = 4; /* MSK configuration */ - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - - if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ - { - switch (data_rate) - { - case DR_1MBPS: - dft_clk_sel = 4; - break; - case DR_500KBPS: - dft_clk_sel = 3; - break; - case DR_250KBPS: - dft_clk_sel = 2; - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - } - - temp = XCVR_TX_DIG->CTRL; - temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK); - temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | - XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | - XCVR_TX_DIG_CTRL_TX_DFT_EN(1) | - XCVR_TX_DIG_CTRL_LFSR_EN(0); - XCVR_TX_DIG->CTRL = temp; - - XCVR_TX_DIG->DFT_PATTERN = tx_pattern; - - if (status == gXcvrSuccess_c) - { - /* Warm-up the Radio */ - XCVR_ForceTxWu(); - } - - return status; -} - -xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length) -{ - uint32_t temp; - uint8_t dft_mode = 0; - uint8_t dft_clk_sel = 0; - xcvrStatus_t status = gXcvrSuccess_c; - uint8_t bitrate_setting = 0xFF; - - if (lfsr_length > 5) - { - return gXcvrInvalidParameters_c; - } - - XCVR_ChangeMode(radio_mode, data_rate); - - /* Select the RF Channel, using the Channel Number register */ - XCVR_OverrideChannel(channel_num, 1); - - switch (radio_mode) - { - case ZIGBEE_MODE: - dft_mode = 7; /* OQPSK configuration */ - break; - case ANT_MODE: - case BLE_MODE: - case GFSK_BT_0p5_h_0p5: - case GFSK_BT_0p5_h_0p32: - case GFSK_BT_0p5_h_0p7: - case GFSK_BT_0p5_h_1p0: - case GFSK_BT_0p3_h_0p5: - case GFSK_BT_0p7_h_0p5: - dft_mode = 3; /* GFSK configuration */ - bitrate_setting = data_rate; - break; - case MSK: - dft_mode = 5; /* MSK configuration */ - break; - - default: - status = gXcvrInvalidParameters_c; - break; - } - - if (status == gXcvrSuccess_c) - { - switch (data_rate) - { - case DR_1MBPS: - dft_clk_sel = 4; - break; - case DR_500KBPS: - dft_clk_sel = 3; - break; - case DR_250KBPS: - dft_clk_sel = 2; - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - } - - if (bitrate_setting < 4) - { - GENFSK->BITRATE = bitrate_setting; - } - - temp = XCVR_TX_DIG->CTRL; - temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | - XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK | - XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | - XCVR_TX_DIG_CTRL_LFSR_EN_MASK); - temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | - XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | - XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | - XCVR_TX_DIG_CTRL_TX_DFT_EN(0) | - XCVR_TX_DIG_CTRL_LFSR_EN(1); - XCVR_TX_DIG->CTRL = temp; - - if (status == gXcvrSuccess_c) - { - /* Warm-up the Radio */ - XCVR_ForceTxWu(); - } - - return status; -} - -void XCVR_DftTxOff(void) -{ - XCVR_ForceTxWd(); - XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */ - /* Clear the RF Channel over-ride */ - XCVR_OverrideChannel(0xFF,1); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */ - XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */ - XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */ - XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */ -} - -xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power) -{ - if (pa_power > 0x3F) - { - return gXcvrInvalidParameters_c; /* Failure */ - } - - if (pa_power != 1) - { - pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */ - } - - XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */ - XCVR_TSM->PA_POWER = pa_power; - - return gXcvrSuccess_c; /* Success */ -} - -xcvrStatus_t XCVR_CoexistenceInit(void) -{ -#if gMWS_UseCoexistence_d - uint32_t temp = 0x00U; - uint32_t end_of_tx_wu = 0x00U; - uint32_t end_of_rx_wu = 0x00U; - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - uint32_t tsm_timing47 = 0x00U; -#else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */ - uint32_t tsm_timing48 = 0x00U; -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - uint32_t tsm_timing50 = 0x00U; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en) - uint32_t tsm_timing48 = 0x00U; - // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en) - uint32_t tsm_timing47 = 0x00U; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - - uint16_t tsm_timing43_rx = 0x00; - uint16_t tsm_timing43_tx = 0x00; - - /* Select GPIO mode for FAD pins */ - temp = XCVR_MISC->FAD_CTRL; - temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK); - XCVR_MISC->FAD_CTRL = temp; - - /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ - end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; - end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - -/***************** - * TX SEQUENCE * - *****************/ - - if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_tx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - - /* Save the TX RF_ACTIVE start time. */ - tsm_timing43_tx = end_of_tx_wu - temp; - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#else - tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - -/***************** - * RX SEQUENCE * - *****************/ - - if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_rx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - - /* Save the RX RF_ACTIVE start time. */ - tsm_timing43_rx = end_of_rx_wu - temp; - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); -#else - tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ - tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); - -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - temp = XCVR_TSM->TIMING47; - temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing47; - XCVR_TSM->TIMING47 = temp; -#else - temp = XCVR_TSM->TIMING48; - temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing48; - XCVR_TSM->TIMING48 = temp; -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - - temp = XCVR_TSM->TIMING50; - temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); - temp |= tsm_timing50; - XCVR_TSM->TIMING50 = temp; - -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - GPIOC->PDDR |= 0x18; - PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); - PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); -#else - GPIOC->PDDR |= 0x0A; - PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); - PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ - tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); - - /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ - tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); - - /* RF_ACTIVE */ - temp = XCVR_TSM->TIMING48; - temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing48; - XCVR_TSM->TIMING48 = temp; - - /* RF_PRIORITY */ - temp = XCVR_TSM->TIMING47; - temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing47; - XCVR_TSM->TIMING47 = temp; - - /* Overwrite pins settings */ - GPIOC->PDDR |= 0x12; - PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); - PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - - tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d; - - if (tsm_timing43_tx > end_of_tx_wu - 1) - { - tsm_timing43_tx = end_of_tx_wu - 1; - } - - tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d; - - if (tsm_timing43_rx > end_of_rx_wu - 1) - { - tsm_timing43_rx = end_of_rx_wu - 1; - } - - XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) | - (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | - (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) | - (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)); - - BTLE_RF->MISC_CTRL = 0x02; - - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK; - - /* Save the updated registers values. */ - XCVR_CoexistenceSaveRestoreTimings(1); -#endif /* gMWS_UseCoexistence_d */ - - return gXcvrSuccess_c; -} - -xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority) -{ -#if gMWS_UseCoexistence_d - uint32_t temp = 0x00U; - uint32_t end_of_tx_wu = 0x00U; - uint32_t end_of_rx_wu = 0x00U; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - uint32_t tsm_timing50 = 0x00U; -#endif -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - uint32_t tsm_timing47 = 0x00U; -#endif - - /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ - end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; - end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - -/***************** - * RX * - *****************/ - - if (XCVR_COEX_HIGH_PRIO == rxPriority) - { - if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_rx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */ - tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */ - tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - else - { - /* Low priority RX */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - -/***************** - * TX * - *****************/ - if (XCVR_COEX_HIGH_PRIO == txPriority) - { - if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_tx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - else - { -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ - tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ - tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - temp = XCVR_TSM->TIMING50; - temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); - temp |= tsm_timing50; - XCVR_TSM->TIMING50 = temp; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - temp = XCVR_TSM->TIMING47; - temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK | - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK | - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK); - temp |= tsm_timing47; - XCVR_TSM->TIMING47 = temp; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - - /* Save the updated registers values. */ - XCVR_CoexistenceSaveRestoreTimings(1); -#endif /* gMWS_UseCoexistence_d */ - - return gXcvrSuccess_c; -} - -xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) -{ -#if gMWS_UseCoexistence_d - static uint32_t tsm_ovrd0_saved = 0x00; - static uint32_t tsm_ovrd1_saved = 0x00; - static uint32_t tsm_ovrd2_saved = 0x00; - static uint32_t tsm_ovrd3_saved = 0x00; - static uint32_t tsm_timing47_saved = 0x00; - static uint32_t tsm_timing48_saved = 0x00; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - static uint32_t tsm_timing49_saved = 0x00; - static uint32_t tsm_timing50_saved = 0x00; -#endif - - if (saveTimings == 0) - { - /* Restore registers values. */ - XCVR_TSM->OVRD0 = tsm_ovrd0_saved; - XCVR_TSM->OVRD1 = tsm_ovrd1_saved; - XCVR_TSM->OVRD2 = tsm_ovrd2_saved; - XCVR_TSM->OVRD3 = tsm_ovrd3_saved; - - XCVR_TSM->TIMING47 = tsm_timing47_saved; - XCVR_TSM->TIMING48 = tsm_timing48_saved; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - XCVR_TSM->TIMING49 = tsm_timing49_saved; - XCVR_TSM->TIMING50 = tsm_timing50_saved; -#endif - } - else - { - /* Save registers values. */ - tsm_ovrd0_saved = XCVR_TSM->OVRD0; - tsm_ovrd1_saved = XCVR_TSM->OVRD1; - tsm_ovrd2_saved = XCVR_TSM->OVRD2; - tsm_ovrd3_saved = XCVR_TSM->OVRD3; - tsm_timing47_saved = XCVR_TSM->TIMING47; - tsm_timing48_saved = XCVR_TSM->TIMING48; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing49_saved = XCVR_TSM->TIMING49; - tsm_timing50_saved = XCVR_TSM->TIMING50; -#endif - } -#endif /* gMWS_UseCoexistence_d */ - - return gXcvrSuccess_c; -} - diff --git a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.h b/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.h deleted file mode 100644 index 9403f81df..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr.h +++ /dev/null @@ -1,1236 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_XCVR_H_ -/* clang-format off */ -#define _FSL_XCVR_H_ -/* clang-format on */ - -#include "fsl_device_registers.h" -#include "fsl_xcvr_trim.h" - -#if gMWS_UseCoexistence_d -#include "MWS.h" -#endif /* gMWS_UseCoexistence_d */ -/*! - * @addtogroup xcvr - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* KW4xZ/KW3xZ/KW2xZ Radio type */ -#define RADIO_IS_GEN_2P0 (1) - -/* Default RF OSC definition. Allows for compile time clock frequency definition */ -#ifdef CLOCK_MAIN - -#else -#if RF_OSC_26MHZ == 1 -#define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */ -#else -#define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */ -#endif /* RF_OSC_26MHZ == 1 */ -#endif /* CLOCK_MAIN */ - -#define TBD_ZERO (0) -#define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0)) - -#define B0(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU) -#define B1(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U) -#define B2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U) -#define B3(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U) - -#define USE_DEFAULT_PRE_REF (0) -#define TRIM_BBA_DCOC_DAC_AT_INIT (1) -#define PRESLOW_ENA (1) - -/* GEN3 TSM defines */ -#if RADIO_IS_GEN_3P0 - -/* TSM timings initializations for Gen3 radio */ -/* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */ -/* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */ -/* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */ -#if RF_OSC_26MHZ == 1 -#define TSM_TIMING00init (0x6d006f00U) /* (bb_ldo_hf_en) */ -#define TSM_TIMING01init (0x6d006f00U) /* (bb_ldo_adcdac_en) */ -#define TSM_TIMING02init (0x6d00ffffU) /* (bb_ldo_bba_en) */ -#define TSM_TIMING03init (0x6d006f00U) /* (bb_ldo_pd_en) */ -#define TSM_TIMING04init (0x6d006f00U) /* (bb_ldo_fdbk_en) */ -#define TSM_TIMING05init (0x6d006f00U) /* (bb_ldo_vcolo_en) */ -#define TSM_TIMING06init (0x6d006f00U) /* (bb_ldo_vtref_en) */ -#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ -#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ -#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ -#define TSM_TIMING10init (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */ -#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ -#define TSM_TIMING12init (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ -#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ -#define TSM_TIMING14init (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */ -#define TSM_TIMING15init (0x6d036f03U) /* (sy_vco_en) */ -#define TSM_TIMING16init (0x6d20ffffU) /* (sy_lo_rx_buf_en) */ -#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ -#define TSM_TIMING18init (0x6d056f05U) /* (sy_divn_en) */ -#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ -#define TSM_TIMING20init (0x6d036f03U) /* (sy_pd_en) */ -#define TSM_TIMING21init (0x6d046f04U) /* (sy_lo_divn_en) */ -#define TSM_TIMING22init (0x6d04ffffU) /* (sy_lo_rx_en) */ -#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ -#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ -#define TSM_TIMING25init (0x6d21ffffU) /* (rx_lna_mixer_en) */ -#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ -#define TSM_TIMING27init (0x6d24ffffU) /* (rx_adc_i_q_en) */ -#define TSM_TIMING28init (0x2524ffffU) /* (rx_adc_reset_en) */ -#define TSM_TIMING29init (0x6d22ffffU) /* (rx_bba_i_q_en) */ -#define TSM_TIMING30init (0x6d24ffffU) /* (rx_bba_pdet_en) */ -#define TSM_TIMING31init (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */ -#define TSM_TIMING32init (0x6d21ffffU) /* (rx_tza_i_q_en) */ -#define TSM_TIMING33init (0x6d24ffffU) /* (rx_tza_pdet_en) */ -#define TSM_TIMING34init (0x6d076f07U) /* (pll_dig_en) */ -#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ -#define TSM_TIMING36init (0x6d6affffU) /* (rx_dig_en) */ -#define TSM_TIMING37init (0x6b6affffU) /* (rx_init) */ -#define TSM_TIMING38init (0x6d0e6f42U) /* (sigma_delta_en) */ -#define TSM_TIMING39init (0x6d6affffU) /* (rx_phy_en) */ -#define TSM_TIMING40init (0x6d2affffU) /* (dcoc_en) */ -#define TSM_TIMING41init (0x2b2affffU) /* (dcoc_init) */ -#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ -#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ -#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ -#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ -#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ -#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ -#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ -#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ -#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ -#define TSM_TIMING51init (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */ -#define TSM_TIMING52init (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */ -#define TSM_TIMING53init (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */ -#define TSM_TIMING54init (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ -#define TSM_TIMING55init (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */ -#define TSM_TIMING56init (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */ -#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ -#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ -#define END_OF_SEQinit (0x6d6c6f67U) /* */ -#define TX_RX_ON_DELinit (0x00008a86U) /* */ -#define TX_RX_SYNTH_init (0x00002318U) /* */ -#else -#define TSM_TIMING00init (0x69006f00U) /* (bb_ldo_hf_en) */ -#define TSM_TIMING01init (0x69006f00U) /* (bb_ldo_adcdac_en) */ -#define TSM_TIMING02init (0x6900ffffU) /* (bb_ldo_bba_en) */ -#define TSM_TIMING03init (0x69006f00U) /* (bb_ldo_pd_en) */ -#define TSM_TIMING04init (0x69006f00U) /* (bb_ldo_fdbk_en) */ -#define TSM_TIMING05init (0x69006f00U) /* (bb_ldo_vcolo_en) */ -#define TSM_TIMING06init (0x69006f00U) /* (bb_ldo_vtref_en) */ -#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ -#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ -#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ -#define TSM_TIMING10init (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */ -#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ -#define TSM_TIMING12init (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ -#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ -#define TSM_TIMING14init (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */ -#define TSM_TIMING15init (0x69036f03U) /* (sy_vco_en) */ -#define TSM_TIMING16init (0x691cffffU) /* (sy_lo_rx_buf_en) */ -#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ -#define TSM_TIMING18init (0x69056f05U) /* (sy_divn_en) */ -#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ -#define TSM_TIMING20init (0x69036f03U) /* (sy_pd_en) */ -#define TSM_TIMING21init (0x69046f04U) /* (sy_lo_divn_en) */ -#define TSM_TIMING22init (0x6904ffffU) /* (sy_lo_rx_en) */ -#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ -#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ -#define TSM_TIMING25init (0x691dffffU) /* (rx_lna_mixer_en) */ -#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ -#define TSM_TIMING27init (0x6920ffffU) /* (rx_adc_i_q_en) */ -#define TSM_TIMING28init (0x2120ffffU) /* (rx_adc_reset_en) */ -#define TSM_TIMING29init (0x691effffU) /* (rx_bba_i_q_en) */ -#define TSM_TIMING30init (0x6920ffffU) /* (rx_bba_pdet_en) */ -#define TSM_TIMING31init (0x691fffffU) /* (rx_bba_tza_dcoc_en) */ -#define TSM_TIMING32init (0x691dffffU) /* (rx_tza_i_q_en) */ -#define TSM_TIMING33init (0x6920ffffU) /* (rx_tza_pdet_en) */ -#define TSM_TIMING34init (0x69076f07U) /* (pll_dig_en) */ -#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ -#define TSM_TIMING36init (0x6966ffffU) /* (rx_dig_en) */ -#define TSM_TIMING37init (0x6766ffffU) /* (rx_init) */ -#define TSM_TIMING38init (0x690e6f42U) /* (sigma_delta_en) */ -#define TSM_TIMING39init (0x6966ffffU) /* (rx_phy_en) */ -#define TSM_TIMING40init (0x6926ffffU) /* (dcoc_en) */ -#define TSM_TIMING41init (0x2726ffffU) /* (dcoc_init) */ -#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ -#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ -#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ -#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ -#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ -#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ -#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ -#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ -#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ -#define TSM_TIMING51init (0x6903ffffU) /* (rxtx_auxpll_bias_en) */ -#define TSM_TIMING52init (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */ -#define TSM_TIMING53init (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */ -#define TSM_TIMING54init (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ -#define TSM_TIMING55init (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */ -#define TSM_TIMING56init (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */ -#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ -#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ -#define END_OF_SEQinit (0x69686f67U) /* */ -#define TX_RX_ON_DELinit (0x00008a86U) /* */ -#define TX_RX_SYNTH_init (0x00002318U) /* */ -#endif /* RF_OSC_26MHZ == 1 */ - -#define AUX_PLL_DELAY (0) -/* TSM bitfield shift and value definitions */ -#define TX_DIG_EN_ASSERT (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */ -#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ -/* EDIT THIS LINE TO CONTROL PA_RAMP! */ -#define PA_RAMP_TIME (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */ -#define PA_RAMP_SEL_0US (0) -#define PA_RAMP_SEL_1US (1) -#define PA_RAMP_SEL_2US (2) -#define PA_RAMP_SEL_4US (3) -#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4)) -#error "Invalid value for PA_RAMP_TIME macro" -#endif /* Error check of PA RAMP TIME */ - -#define ADD_FOR_26MHZ (4) -#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ -#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ -/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ -/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ -#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) - #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) - #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) - #if (PA_RAMP_TIME == 0) - #define PA_RAMP_SEL PA_RAMP_SEL_0US - #define DATA_PADDING_EN (0) - #else - #define DATA_PADDING_EN (1) - #if (PA_RAMP_TIME == 1) - #define PA_RAMP_SEL PA_RAMP_SEL_1US - #else - #define PA_RAMP_SEL PA_RAMP_SEL_2US - #endif /* (PA_RAMP_TIME == 1) */ - #endif /* (PA_RAMP_TIME == 0) */ -#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) */ - #if (PA_RAMP_TIME == 4) - #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) - #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) - #define PA_RAMP_SEL PA_RAMP_SEL_4US - #define DATA_PADDING_EN (1) - #else /* (PA_RAMP_TIME == 4) */ - #error "Invalid value for PA_RAMP_TIME macro" - #endif /* (PA_RAMP_TIME == 4) */ -#endif/* (PA_RAMP_TIME == 4) */ - -#define END_OF_RX_WU (104 + AUX_PLL_DELAY) - -#if RF_OSC_26MHZ == 1 -#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ -#else -#define END_OF_RX_WD (END_OF_RX_WU + 1) -#endif /* RF_OSC_26MHZ == 1 */ - -#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) -#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) - -/* PA Bias Table - Gen3 version */ -#define PA_RAMP_0 0x1 -#define PA_RAMP_1 0x2 -#define PA_RAMP_2 0x4 -#define PA_RAMP_3 0x6 -#define PA_RAMP_4 0x8 -#define PA_RAMP_5 0xc -#define PA_RAMP_6 0x10 -#define PA_RAMP_7 0x14 -#define PA_RAMP_8 0x18 -#define PA_RAMP_9 0x1c -#define PA_RAMP_10 0x22 -#define PA_RAMP_11 0x28 -#define PA_RAMP_12 0x2c -#define PA_RAMP_13 0x30 -#define PA_RAMP_14 0x36 -#define PA_RAMP_15 0x3c - -#else /* Gen2 TSM definitions */ -/* GEN2 TSM defines */ -#define AUX_PLL_DELAY (0) -/* TSM bitfield shift and value definitions */ -#define TX_DIG_EN_ASSERT (95) -#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ -/* EDIT THIS LINE TO CONTROL PA_RAMP! */ -#define PA_RAMP_TIME (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */ -#define PA_RAMP_SEL_0US (0) -#define PA_RAMP_SEL_2US (1) -#define PA_RAMP_SEL_4US (2) -#define PA_RAMP_SEL_8US (3) - -#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4) || (PA_RAMP_TIME == 8)) -#error "Invalid value for PA_RAMP_TIME macro" -#endif /* Error check of PA RAMP TIME */ -#define ADD_FOR_26MHZ (4) -#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ -#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ -/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ -/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ -#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) - #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) - #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) - #define TX_SYNTH_DELAY_ADJ (0) - #define PD_CYCLE_SLIP_TX_HI_ADJ (0) - #define PD_CYCLE_SLIP_TX_LO_ADJ (1) - #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */ - #if (PA_RAMP_TIME == 0) - #define PA_RAMP_SEL PA_RAMP_SEL_0US - #define DATA_PADDING_EN (0) - #define TX_DIG_EN_TX_HI_ADJ (-2) - #else - #define DATA_PADDING_EN (1) - #define TX_DIG_EN_TX_HI_ADJ (0) - #define PA_RAMP_SEL PA_RAMP_SEL_2US - #endif /* (PA_RAMP_TIME == 0) */ -#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ - #if (PA_RAMP_TIME == 4) - #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) - #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) - #define TX_SYNTH_DELAY_ADJ (2) - #define PD_CYCLE_SLIP_TX_HI_ADJ (2) - #define PD_CYCLE_SLIP_TX_LO_ADJ (1) - #define TX_DIG_EN_TX_HI_ADJ (0) - #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */ - #define PA_RAMP_SEL PA_RAMP_SEL_4US - #define DATA_PADDING_EN (1) - #else /* (PA_RAMP_TIME==4) */ - #if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0)) - #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 6) - #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 12) - #define TX_SYNTH_DELAY_ADJ (6) - #define PD_CYCLE_SLIP_TX_HI_ADJ (6) - #define PD_CYCLE_SLIP_TX_LO_ADJ (1) - #define TX_DIG_EN_TX_HI_ADJ (4) - #define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */ - #define PA_RAMP_SEL PA_RAMP_SEL_8US - #define DATA_PADDING_EN (1) - #else /* (PA_RAMP_TIME == 8) */ - #error "Invalid value for PA_RAMP_TIME macro" - #endif /* (PA_RAMP_TIME == 8) */ - #endif/* (PA_RAMP_TIME == 4) */ -#endif /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ - -#define TX_DIG_EN_ASSERT_MSK500 (END_OF_TX_WU - 3) - -#define END_OF_RX_WU (104 + AUX_PLL_DELAY) -#if RF_OSC_26MHZ == 1 -#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ -#else -#define END_OF_RX_WD (END_OF_RX_WU + 1) -#endif /* RF_OSC_26MHZ == 1 */ -#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) -#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) - -/* PA Bias Table */ -#define PA_RAMP_0 0x1 -#define PA_RAMP_1 0x2 -#define PA_RAMP_2 0x4 -#define PA_RAMP_3 0x8 -#define PA_RAMP_4 0xe -#define PA_RAMP_5 0x16 -#define PA_RAMP_6 0x22 -#define PA_RAMP_7 0x2e - -/* BLE LL timing definitions */ -#define TX_ON_DELAY (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */ -#define RX_ON_DELAY (29 + END_OF_RX_WU) -#define RX_ON_DELAY_26MHZ (29 + END_OF_RX_WU_26MHZ) -#define TX_RX_ON_DELAY_VAL (TX_ON_DELAY << 8 | RX_ON_DELAY) -#define TX_RX_ON_DELAY_VAL_26MHZ (TX_ON_DELAY << 8 | RX_ON_DELAY_26MHZ) -#define TX_SYNTH_DELAY (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */ -#define RX_SYNTH_DELAY (0x18) -#define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 | RX_SYNTH_DELAY) - -/* PHY reference waveform assembly */ -#define RW0PS(loc, val) (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */ -#define RW1PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */ -#define RW2PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */ -#endif /* RADIO_IS_GEN_3P0 */ - -/*! @brief Error codes for the XCVR driver. */ -typedef enum _xcvrStatus -{ - gXcvrSuccess_c = 0, - gXcvrInvalidParameters_c, - gXcvrUnsupportedOperation_c, - gXcvrTrimFailure_c -} xcvrStatus_t; - -/*! @brief Health status returned from PHY upon status check function return. */ -typedef enum _healthStatus -{ - NO_ERRORS = 0, - PLL_CTUNE_FAIL = 1, - PLL_CYCLE_SLIP_FAIL = 2, - PLL_FREQ_TARG_FAIL = 4, - PLL_TSM_ABORT_FAIL = 8, -} healthStatus_t; - -/*! @brief Health status returned from PHY upon status check function return. */ -typedef enum _ext_clock_config -{ - EXT_CLK_32_MHZ = 0, - EXT_CLK_26_MHZ = 1, -} ext_clock_config_t; - -/*! @brief Radio operating mode setting types. */ -typedef enum _radio_mode -{ - BLE_MODE = 0, - ZIGBEE_MODE = 1, - ANT_MODE = 2, - - /* BT=0.5, h=** */ - GFSK_BT_0p5_h_0p5 = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */ - GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/ - GFSK_BT_0p5_h_0p7 = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */ - GFSK_BT_0p5_h_1p0 = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */ - - /* BT=** h=0.5 */ - GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */ - GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */ - - MSK = 9, - NUM_RADIO_MODES = 10, -} radio_mode_t; - -/*! @brief Link layer types. */ -typedef enum _link_layer -{ - BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */ - ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */ - ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */ - GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */ - UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */ -} link_layer_t; - -/*! @brief Data rate selections. */ -typedef enum _data_rate -{ - DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */ - DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */ - DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */ -#if RADIO_IS_GEN_3P0 - DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */ -#endif /* RADIO_IS_GEN_3P0 */ - DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */ -} data_rate_t; - -/*! @brief Control settings for Fast Antenna Diversity */ -typedef enum _FAD_LPPS_CTRL -{ - NONE = 0, - FAD_ENABLED = 1, - LPPS_ENABLED = 2 -} FAD_LPPS_CTRL_T; - -/*! @brief XCVR XCVR Panic codes for indicating panic reason. */ -typedef enum _XCVR_PANIC_ID -{ - WRONG_RADIO_ID_DETECTED = 1, - CALIBRATION_INVALID = 2, -} XCVR_PANIC_ID_T; - -/*! @brief Initialization or mode change selection for config routine. */ -typedef enum _XCVR_INIT_MODE_CHG -{ - XCVR_MODE_CHANGE = 0, - XCVR_FIRST_INIT = 1, -} XCVR_INIT_MODE_CHG_T; - -typedef enum _XCVR_COEX_PRIORITY -{ - XCVR_COEX_LOW_PRIO = 0, - XCVR_COEX_HIGH_PRIO = 1 -} XCVR_COEX_PRIORITY_T; - -/*! @brief Current configuration of the radio. */ -typedef struct xcvr_currConfig_tag -{ - radio_mode_t radio_mode; - data_rate_t data_rate; -} xcvr_currConfig_t; - -/*! - * @brief XCVR RX_DIG channel filter coefficient storage - * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage. - */ -typedef struct _xcvr_rx_chf_coeffs -{ - uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */ - uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */ -} xcvr_rx_chf_coeffs_t; - -/*! - * @brief XCVR masked init type for 32 bit registers - * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position. - */ -typedef struct _xcvr_masked_init_32 -{ - uint32_t mask; - uint32_t init; -} xcvr_masked_init_32_t; - -/*! - * @brief XCVR common configure structure - */ -typedef struct _xcvr_common_config -{ - /* XCVR_ANA configs */ - xcvr_masked_init_32_t ana_sy_ctrl1; - - /* XCVR_PLL_DIG configs */ - uint32_t pll_hpm_bump; - uint32_t pll_mod_ctrl; - uint32_t pll_chan_map; - uint32_t pll_lock_detect; - uint32_t pll_hpm_ctrl; -#if !RADIO_IS_GEN_2P1 - uint32_t pll_hpmcal_ctrl; -#endif /* !RADIO_IS_GEN_2P1 */ - uint32_t pll_hpm_sdm_res; - uint32_t pll_lpm_ctrl; - uint32_t pll_lpm_sdm_ctrl1; - uint32_t pll_delay_match; - uint32_t pll_ctune_ctrl; - - /* XCVR_RX_DIG configs */ - uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ - uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ - uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ - uint32_t dcoc_ctrl_1_init; - uint32_t dcoc_cal_gain_init; - uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */ - uint32_t dcoc_cal_rcp_init; - uint32_t lna_gain_val_3_0; - uint32_t lna_gain_val_7_4; - uint32_t lna_gain_val_8; - uint32_t bba_res_tune_val_7_0; - uint32_t bba_res_tune_val_10_8; - uint32_t lna_gain_lin_val_2_0_init; - uint32_t lna_gain_lin_val_5_3_init; - uint32_t lna_gain_lin_val_8_6_init; - uint32_t lna_gain_lin_val_9_init; - uint32_t bba_res_tune_lin_val_3_0_init; - uint32_t bba_res_tune_lin_val_7_4_init; - uint32_t bba_res_tune_lin_val_10_8_init; - uint32_t dcoc_bba_step_init; - uint32_t dcoc_tza_step_00_init; - uint32_t dcoc_tza_step_01_init; - uint32_t dcoc_tza_step_02_init; - uint32_t dcoc_tza_step_03_init; - uint32_t dcoc_tza_step_04_init; - uint32_t dcoc_tza_step_05_init; - uint32_t dcoc_tza_step_06_init; - uint32_t dcoc_tza_step_07_init; - uint32_t dcoc_tza_step_08_init; - uint32_t dcoc_tza_step_09_init; - uint32_t dcoc_tza_step_10_init; -#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) - uint32_t dcoc_cal_fail_th_init; - uint32_t dcoc_cal_pass_th_init; -#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ - uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ - uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ - uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ - uint32_t agc_ctrl_3_init; - /* Other agc config inits moved to modeXdatarate config table */ - uint32_t agc_gain_tbl_03_00_init; - uint32_t agc_gain_tbl_07_04_init; - uint32_t agc_gain_tbl_11_08_init; - uint32_t agc_gain_tbl_15_12_init; - uint32_t agc_gain_tbl_19_16_init; - uint32_t agc_gain_tbl_23_20_init; - uint32_t agc_gain_tbl_26_24_init; - uint32_t rssi_ctrl_0_init; -#if RADIO_IS_GEN_3P0 - uint32_t rssi_ctrl_1_init; -#endif /* RADIO_IS_GEN_3P0 */ - uint32_t cca_ed_lqi_ctrl_0_init; - uint32_t cca_ed_lqi_ctrl_1_init; - - /* XCVR_TSM configs */ - uint32_t tsm_ctrl; - uint32_t tsm_ovrd2_init; - uint32_t end_of_seq_init_26mhz; - uint32_t end_of_seq_init_32mhz; -#if !RADIO_IS_GEN_2P1 - uint32_t lpps_ctrl_init; -#endif /* !RADIO_IS_GEN_2P1 */ - uint32_t tsm_fast_ctrl2_init_26mhz; - uint32_t tsm_fast_ctrl2_init_32mhz; - uint32_t recycle_count_init_26mhz; - uint32_t recycle_count_init_32mhz; - uint32_t pa_ramp_tbl_0_init; - uint32_t pa_ramp_tbl_1_init; -#if RADIO_IS_GEN_3P0 - uint32_t pa_ramp_tbl_2_init; - uint32_t pa_ramp_tbl_3_init; -#endif /* RADIO_IS_GEN_3P0 */ - uint32_t tsm_timing_00_init; - uint32_t tsm_timing_01_init; - uint32_t tsm_timing_02_init; - uint32_t tsm_timing_03_init; - uint32_t tsm_timing_04_init; - uint32_t tsm_timing_05_init; - uint32_t tsm_timing_06_init; - uint32_t tsm_timing_07_init; - uint32_t tsm_timing_08_init; - uint32_t tsm_timing_09_init; - uint32_t tsm_timing_10_init; - uint32_t tsm_timing_11_init; - uint32_t tsm_timing_12_init; - uint32_t tsm_timing_13_init; - uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ - uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ - uint32_t tsm_timing_15_init; - uint32_t tsm_timing_16_init_26mhz; - uint32_t tsm_timing_16_init_32mhz; - uint32_t tsm_timing_17_init; - uint32_t tsm_timing_18_init; - uint32_t tsm_timing_19_init; - uint32_t tsm_timing_20_init; - uint32_t tsm_timing_21_init; - uint32_t tsm_timing_22_init; - uint32_t tsm_timing_23_init; - uint32_t tsm_timing_24_init; - uint32_t tsm_timing_25_init_26mhz; - uint32_t tsm_timing_25_init_32mhz; - uint32_t tsm_timing_26_init; - uint32_t tsm_timing_27_init_26mhz; - uint32_t tsm_timing_27_init_32mhz; - uint32_t tsm_timing_28_init_26mhz; - uint32_t tsm_timing_28_init_32mhz; - uint32_t tsm_timing_29_init_26mhz; - uint32_t tsm_timing_29_init_32mhz; - uint32_t tsm_timing_30_init_26mhz; - uint32_t tsm_timing_30_init_32mhz; - uint32_t tsm_timing_31_init_26mhz; - uint32_t tsm_timing_31_init_32mhz; - uint32_t tsm_timing_32_init_26mhz; - uint32_t tsm_timing_32_init_32mhz; - uint32_t tsm_timing_33_init_26mhz; - uint32_t tsm_timing_33_init_32mhz; - uint32_t tsm_timing_34_init; - uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/ - uint32_t tsm_timing_36_init_26mhz; - uint32_t tsm_timing_36_init_32mhz; - uint32_t tsm_timing_37_init_26mhz; - uint32_t tsm_timing_37_init_32mhz; - uint32_t tsm_timing_38_init; - uint32_t tsm_timing_39_init_26mhz; - uint32_t tsm_timing_39_init_32mhz; - uint32_t tsm_timing_40_init_26mhz; - uint32_t tsm_timing_40_init_32mhz; - uint32_t tsm_timing_41_init_26mhz; - uint32_t tsm_timing_41_init_32mhz; - uint32_t tsm_timing_51_init; - uint32_t tsm_timing_52_init_26mhz; - uint32_t tsm_timing_52_init_32mhz; - uint32_t tsm_timing_53_init; - uint32_t tsm_timing_54_init_26mhz; - uint32_t tsm_timing_54_init_32mhz; - uint32_t tsm_timing_55_init_26mhz; - uint32_t tsm_timing_55_init_32mhz; - uint32_t tsm_timing_56_init_26mhz; - uint32_t tsm_timing_56_init_32mhz; - uint32_t tsm_timing_57_init; - uint32_t tsm_timing_58_init; - - /* XCVR_TX_DIG configs */ - uint32_t tx_ctrl; - uint32_t tx_data_padding; - uint32_t tx_dft_pattern; -#if !RADIO_IS_GEN_2P1 - uint32_t rf_dft_bist_1; - uint32_t rf_dft_bist_2; -#endif /* !RADIO_IS_GEN_2P1 */ -} xcvr_common_config_t; - -/*! @brief XCVR mode specific configure structure (varies by radio mode) */ -typedef struct _xcvr_mode_config -{ - radio_mode_t radio_mode; - uint32_t scgc5_clock_ena_bits; - - /* XCVR_MISC configs */ - xcvr_masked_init_32_t xcvr_ctrl; - - /* XCVR_PHY configs */ -#if RADIO_IS_GEN_3P0 - uint32_t phy_fsk_pd_cfg0; - uint32_t phy_fsk_pd_cfg1; - uint32_t phy_fsk_cfg; - uint32_t phy_fsk_misc; - uint32_t phy_fad_ctrl; -#else - uint32_t phy_pre_ref0_init; - uint32_t phy_pre_ref1_init; - uint32_t phy_pre_ref2_init; - uint32_t phy_cfg1_init; - uint32_t phy_el_cfg_init; /* Should leave EL_WIN_SIZE and EL_INTERVAL to the data_rate specific configuration */ -#endif /* RADIO_IS_GEN_3P0 */ - - /* XCVR_RX_DIG configs */ - uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ - uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ - uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ - - /* XCVR_TSM configs */ -#if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) - uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */ -#endif /* (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) */ - - /* XCVR_TX_DIG configs */ - uint32_t tx_gfsk_ctrl; - uint32_t tx_gfsk_coeff1_26mhz; - uint32_t tx_gfsk_coeff2_26mhz; - uint32_t tx_gfsk_coeff1_32mhz; - uint32_t tx_gfsk_coeff2_32mhz; -} xcvr_mode_config_t; - -/*! - * @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate) - * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay - * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. - */ -typedef struct _xcvr_mode_datarate_config -{ - radio_mode_t radio_mode; - data_rate_t data_rate; - - /* XCVR_ANA configs */ - xcvr_masked_init_32_t ana_sy_ctrl2; - xcvr_masked_init_32_t ana_rx_bba; - xcvr_masked_init_32_t ana_rx_tza; - - /* XCVR_PHY configs */ -#if RADIO_IS_GEN_3P0 - uint32_t phy_fsk_misc_mode_datarate; -#else - uint32_t phy_cfg2_init; -#endif /* RADIO_IS_GEN_3P0 */ - - uint32_t agc_ctrl_2_init_26mhz; - uint32_t agc_ctrl_2_init_32mhz; - xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */ - xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */ - uint32_t rx_rccal_ctrl_0; - uint32_t rx_rccal_ctrl_1; - - /* XCVR_TX_DIG configs */ - uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */ - uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */ -} xcvr_mode_datarate_config_t; - -/*! - * @brief XCVR datarate specific configure structure (varies by data rate) - * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay - * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. - */ -typedef struct _xcvr_datarate_config -{ - data_rate_t data_rate; - - /* XCVR_PHY configs */ - uint32_t phy_el_cfg_init; /* Note: EL_ENABLE is set in xcvr_mode_config_t settings */ - - /* XCVR_RX_DIG configs */ - uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ - uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ - uint32_t agc_ctrl_1_init_26mhz; - uint32_t agc_ctrl_1_init_32mhz; - uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ - uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ - uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ - uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ - uint32_t dcoc_ctrl_2_init_26mhz; - uint32_t dcoc_ctrl_2_init_32mhz; - uint32_t dcoc_cal_iir_init_26mhz; - uint32_t dcoc_cal_iir_init_32mhz; - uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ - uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ -} xcvr_datarate_config_t; - -/*! - * @brief LPUART callback function type - * - * The panic callback function is defined by system if system need to be informed of XCVR fatal errors. - * refer to #XCVR_RegisterPanicCb - */ -typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2); - -/* Make available const structures from config files */ -extern const xcvr_common_config_t xcvr_common_config; -extern const xcvr_mode_config_t zgbe_mode_config; -extern const xcvr_mode_config_t ble_mode_config; -extern const xcvr_mode_config_t ant_mode_config; -extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config; -extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config; -extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config; -extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config; -extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config; -extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config; -extern const xcvr_mode_config_t msk_mode_config; - -#if RADIO_IS_GEN_3P0 -extern const xcvr_datarate_config_t xcvr_2mbps_config; -#endif /* RADIO_IS_GEN_3P0 */ -extern const xcvr_datarate_config_t xcvr_1mbps_config; -extern const xcvr_datarate_config_t xcvr_500kbps_config; -extern const xcvr_datarate_config_t xcvr_250kbps_config; -extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */ - -#if RADIO_IS_GEN_3P0 -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config; -#endif /* RADIO_IS_GEN_3P0 */ -extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config; -extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config; -extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name XCVR functional Operation - * @{ - */ - -/*! - * @brief Initializes an XCVR instance. - * - * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to - * start up the XCVR in most situations. - * - * @param radio_mode The radio mode for which the XCVR should be configured. - * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions. - */ -xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate); - -/*! - * @brief Deinitializes an XCVR instance. - * - * This function gate the XCVR module clock and set all register value to reset value. - * - */ -void XCVR_Deinit(void); - -/*! - * @brief Initializes XCVR configure structure. - * - * This function updates pointers to the XCVR configure structures with default values. - * The configurations are divided into a common structure, a set of radio mode specific - * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at - * each datarate), and a set of data rate specific structures. - * The pointers provided by this routine point to const structures which can be - * copied to variable structures if changes to settings are required. - * - * @param radio_mode [in] The radio mode for which the configuration structures are requested. - * @param data_rate [in] The data rate for which the configuration structures are requested. - * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure. - * @param mode_config [in,out] Pointer to a pointer to the mode specific configuration settings structure. - * @param mode_datarate_config [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure. - * @param datarate_config [in,out] Pointer to a pointer to the data rate specific configuration settings structure. - * @return 0 success, others failure - * @see XCVR_Configure - */ -xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, - data_rate_t data_rate, - const xcvr_common_config_t ** com_config, - const xcvr_mode_config_t ** mode_config, - const xcvr_mode_datarate_config_t ** mode_datarate_config, - const xcvr_datarate_config_t ** datarate_config); - -/*! - * @brief Initializes an XCVR instance. - * - * This function initializes the XCVR module with user-defined settings. - * - * @param com_config Pointer to the common configuration settings structure. - * @param mode_config Pointer to the mode specific configuration settings structure. - * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure. - * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure. - * @param tempDegC temperature of the die in degrees C. - * @param ext_clk indicates the external clock setting, 32MHz or 26MHz. - * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0) - * @return 0 succeed, others failed - */ -xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, - const xcvr_mode_config_t *mode_config, - const xcvr_mode_datarate_config_t *mode_datarate_config, - const xcvr_datarate_config_t *datarate_config, - int16_t tempDegC, - XCVR_INIT_MODE_CHG_T first_init); - -/*! - * @brief Set XCVR register to reset value. - * - * This function set XCVR register to the reset value. - * - */ -void XCVR_Reset(void); - -/*! - * @brief Change the operating mode of the radio. - * - * This function changes the XCVR to a new radio operating mode. - * - * @param new_radio_mode The radio mode for which the XCVR should be configured. - * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @return status of the mode change. - */ - xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate); - -/*! - * @brief Enable Narrowband RSSI measurement. - * - * This function enables the narrowband RSSI measurement - * - * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled. - */ -void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable); - -/*! - * @brief Set an arbitrary frequency for RX and TX for the radio. - * - * This function sets the radio frequency used for RX and RX.. - * - * @param freq target frequency setting in Hz. - * @param refOsc reference oscillator setting in Hz. - * @return status of the frequency change. - * @details - */ - xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc); - -/*! - * @brief Register a callback from upper layers. - * - * This function registers a callback from the upper layers for the radio to call in case of fatal errors. - * - * @param fptr The function pointer to a panic callback. - */ -void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */ - -/*! - * @brief Read the health status of the XCVR to detect errors. - * - * This function enables the upper layers to request the current radio health. - * - * @return The health status of the radio.. - */ -healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */ - -/*! - * @brief Control FAD and LPPS features. - * - * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search. - * - * @param fptr control the FAD and LPPS settings. - * - */ - void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control); - -/*! - * @brief Change the mapping of the radio IRQs. - * - * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. - * - * @param irq0_mapping the LL which should be mapped to the INT0 line. - * @param irq1_mapping the LL which should be mapped to the INT1 line. - * @return status of the mapping request. - * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line. - * @warning - * The same LL must NOT be mapped to both INT lines. - */ - xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping); - -#if RADIO_IS_GEN_3P0 -/*! - * @brief Sets the network address used by the PHY during BLE Bit Streaming Mode. - * - * This function programs the register in the PHY which contains the network address used during BSM. - * - * @param bsm_ntw_address the address to be used during BSM. - * @ note This routine does NOT enable BSM. - */ -void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address); - -/*! - * @brief Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode. - * - * This function reads the register in the PHY which contains the network address used during BSM. - * - * @return bsm_ntw_address the address to be used during BSM. - * @ note This routine does NOT enable BSM. - */ -uint32_t XCVR_GetBSM_NTW_Address(void); -#endif /* RADIO_IS_GEN_3P0 */ - -/*! - * @brief Get the mapping of the one of the radio IRQs. - * - * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. - * - * @param int_num the number, 0 or 1, of the INT line to fetched. - * @return the mapping setting of the specified line. - * @note Any value passed into this routine other than 0 will be treated as a 1. - */ - link_layer_t XCVR_GetIRQMapping(uint8_t int_num); - -/*! - * @brief Get the current configuration of the XCVR. - * - * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc - * - * @param curr_config pointer to a structure to be updated with the current mode and data rate. - * @return the status of the request, success or invalid parameter (null pointer). - * @note This API will return meaningless results if called before the radio is initialized... - */ -xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config); - -/******************************************************************************* - * Customer level trim functions - ******************************************************************************/ -/*! - * @brief Controls setting the XTAL trim value.. - * - * This function enables the upper layers set a crystal trim compensation facor - * - * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error. - * @return The health status of the radio.. - */ -xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim); - -/*! - * @brief Controls getting the XTAL trim value.. - * - * This function enables the upper layers to read the current XTAL compensation factors. - * The returned value is in the range 0..127 (7 bits). - * - * @return The XTAL trim compensation factors.. - */ -uint8_t XCVR_GetXtalTrim(void); - -/*! - * @brief Controls setting the RSSI adjustment.. - * - * This function enables the upper layers to set an RSSI adjustment value. - * - * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step. - * @return The health status of the radio.. - */ -xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj); - -/*! - * @brief Controls getting the RSSI adjustment.. - * - * This function enables the upper layers to read the current XCVR RSSI adjustment value. - * The returned value is a signed 8-bit value, in 1/4 dBm step. - * - * @return The RSSI adjustment value.. - */ -int8_t XCVR_GetRssiAdjustment(void); - -/*! - * @brief Controls setting the PLL to a particular channel. - * - * This function enables setting the radio channel for TX and RX. - * - * @param channel the channel number to set - * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list.. - * @return The status of the channel over-ride. - */ -xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel); - -/*! - * @brief Reads the current frequency for RX and TX for the radio. - * - * This function reads the radio frequency used for RX and RX.. - * - * @return Current radio frequency setting. - */ -uint32_t XCVR_GetFreq(void); - -/*! - * @brief Force receiver warmup. - * - * This function forces the initiation of a receiver warmup sequence. - * - */ -void XCVR_ForceRxWu(void); - -/*! - * @brief Force receiver warmdown. - * - * This function forces the initiation of a receiver warmdown sequence. - * - */ - void XCVR_ForceRxWd(void); - -/*! - * @brief Force transmitter warmup. - * - * This function forces the initiation of a transmit warmup sequence. - * - */ -void XCVR_ForceTxWu(void); - -/*! - * @brief Force transmitter warmdown. - * - * This function forces the initiation of a transmit warmdown sequence. - * - */ -void XCVR_ForceTxWd(void); - -/*! - * @brief Starts transmit with a TX pattern register data sequence. - * - * This function starts transmitting using the DFT pattern register mode. - * - * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. - * @param radio_mode The radio mode for which the XCVR should be configured. - * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @param tx_pattern - the data pattern to transmit on. - * @return The status of the pattern reg transmit. - * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode - * and data rate. - */ -xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern); - -/*! - * @brief Starts transmit with a TX LFSR register data sequence. - * - * This function starts transmitting using the DFT LFSR register mode. - * - * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. - * @param radio_mode The radio mode for which the XCVR should be configured. - * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @param lfsr_length - the length of the LFSR sequence to use. - * @return The status of the LFSR reg transmit. - * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode - * and data rate. - */ -xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length); - -/*! - * @brief Controls clearing all TX DFT settings. - * - * This function reverts all TX DFT settings from the test modes to normal operating mode. - * - */ -void XCVR_DftTxOff(void); - -/*! - * @brief Controls setting the PA power level. - * - * This function enables setting the PA power level to a specific setting, overriding any link layer settings. - * - * @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive. - * @return The status of the PA power over-ride. - */ -xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); - -/*! - * @brief Starts CW TX. - * - * This function starts transmitting CW (no modulation). - * - * @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive. - * @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK). - * @return The status of the CW transmit. - */ -xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol); - -xcvrStatus_t XCVR_CoexistenceInit(void); -xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority); -xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_XCVR_H_ */ - diff --git a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.c b/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.c deleted file mode 100644 index 8edcb0aad..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.c +++ /dev/null @@ -1,995 +0,0 @@ -/* -* Copyright 2016-2017 NXP -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_device_registers.h" -#include "fsl_common.h" -#include "fsl_xcvr.h" -#include "fsl_xcvr_trim.h" -#include "dbg_ram_capture.h" -#include "math.h" - -/******************************************************************************* -* Definitions -******************************************************************************/ - - -/******************************************************************************* -* Prototypes -******************************************************************************/ -void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val); -float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ); -extern float roundf (float); - -/******************************************************************************* -* Variables -******************************************************************************/ -const int8_t TsettleCal = 10; -static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; -static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = -{ - 0, /* Baseline entry is first and not used in this table */ - -16, - +16, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4 -}; - -/******************************************************************************* - * Macros - ******************************************************************************/ -#define ISIGN(x) !((uint16_t)x & 0x8000) -#define ABS(x) ((x) > 0 ? (x) : -(x)) - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! ********************************************************************************* - * \brief This function performs a trim of the BBA DCOC DAC on the DUT - * - * \return status - 1 if passed, 0 if failed. - * - * \ingroup PublicAPIs - * - * \details - * Requires the RX to be warmed up before this function is called. - * - ***********************************************************************************/ -uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) -{ - uint8_t i; - float temp_mi = 0; - float temp_mq = 0; - float temp_pi = 0; - float temp_pq = 0; - float temp_step = 0; - uint8_t bbf_dacinit_i, bbf_dacinit_q; - - uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only. */ - uint32_t bbf_dcoc_step; - uint32_t bbf_dcoc_step_rcp; - TZAdcocstep_t tza_dcoc_step[11]; - uint8_t status = 0; - - /* Save register values. */ - uint32_t dcoc_ctrl_0_stack; - uint32_t dcoc_ctrl_1_stack; - uint32_t agc_ctrl_1_stack; - uint32_t rx_dig_ctrl_stack; - uint32_t dcoc_cal_gain_state; - - XcvrCalDelay(1000); - dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */ - dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */ - rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore. */ - agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */ - dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore. */ - - /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode. */ - XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(0); /* Turn OFF AGC */ - - XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) ; /* Set LNA Manual Gain */ - XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) ; /* Set BBA Manual Gain */ - - XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(0); /* Enable HW DC Calibration -- Disable for SW-DCOC */ - XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ - /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode. */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); - /* Set DCOC Tracking State. */ - XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(0); /* Disables DCOC Tracking when set to 0 */ - /* Apply Manual Gain. */ - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x02) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x00) ; - XcvrCalDelay(TsettleCal); - - dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Capture DC null setting. */ - - bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); - bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8; - - DC_Measure_short(I_CHANNEL, NOMINAL2); - DC_Measure_short(Q_CHANNEL, NOMINAL2); - - /* SWEEP Q CHANNEL */ - /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(Q_CHANNEL, BBF_NEG); - - /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(Q_CHANNEL, BBF_POS); - - XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */ - XcvrCalDelay(TsettleCal); - - /* SWEEP I CHANNEL */ - /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(I_CHANNEL, BBF_NEG); - /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(I_CHANNEL, BBF_POS); - - XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DACs to initial. */ - XcvrCalDelay(TsettleCal); - - /* Calculate BBF DCOC STEPS, RECIPROCALS */ - temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - - temp_step = (temp_mi+temp_pi + temp_mq+temp_pq) / 4; - - bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); - - if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) - { - bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); - - /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */ - for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */ - { - /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */ - switch(i){ - case TZA_STEP_N0: - temp_step = (bbf_dcoc_step >> 3U) / 3.6F; - break; - case TZA_STEP_N1: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); - break; - case TZA_STEP_N2: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); - break; - case TZA_STEP_N3: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); - break; - case TZA_STEP_N4: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); - break; - case TZA_STEP_N5: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); - break; - case TZA_STEP_N6: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16); - break; - case TZA_STEP_N7: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); - break; - case TZA_STEP_N8: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); - break; - case TZA_STEP_N9: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); - break; - case TZA_STEP_N10: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); - break; - default: - break; - } - - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); - } - - /* Make the trims active. */ - XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp) ; - - status = 1; /* Success */ - } - else - { - status = 0; /* Failure */ - } - - /* Restore Registers. */ - XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */ - XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */ - XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings. */ - XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting. */ - XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */ - - return status; -} - -/*! ********************************************************************************* - * \brief This function performs one point of the DC GAIN calibration process on the DUT - * - * \param[in] chan - whether the I or Q channel is being tested. - * \param[in] stage - whether the BBF or TZA gain stage is being tested. - * \param[in] dcoc_init_val - the value being set in the ***DCOC_INIT_* register by the parent. - * \param[in] ext_measmt - the external measurement (in milliVolts) captured by the parent after the ***DCOC_INIT_* register was setup. - * - * \ingroup PublicAPIs - * - * \details - * Relies on a static array to store each point of data for later processing in ::DC_GainCalc(). - * - ***********************************************************************************/ -void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) -{ - int16_t dc_meas_i = 0; - int16_t dc_meas_q = 0; - int16_t sum_dc_meas_i = 0; - int16_t sum_dc_meas_q = 0; - - { - int8_t i; - const int8_t iterations = 1; - sum_dc_meas_i = 0; - sum_dc_meas_q = 0; - - for (i = 0; i < iterations; i++) - { - rx_dc_sample_average(&dc_meas_i, &dc_meas_q); - sum_dc_meas_i = sum_dc_meas_i + dc_meas_i; - sum_dc_meas_q = sum_dc_meas_q + dc_meas_q; - } - sum_dc_meas_i = sum_dc_meas_i / iterations; - sum_dc_meas_q = sum_dc_meas_q / iterations; - } - - measurement_tbl2[chan][dcoc_init_val].step_value = sweep_step_values2[dcoc_init_val]; - - if (chan == I_CHANNEL) - { - measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_i; - } - else - { - measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q; - } -} - -/*! ********************************************************************************* - * \brief This function calculates one point of DC DAC step based on digital samples of I or Q. - * - * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement. - * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. - * - * \return result of the calculation, the measurement DCOC DAC step value for this measurement point. - * - ***********************************************************************************/ -float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ) -{ - static int16_t norm_dc_code; - static float dc_step; - - /* Normalize internal measurement */ - norm_dc_code = meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement; - dc_step = (float)(norm_dc_code) / (float)(meas_ptr->step_value); - dc_step = (dc_step < 0)? -dc_step: dc_step; - - return dc_step; -} - -/*! ********************************************************************************* - * \brief Temporary delay function - * - * \param[in] none. - * - * \return none. - * - * \details - * - ***********************************************************************************/ -void XcvrCalDelay(uint32_t time) -{ - while(time * 32 > 0) /* Time delay is roughly in uSec. */ - { - time--; - } -} - -/*! ********************************************************************************* - * \brief This function calculates the average (DC value) based on a smaller set of digital samples of I and Q. - * - * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. - * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. - * - ***********************************************************************************/ -void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) -{ - static uint32_t samples[128]; /* 544*2*2 (entire packet ram1/2 size) */ - uint16_t i; - uint32_t rx_sample; - uint16_t * sample_ptr; - uint32_t temp, end_of_rx_wu; - uint32_t num_iq_samples; - float avg_i = 0; - float avg_q = 0; - - num_iq_samples = 128; - - /* Clear the entire allocated sample buffer */ - for (i = 0; i < num_iq_samples; i++) - { - samples[i]=0; - } - - /* Assume this has been called *AFTER* RxWu has completed. */ - /* XCVR_ForceRxWu(); */ - - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - - dbg_ram_init(); - /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ -#if RADIO_IS_GEN_3P0 - dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); - dbg_ram_wait_for_complete(); - dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); - dbg_ram_release(); -#else - (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); -#endif /* RADIO_IS_GEN_3P0 */ - - /* Sign extend the IQ samples in place in the sample buffer. */ - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i++) - { - rx_sample = *sample_ptr; - rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - *sample_ptr = rx_sample; - sample_ptr++; - } - - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i += 2) - { - static int16_t i_value; - static int16_t q_value; - - /* Average I & Q channels separately. */ - i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits. */ - q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits. */ - avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ - avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ - } - XcvrCalDelay(10); - *i_avg = (int16_t)avg_i; - *q_avg = (int16_t)avg_q; -} - -/*! ********************************************************************************* - * \brief This function calculates the average (DC value) based on a larger set of digital samples of I and Q. - * - * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. - * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. - * - ***********************************************************************************/ -void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) -{ - static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */ - uint16_t i; - uint32_t rx_sample; - uint16_t * sample_ptr; - uint32_t temp, end_of_rx_wu; - uint32_t num_iq_samples; - float avg_i = 0; - float avg_q = 0; - - num_iq_samples = 512; - - /* Clear the entire allocated sample buffer. */ - for (i = 0; i < num_iq_samples; i++) - { - samples[i]=0; - } - - /* Assume this has been called *AFTER* RxWu has completed. */ - /* XCVR_ForceRxWu(); */ - - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - - dbg_ram_init(); - /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ -#if RADIO_IS_GEN_3P0 - dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); - dbg_ram_wait_for_complete(); - dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ,num_iq_samples * 2 * 2, &samples[0]); - dbg_ram_release(); -#else - (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); -#endif /* RADIO_IS_GEN_3P0 */ - - /* Sign extend the IQ samples in place in the sample buffer. */ - - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i++) - { - rx_sample = *sample_ptr; - rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - *sample_ptr = rx_sample; - sample_ptr++; - } - - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i += 2) - { - static int16_t i_value; - static int16_t q_value; - - /* Average I & Q channels separately. */ - i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits */ - q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits */ - avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ - avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ - } - - XcvrCalDelay(10); - *i_avg = (int16_t)avg_i; - *q_avg = (int16_t)avg_q; -} - -/*! ********************************************************************************* - * rx_dc_est_average : Get DC EST values and return the Average - ***********************************************************************************/ -void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber) -{ - float avg_i = 0; - float avg_q = 0; - uint16_t i = 0; - static uint32_t dc_temp, temp; - uint32_t end_of_rx_wu = 0; - static int16_t dc_meas_i; - static int16_t dc_meas_q; - - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - - /* Read DCOC DC EST register. */ - for (i = 0; i < SampleNumber; i++) - { - dc_temp = XCVR_RX_DIG->DCOC_DC_EST; - dc_meas_i = dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK; - temp = dc_meas_i; - temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - dc_meas_i = temp; - avg_i += (float) dc_meas_i; - - dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; - temp = dc_meas_q; - temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - dc_meas_q = temp; - avg_q += (float) dc_meas_q; - } - - avg_i /= (float) SampleNumber; - avg_q /= (float) SampleNumber; - - *i_avg = (int16_t)avg_i; - *q_avg = (int16_t)avg_q; -} - -/*! ********************************************************************************* - * \brief This function performs a trim of the BBA DCOC DAC on the DUT - * - * \return status - 1 if passed, 0 if failed. - * - * \ingroup PublicAPIs - * - * \details - * Requires the RX to be warmed up before this function is called. - * - ***********************************************************************************/ -uint8_t rx_bba_dcoc_dac_trim_DCest(void) -{ - uint8_t i; - float temp_mi = 0; - float temp_mq = 0; - float temp_pi = 0; - float temp_pq = 0; - float temp_step = 0; - - uint32_t bbf_dcoc_step; - uint32_t bbf_dcoc_step_rcp; - TZAdcocstep_t tza_dcoc_step[11]; - uint8_t status = 0; - - uint8_t bbf_dacinit_i, bbf_dacinit_q; - uint8_t tza_dacinit_i, tza_dacinit_q; - int16_t dc_meas_i; - int16_t dc_meas_q; - uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only */ - uint32_t temp; - - uint32_t dcoc_ctrl_0_stack; - uint32_t dcoc_ctrl_1_stack; - uint32_t agc_ctrl_1_stack; - uint32_t rx_dig_ctrl_stack; - uint32_t dcoc_cal_gain_state; - - /* Save register */ - dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ - dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ - rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ - agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ - dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ - - /* Register config */ - /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ - temp = XCVR_RX_DIG->RX_DIG_CTRL; - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ - XCVR_RX_DIG->RX_DIG_CTRL = temp; - - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ - - /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ - temp = XCVR_RX_DIG->DCOC_CTRL_0; - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ - XCVR_RX_DIG->DCOC_CTRL_0 = temp; - - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); - - XcvrCalDelay(TsettleCal); - - /* Set default DCOC DAC INIT Value */ - dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ - bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); - bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8; - tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16; - tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; - - XcvrCalDelay(TsettleCal * 4); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); - measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; - measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; - measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i; - measurement_tbl2[Q_CHANNEL][NOMINAL2].internal_measurement = dc_meas_q; - - /* SWEEP I/Q CHANNEL */ - /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - XcvrCalDelay(TsettleCal * 2); - - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); - measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16; - measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16; - measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i; - measurement_tbl2[Q_CHANNEL][BBF_NEG].internal_measurement = dc_meas_q; - - - /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); - measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16; - measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16; - measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i; - measurement_tbl2[Q_CHANNEL][BBF_POS].internal_measurement = dc_meas_q; - - XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ - - /* Calculate BBF DCOC STEPS, RECIPROCALS */ - temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - - temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; - bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); - - if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) - { - bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); - - /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ - for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) - { - /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ - switch(i){ - case TZA_STEP_N0: - temp_step = (bbf_dcoc_step>>3U) / 3.6F; - break; - case TZA_STEP_N1: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16); - break; - case TZA_STEP_N2: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16); - break; - case TZA_STEP_N3: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16); - break; - case TZA_STEP_N4: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16); - break; - case TZA_STEP_N5: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16); - break; - case TZA_STEP_N6: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16); - break; - case TZA_STEP_N7: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16); - break; - case TZA_STEP_N8: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16); - break; - case TZA_STEP_N9: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16); - break; - case TZA_STEP_N10: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16); - break; - default: - break; - } - - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); - } - - /* Make the trims active */ - XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp); - - status = 1; /* Success */ - } - else - { - status = 0; /* Failure */ - } - - /* Restore Registers */ - XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ - XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ - XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ - XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ - - return status; -} - -/*! ********************************************************************************* - * DCOC_DAC_INIT_Cal : slope sign seek depending on measure's sign - ***********************************************************************************/ -void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) -{ - int16_t dc_meas_i = 2000, dc_meas_i_p = 2000; - int16_t dc_meas_q = 2000, dc_meas_q_p = 2000; - uint8_t curr_tza_dac_i, curr_tza_dac_q; - uint8_t curr_bba_dac_i, curr_bba_dac_q; - uint8_t p_tza_dac_i, p_tza_dac_q; - uint8_t p_bba_dac_i, p_bba_dac_q; - uint8_t i = 0; - uint8_t bba_gain = 11; - bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; - - uint32_t dcoc_ctrl_0_stack; - uint32_t dcoc_ctrl_1_stack; - uint32_t agc_ctrl_1_stack; - uint32_t rx_dig_ctrl_stack; - uint32_t dcoc_cal_gain_state; - uint32_t xcvr_ctrl_stack; - - uint32_t temp; - - /* Save registers */ - dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ - dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ - rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ - agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ - dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ - - /* WarmUp */ - if (standalone_operation) - { - temp = XCVR_MISC->XCVR_CTRL; - xcvr_ctrl_stack = temp; - temp &= ~(XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK); - temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(0); - XCVR_MISC->XCVR_CTRL = temp; - XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */ - XCVR_ForceRxWu(); - XcvrCalDelay(2000); - } - - /* Register config */ - /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ - temp = XCVR_RX_DIG->RX_DIG_CTRL; - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ - XCVR_RX_DIG->RX_DIG_CTRL = temp; - - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ - - /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ - temp = XCVR_RX_DIG->DCOC_CTRL_0; - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ - XCVR_RX_DIG->DCOC_CTRL_0 = temp; - - XcvrCalDelay(TsettleCal); - - /* Set default DCOC DAC INIT Value */ - /* LNA and BBA DAC Sweep */ - curr_bba_dac_i = 0x20; - curr_bba_dac_q = 0x20; - curr_tza_dac_i = 0x80; - curr_tza_dac_q = 0x80; - - /* Perform a first DC measurement to ensure that measurement is not clipping */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); - - do - { - bba_gain--; - /* Set DAC user gain */ - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | - XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */ - XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | - XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ - XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); - } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900)); - - for (i = 0; i < 0x0F; i++) - { - /* I channel : */ - if (!TZA_I_OK) - { - if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0)) - { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) - { - curr_tza_dac_i = p_tza_dac_i; - } - - TZA_I_OK = 1; - } - else - { - p_tza_dac_i = curr_tza_dac_i; - - if (ISIGN(dc_meas_i)) /* If positif */ - { - curr_tza_dac_i--; - } - else - { - curr_tza_dac_i++; - } - } - } - else /* Sweep BBA I */ - { - if (!BBA_I_OK) - { - if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20)) - { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) - { - curr_bba_dac_i = p_bba_dac_i; - } - - BBA_I_OK = 1; - } - else - { - p_bba_dac_i = curr_bba_dac_i; - if (ISIGN(dc_meas_i)) /* If positif */ - { - curr_bba_dac_i--; - } - else - { - curr_bba_dac_i++; - } - } - } - } - - /* Q channel : */ - if (!TZA_Q_OK) - { - if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0)) - { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) - { - curr_tza_dac_q = p_tza_dac_q; - } - TZA_Q_OK = 1; - } - else - { - p_tza_dac_q = curr_tza_dac_q; - if (ISIGN(dc_meas_q)) /* If positif */ - { - curr_tza_dac_q--; - } - else - { - curr_tza_dac_q++; - } - } - } - else /* Sweep BBA Q */ - { - if (!BBA_Q_OK) - { - if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20)) - { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) - { - curr_bba_dac_q = p_bba_dac_q; - } - BBA_Q_OK = 1; - } - else - { - p_bba_dac_q = curr_bba_dac_q; - if (ISIGN(dc_meas_q)) /* If positif */ - { - curr_bba_dac_q--; - } - else - { - curr_bba_dac_q++; - } - } - } - } - - /* DC OK break : */ - if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK) - { - break; - } - - dc_meas_i_p = dc_meas_i; /* Store as previous value */ - dc_meas_q_p = dc_meas_q; /* Store as previous value */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); - XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); - } - - /* Apply optimized DCOC DAC INIT : */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); - - /* WarmDown */ - if (standalone_operation) - { - XCVR_ForceRxWd(); /* Don't leave the receiver running. */ - XcvrCalDelay(200); - XCVR_OverrideChannel(0xFF,1); /* Release channel overrides */ - XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack; - } - - /* Restore register */ - XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ - XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ - XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ - XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ -} - diff --git a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.h b/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.h deleted file mode 100644 index 9054b9e2a..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/fsl_xcvr_trim.h +++ /dev/null @@ -1,132 +0,0 @@ -/* -* Copyright 2016-2017 NXP -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -#ifndef _FSL_XCVR_TRIM_H_ -/* Clang-format off. */ -#define _FSL_XCVR_TRIM_H_ -/* Clang-format on. */ - -#include "fsl_device_registers.h" -/*! -* @addtogroup xcvr -* @{ -*/ - -/*! @file*/ - -/************************************************************************************ -************************************************************************************* -* Public constant definitions -************************************************************************************* -************************************************************************************/ - -/************************************************************************************ -************************************************************************************* -* Public type definitions -************************************************************************************* -************************************************************************************/ - -/* \brief The enumerations used to define the I & Q channel selections. */ -typedef enum -{ - I_CHANNEL = 0, - Q_CHANNEL = 1, - NUM_I_Q_CHAN = 2 -} IQ_t; - -typedef enum /* Enumeration of ADC_GAIN_CAL 2 */ -{ - NOMINAL2 = 0, - BBF_NEG = 1, - BBF_POS = 2, - TZA_STEP_N0 = 3, - TZA_STEP_N1 = 4, - TZA_STEP_N2 = 5, - TZA_STEP_N3 = 6, - TZA_STEP_N4 = 7, - TZA_STEP_N5 = 8, - TZA_STEP_N6 = 9, - TZA_STEP_N7 = 10, - TZA_STEP_N8 = 11, - TZA_STEP_N9 = 12, - TZA_STEP_N10 = 13, - TZA_STEP_P0 = 14, - TZA_STEP_P1 = 15, - TZA_STEP_P2 = 16, - TZA_STEP_P3 = 17, - TZA_STEP_P4 = 18, - TZA_STEP_P5 = 19, - TZA_STEP_P6 = 20, - TZA_STEP_P7 = 21, - TZA_STEP_P8 = 22, - TZA_STEP_P9 = 23, - TZA_STEP_P10 = 24, - - NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */ -} DAC_SWEEP_STEP2_t; - -/* \brief Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */ -typedef struct -{ - uint16_t dcoc_step; - uint16_t dcoc_step_rcp; -// uint16_t dcoc_step_q; -// uint16_t dcoc_step_rcp_q; -} TZAdcocstep_t; - -typedef struct -{ - int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */ - int16_t internal_measurement; /* The value (average code) measured from DMA samples. */ -// uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */ -} GAIN_CALC_TBL_ENTRY2_T; - -/******************************************************************************* -* Definitions -******************************************************************************/ -void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg); -void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg); -uint8_t rx_bba_dcoc_dac_trim_shortIQ(void); -void XcvrCalDelay(uint32_t time); -void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber); -uint8_t rx_bba_dcoc_dac_trim_DCest(void); -void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); - - - - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_XCVR_TRIM_H_ */ - diff --git a/third_party/nxp/MKW41Z4/XCVR/ifr_radio.c b/third_party/nxp/MKW41Z4/XCVR/ifr_radio.c deleted file mode 100644 index b3e2256ad..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/ifr_radio.c +++ /dev/null @@ -1,532 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_device_registers.h" -#include "fsl_xcvr.h" -#include "ifr_radio.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define IFR_RAM (0) - -#if RADIO_IS_GEN_3P0 -#define RDINDX (0x41U) -#define K3_BASE_INDEX (0x11U) /* Based for read index */ -#else -#define RDRSRC (0x03U) -#define KW4x_512_BASE (0x20000U) -#define KW4x_256_BASE (0x10000U) -#endif /* RADIO_IS_GEN_3P0 */ - -#if RADIO_IS_GEN_2P1 -#define FTFA (FTFE) -#endif /* RADIO_IS_GEN_2P1 */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -uint32_t read_another_ifr_word(void); -uint32_t read_first_ifr_word(uint32_t read_addr); - -#if RADIO_IS_GEN_3P0 -uint64_t read_index_ifr(uint32_t read_addr); -#else -/*! ********************************************************************************* - * @brief Reads a location in block 1 IFR for use by the radio. - * - * This function handles reading IFR data from flash memory for trim loading. - * - * @param read_addr the address in the IFR to be read. - * - * @details This function wraps both the Gen2 read_resource command and the Gen2.1 and Gen3 read_index -***********************************************************************************/ -#if RADIO_IS_GEN_2P1 -uint64_t read_resource_ifr(uint32_t read_addr); -#else -uint32_t read_resource_ifr(uint32_t read_addr); -#endif /* RADIO_IS_GEN_2P1 */ -#endif /* RADIO_IS_GEN_3P0 */ - -void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data); - -/******************************************************************************* - * Variables - ******************************************************************************/ -static uint32_t ifr_read_addr; - -#if RADIO_IS_GEN_3P0 -static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ -static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ -const uint32_t BLOCK_1_IFR[]= -{ - /* Revised fallback table which should work with untrimmed parts */ - 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ - - /* Trim table is empty for Gen3 by default */ - - /* No TRIM_STATUS in SW fallback array. */ - 0xFEED0E0FU /* End of File */ -}; -#else -#if RADIO_IS_GEN_2P0 -const uint32_t BLOCK_1_IFR[]= -{ - /* Revised fallback table which should work with untrimmed parts */ - 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ - - 0x4005912CU, /* RSIM_ANA_TRIM address */ - 0x784B0000U, /* RSIM_ANA_TRIM default value */ - - /* No TRIM_STATUS in SW fallback array. */ - 0xFEED0E0FU /* End of File */ -}; -#else -static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ -static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ -const uint32_t BLOCK_1_IFR[]= -{ - /* Revised fallback table which should work with untrimmed parts */ - 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ - - 0x4005912CU, /* RSIM_ANA_TRIM address */ - 0x784B0000U, /* RSIM_ANA_TRIM default value */ - - /* No TRIM_STATUS in SW fallback array. */ - 0xFEED0E0FU /* End of File */ -}; -#endif /* RADIO_IS_GEN_2P0 */ -#endif /* RADIO_IS_GEN_3P0 */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! ********************************************************************************* - * \brief Read command for reading the first 32bit word from IFR, encapsulates different - * flash IFR read mechanisms for multiple generations of SOC - * - * \param read_addr flash address - * - * \return 8 bytes of packed data containing radio trims only - * -***********************************************************************************/ -uint32_t read_first_ifr_word(uint32_t read_addr) -{ - ifr_read_addr = read_addr; - return read_another_ifr_word(); -} - -/*! ********************************************************************************* - * \brief Read command for reading additional 32bit words from IFR. Encapsulates multiple IFR read mechanisms. - * - * \param read_addr flash address - * - * \return 8 bytes of packed data containing radio trims only - * - * \remarks PRE-CONDITIONS: - * The function read_first_ifr_word() must have been called so that the ifr_read_addr variable is setup prior to use. - * -***********************************************************************************/ -uint32_t read_another_ifr_word(void) -{ - uint32_t packed_data; - -#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) - /* Using some static storage and alternating reads to read_index_ifr to replace read_resource_ifr */ - if (num_words_avail == 0) - { -#if RADIO_IS_GEN_3P0 - packed_data_long = read_index_ifr(ifr_read_addr); -#else /* Use 64 bit return version of read_resource */ - packed_data_long = read_resource_ifr(ifr_read_addr); -#endif /* RADIO_IS_GEN_3P0 */ - - num_words_avail = 2; - ifr_read_addr++; /* Read index addresses increment by 1 */ - } - - packed_data = (uint32_t)(packed_data_long & 0xFFFFFFFF); - packed_data_long = packed_data_long >> 32; - num_words_avail--; -#else - packed_data = read_resource_ifr(ifr_read_addr); - ifr_read_addr += 4; /* Read resource addresses increment by 4 */ -#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ - - return packed_data; -} - -#if RADIO_IS_GEN_3P0 -/*! ********************************************************************************* - * \brief Read command for reading from IFR using RDINDEX command - * - * \param read_addr flash address - * - * \return 8 bytes of packed data containing radio trims only - * -***********************************************************************************/ -uint64_t read_index_ifr(uint32_t read_addr) -{ - uint8_t rdindex = read_addr; - uint64_t read_data; - uint8_t i; - uint32_t primask; - - while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */ - - if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) - { - FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */ - } - - FTFE->FCCOB[0] = RDINDX; - FTFE->FCCOB[1] = rdindex; - - primask = DisableGlobalIRQ(); - FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; - while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ - EnableGlobalIRQ(primask); - - /* Pack read data back into 64 bit type */ - read_data = FTFE->FCCOB[11]; /* MSB goes in first, will be shifted left sequentially */ - for (i = 10; i > 3; i--) - { - read_data = read_data << 8; - read_data |= FTFE->FCCOB[i]; - } - - return read_data; -} -#else - -/*! ********************************************************************************* - * \brief Read command for reading from IFR - * - * \param read_addr flash address - * - * \return packed data containing radio trims only - * -***********************************************************************************/ -#if RADIO_IS_GEN_2P0 -uint32_t read_resource_ifr(uint32_t read_addr) -{ - uint32_t primask; - uint32_t packed_data; - uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; - uint32_t read_data31_24, read_data23_16, read_data15_8, read_data7_0; - - flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); - flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); - flash_addr7_0 = (uint8_t)(read_addr & 0xFF); - - while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ - - if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK) == FTFA_FSTAT_ACCERR_MASK ) - { - FTFA->FSTAT = (1<FCCOB0 = RDRSRC; - FTFA->FCCOB1 = flash_addr23_16; - FTFA->FCCOB2 = flash_addr15_8; - FTFA->FCCOB3 = flash_addr7_0; - FTFA->FCCOB8 = 0x00; - - primask = DisableGlobalIRQ(); - FTFA->FSTAT = FTFA_FSTAT_CCIF_MASK; - while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ - EnableGlobalIRQ(primask); - - /* Start reading */ - read_data31_24 = FTFA->FCCOB4; /* FTFA->FCCOB[4] */ - read_data23_16 = FTFA->FCCOB5; /* FTFA->FCCOB[5] */ - read_data15_8 = FTFA->FCCOB6; /* FTFA->FCCOB[6] */ - read_data7_0 = FTFA->FCCOB7; /* FTFA->FCCOB[7] */ - - packed_data = (read_data31_24 << 24) | (read_data23_16 << 16) | (read_data15_8 << 8) | (read_data7_0 << 0); - - return packed_data; -} -#else -uint64_t read_resource_ifr(uint32_t read_addr) -{ - uint32_t primask; - uint64_t packed_data; - uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; - uint8_t read_data[8]; - uint64_t temp_64; - uint8_t i; - - flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); - flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); - flash_addr7_0 = (uint8_t)(read_addr & 0xFF); - while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ - - if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) - { - FTFE->FSTAT = (1<FCCOB0 = RDRSRC; - FTFE->FCCOB1 = flash_addr23_16; - FTFE->FCCOB2 = flash_addr15_8; - FTFE->FCCOB3 = flash_addr7_0; - FTFE->FCCOB4 = 0x00; - - primask = DisableGlobalIRQ(); - FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; - while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ - EnableGlobalIRQ(primask); - - /* Start reading */ - read_data[7] = FTFE->FCCOB4; - read_data[6] = FTFE->FCCOB5; - read_data[5] = FTFE->FCCOB6; - read_data[4] = FTFE->FCCOB7; - read_data[3] = FTFE->FCCOB8; - read_data[2] = FTFE->FCCOB9; - read_data[1] = FTFE->FCCOBA; - read_data[0] = FTFE->FCCOBB; - - packed_data = 0; - for (i = 0; i < 8; i++) - { - temp_64 = read_data[i]; - packed_data |= temp_64 << (i * 8); - } - - return packed_data; -} - -#endif /* RADIO_IS_GEN_2P0 */ -#endif /* RADIO_IS_GEN_3P0 */ - -/*! ********************************************************************************* - * \brief Store a SW trim value in the table passed in from calling function. - * - * \param sw_trim_tbl pointer to the software trim table to hold SW trim values - * \param num_entries the number of entries in the SW trim table - * \param addr the software trim ID - * \param data the value of the software trim - * -***********************************************************************************/ -void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data) -{ - uint16_t i; - - if (sw_trim_tbl != NULL) - { - for (i = 0; i < num_entries; i++) - { - if (addr == sw_trim_tbl[i].trim_id) - { - sw_trim_tbl[i].trim_value = data; - sw_trim_tbl[i].valid = 1; - break; /* Don't need to scan the array any further... */ - } - } - } -} - -/*! ********************************************************************************* - * \brief Process block 1 IFR data. - * - * \param sw_trim_tbl pointer to the software trim table to hold SW trim values - * \param num_entries the number of entries in the SW trim table - * - * \remarks - * Uses a IFR v2 formatted default array if the IFR is blank or corrupted. - * Stores SW trim values to an array passed into this function. - * -***********************************************************************************/ -void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries) -{ - uint32_t dest_addr; - uint32_t read_addr; - uint32_t dest_data; - uint32_t packed_data; - uint32_t *ifr_ptr; - -#if RADIO_IS_GEN_3P0 - num_words_avail = 0; /* Prep for handling 64 bit words from flash */ -#endif /* RADIO_IS_GEN_3P0 */ - -#if RADIO_IS_GEN_3P0 - read_addr = K3_BASE_INDEX; -#else -#ifdef CPU_MKW41Z256VHT4 - read_addr = KW4x_256_BASE; -#else - read_addr = KW4x_512_BASE; -#endif /* CPU_MKW41Z256VHT4 */ -#endif /* RADIO_IS_GEN_3P0 */ - - /* Read first entry in IFR table */ - packed_data = read_first_ifr_word(read_addr); - if ((packed_data&~IFR_VERSION_MASK) == IFR_VERSION_HDR) - { - /* Valid header was found, process real IFR data */ - XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); - store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array*/ - packed_data = read_another_ifr_word(); - - while (packed_data !=IFR_EOF_SYMBOL) - { - if (IS_A_SW_ID(packed_data)) /* SW Trim case (non_reg writes) */ - { - dest_addr = packed_data; - packed_data = read_another_ifr_word(); - dest_data = packed_data; - /* Place SW trim in array for driver SW to use */ - store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); - } - else - { - if (IS_VALID_REG_ADDR(packed_data)) /* Valid register write address */ - { - dest_addr = packed_data; - packed_data = read_another_ifr_word(); - dest_data = packed_data; - *(uint32_t *)(dest_addr) = dest_data; - } - else - { /* Invalid address case */ - - } - } - - packed_data=read_another_ifr_word(); - } - } - else - { - /* Valid header is not present, use blind IFR trim table */ - ifr_ptr = (void *)BLOCK_1_IFR; - packed_data = *ifr_ptr; - XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); - store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array */ - ifr_ptr++; - packed_data= *ifr_ptr; - - while (packed_data != IFR_EOF_SYMBOL) - { - if (IS_A_SW_ID(packed_data)) - { - /* SW Trim case (non_reg writes) */ - dest_addr = packed_data; - ifr_ptr++; - packed_data = *(ifr_ptr); - dest_data = packed_data; - /* Place SW trim in array for driver SW to use */ - store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); - } - else - { - dest_addr = packed_data; - ifr_ptr++; - packed_data = *ifr_ptr; - dest_data = packed_data; - - /* Valid register write address */ - if (IS_VALID_REG_ADDR(dest_addr)) - { - *(uint32_t *)(dest_addr) = dest_data; - } - else - { - /* Invalid address case */ - } - } - - ifr_ptr++; - packed_data= *ifr_ptr; - } - } -} - -#if RADIO_IS_GEN_3P0 - -#else -uint32_t handle_ifr_die_id(void) -{ - uint32_t id_x, id_y; - uint32_t id; - - id = read_resource_ifr(0x90); - id_x = id & 0x00FF0000; - id_y = id & 0x000000FF; - - return (id_x | id_y); -} - -uint32_t handle_ifr_die_kw_type(void) -{ - uint32_t zb, ble; - - zb = read_resource_ifr(0x80) & 0x8000; - ble= read_resource_ifr(0x88) & 0x100000; - - return (zb | ble); -} - -#endif /* RADIO_IS_GEN_3P0 */ - -/*! ********************************************************************************* - * \brief Dumps block 1 IFR data to an array. - * - * \param dump_tbl pointer to the table to hold the dumped IFR values - * \param num_entries the number of entries to dump - * - * \remarks - * Starts at the first address in IFR and dumps sequential entries. - * -***********************************************************************************/ -void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries) -{ -#if RADIO_IS_GEN_3P0 - uint32_t ifr_address = 0x20000; -#else - uint32_t ifr_address = 0x20000; -#endif /* RADIO_IS_GEN_3P0 */ - uint32_t * dump_ptr = dump_tbl; - uint8_t i; - - *dump_ptr = read_first_ifr_word(ifr_address); - dump_ptr++; - - for (i = 0; i < num_entries - 1; i++) - { - *dump_ptr = read_another_ifr_word(); - dump_ptr++; - } -} - diff --git a/third_party/nxp/MKW41Z4/XCVR/ifr_radio.h b/third_party/nxp/MKW41Z4/XCVR/ifr_radio.h deleted file mode 100644 index e02277f5a..000000000 --- a/third_party/nxp/MKW41Z4/XCVR/ifr_radio.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __IFR_RADIO_H__ -/* clang-format off */ -#define __IFR_RADIO_H__ -/* clang-format on */ - -#include -/* clang-format off */ -#define _FSL_XCVR_H_ -/* clang-format on */ - -/*! - * @addtogroup xcvr - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define IFR_EOF_SYMBOL (0xFEED0E0FU) /* < Denotes the "End of File" for IFR data */ -#define IFR_VERSION_HDR (0xABCD0000U) /* < Constant value for upper 16 bits of IFR data header */ -#define IFR_VERSION_MASK (0x0000FFFFU) /* < Mask for version number (lower 16 bits) of IFR data header */ -#define IFR_SW_ID_MIN (0x00000000U) /* < Lower limit of SW trim IDs */ -#define IFR_SW_ID_MAX (0x0000FFFFU) /* < Lower limit of SW trim IDs */ - -#define IS_A_SW_ID(x) ((IFR_SW_ID_MIN < (x)) && (IFR_SW_ID_MAX >= (x))) - -/* K3 valid registers support */ -#if (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) -#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x41000000U) /* Valid addresses are 0x410xxxxx */ -#endif /* (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) */ -/* KW41 and KW35/36 valid registers support */ -#if (defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) || \ - defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) || \ - defined(CPU_MKW21Z256VHT4) || defined(CPU_MKW21Z512VHT4) || \ - defined(CPU_MKW35A512VFP4) || defined(CPU_MKW36A512VFP4) ) - -#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x40050000U) /* Valid addresses are 0x4005xxxx */ -#endif - -#define MAKE_MASK(size) ((1 << (size)) - 1) -#define MAKE_MASKSHFT(size, bitpos) (MAKE_MASK(size) << (bitpos)) - -#define IFR_TZA_CAP_TUNE_MASK (0x0000000FU) -#define IFR_TZA_CAP_TUNE_SHIFT (0) -#define IFR_BBF_CAP_TUNE_MASK (0x000F0000U) -#define IFR_BBF_CAP_TUNE_SHIFT (16) -#define IFR_RES_TUNE2_MASK (0x00F00000U) -#define IFR_RES_TUNE2_SHIFT (20) - -/* \var typedef uint8_t IFR_ERROR_T */ -/* \brief The IFR error reporting type. */ -/* See #IFR_ERROR_T_enum for the enumeration definitions. */ -typedef uint8_t IFR_ERROR_T; - -/* \brief The enumerations used to describe IFR errors. */ -enum IFR_ERROR_T_enum -{ - IFR_SUCCESS = 0, - INVALID_POINTER = 1, /* < NULL pointer error */ - INVALID_DEST_SIZE_SHIFT = 2, /* < the bits won't fit as specified in the destination */ -}; - -/* \var typedef uint16_t SW_TRIM_ID_T */ -/* \brief The SW trim ID type. */ -/* See #SW_TRIM_ID_T_enum for the enumeration definitions. */ -typedef uint16_t SW_TRIM_ID_T; - -/* \brief The enumerations used to define SW trim IDs. */ -enum SW_TRIM_ID_T_enum -{ - Q_RELATIVE_GAIN_BY_PART = 0, /* < Q vs I relative gain trim ID */ - ADC_GAIN = 1, /* < ADC gain trim ID */ - ZB_FILT_TRIM = 2, /* < Baseband Bandwidth filter trim ID for BLE */ - BLE_FILT_TRIM = 3, /* < Baseband Bandwidth filter trim ID for BLE */ - TRIM_STATUS = 4, /* < Status result of the trim process (error indications) */ - TRIM_VERSION = 0xABCD, /* < Version number of the IFR trim algorithm/format. */ -}; - -/* \var typedef uint32_t IFR_TRIM_STATUS_T */ -/* \brief The definition of failure bits stored in IFR trim status word. */ -/* See #IFR_TRIM_STATUS_T_enum for the enumeration definitions. */ -typedef uint32_t IFR_TRIM_STATUS_T; - -/* \brief The enumerations used to describe trim algorithm failures in the status entry in IFR. */ -/* This enum represents multiple values which can be OR'd together in a single status word. */ -enum IFR_TRIM_STATUS_T_enum -{ - TRIM_ALGORITHM_SUCCESS = 0, - BGAP_VOLTAGE_TRIM_FAILED = 1, /* < algorithm failure in BGAP voltagetrim */ - IQMC_GAIN_ADJ_FAILED = 2, /* < algorithm failure in IQMC gain trim */ - IQMC_PHASE_ADJ_FAILED = 4, /* < algorithm failure in IQMC phase trim */ - IQMC_DC_GAIN_ADJ_FAILED = 8, /* < */ - ADC_GAIN_TRIM_FAILED = 10, /* <*/ - ZB_FILT_TRIM_FAILED = 20, /* < */ - BLE_FILT_TRIM_FAILED = 40, /* < */ -}; - -/* \var typedef struct IFR_SW_TRIM_TBL_ENTRY_T */ -/* \brief Structure defining an entry in a table used to contain values to be passed back from IFR */ -/* handling routine to XCVR driver software. */ -typedef struct -{ - SW_TRIM_ID_T trim_id; /* < The assigned ID */ - uint32_t trim_value; /* < The value fetched from IFR.*/ - uint8_t valid; /* < validity of the trim_value field after IFR processing is complete (TRUE/FALSE).*/ -} IFR_SW_TRIM_TBL_ENTRY_T; - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @brief Reads a location in block 1 IFR for use by the radio. - * - * This function handles reading IFR data from flash memory for trim loading. - * - * @param read_addr the address in the IFR to be read. - */ -uint32_t read_resource_ifr(uint32_t read_addr); - -/*! - * @brief Reads a location in a simulated data array to support IFR handler testing. - * - * This function handles reading data from a const table for testing the trim loading functions. - * - * @param read_addr the address in the IFR to be read. - */ -uint32_t read_resource(uint16_t resource_id); - -/*! - * @brief Main IFR handler function called by XCVR driver software to process trim table. - * - * This function handles reading data from IFR and either loading to registers or storing to a SW trim values table. - * - * @param sw_trim_tbl pointer to the table used to store software trim values. - * @param num_entries the number of entries that can be stored in the SW trim table. - */ -void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries); - -/*! - * @brief Handler function to read die_id from IFR locations.. - * - * This function handles reading die ID value for debug and testing usage. - * - * @return the value of the die ID field. - */ -uint32_t handle_ifr_die_id(void); - -/*! - * @brief Handler function to read KW chip version from IFR locations.. - * - * This function handles reading KW chip version for debug and testing usage. - * - * @return the value of the KW version field. - */ -uint32_t handle_ifr_die_kw_type(void); - -/*! - * @brief Debug function to dump the IFR contents to a RAM array. - * - * This function handles reading data from IFR and storing to a RAM array for debug. - * - * @param dump_tbl pointer to the table used to store IFR entry values. - * @param num_entries the number of entries that can be stored in the dump table. - */ -void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries); - -#endif /*__IFR_RADIO_H__ */ - diff --git a/third_party/nxp/MKW41Z4/clock_config.c b/third_party/nxp/MKW41Z4/clock_config.c deleted file mode 100644 index 0477f43e6..000000000 --- a/third_party/nxp/MKW41Z4/clock_config.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock - * and flash clock are in allowed range during clock mode switch. - * - * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. - * - * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and - * internal reference clock(MCGIRCLK). Follow the steps to setup: - * - * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. - * - * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured - * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig - * explicitly to setup MCGIRCLK. - * - * 3). Don't need to configure FLL explicitly, because if target mode is FLL - * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, - * if the target mode is not FLL mode, the FLL is disabled. - * - * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been - * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could - * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. - * - * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. - */ - -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!ClocksProfile -product: Clocks v1.0 -processor: MKW41Z512xxx4 -package_id: MKW41Z512VHT4 -mcu_data: ksdk2_0 -processor_version: 0.1.28 -board: FRDM-KW41Z - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -#include "fsl_rtc.h" -#include "clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define RTC_OSC_CAP_LOAD_0PF 0x0U /*!< RTC oscillator capacity load: 0pF */ -#define SIM_LPUART_CLK_SEL_OSCERCLK_CLK 2U /*!< LPUART clock select: OSCERCLK clock */ -#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */ -#define SIM_TPM_CLK_SEL_OSCERCLK_CLK 2U /*!< TPM clock select: OSCERCLK clock */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_FllStableDelay - * Description : This function is used to delay for FLL stable. - * - *END**************************************************************************/ -static void CLOCK_CONFIG_FllStableDelay(void) -{ - uint32_t i = 30000U; - - while (i--) - { - __NOP(); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_SetRtcClock - * Description : This function is used to configuring RTC clock - * - *END**************************************************************************/ -static void CLOCK_CONFIG_SetRtcClock() -{ - /* RTC clock gate enable */ - CLOCK_EnableClock(kCLOCK_Rtc0); - - /* Set RTC_TSR if there is fault value in RTC */ - if (RTC->SR & RTC_SR_TIF_MASK) - { - RTC -> TSR = RTC -> TSR; - } - - /* RTC clock gate disable */ - CLOCK_DisableClock(kCLOCK_Rtc0); -} - -/*FUNCTION********************************************************************** - * - * Function Name : CLOCK_CONFIG_EnableRtcOsc - * Description : This function is used to enabling RTC oscillator - * Param capLoad : Oscillator capacity load - * - *END**************************************************************************/ -static void CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad) -{ - /* RTC clock gate enable */ - CLOCK_EnableClock(kCLOCK_Rtc0); - - if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) /* Only if the Rtc oscillator is not already enabled */ - { - /* Set the specified capacitor configuration for the RTC oscillator */ - RTC_SetOscCapLoad(RTC, capLoad); - /* Enable the RTC 32KHz oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; - } - - /* RTC clock gate disable */ - CLOCK_DisableClock(kCLOCK_Rtc0); - CLOCK_SetXtal32Freq(32768); -} - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_RfOscInit - * Description : This function is used to setup Ref oscillator for KW40_512. - * - *END**************************************************************************/ -void BOARD_RfOscInit(void) -{ - uint32_t tempTrim; - uint8_t revId; - - /* Obtain REV ID from SIM */ - revId = (uint8_t)((uint32_t)(SIM->SDID & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT); - - if (0 == revId) - { - tempTrim = RSIM->ANA_TRIM; - RSIM->ANA_TRIM |= RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK; /* Set max trim for BB LDO for XO */ - }/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */ - - /* Turn on clocks for the XCVR */ - - /* Enable RF OSC in RSIM and wait for ready */ - RSIM->CONTROL = ((RSIM->CONTROL & ~RSIM_CONTROL_RF_OSC_EN_MASK) | RSIM_CONTROL_RF_OSC_EN(1)); - - /* ERR010224 */ - RSIM->RF_OSC_CTRL |= - RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */ - - while ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0); /* Wait for RF_OSC_READY */ - - if (0 == revId) - { - SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; - XCVR_TSM->OVRD0 |= XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK | - XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK; /* Force ADC DAC LDO on to prevent BGAP failure */ - - RSIM->ANA_TRIM = tempTrim; /* Reset LDO trim settings */ - }/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */ - -} - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitOsc0 - * Description : This function is used to setup MCG OSC with Ref oscillator for KW40_512. - * - *END**************************************************************************/ -void BOARD_InitOsc0(void) -{ - const osc_config_t oscConfig = - { - .freq = BOARD_XTAL0_CLK_HZ, .workMode = kOSC_ModeExt, - }; - - /* Initializes OSC0 according to previous configuration to meet Ref OSC needs. */ - CLOCK_InitOsc0(&oscConfig); - - /* Passing the XTAL0 frequency to clock driver. */ - CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** -!!Configuration -name: BOARD_BootClockRUN -outputs: -- {id: Bus_clock.outFreq, value: 23.986176 MHz} -- {id: Core_clock.outFreq, value: 47.972352 MHz} -- {id: ERCLK32K.outFreq, value: 32.768 kHz} -- {id: Flash_clock.outFreq, value: 23.986176 MHz} -- {id: LPO_clock.outFreq, value: 1 kHz} -- {id: LPUART0CLK.outFreq, value: 32 MHz} -- {id: MCGFLLCLK.outFreq, value: 47.972352 MHz} -- {id: MCGIRCLK.outFreq, value: 32.768 kHz} -- {id: OSCERCLK.outFreq, value: 32 MHz} -- {id: System_clock.outFreq, value: 47.972352 MHz} -- {id: TPMCLK.outFreq, value: 32 MHz} -settings: -- {id: MCGMode, value: FEE} -- {id: LPUART0ClkConfig, value: 'yes'} -- {id: MCG.FCRDIV.scale, value: '1'} -- {id: MCG.FLL_mul.scale, value: '1464'} -- {id: MCG.IREFS.sel, value: MCG.FRDIV} -- {id: MCG.OSCSEL.sel, value: RTC_32K.OSCCLK32K} -- {id: MCG_C1_IRCLKEN_CFG, value: Enabled} -- {id: RTC_CR_OSCE_CFG, value: Oscillator_enabled} -- {id: SIM.LPUART0SRCSEL.sel, value: REFOSC.OSCCLK} -- {id: SIM.TPMSRCSEL.sel, value: REFOSC.OSCCLK} -- {id: TPMClkConfig, value: 'yes'} -sources: -- {id: REFOSC.OSC.outFreq, value: 32 MHz, enabled: true} -- {id: RTC_32K.OSC32kHz.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const mcg_config_t mcgConfig_BOARD_BootClockRUN = -{ - .mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */ - .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ - .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ - .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ - .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ - .drs = kMCG_DrsMid, /* Mid frequency range */ - .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ - .oscsel = kMCG_OscselRtc, /* Selects 32 kHz RTC Oscillator */ -}; -const sim_clock_config_t simConfig_BOARD_BootClockRUN = -{ - .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ - .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */ -}; - -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Setup the reference oscillator. */ - BOARD_RfOscInit(); - /* Set the system clock dividers in SIM to safe value. */ - CLOCK_SetSimSafeDivs(); - /* Enable RTC oscillator. */ - CLOCK_CONFIG_EnableRtcOsc(RTC_OSC_CAP_LOAD_0PF); - /* Initializes OSC0 according to Ref OSC needs. */ - BOARD_InitOsc0(); - /* Set MCG to FEE mode. */ - CLOCK_BootToFeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, - mcgConfig_BOARD_BootClockRUN.frdiv, - mcgConfig_BOARD_BootClockRUN.dmx32, - mcgConfig_BOARD_BootClockRUN.drs, - CLOCK_CONFIG_FllStableDelay); - /* Configure the Internal Reference clock (MCGIRCLK). */ - CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, - mcgConfig_BOARD_BootClockRUN.ircs, - mcgConfig_BOARD_BootClockRUN.fcrdiv); - /* Set the clock configuration in SIM module. */ - CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); - /* Configure RTC clock. */ - CLOCK_CONFIG_SetRtcClock(); - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; - /* Set LPUART0 clock source. */ - CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_OSCERCLK_CLK); - /* Set TPM clock source. */ - CLOCK_SetTpmClock(SIM_TPM_CLK_SEL_OSCERCLK_CLK); -} - diff --git a/third_party/nxp/MKW41Z4/clock_config.h b/third_party/nxp/MKW41Z4/clock_config.h deleted file mode 100644 index ec19393d1..000000000 --- a/third_party/nxp/MKW41Z4/clock_config.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 32000000U /*!< Board xtal0 frequency in Hz */ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 47972352U /*!< Core clock frequency: 47972352Hz */ - -/*! @brief MCG set for BOARD_BootClockRUN configuration. - */ -extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; -/*! @brief SIM module set for BOARD_BootClockRUN configuration. - */ -extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; -/*! @brief OSC set for BOARD_BootClockRUN configuration. - */ -extern const osc_config_t oscConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.c b/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.c deleted file mode 100644 index fea206bd1..000000000 --- a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.c +++ /dev/null @@ -1,1696 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dspi_cmsis.h" - -#if ((RTE_SPI0 && defined(DSPI0)) || (RTE_SPI1 && defined(DSPI1)) || (RTE_SPI2 && defined(DSPI2))) - -#define ARM_DSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ - -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS; - -typedef const struct _cmsis_dspi_resource -{ - SPI_Type *base; - uint32_t instance; - uint32_t (*GetFreq)(void); -} cmsis_dspi_resource_t; - -typedef union _cmsis_dspi_handle -{ - dspi_master_handle_t masterHandle; - dspi_slave_handle_t slaveHandle; -} cmsis_dspi_handle_t; - -typedef struct _cmsis_dspi_interrupt_driver_state -{ - cmsis_dspi_resource_t *resource; - cmsis_dspi_handle_t *handle; - ARM_SPI_SignalEvent_t event; - - uint32_t baudRate_Bps; - bool isInitialized; - bool isConfigured; - bool isPowerOn; -} cmsis_dspi_interrupt_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -typedef const struct _cmsis_dspi_dma_resource -{ - DMA_Type *txDmaBase; - uint32_t txDmaChannel; - DMAMUX_Type *txDmamuxBase; - uint8_t txDmaRequest; - - DMA_Type *rxDmaBase; - uint32_t rxDmaChannel; - DMAMUX_Type *rxDmamuxBase; - uint8_t rxDmaRequest; -} cmsis_dspi_dma_resource_t; - -typedef struct _cmsis_dspi_dma_driver_state -{ - cmsis_dspi_resource_t *resource; - cmsis_dspi_dma_resource_t *dmaResource; - union _cmsis_dma_handle - { - dspi_master_dma_handle_t masterHandle; - dspi_slave_dma_handle_t slaveHandle; - } handle; - dma_handle_t txHandle; - dma_handle_t rxHandle; - ARM_SPI_SignalEvent_t event; - - uint32_t baudRate_Bps; - bool isInitialized; - bool isConfigured; - bool isPowerOn; -} cmsis_dspi_dma_driver_state_t; -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -typedef union _cmsis_dspi_edma_handle -{ - dspi_master_edma_handle_t masterHandle; - dspi_slave_edma_handle_t slaveHandle; -} cmsis_dspi_edma_handle_t; - -typedef const struct _cmsis_dspi_edma_resource -{ - DMA_Type *txEdmaBase; - uint32_t txEdmaChannel; - DMAMUX_Type *txDmamuxBase; - uint8_t txDmaRequest; - - DMA_Type *rxEdmaBase; - uint32_t rxEdmaChannel; - DMAMUX_Type *rxDmamuxBase; - uint8_t rxDmaRequest; - - DMA_Type *masterLinkEdmaBase; - uint32_t masterLinkChannel; -} cmsis_dspi_edma_resource_t; - -typedef struct _cmsis_dspi_edma_driver_state -{ - cmsis_dspi_resource_t *resource; - cmsis_dspi_edma_resource_t *dmaResource; - cmsis_dspi_edma_handle_t *handle; - edma_handle_t *edmaRxRegToRxDataHandle; - edma_handle_t *edmaTxDataToIntermediaryHandle; - edma_handle_t *edmaIntermediaryToTxRegHandle; - edma_handle_t *edmaTxDataToTxRegHandle; - ARM_SPI_SignalEvent_t event; - - uint32_t baudRate_Bps; - bool isInitialized; - bool isConfigured; - bool isPowerOn; -} cmsis_dspi_edma_driver_state_t; -#endif - -/* Driver Version */ -static const ARM_DRIVER_VERSION s_dspiDriverVersion = {ARM_SPI_API_VERSION, ARM_DSPI_DRV_VERSION}; - -/* Driver Capabilities */ -static const ARM_SPI_CAPABILITIES s_dspiDriverCapabilities = { - 1, /* Simplex Mode (Master and Slave) */ - 0, /* TI Synchronous Serial Interface */ - 0, /* Microwire Interface */ - 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ -}; - -/* - *Common Control function used by DSPI_InterruptControl / DSPI_EdmaControl. - */ -static int32_t DSPI_CommonControl(uint32_t control, uint32_t arg, cmsis_dspi_resource_t *resource, bool *isConfigured) -{ - dspi_master_config_t masterConfig; - DSPI_MasterGetDefaultConfig(&masterConfig); - dspi_slave_config_t slaveConfig; - DSPI_SlaveGetDefaultConfig(&slaveConfig); - masterConfig.ctarConfig.baudRate = arg; - -#if (defined(RTE_SPI0_PCS_TO_SCK_DELAY) && defined(RTE_SPI0_SCK_TO_PSC_DELAY) && \ - defined(RTE_SPI0_BETWEEN_TRANSFER_DELAY)) - if (0U == resource->instance) - { - masterConfig.ctarConfig.pcsToSckDelayInNanoSec = RTE_SPI0_PCS_TO_SCK_DELAY; - masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = RTE_SPI0_SCK_TO_PSC_DELAY; - masterConfig.ctarConfig.betweenTransferDelayInNanoSec = RTE_SPI0_BETWEEN_TRANSFER_DELAY; - } -#endif /*RTE DSPI0 trnafer delay time configure */ - -#if (defined(RTE_SPI1_PCS_TO_SCK_DELAY) && defined(RTE_SPI1_SCK_TO_PSC_DELAY) && \ - defined(RTE_SPI1_BETWEEN_TRANSFER_DELAY)) - if (1U == resource->instance) - { - masterConfig.ctarConfig.pcsToSckDelayInNanoSec = RTE_SPI1_PCS_TO_SCK_DELAY; - masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = RTE_SPI1_SCK_TO_PSC_DELAY; - masterConfig.ctarConfig.betweenTransferDelayInNanoSec = RTE_SPI1_BETWEEN_TRANSFER_DELAY; - } -#endif /*RTE DSPI1 trnafer delay time configure */ - -#if (defined(RTE_SPI2_PCS_TO_SCK_DELAY) && defined(RTE_SPI2_SCK_TO_PSC_DELAY) && \ - defined(RTE_SPI2_BETWEEN_TRANSFER_DELAY)) - if (2U == resource->instance) - { - masterConfig.ctarConfig.pcsToSckDelayInNanoSec = RTE_SPI2_PCS_TO_SCK_DELAY; - masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = RTE_SPI2_SCK_TO_PSC_DELAY; - masterConfig.ctarConfig.betweenTransferDelayInNanoSec = RTE_SPI2_BETWEEN_TRANSFER_DELAY; - } -#endif /*RTE DSPI2 trnafer delay time configure */ - - switch (control & ARM_SPI_FRAME_FORMAT_Msk) - { - case ARM_SPI_CPOL0_CPHA0: /* Clock Polarity 0, Clock Phase 0*/ - if (DSPI_IsMaster(resource->base)) - { - masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow; - masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - } - else - { - slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow; - slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - } - break; - - case ARM_SPI_CPOL0_CPHA1: /* Clock Polarity 0, Clock Phase 1*/ - if (DSPI_IsMaster(resource->base)) - { - masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow; - masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge; - } - else - { - slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow; - slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge; - } - break; - - case ARM_SPI_CPOL1_CPHA0: /* Clock Polarity 1, Clock Phase 0*/ - if (DSPI_IsMaster(resource->base)) - { - masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - } - else - { - slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - } - break; - - case ARM_SPI_CPOL1_CPHA1: /* Clock Polarity 1, Clock Phase 1*/ - if (DSPI_IsMaster(resource->base)) - { - masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge; - } - else - { - slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge; - } - break; - - default: - break; - } - - if (control & ARM_SPI_DATA_BITS_Msk) /* setting Number of Data bits */ - { - if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4) && - (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16)) - { - if (DSPI_IsMaster(resource->base)) - { - masterConfig.ctarConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); - } - else - { - slaveConfig.ctarConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); - } - } - else - { - return ARM_SPI_ERROR_DATA_BITS; - } - } - - switch (control & ARM_SPI_BIT_ORDER_Msk) - { - case ARM_SPI_LSB_MSB: /* SPI Bit order from LSB to MSB */ - if (DSPI_IsMaster(resource->base)) - { - masterConfig.ctarConfig.direction = kDSPI_LsbFirst; - } - break; - - case ARM_SPI_MSB_LSB: /* SPI Bit order from MSB to LSB */ - if (DSPI_IsMaster(resource->base)) - { - masterConfig.ctarConfig.direction = kDSPI_MsbFirst; - } - break; - - default: - break; - } - - if (DSPI_IsMaster(resource->base)) - { - if (*isConfigured) - { - DSPI_Deinit(resource->base); - } - DSPI_MasterInit(resource->base, &masterConfig, resource->GetFreq()); - *isConfigured = true; - } - else - { - if (*isConfigured) - { - DSPI_Deinit(resource->base); - } - DSPI_SlaveInit(resource->base, &slaveConfig); - *isConfigured = true; - } - - return ARM_DRIVER_OK; -} - -/******************************************************************************* - * Code - ******************************************************************************/ - -static ARM_DRIVER_VERSION DSPIx_GetVersion(void) -{ - return s_dspiDriverVersion; -} - -static ARM_SPI_CAPABILITIES DSPIx_GetCapabilities(void) -{ - return s_dspiDriverCapabilities; -} - -#endif - -#if (RTE_SPI0_DMA_EN || RTE_SPI1_DMA_EN || RTE_SPI2_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -void KSDK_DSPI_MasterEdmaCallback(SPI_Type *base, dspi_master_edma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_DSPI_OutOfRange == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - /* User data is actually CMSIS driver callback. */ - if ((0U != event) && (userData)) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} -void KSDK_DSPI_SlaveEdmaCallback(SPI_Type *base, dspi_slave_edma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_DSPI_OutOfRange == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - /* User data is actually CMSIS driver callback. */ - if ((0U != event) && (userData)) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -static int32_t DSPI_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_dspi_edma_driver_state_t *dspi) -{ - if (dspi->isInitialized) - { - return ARM_DRIVER_OK; - } - - dspi->isInitialized = true; - dspi->event = cb_event; - return ARM_DRIVER_OK; -} - -static int32_t DSPI_EdmaUninitialize(cmsis_dspi_edma_driver_state_t *dspi) -{ - dspi->isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t DSPI_EdmaPowerControl(ARM_POWER_STATE state, cmsis_dspi_edma_driver_state_t *dspi) -{ - switch (state) - { - case ARM_POWER_OFF: - if (dspi->isPowerOn) - { - DSPI_Deinit(dspi->resource->base); - DMAMUX_DisableChannel(dspi->dmaResource->rxDmamuxBase, dspi->dmaResource->rxEdmaChannel); - DMAMUX_DisableChannel(dspi->dmaResource->txDmamuxBase, dspi->dmaResource->txEdmaChannel); - dspi->isPowerOn = false; - dspi->isConfigured = false; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - if (!dspi->isInitialized) - { - return ARM_DRIVER_ERROR; - } - /* Enable Clock gate */ - CLOCK_EnableClock(s_dspiClock[dspi->resource->instance]); - dspi->isPowerOn = true; - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - return ARM_DRIVER_OK; -} - -static int32_t DSPI_EdmaSend(const void *data, uint32_t num, cmsis_dspi_edma_driver_state_t *dspi) -{ - int32_t ret; - status_t status; - dspi_transfer_t xfer; - - xfer.rxData = NULL; - xfer.txData = (uint8_t *)data; - xfer.dataSize = num; - - if (DSPI_IsMaster(dspi->resource->base)) - { -#if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL)) - if (0U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI0_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI0 PCS select configuration */ -#if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL)) - if (1U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI1_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI1 PCS select configuration */ -#if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL)) - if (2U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI2_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI2 PCS select configuration */ - } - else - { - /* DSPI slave use Ctar0 setting and slave can only use PCS0. */ - xfer.configFlags = kDSPI_SlaveCtar0; - } - - if (DSPI_IsMaster(dspi->resource->base)) - { - status = DSPI_MasterTransferEDMA(dspi->resource->base, &dspi->handle->masterHandle, &xfer); - } - else - { - status = DSPI_SlaveTransferEDMA(dspi->resource->base, &dspi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_DSPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t DSPI_EdmaReceive(void *data, uint32_t num, cmsis_dspi_edma_driver_state_t *dspi) -{ - int32_t ret; - status_t status; - dspi_transfer_t xfer; - - xfer.txData = NULL; - xfer.rxData = (uint8_t *)data; - xfer.dataSize = num; - - if (DSPI_IsMaster(dspi->resource->base)) - { -#if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL)) - if (0U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI0_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI0 PCS select configuration */ -#if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL)) - if (1U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI1_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI1 PCS select configuration */ -#if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL)) - if (2U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI2_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI2 PCS select configuration */ - } - else - { - /* DSPI slave use Ctar0 setting and slave can only use PCS0. */ - xfer.configFlags = kDSPI_SlaveCtar0; - } - - if (DSPI_IsMaster(dspi->resource->base)) - { - status = DSPI_MasterTransferEDMA(dspi->resource->base, &dspi->handle->masterHandle, &xfer); - } - else - { - status = DSPI_SlaveTransferEDMA(dspi->resource->base, &dspi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_DSPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t DSPI_EdmaTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_dspi_edma_driver_state_t *dspi) -{ - int32_t ret; - status_t status; - dspi_transfer_t xfer; - - xfer.txData = (uint8_t *)data_out; - xfer.rxData = (uint8_t *)data_in; - xfer.dataSize = num; - - if (DSPI_IsMaster(dspi->resource->base)) - { -#if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL)) - if (0U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI0_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI0 PCS select configuration */ -#if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL)) - if (1U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI1_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI1 PCS select configuration */ -#if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL)) - if (2U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI2_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI2 PCS select configuration */ - } - else - { - /* DSPI slave use Ctar0 setting and slave can only use PCS0. */ - xfer.configFlags = kDSPI_SlaveCtar0; - } - - if (DSPI_IsMaster(dspi->resource->base)) - { - status = DSPI_MasterTransferEDMA(dspi->resource->base, &dspi->handle->masterHandle, &xfer); - } - else - { - status = DSPI_SlaveTransferEDMA(dspi->resource->base, &dspi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_DSPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -static uint32_t DSPI_EdmaGetCount(cmsis_dspi_edma_driver_state_t *dspi) -{ - uint32_t cnt; - size_t bytes; - - if (DSPI_IsMaster(dspi->resource->base)) - { - if (dspi->handle->masterHandle.state != kDSPI_Idle) - { - cnt = 0UL; - return cnt; - } - bytes = (uint32_t)dspi->handle->masterHandle.nbytes * - EDMA_GetRemainingMajorLoopCount(dspi->dmaResource->rxEdmaBase, dspi->dmaResource->rxEdmaChannel); - cnt = dspi->handle->masterHandle.totalByteCount - bytes; - } - else - { - if (dspi->handle->slaveHandle.state != kDSPI_Idle) - { - cnt = 0UL; - return cnt; - } - bytes = (uint32_t)dspi->handle->slaveHandle.nbytes * - EDMA_GetRemainingMajorLoopCount(dspi->dmaResource->rxEdmaBase, dspi->dmaResource->rxEdmaChannel); - cnt = dspi->handle->slaveHandle.totalByteCount - bytes; - } - - return cnt; -} - -static int32_t DSPI_EdmaControl(uint32_t control, uint32_t arg, cmsis_dspi_edma_driver_state_t *dspi) -{ - if (!dspi->isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - cmsis_dspi_edma_resource_t *dmaResource = dspi->dmaResource; - - switch (control & ARM_SPI_CONTROL_Msk) - { - case ARM_SPI_MODE_INACTIVE: - DSPI_Enable(dspi->resource->base, false); - return ARM_DRIVER_OK; - - case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */ - DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Master); - memset((dspi->edmaRxRegToRxDataHandle), 0, sizeof(edma_handle_t)); - memset((dspi->edmaTxDataToIntermediaryHandle), 0, sizeof(edma_handle_t)); - memset((dspi->edmaIntermediaryToTxRegHandle), 0, sizeof(edma_handle_t)); - - EDMA_CreateHandle(dspi->edmaRxRegToRxDataHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel); - DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, dmaResource->rxDmaRequest); - DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel); - - EDMA_CreateHandle(dspi->edmaTxDataToIntermediaryHandle, dmaResource->txEdmaBase, - dmaResource->txEdmaChannel); - - EDMA_CreateHandle(dspi->edmaIntermediaryToTxRegHandle, dmaResource->masterLinkEdmaBase, - dmaResource->masterLinkChannel); - - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(dspi->resource->base)) - { - DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->masterLinkChannel, dmaResource->txDmaRequest); - DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->masterLinkChannel); - } - DSPI_MasterTransferCreateHandleEDMA(dspi->resource->base, &(dspi->handle->masterHandle), - KSDK_DSPI_MasterEdmaCallback, (void *)dspi->event, - (dspi->edmaRxRegToRxDataHandle), (dspi->edmaTxDataToIntermediaryHandle), - (dspi->edmaIntermediaryToTxRegHandle)); - - dspi->baudRate_Bps = arg; - dspi->isConfigured = true; - - break; - - case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */ - DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Slave); - memset(dspi->edmaRxRegToRxDataHandle, 0, sizeof(edma_handle_t)); - memset(dspi->edmaTxDataToTxRegHandle, 0, sizeof(edma_handle_t)); - - EDMA_CreateHandle(dspi->edmaTxDataToTxRegHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel); - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(dspi->resource->base)) - { - DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, dmaResource->txDmaRequest); - DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel); - } - - EDMA_CreateHandle(dspi->edmaRxRegToRxDataHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel); - DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, dmaResource->rxDmaRequest); - DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel); - - DSPI_SlaveTransferCreateHandleEDMA(dspi->resource->base, &(dspi->handle->slaveHandle), - KSDK_DSPI_SlaveEdmaCallback, (void *)dspi->event, - (dspi->edmaRxRegToRxDataHandle), (dspi->edmaTxDataToTxRegHandle)); - - dspi->isConfigured = true; - break; - - case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ - if (!DSPI_IsMaster(dspi->resource->base)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - if (0 == DSPI_MasterSetBaudRate(dspi->resource->base, kDSPI_Ctar0, arg, dspi->resource->GetFreq())) - { - return ARM_DRIVER_ERROR; - } - - dspi->baudRate_Bps = arg; - return ARM_DRIVER_OK; - - case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */ - if (!DSPI_IsMaster(dspi->resource->base)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return dspi->baudRate_Bps; - - case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */ - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ - if (DSPI_IsMaster(dspi->resource->base)) - { - DSPI_MasterTransferAbortEDMA(dspi->resource->base, &dspi->handle->masterHandle); - } - else - { - DSPI_SlaveTransferAbortEDMA(dspi->resource->base, &dspi->handle->slaveHandle); - } - return ARM_DRIVER_OK; - - default: - break; - } - - return DSPI_CommonControl(control, dspi->baudRate_Bps, dspi->resource, &dspi->isConfigured); -} - -ARM_SPI_STATUS DSPI_EdmaGetStatus(cmsis_dspi_edma_driver_state_t *dspi) -{ - ARM_SPI_STATUS stat; - uint32_t ksdk_dspi_status = DSPI_GetStatusFlags(dspi->resource->base); - - if (DSPI_IsMaster(dspi->resource->base)) - { - stat.busy = (kDSPI_Busy == dspi->handle->masterHandle.state) ? (1U) : (0U); - } - else - { - stat.busy = (kDSPI_Busy == dspi->handle->slaveHandle.state) ? (1U) : (0U); - } - - stat.data_lost = - ((ksdk_dspi_status & kDSPI_TxFifoUnderflowFlag) || (ksdk_dspi_status & kDSPI_RxFifoOverflowFlag)) ? (1U) : (0U); - stat.mode_fault = 0U; - - return stat; -} -#endif /* defined(FSL_FEATURE_SOC_EDMA_COUNT) */ - -#endif - -#if ((RTE_SPI0 && !RTE_SPI0_DMA_EN) || (RTE_SPI1 && !RTE_SPI1_DMA_EN) || (RTE_SPI2 && !RTE_SPI2_DMA_EN)) - -void KSDK_DSPI_MasterInterruptCallback(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_DSPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - /* User data is actually CMSIS driver callback. */ - if ((0U != event) && (userData)) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} -void KSDK_DSPI_SlaveInterruptCallback(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_Success == status) - { - event = ARM_SPI_EVENT_TRANSFER_COMPLETE; - } - - if (kStatus_DSPI_Error == status) - { - event = ARM_SPI_EVENT_DATA_LOST; - } - /* User data is actually CMSIS driver callback. */ - if ((0U != event) && (userData)) - { - ((ARM_SPI_SignalEvent_t)userData)(event); - } -} - -static int32_t DSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_dspi_interrupt_driver_state_t *dspi) -{ - if (dspi->isInitialized) - { - return ARM_DRIVER_OK; - } - dspi->event = cb_event; - dspi->isInitialized = true; - return ARM_DRIVER_OK; -} - -static int32_t DSPI_InterruptUninitialize(cmsis_dspi_interrupt_driver_state_t *dspi) -{ - dspi->isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t DSPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_dspi_interrupt_driver_state_t *dspi) -{ - switch (state) - { - case ARM_POWER_OFF: - if (dspi->isPowerOn) - { - DSPI_Deinit(dspi->resource->base); - dspi->isPowerOn = false; - dspi->isConfigured = false; - } - break; - - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_POWER_FULL: - if (!dspi->isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!dspi->isPowerOn) - { - CLOCK_EnableClock(s_dspiClock[dspi->resource->instance]); - dspi->isPowerOn = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - return ARM_DRIVER_OK; -} - -static int32_t DSPI_InterruptSend(const void *data, uint32_t num, cmsis_dspi_interrupt_driver_state_t *dspi) -{ - int32_t ret; - status_t status; - dspi_transfer_t xfer; - - xfer.rxData = NULL; - xfer.txData = (uint8_t *)data; - xfer.dataSize = num; - - if (DSPI_IsMaster(dspi->resource->base)) - { -#if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL)) - if (0U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI0_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI0 PCS select configuration */ -#if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL)) - if (1U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI1_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI1 PCS select configuration */ -#if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL)) - if (2U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI2_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI2 PCS select configuration */ - } - else - { - /* DSPI slave use Ctar0 setting and slave can only use PCS0. */ - xfer.configFlags = kDSPI_SlaveCtar0; - } - - if (DSPI_IsMaster(dspi->resource->base)) - { - status = DSPI_MasterTransferNonBlocking(dspi->resource->base, &dspi->handle->masterHandle, &xfer); - } - else - { - status = DSPI_SlaveTransferNonBlocking(dspi->resource->base, &dspi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_DSPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t DSPI_InterruptReceive(void *data, uint32_t num, cmsis_dspi_interrupt_driver_state_t *dspi) -{ - int32_t ret; - status_t status; - dspi_transfer_t xfer; - - xfer.txData = NULL; - xfer.rxData = (uint8_t *)data; - xfer.dataSize = num; - - if (DSPI_IsMaster(dspi->resource->base)) - { -#if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL)) - if (0U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI0_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI0 PCS select configuration */ -#if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL)) - if (1U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI1_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI1 PCS select configuration */ -#if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL)) - if (2U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI2_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI2 PCS select configuration */ - } - else - { - /* DSPI slave use Ctar0 setting and slave can only use PCS0. */ - xfer.configFlags = kDSPI_SlaveCtar0; - } - - if (DSPI_IsMaster(dspi->resource->base)) - { - status = DSPI_MasterTransferNonBlocking(dspi->resource->base, &dspi->handle->masterHandle, &xfer); - } - else - { - status = DSPI_SlaveTransferNonBlocking(dspi->resource->base, &dspi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_DSPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t DSPI_InterruptTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_dspi_interrupt_driver_state_t *dspi) -{ - int32_t ret; - status_t status; - dspi_transfer_t xfer; - - xfer.txData = (uint8_t *)data_out; - xfer.rxData = (uint8_t *)data_in; - xfer.dataSize = num; - - if (DSPI_IsMaster(dspi->resource->base)) - { -#if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL)) - if (0U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI0_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI0 PCS select configuration */ -#if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL)) - if (1U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI1_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI1 PCS select configuration */ -#if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL)) - if (2U == dspi->resource->instance) - { - xfer.configFlags = kDSPI_MasterCtar0 | RTE_SPI2_MASTER_PCS_PIN_SEL; - } -#endif /* DSPI2 PCS select configuration */ - } - else - { - /* DSPI slave use Ctar0 setting and slave can only use PCS0. */ - xfer.configFlags = kDSPI_SlaveCtar0; - } - - if (DSPI_IsMaster(dspi->resource->base)) - { - status = DSPI_MasterTransferNonBlocking(dspi->resource->base, &dspi->handle->masterHandle, &xfer); - } - else - { - status = DSPI_SlaveTransferNonBlocking(dspi->resource->base, &dspi->handle->slaveHandle, &xfer); - } - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_DSPI_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -static uint32_t DSPI_InterruptGetCount(cmsis_dspi_interrupt_driver_state_t *dspi) -{ - if (DSPI_IsMaster(dspi->resource->base)) - { - return dspi->handle->masterHandle.totalByteCount - dspi->handle->masterHandle.remainingReceiveByteCount; - } - else - { - return dspi->handle->slaveHandle.totalByteCount - dspi->handle->slaveHandle.remainingReceiveByteCount; - } -} - -static int32_t DSPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_dspi_interrupt_driver_state_t *dspi) -{ - if (!dspi->isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - switch (control & ARM_SPI_CONTROL_Msk) - { - case ARM_SPI_MODE_INACTIVE: - DSPI_Enable(dspi->resource->base, false); - return ARM_DRIVER_OK; - - case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */ - DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Master); - DSPI_MasterTransferCreateHandle(dspi->resource->base, &dspi->handle->masterHandle, - KSDK_DSPI_MasterInterruptCallback, (void *)dspi->event); - dspi->baudRate_Bps = arg; - dspi->isConfigured = true; - break; - - case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */ - DSPI_SetMasterSlaveMode(dspi->resource->base, kDSPI_Slave); - DSPI_SlaveTransferCreateHandle(dspi->resource->base, &dspi->handle->slaveHandle, - KSDK_DSPI_SlaveInterruptCallback, (void *)dspi->event); - - dspi->isConfigured = true; - break; - - case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */ - if (!DSPI_IsMaster(dspi->resource->base)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return dspi->baudRate_Bps; - - case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ - if (!DSPI_IsMaster(dspi->resource->base)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - if (0 == DSPI_MasterSetBaudRate(dspi->resource->base, kDSPI_Ctar0, arg, dspi->resource->GetFreq())) - { - return ARM_DRIVER_ERROR; - } - - dspi->baudRate_Bps = arg; - return ARM_DRIVER_OK; - - case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */ - return ARM_DRIVER_ERROR_UNSUPPORTED; - - case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ - if (DSPI_IsMaster(dspi->resource->base)) - { - DSPI_MasterTransferAbort(dspi->resource->base, &dspi->handle->masterHandle); - } - else - { - DSPI_SlaveTransferAbort(dspi->resource->base, &dspi->handle->slaveHandle); - } - return ARM_DRIVER_OK; - default: - break; - } - return DSPI_CommonControl(control, dspi->baudRate_Bps, dspi->resource, &dspi->isConfigured); -} - -ARM_SPI_STATUS DSPI_InterruptGetStatus(cmsis_dspi_interrupt_driver_state_t *dspi) -{ - ARM_SPI_STATUS stat; - uint32_t ksdk_dspi_status = DSPI_GetStatusFlags(dspi->resource->base); - - if (DSPI_IsMaster(dspi->resource->base)) - { - stat.busy = ((dspi->handle->masterHandle.remainingSendByteCount > 0) || - (dspi->handle->masterHandle.remainingReceiveByteCount > 0)) ? - (1U) : - (0U); - } - else - { - stat.busy = ((dspi->handle->slaveHandle.remainingSendByteCount > 0) || - (dspi->handle->slaveHandle.remainingReceiveByteCount > 0)) ? - (1U) : - (0U); - } - stat.data_lost = - ((ksdk_dspi_status & kDSPI_TxFifoUnderflowFlag) || (ksdk_dspi_status & kDSPI_RxFifoOverflowFlag)) ? (1U) : (0U); - stat.mode_fault = 0U; - - return stat; -} - -#endif - -#if defined(DSPI0) && RTE_SPI0 - -extern uint32_t DSPI0_GetFreq(void); -extern void DSPI0_InitPins(void); -extern void DSPI0_DeinitPins(void); - -cmsis_dspi_resource_t DSPI0_Resource = {DSPI0, 0, DSPI0_GetFreq}; - -#if RTE_SPI0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -cmsis_dspi_edma_resource_t DSPI0_EdmaResource = { - RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, RTE_SPI0_DMA_TX_DMAMUX_BASE, RTE_SPI0_DMA_TX_PERI_SEL, - - RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH, RTE_SPI0_DMA_RX_DMAMUX_BASE, RTE_SPI0_DMA_RX_PERI_SEL, - - RTE_SPI0_DMA_LINK_DMA_BASE, RTE_SPI0_DMA_LINK_CH}; - -cmsis_dspi_edma_handle_t DSPI0_EdmaHandle; - -edma_handle_t DSPI0_EdmaRxRegToRxDataHandle; -edma_handle_t DSPI0_EedmaTxDataToIntermediaryHandle; -edma_handle_t DSPI0_EedmaIntermediaryToTxRegHandle; -edma_handle_t DSPI0_EedmaTxDataToTxRegHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("dspi0_edma_driver_state") -cmsis_dspi_edma_driver_state_t DSPI0_EdmaDriverState = { -#else -cmsis_dspi_edma_driver_state_t DSPI0_EdmaDriverState = { -#endif - &DSPI0_Resource, - &DSPI0_EdmaResource, - &DSPI0_EdmaHandle, - &DSPI0_EdmaRxRegToRxDataHandle, - &DSPI0_EedmaTxDataToIntermediaryHandle, - &DSPI0_EedmaIntermediaryToTxRegHandle, - &DSPI0_EedmaTxDataToTxRegHandle, -}; - -static int32_t DSPI0_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - DSPI0_InitPins(); - return DSPI_EdmaInitialize(cb_event, &DSPI0_EdmaDriverState); -} - -static int32_t DSPI0_EdmaUninitialize(void) -{ - DSPI0_DeinitPins(); - return DSPI_EdmaUninitialize(&DSPI0_EdmaDriverState); -} - -static int32_t DSPI0_EdmaPowerControl(ARM_POWER_STATE state) -{ - return DSPI_EdmaPowerControl(state, &DSPI0_EdmaDriverState); -} - -static int32_t DSPI0_EdmaSend(const void *data, uint32_t num) -{ - return DSPI_EdmaSend(data, num, &DSPI0_EdmaDriverState); -} - -static int32_t DSPI0_EdmaReceive(void *data, uint32_t num) -{ - return DSPI_EdmaReceive(data, num, &DSPI0_EdmaDriverState); -} - -static int32_t DSPI0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return DSPI_EdmaTransfer(data_out, data_in, num, &DSPI0_EdmaDriverState); -} - -static uint32_t DSPI0_EdmaGetCount(void) -{ - return DSPI_EdmaGetCount(&DSPI0_EdmaDriverState); -} - -static int32_t DSPI0_EdmaControl(uint32_t control, uint32_t arg) -{ - return DSPI_EdmaControl(control, arg, &DSPI0_EdmaDriverState); -} - -static ARM_SPI_STATUS DSPI0_EdmaGetStatus(void) -{ - return DSPI_EdmaGetStatus(&DSPI0_EdmaDriverState); -} - -#endif - -#else -cmsis_dspi_handle_t DSPI0_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("dspi0_interrupt_driver_state") -cmsis_dspi_interrupt_driver_state_t DSPI0_InterruptDriverState = { -#else -cmsis_dspi_interrupt_driver_state_t DSPI0_InterruptDriverState = { -#endif - &DSPI0_Resource, &DSPI0_Handle, -}; - -static int32_t DSPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - DSPI0_InitPins(); - return DSPI_InterruptInitialize(cb_event, &DSPI0_InterruptDriverState); -} - -static int32_t DSPI0_InterruptUninitialize(void) -{ - DSPI0_DeinitPins(); - return DSPI_InterruptUninitialize(&DSPI0_InterruptDriverState); -} - -static int32_t DSPI0_InterruptPowerControl(ARM_POWER_STATE state) -{ - return DSPI_InterruptPowerControl(state, &DSPI0_InterruptDriverState); -} - -static int32_t DSPI0_InterruptSend(const void *data, uint32_t num) -{ - return DSPI_InterruptSend(data, num, &DSPI0_InterruptDriverState); -} - -static int32_t DSPI0_InterruptReceive(void *data, uint32_t num) -{ - return DSPI_InterruptReceive(data, num, &DSPI0_InterruptDriverState); -} - -static int32_t DSPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return DSPI_InterruptTransfer(data_out, data_in, num, &DSPI0_InterruptDriverState); -} - -static uint32_t DSPI0_InterruptGetCount(void) -{ - return DSPI_InterruptGetCount(&DSPI0_InterruptDriverState); -} - -static int32_t DSPI0_InterruptControl(uint32_t control, uint32_t arg) -{ - return DSPI_InterruptControl(control, arg, &DSPI0_InterruptDriverState); -} - -static ARM_SPI_STATUS DSPI0_InterruptGetStatus(void) -{ - return DSPI_InterruptGetStatus(&DSPI0_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI0 = {DSPIx_GetVersion, DSPIx_GetCapabilities, -#if RTE_SPI0_DMA_EN - DSPI0_EdmaInitialize, DSPI0_EdmaUninitialize, DSPI0_EdmaPowerControl, DSPI0_EdmaSend, - DSPI0_EdmaReceive, DSPI0_EdmaTransfer, DSPI0_EdmaGetCount, DSPI0_EdmaControl, - DSPI0_EdmaGetStatus -#else - DSPI0_InterruptInitialize, DSPI0_InterruptUninitialize, DSPI0_InterruptPowerControl, - DSPI0_InterruptSend, DSPI0_InterruptReceive, DSPI0_InterruptTransfer, - DSPI0_InterruptGetCount, DSPI0_InterruptControl, DSPI0_InterruptGetStatus -#endif -}; - -#endif /* DSPI0 */ - -#if defined(DSPI1) && RTE_SPI1 - -extern uint32_t DSPI1_GetFreq(void); -extern void DSPI1_InitPins(void); -extern void DSPI1_DeinitPins(void); - -cmsis_dspi_resource_t DSPI1_Resource = {DSPI1, 1, DSPI1_GetFreq}; - -#if RTE_SPI1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -cmsis_dspi_edma_resource_t DSPI1_EdmaResource = { - RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_TX_DMAMUX_BASE, RTE_SPI1_DMA_TX_PERI_SEL, - - RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, RTE_SPI1_DMA_RX_DMAMUX_BASE, RTE_SPI1_DMA_RX_PERI_SEL, - - RTE_SPI1_DMA_LINK_DMA_BASE, RTE_SPI1_DMA_LINK_CH}; - -cmsis_dspi_edma_handle_t DSPI1_EdmaHandle; - -edma_handle_t DSPI1_EdmaRxRegToRxDataHandle; -edma_handle_t DSPI1_EedmaTxDataToIntermediaryHandle; -edma_handle_t DSPI1_EedmaIntermediaryToTxRegHandle; -edma_handle_t DSPI1_EedmaTxDataToTxRegHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("dspi1_edma_driver_state") -cmsis_dspi_edma_driver_state_t DSPI1_EdmaDriverState = { -#else -cmsis_dspi_edma_driver_state_t DSPI1_EdmaDriverState = { -#endif - &DSPI1_Resource, - &DSPI1_EdmaResource, - &DSPI1_EdmaHandle, - &DSPI1_EdmaRxRegToRxDataHandle, - &DSPI1_EedmaTxDataToIntermediaryHandle, - &DSPI1_EedmaIntermediaryToTxRegHandle, - &DSPI1_EedmaTxDataToTxRegHandle, -}; - -static int32_t DSPI1_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - DSPI1_InitPins(); - return DSPI_EdmaInitialize(cb_event, &DSPI1_EdmaDriverState); -} - -static int32_t DSPI1_EdmaUninitialize(void) -{ - DSPI1_DeinitPins(); - return DSPI_EdmaUninitialize(&DSPI1_EdmaDriverState); -} - -static int32_t DSPI1_EdmaPowerControl(ARM_POWER_STATE state) -{ - return DSPI_EdmaPowerControl(state, &DSPI1_EdmaDriverState); -} - -static int32_t DSPI1_EdmaSend(const void *data, uint32_t num) -{ - return DSPI_EdmaSend(data, num, &DSPI1_EdmaDriverState); -} - -static int32_t DSPI1_EdmaReceive(void *data, uint32_t num) -{ - return DSPI_EdmaReceive(data, num, &DSPI1_EdmaDriverState); -} - -static int32_t DSPI1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return DSPI_EdmaTransfer(data_out, data_in, num, &DSPI1_EdmaDriverState); -} - -static uint32_t DSPI1_EdmaGetCount(void) -{ - return DSPI_EdmaGetCount(&DSPI1_EdmaDriverState); -} - -static int32_t DSPI1_EdmaControl(uint32_t control, uint32_t arg) -{ - return DSPI_EdmaControl(control, arg, &DSPI1_EdmaDriverState); -} - -static ARM_SPI_STATUS DSPI1_EdmaGetStatus(void) -{ - return DSPI_EdmaGetStatus(&DSPI1_EdmaDriverState); -} - -#endif - -#else - -cmsis_dspi_handle_t DSPI1_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("dspi1_interrupt_driver_state") -cmsis_dspi_interrupt_driver_state_t DSPI1_InterruptDriverState = { -#else -cmsis_dspi_interrupt_driver_state_t DSPI1_InterruptDriverState = { -#endif - &DSPI1_Resource, &DSPI1_Handle, -}; - -static int32_t DSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - DSPI1_InitPins(); - return DSPI_InterruptInitialize(cb_event, &DSPI1_InterruptDriverState); -} - -static int32_t DSPI1_InterruptUninitialize(void) -{ - DSPI1_DeinitPins(); - return DSPI_InterruptUninitialize(&DSPI1_InterruptDriverState); -} - -static int32_t DSPI1_InterruptPowerControl(ARM_POWER_STATE state) -{ - return DSPI_InterruptPowerControl(state, &DSPI1_InterruptDriverState); -} - -static int32_t DSPI1_InterruptSend(const void *data, uint32_t num) -{ - return DSPI_InterruptSend(data, num, &DSPI1_InterruptDriverState); -} - -static int32_t DSPI1_InterruptReceive(void *data, uint32_t num) -{ - return DSPI_InterruptReceive(data, num, &DSPI1_InterruptDriverState); -} - -static int32_t DSPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return DSPI_InterruptTransfer(data_out, data_in, num, &DSPI1_InterruptDriverState); -} - -static uint32_t DSPI1_InterruptGetCount(void) -{ - return DSPI_InterruptGetCount(&DSPI1_InterruptDriverState); -} - -static int32_t DSPI1_InterruptControl(uint32_t control, uint32_t arg) -{ - return DSPI_InterruptControl(control, arg, &DSPI1_InterruptDriverState); -} - -static ARM_SPI_STATUS DSPI1_InterruptGetStatus(void) -{ - return DSPI_InterruptGetStatus(&DSPI1_InterruptDriverState); -} - -#endif - -ARM_DRIVER_SPI Driver_SPI1 = {DSPIx_GetVersion, DSPIx_GetCapabilities, -#if RTE_SPI1_DMA_EN - DSPI1_EdmaInitialize, DSPI1_EdmaUninitialize, DSPI1_EdmaPowerControl, DSPI1_EdmaSend, - DSPI1_EdmaReceive, DSPI1_EdmaTransfer, DSPI1_EdmaGetCount, DSPI1_EdmaControl, - DSPI1_EdmaGetStatus -#else - DSPI1_InterruptInitialize, DSPI1_InterruptUninitialize, DSPI1_InterruptPowerControl, - DSPI1_InterruptSend, DSPI1_InterruptReceive, DSPI1_InterruptTransfer, - DSPI1_InterruptGetCount, DSPI1_InterruptControl, DSPI1_InterruptGetStatus -#endif -}; - -#endif /* DSPI1 */ - -#if defined(DSPI2) && RTE_SPI2 - -extern uint32_t DSPI2_GetFreq(void); -extern void DSPI2_InitPins(void); -extern void DSPI2_DeinitPins(void); - -cmsis_dspi_resource_t DSPI2_Resource = {DSPI2, 2, DSPI2_GetFreq}; - -#if RTE_SPI2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -cmsis_dspi_edma_resource_t DSPI2_EdmaResource = { - RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_TX_DMAMUX_BASE, RTE_SPI2_DMA_TX_PERI_SEL, - - RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, RTE_SPI2_DMA_RX_DMAMUX_BASE, RTE_SPI2_DMA_RX_PERI_SEL, - - RTE_SPI2_DMA_LINK_DMA_BASE, RTE_SPI2_DMA_LINK_CH}; - -cmsis_dspi_edma_handle_t DSPI2_EdmaHandle; - -edma_handle_t DSPI2_EdmaRxRegToRxDataHandle; -edma_handle_t DSPI2_EedmaTxDataToIntermediaryHandle; -edma_handle_t DSPI2_EedmaIntermediaryToTxRegHandle; -edma_handle_t DSPI2_EedmaTxDataToTxRegHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("dspi2_edma_driver_state") -cmsis_dspi_edma_driver_state_t DSPI2_EdmaDriverState = { -#else -cmsis_dspi_edma_driver_state_t DSPI2_EdmaDriverState = { -#endif - &DSPI2_Resource, - &DSPI2_EdmaResource, - &DSPI2_EdmaHandle, - &DSPI2_EdmaRxRegToRxDataHandle, - &DSPI2_EedmaTxDataToIntermediaryHandle, - &DSPI2_EedmaIntermediaryToTxRegHandle, - &DSPI2_EedmaTxDataToTxRegHandle, -}; - -static int32_t DSPI2_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - DSPI2_InitPins(); - return DSPI_EdmaInitialize(cb_event, &DSPI2_EdmaDriverState); -} - -static int32_t DSPI2_EdmaUninitialize(void) -{ - DSPI2_DeinitPins(); - return DSPI_EdmaUninitialize(&DSPI2_EdmaDriverState); -} - -static int32_t DSPI2_EdmaPowerControl(ARM_POWER_STATE state) -{ - return DSPI_EdmaPowerControl(state, &DSPI2_EdmaDriverState); -} - -static int32_t DSPI2_EdmaSend(const void *data, uint32_t num) -{ - return DSPI_EdmaSend(data, num, &DSPI2_EdmaDriverState); -} - -static int32_t DSPI2_EdmaReceive(void *data, uint32_t num) -{ - return DSPI_EdmaReceive(data, num, &DSPI2_EdmaDriverState); -} - -static int32_t DSPI2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return DSPI_EdmaTransfer(data_out, data_in, num, &DSPI2_EdmaDriverState); -} - -static uint32_t DSPI2_EdmaGetCount(void) -{ - return DSPI_EdmaGetCount(&DSPI2_EdmaDriverState); -} - -static int32_t DSPI2_EdmaControl(uint32_t control, uint32_t arg) -{ - return DSPI_EdmaControl(control, arg, &DSPI2_EdmaDriverState); -} - -static ARM_SPI_STATUS DSPI2_EdmaGetStatus(void) -{ - return DSPI_EdmaGetStatus(&DSPI2_EdmaDriverState); -} - -#endif - -#else - -cmsis_dspi_handle_t DSPI2_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("dspi2_interrupt_driver_state") -cmsis_dspi_interrupt_driver_state_t DSPI2_InterruptDriverState = { -#else -cmsis_dspi_interrupt_driver_state_t DSPI2_InterruptDriverState = { -#endif - &DSPI2_Resource, &DSPI2_Handle, -}; - -static int32_t DSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) -{ - DSPI2_InitPins(); - return DSPI_InterruptInitialize(cb_event, &DSPI2_InterruptDriverState); -} - -static int32_t DSPI2_InterruptUninitialize(void) -{ - DSPI2_DeinitPins(); - return DSPI_InterruptUninitialize(&DSPI2_InterruptDriverState); -} - -static int32_t DSPI2_InterruptPowerControl(ARM_POWER_STATE state) -{ - return DSPI_InterruptPowerControl(state, &DSPI2_InterruptDriverState); -} - -static int32_t DSPI2_InterruptSend(const void *data, uint32_t num) -{ - return DSPI_InterruptSend(data, num, &DSPI2_InterruptDriverState); -} - -static int32_t DSPI2_InterruptReceive(void *data, uint32_t num) -{ - return DSPI_InterruptReceive(data, num, &DSPI2_InterruptDriverState); -} - -static int32_t DSPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return DSPI_InterruptTransfer(data_out, data_in, num, &DSPI2_InterruptDriverState); -} - -static uint32_t DSPI2_InterruptGetCount(void) -{ - return DSPI_InterruptGetCount(&DSPI2_InterruptDriverState); -} - -static int32_t DSPI2_InterruptControl(uint32_t control, uint32_t arg) -{ - return DSPI_InterruptControl(control, arg, &DSPI2_InterruptDriverState); -} - -static ARM_SPI_STATUS DSPI2_InterruptGetStatus(void) -{ - return DSPI_InterruptGetStatus(&DSPI2_InterruptDriverState); -} -#endif - -ARM_DRIVER_SPI Driver_SPI2 = {DSPIx_GetVersion, DSPIx_GetCapabilities, -#if RTE_SPI2_DMA_EN - DSPI2_EdmaInitialize, DSPI2_EdmaUninitialize, DSPI2_EdmaPowerControl, DSPI2_EdmaSend, - DSPI2_EdmaReceive, DSPI2_EdmaTransfer, DSPI2_EdmaGetCount, DSPI2_EdmaControl, - DSPI2_EdmaGetStatus -#else - DSPI2_InterruptInitialize, DSPI2_InterruptUninitialize, DSPI2_InterruptPowerControl, - DSPI2_InterruptSend, DSPI2_InterruptReceive, DSPI2_InterruptTransfer, - DSPI2_InterruptGetCount, DSPI2_InterruptControl, DSPI2_InterruptGetStatus -#endif -}; - -#endif /* DSPI2 */ diff --git a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.h b/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.h deleted file mode 100644 index ff90e3035..000000000 --- a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_dspi_cmsis.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DSPI_CMSISI_H_ -#define _FSL_DSPI_CMSISI_H_ - -#include "fsl_common.h" -#include "RTE_Device.h" -#include "Driver_SPI.h" -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -#include "fsl_dspi_edma.h" -#include "fsl_dmamux.h" -#include "fsl_edma.h" -#endif - -#if defined(DSPI0) -extern ARM_DRIVER_SPI Driver_SPI0; -#endif /* DSPI0 */ - -#if defined(DSPI1) -extern ARM_DRIVER_SPI Driver_SPI1; -#endif /* DSPI1 */ - -#if defined(DSPI2) -extern ARM_DRIVER_SPI Driver_SPI2; -#endif /* DSPI2 */ - -#endif diff --git a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.c b/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.c deleted file mode 100644 index ea411db87..000000000 --- a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.c +++ /dev/null @@ -1,1996 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_cmsis.h" - -#if ((RTE_I2C0 && defined(I2C0)) || (RTE_I2C1 && defined(I2C1)) || (RTE_I2C2 && defined(I2C2)) || \ - (RTE_I2C3 && defined(I2C3))) - -#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) - -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef const struct _cmsis_i2c_resource -{ - I2C_Type *base; /*!< I2C peripheral base address. */ - uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ - -} cmsis_i2c_resource_t; - -typedef union _cmsis_i2c_handle -{ - i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */ - i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */ -} cmsis_i2c_handle_t; - -typedef struct _cmsis_i2c_interrupt_driver_state -{ - cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */ - cmsis_i2c_handle_t *handle; - ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */ - bool isInitialized; /*!< Is initialized or not. */ -} cmsis_i2c_interrupt_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -typedef const struct _cmsis_i2c_dma_resource -{ - DMA_Type *i2cDmaBase; /*!< DMA peripheral base address for i2c. */ - uint32_t i2cDmaChannel; /*!< DMA channel for i2c. */ - DMAMUX_Type *i2cDmamuxBase; /*!< DMAMUX peripheral base address for i2c. */ - uint16_t i2cDmaRequest; /*!< i2c DMA request source. */ -} cmsis_i2c_dma_resource_t; - -typedef struct _cmsis_i2c_dma_driver_state -{ - cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */ - cmsis_i2c_dma_resource_t *dmaResource; /*!< i2c DMA resource. */ - i2c_master_dma_handle_t *master_dma_handle; /*!< i2c DMA transfer handle. */ - dma_handle_t *dmaHandle; /*!< DMA i2c handle. */ - bool isInitialized; /*!< Is initialized or not. */ -} cmsis_i2c_dma_driver_state_t; -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -typedef const struct _cmsis_i2c_edma_resource -{ - DMA_Type *i2cEdmaBase; /*!< EDMA peripheral base address for i2c. */ - uint32_t i2cEdmaChannel; /*!< EDMA channel for i2c. */ - DMAMUX_Type *i2cDmamuxBase; /*!< DMAMUX peripheral base address for i2c. */ - uint16_t i2cDmaRequest; /*!< i2c EDMA request source. */ -} cmsis_i2c_edma_resource_t; - -typedef struct _cmsis_i2c_edma_driver_state -{ - cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */ - cmsis_i2c_edma_resource_t *edmaResource; /*!< i2c EDMA resource. */ - i2c_master_edma_handle_t *master_edma_handle; /*!< i2c EDMA transfer handle. */ - edma_handle_t *edmaHandle; /*!< EDMA i2c handle. */ - bool isInitialized; /*!< Is initialized or not. */ -} cmsis_i2c_edma_driver_state_t; -#endif /* FSL_FEATURE_SOC_EDMA_COUNT */ - -static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION}; -static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = { - 0, /*< supports 10-bit addressing */ -}; - -static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; -extern uint32_t I2C_GetInstance(I2C_Type *base); - -static ARM_DRIVER_VERSION I2Cx_GetVersion(void) -{ - return s_i2cDriverVersion; -} - -static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void) -{ - return s_i2cDriverCapabilities; -} - -#endif - -#if (RTE_I2C0_DMA_EN || RTE_I2C1_DMA_EN || RTE_I2C2_DMA_EN || RTE_I2C3_DMA_EN) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -void KSDK_I2C_MASTER_DmaCallback(I2C_Type *base, i2c_master_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event; - - if (status == kStatus_Success) /* Occurs after Master Transmit/Receive operation has finished. */ - { - event = ARM_I2C_EVENT_TRANSFER_DONE; - } - - if (status == kStatus_I2C_Addr_Nak) - { - event = ARM_I2C_EVENT_ADDRESS_NACK; - } - - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} - -static int32_t I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_dma_driver_state_t *i2c) -{ - if (!(i2c->isInitialized)) - { - /* Configure DMAMUX channel */ - DMAMUX_SetSource(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmaChannel, - (uint8_t)i2c->dmaResource->i2cDmaRequest); - DMAMUX_EnableChannel(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmaChannel); - /* Creat dmahandle */ - DMA_CreateHandle(i2c->dmaHandle, i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); - /* Create master_dma_handle. */ - I2C_MasterTransferCreateHandleDMA(i2c->resource->base, i2c->master_dma_handle, KSDK_I2C_MASTER_DmaCallback, - (void *)cb_event, i2c->dmaHandle); - i2c->isInitialized = true; - } - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t *i2c) -{ - i2c->isInitialized = false; - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_DmaTransmit( - uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_dma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Write; /* Transfer direction.*/ - masterXfer.subaddress = 0; /* Sub address */ - masterXfer.subaddressSize = 0; /* Size of command buffer.*/ - masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/ - masterXfer.dataSize = num; /* Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ - - if (i2c->resource->base->S & 0x20) - { - masterXfer.flags |= kI2C_TransferRepeatedStartFlag; - } - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - case kStatus_I2C_Timeout: - ret = ARM_DRIVER_ERROR_TIMEOUT; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_DmaReceive( - uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_dma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Read; /* Transfer direction.*/ - masterXfer.subaddress = 0; /* Sub address */ - masterXfer.subaddressSize = 0; /* Size of command buffer.*/ - masterXfer.data = data; /* Transfer buffer.*/ - masterXfer.dataSize = num; /* Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ - - if (i2c->resource->base->S & 0x20) - { - masterXfer.flags |= kI2C_TransferRepeatedStartFlag; - } - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - case kStatus_I2C_Timeout: - ret = ARM_DRIVER_ERROR_TIMEOUT; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t *i2c) -{ - size_t cnt; /* The number of currently transferred data bytes */ - - I2C_MasterTransferGetCountDMA(i2c->resource->base, i2c->master_dma_handle, &cnt); - return cnt; -} - -int32_t I2C_Master_DmaControl(uint32_t control, uint32_t arg, cmsis_i2c_dma_driver_state_t *i2c) -{ - uint32_t baudRate_Bps; - volatile uint8_t dummy = 0; - - /* Add this to avoid warning. */ - dummy++; - - switch (control) - { - /* Not supported */ - case ARM_I2C_OWN_ADDRESS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Set Bus Speed; arg = bus speed */ - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - baudRate_Bps = 100000; - break; - - case ARM_I2C_BUS_SPEED_FAST: - baudRate_Bps = 400000; - break; - - case ARM_I2C_BUS_SPEED_FAST_PLUS: - baudRate_Bps = 1000000; - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); - - return ARM_DRIVER_OK; - - /* Not supported */ - case ARM_I2C_BUS_CLEAR: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Aborts the data transfer when Master for Transmit or Receive */ - case ARM_I2C_ABORT_TRANSFER: - if (i2c->resource->base->C1 & I2C_C1_MST_MASK) - { - /* Disable dma */ - I2C_MasterTransferAbortDMA(i2c->resource->base, i2c->master_dma_handle); - /* If master receive */ - if (i2c->master_dma_handle->transfer.direction == kI2C_Read) - { - i2c->resource->base->C1 |= I2C_C1_TXAK_MASK; - while (!(i2c->resource->base->S & I2C_S_TCF_MASK)) - { - } - i2c->resource->base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - dummy = i2c->resource->base->D; - } - /* If master transmit */ - else - { - while (!(i2c->resource->base->S & I2C_S_TCF_MASK)) - { - } - i2c->resource->base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - } - - i2c->master_dma_handle->transferSize = 0; - i2c->master_dma_handle->transfer.data = NULL; - i2c->master_dma_handle->transfer.dataSize = 0; - } - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t I2C_Master_DmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_dma_driver_state_t *i2c) -{ - switch (state) - { - /* Terminates any pending data transfers, disable i2c moduole and i2c clock and related dma */ - case ARM_POWER_OFF: - I2C_Master_DmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); - I2C_MasterDeinit(i2c->resource->base); - DMAMUX_DisableChannel(i2c->dmaResource->i2cDmamuxBase, i2c->dmaResource->i2cDmaChannel); - return ARM_DRIVER_OK; - - /* Not supported */ - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Enable i2c moduole and i2c clock */ - case ARM_POWER_FULL: - CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(i2c->resource->base)]); - i2c->resource->base->C1 = I2C_C1_IICEN(1); - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -ARM_I2C_STATUS I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t *i2c) -{ - ARM_I2C_STATUS stat = {0}; - uint32_t ksdk_i2c_master_status = I2C_MasterGetStatusFlags(i2c->resource->base); - - stat.busy = !(!(ksdk_i2c_master_status & kI2C_BusBusyFlag)); /* Busy flag.*/ - - stat.mode = 1; /* Mode: 0=Slave, 1=Master.*/ - - stat.direction = - !(!(ksdk_i2c_master_status & kI2C_TransferDirectionFlag)); /* Direction: 0=Transmitter, 1=Receiver.*/ - - stat.arbitration_lost = - !(!(ksdk_i2c_master_status & - kI2C_ArbitrationLostFlag)); /* Master lost arbitration (cleared on start of next Master operation)*/ - - return stat; -} -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -void KSDK_I2C_MASTER_EdmaCallback(I2C_Type *base, i2c_master_edma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event; - - /* Occurs after Master Transmit/Receive operation has finished. */ - if (status == kStatus_Success) - { - event = ARM_I2C_EVENT_TRANSFER_DONE; - } - - if (status == kStatus_I2C_Addr_Nak) - { - event = ARM_I2C_EVENT_ADDRESS_NACK; - } - - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} - -static int32_t I2C_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_edma_driver_state_t *i2c) -{ - if (!(i2c->isInitialized)) - { - /* Configure DMAMUX channel */ - DMAMUX_SetSource(i2c->edmaResource->i2cDmamuxBase, i2c->edmaResource->i2cEdmaChannel, - (uint8_t)i2c->edmaResource->i2cDmaRequest); - DMAMUX_EnableChannel(i2c->edmaResource->i2cDmamuxBase, i2c->edmaResource->i2cEdmaChannel); - /* Creat edmahandle */ - EDMA_CreateHandle(i2c->edmaHandle, i2c->edmaResource->i2cEdmaBase, i2c->edmaResource->i2cEdmaChannel); - /* Create master_edma_handle. */ - I2C_MasterCreateEDMAHandle(i2c->resource->base, i2c->master_edma_handle, KSDK_I2C_MASTER_EdmaCallback, - (void *)cb_event, i2c->edmaHandle); - i2c->isInitialized = true; - } - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_EdmaUninitialize(cmsis_i2c_edma_driver_state_t *i2c) -{ - i2c->isInitialized = false; - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_EdmaTransmit( - uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_edma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_edma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Write; /* Transfer direction.*/ - masterXfer.subaddress = 0; /* Sub address */ - masterXfer.subaddressSize = 0; /* Size of command buffer.*/ - masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/ - masterXfer.dataSize = num; /* Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ - - if (i2c->resource->base->S & 0x20) - { - masterXfer.flags |= kI2C_TransferRepeatedStartFlag; - } - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferEDMA(i2c->resource->base, i2c->master_edma_handle, &masterXfer); - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - case kStatus_I2C_Timeout: - ret = ARM_DRIVER_ERROR_TIMEOUT; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_EdmaReceive( - uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_edma_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->master_edma_handle->state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - masterXfer.slaveAddress = addr; /* 7-bit slave address.*/ - masterXfer.direction = kI2C_Read; /* Transfer direction.*/ - masterXfer.subaddress = 0; /* Sub address */ - masterXfer.subaddressSize = 0; /* Size of command buffer.*/ - masterXfer.data = data; /* Transfer buffer.*/ - masterXfer.dataSize = num; /* Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ - - if (i2c->resource->base->S & 0x20) - { - masterXfer.flags |= kI2C_TransferRepeatedStartFlag; - } - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferEDMA(i2c->resource->base, i2c->master_edma_handle, &masterXfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - - case kStatus_I2C_Timeout: - ret = ARM_DRIVER_ERROR_TIMEOUT; - break; - - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_EdmaGetDataCount(cmsis_i2c_edma_driver_state_t *i2c) -{ - size_t cnt; /* The number of currently transferred data bytes */ - - I2C_MasterTransferGetCountEDMA(i2c->resource->base, i2c->master_edma_handle, &cnt); - - return cnt; -} - -int32_t I2C_Master_EdmaControl(uint32_t control, uint32_t arg, cmsis_i2c_edma_driver_state_t *i2c) -{ - uint32_t baudRate_Bps; - volatile uint8_t dummy = 0; - - /* Add this to avoid warning. */ - dummy++; - - switch (control) - { - /* Not supported */ - case ARM_I2C_OWN_ADDRESS: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Set Bus Speed; arg = bus speed */ - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - baudRate_Bps = 100000; - break; - - case ARM_I2C_BUS_SPEED_FAST: - baudRate_Bps = 400000; - break; - - case ARM_I2C_BUS_SPEED_FAST_PLUS: - baudRate_Bps = 1000000; - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, (i2c->resource->GetFreq)()); - - return ARM_DRIVER_OK; - - /* Not supported */ - case ARM_I2C_BUS_CLEAR: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Aborts the data transfer when Master for Transmit or Receive */ - case ARM_I2C_ABORT_TRANSFER: - - if (i2c->resource->base->C1 & I2C_C1_MST_MASK) - { - /* Disable edma */ - I2C_MasterTransferAbortEDMA(i2c->resource->base, i2c->master_edma_handle); - /* If master receive */ - if (i2c->master_edma_handle->transfer.direction == kI2C_Read) - { - i2c->resource->base->C1 |= I2C_C1_TXAK_MASK; - while (!(i2c->resource->base->S & I2C_S_TCF_MASK)) - { - } - i2c->resource->base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - dummy = i2c->resource->base->D; - } - /* If master transmit */ - else - { - while (!(i2c->resource->base->S & I2C_S_TCF_MASK)) - { - } - i2c->resource->base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - } - - i2c->master_edma_handle->transferSize = 0; - i2c->master_edma_handle->transfer.data = NULL; - i2c->master_edma_handle->transfer.dataSize = 0; - } - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -int32_t I2C_Master_EdmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_edma_driver_state_t *i2c) -{ - switch (state) - { - /* Terminates any pending data transfers, disable i2c moduole and i2c clock and related edma */ - case ARM_POWER_OFF: - I2C_Master_EdmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); - I2C_MasterDeinit(i2c->resource->base); - DMAMUX_DisableChannel(i2c->edmaResource->i2cDmamuxBase, i2c->edmaResource->i2cEdmaChannel); - - return ARM_DRIVER_OK; - - /* Not supported */ - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Enable i2c moduole and i2c clock */ - case ARM_POWER_FULL: - CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(i2c->resource->base)]); - i2c->resource->base->C1 = I2C_C1_IICEN(1); - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -ARM_I2C_STATUS I2C_Master_EdmaGetStatus(cmsis_i2c_edma_driver_state_t *i2c) -{ - ARM_I2C_STATUS stat = {0}; - uint32_t ksdk_i2c_master_status = I2C_MasterGetStatusFlags(i2c->resource->base); - - stat.busy = !(!(ksdk_i2c_master_status & kI2C_BusBusyFlag)); /* Busy flag.*/ - - stat.mode = 1; /* Mode: 0=Slave, 1=Master.*/ - - stat.direction = - !(!(ksdk_i2c_master_status & kI2C_TransferDirectionFlag)); /* Direction: 0=Transmitter, 1=Receiver.*/ - - stat.arbitration_lost = - !(!(ksdk_i2c_master_status & - kI2C_ArbitrationLostFlag)); /* Master lost arbitration (cleared on start of next Master operation)*/ - - return stat; -} -#endif - -#endif - -#if ((RTE_I2C0 && !RTE_I2C0_DMA_EN) || (RTE_I2C1 && !RTE_I2C1_DMA_EN) || (RTE_I2C2 && !RTE_I2C2_DMA_EN) || \ - (RTE_I2C3 && !RTE_I2C3_DMA_EN)) - -static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) -{ - uint32_t event; - - switch (xfer->event) - { - case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */ - event = ARM_I2C_EVENT_TRANSFER_DONE; - break; - - case kI2C_SlaveGenaralcallEvent: - event = ARM_I2C_EVENT_GENERAL_CALL; - break; - - default: - event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; - break; - } - - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} -static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base, - i2c_master_handle_t *handle, - status_t status, - void *userData) -{ - uint32_t event; - - switch (status) - { - case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */ - event = ARM_I2C_EVENT_TRANSFER_DONE; - break; - - case kStatus_I2C_Addr_Nak: /* Occurs in master mode when address is not acknowledged from slave.*/ - event = ARM_I2C_EVENT_ADDRESS_NACK; - break; - - case kStatus_I2C_ArbitrationLost: /* Occurs in master mode when arbitration is lost.*/ - event = ARM_I2C_EVENT_ARBITRATION_LOST; - break; - - default: - event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; - break; - } - - /* User data is actually CMSIS driver callback. */ - if (userData) - { - ((ARM_I2C_SignalEvent_t)userData)(event); - } -} - -static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */ - return ARM_DRIVER_OK; -} - -static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - i2c->isInitialized = false; - return ARM_DRIVER_OK; -} - -int32_t I2C_Master_InterruptTransmit( - uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->handle->master_handle.state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - /* Create master_handle */ - I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), - KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Write; /* Transfer direction.*/ - masterXfer.subaddress = (uint32_t)NULL; /* Sub address */ - masterXfer.subaddressSize = 0; /* Size of command buffer.*/ - masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/ - masterXfer.dataSize = num; /* Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ - - if (i2c->resource->base->S & 0x20) - { - masterXfer.flags |= kI2C_TransferRepeatedStartFlag; - } - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - - case kStatus_I2C_Timeout: - ret = ARM_DRIVER_ERROR_TIMEOUT; - break; - - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Master_InterruptReceive( - uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - i2c_master_transfer_t masterXfer; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (i2c->handle->master_handle.state != 0) - { - return ARM_DRIVER_ERROR_BUSY; - } - - /* Create master_handle */ - I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), - KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); - - masterXfer.slaveAddress = addr; /*7-bit slave address.*/ - masterXfer.direction = kI2C_Read; /* Transfer direction.*/ - masterXfer.subaddress = (uint32_t)NULL; /* Sub address */ - masterXfer.subaddressSize = 0; /* Size of command buffer.*/ - masterXfer.data = data; /* Transfer buffer.*/ - masterXfer.dataSize = num; /* Transfer size.*/ - masterXfer.flags = kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/ - - if (i2c->resource->base->S & 0x20) - { - masterXfer.flags |= kI2C_TransferRepeatedStartFlag; - } - - if (xfer_pending) - { - masterXfer.flags |= kI2C_TransferNoStopFlag; - } - - status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - - case kStatus_I2C_Timeout: - ret = ARM_DRIVER_ERROR_TIMEOUT; - break; - - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - - /* Create slave_handle */ - I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, - (void *)i2c->cb_event); - - status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); - - i2c->handle->slave_handle.transfer.data = - (uint8_t *)data; /* Pointer to buffer with data to transmit to I2C Master */ - i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */ - i2c->handle->slave_handle.transfer.transferredCount = - 0; /* Number of bytes actually transferred since start or last repeated start. */ - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - int32_t status; - int32_t ret; - - i2c->resource->base->C2 = I2C_C2_GCAEN(1); /* Enable general call */ - - /* Create slave_handle */ - I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, - (void *)i2c->cb_event); - - status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); - - i2c->handle->slave_handle.transfer.data = data; /* Pointer to buffer with data to transmit to I2C Master */ - i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */ - i2c->handle->slave_handle.transfer.transferredCount = - 0; /* Number of bytes actually transferred since start or last repeated start. */ - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - - case kStatus_I2C_Busy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} -int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - uint32_t cnt; /* The number of currently transferred data bytes */ - - if (i2c->handle->slave_handle.transfer.transferredCount) - { - cnt = i2c->handle->slave_handle.transfer.transferredCount; - } - else - { - cnt = &(i2c->handle->master_handle).transferSize - &(i2c->handle->master_handle).transfer.dataSize; - } - - return cnt; -} - -int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - uint32_t baudRate_Bps; - - switch (control) - { - /* Set Own Slave Address; arg = slave address */ - case ARM_I2C_OWN_ADDRESS: - i2c->resource->base->A1 = (arg << 1U); - return ARM_DRIVER_OK; - - /* Set Bus Speed; arg = bus speed */ - case ARM_I2C_BUS_SPEED: - switch (arg) - { - case ARM_I2C_BUS_SPEED_STANDARD: - baudRate_Bps = 100000; - break; - - case ARM_I2C_BUS_SPEED_FAST: - baudRate_Bps = 400000; - break; - - case ARM_I2C_BUS_SPEED_FAST_PLUS: - baudRate_Bps = 1000000; - break; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); - - return ARM_DRIVER_OK; - /* Not supported */ - case ARM_I2C_BUS_CLEAR: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Aborts the data transfer between Master and Slave for Transmit or Receive */ - case ARM_I2C_ABORT_TRANSFER: - if (i2c->resource->base->C1 & I2C_C1_MST_MASK) - { - /* Disable master interrupt and send STOP signal */ - I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle)); - - i2c->handle->master_handle.transferSize = 0; - i2c->handle->master_handle.transfer.data = NULL; - i2c->handle->master_handle.transfer.dataSize = 0; - } - /* If slave receive */ - if ((i2c->handle->slave_handle.isBusy) && (!(i2c->resource->base->S & kI2C_TransferDirectionFlag))) - { - i2c->resource->base->C1 |= I2C_C1_TXAK_MASK; - - while (i2c->handle->slave_handle.isBusy) - { - } - /* Disable slave interrupt */ - - I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle)); - - i2c->handle->slave_handle.transfer.data = NULL; - i2c->handle->slave_handle.transfer.dataSize = 0; - } - return ARM_DRIVER_OK; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c) -{ - switch (state) - { - /* Terminates any pending data transfers, disable i2c moduole and i2c clock */ - case ARM_POWER_OFF: - - I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); - - I2C_MasterDeinit(i2c->resource->base); - - return ARM_DRIVER_OK; - - /* Not supported */ - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Enable i2c moduole and i2c clock */ - case ARM_POWER_FULL: - - CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(i2c->resource->base)]); - - i2c->resource->base->C1 = I2C_C1_IICEN(1); - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c) -{ - ARM_I2C_STATUS stat = {0}; - uint32_t ksdk_i2c_status = I2C_SlaveGetStatusFlags(i2c->resource->base); - stat.busy = !(!(ksdk_i2c_status & kI2C_BusBusyFlag)); /* Busy flag.*/ - - if (i2c->resource->base->C1 & I2C_C1_MST_MASK) - { - stat.direction = !(!(ksdk_i2c_status & kI2C_TransferDirectionFlag)); /* Direction: 0=Transmitter, 1=Receiver.*/ - stat.mode = 1; /* Mode: 0=Slave, 1=Master.*/ - } - - if (i2c->handle->slave_handle.isBusy) - { - stat.direction = !(ksdk_i2c_status & kI2C_TransferDirectionFlag); /* Direction: 0=Transmitter, 1=Receiver.*/ - stat.mode = 0; /* Mode: 0=Slave, 1=Master.*/ - } - - stat.arbitration_lost = - !(!(ksdk_i2c_status & - kI2C_ArbitrationLostFlag)); /* Master lost arbitration (cleared on start of next Master operation)*/ - - return stat; -} - -#endif - -#if defined(I2C0) && RTE_I2C0 -extern uint32_t I2C0_GetFreq(void); -extern void I2C0_InitPins(void); -extern void I2C0_DeinitPins(void); - -cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq}; - -#if RTE_I2C0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C0_DmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH, - RTE_I2C0_Master_DMAMUX_BASE, RTE_I2C0_Master_PERI_SEL}; - -i2c_master_dma_handle_t I2C0_DmaHandle; -dma_handle_t I2C0_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c0_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { -#endif - &I2C0_Resource, &I2C0_DmaResource, &I2C0_DmaHandle, &I2C0_DmaTxRxHandle, -}; - -static int32_t I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C0_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaUninitialize(void) -{ - I2C0_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C0_DmaDriverState); -} - -int32_t I2C0_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C0_DmaDriverState); -} - -ARM_I2C_STATUS I2C0_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C0_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_i2c_edma_resource_t I2C0_EdmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH, - RTE_I2C0_Master_DMAMUX_BASE, RTE_I2C0_Master_PERI_SEL}; - -i2c_master_edma_handle_t I2C0_EdmaHandle; -edma_handle_t I2C0_EdmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c0_edma_driver_state") -cmsis_i2c_edma_driver_state_t I2C0_EdmaDriverState = { -#else -cmsis_i2c_edma_driver_state_t I2C0_EdmaDriverState = { -#endif - &I2C0_Resource, &I2C0_EdmaResource, &I2C0_EdmaHandle, &I2C0_EdmaTxRxHandle, -}; - -static int32_t I2C0_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C0_InitPins(); - return I2C_Master_EdmaInitialize(cb_event, &I2C0_EdmaDriverState); -} - -int32_t I2C0_Master_EdmaUninitialize(void) -{ - I2C0_DeinitPins(); - return I2C_Master_EdmaUninitialize(&I2C0_EdmaDriverState); -} - -int32_t I2C0_Master_EdmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_EdmaPowerControl(state, &I2C0_EdmaDriverState); -} - -int32_t I2C0_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C0_EdmaDriverState); -} - -int32_t I2C0_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C0_EdmaDriverState); -} - -int32_t I2C0_Master_EdmaGetDataCount(void) -{ - return I2C_Master_EdmaGetDataCount(&I2C0_EdmaDriverState); -} - -int32_t I2C0_Master_EdmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_EdmaControl(control, arg, &I2C0_EdmaDriverState); -} - -ARM_I2C_STATUS I2C0_Master_EdmaGetStatus(void) -{ - return I2C_Master_EdmaGetStatus(&I2C0_EdmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C0_handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c0_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { -#endif - &I2C0_Resource, &I2C0_handle, - -}; - -static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C0_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState); -} - -static int32_t I2C0_InterruptUninitialize(void) -{ - I2C0_DeinitPins(); - return I2C_InterruptUninitialize(&I2C0_InterruptDriverState); -} - -static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState); -} - -int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState); -} - -int32_t I2C0_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState); -} - -int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState); -} - -ARM_I2C_STATUS I2C0_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C0_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C0_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - I2C0_Master_EdmaInitialize, I2C0_Master_EdmaUninitialize, I2C0_Master_EdmaPowerControl, - I2C0_Master_EdmaTransmit, I2C0_Master_EdmaReceive, NULL, NULL, - I2C0_Master_EdmaGetDataCount, I2C0_Master_EdmaControl, I2C0_Master_EdmaGetStatus -#else - I2C0_Master_DmaInitialize, I2C0_Master_DmaUninitialize, I2C0_Master_DmaPowerControl, - I2C0_Master_DmaTransmit, I2C0_Master_DmaReceive, NULL, NULL, I2C0_Master_DmaGetDataCount, - I2C0_Master_DmaControl, I2C0_Master_DmaGetStatus -#endif -#else - I2C0_InterruptInitialize, I2C0_InterruptUninitialize, I2C0_InterruptPowerControl, - I2C0_Master_InterruptTransmit, I2C0_Master_InterruptReceive, I2C0_Slave_InterruptTransmit, - I2C0_Slave_InterruptReceive, I2C0_InterruptGetDataCount, I2C0_InterruptControl, - I2C0_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C1) && RTE_I2C1 - -extern uint32_t I2C1_GetFreq(void); -extern void I2C1_InitPins(void); -extern void I2C1_DeinitPins(void); - -cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq}; - -#if RTE_I2C1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C1_DmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH, - RTE_I2C1_Master_DMAMUX_BASE, RTE_I2C1_Master_PERI_SEL}; - -i2c_master_dma_handle_t I2C1_DmaHandle; -dma_handle_t I2C1_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c1_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { -#endif - &I2C1_Resource, &I2C1_DmaResource, &I2C1_DmaHandle, &I2C1_DmaTxRxHandle, -}; - -static int32_t I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C1_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaUninitialize(void) -{ - I2C1_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(state, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C1_DmaDriverState); -} - -int32_t I2C1_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C1_DmaDriverState); -} - -ARM_I2C_STATUS I2C1_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C1_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_i2c_edma_resource_t I2C1_EdmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH, - RTE_I2C1_Master_DMAMUX_BASE, RTE_I2C1_Master_PERI_SEL}; - -i2c_master_edma_handle_t I2C1_EdmaHandle; -edma_handle_t I2C1_EdmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c1_edma_driver_state") -cmsis_i2c_edma_driver_state_t I2C1_EdmaDriverState = { -#else -cmsis_i2c_edma_driver_state_t I2C1_EdmaDriverState = { -#endif - &I2C1_Resource, &I2C1_EdmaResource, &I2C1_EdmaHandle, &I2C1_EdmaTxRxHandle, -}; - -static int32_t I2C1_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C1_InitPins(); - return I2C_Master_EdmaInitialize(cb_event, &I2C1_EdmaDriverState); -} - -int32_t I2C1_Master_EdmaUninitialize(void) -{ - I2C1_DeinitPins(); - return I2C_Master_EdmaUninitialize(&I2C1_EdmaDriverState); -} - -int32_t I2C1_Master_EdmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_EdmaPowerControl(state, &I2C1_EdmaDriverState); -} - -int32_t I2C1_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C1_EdmaDriverState); -} - -int32_t I2C1_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C1_EdmaDriverState); -} - -int32_t I2C1_Master_EdmaGetDataCount(void) -{ - return I2C_Master_EdmaGetDataCount(&I2C1_EdmaDriverState); -} - -int32_t I2C1_Master_EdmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_EdmaControl(control, arg, &I2C1_EdmaDriverState); -} - -ARM_I2C_STATUS I2C1_Master_EdmaGetStatus(void) -{ - return I2C_Master_EdmaGetStatus(&I2C1_EdmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C1_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c1_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { -#endif - &I2C1_Resource, &I2C1_Handle, -}; - -static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C1_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState); -} - -static int32_t I2C1_InterruptUninitialize(void) -{ - I2C1_DeinitPins(); - return I2C_InterruptUninitialize(&I2C1_InterruptDriverState); -} - -static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState); -} - -int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState); -} - -int32_t I2C1_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState); -} - -int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState); -} - -ARM_I2C_STATUS I2C1_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C1_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C1_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - I2C1_Master_EdmaInitialize, I2C1_Master_EdmaUninitialize, I2C1_Master_EdmaPowerControl, - I2C1_Master_EdmaTransmit, I2C1_Master_EdmaReceive, NULL, NULL, - I2C1_Master_EdmaGetDataCount, I2C1_Master_EdmaControl, I2C1_Master_EdmaGetStatus -#else - I2C1_Master_DmaInitialize, I2C1_Master_DmaUninitialize, I2C1_Master_DmaPowerControl, - I2C1_Master_DmaTransmit, I2C1_Master_DmaReceive, NULL, NULL, I2C1_Master_DmaGetDataCount, - I2C1_Master_DmaControl, I2C1_Master_DmaGetStatus -#endif -#else - I2C1_InterruptInitialize, I2C1_InterruptUninitialize, I2C1_InterruptPowerControl, - I2C1_Master_InterruptTransmit, I2C1_Master_InterruptReceive, I2C1_Slave_InterruptTransmit, - I2C1_Slave_InterruptReceive, I2C1_InterruptGetDataCount, I2C1_InterruptControl, - I2C1_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C2) && RTE_I2C2 - -extern uint32_t I2C2_GetFreq(void); -extern void I2C2_InitPins(void); -extern void I2C2_DeinitPins(void); - -cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq}; - -#if RTE_I2C2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C2_DmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH, - RTE_I2C2_Master_DMAMUX_BASE, RTE_I2C2_Master_PERI_SEL}; - -i2c_master_dma_handle_t I2C2_DmaHandle; -dma_handle_t I2C2_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c2_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { -#endif - &I2C2_Resource, &I2C2_DmaResource, &I2C2_DmaHandle, &I2C2_DmaTxRxHandle, -}; - -static int32_t I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C2_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaUninitialize(void) -{ - I2C2_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(&I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C2_DmaDriverState); -} - -int32_t I2C2_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C2_DmaDriverState); -} - -ARM_I2C_STATUS I2C2_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C2_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_i2c_edma_resource_t I2C2_EdmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH, - RTE_I2C2_Master_DMAMUX_BASE, RTE_I2C2_Master_PERI_SEL}; - -i2c_master_edma_handle_t I2C2_EdmaHandle; -edma_handle_t I2C2_EdmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c2_edma_driver_state") -cmsis_i2c_edma_driver_state_t I2C2_EdmaDriverState = { -#else -cmsis_i2c_edma_driver_state_t I2C2_EdmaDriverState = { -#endif - &I2C2_Resource, &I2C2_EdmaResource, &I2C2_EdmaHandle, &I2C2_EdmaTxRxHandle, -}; - -static int32_t I2C2_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C2_InitPins(); - return I2C_Master_EdmaInitialize(cb_event, &I2C2_EdmaDriverState); -} - -int32_t I2C2_Master_EdmaUninitialize(void) -{ - I2C2_DeinitPins(); - return I2C_Master_EdmaUninitialize(&I2C2_EdmaDriverState); -} - -int32_t I2C2_Master_EdmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_EdmaPowerControl(state, &I2C2_EdmaDriverState); -} - -int32_t I2C2_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C2_EdmaDriverState); -} - -int32_t I2C2_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C2_EdmaDriverState); -} - -int32_t I2C2_Master_EdmaGetDataCount(void) -{ - return I2C_Master_EdmaGetDataCount(&I2C2_EdmaDriverState); -} - -int32_t I2C2_Master_EdmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_EdmaControl(control, arg, &I2C2_EdmaDriverState); -} - -ARM_I2C_STATUS I2C2_Master_EdmaGetStatus(void) -{ - return I2C_Master_EdmaGetStatus(&I2C2_EdmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C2_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c2_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { -#endif - &I2C2_Resource, &I2C2_Handle, - -}; - -static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C2_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState); -} - -static int32_t I2C2_InterruptUninitialize(void) -{ - I2C2_DeinitPins(); - return I2C_InterruptUninitialize(&I2C2_InterruptDriverState); -} - -static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState); -} - -int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState); -} - -int32_t I2C2_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState); -} - -int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState); -} - -ARM_I2C_STATUS I2C2_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C2_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C2_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - I2C2_Master_EdmaInitialize, I2C2_Master_EdmaUninitialize, I2C2_Master_EdmaPowerControl, - I2C2_Master_EdmaTransmit, I2C2_Master_EdmaReceive, NULL, NULL, - I2C2_Master_EdmaGetDataCount, I2C2_Master_EdmaControl, I2C2_Master_EdmaGetStatus -#else - I2C2_Master_DmaInitialize, I2C2_Master_DmaUninitialize, I2C2_Master_DmaPowerControl, - I2C2_Master_DmaTransmit, I2C2_Master_DmaReceive, NULL, NULL, I2C2_Master_DmaGetDataCount, - I2C2_Master_DmaControl, I2C2_Master_DmaGetStatus -#endif -#else - I2C2_InterruptInitialize, I2C2_InterruptUninitialize, I2C2_InterruptPowerControl, - I2C2_Master_InterruptTransmit, I2C2_Master_InterruptReceive, I2C2_Slave_InterruptTransmit, - I2C2_Slave_InterruptReceive, I2C2_InterruptGetDataCount, I2C2_InterruptControl, - I2C2_InterruptGetStatus -#endif -}; - -#endif - -#if defined(I2C3) && RTE_I2C3 - -extern uint32_t I2C3_GetFreq(void); -extern void I2C3_InitPins(void); -extern void I2C3_DeinitPins(void); - -cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq}; - -#if RTE_I2C3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_i2c_dma_resource_t I2C3_DmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH, - RTE_I2C3_Master_DMAMUX_BASE, RTE_I2C3_Master_PERI_SEL}; - -i2c_master_dma_handle_t I2C3_DmaHandle; -dma_handle_t I2C3_DmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c3_dma_driver_state") -cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { -#else -cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { -#endif - &I2C3_Resource, &I2C3_DmaResource, &I2C3_DmaHandle, &I2C3_DmaTxRxHandle, -}; - -static int32_t I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C3_InitPins(); - return I2C_Master_DmaInitialize(cb_event, &I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaUninitialize(void) -{ - I2C3_DeinitPins(); - return I2C_Master_DmaUninitialize(&I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_DmaPowerControl(&I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaGetDataCount(void) -{ - return I2C_Master_DmaGetDataCount(&I2C3_DmaDriverState); -} - -int32_t I2C3_Master_DmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_DmaControl(control, arg, &I2C3_DmaDriverState); -} - -ARM_I2C_STATUS I2C3_Master_DmaGetStatus(void) -{ - return I2C_Master_DmaGetStatus(&I2C3_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_i2c_edma_resource_t I2C3_EdmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH, - RTE_I2C3_Master_DMAMUX_BASE, RTE_I2C3_Master_PERI_SEL}; - -i2c_master_edma_handle_t I2C3_EdmaHandle; -edma_handle_t I2C3_EdmaTxRxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c3_edma_driver_state") -cmsis_i2c_edma_driver_state_t I2C3_EdmaDriverState = { -#else -cmsis_i2c_edma_driver_state_t I2C3_EdmaDriverState = { -#endif - &I2C3_Resource, &I2C3_EdmaResource, &I2C3_EdmaHandle, &I2C3_EdmaTxRxHandle, -}; - -static int32_t I2C3_Master_EdmaInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C3_InitPins(); - return I2C_Master_EdmaInitialize(cb_event, &I2C3_EdmaDriverState); -} - -int32_t I2C3_Master_EdmaUninitialize(void) -{ - I2C3_DeinitPins(); - return I2C_Master_EdmaUninitialize(&I2C3_EdmaDriverState); -} - -int32_t I2C3_Master_EdmaPowerControl(ARM_POWER_STATE state) -{ - return I2C_Master_EdmaPowerControl(state, &I2C3_EdmaDriverState); -} - -int32_t I2C3_Master_EdmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaTransmit(addr, data, num, xfer_pending, &I2C3_EdmaDriverState); -} - -int32_t I2C3_Master_EdmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_EdmaReceive(addr, data, num, xfer_pending, &I2C3_EdmaDriverState); -} - -int32_t I2C3_Master_EdmaGetDataCount(void) -{ - return I2C_Master_EdmaGetDataCount(&I2C3_EdmaDriverState); -} - -int32_t I2C3_Master_EdmaControl(uint32_t control, uint32_t arg) -{ - return I2C_Master_EdmaControl(control, arg, &I2C3_EdmaDriverState); -} - -ARM_I2C_STATUS I2C3_Master_EdmaGetStatus(void) -{ - return I2C_Master_EdmaGetStatus(&I2C3_EdmaDriverState); -} - -#endif - -#else - -cmsis_i2c_handle_t I2C3_Handle; - -#if defined(__CC_ARM) -ARMCC_SECTION("i2c3_interrupt_driver_state") -cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { -#else -cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { -#endif - &I2C3_Resource, &I2C3_Handle, -}; - -static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) -{ - I2C3_InitPins(); - return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState); -} - -static int32_t I2C3_InterruptUninitialize(void) -{ - I2C3_DeinitPins(); - return I2C_InterruptUninitialize(&I2C3_InterruptDriverState); -} - -static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state) -{ - return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) -{ - return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState); -} - -int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num) -{ - return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState); -} - -int32_t I2C3_InterruptGetDataCount(void) -{ - return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState); -} - -int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg) -{ - return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState); -} - -ARM_I2C_STATUS I2C3_InterruptGetStatus(void) -{ - return I2C_InterruptGetStatus(&I2C3_InterruptDriverState); -} - -#endif - -ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion, I2Cx_GetCapabilities, -#if RTE_I2C3_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - I2C3_Master_EdmaInitialize, I2C3_Master_EdmaUninitialize, I2C3_Master_EdmaPowerControl, - I2C3_Master_EdmaTransmit, I2C3_Master_EdmaReceive, NULL, NULL, - I2C3_Master_EdmaGetDataCount, I2C3_Master_EdmaControl, I2C3_Master_EdmaGetStatus -#else - I2C3_Master_DmaInitialize, I2C3_Master_DmaUninitialize, I2C3_Master_DmaPowerControl, - I2C3_Master_DmaTransmit, I2C3_Master_DmaReceive, NULL, NULL, I2C3_Master_DmaGetDataCount, - I2C3_Master_DmaControl, I2C3_Master_DmaGetStatus -#endif -#else - I2C3_InterruptInitialize, I2C3_InterruptUninitialize, I2C3_InterruptPowerControl, - I2C3_Master_InterruptTransmit, I2C3_Master_InterruptReceive, I2C3_Slave_InterruptTransmit, - I2C3_Slave_InterruptReceive, I2C3_InterruptGetDataCount, I2C3_InterruptControl, - I2C3_InterruptGetStatus -#endif -}; - -#endif diff --git a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.h b/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.h deleted file mode 100644 index 453bf7e4f..000000000 --- a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_i2c_cmsis.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_I2C_CMSIS_H_ -#define _FSL_I2C_CMSIS_H_ -#include "fsl_common.h" -#include "Driver_I2C.h" -#include "RTE_Device.h" -#include "fsl_i2c.h" -#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) -#include "fsl_dmamux.h" -#endif -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_i2c_dma.h" -#endif -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -#include "fsl_i2c_edma.h" -#endif - -#if defined(I2C0) -extern ARM_DRIVER_I2C Driver_I2C0; -#endif - -#if defined(I2C1) -extern ARM_DRIVER_I2C Driver_I2C1; -#endif - -#if defined(I2C2) -extern ARM_DRIVER_I2C Driver_I2C2; -#endif - -#if defined(I2C3) -extern ARM_DRIVER_I2C Driver_I2C3; -#endif - -#endif diff --git a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.c b/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.c deleted file mode 100644 index 4e6e3f4e6..000000000 --- a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.c +++ /dev/null @@ -1,2970 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpuart_cmsis.h" - -/* Re-mapping for LPUART & UART indexing. */ -#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && FSL_FEATURE_SOC_UART_COUNT - -#ifdef RTE_USART0 -#undef RTE_USART0 -#endif -#ifdef RTE_USART0_DMA_EN -#undef RTE_USART0_DMA_EN -#endif -#ifdef RTE_USART0_DMA_TX_CH -#undef RTE_USART0_DMA_TX_CH -#endif -#ifdef RTE_USART0_DMA_TX_PERI_SEL -#undef RTE_USART0_DMA_TX_PERI_SEL -#endif -#ifdef RTE_USART0_DMA_TX_DMAMUX_BASE -#undef RTE_USART0_DMA_TX_DMAMUX_BASE -#endif -#ifdef RTE_USART0_DMA_TX_DMA_BASE -#undef RTE_USART0_DMA_TX_DMA_BASE -#endif -#ifdef RTE_USART0_DMA_RX_CH -#undef RTE_USART0_DMA_RX_CH -#endif -#ifdef RTE_USART0_DMA_RX_PERI_SEL -#undef RTE_USART0_DMA_RX_PERI_SEL -#endif -#ifdef RTE_USART0_DMA_RX_DMAMUX_BASE -#undef RTE_USART0_DMA_RX_DMAMUX_BASE -#endif -#ifdef RTE_USART0_DMA_RX_DMA_BASE -#undef RTE_USART0_DMA_RX_DMA_BASE -#endif -#ifdef USART0_RX_BUFFER_ENABLE -#undef USART0_RX_BUFFER_ENABLE -#endif - -#if (FSL_FEATURE_SOC_UART_COUNT == 3) - -#ifdef RTE_USART3 -#define RTE_USART0 RTE_USART3 -#endif -#ifdef RTE_USART3_DMA_EN -#define RTE_USART0_DMA_EN RTE_USART3_DMA_EN -#endif -#ifdef RTE_USART3_DMA_TX_CH -#define RTE_USART0_DMA_TX_CH RTE_USART3_DMA_TX_CH -#endif -#ifdef RTE_USART3_DMA_TX_PERI_SEL -#define RTE_USART0_DMA_TX_PERI_SEL RTE_USART3_DMA_TX_PERI_SEL -#endif -#ifdef RTE_USART3_DMA_TX_DMAMUX_BASE -#define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART3_DMA_TX_DMAMUX_BASE -#endif -#ifdef RTE_USART3_DMA_TX_DMA_BASE -#define RTE_USART0_DMA_TX_DMA_BASE RTE_USART3_DMA_TX_DMA_BASE -#endif -#ifdef RTE_USART3_DMA_RX_CH -#define RTE_USART0_DMA_RX_CH RTE_USART3_DMA_RX_CH -#endif -#ifdef RTE_USART3_DMA_RX_PERI_SEL -#define RTE_USART0_DMA_RX_PERI_SEL RTE_USART3_DMA_RX_PERI_SEL -#endif -#ifdef RTE_USART3_DMA_RX_DMAMUX_BASE -#define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART3_DMA_RX_DMAMUX_BASE -#endif -#ifdef RTE_USART3_DMA_RX_DMA_BASE -#define RTE_USART0_DMA_RX_DMA_BASE RTE_USART3_DMA_RX_DMA_BASE -#endif -#ifdef USART3_RX_BUFFER_ENABLE -#define USART0_RX_BUFFER_ENABLE USART3_RX_BUFFER_ENABLE -#endif - -#endif - -#if (FSL_FEATURE_SOC_UART_COUNT == 4) - -#ifdef RTE_USART4 -#define RTE_USART0 RTE_USART4 -#endif -#ifdef RTE_USART4_DMA_EN -#define RTE_USART0_DMA_EN RTE_USART4_DMA_EN -#endif -#ifdef RTE_USART4_DMA_TX_CH -#define RTE_USART0_DMA_TX_CH RTE_USART4_DMA_TX_CH -#endif -#ifdef RTE_USART4_DMA_TX_PERI_SEL -#define RTE_USART0_DMA_TX_PERI_SEL RTE_USART4_DMA_TX_PERI_SEL -#endif -#ifdef RTE_USART4_DMA_TX_DMAMUX_BASE -#define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART4_DMA_TX_DMAMUX_BASE -#endif -#ifdef RTE_USART4_DMA_TX_DMA_BASE -#define RTE_USART0_DMA_TX_DMA_BASE RTE_USART4_DMA_TX_DMA_BASE -#endif -#ifdef RTE_USART4_DMA_RX_CH -#define RTE_USART0_DMA_RX_CH RTE_USART4_DMA_RX_CH -#endif -#ifdef RTE_USART4_DMA_RX_PERI_SEL -#define RTE_USART0_DMA_RX_PERI_SEL RTE_USART4_DMA_RX_PERI_SEL -#endif -#ifdef RTE_USART4_DMA_RX_DMAMUX_BASE -#define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART4_DMA_RX_DMAMUX_BASE -#endif -#ifdef RTE_USART4_DMA_RX_DMA_BASE -#define RTE_USART0_DMA_RX_DMA_BASE RTE_USART4_DMA_RX_DMA_BASE -#endif -#ifdef USART4_RX_BUFFER_ENABLE -#define USART0_RX_BUFFER_ENABLE USART4_RX_BUFFER_ENABLE -#endif - -#endif - -#if (FSL_FEATURE_SOC_UART_COUNT == 5) - -#ifdef RTE_USART5 -#define RTE_USART0 RTE_USART5 -#endif -#ifdef RTE_USART5_DMA_EN -#define RTE_USART0_DMA_EN RTE_USART5_DMA_EN -#endif -#ifdef RTE_USART5_DMA_TX_CH -#define RTE_USART0_DMA_TX_CH RTE_USART5_DMA_TX_CH -#endif -#ifdef RTE_USART5_DMA_TX_PERI_SEL -#define RTE_USART0_DMA_TX_PERI_SEL RTE_USART5_DMA_TX_PERI_SEL -#endif -#ifdef RTE_USART5_DMA_TX_DMAMUX_BASE -#define RTE_USART0_DMA_TX_DMAMUX_BASE RTE_USART5_DMA_TX_DMAMUX_BASE -#endif -#ifdef RTE_USART5_DMA_TX_DMA_BASE -#define RTE_USART0_DMA_TX_DMA_BASE RTE_USART5_DMA_TX_DMA_BASE -#endif -#ifdef RTE_USART5_DMA_RX_CH -#define RTE_USART0_DMA_RX_CH RTE_USART5_DMA_RX_CH -#endif -#ifdef RTE_USART5_DMA_RX_PERI_SEL -#define RTE_USART0_DMA_RX_PERI_SEL RTE_USART5_DMA_RX_PERI_SEL -#endif -#ifdef RTE_USART5_DMA_RX_DMAMUX_BASE -#define RTE_USART0_DMA_RX_DMAMUX_BASE RTE_USART5_DMA_RX_DMAMUX_BASE -#endif -#ifdef RTE_USART5_DMA_RX_DMA_BASE -#define RTE_USART0_DMA_RX_DMA_BASE RTE_USART5_DMA_RX_DMA_BASE -#endif -#ifdef USART5_RX_BUFFER_ENABLE -#define USART0_RX_BUFFER_ENABLE USART5_RX_BUFFER_ENABLE -#endif - -#endif - -#endif - -#if ((RTE_USART0 && defined(LPUART0)) || (RTE_USART1 && defined(LPUART1)) || (RTE_USART2 && defined(LPUART2)) || \ - (RTE_USART3 && defined(LPUART3)) || (RTE_USART4 && defined(LPUART4)) || (RTE_USART5 && defined(LPUART5))) - -#define ARM_LPUART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) - -/* - * ARMCC does not support split the data section automatically, so the driver - * needs to split the data to separate sections explicitly, to reduce codesize. - */ -#if defined(__CC_ARM) -#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) -#endif - -typedef const struct _cmsis_lpuart_resource -{ - LPUART_Type *base; /*!< LPUART peripheral base address. */ - uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ -} cmsis_lpuart_resource_t; - -typedef struct _cmsis_lpuart_non_blocking_driver_state -{ - cmsis_lpuart_resource_t *resource; /*!< Basic LPUART resource. */ - lpuart_handle_t *handle; /*!< Interupt transfer handle. */ - ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ - bool isInitialized; /*!< Is initialized or not. */ - bool isPowerOn; /*!< Is power on or not. */ - bool isConfigured; /*!< Configured to work or not. */ -} cmsis_lpuart_non_blocking_driver_state_t; - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -typedef struct _cmsis_lpuart_dma_resource -{ - DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */ - uint32_t txDmaChannel; /*!< DMA channel for LPUART TX. */ - DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */ - uint8_t txDmaRequest; /*!< TX DMA request source. */ - - DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */ - uint32_t rxDmaChannel; /*!< DMA channel for LPUART RX. */ - DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */ - uint8_t rxDmaRequest; /*!< RX DMA request source. */ -} cmsis_lpuart_dma_resource_t; - -typedef struct _cmsis_lpuart_dma_driver_state -{ - cmsis_lpuart_resource_t *resource; /*!< LPUART basic resource. */ - cmsis_lpuart_dma_resource_t *dmaResource; /*!< LPUART DMA resource. */ - lpuart_dma_handle_t *handle; /*!< LPUART DMA transfer handle. */ - dma_handle_t *rxHandle; /*!< DMA RX handle. */ - dma_handle_t *txHandle; /*!< DMA TX handle. */ - ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ - bool isInitialized; /*!< Is initialized or not. */ - bool isPowerOn; /*!< Is power on or not. */ - bool isConfigured; /*!< Configured to work or not. */ -} cmsis_lpuart_dma_driver_state_t; -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -typedef struct _cmsis_lpuart_edma_resource -{ - DMA_Type *txEdmaBase; /*!< EDMA peripheral base address for TX. */ - uint32_t txEdmaChannel; /*!< EDMA channel for LPUART TX. */ - DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */ - uint8_t txDmaRequest; /*!< TX EDMA request source. */ - - DMA_Type *rxEdmaBase; /*!< EDMA peripheral base address for RX. */ - uint32_t rxEdmaChannel; /*!< EDMA channel for LPUART RX. */ - DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */ - uint8_t rxDmaRequest; /*!< RX EDMA request source. */ -} cmsis_lpuart_edma_resource_t; - -typedef struct _cmsis_lpuart_edma_driver_state -{ - cmsis_lpuart_resource_t *resource; /*!< LPUART basic resource. */ - cmsis_lpuart_edma_resource_t *dmaResource; /*!< LPUART EDMA resource. */ - lpuart_edma_handle_t *handle; /*!< LPUART EDMA transfer handle. */ - edma_handle_t *rxHandle; /*!< EDMA RX handle. */ - edma_handle_t *txHandle; /*!< EDMA TX handle. */ - ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ - bool isInitialized; /*!< Is initialized or not. */ - bool isPowerOn; /*!< Is power on or not. */ - bool isConfigured; /*!< Configured to work or not. */ -} cmsis_lpuart_edma_driver_state_t; -#endif - -enum _lpuart_transfer_states -{ - kLPUART_TxIdle, /*!< TX idle. */ - kLPUART_TxBusy, /*!< TX busy. */ - kLPUART_RxIdle, /*!< RX idle. */ - kLPUART_RxBusy /*!< RX busy. */ -}; - -/* Driver Version */ -static const ARM_DRIVER_VERSION s_lpuartDriverVersion = {ARM_USART_API_VERSION, ARM_LPUART_DRV_VERSION}; - -static const ARM_USART_CAPABILITIES s_lpuartDriverCapabilities = { - 1, /* supports LPUART (Asynchronous) mode */ - 0, /* supports Synchronous Master mode */ - 0, /* supports Synchronous Slave mode */ - 0, /* supports LPUART Single-wire mode */ - 0, /* supports LPUART IrDA mode */ - 0, /* supports LPUART Smart Card mode */ - 0, /* Smart Card Clock generator */ - 0, /* RTS Flow Control available */ - 0, /* CTS Flow Control available */ - 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ - 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ - 0, /* RTS Line: 0=not available, 1=available */ - 0, /* CTS Line: 0=not available, 1=available */ - 0, /* DTR Line: 0=not available, 1=available */ - 0, /* DSR Line: 0=not available, 1=available */ - 0, /* DCD Line: 0=not available, 1=available */ - 0, /* RI Line: 0=not available, 1=available */ - 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ - 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ - 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ - 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ -}; - -/* - * Common control function used by LPUART_NonBlockingControl/LPUART_DmaControl/LPUART_EdmaControl - */ -static int32_t LPUART_CommonControl(uint32_t control, - uint32_t arg, - cmsis_lpuart_resource_t *resource, - bool *isConfigured) -{ - lpuart_config_t config; - - LPUART_GetDefaultConfig(&config); - - switch (control & ARM_USART_CONTROL_Msk) - { - case ARM_USART_MODE_ASYNCHRONOUS: - /* USART Baudrate */ - config.baudRate_Bps = arg; - break; - - /* TX/RX IO is controlled in application layer. */ - case ARM_USART_CONTROL_TX: - if (arg) - { - LPUART_EnableTx(resource->base, true); - } - else - { - LPUART_EnableTx(resource->base, false); - } - return ARM_DRIVER_OK; - - case ARM_USART_CONTROL_RX: - if (arg) - { - LPUART_EnableRx(resource->base, true); - } - else - { - LPUART_EnableRx(resource->base, false); - } - - return ARM_DRIVER_OK; - - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_DATA_BITS_Msk) - { -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - case ARM_USART_DATA_BITS_7: - config.dataBitsCount = kLPUART_SevenDataBits; - break; -#endif - case ARM_USART_DATA_BITS_8: - config.dataBitsCount = kLPUART_EightDataBits; - break; - - default: - return ARM_USART_ERROR_DATA_BITS; - } - - switch (control & ARM_USART_PARITY_Msk) - { - case ARM_USART_PARITY_NONE: - config.parityMode = kLPUART_ParityDisabled; - break; - case ARM_USART_PARITY_EVEN: - config.parityMode = kLPUART_ParityEven; - break; - case ARM_USART_PARITY_ODD: - config.parityMode = kLPUART_ParityOdd; - break; - default: - return ARM_USART_ERROR_PARITY; - } - - switch (control & ARM_USART_STOP_BITS_Msk) - { - case ARM_USART_STOP_BITS_1: - /* The GetDefaultConfig has already set for this case. */ - break; -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - case ARM_USART_STOP_BITS_2: - config.stopBitCount = kLPUART_TwoStopBit; - break; -#endif - default: - return ARM_USART_ERROR_STOP_BITS; - } - - /* If LPUART is already configured, deinit it first. */ - if (*isConfigured) - { - LPUART_Deinit(resource->base); - *isConfigured = false; - } - - config.enableTx = true; - config.enableRx = true; - - if (kStatus_LPUART_BaudrateNotSupport == LPUART_Init(resource->base, &config, resource->GetFreq())) - { - return ARM_USART_ERROR_BAUDRATE; - } - - *isConfigured = true; - - return ARM_DRIVER_OK; -} - -static ARM_DRIVER_VERSION LPUARTx_GetVersion(void) -{ - return s_lpuartDriverVersion; -} - -static ARM_USART_CAPABILITIES LPUARTx_GetCapabilities(void) -{ - return s_lpuartDriverCapabilities; -} - -static int32_t LPUARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) -{ - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static ARM_USART_MODEM_STATUS LPUARTx_GetModemStatus(void) -{ - ARM_USART_MODEM_STATUS modem_status; - - modem_status.cts = 0U; - modem_status.dsr = 0U; - modem_status.ri = 0U; - modem_status.dcd = 0U; - - return modem_status; -} - -#endif - -#if ((RTE_USART0_DMA_EN && defined(LPUART0)) || (RTE_USART1_DMA_EN && defined(LPUART1)) || \ - (RTE_USART2_DMA_EN && defined(LPUART2)) || (RTE_USART3_DMA_EN && defined(LPUART3)) || \ - (RTE_USART4_DMA_EN && defined(LPUART4)) || (RTE_USART5_DMA_EN && defined(LPUART5))) - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -void KSDK_LPUART_DmaCallback(LPUART_Type *base, lpuart_dma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_LPUART_TxIdle == status) - { - event = ARM_USART_EVENT_SEND_COMPLETE; - } - else if (kStatus_LPUART_RxIdle == status) - { - event = ARM_USART_EVENT_RECEIVE_COMPLETE; - } - - /* User data is actually CMSIS driver callback. */ - if ((0U != event) && (userData)) - { - ((ARM_USART_SignalEvent_t)userData)(event); - } -} - -static int32_t LPUART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_lpuart_dma_driver_state_t *lpuart) -{ - if (lpuart->isInitialized) - { - /* Driver is already initialized */ - return ARM_DRIVER_OK; - } - - lpuart->cb_event = cb_event; - lpuart->isInitialized = true; - - return ARM_DRIVER_OK; -} - -static int32_t LPUART_DmaUninitialize(cmsis_lpuart_dma_driver_state_t *lpuart) -{ - lpuart->isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t LPUART_DmaPowerControl(ARM_POWER_STATE state, cmsis_lpuart_dma_driver_state_t *lpuart) -{ - lpuart_config_t config; - cmsis_lpuart_dma_resource_t *dmaResource; - - switch (state) - { - case ARM_POWER_OFF: - if (lpuart->isPowerOn) - { - LPUART_Deinit(lpuart->resource->base); - DMAMUX_DisableChannel(lpuart->dmaResource->rxDmamuxBase, lpuart->dmaResource->rxDmaChannel); - DMAMUX_DisableChannel(lpuart->dmaResource->txDmamuxBase, lpuart->dmaResource->txDmaChannel); - lpuart->isPowerOn = false; - lpuart->isConfigured = false; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Must be initialized first. */ - if (!lpuart->isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!lpuart->isPowerOn) - { - LPUART_GetDefaultConfig(&config); - config.enableTx = true; - config.enableRx = true; - - dmaResource = lpuart->dmaResource; - - /* Set up DMA setting. */ - DMA_CreateHandle(lpuart->rxHandle, dmaResource->rxDmaBase, dmaResource->rxDmaChannel); - DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel, dmaResource->rxDmaRequest); - DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel); - - DMA_CreateHandle(lpuart->txHandle, dmaResource->txDmaBase, dmaResource->txDmaChannel); - DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txDmaChannel, dmaResource->txDmaRequest); - DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txDmaChannel); - - /* Setup the LPUART. */ - LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq()); - LPUART_TransferCreateHandleDMA(lpuart->resource->base, lpuart->handle, KSDK_LPUART_DmaCallback, - (void *)lpuart->cb_event, lpuart->txHandle, lpuart->rxHandle); - - lpuart->isPowerOn = true; - lpuart->isConfigured = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t LPUART_DmaSend(const void *data, uint32_t num, cmsis_lpuart_dma_driver_state_t *lpuart) -{ - int32_t ret; - status_t status; - lpuart_transfer_t xfer; - - xfer.data = (uint8_t *)data; - xfer.dataSize = num; - - status = LPUART_TransferSendDMA(lpuart->resource->base, lpuart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_LPUART_RxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t LPUART_DmaReceive(void *data, uint32_t num, cmsis_lpuart_dma_driver_state_t *lpuart) -{ - int32_t ret; - status_t status; - lpuart_transfer_t xfer; - - xfer.data = data; - xfer.dataSize = num; - - status = LPUART_TransferReceiveDMA(lpuart->resource->base, lpuart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_LPUART_TxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t LPUART_DmaTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_lpuart_dma_driver_state_t *lpuart) -{ - /* Only in synchronous mode */ - return ARM_DRIVER_ERROR; -} - -static uint32_t LPUART_DmaGetTxCount(cmsis_lpuart_dma_driver_state_t *lpuart) -{ - uint32_t cnt; - - /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ - if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCountDMA(lpuart->resource->base, lpuart->handle, &cnt)) - { - cnt = lpuart->handle->txDataSizeAll; - } - - return cnt; -} - -static uint32_t LPUART_DmaGetRxCount(cmsis_lpuart_dma_driver_state_t *lpuart) -{ - uint32_t cnt; - - if (kStatus_NoTransferInProgress == LPUART_TransferGetReceiveCountDMA(lpuart->resource->base, lpuart->handle, &cnt)) - { - cnt = lpuart->handle->rxDataSizeAll; - } - - return cnt; -} - -static int32_t LPUART_DmaControl(uint32_t control, uint32_t arg, cmsis_lpuart_dma_driver_state_t *lpuart) -{ - /* Must be power on. */ - if (!lpuart->isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - /* Does not support these features. */ - if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_CONTROL_Msk) - { - /* Abort Send */ - case ARM_USART_ABORT_SEND: - LPUART_TransferAbortSendDMA(lpuart->resource->base, lpuart->handle); - return ARM_DRIVER_OK; - - /* Abort receive */ - case ARM_USART_ABORT_RECEIVE: - LPUART_TransferAbortReceiveDMA(lpuart->resource->base, lpuart->handle); - return ARM_DRIVER_OK; - - default: - break; - } - - return LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->isConfigured); -} - -static ARM_USART_STATUS LPUART_DmaGetStatus(cmsis_lpuart_dma_driver_state_t *lpuart) -{ - ARM_USART_STATUS stat; - uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base); - - stat.tx_busy = ((kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U)); - stat.rx_busy = ((kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U)); - - stat.tx_underflow = 0U; - stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag))); -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag))); -#else - stat.rx_break = 0U; -#endif - stat.rx_framing_error = (!(!(ksdk_lpuart_status & kLPUART_FramingErrorFlag))); - stat.rx_parity_error = (!(!(ksdk_lpuart_status & kLPUART_ParityErrorFlag))); - - return stat; -} -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -void KSDK_LPUART_EdmaCallback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_LPUART_TxIdle == status) - { - event = ARM_USART_EVENT_SEND_COMPLETE; - } - if (kStatus_LPUART_RxIdle == status) - { - event = ARM_USART_EVENT_RECEIVE_COMPLETE; - } - - /* User data is actually CMSIS driver callback. */ - if ((0U != event) && (userData)) - { - ((ARM_USART_SignalEvent_t)userData)(event); - } -} - -static int32_t LPUART_EdmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_lpuart_edma_driver_state_t *lpuart) -{ - if (lpuart->isInitialized) - { - /* Driver is already initialized */ - return ARM_DRIVER_OK; - } - - lpuart->cb_event = cb_event; - lpuart->isInitialized = true; - - return ARM_DRIVER_OK; -} - -static int32_t LPUART_EdmaUninitialize(cmsis_lpuart_edma_driver_state_t *lpuart) -{ - lpuart->isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t LPUART_EdmaPowerControl(ARM_POWER_STATE state, cmsis_lpuart_edma_driver_state_t *lpuart) -{ - lpuart_config_t config; - cmsis_lpuart_edma_resource_t *dmaResource; - - switch (state) - { - case ARM_POWER_OFF: - if (lpuart->isPowerOn) - { - LPUART_Deinit(lpuart->resource->base); - DMAMUX_DisableChannel(lpuart->dmaResource->rxDmamuxBase, lpuart->dmaResource->rxEdmaChannel); - DMAMUX_DisableChannel(lpuart->dmaResource->txDmamuxBase, lpuart->dmaResource->txEdmaChannel); - lpuart->isPowerOn = false; - lpuart->isConfigured = false; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Must be initialized first. */ - if (!lpuart->isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!lpuart->isPowerOn) - { - LPUART_GetDefaultConfig(&config); - config.enableTx = true; - config.enableRx = true; - - dmaResource = lpuart->dmaResource; - - /* Set up EDMA setting. */ - EDMA_CreateHandle(lpuart->rxHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel); - DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, dmaResource->rxDmaRequest); - DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel); - - EDMA_CreateHandle(lpuart->txHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel); - DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, dmaResource->txDmaRequest); - DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel); - - /* Setup the LPUART. */ - LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq()); - LPUART_TransferCreateHandleEDMA(lpuart->resource->base, lpuart->handle, KSDK_LPUART_EdmaCallback, - (void *)lpuart->cb_event, lpuart->txHandle, lpuart->rxHandle); - - lpuart->isPowerOn = true; - lpuart->isConfigured = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t LPUART_EdmaSend(const void *data, uint32_t num, cmsis_lpuart_edma_driver_state_t *lpuart) -{ - int32_t ret; - status_t status; - lpuart_transfer_t xfer; - - xfer.data = (uint8_t *)data; - xfer.dataSize = num; - - status = LPUART_SendEDMA(lpuart->resource->base, lpuart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_LPUART_RxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t LPUART_EdmaReceive(void *data, uint32_t num, cmsis_lpuart_edma_driver_state_t *lpuart) -{ - int32_t ret; - status_t status; - lpuart_transfer_t xfer; - - xfer.data = data; - xfer.dataSize = num; - - status = LPUART_ReceiveEDMA(lpuart->resource->base, lpuart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_LPUART_TxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t LPUART_EdmaTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_lpuart_edma_driver_state_t *lpuart) -{ - /* Only in synchronous mode */ - return ARM_DRIVER_ERROR; -} - -static uint32_t LPUART_EdmaGetTxCount(cmsis_lpuart_edma_driver_state_t *lpuart) -{ - uint32_t cnt; - - if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCountEDMA(lpuart->resource->base, lpuart->handle, &cnt)) - { - cnt = lpuart->handle->txDataSizeAll; - } - - return cnt; -} - -static uint32_t LPUART_EdmaGetRxCount(cmsis_lpuart_edma_driver_state_t *lpuart) -{ - uint32_t cnt; - - if (kStatus_NoTransferInProgress == - LPUART_TransferGetReceiveCountEDMA(lpuart->resource->base, lpuart->handle, &cnt)) - { - cnt = lpuart->handle->rxDataSizeAll; - } - - return cnt; -} - -static int32_t LPUART_EdmaControl(uint32_t control, uint32_t arg, cmsis_lpuart_edma_driver_state_t *lpuart) -{ - /* Must be power on. */ - if (!lpuart->isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - /* Does not support these features. */ - if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_CONTROL_Msk) - { - /* Abort Send */ - case ARM_USART_ABORT_SEND: - LPUART_TransferAbortSendEDMA(lpuart->resource->base, lpuart->handle); - return ARM_DRIVER_OK; - - /* Abort receive */ - case ARM_USART_ABORT_RECEIVE: - LPUART_TransferAbortReceiveEDMA(lpuart->resource->base, lpuart->handle); - return ARM_DRIVER_OK; - - default: - break; - } - - return LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->isConfigured); -} - -static ARM_USART_STATUS LPUART_EdmaGetStatus(cmsis_lpuart_edma_driver_state_t *lpuart) -{ - ARM_USART_STATUS stat; - uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base); - - stat.tx_busy = ((kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U)); - stat.rx_busy = ((kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U)); - - stat.tx_underflow = 0U; - stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag))); -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag))); -#else - stat.rx_break = 0U; -#endif - stat.rx_framing_error = (!(!(ksdk_lpuart_status & kLPUART_FramingErrorFlag))); - stat.rx_parity_error = (!(!(ksdk_lpuart_status & kLPUART_ParityErrorFlag))); - - return stat; -} -#endif - -#endif - -#if (((RTE_USART0 && !RTE_USART0_DMA_EN) && defined(LPUART0)) || \ - ((RTE_USART1 && !RTE_USART1_DMA_EN) && defined(LPUART1)) || \ - ((RTE_USART2 && !RTE_USART2_DMA_EN) && defined(LPUART2)) || \ - ((RTE_USART3 && !RTE_USART3_DMA_EN) && defined(LPUART3)) || \ - ((RTE_USART4 && !RTE_USART4_DMA_EN) && defined(LPUART4)) || \ - ((RTE_USART5 && !RTE_USART5_DMA_EN) && defined(LPUART5))) - -void KSDK_LPUART_NonBlockingCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) -{ - uint32_t event = 0U; - - if (kStatus_LPUART_TxIdle == status) - { - event = ARM_USART_EVENT_SEND_COMPLETE; - } - if (kStatus_LPUART_RxIdle == status) - { - event = ARM_USART_EVENT_RECEIVE_COMPLETE; - } - if (kStatus_LPUART_RxHardwareOverrun == status) - { - event = ARM_USART_EVENT_RX_OVERFLOW; - } - - /* User data is actually CMSIS driver callback. */ - if ((0U != event) && (userData)) - { - ((ARM_USART_SignalEvent_t)userData)(event); - } -} - -static int32_t LPUART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, - cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - if (lpuart->isInitialized) - { - /* Driver is already initialized */ - return ARM_DRIVER_OK; - } - - lpuart->cb_event = cb_event; - lpuart->isInitialized = true; - - return ARM_DRIVER_OK; -} - -static int32_t LPUART_NonBlockingUninitialize(cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - lpuart->isInitialized = false; - return ARM_DRIVER_OK; -} - -static int32_t LPUART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - lpuart_config_t config; - - switch (state) - { - case ARM_POWER_OFF: - if (lpuart->isPowerOn) - { - LPUART_Deinit(lpuart->resource->base); - lpuart->isPowerOn = false; - lpuart->isConfigured = false; - } - break; - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Must be initialized first. */ - if (!lpuart->isInitialized) - { - return ARM_DRIVER_ERROR; - } - - if (!lpuart->isPowerOn) - { - LPUART_GetDefaultConfig(&config); - config.enableTx = true; - config.enableRx = true; - - LPUART_Init(lpuart->resource->base, &config, lpuart->resource->GetFreq()); - LPUART_TransferCreateHandle(lpuart->resource->base, lpuart->handle, KSDK_LPUART_NonBlockingCallback, - (void *)lpuart->cb_event); - lpuart->isPowerOn = true; - lpuart->isConfigured = true; - } - break; - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - return ARM_DRIVER_OK; -} - -static int32_t LPUART_NonBlockingSend(const void *data, uint32_t num, cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - int32_t ret; - status_t status; - lpuart_transfer_t xfer; - - xfer.data = (uint8_t *)data; - xfer.dataSize = num; - - status = LPUART_TransferSendNonBlocking(lpuart->resource->base, lpuart->handle, &xfer); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_LPUART_RxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t LPUART_NonBlockingReceive(void *data, uint32_t num, cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - int32_t ret; - status_t status; - lpuart_transfer_t xfer; - - xfer.data = data; - xfer.dataSize = num; - - status = LPUART_TransferReceiveNonBlocking(lpuart->resource->base, lpuart->handle, &xfer, NULL); - - switch (status) - { - case kStatus_Success: - ret = ARM_DRIVER_OK; - break; - case kStatus_InvalidArgument: - ret = ARM_DRIVER_ERROR_PARAMETER; - break; - case kStatus_LPUART_TxBusy: - ret = ARM_DRIVER_ERROR_BUSY; - break; - default: - ret = ARM_DRIVER_ERROR; - break; - } - - return ret; -} - -static int32_t LPUART_NonBlockingTransfer(const void *data_out, - void *data_in, - uint32_t num, - cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - /* Only in synchronous mode */ - return ARM_DRIVER_ERROR; -} - -static uint32_t LPUART_NonBlockingGetTxCount(cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - uint32_t cnt; - - /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ - if (kStatus_NoTransferInProgress == LPUART_TransferGetSendCount(lpuart->resource->base, lpuart->handle, &cnt)) - { - cnt = lpuart->handle->txDataSizeAll; - } - - return cnt; -} - -static uint32_t LPUART_NonBlockingGetRxCount(cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - uint32_t cnt; - - if (kStatus_NoTransferInProgress == LPUART_TransferGetReceiveCount(lpuart->resource->base, lpuart->handle, &cnt)) - { - cnt = lpuart->handle->rxDataSizeAll; - } - - return cnt; -} - -static int32_t LPUART_NonBlockingControl(uint32_t control, - uint32_t arg, - cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - /* Must be power on. */ - if (!lpuart->isPowerOn) - { - return ARM_DRIVER_ERROR; - } - - /* Does not support these features. */ - if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) - { - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - switch (control & ARM_USART_CONTROL_Msk) - { - /* Abort Send */ - case ARM_USART_ABORT_SEND: - LPUART_TransferAbortSend(lpuart->resource->base, lpuart->handle); - return ARM_DRIVER_OK; - - /* Abort receive */ - case ARM_USART_ABORT_RECEIVE: - LPUART_TransferAbortReceive(lpuart->resource->base, lpuart->handle); - return ARM_DRIVER_OK; - - default: - break; - } - - return LPUART_CommonControl(control, arg, lpuart->resource, &lpuart->isConfigured); -} - -static ARM_USART_STATUS LPUART_NonBlockingGetStatus(cmsis_lpuart_non_blocking_driver_state_t *lpuart) -{ - ARM_USART_STATUS stat; - uint32_t ksdk_lpuart_status = LPUART_GetStatusFlags(lpuart->resource->base); - - stat.tx_busy = ((kLPUART_TxBusy == lpuart->handle->txState) ? (1U) : (0U)); - stat.rx_busy = ((kLPUART_RxBusy == lpuart->handle->rxState) ? (1U) : (0U)); - - stat.tx_underflow = 0U; - stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag))); -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag))); -#else - stat.rx_break = 0U; -#endif - stat.rx_framing_error = (!(!(ksdk_lpuart_status & kLPUART_FramingErrorFlag))); - stat.rx_parity_error = (!(!(ksdk_lpuart_status & kLPUART_ParityErrorFlag))); - - return stat; -} - -#endif - -#if defined(LPUART0) && RTE_USART0 - -extern uint32_t LPUART0_GetFreq(void); -extern void LPUART0_InitPins(void); -extern void LPUART0_DeinitPins(void); - -cmsis_lpuart_resource_t LPUART0_Resource = {LPUART0, LPUART0_GetFreq}; - -#if RTE_USART0_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_lpuart_dma_resource_t LPUART0_DmaResource = { - RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_TX_PERI_SEL, - - RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_DMAMUX_BASE, RTE_USART0_DMA_RX_PERI_SEL, -}; - -lpuart_dma_handle_t LPUART0_DmaHandle; -dma_handle_t LPUART0_DmaRxHandle; -dma_handle_t LPUART0_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart0_dma_driver_state") -cmsis_lpuart_dma_driver_state_t LPUART0_DmaDriverState = { -#else -cmsis_lpuart_dma_driver_state_t LPUART0_DmaDriverState = { -#endif - &LPUART0_Resource, &LPUART0_DmaResource, &LPUART0_DmaHandle, &LPUART0_DmaRxHandle, &LPUART0_DmaTxHandle, -}; - -static int32_t LPUART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART0_InitPins(); - return LPUART_DmaInitialize(cb_event, &LPUART0_DmaDriverState); -} - -static int32_t LPUART0_DmaUninitialize(void) -{ - LPUART0_DeinitPins(); - return LPUART_DmaUninitialize(&LPUART0_DmaDriverState); -} - -static int32_t LPUART0_DmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_DmaPowerControl(state, &LPUART0_DmaDriverState); -} - -static int32_t LPUART0_DmaSend(const void *data, uint32_t num) -{ - return LPUART_DmaSend(data, num, &LPUART0_DmaDriverState); -} - -static int32_t LPUART0_DmaReceive(void *data, uint32_t num) -{ - return LPUART_DmaReceive(data, num, &LPUART0_DmaDriverState); -} - -static int32_t LPUART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_DmaTransfer(data_out, data_in, num, &LPUART0_DmaDriverState); -} - -static uint32_t LPUART0_DmaGetTxCount(void) -{ - return LPUART_DmaGetTxCount(&LPUART0_DmaDriverState); -} - -static uint32_t LPUART0_DmaGetRxCount(void) -{ - return LPUART_DmaGetRxCount(&LPUART0_DmaDriverState); -} - -static int32_t LPUART0_DmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_DmaControl(control, arg, &LPUART0_DmaDriverState); -} - -static ARM_USART_STATUS LPUART0_DmaGetStatus(void) -{ - return LPUART_DmaGetStatus(&LPUART0_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_lpuart_edma_resource_t LPUART0_EdmaResource = { - RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_TX_PERI_SEL, - - RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_DMAMUX_BASE, RTE_USART0_DMA_RX_PERI_SEL, -}; - -lpuart_edma_handle_t LPUART0_EdmaHandle; -edma_handle_t LPUART0_EdmaRxHandle; -edma_handle_t LPUART0_EdmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart0_edma_driver_state") -cmsis_lpuart_edma_driver_state_t LPUART0_EdmaDriverState = { -#else -cmsis_lpuart_edma_driver_state_t LPUART0_EdmaDriverState = { -#endif - &LPUART0_Resource, &LPUART0_EdmaResource, &LPUART0_EdmaHandle, &LPUART0_EdmaRxHandle, &LPUART0_EdmaTxHandle, -}; - -static int32_t LPUART0_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART0_InitPins(); - return LPUART_EdmaInitialize(cb_event, &LPUART0_EdmaDriverState); -} - -static int32_t LPUART0_EdmaUninitialize(void) -{ - LPUART0_DeinitPins(); - return LPUART_EdmaUninitialize(&LPUART0_EdmaDriverState); -} - -static int32_t LPUART0_EdmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_EdmaPowerControl(state, &LPUART0_EdmaDriverState); -} - -static int32_t LPUART0_EdmaSend(const void *data, uint32_t num) -{ - return LPUART_EdmaSend(data, num, &LPUART0_EdmaDriverState); -} - -static int32_t LPUART0_EdmaReceive(void *data, uint32_t num) -{ - return LPUART_EdmaReceive(data, num, &LPUART0_EdmaDriverState); -} - -static int32_t LPUART0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART0_EdmaDriverState); -} - -static uint32_t LPUART0_EdmaGetTxCount(void) -{ - return LPUART_EdmaGetTxCount(&LPUART0_EdmaDriverState); -} - -static uint32_t LPUART0_EdmaGetRxCount(void) -{ - return LPUART_EdmaGetRxCount(&LPUART0_EdmaDriverState); -} - -static int32_t LPUART0_EdmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_EdmaControl(control, arg, &LPUART0_EdmaDriverState); -} - -static ARM_USART_STATUS LPUART0_EdmaGetStatus(void) -{ - return LPUART_EdmaGetStatus(&LPUART0_EdmaDriverState); -} - -#endif - -#else - -lpuart_handle_t LPUART0_Handle; - -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart0_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart1_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart0_non_blocking_driver_state") -cmsis_lpuart_non_blocking_driver_state_t LPUART0_NonBlockingDriverState = { -#else -cmsis_lpuart_non_blocking_driver_state_t LPUART0_NonBlockingDriverState = { -#endif - &LPUART0_Resource, &LPUART0_Handle, -}; - -static int32_t LPUART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART0_InitPins(); - return LPUART_NonBlockingInitialize(cb_event, &LPUART0_NonBlockingDriverState); -} - -static int32_t LPUART0_NonBlockingUninitialize(void) -{ - LPUART0_DeinitPins(); - return LPUART_NonBlockingUninitialize(&LPUART0_NonBlockingDriverState); -} - -static int32_t LPUART0_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = LPUART_NonBlockingPowerControl(state, &LPUART0_NonBlockingDriverState); - -#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (LPUART0_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - LPUART_TransferStartRingBuffer(LPUART0_NonBlockingDriverState.resource->base, - LPUART0_NonBlockingDriverState.handle, lpuart0_rxRingBuffer, - USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t LPUART0_NonBlockingSend(const void *data, uint32_t num) -{ - return LPUART_NonBlockingSend(data, num, &LPUART0_NonBlockingDriverState); -} - -static int32_t LPUART0_NonBlockingReceive(void *data, uint32_t num) -{ - return LPUART_NonBlockingReceive(data, num, &LPUART0_NonBlockingDriverState); -} - -static int32_t LPUART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART0_NonBlockingDriverState); -} - -static uint32_t LPUART0_NonBlockingGetTxCount(void) -{ - return LPUART_NonBlockingGetTxCount(&LPUART0_NonBlockingDriverState); -} - -static uint32_t LPUART0_NonBlockingGetRxCount(void) -{ - return LPUART_NonBlockingGetRxCount(&LPUART0_NonBlockingDriverState); -} - -static int32_t LPUART0_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = LPUART_NonBlockingControl(control, arg, &LPUART0_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } - - /* Enable the receive interrupts if ring buffer is used */ - if (LPUART0_NonBlockingDriverState.handle->rxRingBuffer != NULL) - { - LPUART_EnableInterrupts(LPUART0_NonBlockingDriverState.resource->base, - kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS LPUART0_NonBlockingGetStatus(void) -{ - return LPUART_NonBlockingGetStatus(&LPUART0_NonBlockingDriverState); -} - -#endif - -#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) -#if (FSL_FEATURE_SOC_UART_COUNT == 3) -ARM_DRIVER_USART Driver_USART3 = { -#elif(FSL_FEATURE_SOC_UART_COUNT == 4) -ARM_DRIVER_USART Driver_USART4 = { -#elif(FSL_FEATURE_SOC_UART_COUNT == 5) -ARM_DRIVER_USART Driver_USART5 = { -#else -ARM_DRIVER_USART Driver_USART0 = { -#endif -#else -ARM_DRIVER_USART Driver_USART0 = { -#endif - - LPUARTx_GetVersion, LPUARTx_GetCapabilities, -#if RTE_USART0_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - LPUART0_EdmaInitialize, LPUART0_EdmaUninitialize, LPUART0_EdmaPowerControl, LPUART0_EdmaSend, - LPUART0_EdmaReceive, LPUART0_EdmaTransfer, LPUART0_EdmaGetTxCount, LPUART0_EdmaGetRxCount, - LPUART0_EdmaControl, LPUART0_EdmaGetStatus, -#else - LPUART0_DmaInitialize, LPUART0_DmaUninitialize, LPUART0_DmaPowerControl, LPUART0_DmaSend, LPUART0_DmaReceive, - LPUART0_DmaTransfer, LPUART0_DmaGetTxCount, LPUART0_DmaGetRxCount, LPUART0_DmaControl, LPUART0_DmaGetStatus, -#endif -#else - LPUART0_NonBlockingInitialize, - LPUART0_NonBlockingUninitialize, - LPUART0_NonBlockingPowerControl, - LPUART0_NonBlockingSend, - LPUART0_NonBlockingReceive, - LPUART0_NonBlockingTransfer, - LPUART0_NonBlockingGetTxCount, - LPUART0_NonBlockingGetRxCount, - LPUART0_NonBlockingControl, - LPUART0_NonBlockingGetStatus, -#endif - LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; - -#endif /* LPUART0 */ - -#if defined(LPUART1) && RTE_USART1 - -extern uint32_t LPUART1_GetFreq(void); -extern void LPUART1_InitPins(void); -extern void LPUART1_DeinitPins(void); - -cmsis_lpuart_resource_t LPUART1_Resource = {LPUART1, LPUART1_GetFreq}; - -#if RTE_USART1_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_lpuart_dma_resource_t LPUART1_DmaResource = { - RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_TX_PERI_SEL, - - RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_DMAMUX_BASE, RTE_USART1_DMA_RX_PERI_SEL, -}; - -lpuart_dma_handle_t LPUART1_DmaHandle; -dma_handle_t LPUART1_DmaRxHandle; -dma_handle_t LPUART1_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart1_dma_driver_state") -cmsis_lpuart_dma_driver_state_t LPUART1_DmaDriverState = { -#else -cmsis_lpuart_dma_driver_state_t LPUART1_DmaDriverState = { -#endif - &LPUART1_Resource, &LPUART1_DmaResource, &LPUART1_DmaHandle, &LPUART1_DmaRxHandle, &LPUART1_DmaTxHandle, -}; - -static int32_t LPUART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART1_InitPins(); - return LPUART_DmaInitialize(cb_event, &LPUART1_DmaDriverState); -} - -static int32_t LPUART1_DmaUninitialize(void) -{ - LPUART1_DeinitPins(); - return LPUART_DmaUninitialize(&LPUART1_DmaDriverState); -} - -static int32_t LPUART1_DmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_DmaPowerControl(state, &LPUART1_DmaDriverState); -} - -static int32_t LPUART1_DmaSend(const void *data, uint32_t num) -{ - return LPUART_DmaSend(data, num, &LPUART1_DmaDriverState); -} - -static int32_t LPUART1_DmaReceive(void *data, uint32_t num) -{ - return LPUART_DmaReceive(data, num, &LPUART1_DmaDriverState); -} - -static int32_t LPUART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_DmaTransfer(data_out, data_in, num, &LPUART1_DmaDriverState); -} - -static uint32_t LPUART1_DmaGetTxCount(void) -{ - return LPUART_DmaGetTxCount(&LPUART1_DmaDriverState); -} - -static uint32_t LPUART1_DmaGetRxCount(void) -{ - return LPUART_DmaGetRxCount(&LPUART1_DmaDriverState); -} - -static int32_t LPUART1_DmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_DmaControl(control, arg, &LPUART1_DmaDriverState); -} - -static ARM_USART_STATUS LPUART1_DmaGetStatus(void) -{ - return LPUART_DmaGetStatus(&LPUART1_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_lpuart_edma_resource_t LPUART1_EdmaResource = { - RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_TX_PERI_SEL, - - RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_DMAMUX_BASE, RTE_USART1_DMA_RX_PERI_SEL, -}; - -lpuart_edma_handle_t LPUART1_EdmaHandle; -edma_handle_t LPUART1_EdmaRxHandle; -edma_handle_t LPUART1_EdmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart1_edma_driver_state") -cmsis_lpuart_edma_driver_state_t LPUART1_EdmaDriverState = { -#else -cmsis_lpuart_edma_driver_state_t LPUART1_EdmaDriverState = { -#endif - &LPUART1_Resource, &LPUART1_EdmaResource, &LPUART1_EdmaHandle, &LPUART1_EdmaRxHandle, &LPUART1_EdmaTxHandle, -}; - -static int32_t LPUART1_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART1_InitPins(); - return LPUART_EdmaInitialize(cb_event, &LPUART1_EdmaDriverState); -} - -static int32_t LPUART1_EdmaUninitialize(void) -{ - LPUART1_DeinitPins(); - return LPUART_EdmaUninitialize(&LPUART1_EdmaDriverState); -} - -static int32_t LPUART1_EdmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_EdmaPowerControl(state, &LPUART1_EdmaDriverState); -} - -static int32_t LPUART1_EdmaSend(const void *data, uint32_t num) -{ - return LPUART_EdmaSend(data, num, &LPUART1_EdmaDriverState); -} - -static int32_t LPUART1_EdmaReceive(void *data, uint32_t num) -{ - return LPUART_EdmaReceive(data, num, &LPUART1_EdmaDriverState); -} - -static int32_t LPUART1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART1_EdmaDriverState); -} - -static uint32_t LPUART1_EdmaGetTxCount(void) -{ - return LPUART_EdmaGetTxCount(&LPUART1_EdmaDriverState); -} - -static uint32_t LPUART1_EdmaGetRxCount(void) -{ - return LPUART_EdmaGetRxCount(&LPUART1_EdmaDriverState); -} - -static int32_t LPUART1_EdmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_EdmaControl(control, arg, &LPUART1_EdmaDriverState); -} - -static ARM_USART_STATUS LPUART1_EdmaGetStatus(void) -{ - return LPUART_EdmaGetStatus(&LPUART1_EdmaDriverState); -} - -#endif - -#else - -lpuart_handle_t LPUART1_Handle; - -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart1_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart2_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart1_non_blocking_driver_state") -cmsis_lpuart_non_blocking_driver_state_t LPUART1_NonBlockingDriverState = { -#else -cmsis_lpuart_non_blocking_driver_state_t LPUART1_NonBlockingDriverState = { -#endif - &LPUART1_Resource, &LPUART1_Handle, -}; - -static int32_t LPUART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART1_InitPins(); - return LPUART_NonBlockingInitialize(cb_event, &LPUART1_NonBlockingDriverState); -} - -static int32_t LPUART1_NonBlockingUninitialize(void) -{ - LPUART1_DeinitPins(); - return LPUART_NonBlockingUninitialize(&LPUART1_NonBlockingDriverState); -} - -static int32_t LPUART1_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = LPUART_NonBlockingPowerControl(state, &LPUART1_NonBlockingDriverState); - -#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (LPUART1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - LPUART_TransferStartRingBuffer(LPUART1_NonBlockingDriverState.resource->base, - LPUART1_NonBlockingDriverState.handle, lpuart1_rxRingBuffer, - USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t LPUART1_NonBlockingSend(const void *data, uint32_t num) -{ - return LPUART_NonBlockingSend(data, num, &LPUART1_NonBlockingDriverState); -} - -static int32_t LPUART1_NonBlockingReceive(void *data, uint32_t num) -{ - return LPUART_NonBlockingReceive(data, num, &LPUART1_NonBlockingDriverState); -} - -static int32_t LPUART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART1_NonBlockingDriverState); -} - -static uint32_t LPUART1_NonBlockingGetTxCount(void) -{ - return LPUART_NonBlockingGetTxCount(&LPUART1_NonBlockingDriverState); -} - -static uint32_t LPUART1_NonBlockingGetRxCount(void) -{ - return LPUART_NonBlockingGetRxCount(&LPUART1_NonBlockingDriverState); -} - -static int32_t LPUART1_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = LPUART_NonBlockingControl(control, arg, &LPUART1_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } - - /* Enable the receive interrupts if ring buffer is used */ - if (LPUART1_NonBlockingDriverState.handle->rxRingBuffer != NULL) - { - LPUART_EnableInterrupts(LPUART1_NonBlockingDriverState.resource->base, - kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS LPUART1_NonBlockingGetStatus(void) -{ - return LPUART_NonBlockingGetStatus(&LPUART1_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART1 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, -#if RTE_USART1_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - LPUART1_EdmaInitialize, LPUART1_EdmaUninitialize, LPUART1_EdmaPowerControl, - LPUART1_EdmaSend, LPUART1_EdmaReceive, LPUART1_EdmaTransfer, - LPUART1_EdmaGetTxCount, LPUART1_EdmaGetRxCount, LPUART1_EdmaControl, - LPUART1_EdmaGetStatus, -#else - LPUART1_DmaInitialize, LPUART1_DmaUninitialize, LPUART1_DmaPowerControl, - LPUART1_DmaSend, LPUART1_DmaReceive, LPUART1_DmaTransfer, - LPUART1_DmaGetTxCount, LPUART1_DmaGetRxCount, LPUART1_DmaControl, - LPUART1_DmaGetStatus, -#endif -#else - LPUART1_NonBlockingInitialize, - LPUART1_NonBlockingUninitialize, - LPUART1_NonBlockingPowerControl, - LPUART1_NonBlockingSend, - LPUART1_NonBlockingReceive, - LPUART1_NonBlockingTransfer, - LPUART1_NonBlockingGetTxCount, - LPUART1_NonBlockingGetRxCount, - LPUART1_NonBlockingControl, - LPUART1_NonBlockingGetStatus, -#endif - LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; - -#endif /* LPUART1 */ - -#if defined(LPUART2) && RTE_USART2 - -extern uint32_t LPUART2_GetFreq(void); -extern void LPUART2_InitPins(void); -extern void LPUART2_DeinitPins(void); - -cmsis_lpuart_resource_t LPUART2_Resource = {LPUART2, LPUART2_GetFreq}; - -#if RTE_USART2_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_lpuart_dma_resource_t LPUART2_DmaResource = { - RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_TX_PERI_SEL, - - RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_DMAMUX_BASE, RTE_USART2_DMA_RX_PERI_SEL, -}; - -lpuart_dma_handle_t LPUART2_DmaHandle; -dma_handle_t LPUART2_DmaRxHandle; -dma_handle_t LPUART2_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart2_dma_driver_state") -cmsis_lpuart_dma_driver_state_t LPUART2_DmaDriverState = { -#else -cmsis_lpuart_dma_driver_state_t LPUART2_DmaDriverState = { -#endif - &LPUART2_Resource, &LPUART2_DmaResource, &LPUART2_DmaHandle, &LPUART2_DmaRxHandle, &LPUART2_DmaTxHandle, -}; - -static int32_t LPUART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART2_InitPins(); - return LPUART_DmaInitialize(cb_event, &LPUART2_DmaDriverState); -} - -static int32_t LPUART2_DmaUninitialize(void) -{ - LPUART2_DeinitPins(); - return LPUART_DmaUninitialize(&LPUART2_DmaDriverState); -} - -static int32_t LPUART2_DmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_DmaPowerControl(state, &LPUART2_DmaDriverState); -} - -static int32_t LPUART2_DmaSend(const void *data, uint32_t num) -{ - return LPUART_DmaSend(data, num, &LPUART2_DmaDriverState); -} - -static int32_t LPUART2_DmaReceive(void *data, uint32_t num) -{ - return LPUART_DmaReceive(data, num, &LPUART2_DmaDriverState); -} - -static int32_t LPUART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_DmaTransfer(data_out, data_in, num, &LPUART2_DmaDriverState); -} - -static uint32_t LPUART2_DmaGetTxCount(void) -{ - return LPUART_DmaGetTxCount(&LPUART2_DmaDriverState); -} - -static uint32_t LPUART2_DmaGetRxCount(void) -{ - return LPUART_DmaGetRxCount(&LPUART2_DmaDriverState); -} - -static int32_t LPUART2_DmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_DmaControl(control, arg, &LPUART2_DmaDriverState); -} - -static ARM_USART_STATUS LPUART2_DmaGetStatus(void) -{ - return LPUART_DmaGetStatus(&LPUART2_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_lpuart_edma_resource_t LPUART2_EdmaResource = { - RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_TX_PERI_SEL, - - RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_DMAMUX_BASE, RTE_USART2_DMA_RX_PERI_SEL, -}; - -lpuart_edma_handle_t LPUART2_EdmaHandle; -edma_handle_t LPUART2_EdmaRxHandle; -edma_handle_t LPUART2_EdmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart2_edma_driver_state") -cmsis_lpuart_edma_driver_state_t LPUART2_EdmaDriverState = { -#else -cmsis_lpuart_edma_driver_state_t LPUART2_EdmaDriverState = { -#endif - &LPUART2_Resource, &LPUART2_EdmaResource, &LPUART2_EdmaHandle, &LPUART2_EdmaRxHandle, &LPUART2_EdmaTxHandle, -}; - -static int32_t LPUART2_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART2_InitPins(); - return LPUART_EdmaInitialize(cb_event, &LPUART2_EdmaDriverState); -} - -static int32_t LPUART2_EdmaUninitialize(void) -{ - LPUART2_DeinitPins(); - return LPUART_EdmaUninitialize(&LPUART2_EdmaDriverState); -} - -static int32_t LPUART2_EdmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_EdmaPowerControl(state, &LPUART2_EdmaDriverState); -} - -static int32_t LPUART2_EdmaSend(const void *data, uint32_t num) -{ - return LPUART_EdmaSend(data, num, &LPUART2_EdmaDriverState); -} - -static int32_t LPUART2_EdmaReceive(void *data, uint32_t num) -{ - return LPUART_EdmaReceive(data, num, &LPUART2_EdmaDriverState); -} - -static int32_t LPUART2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART2_EdmaDriverState); -} - -static uint32_t LPUART2_EdmaGetTxCount(void) -{ - return LPUART_EdmaGetTxCount(&LPUART2_EdmaDriverState); -} - -static uint32_t LPUART2_EdmaGetRxCount(void) -{ - return LPUART_EdmaGetRxCount(&LPUART2_EdmaDriverState); -} - -static int32_t LPUART2_EdmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_EdmaControl(control, arg, &LPUART2_EdmaDriverState); -} - -static ARM_USART_STATUS LPUART2_EdmaGetStatus(void) -{ - return LPUART_EdmaGetStatus(&LPUART2_EdmaDriverState); -} - -#endif - -#else - -lpuart_handle_t LPUART2_Handle; - -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart2_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart3_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart2_non_blocking_driver_state") -cmsis_lpuart_non_blocking_driver_state_t LPUART2_NonBlockingDriverState = { -#else -cmsis_lpuart_non_blocking_driver_state_t LPUART2_NonBlockingDriverState = { -#endif - &LPUART2_Resource, &LPUART2_Handle, -}; - -static int32_t LPUART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART2_InitPins(); - return LPUART_NonBlockingInitialize(cb_event, &LPUART2_NonBlockingDriverState); -} - -static int32_t LPUART2_NonBlockingUninitialize(void) -{ - LPUART2_DeinitPins(); - return LPUART_NonBlockingUninitialize(&LPUART2_NonBlockingDriverState); -} - -static int32_t LPUART2_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = LPUART_NonBlockingPowerControl(state, &LPUART2_NonBlockingDriverState); - -#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (LPUART2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - LPUART_TransferStartRingBuffer(LPUART2_NonBlockingDriverState.resource->base, - LPUART2_NonBlockingDriverState.handle, lpuart2_rxRingBuffer, - USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t LPUART2_NonBlockingSend(const void *data, uint32_t num) -{ - return LPUART_NonBlockingSend(data, num, &LPUART2_NonBlockingDriverState); -} - -static int32_t LPUART2_NonBlockingReceive(void *data, uint32_t num) -{ - return LPUART_NonBlockingReceive(data, num, &LPUART2_NonBlockingDriverState); -} - -static int32_t LPUART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART2_NonBlockingDriverState); -} - -static uint32_t LPUART2_NonBlockingGetTxCount(void) -{ - return LPUART_NonBlockingGetTxCount(&LPUART2_NonBlockingDriverState); -} - -static uint32_t LPUART2_NonBlockingGetRxCount(void) -{ - return LPUART_NonBlockingGetRxCount(&LPUART2_NonBlockingDriverState); -} - -static int32_t LPUART2_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = LPUART_NonBlockingControl(control, arg, &LPUART2_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } - - /* Enable the receive interrupts if ring buffer is used */ - if (LPUART2_NonBlockingDriverState.handle->rxRingBuffer != NULL) - { - LPUART_EnableInterrupts(LPUART2_NonBlockingDriverState.resource->base, - kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS LPUART2_NonBlockingGetStatus(void) -{ - return LPUART_NonBlockingGetStatus(&LPUART2_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART2 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, -#if RTE_USART2_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - LPUART2_EdmaInitialize, LPUART2_EdmaUninitialize, LPUART2_EdmaPowerControl, - LPUART2_EdmaSend, LPUART2_EdmaReceive, LPUART2_EdmaTransfer, - LPUART2_EdmaGetTxCount, LPUART2_EdmaGetRxCount, LPUART2_EdmaControl, - LPUART2_EdmaGetStatus, -#else - LPUART2_DmaInitialize, LPUART2_DmaUninitialize, LPUART2_DmaPowerControl, - LPUART2_DmaSend, LPUART2_DmaReceive, LPUART2_DmaTransfer, - LPUART2_DmaGetTxCount, LPUART2_DmaGetRxCount, LPUART2_DmaControl, - LPUART2_DmaGetStatus, -#endif -#else - LPUART2_NonBlockingInitialize, - LPUART2_NonBlockingUninitialize, - LPUART2_NonBlockingPowerControl, - LPUART2_NonBlockingSend, - LPUART2_NonBlockingReceive, - LPUART2_NonBlockingTransfer, - LPUART2_NonBlockingGetTxCount, - LPUART2_NonBlockingGetRxCount, - LPUART2_NonBlockingControl, - LPUART2_NonBlockingGetStatus, -#endif - LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; - -#endif /* LPUART2 */ - -#if defined(LPUART3) && RTE_USART3 - -extern uint32_t LPUART3_GetFreq(void); -extern void LPUART3_InitPins(void); -extern void LPUART3_DeinitPins(void); - -cmsis_lpuart_resource_t LPUART3_Resource = {LPUART3, LPUART3_GetFreq}; - -#if RTE_USART3_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_lpuart_dma_resource_t LPUART3_DmaResource = { - RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_TX_PERI_SEL, - - RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_DMAMUX_BASE, RTE_USART3_DMA_RX_PERI_SEL, -}; - -lpuart_dma_handle_t LPUART3_DmaHandle; -dma_handle_t LPUART3_DmaRxHandle; -dma_handle_t LPUART3_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart3_dma_driver_state") -cmsis_lpuart_dma_driver_state_t LPUART3_DmaDriverState = { -#else -cmsis_lpuart_dma_driver_state_t LPUART3_DmaDriverState = { -#endif - &LPUART3_Resource, &LPUART3_DmaResource, &LPUART3_DmaHandle, &LPUART3_DmaRxHandle, &LPUART3_DmaTxHandle, -}; - -static int32_t LPUART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART3_InitPins(); - return LPUART_DmaInitialize(cb_event, &LPUART3_DmaDriverState); -} - -static int32_t LPUART3_DmaUninitialize(void) -{ - LPUART3_DeinitPins(); - return LPUART_DmaUninitialize(&LPUART3_DmaDriverState); -} - -static int32_t LPUART3_DmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_DmaPowerControl(state, &LPUART3_DmaDriverState); -} - -static int32_t LPUART3_DmaSend(const void *data, uint32_t num) -{ - return LPUART_DmaSend(data, num, &LPUART3_DmaDriverState); -} - -static int32_t LPUART3_DmaReceive(void *data, uint32_t num) -{ - return LPUART_DmaReceive(data, num, &LPUART3_DmaDriverState); -} - -static int32_t LPUART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_DmaTransfer(data_out, data_in, num, &LPUART3_DmaDriverState); -} - -static uint32_t LPUART3_DmaGetTxCount(void) -{ - return LPUART_DmaGetTxCount(&LPUART3_DmaDriverState); -} - -static uint32_t LPUART3_DmaGetRxCount(void) -{ - return LPUART_DmaGetRxCount(&LPUART3_DmaDriverState); -} - -static int32_t LPUART3_DmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_DmaControl(control, arg, &LPUART3_DmaDriverState); -} - -static ARM_USART_STATUS LPUART3_DmaGetStatus(void) -{ - return LPUART_DmaGetStatus(&LPUART3_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_lpuart_edma_resource_t LPUART3_EdmaResource = { - RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_TX_PERI_SEL, - - RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_DMAMUX_BASE, RTE_USART3_DMA_RX_PERI_SEL, -}; - -lpuart_edma_handle_t LPUART3_EdmaHandle; -edma_handle_t LPUART3_EdmaRxHandle; -edma_handle_t LPUART3_EdmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart3_edma_driver_state") -cmsis_lpuart_edma_driver_state_t LPUART3_EdmaDriverState = { -#else -cmsis_lpuart_edma_driver_state_t LPUART3_EdmaDriverState = { -#endif - &LPUART3_Resource, &LPUART3_EdmaResource, &LPUART3_EdmaHandle, &LPUART3_EdmaRxHandle, &LPUART3_EdmaTxHandle, -}; - -static int32_t LPUART3_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART3_InitPins(); - return LPUART_EdmaInitialize(cb_event, &LPUART3_EdmaDriverState); -} - -static int32_t LPUART3_EdmaUninitialize(void) -{ - LPUART3_DeinitPins(); - return LPUART_EdmaUninitialize(&LPUART3_EdmaDriverState); -} - -static int32_t LPUART3_EdmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_EdmaPowerControl(state, &LPUART3_EdmaDriverState); -} - -static int32_t LPUART3_EdmaSend(const void *data, uint32_t num) -{ - return LPUART_EdmaSend(data, num, &LPUART3_EdmaDriverState); -} - -static int32_t LPUART3_EdmaReceive(void *data, uint32_t num) -{ - return LPUART_EdmaReceive(data, num, &LPUART3_EdmaDriverState); -} - -static int32_t LPUART3_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART3_EdmaDriverState); -} - -static uint32_t LPUART3_EdmaGetTxCount(void) -{ - return LPUART_EdmaGetTxCount(&LPUART3_EdmaDriverState); -} - -static uint32_t LPUART3_EdmaGetRxCount(void) -{ - return LPUART_EdmaGetRxCount(&LPUART3_EdmaDriverState); -} - -static int32_t LPUART3_EdmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_EdmaControl(control, arg, &LPUART3_EdmaDriverState); -} - -static ARM_USART_STATUS LPUART3_EdmaGetStatus(void) -{ - return LPUART_EdmaGetStatus(&LPUART3_EdmaDriverState); -} - -#endif - -#else - -lpuart_handle_t LPUART3_Handle; - -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart3_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart4_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart3_non_blocking_driver_state") -cmsis_lpuart_non_blocking_driver_state_t LPUART3_NonBlockingDriverState = { -#else -cmsis_lpuart_non_blocking_driver_state_t LPUART3_NonBlockingDriverState = { -#endif - &LPUART3_Resource, &LPUART3_Handle, -}; - -static int32_t LPUART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART3_InitPins(); - return LPUART_NonBlockingInitialize(cb_event, &LPUART3_NonBlockingDriverState); -} - -static int32_t LPUART3_NonBlockingUninitialize(void) -{ - LPUART3_DeinitPins(); - return LPUART_NonBlockingUninitialize(&LPUART3_NonBlockingDriverState); -} - -static int32_t LPUART3_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = LPUART_NonBlockingPowerControl(state, &LPUART3_NonBlockingDriverState); - -#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (LPUART3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - LPUART_TransferStartRingBuffer(LPUART3_NonBlockingDriverState.resource->base, - LPUART3_NonBlockingDriverState.handle, lpuart3_rxRingBuffer, - USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t LPUART3_NonBlockingSend(const void *data, uint32_t num) -{ - return LPUART_NonBlockingSend(data, num, &LPUART3_NonBlockingDriverState); -} - -static int32_t LPUART3_NonBlockingReceive(void *data, uint32_t num) -{ - return LPUART_NonBlockingReceive(data, num, &LPUART3_NonBlockingDriverState); -} - -static int32_t LPUART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART3_NonBlockingDriverState); -} - -static uint32_t LPUART3_NonBlockingGetTxCount(void) -{ - return LPUART_NonBlockingGetTxCount(&LPUART3_NonBlockingDriverState); -} - -static uint32_t LPUART3_NonBlockingGetRxCount(void) -{ - return LPUART_NonBlockingGetRxCount(&LPUART3_NonBlockingDriverState); -} - -static int32_t LPUART3_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = LPUART_NonBlockingControl(control, arg, &LPUART3_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } - - /* Enable the receive interrupts if ring buffer is used */ - if (LPUART3_NonBlockingDriverState.handle->rxRingBuffer != NULL) - { - LPUART_EnableInterrupts(LPUART3_NonBlockingDriverState.resource->base, - kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS LPUART3_NonBlockingGetStatus(void) -{ - return LPUART_NonBlockingGetStatus(&LPUART3_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART3 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, -#if RTE_USART3_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - LPUART3_EdmaInitialize, LPUART3_EdmaUninitialize, LPUART3_EdmaPowerControl, - LPUART3_EdmaSend, LPUART3_EdmaReceive, LPUART3_EdmaTransfer, - LPUART3_EdmaGetTxCount, LPUART3_EdmaGetRxCount, LPUART3_EdmaControl, - LPUART3_EdmaGetStatus, -#else - LPUART3_DmaInitialize, LPUART3_DmaUninitialize, LPUART3_DmaPowerControl, - LPUART3_DmaSend, LPUART3_DmaReceive, LPUART3_DmaTransfer, - LPUART3_DmaGetTxCount, LPUART3_DmaGetRxCount, LPUART3_DmaControl, - LPUART3_DmaGetStatus, -#endif -#else - LPUART3_NonBlockingInitialize, - LPUART3_NonBlockingUninitialize, - LPUART3_NonBlockingPowerControl, - LPUART3_NonBlockingSend, - LPUART3_NonBlockingReceive, - LPUART3_NonBlockingTransfer, - LPUART3_NonBlockingGetTxCount, - LPUART3_NonBlockingGetRxCount, - LPUART3_NonBlockingControl, - LPUART3_NonBlockingGetStatus, -#endif - LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; - -#endif /* LPUART3 */ - -#if defined(LPUART4) && RTE_USART4 - -extern uint32_t LPUART4_GetFreq(void); -extern void LPUART4_InitPins(void); -extern void LPUART4_DeinitPins(void); - -cmsis_lpuart_resource_t LPUART4_Resource = {LPUART4, LPUART4_GetFreq}; - -#if RTE_USART4_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_lpuart_dma_resource_t LPUART4_DmaResource = { - RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_TX_PERI_SEL, - - RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_DMAMUX_BASE, RTE_USART4_DMA_RX_PERI_SEL, -}; - -lpuart_dma_handle_t LPUART4_DmaHandle; -dma_handle_t LPUART4_DmaRxHandle; -dma_handle_t LPUART4_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart4_dma_driver_state") -cmsis_lpuart_dma_driver_state_t LPUART4_DmaDriverState = { -#else -cmsis_lpuart_dma_driver_state_t LPUART4_DmaDriverState = { -#endif - &LPUART4_Resource, &LPUART4_DmaResource, &LPUART4_DmaHandle, &LPUART4_DmaRxHandle, &LPUART4_DmaTxHandle}; - -static int32_t LPUART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART4_InitPins(); - return LPUART_DmaInitialize(cb_event, &LPUART4_DmaDriverState); -} - -static int32_t LPUART4_DmaUninitialize(void) -{ - LPUART4_DeinitPins(); - return LPUART_DmaUninitialize(&LPUART4_DmaDriverState); -} - -static int32_t LPUART4_DmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_DmaPowerControl(state, &LPUART4_DmaDriverState); -} - -static int32_t LPUART4_DmaSend(const void *data, uint32_t num) -{ - return LPUART_DmaSend(data, num, &LPUART4_DmaDriverState); -} - -static int32_t LPUART4_DmaReceive(void *data, uint32_t num) -{ - return LPUART_DmaReceive(data, num, &LPUART4_DmaDriverState); -} - -static int32_t LPUART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_DmaTransfer(data_out, data_in, num, &LPUART4_DmaDriverState); -} - -static uint32_t LPUART4_DmaGetTxCount(void) -{ - return LPUART_DmaGetTxCount(&LPUART4_DmaDriverState); -} - -static uint32_t LPUART4_DmaGetRxCount(void) -{ - return LPUART_DmaGetRxCount(&LPUART4_DmaDriverState); -} - -static int32_t LPUART4_DmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_DmaControl(control, arg, &LPUART4_DmaDriverState); -} - -static ARM_USART_STATUS LPUART4_DmaGetStatus(void) -{ - return LPUART_DmaGetStatus(&LPUART4_DmaDriverState); -} - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_lpuart_edma_resource_t LPUART4_EdmaResource = { - RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_TX_PERI_SEL, - - RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_DMAMUX_BASE, RTE_USART4_DMA_RX_PERI_SEL, -}; - -lpuart_edma_handle_t LPUART4_EdmaHandle; -edma_handle_t LPUART4_EdmaRxHandle; -edma_handle_t LPUART4_EdmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart4_edma_driver_state") -cmsis_lpuart_edma_driver_state_t LPUART4_EdmaDriverState = { -#else -cmsis_lpuart_edma_driver_state_t LPUART4_EdmaDriverState = { -#endif - &LPUART4_Resource, &LPUART4_EdmaResource, &LPUART4_EdmaHandle, &LPUART4_EdmaRxHandle, &LPUART4_EdmaTxHandle}; - -static int32_t LPUART4_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART4_InitPins(); - return LPUART_EdmaInitialize(cb_event, &LPUART4_EdmaDriverState); -} - -static int32_t LPUART4_EdmaUninitialize(void) -{ - LPUART4_DeinitPins(); - return LPUART_EdmaUninitialize(&LPUART4_EdmaDriverState); -} - -static int32_t LPUART4_EdmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_EdmaPowerControl(state, &LPUART4_EdmaDriverState); -} - -static int32_t LPUART4_EdmaSend(const void *data, uint32_t num) -{ - return LPUART_EdmaSend(data, num, &LPUART4_EdmaDriverState); -} - -static int32_t LPUART4_EdmaReceive(void *data, uint32_t num) -{ - return LPUART_EdmaReceive(data, num, &LPUART4_EdmaDriverState); -} - -static int32_t LPUART4_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART4_EdmaDriverState); -} - -static uint32_t LPUART4_EdmaGetTxCount(void) -{ - return LPUART_EdmaGetTxCount(&LPUART4_EdmaDriverState); -} - -static uint32_t LPUART4_EdmaGetRxCount(void) -{ - return LPUART_EdmaGetRxCount(&LPUART4_EdmaDriverState); -} - -static int32_t LPUART4_EdmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_EdmaControl(control, arg, &LPUART4_EdmaDriverState); -} - -static ARM_USART_STATUS LPUART4_EdmaGetStatus(void) -{ - return LPUART_EdmaGetStatus(&LPUART4_EdmaDriverState); -} - -#endif - -#else - -lpuart_handle_t LPUART4_Handle; - -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart4_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart5_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart4_non_blocking_driver_state") -cmsis_lpuart_non_blocking_driver_state_t LPUART4_NonBlockingDriverState = { -#else -cmsis_lpuart_non_blocking_driver_state_t LPUART4_NonBlockingDriverState = { -#endif - &LPUART4_Resource, &LPUART4_Handle, -}; - -static int32_t LPUART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART4_InitPins(); - return LPUART_NonBlockingInitialize(cb_event, &LPUART4_NonBlockingDriverState); -} - -static int32_t LPUART4_NonBlockingUninitialize(void) -{ - LPUART4_DeinitPins(); - return LPUART_NonBlockingUninitialize(&LPUART4_NonBlockingDriverState); -} - -static int32_t LPUART4_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = LPUART_NonBlockingPowerControl(state, &LPUART4_NonBlockingDriverState); - -#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (LPUART4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - LPUART_TransferStartRingBuffer(LPUART4_NonBlockingDriverState.resource->base, - LPUART4_NonBlockingDriverState.handle, lpuart4_rxRingBuffer, - USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t LPUART4_NonBlockingSend(const void *data, uint32_t num) -{ - return LPUART_NonBlockingSend(data, num, &LPUART4_NonBlockingDriverState); -} - -static int32_t LPUART4_NonBlockingReceive(void *data, uint32_t num) -{ - return LPUART_NonBlockingReceive(data, num, &LPUART4_NonBlockingDriverState); -} - -static int32_t LPUART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART4_NonBlockingDriverState); -} - -static uint32_t LPUART4_NonBlockingGetTxCount(void) -{ - return LPUART_NonBlockingGetTxCount(&LPUART4_NonBlockingDriverState); -} - -static uint32_t LPUART4_NonBlockingGetRxCount(void) -{ - return LPUART_NonBlockingGetRxCount(&LPUART4_NonBlockingDriverState); -} - -static int32_t LPUART4_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = LPUART_NonBlockingControl(control, arg, &LPUART4_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } - - /* Enable the receive interrupts if ring buffer is used */ - if (LPUART4_NonBlockingDriverState.handle->rxRingBuffer != NULL) - { - LPUART_EnableInterrupts(LPUART4_NonBlockingDriverState.resource->base, - kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS LPUART4_NonBlockingGetStatus(void) -{ - return LPUART_NonBlockingGetStatus(&LPUART4_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART4 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, -#if RTE_USART4_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - LPUART4_EdmaInitialize, LPUART4_EdmaUninitialize, LPUART4_EdmaPowerControl, - LPUART4_EdmaSend, LPUART4_EdmaReceive, LPUART4_EdmaTransfer, - LPUART4_EdmaGetTxCount, LPUART4_EdmaGetRxCount, LPUART4_EdmaControl, - LPUART4_EdmaGetStatus, -#else - LPUART4_DmaInitialize, LPUART4_DmaUninitialize, LPUART4_DmaPowerControl, - LPUART4_DmaSend, LPUART4_DmaReceive, LPUART4_DmaTransfer, - LPUART4_DmaGetTxCount, LPUART4_DmaGetRxCount, LPUART4_DmaControl, - LPUART4_DmaGetStatus, -#endif -#else - LPUART4_NonBlockingInitialize, - LPUART4_NonBlockingUninitialize, - LPUART4_NonBlockingPowerControl, - LPUART4_NonBlockingSend, - LPUART4_NonBlockingReceive, - LPUART4_NonBlockingTransfer, - LPUART4_NonBlockingGetTxCount, - LPUART4_NonBlockingGetRxCount, - LPUART4_NonBlockingControl, - LPUART4_NonBlockingGetStatus, -#endif - LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; - -#endif /* LPUART4 */ - -#if defined(LPUART5) && RTE_USART5 - -extern uint32_t LPUART5_GetFreq(void); -extern void LPUART5_InitPins(void); -extern void LPUART5_DeinitPins(void); - -cmsis_lpuart_resource_t LPUART5_Resource = {LPUART5, LPUART5_GetFreq}; - -#if RTE_USART5_DMA_EN - -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) - -cmsis_lpuart_dma_resource_t LPUART5_DmaResource = { - RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_TX_PERI_SEL, - - RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_DMAMUX_BASE, RTE_USART5_DMA_RX_PERI_SEL, -}; - -lpuart_dma_handle_t LPUART5_DmaHandle; -dma_handle_t LPUART5_DmaRxHandle; -dma_handle_t LPUART5_DmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart5_dma_driver_state") -cmsis_lpuart_dma_driver_state_t LPUART5_DmaDriverState = { -#else -cmsis_lpuart_dma_driver_state_t LPUART5_DmaDriverState = { -#endif - &LPUART5_Resource, &LPUART5_DmaResource, &LPUART5_DmaHandle, &LPUART5_DmaRxHandle, &LPUART5_DmaTxHandle, -}; - -static int32_t LPUART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART5_InitPins(); - return LPUART_DmaInitialize(cb_event, &LPUART5_DmaDriverState); -} - -static int32_t LPUART5_DmaUninitialize(void) -{ - LPUART5_DeinitPins(); - return LPUART_DmaUninitialize(&LPUART5_DmaDriverState); -} - -static int32_t LPUART5_DmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_DmaPowerControl(state, &LPUART5_DmaDriverState); -} - -static int32_t LPUART5_DmaSend(const void *data, uint32_t num) -{ - return LPUART_DmaSend(data, num, &LPUART5_DmaDriverState); -} - -static int32_t LPUART5_DmaReceive(void *data, uint32_t num) -{ - return LPUART_DmaReceive(data, num, &LPUART5_DmaDriverState); -} - -static int32_t LPUART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_DmaTransfer(data_out, data_in, num, &LPUART5_DmaDriverState); -} - -static uint32_t LPUART5_DmaGetTxCount(void) -{ - return LPUART_DmaGetTxCount(&LPUART5_DmaDriverState); -} - -static uint32_t LPUART5_DmaGetRxCount(void) -{ - return LPUART_DmaGetRxCount(&LPUART5_DmaDriverState); -} - -static int32_t LPUART5_DmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_DmaControl(control, arg, &LPUART5_DmaDriverState); -} - -static ARM_USART_STATUS LPUART5_DmaGetStatus(void) -{ - return LPUART_DmaGetStatus(&LPUART5_DmaDriverState); -} - -/* LPUART5 Driver Control Block */ - -#endif - -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - -cmsis_lpuart_edma_resource_t LPUART5_EdmaResource = { - RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_TX_PERI_SEL, - - RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_DMAMUX_BASE, RTE_USART5_DMA_RX_PERI_SEL, -}; - -lpuart_edma_handle_t LPUART5_EdmaHandle; -edma_handle_t LPUART5_EdmaRxHandle; -edma_handle_t LPUART5_EdmaTxHandle; - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart5_edma_driver_state") -cmsis_lpuart_edma_driver_state_t LPUART5_EdmaDriverState = { -#else -cmsis_lpuart_edma_driver_state_t LPUART5_EdmaDriverState = { -#endif - &LPUART5_Resource, &LPUART5_EdmaResource, &LPUART5_EdmaHandle, &LPUART5_EdmaRxHandle, &LPUART5_EdmaTxHandle, -}; - -static int32_t LPUART5_EdmaInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART5_InitPins(); - return LPUART_EdmaInitialize(cb_event, &LPUART5_EdmaDriverState); -} - -static int32_t LPUART5_EdmaUninitialize(void) -{ - LPUART5_DeinitPins(); - return LPUART_EdmaUninitialize(&LPUART5_EdmaDriverState); -} - -static int32_t LPUART5_EdmaPowerControl(ARM_POWER_STATE state) -{ - return LPUART_EdmaPowerControl(state, &LPUART5_EdmaDriverState); -} - -static int32_t LPUART5_EdmaSend(const void *data, uint32_t num) -{ - return LPUART_EdmaSend(data, num, &LPUART5_EdmaDriverState); -} - -static int32_t LPUART5_EdmaReceive(void *data, uint32_t num) -{ - return LPUART_EdmaReceive(data, num, &LPUART5_EdmaDriverState); -} - -static int32_t LPUART5_EdmaTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_EdmaTransfer(data_out, data_in, num, &LPUART5_EdmaDriverState); -} - -static uint32_t LPUART5_EdmaGetTxCount(void) -{ - return LPUART_EdmaGetTxCount(&LPUART5_EdmaDriverState); -} - -static uint32_t LPUART5_EdmaGetRxCount(void) -{ - return LPUART_EdmaGetRxCount(&LPUART5_EdmaDriverState); -} - -static int32_t LPUART5_EdmaControl(uint32_t control, uint32_t arg) -{ - return LPUART_EdmaControl(control, arg, &LPUART5_EdmaDriverState); -} - -static ARM_USART_STATUS LPUART5_EdmaGetStatus(void) -{ - return LPUART_EdmaGetStatus(&LPUART5_EdmaDriverState); -} - -#endif - -#else - -lpuart_handle_t LPUART5_Handle; - -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) -static uint8_t lpuart5_rxRingBuffer[USART_RX_BUFFER_LEN]; -#endif - -#if defined(__CC_ARM) -ARMCC_SECTION("lpuart5_non_blocking_driver_state") -cmsis_lpuart_non_blocking_driver_state_t LPUART5_NonBlockingDriverState = { -#else -cmsis_lpuart_non_blocking_driver_state_t LPUART5_NonBlockingDriverState = { -#endif - &LPUART5_Resource, &LPUART5_Handle, -}; - -static int32_t LPUART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) -{ - LPUART5_InitPins(); - return LPUART_NonBlockingInitialize(cb_event, &LPUART5_NonBlockingDriverState); -} - -static int32_t LPUART5_NonBlockingUninitialize(void) -{ - LPUART5_DeinitPins(); - return LPUART_NonBlockingUninitialize(&LPUART5_NonBlockingDriverState); -} - -static int32_t LPUART5_NonBlockingPowerControl(ARM_POWER_STATE state) -{ - uint32_t result; - - result = LPUART_NonBlockingPowerControl(state, &LPUART5_NonBlockingDriverState); - -#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) - if ((state == ARM_POWER_FULL) && (LPUART5_NonBlockingDriverState.handle->rxRingBuffer == NULL)) - { - LPUART_TransferStartRingBuffer(LPUART5_NonBlockingDriverState.resource->base, - LPUART5_NonBlockingDriverState.handle, lpuart5_rxRingBuffer, - USART_RX_BUFFER_LEN); - } -#endif - - return result; -} - -static int32_t LPUART5_NonBlockingSend(const void *data, uint32_t num) -{ - return LPUART_NonBlockingSend(data, num, &LPUART5_NonBlockingDriverState); -} - -static int32_t LPUART5_NonBlockingReceive(void *data, uint32_t num) -{ - return LPUART_NonBlockingReceive(data, num, &LPUART5_NonBlockingDriverState); -} - -static int32_t LPUART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) -{ - return LPUART_NonBlockingTransfer(data_out, data_in, num, &LPUART5_NonBlockingDriverState); -} - -static uint32_t LPUART5_NonBlockingGetTxCount(void) -{ - return LPUART_NonBlockingGetTxCount(&LPUART5_NonBlockingDriverState); -} - -static uint32_t LPUART5_NonBlockingGetRxCount(void) -{ - return LPUART_NonBlockingGetRxCount(&LPUART5_NonBlockingDriverState); -} - -static int32_t LPUART5_NonBlockingControl(uint32_t control, uint32_t arg) -{ - int32_t result; - - result = LPUART_NonBlockingControl(control, arg, &LPUART5_NonBlockingDriverState); - if (ARM_DRIVER_OK != result) - { - return result; - } - - /* Enable the receive interrupts if ring buffer is used */ - if (LPUART5_NonBlockingDriverState.handle->rxRingBuffer != NULL) - { - LPUART_EnableInterrupts(LPUART5_NonBlockingDriverState.resource->base, - kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - return ARM_DRIVER_OK; -} - -static ARM_USART_STATUS LPUART5_NonBlockingGetStatus(void) -{ - return LPUART_NonBlockingGetStatus(&LPUART5_NonBlockingDriverState); -} - -#endif - -ARM_DRIVER_USART Driver_USART5 = {LPUARTx_GetVersion, LPUARTx_GetCapabilities, -#if RTE_USART5_DMA_EN -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) - LPUART5_EdmaInitialize, LPUART5_EdmaUninitialize, LPUART5_EdmaPowerControl, - LPUART5_EdmaSend, LPUART5_EdmaReceive, LPUART5_EdmaTransfer, - LPUART5_EdmaGetTxCount, LPUART5_EdmaGetRxCount, LPUART5_EdmaControl, - LPUART5_EdmaGetStatus, -#else - LPUART5_DmaInitialize, LPUART5_DmaUninitialize, LPUART5_DmaPowerControl, - LPUART5_DmaSend, LPUART5_DmaReceive, LPUART5_DmaTransfer, - LPUART5_DmaGetTxCount, LPUART5_DmaGetRxCount, LPUART5_DmaControl, - LPUART5_DmaGetStatus, -#endif -#else - LPUART5_NonBlockingInitialize, - LPUART5_NonBlockingUninitialize, - LPUART5_NonBlockingPowerControl, - LPUART5_NonBlockingSend, - LPUART5_NonBlockingReceive, - LPUART5_NonBlockingTransfer, - LPUART5_NonBlockingGetTxCount, - LPUART5_NonBlockingGetRxCount, - LPUART5_NonBlockingControl, - LPUART5_NonBlockingGetStatus, -#endif - LPUARTx_SetModemControl, LPUARTx_GetModemStatus}; - -#endif /* LPUART5 */ diff --git a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.h b/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.h deleted file mode 100644 index b0b5b2ee2..000000000 --- a/third_party/nxp/MKW41Z4/cmsis_drivers/fsl_lpuart_cmsis.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_LPUART_CMSIS_H_ -#define _FSL_LPUART_CMSIS_H_ - -#include "fsl_common.h" -#include "Driver_USART.h" -#include "RTE_Device.h" -#include "fsl_lpuart.h" -#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) -#include "fsl_dmamux.h" -#endif -#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) -#include "fsl_lpuart_dma.h" -#endif -#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) -#include "fsl_lpuart_edma.h" -#endif - -#if defined(LPUART0) -extern ARM_DRIVER_USART Driver_USART0; -#endif /* LPUART0 */ - -#if defined(LPUART1) -extern ARM_DRIVER_USART Driver_USART1; -#endif /* LPUART1 */ - -#if defined(LPUART2) -extern ARM_DRIVER_USART Driver_USART2; -#endif /* LPUART2 */ - -#if defined(LPUART3) -extern ARM_DRIVER_USART Driver_USART3; -#endif /* LPUART3 */ - -#if defined(LPUART4) -extern ARM_DRIVER_USART Driver_USART4; -#endif /* LPUART4 */ - -#if defined(LPUART5) -extern ARM_DRIVER_USART Driver_USART5; -#endif /* LPUART5 */ - -#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 3) - -extern ARM_DRIVER_USART Driver_USART3; - -#endif - -#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 4) - -extern ARM_DRIVER_USART Driver_USART4; - -#endif - -#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 5) -extern ARM_DRIVER_USART Driver_USART5; - -#endif - -#endif /* _FSL_LPUART_CMSIS_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_adc16.c b/third_party/nxp/MKW41Z4/drivers/fsl_adc16.c deleted file mode 100644 index 0af6a4443..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_adc16.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_adc16.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ADC16 module. - * - * @param base ADC16 peripheral base address - */ -static uint32_t ADC16_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ADC16 bases for each instance. */ -static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ADC16 clocks for each instance. */ -static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ADC16_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_adc16Bases); instance++) - { - if (s_adc16Bases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_adc16Bases)); - - return instance; -} - -void ADC16_Init(ADC_Type *base, const adc16_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* ADCx_CFG1. */ - tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); - if (kADC16_LongSampleDisabled != config->longSampleMode) - { - tmp32 |= ADC_CFG1_ADLSMP_MASK; - } - tmp32 |= ADC_CFG1_ADIV(config->clockDivider); - if (config->enableLowPower) - { - tmp32 |= ADC_CFG1_ADLPC_MASK; - } - base->CFG1 = tmp32; - - /* ADCx_CFG2. */ - tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); - if (kADC16_LongSampleDisabled != config->longSampleMode) - { - tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); - } - if (config->enableHighSpeed) - { - tmp32 |= ADC_CFG2_ADHSC_MASK; - } - if (config->enableAsynchronousClock) - { - tmp32 |= ADC_CFG2_ADACKEN_MASK; - } - base->CFG2 = tmp32; - - /* ADCx_SC2. */ - tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK); - tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); - base->SC2 = tmp32; - - /* ADCx_SC3. */ - if (config->enableContinuousConversion) - { - base->SC3 |= ADC_SC3_ADCO_MASK; - } - else - { - base->SC3 &= ~ADC_SC3_ADCO_MASK; - } -} - -void ADC16_Deinit(ADC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void ADC16_GetDefaultConfig(adc16_config_t *config) -{ - assert(NULL != config); - - config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; - config->clockSource = kADC16_ClockSourceAsynchronousClock; - config->enableAsynchronousClock = true; - config->clockDivider = kADC16_ClockDivider8; - config->resolution = kADC16_ResolutionSE12Bit; - config->longSampleMode = kADC16_LongSampleDisabled; - config->enableHighSpeed = false; - config->enableLowPower = false; - config->enableContinuousConversion = false; -} - -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION -status_t ADC16_DoAutoCalibration(ADC_Type *base) -{ - bool bHWTrigger = false; - volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */ - status_t status = kStatus_Success; - - /* The calibration would be failed when in hardwar mode. - * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ - if (0U != (ADC_SC2_ADTRG_MASK & base->SC2)) - { - bHWTrigger = true; - base->SC2 &= ~ADC_SC2_ADTRG_MASK; - } - - /* Clear the CALF and launch the calibration. */ - base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK; - while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U))) - { - /* Check the CALF when the calibration is active. */ - if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) - { - status = kStatus_Fail; - break; - } - } - tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */ - - /* Restore the hardware trigger setting if it was enabled before. */ - if (bHWTrigger) - { - base->SC2 |= ADC_SC2_ADTRG_MASK; - } - /* Check the CALF at the end of calibration. */ - if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) - { - status = kStatus_Fail; - } - if (kStatus_Success != status) /* Check if the calibration process is succeed. */ - { - return status; - } - - /* Calculate the calibration values. */ - tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS; - tmp32 = 0x8000U | (tmp32 >> 1U); - base->PG = tmp32; - -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS; - tmp32 = 0x8000U | (tmp32 >> 1U); - base->MG = tmp32; -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ - - return kStatus_Success; -} -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ - -#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT -void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) -{ - if (kADC16_ChannelMuxA == mode) - { - base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; - } - else /* kADC16_ChannelMuxB. */ - { - base->CFG2 |= ADC_CFG2_MUXSEL_MASK; - } -} -#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ - -void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) -{ - uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); - - if (!config) /* Pass "NULL" to disable the feature. */ - { - base->SC2 = tmp32; - return; - } - /* Enable the feature. */ - tmp32 |= ADC_SC2_ACFE_MASK; - - /* Select the hardware compare working mode. */ - switch (config->hardwareCompareMode) - { - case kADC16_HardwareCompareMode0: - break; - case kADC16_HardwareCompareMode1: - tmp32 |= ADC_SC2_ACFGT_MASK; - break; - case kADC16_HardwareCompareMode2: - tmp32 |= ADC_SC2_ACREN_MASK; - break; - case kADC16_HardwareCompareMode3: - tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK; - break; - default: - break; - } - base->SC2 = tmp32; - - /* Load the compare values. */ - base->CV1 = ADC_CV1_CV(config->value1); - base->CV2 = ADC_CV2_CV(config->value2); -} - -#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE -void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) -{ - uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); - - if (kADC16_HardwareAverageDisabled != mode) - { - tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode); - } - base->SC3 = tmp32; -} -#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) -{ - uint32_t tmp32; - - if (!config) /* Passing "NULL" is to disable the feature. */ - { - base->PGA = 0U; - return; - } - - /* Enable the PGA and set the gain value. */ - tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain); - - /* Configure the misc features for PGA. */ - if (config->enableRunInNormalMode) - { - tmp32 |= ADC_PGA_PGALPb_MASK; - } -#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING - if (config->disablePgaChopping) - { - tmp32 |= ADC_PGA_PGACHPb_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ -#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT - if (config->enableRunInOffsetMeasurement) - { - tmp32 |= ADC_PGA_PGAOFSM_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ - base->PGA = tmp32; -} -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -uint32_t ADC16_GetStatusFlags(ADC_Type *base) -{ - uint32_t ret = 0; - - if (0U != (base->SC2 & ADC_SC2_ADACT_MASK)) - { - ret |= kADC16_ActiveFlag; - } -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION - if (0U != (base->SC3 & ADC_SC3_CALF_MASK)) - { - ret |= kADC16_CalibrationFailedFlag; - } -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ - return ret; -} - -void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION - if (0U != (mask & kADC16_CalibrationFailedFlag)) - { - base->SC3 |= ADC_SC3_CALF_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ -} - -void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) -{ - assert(channelGroup < ADC_SC1_COUNT); - assert(NULL != config); - - uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */ - -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - /* Enable the differential conversion. */ - if (config->enableDifferentialConversion) - { - sc1 |= ADC_SC1_DIFF_MASK; - } -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ - /* Enable the interrupt when the conversion is done. */ - if (config->enableInterruptOnConversionCompleted) - { - sc1 |= ADC_SC1_AIEN_MASK; - } - base->SC1[channelGroup] = sc1; -} - -uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) -{ - assert(channelGroup < ADC_SC1_COUNT); - - uint32_t ret = 0U; - - if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK)) - { - ret |= kADC16_ChannelConversionDoneFlag; - } - return ret; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_adc16.h b/third_party/nxp/MKW41Z4/drivers/fsl_adc16.h deleted file mode 100644 index ea62c55fe..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_adc16.h +++ /dev/null @@ -1,525 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_ADC16_H_ -#define _FSL_ADC16_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup adc16 - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief ADC16 driver version 2.0.0. */ -#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief Channel status flags. - */ -enum _adc16_channel_status_flags -{ - kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */ -}; - -/*! - * @brief Converter status flags. - */ -enum _adc16_status_flags -{ - kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */ -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION - kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */ -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ -}; - -#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT -/*! - * @brief Channel multiplexer mode for each channel. - * - * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b - * are the different channels that share the same channel number. - */ -typedef enum _adc_channel_mux_mode -{ - kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */ - kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */ -} adc16_channel_mux_mode_t; -#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ - -/*! - * @brief Clock divider for the converter. - */ -typedef enum _adc16_clock_divider -{ - kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */ - kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */ - kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */ - kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */ -} adc16_clock_divider_t; - -/*! - *@brief Converter's resolution. - */ -typedef enum _adc16_resolution -{ - /* This group of enumeration is for internal use which is related to register setting. */ - kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */ - kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */ - kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */ - - /* This group of enumeration is for a public user. */ - kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */ - kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */ - kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */ -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */ - kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */ - kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */ -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ - -#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) - /* 16-bit is supported by default. */ - kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */ - kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */ -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */ -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ -#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */ -} adc16_resolution_t; - -/*! - * @brief Clock source. - */ -typedef enum _adc16_clock_source -{ - kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */ - kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */ - kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */ - kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */ - - /* Chip defined clock source */ - kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */ -} adc16_clock_source_t; - -/*! - * @brief Long sample mode. - */ -typedef enum _adc16_long_sample_mode -{ - kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ - kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ - kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ - kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ - kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */ -} adc16_long_sample_mode_t; - -/*! - * @brief Reference voltage source. - */ -typedef enum _adc16_reference_voltage_source -{ - kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ - kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */ -} adc16_reference_voltage_source_t; - -#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE -/*! - * @brief Hardware average mode. - */ -typedef enum _adc16_hardware_average_mode -{ - kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ - kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ - kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ - kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ - kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/ -} adc16_hardware_average_mode_t; -#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ - -/*! - * @brief Hardware compare mode. - */ -typedef enum _adc16_hardware_compare_mode -{ - kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */ - kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */ - kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2; - else, value1 > x > value2. */ - kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2; - else x >= value1 || x <= value2. */ -} adc16_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -/*! - * @brief PGA's Gain mode. - */ -typedef enum _adc16_pga_gain -{ - kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */ - kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */ - kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */ - kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */ - kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */ - kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */ - kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */ -} adc16_pga_gain_t; -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -/*! - * @brief ADC16 converter configuration. - */ -typedef struct _adc16_config -{ - adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ - adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */ - bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */ - adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */ - adc16_resolution_t resolution; /*!< Select the sample resolution mode. */ - adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */ - bool enableHighSpeed; /*!< Enable the high-speed mode. */ - bool enableLowPower; /*!< Enable low power. */ - bool enableContinuousConversion; /*!< Enable continuous conversion mode. */ -} adc16_config_t; - -/*! - * @brief ADC16 Hardware comparison configuration. - */ -typedef struct _adc16_hardware_compare_config -{ - adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. - See "adc16_hardware_compare_mode_t". */ - int16_t value1; /*!< Setting value1 for hardware compare mode. */ - int16_t value2; /*!< Setting value2 for hardware compare mode. */ -} adc16_hardware_compare_config_t; - -/*! - * @brief ADC16 channel conversion configuration. - */ -typedef struct _adc16_channel_config -{ - uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. - See channel connection information for each chip in Reference - Manual document. */ - bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ -#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE - bool enableDifferentialConversion; /*!< Using Differential sample mode. */ -#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ -} adc16_channel_config_t; - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -/*! - * @brief ADC16 programmable gain amplifier configuration. - */ -typedef struct _adc16_pga_config -{ - adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */ - bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */ -#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING - bool disablePgaChopping; /*!< Disable the PGA chopping function. - The PGA employs chopping to remove/reduce offset and 1/f noise and offers - an offset measurement configuration that aids the offset calibration. */ -#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ -#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT - bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode. - When this feature is enabled, the PGA disconnects itself from the external - inputs and auto-configures into offset measurement mode. With this field - set, run the ADC in the recommended settings and enable the maximum hardware - averaging to get the PGA offset number. The output is the - (PGA offset * (64+1)) for the given PGA setting. */ -#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ -} adc16_pga_config_t; -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the ADC16 module. - * - * @param base ADC16 peripheral base address. - * @param config Pointer to configuration structure. See "adc16_config_t". - */ -void ADC16_Init(ADC_Type *base, const adc16_config_t *config); - -/*! - * @brief De-initializes the ADC16 module. - * - * @param base ADC16 peripheral base address. - */ -void ADC16_Deinit(ADC_Type *base); - -/*! - * @brief Gets an available pre-defined settings for the converter's configuration. - * - * This function initializes the converter configuration structure with available settings. The default values are as follows. - * @code - * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; - * config->clockSource = kADC16_ClockSourceAsynchronousClock; - * config->enableAsynchronousClock = true; - * config->clockDivider = kADC16_ClockDivider8; - * config->resolution = kADC16_ResolutionSE12Bit; - * config->longSampleMode = kADC16_LongSampleDisabled; - * config->enableHighSpeed = false; - * config->enableLowPower = false; - * config->enableContinuousConversion = false; - * @endcode - * @param config Pointer to the configuration structure. - */ -void ADC16_GetDefaultConfig(adc16_config_t *config); - -#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION -/*! - * @brief Automates the hardware calibration. - * - * This auto calibration helps to adjust the plus/minus side gain automatically. - * Execute the calibration before using the converter. Note that the hardware trigger should be used - * during the calibration. - * - * @param base ADC16 peripheral base address. - * - * @return Execution status. - * @retval kStatus_Success Calibration is done successfully. - * @retval kStatus_Fail Calibration has failed. - */ -status_t ADC16_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ - -#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION -/*! - * @brief Sets the offset value for the conversion result. - * - * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result - * is subtracted by it. Note, the hardware calibration fills the offset value automatically. - * - * @param base ADC16 peripheral base address. - * @param value Setting offset value. - */ -static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value) -{ - base->OFS = (uint32_t)(value); -} -#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ - -/* @} */ - -/*! - * @name Advanced Features - * @{ - */ - -#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA -/*! - * @brief Enables generating the DMA trigger when the conversion is complete. - * - * @param base ADC16 peripheral base address. - * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled. - */ -static inline void ADC16_EnableDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SC2 |= ADC_SC2_DMAEN_MASK; - } - else - { - base->SC2 &= ~ADC_SC2_DMAEN_MASK; - } -} -#endif /* FSL_FEATURE_ADC16_HAS_DMA */ - -/*! - * @brief Enables the hardware trigger mode. - * - * @param base ADC16 peripheral base address. - * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled. - */ -static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable) -{ - if (enable) - { - base->SC2 |= ADC_SC2_ADTRG_MASK; - } - else - { - base->SC2 &= ~ADC_SC2_ADTRG_MASK; - } -} - -#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT -/*! - * @brief Sets the channel mux mode. - * - * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an - * indicated channel. - * - * @param base ADC16 peripheral base address. - * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". - */ -void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode); -#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ - -/*! - * @brief Configures the hardware compare mode. - * - * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the result - * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate reference - * manual for more information. - * - * @param base ADC16 peripheral base address. - * @param config Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature. - */ -void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config); - -#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE -/*! - * @brief Sets the hardware average mode. - * - * The hardware average mode provides a way to process the conversion result automatically by using hardware. The multiple - * conversion results are accumulated and averaged internally making them easier to read. - * - * @param base ADC16 peripheral base address. - * @param mode Setting the hardware average mode. See "adc16_hardware_average_mode_t". - */ -void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode); -#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ - -#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA -/*! - * @brief Configures the PGA for the converter's front end. - * - * @param base ADC16 peripheral base address. - * @param config Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature. - */ -void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config); -#endif /* FSL_FEATURE_ADC16_HAS_PGA */ - -/*! - * @brief Gets the status flags of the converter. - * - * @param base ADC16 peripheral base address. - * - * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". - */ -uint32_t ADC16_GetStatusFlags(ADC_Type *base); - -/*! - * @brief Clears the status flags of the converter. - * - * @param base ADC16 peripheral base address. - * @param mask Mask value for the cleared flags. See "_adc16_status_flags". - */ -void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Conversion Channel - * @{ - */ - -/*! - * @brief Configures the conversion channel. - * - * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API - * configures the channel while the external trigger source helps to trigger the conversion. - * - * Note that the "Channel Group" has a detailed description. - * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one - * group of status and control registers, one for each conversion. The channel group parameter indicates which group of - * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B registers. The - * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of - * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and hardware - * trigger modes. Channel group 1 and greater indicates multiple channel group registers for - * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for the - * number of SC1n registers (channel groups) specific to this device. Channel group 1 or greater are not used - * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. - * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and - * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a - * conversion aborts the current conversion. - * - * @param base ADC16 peripheral base address. - * @param channelGroup Channel group index. - * @param config Pointer to the "adc16_channel_config_t" structure for the conversion channel. - */ -void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config); - -/*! - * @brief Gets the conversion value. - * - * @param base ADC16 peripheral base address. - * @param channelGroup Channel group index. - * - * @return Conversion value. - */ -static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) -{ - assert(channelGroup < ADC_R_COUNT); - - return base->R[channelGroup]; -} - -/*! - * @brief Gets the status flags of channel. - * - * @param base ADC16 peripheral base address. - * @param channelGroup Channel group index. - * - * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". - */ -uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_ADC16_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_clock.c b/third_party/nxp/MKW41Z4/drivers/fsl_clock.c deleted file mode 100644 index 1885b990f..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_clock.c +++ /dev/null @@ -1,1374 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_clock.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Macro definition remap workaround. */ -#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) -#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK -#endif -#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) -#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK -#endif -#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK))) -#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK -#endif -#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK))) -#define MCG_C6_CME0_MASK MCG_C6_CME_MASK -#endif - -/* PLL fixed multiplier when there is not PRDIV and VDIV. */ -#define PLL_FIXED_MULT (375U) -/* Max frequency of the reference clock used for internal clock trim. */ -#define TRIM_REF_CLK_MIN (8000000U) -/* Min frequency of the reference clock used for internal clock trim. */ -#define TRIM_REF_CLK_MAX (16000000U) -/* Max trim value of fast internal reference clock. */ -#define TRIM_FIRC_MAX (5000000U) -/* Min trim value of fast internal reference clock. */ -#define TRIM_FIRC_MIN (3000000U) -/* Max trim value of fast internal reference clock. */ -#define TRIM_SIRC_MAX (39063U) -/* Min trim value of fast internal reference clock. */ -#define TRIM_SIRC_MIN (31250U) - -#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT) -#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) -#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT) -#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT) -#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) -#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT) -#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) -#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) -#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT) -#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) -#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT) -#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) -#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) -#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) -#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) -#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT) -#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT) -#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) -#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) - -#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK) - -#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) -#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) -#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) - -/* MCG_S_CLKST definition. */ -enum _mcg_clkout_stat -{ - kMCG_ClkOutStatFll, /* FLL. */ - kMCG_ClkOutStatInt, /* Internal clock. */ - kMCG_ClkOutStatExt, /* External clock. */ - kMCG_ClkOutStatPll /* PLL. */ -}; - -/* MCG_S_PLLST definition. */ -enum _mcg_pllst -{ - kMCG_PllstFll, /* FLL is used. */ - kMCG_PllstPll /* PLL is used. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Slow internal reference clock frequency. */ -static uint32_t s_slowIrcFreq = 32768U; -/* Fast internal reference clock frequency. */ -static uint32_t s_fastIrcFreq = 4000000U; - -/* External XTAL0 (OSC0) clock frequency. */ -uint32_t g_xtal0Freq; -/* External XTAL32K clock frequency. */ -uint32_t g_xtal32Freq; - - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the MCG external reference clock frequency. - * - * Get the current MCG external reference clock frequency in Hz. It is - * the frequency select by MCG_C7[OSCSEL]. This is an internal function. - * - * @return MCG external reference clock frequency in Hz. - */ -static uint32_t CLOCK_GetMcgExtClkFreq(void); - -/*! - * @brief Get the MCG FLL external reference clock frequency. - * - * Get the current MCG FLL external reference clock frequency in Hz. It is - * the frequency after by MCG_C1[FRDIV]. This is an internal function. - * - * @return MCG FLL external reference clock frequency in Hz. - */ -static uint32_t CLOCK_GetFllExtRefClkFreq(void); - -/*! - * @brief Get the MCG FLL reference clock frequency. - * - * Get the current MCG FLL reference clock frequency in Hz. It is - * the frequency select by MCG_C1[IREFS]. This is an internal function. - * - * @return MCG FLL reference clock frequency in Hz. - */ -static uint32_t CLOCK_GetFllRefClkFreq(void); - -/*! - * @brief Get the frequency of clock selected by MCG_C2[IRCS]. - * - * This clock's two output: - * 1. MCGOUTCLK when MCG_S[CLKST]=0. - * 2. MCGIRCLK when MCG_C1[IRCLKEN]=1. - * - * @return The frequency in Hz. - */ -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void); - - -/*! - * @brief Calculate the RANGE value base on crystal frequency. - * - * To setup external crystal oscillator, must set the register bits RANGE - * base on the crystal frequency. This function returns the RANGE base on the - * input frequency. This is an internal function. - * - * @param freq Crystal frequency in Hz. - * @return The RANGE value. - */ -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); - - - - -/******************************************************************************* - * Code - ******************************************************************************/ - -#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN -/*! - * @brief Delay function to wait FLL stable. - * - * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least - * 1ms. Every time changes FLL setting, should wait this time for FLL stable. - */ -void CLOCK_FllStableDelay(void) -{ - /* - Should wait at least 1ms. Because in these modes, the core clock is 100MHz - at most, so this function could obtain the 1ms delay. - */ - volatile uint32_t i = 30000U; - while (i--) - { - __NOP(); - } -} -#else /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */ -/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to - * create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this - * file would call the CLOCK_FllStableDelay() regardness how it is defined. - */ -extern void CLOCK_FllStableDelay(void); -#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */ - -static uint32_t CLOCK_GetMcgExtClkFreq(void) -{ - uint32_t freq; - - switch (MCG_C7_OSCSEL_VAL) - { - case 0U: - /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ - assert(g_xtal0Freq); - freq = g_xtal0Freq; - break; - case 1U: - /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ - assert(g_xtal32Freq); - freq = g_xtal32Freq; - break; - default: - freq = 0U; - break; - } - - return freq; -} - -static uint32_t CLOCK_GetFllExtRefClkFreq(void) -{ - /* FllExtRef = McgExtRef / FllExtRefDiv */ - uint8_t frdiv; - uint8_t range; - uint8_t oscsel; - - uint32_t freq = CLOCK_GetMcgExtClkFreq(); - - if (!freq) - { - return freq; - } - - frdiv = MCG_C1_FRDIV_VAL; - freq >>= frdiv; - - range = MCG_C2_RANGE_VAL; - oscsel = MCG_C7_OSCSEL_VAL; - - /* - When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536. - 1. MCG_C7[OSCSEL] selects IRC48M. - 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0. - */ - if (((0U != range) - && (kMCG_OscselOsc == oscsel) - ) - ) - { - switch (frdiv) - { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - freq >>= 5u; - break; - case 6: - /* 64*20=1280 */ - freq /= 20u; - break; - case 7: - /* 128*12=1536 */ - freq /= 12u; - break; - default: - freq = 0u; - break; - } - } - - return freq; -} - -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void) -{ - if (kMCG_IrcSlow == MCG_S_IRCST_VAL) - { - /* Slow internal reference clock selected*/ - return s_slowIrcFreq; - } - else - { - /* Fast internal reference clock selected*/ - return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL; - } -} - -static uint32_t CLOCK_GetFllRefClkFreq(void) -{ - /* If use external reference clock. */ - if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { - return CLOCK_GetFllExtRefClkFreq(); - } - /* If use internal reference clock. */ - else - { - return s_slowIrcFreq; - } -} - - -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) -{ - uint8_t range; - - if (freq <= 39063U) - { - range = 0U; - } - else if (freq <= 8000000U) - { - range = 1U; - } - else - { - range = 2U; - } - - return range; -} - - -uint32_t CLOCK_GetEr32kClkFreq(void) -{ - uint32_t freq; - - switch (SIM_SOPT1_OSC32KSEL_VAL) - { - case 0U: /* OSC 32k clock */ - case 2U: /* RTC 32k clock */ - /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ - assert(g_xtal32Freq); - freq = g_xtal32Freq; - break; - case 3U: /* LPO clock */ - freq = LPO_CLK_FREQ; - break; - default: - freq = 0U; - break; - } - return freq; -} - -uint32_t CLOCK_GetOsc0ErClkFreq(void) -{ - /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ - assert(g_xtal0Freq); - return g_xtal0Freq; -} - -uint32_t CLOCK_GetPlatClkFreq(void) -{ - return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); -} - -uint32_t CLOCK_GetFlashClkFreq(void) -{ - uint32_t freq; - - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); - freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); - - return freq; -} - -uint32_t CLOCK_GetBusClkFreq(void) -{ - uint32_t freq; - - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); - freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); - - return freq; -} - -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); -} - -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - - switch (clockName) - { - case kCLOCK_CoreSysClk: - case kCLOCK_PlatClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); - break; - case kCLOCK_BusClk: - case kCLOCK_FlashClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); - freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); - break; - case kCLOCK_Er32kClk: - freq = CLOCK_GetEr32kClkFreq(); - break; - case kCLOCK_McgInternalRefClk: - freq = CLOCK_GetInternalRefClkFreq(); - break; - case kCLOCK_McgFllClk: - freq = CLOCK_GetFllFreq(); - break; - case kCLOCK_LpoClk: - freq = LPO_CLK_FREQ; - break; - case kCLOCK_Osc0ErClk: - /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ - assert(g_xtal0Freq); - freq = g_xtal0Freq; - break; - default: - freq = 0U; - break; - } - - return freq; -} - -void CLOCK_SetSimConfig(sim_clock_config_t const *config) -{ - SIM->CLKDIV1 = config->clkdiv1; - CLOCK_SetEr32kClock(config->er32kSrc); -} - -uint32_t CLOCK_GetOutClkFreq(void) -{ - uint32_t mcgoutclk; - uint32_t clkst = MCG_S_CLKST_VAL; - - switch (clkst) - { - case kMCG_ClkOutStatFll: - mcgoutclk = CLOCK_GetFllFreq(); - break; - case kMCG_ClkOutStatInt: - mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); - break; - case kMCG_ClkOutStatExt: - mcgoutclk = CLOCK_GetMcgExtClkFreq(); - break; - default: - mcgoutclk = 0U; - break; - } - return mcgoutclk; -} - -uint32_t CLOCK_GetFllFreq(void) -{ - static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; - - uint8_t drs, dmx32; - uint32_t freq; - - /* If FLL is not enabled currently, then return 0U. */ - if ((MCG->C2 & MCG_C2_LP_MASK) - ) - { - return 0U; - } - - /* Get FLL reference clock frequency. */ - freq = CLOCK_GetFllRefClkFreq(); - if (!freq) - { - return freq; - } - - drs = MCG_C4_DRST_DRS_VAL; - dmx32 = MCG_C4_DMX32_VAL; - - return freq * fllFactorTable[drs][dmx32]; -} - -uint32_t CLOCK_GetInternalRefClkFreq(void) -{ - /* If MCGIRCLK is gated. */ - if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) - { - return 0U; - } - - return CLOCK_GetInternalRefClkSelectFreq(); -} - -uint32_t CLOCK_GetFixedFreqClkFreq(void) -{ - uint32_t freq = CLOCK_GetFllRefClkFreq(); - - /* MCGFFCLK must be no more than MCGOUTCLK/8. */ - if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U))) - { - return freq; - } - else - { - return 0U; - } -} - - -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) -{ - bool needDelay; - uint32_t i; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */ - if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) - { - return kStatus_MCG_SourceUsed; - } -#endif /* MCG_CONFIG_CHECK_PARAM */ - - if (MCG_C7_OSCSEL_VAL != oscsel) - { - /* If change OSCSEL, need to delay, ERR009878. */ - needDelay = true; - } - else - { - needDelay = false; - } - - MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); - if (needDelay) - { - /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ - i = 1500U; - while (i--) - { - __NOP(); - } - } - - return kStatus_Success; -} - -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) -{ - uint32_t mcgOutClkState = MCG_S_CLKST_VAL; - mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL; - uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - /* If MCGIRCLK is used as system clock source. */ - if (kMCG_ClkOutStatInt == mcgOutClkState) - { - /* If need to change MCGIRCLK source or driver, return error. */ - if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) - { - return kStatus_MCG_SourceUsed; - } - } -#endif - - /* If need to update the FCRDIV. */ - if (fcrdiv != curFcrdiv) - { - /* If fast IRC is in use currently, change to slow IRC. */ - if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK))) - { - MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); - while (MCG_S_IRCST_VAL != kMCG_IrcSlow) - { - } - } - /* Update FCRDIV. */ - MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); - } - - /* Set internal reference clock selection. */ - MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); - MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; - - /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ - if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable)) - { - while (MCG_S_IRCST_VAL != ircs) - { - } - } - - return kStatus_Success; -} - - - -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) -{ - /* Clear the previous flag, MCG_SC[LOCS0]. */ - MCG->SC &= ~MCG_SC_ATMF_MASK; - - if (kMCG_MonitorNone == mode) - { - MCG->C6 &= ~MCG_C6_CME0_MASK; - } - else - { - if (kMCG_MonitorInt == mode) - { - MCG->C2 &= ~MCG_C2_LOCRE0_MASK; - } - else - { - MCG->C2 |= MCG_C2_LOCRE0_MASK; - } - MCG->C6 |= MCG_C6_CME0_MASK; - } -} - - -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) -{ - uint8_t mcg_c8 = MCG->C8; - - mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); - - if (kMCG_MonitorNone != mode) - { - if (kMCG_MonitorReset == mode) - { - mcg_c8 |= MCG_C8_LOCRE1_MASK; - } - mcg_c8 |= MCG_C8_CME1_MASK; - } - MCG->C8 = mcg_c8; -} - - -uint32_t CLOCK_GetStatusFlags(void) -{ - uint32_t ret = 0U; - - if (MCG->C8 & MCG_C8_LOCS1_MASK) - { - ret |= kMCG_RtcOscLostFlag; - } - return ret; -} - -void CLOCK_ClearStatusFlags(uint32_t mask) -{ - uint8_t reg; - - if (mask & kMCG_RtcOscLostFlag) - { - reg = MCG->C8; - MCG->C8 = reg; - } -} - -void CLOCK_InitOsc0(osc_config_t const *config) -{ - uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); - - - MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); - - if ((kOSC_ModeExt != config->workMode) - ) - { - /* Wait for stable. */ - while (!(MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } -} - -void CLOCK_DeinitOsc0(void) -{ - MCG->C2 &= ~OSC_MODE_MASK; -} - - -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) -{ - uint32_t multi; /* extFreq / desireFreq */ - uint32_t actv; /* Auto trim value. */ - uint8_t mcg_sc; - - static const uint32_t trimRange[2][2] = { - /* Min Max */ - {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */ - {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */ - }; - - if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) - { - return kStatus_MCG_AtmBusClockInvalid; - } - - /* Check desired frequency range. */ - if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) - { - return kStatus_MCG_AtmDesiredFreqInvalid; - } - - /* - Make sure internal reference clock is not used to generate bus clock. - Here only need to check (MCG_S_IREFST == 1). - */ - if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) - { - return kStatus_MCG_AtmIrcUsed; - } - - multi = extFreq / desireFreq; - actv = multi * 21U; - - if (kMCG_AtmSel4m == atms) - { - actv *= 128U; - } - - /* Now begin to start trim. */ - MCG->ATCVL = (uint8_t)actv; - MCG->ATCVH = (uint8_t)(actv >> 8U); - - mcg_sc = MCG->SC; - mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); - mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); - MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); - - /* Wait for finished. */ - while (MCG->SC & MCG_SC_ATME_MASK) - { - } - - /* Error occurs? */ - if (MCG->SC & MCG_SC_ATMF_MASK) - { - /* Clear the failed flag. */ - MCG->SC = mcg_sc; - return kStatus_MCG_AtmHardwareFail; - } - - *actualFreq = extFreq / multi; - - if (kMCG_AtmSel4m == atms) - { - s_fastIrcFreq = *actualFreq; - } - else - { - s_slowIrcFreq = *actualFreq; - } - - return kStatus_Success; -} - -mcg_mode_t CLOCK_GetMode(void) -{ - mcg_mode_t mode = kMCG_ModeError; - uint32_t clkst = MCG_S_CLKST_VAL; - uint32_t irefst = MCG_S_IREFST_VAL; - uint32_t lp = MCG_C2_LP_VAL; - - /*------------------------------------------------------------------ - Mode and Registers - ____________________________________________________________________ - - Mode | CLKST | IREFST | PLLST | LP - ____________________________________________________________________ - - FEI | 00(FLL) | 1(INT) | 0(FLL) | X - ____________________________________________________________________ - - FEE | 00(FLL) | 0(EXT) | 0(FLL) | X - ____________________________________________________________________ - - FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) - ____________________________________________________________________ - - FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) - ____________________________________________________________________ - - BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) - ____________________________________________________________________ - - BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) - ____________________________________________________________________ - - PEE | 11(PLL) | 0(EXT) | 1(PLL) | X - ____________________________________________________________________ - - PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) - ____________________________________________________________________ - - PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) - ____________________________________________________________________ - - PEI | 11(PLL) | 1(INT) | 1(PLL) | X - ____________________________________________________________________ - - ----------------------------------------------------------------------*/ - - switch (clkst) - { - case kMCG_ClkOutStatFll: - if (kMCG_FllSrcExternal == irefst) - { - mode = kMCG_ModeFEE; - } - else - { - mode = kMCG_ModeFEI; - } - break; - case kMCG_ClkOutStatInt: - if (lp) - { - mode = kMCG_ModeBLPI; - } - else - { - { - mode = kMCG_ModeFBI; - } - } - break; - case kMCG_ClkOutStatExt: - if (lp) - { - mode = kMCG_ModeBLPE; - } - else - { - { - mode = kMCG_ModeFBE; - } - } - break; - default: - break; - } - - return mode; -} - -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - mcg_c4 = MCG->C4; - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = - ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */ - - /* Wait and check status. */ - while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ - MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)); - - /* Check MCG_S[CLKST] */ - while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) - { - } - - /* Wait for FLL stable time. */ - if (fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - mcg_c4 = MCG->C4; - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ - - /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (MCG->C2 & MCG_C2_EREFS_MASK) - { - while (!(MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } - } - - /* Wait and check status. */ - while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - /* Set DRS and DMX32. */ - mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); - MCG->C4 = mcg_c4; - - /* Wait for DRST_DRS update. */ - while (MCG->C4 != mcg_c4) - { - } - - /* Check MCG_S[CLKST] */ - while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) - { - } - - /* Wait for FLL stable time. */ - if (fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - - if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || - (kMCG_ModeBLPI == mode))) - - { - return kStatus_MCG_ModeUnreachable; - } -#endif - - mcg_c4 = MCG->C4; - - MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = - ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ - | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ - - /* Wait and check status. */ - while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) - { - } - - MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)); - - /* Wait for FLL stable time. */ - if (fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - uint8_t mcg_c4; - bool change_drs = false; - -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || - (kMCG_ModeBLPE == mode))) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - - - /* Set LP bit to enable the FLL */ - MCG->C2 &= ~MCG_C2_LP_MASK; - - mcg_c4 = MCG->C4; - - /* - Errata: ERR007993 - Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before - reference clock source changes, then reset to previous value after - reference clock changes. - */ - if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) - { - change_drs = true; - /* Change the LSB of DRST_DRS. */ - MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); - } - - /* Set CLKS and IREFS. */ - MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ - - /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (MCG->C2 & MCG_C2_EREFS_MASK) - { - while (!(MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } - } - - /* Wait for Reference clock Status bit to clear */ - while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) - { - } - - /* Errata: ERR007993 */ - if (change_drs) - { - MCG->C4 = mcg_c4; - } - - /* Set DRST_DRS and DMX32. */ - mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); - - /* Wait for clock status bits to show clock source is ext ref clk */ - while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) - { - } - - /* Wait for fll stable time. */ - if (fllStableDelay) - { - fllStableDelay(); - } - - return kStatus_Success; -} - -status_t CLOCK_SetBlpiMode(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) - { - return kStatus_MCG_ModeUnreachable; - } -#endif /* MCG_CONFIG_CHECK_PARAM */ - - /* Set LP. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - -status_t CLOCK_SetBlpeMode(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) - { - return kStatus_MCG_ModeUnreachable; - } -#endif - - /* Set LP bit to enter BLPE mode. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - - -status_t CLOCK_ExternalModeToFbeModeQuick(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG->S & MCG_S_IREFST_MASK) - { - return kStatus_MCG_ModeInvalid; - } -#endif /* MCG_CONFIG_CHECK_PARAM */ - - /* Disable low power */ - MCG->C2 &= ~MCG_C2_LP_MASK; - - MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); - while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) - { - } - - - return kStatus_Success; -} - -status_t CLOCK_InternalModeToFbiModeQuick(void) -{ -#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (!(MCG->S & MCG_S_IREFST_MASK)) - { - return kStatus_MCG_ModeInvalid; - } -#endif - - /* Disable low power */ - MCG->C2 &= ~MCG_C2_LP_MASK; - - MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); - while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) - { - } - - - return kStatus_Success; -} - -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay); -} - -status_t CLOCK_BootToFeeMode( - mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) -{ - - CLOCK_SetExternalRefClkConfig(oscsel); - - return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay); -} - -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) -{ - /* If reset mode is FEI mode, set MCGIRCLK and always success. */ - CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); - - /* If reset mode is not BLPI, first enter FBI mode. */ - MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal); - while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) - { - } - - /* Enter BLPI mode. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) -{ - - CLOCK_SetExternalRefClkConfig(oscsel); - - /* Set to FBE mode. */ - MCG->C1 = - ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ - | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ - - /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (MCG->C2 & MCG_C2_EREFS_MASK) - { - while (!(MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - } - } - - /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ - while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != - (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) - { - } - - /* In FBE now, start to enter BLPE. */ - MCG->C2 |= MCG_C2_LP_MASK; - - return kStatus_Success; -} - - -/* - The transaction matrix. It defines the path for mode switch, the row is for - current mode and the column is target mode. - For example, switch from FEI to PEE: - 1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE. - 2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE. - 3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE. - Thus the MCG mode has changed from FEI to PEE. - */ -static const mcg_mode_t mcgModeMatrix[6][6] = { - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE}, /* FEI */ - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE}, /* FBI */ - {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI}, /* BLPI */ - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE}, /* FEE */ - {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE}, /* FBE */ - {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE}, /* BLPE */ - /* FEI FBI BLPI FEE FBE BLPE */ -}; - -status_t CLOCK_SetMcgConfig(const mcg_config_t *config) -{ - mcg_mode_t next_mode; - status_t status = kStatus_Success; - - - /* If need to change external clock, MCG_C7[OSCSEL]. */ - if (MCG_C7_OSCSEL_VAL != config->oscsel) - { - /* If external clock is in use, change to FEI first. */ - if (!(MCG->S & MCG_S_IRCST_MASK)) - { - CLOCK_ExternalModeToFbeModeQuick(); - CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0); - } - - CLOCK_SetExternalRefClkConfig(config->oscsel); - } - - /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ - if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt) - { - MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ - - { - CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); - } - } - - /* Configure MCGIRCLK. */ - CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv); - - next_mode = CLOCK_GetMode(); - - do - { - next_mode = mcgModeMatrix[next_mode][config->mcgMode]; - - switch (next_mode) - { - case kMCG_ModeFEI: - status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); - break; - case kMCG_ModeFEE: - status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); - break; - case kMCG_ModeFBI: - status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0); - break; - case kMCG_ModeFBE: - status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0); - break; - case kMCG_ModeBLPI: - status = CLOCK_SetBlpiMode(); - break; - case kMCG_ModeBLPE: - status = CLOCK_SetBlpeMode(); - break; - default: - break; - } - if (kStatus_Success != status) - { - return status; - } - } while (next_mode != config->mcgMode); - - return kStatus_Success; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_clock.h b/third_party/nxp/MKW41Z4/drivers/fsl_clock.h deleted file mode 100644 index 3e7642277..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_clock.h +++ /dev/null @@ -1,1191 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Configures whether to check a parameter in a function. - * - * Some MCG settings must be changed with conditions, for example: - * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when - * MCGIRCLK is used as a system clock source. - * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used - * as a system clock source. For example, in FBE/BLPE/PBE modes. - * 3. The users should only switch between the supported clock modes. - * - * MCG functions check the parameter and MCG status before setting, if not allowed - * to change, the functions return error. The parameter checking increases code size, - * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to - * disable parameter checking. - */ -#ifndef MCG_CONFIG_CHECK_PARAM -#define MCG_CONFIG_CHECK_PARAM 0U -#endif - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could contol the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.2.1. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) -/*@}*/ - -/*! @brief External XTAL0 (OSC0) clock frequency. - * - * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the - * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, - * if XTAL0 is 8 MHz: - * @code - * CLOCK_InitOsc0(...); // Set up the OSC0 - * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver. - * @endcode - * - * This is important for the multicore platforms where only one core needs to set up the - * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq - * to get a valid clock frequency. - */ -extern uint32_t g_xtal0Freq; - - -/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. - * - * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the - * function CLOCK_SetXtal32Freq to set the value in the clock driver. - * - * This is important for the multicore platforms where only one core needs to set up - * the clock. All other cores need to call the CLOCK_SetXtal32Freq - * to get a valid clock frequency. - */ -extern uint32_t g_xtal32Freq; - - -#if (defined(OSC) && !(defined(OSC0))) -#define OSC0 OSC -#endif - -/*! @brief Clock ip name array for DMAMUX. */ -#define DMAMUX_CLOCKS \ - { \ - kCLOCK_Dmamux0 \ - } - -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc0 \ - } - -/*! @brief Clock ip name array for PIT. */ -#define PIT_CLOCKS \ - { \ - kCLOCK_Pit0 \ - } - -/*! @brief Clock ip name array for PORT. */ -#define PORT_CLOCKS \ - { \ - kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC \ - } - -/*! @brief Clock ip name array for TSI. */ -#define TSI_CLOCKS \ - { \ - kCLOCK_Tsi0 \ - } - -/*! @brief Clock ip name array for DSPI. */ -#define DSPI_CLOCKS \ - { \ - kCLOCK_Spi0, kCLOCK_Spi1 \ - } - -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_Lpuart0 \ - } - -/*! @brief Clock ip name array for DAC. */ -#define DAC_CLOCKS \ - { \ - kCLOCK_Dac0 \ - } - -/*! @brief Clock ip name array for LPTMR. */ -#define LPTMR_CLOCKS \ - { \ - kCLOCK_Lptmr0 \ - } - -/*! @brief Clock ip name array for ADC16. */ -#define ADC16_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } - -/*! @brief Clock ip name array for TRNG. */ -#define TRNG_CLOCKS \ - { \ - kCLOCK_Trng0 \ - } - -/*! @brief Clock ip name array for DMA. */ -#define EDMA_CLOCKS \ - { \ - kCLOCK_Dma0 \ - } - -/*! @brief Clock ip name array for CMT. */ -#define CMT_CLOCKS \ - { \ - kCLOCK_Cmt0 \ - } - -/*! @brief Clock ip name array for TPM. */ -#define TPM_CLOCKS \ - { \ - kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \ - } - -/*! @brief Clock ip name array for LTC. */ -#define LTC_CLOCKS \ - { \ - kCLOCK_Ltc0 \ - } - -/*! @brief Clock ip name array for I2C. */ -#define I2C_CLOCKS \ - { \ - kCLOCK_I2c0, kCLOCK_I2c1 \ - } - -/*! @brief Clock ip name array for CMP. */ -#define CMP_CLOCKS \ - { \ - kCLOCK_Cmp0 \ - } - -/*! @brief Clock ip name array for VREF. */ -#define VREF_CLOCKS \ - { \ - kCLOCK_Vref0 \ - } - -/*! @brief Clock ip name array for DCDC. */ -#define DCDC_CLOCKS \ - { \ - kCLOCK_Dcdc0 \ - } - -/*! - * @brief LPO clock frequency. - */ -#define LPO_CLK_FREQ 1000U - -/*! @brief Prepherials clock source definition. */ -#define SYS_CLK kCLOCK_CoreSysClk -#define BUS_CLK kCLOCK_BusClk - -#define I2C0_CLK_SRC BUS_CLK -#define I2C1_CLK_SRC SYS_CLK -#define DSPI0_CLK_SRC BUS_CLK -#define DSPI1_CLK_SRC BUS_CLK - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - /* ----------------------------- System layer clock -------------------------------*/ - kCLOCK_CoreSysClk, /*!< Core/system clock */ - kCLOCK_PlatClk, /*!< Platform clock */ - kCLOCK_BusClk, /*!< Bus clock */ - kCLOCK_FlashClk, /*!< Flash clock */ - - /* ---------------------------------- OSC clock -----------------------------------*/ - kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ - kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ - - /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ - kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ - kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ - kCLOCK_McgFllClk, /*!< MCGFLLCLK */ - kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ - - /* --------------------------------- Other clock ----------------------------------*/ - kCLOCK_LpoClk, /*!< LPO clock */ - -} clock_name_t; - -/*------------------------------------------------------------------------------ - - clock_gate_t definition: - - 31 16 0 - ----------------------------------------------------------------- - | SIM_SCGC register offset | control bit offset in SCGC | - ----------------------------------------------------------------- - - For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the - SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as - - kClockGateSdhc0 = (0x1030 << 16) | 17; - -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 16U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, - - kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U), - kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), - kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), - kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), - kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), - - kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), - kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U), - kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), - kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), - kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), - kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U), - kCLOCK_Aesa = CLK_GATE_DEFINE(0x1038U, 24U), - kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x1038U, 24U), - kCLOCK_Rsim = CLK_GATE_DEFINE(0x1038U, 25U), - kCLOCK_Dcdc0 = CLK_GATE_DEFINE(0x1038U, 26U), - kCLOCK_Btll = CLK_GATE_DEFINE(0x1038U, 27U), - kCLOCK_PhyDig = CLK_GATE_DEFINE(0x1038U, 28U), - kCLOCK_ZigBee = CLK_GATE_DEFINE(0x1038U, 29U), - kCLOCK_GenFsk = CLK_GATE_DEFINE(0x1038U, 31U), - - kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), - kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), - kCLOCK_Trng0 = CLK_GATE_DEFINE(0x103CU, 9U), - kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), - kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), - kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), - kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U), - kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U), - kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U), - kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), - kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), - kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U), - - kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U), -} clock_ip_name_t; - -/*!@brief SIM configuration structure for clock setting. */ -typedef struct _sim_clock_config -{ - uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */ - uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */ - uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */ - uint8_t er32kSrc; /*!< ERCLK32K source selection. */ - uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ -} sim_clock_config_t; - -/*! @brief OSC work mode. */ -typedef enum _osc_mode -{ - kOSC_ModeExt = 0U, /*!< Use an external clock. */ -#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) - kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ -#else - kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ -#endif - kOSC_ModeOscHighGain = 0U -#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) - | - MCG_C2_EREFS_MASK -#else - | - MCG_C2_EREFS0_MASK -#endif -#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) - | - MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ -#else - | - MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ -#endif -} osc_mode_t; - - -/*! - * @brief OSC Initialization Configuration Structure - * - * Defines the configuration data structure to initialize the OSC. - * When porting to a new board, set the following members - * according to the board setting: - * 1. freq: The external frequency. - * 2. workMode: The OSC module mode. - */ -typedef struct _osc_config -{ - uint32_t freq; /*!< External clock frequency. */ - osc_mode_t workMode; /*!< OSC work mode setting. */ -} osc_config_t; - -/*! @brief MCG FLL reference clock source select. */ -typedef enum _mcg_fll_src -{ - kMCG_FllSrcExternal, /*!< External reference clock is selected */ - kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ -} mcg_fll_src_t; - -/*! @brief MCG internal reference clock select */ -typedef enum _mcg_irc_mode -{ - kMCG_IrcSlow, /*!< Slow internal reference clock selected */ - kMCG_IrcFast /*!< Fast internal reference clock selected */ -} mcg_irc_mode_t; - -/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ -typedef enum _mcg_dmx32 -{ - kMCG_Dmx32Default, /*!< DCO has a default range of 25% */ - kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ -} mcg_dmx32_t; - -/*! @brief MCG DCO range select */ -typedef enum _mcg_drs -{ - kMCG_DrsLow, /*!< Low frequency range */ - kMCG_DrsMid, /*!< Mid frequency range */ - kMCG_DrsMidHigh, /*!< Mid-High frequency range */ - kMCG_DrsHigh /*!< High frequency range */ -} mcg_drs_t; - -/*! @brief MCG PLL reference clock select */ -typedef enum _mcg_pll_ref_src -{ - kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */ - kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ -} mcg_pll_ref_src_t; - -/*! @brief MCGOUT clock source. */ -typedef enum _mcg_clkout_src -{ - kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ - kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */ - kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */ -} mcg_clkout_src_t; - -/*! @brief MCG Automatic Trim Machine Select */ -typedef enum _mcg_atm_select -{ - kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ - kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ -} mcg_atm_select_t; - -/*! @brief MCG OSC Clock Select */ -typedef enum _mcg_oscsel -{ - kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */ - kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */ -} mcg_oscsel_t; - -/*! @brief MCG PLLCS select */ -typedef enum _mcg_pll_clk_select -{ - kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */ - kMCG_PllClkSelPll1 /* PLL1 output clock is selected */ -} mcg_pll_clk_select_t; - -/*! @brief MCG clock monitor mode. */ -typedef enum _mcg_monitor_mode -{ - kMCG_MonitorNone, /*!< Clock monitor is disabled. */ - kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */ - kMCG_MonitorReset /*!< System reset when clock lost. */ -} mcg_monitor_mode_t; - -/*! @brief MCG status. */ -enum _mcg_status -{ - kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */ - kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific - function. */ - kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */ - kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */ - kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */ - kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */ - kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because - it is in use. */ -}; - -/*! @brief MCG status flags. */ -enum _mcg_status_flags_t -{ - kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ -}; - -/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ -enum _mcg_irclk_enable_mode -{ - kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ - kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ -}; - - -/*! @brief MCG mode definitions */ -typedef enum _mcg_mode -{ - kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ - kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */ - kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */ - kMCG_ModeFEE, /*!< FEE - FLL Engaged External */ - kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */ - kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */ - kMCG_ModeError /*!< Unknown mode */ -} mcg_mode_t; - - -/*! @brief MCG mode change configuration structure - * - * When porting to a new board, set the following members - * according to the board setting: - * 1. frdiv: If the FLL uses the external reference clock, set this - * value to ensure that the external reference clock divided by frdiv is - * in the 31.25 kHz to 39.0625 kHz range. - * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after - * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to - * FSL_FEATURE_MCG_PLL_REF_MAX range. - */ -typedef struct _mcg_config -{ - mcg_mode_t mcgMode; /*!< MCG mode. */ - - /* ----------------------- MCGIRCCLK settings ------------------------ */ - uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */ - mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */ - uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */ - - /* ------------------------ MCG FLL settings ------------------------- */ - uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */ - mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */ - mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */ - mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */ - -/* ------------------------ MCG PLL settings ------------------------- */ -} mcg_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Enable the clock for specific IP. - * - * @param name Which clock to enable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_EnableClock(clock_ip_name_t name) -{ - uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); - (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); -} - -/*! - * @brief Disable the clock for specific IP. - * - * @param name Which clock to disable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_DisableClock(clock_ip_name_t name) -{ - uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); - (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); -} - -/*! - * @brief Set ERCLK32K source. - * - * @param src The value to set ERCLK32K clock source. - */ -static inline void CLOCK_SetEr32kClock(uint32_t src) -{ - SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); -} - -/*! - * @brief Set LPUART clock source. - * - * @param src The value to set LPUART clock source. - */ -static inline void CLOCK_SetLpuartClock(uint32_t src) -{ - SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src)); -} - -/*! - * @brief Set TPM clock source. - * - * @param src The value to set TPM clock source. - */ -static inline void CLOCK_SetTpmClock(uint32_t src) -{ - SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src)); -} - -/*! - * @brief Set CLKOUT source. - * - * @param src The value to set CLKOUT source. - */ -static inline void CLOCK_SetClkOutClock(uint32_t src) -{ - SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); -} - -/*! - * @brief System clock divider - * - * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4]. - * - * @param outdiv1 Clock 1 output divider value. - * - * @param outdiv4 Clock 4 output divider value. - */ -static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4) -{ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4); -} - -/*! - * @brief Gets the clock frequency for a specific clock name. - * - * This function checks the current clock configurations and then calculates - * the clock frequency for a specific clock name defined in clock_name_t. - * The MCG must be properly configured before using this function. - * - * @param clockName Clock names defined in clock_name_t - * @return Clock frequency value in Hertz - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); - -/*! - * @brief Get the core clock or system clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); - -/*! - * @brief Get the platform clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetPlatClkFreq(void); - -/*! - * @brief Get the bus clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetBusClkFreq(void); - -/*! - * @brief Get the flash clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetFlashClkFreq(void); - -/*! - * @brief Get the external reference 32K clock frequency (ERCLK32K). - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetEr32kClkFreq(void); - -/*! - * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetOsc0ErClkFreq(void); - -/*! - * @brief Set the clock configure in SIM module. - * - * This function sets system layer clock settings in SIM module. - * - * @param config Pointer to the configure structure. - */ -void CLOCK_SetSimConfig(sim_clock_config_t const *config); - -/*! - * @brief Set the system clock dividers in SIM to safe value. - * - * The system level clocks (core clock, bus clock, flexbus clock and flash clock) - * must be in allowed ranges. During MCG clock mode switch, the MCG output clock - * changes then the system level clocks may be out of range. This function could - * be used before MCG mode change, to make sure system level clocks are in allowed - * range. - * - * @param config Pointer to the configure structure. - */ -static inline void CLOCK_SetSimSafeDivs(void) -{ - SIM->CLKDIV1 = 0x00040000U; -} - -/*! @name MCG frequency functions. */ -/*@{*/ - -/*! - * @brief Gets the MCG output clock (MCGOUTCLK) frequency. - * - * This function gets the MCG output clock frequency in Hz based on the current MCG - * register value. - * - * @return The frequency of MCGOUTCLK. - */ -uint32_t CLOCK_GetOutClkFreq(void); - -/*! - * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency. - * - * This function gets the MCG FLL clock frequency in Hz based on the current MCG - * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and - * disabled in low power state in other modes. - * - * @return The frequency of MCGFLLCLK. - */ -uint32_t CLOCK_GetFllFreq(void); - -/*! - * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency. - * - * This function gets the MCG internal reference clock frequency in Hz based - * on the current MCG register value. - * - * @return The frequency of MCGIRCLK. - */ -uint32_t CLOCK_GetInternalRefClkFreq(void); - -/*! - * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency. - * - * This function gets the MCG fixed frequency clock frequency in Hz based - * on the current MCG register value. - * - * @return The frequency of MCGFFCLK. - */ -uint32_t CLOCK_GetFixedFreqClkFreq(void); - - -/*@}*/ - -/*! @name MCG clock configuration. */ -/*@{*/ - -/*! - * @brief Enables or disables the MCG low power. - * - * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words, - * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and - * PBI modes, enabling low power sets the MCG to BLPI mode. - * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings. - * - * @param enable True to enable MCG low power, false to disable MCG low power. - */ -static inline void CLOCK_SetLowPowerEnable(bool enable) -{ - if (enable) - { - MCG->C2 |= MCG_C2_LP_MASK; - } - else - { - MCG->C2 &= ~MCG_C2_LP_MASK; - } -} - -/*! - * @brief Configures the Internal Reference clock (MCGIRCLK). - * - * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC - * source. If the fast IRC is used, this function sets the fast IRC divider. - * This function also sets whether the \c MCGIRCLK is enabled in stop mode. - * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, - * using the function in these modes it is not allowed. - * - * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. - * @param ircs MCGIRCLK clock source, choose fast or slow. - * @param fcrdiv Fast IRC divider setting (\c FCRDIV). - * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source, - * the confuration should not be changed. Otherwise, a glitch occurs. - * @retval kStatus_Success MCGIRCLK configuration finished successfully. - */ -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); - -/*! - * @brief Selects the MCG external reference clock. - * - * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], - * and waits for the clock source to be stable. Because the external reference - * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes. - * - * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. - * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source, - * the confuration should not be changed. Otherwise, a glitch occurs. - * @retval kStatus_Success External reference clock set successfully. - */ -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); - -/*! - * @brief Set the FLL external reference clock divider value. - * - * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV]. - * - * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV]. - */ -static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv) -{ - MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv); -} - - - -/*@}*/ - -/*! @name MCG clock lock monitor functions. */ -/*@{*/ - - -/*! - * @brief Sets the RTC OSC clock monitor mode. - * - * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details. - * - * @param mode Monitor mode to set. - */ -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); - - -/*! - * @brief Gets the MCG status flags. - * - * This function gets the MCG clock status flags. All status flags are - * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To - * check a specific flag, compare the return value with the flag. - * - * Example: - * @code - // To check the clock lost lock status of OSC0 and PLL0. - uint32_t mcgFlags; - - mcgFlags = CLOCK_GetStatusFlags(); - - if (mcgFlags & kMCG_Osc0LostFlag) - { - // OSC0 clock lock lost. Do something. - } - if (mcgFlags & kMCG_Pll0LostFlag) - { - // PLL0 clock lock lost. Do something. - } - @endcode - * - * @return Logical OR value of the @ref _mcg_status_flags_t. - */ -uint32_t CLOCK_GetStatusFlags(void); - -/*! - * @brief Clears the MCG status flags. - * - * This function clears the MCG clock lock lost status. The parameter is a logical - * OR value of the flags to clear. See @ref _mcg_status_flags_t. - * - * Example: - * @code - // To clear the clock lost lock status flags of OSC0 and PLL0. - - CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); - @endcode - * - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration @ref _mcg_status_flags_t. - */ -void CLOCK_ClearStatusFlags(uint32_t mask); - -/*@}*/ - -/*! - * @name OSC configuration - * @{ - */ - - -/*! - * @brief Initializes the OSC0. - * - * This function initializes the OSC0 according to the board configuration. - * - * @param config Pointer to the OSC0 configuration structure. - */ -void CLOCK_InitOsc0(osc_config_t const *config); - -/*! - * @brief Deinitializes the OSC0. - * - * This function deinitializes the OSC0. - */ -void CLOCK_DeinitOsc0(void); - -/* @} */ - -/*! - * @name External clock frequency - * @{ - */ - -/*! - * @brief Sets the XTAL0 frequency based on board settings. - * - * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. - */ -static inline void CLOCK_SetXtal0Freq(uint32_t freq) -{ - g_xtal0Freq = freq; -} - - -/*! - * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings. - * - * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. - */ -static inline void CLOCK_SetXtal32Freq(uint32_t freq) -{ - g_xtal32Freq = freq; -} -/* @} */ - -/*! - * @name MCG auto-trim machine. - * @{ - */ - -/*! - * @brief Auto trims the internal reference clock. - * - * This function trims the internal reference clock by using the external clock. If - * successful, it returns the kStatus_Success and the frequency after - * trimming is received in the parameter @p actualFreq. If an error occurs, - * the error code is returned. - * - * @param extFreq External clock frequency, which should be a bus clock. - * @param desireFreq Frequency to trim to. - * @param actualFreq Actual frequency after trimming. - * @param atms Trim fast or slow internal reference clock. - * @retval kStatus_Success ATM success. - * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM. - * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. - * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source. - * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming. - */ -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); -/* @} */ - -/*! @name MCG mode functions. */ -/*@{*/ - -/*! - * @brief Gets the current MCG mode. - * - * This function checks the MCG registers and determines the current MCG mode. - * - * @return Current MCG mode or error code; See @ref mcg_mode_t. - */ -mcg_mode_t CLOCK_GetMode(void); - -/*! - * @brief Sets the MCG to FEI mode. - * - * This function sets the MCG to FEI mode. If setting to FEI mode fails - * from the current mode, this function returns an error. - * - * @param dmx32 DMX32 in FEI mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing - * NULL does not cause a delay. - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to a frequency above 32768 Hz. - */ -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FEE mode. - * - * This function sets the MCG to FEE mode. If setting to FEE mode fails - * from the current mode, this function returns an error. - * - * @param frdiv FLL reference clock divider setting, FRDIV. - * @param dmx32 DMX32 in FEE mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to make sure FLL is stable. Passing - * NULL does not cause a delay. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FBI mode. - * - * This function sets the MCG to FBI mode. If setting to FBI mode fails - * from the current mode, this function returns an error. - * - * @param dmx32 DMX32 in FBI mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL - * is not used in FBI mode, this parameter can be NULL. Passing - * NULL does not cause a delay. - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to frequency above 32768 Hz. - */ -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FBE mode. - * - * This function sets the MCG to FBE mode. If setting to FBE mode fails - * from the current mode, this function returns an error. - * - * @param frdiv FLL reference clock divider setting, FRDIV. - * @param dmx32 DMX32 in FBE mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL - * is not used in FBE mode, this parameter can be NULL. Passing NULL - * does not cause a delay. - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to BLPI mode. - * - * This function sets the MCG to BLPI mode. If setting to BLPI mode fails - * from the current mode, this function returns an error. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetBlpiMode(void); - -/*! - * @brief Sets the MCG to BLPE mode. - * - * This function sets the MCG to BLPE mode. If setting to BLPE mode fails - * from the current mode, this function returns an error. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_SetBlpeMode(void); - - -/*! - * @brief Switches the MCG to FBE mode from the external mode. - * - * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. - * The external clock is used as the system clock souce and PLL is disabled. However, - * the FLL settings are not configured. This is a lite function with a small code size, which is useful - * during the mode switch. For example, to switch from PEE mode to FEI mode: - * - * @code - * CLOCK_ExternalModeToFbeModeQuick(); - * CLOCK_SetFeiMode(...); - * @endcode - * - * @retval kStatus_Success Switched successfully. - * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function. - */ -status_t CLOCK_ExternalModeToFbeModeQuick(void); - -/*! - * @brief Switches the MCG to FBI mode from internal modes. - * - * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. - * The MCGIRCLK is used as the system clock souce and PLL is disabled. However, - * FLL settings are not configured. This is a lite function with a small code size, which is useful - * during the mode switch. For example, to switch from PEI mode to FEE mode: - * - * @code - * CLOCK_InternalModeToFbiModeQuick(); - * CLOCK_SetFeeMode(...); - * @endcode - * - * @retval kStatus_Success Switched successfully. - * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function. - */ -status_t CLOCK_InternalModeToFbiModeQuick(void); - -/*! - * @brief Sets the MCG to FEI mode during system boot up. - * - * This function sets the MCG to FEI mode from the reset mode. It can also be used to - * set up MCG during system boot up. - * - * @param dmx32 DMX32 in FEI mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to ensure that the FLL is stable. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed - * to frequency above 32768 Hz. - */ -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to FEE mode during system bootup. - * - * This function sets MCG to FEE mode from the reset mode. It can also be used to - * set up the MCG during system boot up. - * - * @param oscsel OSC clock select, OSCSEL. - * @param frdiv FLL reference clock divider setting, FRDIV. - * @param dmx32 DMX32 in FEE mode. - * @param drs The DCO range selection. - * @param fllStableDelay Delay function to ensure that the FLL is stable. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToFeeMode( - mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); - -/*! - * @brief Sets the MCG to BLPI mode during system boot up. - * - * This function sets the MCG to BLPI mode from the reset mode. It can also be used to - * set up the MCG during sytem boot up. - * - * @param fcrdiv Fast IRC divider, FCRDIV. - * @param ircs The internal reference clock to select, IRCS. - * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. - * - * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); - -/*! - * @brief Sets the MCG to BLPE mode during sytem boot up. - * - * This function sets the MCG to BLPE mode from the reset mode. It can also be used to - * set up the MCG during sytem boot up. - * - * @param oscsel OSC clock select, MCG_C7[OSCSEL]. - * - * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. - * @retval kStatus_Success Switched to the target mode successfully. - */ -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); - - -/*! - * @brief Sets the MCG to a target mode. - * - * This function sets MCG to a target mode defined by the configuration - * structure. If switching to the target mode fails, this function - * chooses the correct path. - * - * @param config Pointer to the target MCG mode configuration structure. - * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status. - * - * @note If the external clock is used in the target mode, ensure that it is - * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this - * function. - */ -status_t CLOCK_SetMcgConfig(mcg_config_t const *config); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_cmp.c b/third_party/nxp/MKW41Z4/drivers/fsl_cmp.c deleted file mode 100644 index 6a5f15a75..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_cmp.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_cmp.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for CMP module. - * - * @param base CMP peripheral base address - */ -static uint32_t CMP_GetInstance(CMP_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to CMP bases for each instance. */ -static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to CMP clocks for each instance. */ -static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Codes - ******************************************************************************/ -static uint32_t CMP_GetInstance(CMP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++) - { - if (s_cmpBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_cmpBases)); - - return instance; -} - -void CMP_Init(CMP_Type *base, const cmp_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure. */ - CMP_Enable(base, false); /* Disable the CMP module during configuring. */ - /* CMPx_CR1. */ - tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); - if (config->enableHighSpeed) - { - tmp8 |= CMP_CR1_PMODE_MASK; - } - if (config->enableInvertOutput) - { - tmp8 |= CMP_CR1_INV_MASK; - } - if (config->useUnfilteredOutput) - { - tmp8 |= CMP_CR1_COS_MASK; - } - if (config->enablePinOut) - { - tmp8 |= CMP_CR1_OPE_MASK; - } -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - if (config->enableTriggerMode) - { - tmp8 |= CMP_CR1_TRIGM_MASK; - } - else - { - tmp8 &= ~CMP_CR1_TRIGM_MASK; - } -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ - base->CR1 = tmp8; - - /* CMPx_CR0. */ - tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; - tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); - base->CR0 = tmp8; - - CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ -} - -void CMP_Deinit(CMP_Type *base) -{ - /* Disable the CMP module. */ - CMP_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - assert(NULL != config); - - config->enableCmp = true; /* Enable the CMP module after initialization. */ - config->hysteresisMode = kCMP_HysteresisLevel0; - config->enableHighSpeed = false; - config->enableInvertOutput = false; - config->useUnfilteredOutput = false; - config->enablePinOut = false; -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - config->enableTriggerMode = false; -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ -} - -void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) -{ - uint8_t tmp8 = base->MUXCR; - - tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); - tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); - base->MUXCR = tmp8; -} - -#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA -void CMP_EnableDMA(CMP_Type *base, bool enable) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (enable) - { - tmp8 |= CMP_SCR_DMAEN_MASK; - } - else - { - tmp8 &= ~CMP_SCR_DMAEN_MASK; - } - base->SCR = tmp8; -} -#endif /* FSL_FEATURE_CMP_HAS_DMA */ - -void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - -#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT - /* Choose the clock source for sampling. */ - if (config->enableSample) - { - base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ - } - else - { - base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ - } -#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ - /* Set the filter count. */ - tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; - tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); - base->CR0 = tmp8; - /* Set the filter period. It is used as the divider to bus clock. */ - base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); -} - -void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) -{ - uint8_t tmp8 = 0U; - - if (NULL == config) - { - /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ - base->DACCR = 0U; - return; - } - /* CMPx_DACCR. */ - tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ - if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) - { - tmp8 |= CMP_DACCR_VRSEL_MASK; - } - tmp8 |= CMP_DACCR_VOSEL(config->DACValue); - - base->DACCR = tmp8; -} - -void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingInterruptEnable & mask)) - { - tmp8 |= CMP_SCR_IER_MASK; - } - if (0U != (kCMP_OutputFallingInterruptEnable & mask)) - { - tmp8 |= CMP_SCR_IEF_MASK; - } - base->SCR = tmp8; -} - -void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingInterruptEnable & mask)) - { - tmp8 &= ~CMP_SCR_IER_MASK; - } - if (0U != (kCMP_OutputFallingInterruptEnable & mask)) - { - tmp8 &= ~CMP_SCR_IEF_MASK; - } - base->SCR = tmp8; -} - -uint32_t CMP_GetStatusFlags(CMP_Type *base) -{ - uint32_t ret32 = 0U; - - if (0U != (CMP_SCR_CFR_MASK & base->SCR)) - { - ret32 |= kCMP_OutputRisingEventFlag; - } - if (0U != (CMP_SCR_CFF_MASK & base->SCR)) - { - ret32 |= kCMP_OutputFallingEventFlag; - } - if (0U != (CMP_SCR_COUT_MASK & base->SCR)) - { - ret32 |= kCMP_OutputAssertEventFlag; - } - return ret32; -} - -void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingEventFlag & mask)) - { - tmp8 |= CMP_SCR_CFR_MASK; - } - if (0U != (kCMP_OutputFallingEventFlag & mask)) - { - tmp8 |= CMP_SCR_CFF_MASK; - } - base->SCR = tmp8; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_cmp.h b/third_party/nxp/MKW41Z4/drivers/fsl_cmp.h deleted file mode 100644 index 5d16bf08d..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_cmp.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CMP_H_ -#define _FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CMP driver version 2.0.0. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! -* @brief Interrupt enable/disable mask. -*/ -enum _cmp_interrupt_enable -{ - kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ - kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ -}; - -/*! - * @brief Status flags' mask. - */ -enum _cmp_status_flags -{ - kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ - kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ - kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ -}; - -/*! - * @brief CMP Hysteresis mode. - */ -typedef enum _cmp_hysteresis_mode -{ - kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ - kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ - kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ - kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ -} cmp_hysteresis_mode_t; - -/*! - * @brief CMP Voltage Reference source. - */ -typedef enum _cmp_reference_voltage_source -{ - kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */ - kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */ -} cmp_reference_voltage_source_t; - -/*! - * @brief Configures the comparator. - */ -typedef struct _cmp_config -{ - bool enableCmp; /*!< Enable the CMP module. */ - cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ - bool enableHighSpeed; /*!< Enable High-speed (HS) comparison mode. */ - bool enableInvertOutput; /*!< Enable the inverted comparator output. */ - bool useUnfilteredOutput; /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */ - bool enablePinOut; /*!< The comparator output is available on the associated pin. */ -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - bool enableTriggerMode; /*!< Enable the trigger mode. */ -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ -} cmp_config_t; - -/*! - * @brief Configures the filter. - */ -typedef struct _cmp_filter_config -{ -#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT - bool enableSample; /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */ -#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ - uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/ - uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */ -} cmp_filter_config_t; - -/*! - * @brief Configures the internal DAC. - */ -typedef struct _cmp_dac_config -{ - cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ - uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ -} cmp_dac_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the CMP. - * - * This function initializes the CMP module. The operations included are as follows. - * - Enabling the clock for CMP module. - * - Configuring the comparator. - * - Enabling the CMP module. - * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for - * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. - * - * @param base CMP peripheral base address. - * @param config Pointer to the configuration structure. - */ -void CMP_Init(CMP_Type *base, const cmp_config_t *config); - -/*! - * @brief De-initializes the CMP module. - * - * This function de-initializes the CMP module. The operations included are as follows. - * - Disabling the CMP module. - * - Disabling the clock for CMP module. - * - * This function disables the clock for the CMP. - * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the - * clock for the CMP, ensure that all the CMP instances are not used. - * - * @param base CMP peripheral base address. - */ -void CMP_Deinit(CMP_Type *base); - -/*! - * @brief Enables/disables the CMP module. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the module. - */ -static inline void CMP_Enable(CMP_Type *base, bool enable) -{ - if (enable) - { - base->CR1 |= CMP_CR1_EN_MASK; - } - else - { - base->CR1 &= ~CMP_CR1_EN_MASK; - } -} - -/*! -* @brief Initializes the CMP user configuration structure. -* -* This function initializes the user configuration structure to these default values. -* @code -* config->enableCmp = true; -* config->hysteresisMode = kCMP_HysteresisLevel0; -* config->enableHighSpeed = false; -* config->enableInvertOutput = false; -* config->useUnfilteredOutput = false; -* config->enablePinOut = false; -* config->enableTriggerMode = false; -* @endcode -* @param config Pointer to the configuration structure. -*/ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/*! - * @brief Sets the input channels for the comparator. - * - * This function sets the input channels for the comparator. - * Note that two input channels cannot be set the same way in the application. When the user selects the same input - * from the analog mux to the positive and negative port, the comparator is disabled automatically. - * - * @param base CMP peripheral base address. - * @param positiveChannel Positive side input channel number. Available range is 0-7. - * @param negativeChannel Negative side input channel number. Available range is 0-7. - */ -void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); - -/* @} */ - -/*! - * @name Advanced Features - * @{ - */ - -#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA -/*! - * @brief Enables/disables the DMA request for rising/falling events. - * - * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of - * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP - * if the DMA is disabled. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the feature. - */ -void CMP_EnableDMA(CMP_Type *base, bool enable); -#endif /* FSL_FEATURE_CMP_HAS_DMA */ - -#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE -/*! - * @brief Enables/disables the window mode. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the feature. - */ -static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) -{ - if (enable) - { - base->CR1 |= CMP_CR1_WE_MASK; - } - else - { - base->CR1 &= ~CMP_CR1_WE_MASK; - } -} -#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ - -#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE -/*! - * @brief Enables/disables the pass through mode. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the feature. - */ -static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) -{ - if (enable) - { - base->MUXCR |= CMP_MUXCR_PSTM_MASK; - } - else - { - base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; - } -} -#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ - -/*! - * @brief Configures the filter. - * - * @param base CMP peripheral base address. - * @param config Pointer to the configuration structure. - */ -void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); - -/*! - * @brief Configures the internal DAC. - * - * @param base CMP peripheral base address. - * @param config Pointer to the configuration structure. "NULL" disables the feature. - */ -void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); - -/*! - * @brief Enables the interrupts. - * - * @param base CMP peripheral base address. - * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". - */ -void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); - -/*! - * @brief Disables the interrupts. - * - * @param base CMP peripheral base address. - * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". - */ -void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Results - * @{ - */ - -/*! - * @brief Gets the status flags. - * - * @param base CMP peripheral base address. - * - * @return Mask value for the asserted flags. See "_cmp_status_flags". - */ -uint32_t CMP_GetStatusFlags(CMP_Type *base); - -/*! - * @brief Clears the status flags. - * - * @param base CMP peripheral base address. - * @param mask Mask value for the flags. See "_cmp_status_flags". - */ -void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); - -/* @} */ -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_CMP_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_cmt.c b/third_party/nxp/MKW41Z4/drivers/fsl_cmt.c deleted file mode 100644 index 8cf72bc7e..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_cmt.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_cmt.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* The standard intermediate frequency (IF). */ -#define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U) -/* CMT data modulate mask. */ -#define CMT_MODULATE_COUNT_WIDTH (8U) -/* CMT diver 1. */ -#define CMT_CMTDIV_ONE (1) -/* CMT diver 2. */ -#define CMT_CMTDIV_TWO (2) -/* CMT diver 4. */ -#define CMT_CMTDIV_FOUR (4) -/* CMT diver 8. */ -#define CMT_CMTDIV_EIGHT (8) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for CMT module. - * - * @param base CMT peripheral base address. - */ -static uint32_t CMT_GetInstance(CMT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to cmt clocks for each instance. */ -static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to cmt bases for each instance. */ -static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS; - -/*! @brief Pointers to cmt IRQ number for each instance. */ -static const IRQn_Type s_cmtIrqs[] = CMT_IRQS; - -/******************************************************************************* - * Codes - ******************************************************************************/ - -static uint32_t CMT_GetInstance(CMT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_cmtBases); instance++) - { - if (s_cmtBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_cmtBases)); - - return instance; -} - -void CMT_GetDefaultConfig(cmt_config_t *config) -{ - assert(config); - - /* Default infrared output is enabled and set with high active, the divider is set to 1. */ - config->isInterruptEnabled = false; - config->isIroEnabled = true; - config->iroPolarity = kCMT_IROActiveHigh; - config->divider = kCMT_SecondClkDiv1; -} - -void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz) -{ - assert(config); - assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ); - - uint8_t divider; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate clock. */ - CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Sets clock divider. The divider set in pps should be set - to make sycClock_Hz/divder = 8MHz */ - base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1); - divider = base->MSC; - divider &= ~CMT_MSC_CMTDIV_MASK; - divider |= CMT_MSC_CMTDIV(config->divider); - base->MSC = divider; - - /* Set the IRO signal. */ - base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled); - - /* Set interrupt. */ - if (config->isInterruptEnabled) - { - CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable); - EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); - } -} - -void CMT_Deinit(CMT_Type *base) -{ - /*Disable the CMT modulator. */ - base->MSC = 0; - - /* Disable the interrupt. */ - CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable); - DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig) -{ - uint8_t mscReg = base->MSC; - - /* Judge the mode. */ - if (mode != kCMT_DirectIROCtl) - { - assert(modulateConfig); - - /* Set carrier generator. */ - CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1); - if (mode == kCMT_FSKMode) - { - CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2); - } - - /* Set carrier modulator. */ - CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount); - mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK); - mscReg |= mode; - } - else - { - mscReg &= ~CMT_MSC_MCGEN_MASK; - } - /* Set the CMT mode. */ - base->MSC = mscReg; -} - -cmt_mode_t CMT_GetMode(CMT_Type *base) -{ - uint8_t mode = base->MSC; - - if (!(mode & CMT_MSC_MCGEN_MASK)) - { /* Carrier modulator disabled and the IRO signal is in direct software control. */ - return kCMT_DirectIROCtl; - } - else - { - /* Carrier modulator is enabled. */ - if (mode & CMT_MSC_BASE_MASK) - { - /* Base band mode. */ - return kCMT_BasebandMode; - } - else if (mode & CMT_MSC_FSK_MASK) - { - /* FSK mode. */ - return kCMT_FSKMode; - } - else - { - /* Time mode. */ - return kCMT_TimeMode; - } - } -} - -uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz) -{ - uint32_t frequency; - uint32_t divider; - - /* Get intermediate frequency. */ - frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1); - - /* Get the second divider. */ - divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT); - /* Get CMT frequency. */ - switch ((cmt_second_clkdiv_t)divider) - { - case kCMT_SecondClkDiv1: - frequency = frequency / CMT_CMTDIV_ONE; - break; - case kCMT_SecondClkDiv2: - frequency = frequency / CMT_CMTDIV_TWO; - break; - case kCMT_SecondClkDiv4: - frequency = frequency / CMT_CMTDIV_FOUR; - break; - case kCMT_SecondClkDiv8: - frequency = frequency / CMT_CMTDIV_EIGHT; - break; - default: - frequency = frequency / CMT_CMTDIV_ONE; - break; - } - - return frequency; -} - -void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount) -{ - /* Set modulate mark. */ - base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK; - base->CMD2 = (markCount & CMT_CMD2_MB_MASK); - /* Set modulate space. */ - base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK; - base->CMD4 = spaceCount & CMT_CMD4_SB_MASK; -} - -void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state) -{ - uint8_t ocReg = base->OC; - - ocReg &= ~CMT_OC_IROL_MASK; - ocReg |= CMT_OC_IROL(state); - - /* Set the infrared output signal control. */ - base->OC = ocReg; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_cmt.h b/third_party/nxp/MKW41Z4/drivers/fsl_cmt.h deleted file mode 100644 index 3d81f8a9a..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_cmt.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_CMT_H_ -#define _FSL_CMT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmt - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CMT driver version 2.0.1. */ -#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief The modes of CMT. - */ -typedef enum _cmt_mode -{ - kCMT_DirectIROCtl = 0x00U, /*!< Carrier modulator is disabled and the IRO signal is directly in software control */ - kCMT_TimeMode = 0x01U, /*!< Carrier modulator is enabled in time mode. */ - kCMT_FSKMode = 0x05U, /*!< Carrier modulator is enabled in FSK mode. */ - kCMT_BasebandMode = 0x09U /*!< Carrier modulator is enabled in baseband mode. */ -} cmt_mode_t; - -/*! - * @brief The CMT clock divide primary prescaler. - * The primary clock divider is used to divider the bus clock to - * get the intermediate frequency to approximately equal to 8 MHZ. - * When the bus clock is 8 MHZ, set primary prescaler to "kCMT_PrimaryClkDiv1". - */ -typedef enum _cmt_primary_clkdiv -{ - kCMT_PrimaryClkDiv1 = 0U, /*!< The intermediate frequency is the bus clock divided by 1. */ - kCMT_PrimaryClkDiv2 = 1U, /*!< The intermediate frequency is the bus clock divided by 2. */ - kCMT_PrimaryClkDiv3 = 2U, /*!< The intermediate frequency is the bus clock divided by 3. */ - kCMT_PrimaryClkDiv4 = 3U, /*!< The intermediate frequency is the bus clock divided by 4. */ - kCMT_PrimaryClkDiv5 = 4U, /*!< The intermediate frequency is the bus clock divided by 5. */ - kCMT_PrimaryClkDiv6 = 5U, /*!< The intermediate frequency is the bus clock divided by 6. */ - kCMT_PrimaryClkDiv7 = 6U, /*!< The intermediate frequency is the bus clock divided by 7. */ - kCMT_PrimaryClkDiv8 = 7U, /*!< The intermediate frequency is the bus clock divided by 8. */ - kCMT_PrimaryClkDiv9 = 8U, /*!< The intermediate frequency is the bus clock divided by 9. */ - kCMT_PrimaryClkDiv10 = 9U, /*!< The intermediate frequency is the bus clock divided by 10. */ - kCMT_PrimaryClkDiv11 = 10U, /*!< The intermediate frequency is the bus clock divided by 11. */ - kCMT_PrimaryClkDiv12 = 11U, /*!< The intermediate frequency is the bus clock divided by 12. */ - kCMT_PrimaryClkDiv13 = 12U, /*!< The intermediate frequency is the bus clock divided by 13. */ - kCMT_PrimaryClkDiv14 = 13U, /*!< The intermediate frequency is the bus clock divided by 14. */ - kCMT_PrimaryClkDiv15 = 14U, /*!< The intermediate frequency is the bus clock divided by 15. */ - kCMT_PrimaryClkDiv16 = 15U /*!< The intermediate frequency is the bus clock divided by 16. */ -} cmt_primary_clkdiv_t; - -/*! - * @brief The CMT clock divide secondary prescaler. - * The second prescaler can be used to divide the 8 MHZ CMT clock - * by 1, 2, 4, or 8 according to the specification. - */ -typedef enum _cmt_second_clkdiv -{ - kCMT_SecondClkDiv1 = 0U, /*!< The CMT clock is the intermediate frequency frequency divided by 1. */ - kCMT_SecondClkDiv2 = 1U, /*!< The CMT clock is the intermediate frequency frequency divided by 2. */ - kCMT_SecondClkDiv4 = 2U, /*!< The CMT clock is the intermediate frequency frequency divided by 4. */ - kCMT_SecondClkDiv8 = 3U /*!< The CMT clock is the intermediate frequency frequency divided by 8. */ -} cmt_second_clkdiv_t; - -/*! - * @brief The CMT infrared output polarity. - */ -typedef enum _cmt_infrared_output_polarity -{ - kCMT_IROActiveLow = 0U, /*!< The CMT infrared output signal polarity is active-low. */ - kCMT_IROActiveHigh = 1U /*!< The CMT infrared output signal polarity is active-high. */ -} cmt_infrared_output_polarity_t; - -/*! - * @brief The CMT infrared output signal state control. - */ -typedef enum _cmt_infrared_output_state -{ - kCMT_IROCtlLow = 0U, /*!< The CMT Infrared output signal state is controlled to low. */ - kCMT_IROCtlHigh = 1U /*!< The CMT Infrared output signal state is controlled to high. */ -} cmt_infrared_output_state_t; - -/*! - * @brief CMT interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the CMT interrupt configurations. - */ -enum _cmt_interrupt_enable -{ - kCMT_EndOfCycleInterruptEnable = CMT_MSC_EOCIE_MASK, /*!< CMT end of cycle interrupt. */ -}; - -/*! - * @brief CMT carrier generator and modulator configuration structure - * - */ -typedef struct _cmt_modulate_config -{ - uint8_t highCount1; /*!< The high-time for carrier generator first register. */ - uint8_t lowCount1; /*!< The low-time for carrier generator first register. */ - uint8_t highCount2; /*!< The high-time for carrier generator second register for FSK mode. */ - uint8_t lowCount2; /*!< The low-time for carrier generator second register for FSK mode. */ - uint16_t markCount; /*!< The mark time for the modulator gate. */ - uint16_t spaceCount; /*!< The space time for the modulator gate. */ -} cmt_modulate_config_t; - -/*! @brief CMT basic configuration structure. */ -typedef struct _cmt_config -{ - bool isInterruptEnabled; /*!< Timer interrupt 0-disable, 1-enable. */ - bool isIroEnabled; /*!< The IRO output 0-disabled, 1-enabled. */ - cmt_infrared_output_polarity_t iroPolarity; /*!< The IRO polarity. */ - cmt_second_clkdiv_t divider; /*!< The CMT clock divide prescaler. */ -} cmt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Gets the CMT default configuration structure. This API - * gets the default configuration structure for the CMT_Init(). - * Use the initialized structure unchanged in CMT_Init() or modify - * fields of the structure before calling the CMT_Init(). - * - * @param config The CMT configuration structure pointer. - */ -void CMT_GetDefaultConfig(cmt_config_t *config); - -/*! - * @brief Initializes the CMT module. - * - * This function ungates the module clock and sets the CMT internal clock, - * interrupt, and infrared output signal for the CMT module. - * - * @param base CMT peripheral base address. - * @param config The CMT basic configuration structure. - * @param busClock_Hz The CMT module input clock - bus clock frequency. - */ -void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz); - -/*! - * @brief Disables the CMT module and gate control. - * - * This function disables CMT modulator, interrupts, and gates the - * CMT clock control. CMT_Init must be called to use the CMT again. - * - * @param base CMT peripheral base address. - */ -void CMT_Deinit(CMT_Type *base); - -/*! @}*/ - -/*! - * @name Basic Control Operations - * @{ - */ - -/*! - * @brief Selects the mode for CMT. - * - * @param base CMT peripheral base address. - * @param mode The CMT feature mode enumeration. See "cmt_mode_t". - * @param modulateConfig The carrier generation and modulator configuration. - */ -void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig); - -/*! - * @brief Gets the mode of the CMT module. - * - * @param base CMT peripheral base address. - * @return The CMT mode. - * kCMT_DirectIROCtl Carrier modulator is disabled; the IRO signal is directly in software control. - * kCMT_TimeMode Carrier modulator is enabled in time mode. - * kCMT_FSKMode Carrier modulator is enabled in FSK mode. - * kCMT_BasebandMode Carrier modulator is enabled in baseband mode. - */ -cmt_mode_t CMT_GetMode(CMT_Type *base); - -/*! - * @brief Gets the actual CMT clock frequency. - * - * @param base CMT peripheral base address. - * @param busClock_Hz CMT module input clock - bus clock frequency. - * @return The CMT clock frequency. - */ -uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz); - -/*! - * @brief Sets the primary data set for the CMT carrier generator counter. - * - * This function sets the high-time and low-time of the primary data set for the - * CMT carrier generator counter to control the period and the duty cycle of the - * output carrier signal. - * If the CMT clock period is Tcmt, the period of the carrier generator signal equals - * (highCount + lowCount) * Tcmt. The duty cycle equals to highCount / (highCount + lowCount). - * - * @param base CMT peripheral base address. - * @param highCount The number of CMT clocks for carrier generator signal high time, - * integer in the range of 1 ~ 0xFF. - * @param lowCount The number of CMT clocks for carrier generator signal low time, - * integer in the range of 1 ~ 0xFF. - */ -static inline void CMT_SetCarrirGenerateCountOne(CMT_Type *base, uint32_t highCount, uint32_t lowCount) -{ - assert(highCount <= CMT_CGH1_PH_MASK); - assert(highCount); - assert(lowCount <= CMT_CGL1_PL_MASK); - assert(lowCount); - - base->CGH1 = highCount; - base->CGL1 = lowCount; -} - -/*! - * @brief Sets the secondary data set for the CMT carrier generator counter. - * - * This function is used for FSK mode setting the high-time and low-time of the secondary - * data set CMT carrier generator counter to control the period and the duty cycle - * of the output carrier signal. - * If the CMT clock period is Tcmt, the period of the carrier generator signal equals - * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount). - * - * @param base CMT peripheral base address. - * @param highCount The number of CMT clocks for carrier generator signal high time, - * integer in the range of 1 ~ 0xFF. - * @param lowCount The number of CMT clocks for carrier generator signal low time, - * integer in the range of 1 ~ 0xFF. - */ -static inline void CMT_SetCarrirGenerateCountTwo(CMT_Type *base, uint32_t highCount, uint32_t lowCount) -{ - assert(highCount <= CMT_CGH2_SH_MASK); - assert(highCount); - assert(lowCount <= CMT_CGL2_SL_MASK); - assert(lowCount); - - base->CGH2 = highCount; - base->CGL2 = lowCount; -} - -/*! - * @brief Sets the modulation mark and space time period for the CMT modulator. - * - * This function sets the mark time period of the CMT modulator counter - * to control the mark time of the output modulated signal from the carrier generator output signal. - * If the CMT clock frequency is Fcmt and the carrier out signal frequency is fcg: - * - In Time and Baseband mode: The mark period of the generated signal equals (markCount + 1) / (Fcmt/8). - * The space period of the generated signal equals spaceCount / (Fcmt/8). - * - In FSK mode: The mark period of the generated signal equals (markCount + 1)/fcg. - * The space period of the generated signal equals spaceCount / fcg. - * - * @param base Base address for current CMT instance. - * @param markCount The number of clock period for CMT modulator signal mark period, - * in the range of 0 ~ 0xFFFF. - * @param spaceCount The number of clock period for CMT modulator signal space period, - * in the range of the 0 ~ 0xFFFF. - */ -void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount); - -/*! - * @brief Enables or disables the extended space operation. - * - * This function is used to make the space period longer - * for time, baseband, and FSK modes. - * - * @param base CMT peripheral base address. - * @param enable True enable the extended space, false disable the extended space. - */ -static inline void CMT_EnableExtendedSpace(CMT_Type *base, bool enable) -{ - if (enable) - { - base->MSC |= CMT_MSC_EXSPC_MASK; - } - else - { - base->MSC &= ~CMT_MSC_EXSPC_MASK; - } -} - -/*! - * @brief Sets the IRO (infrared output) signal state. - * - * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set - * and the IRO signal is enabled. - * - * @param base CMT peripheral base address. - * @param state The control of the IRO signal. See "cmt_infrared_output_state_t" - */ -void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state); - -/*! - * @brief Enables the CMT interrupt. - * - * This function enables the CMT interrupts according to the provided mask if enabled. - * The CMT only has the end of the cycle interrupt - an interrupt occurs at the end - * of the modulator cycle. This interrupt provides a means for the user - * to reload the new mark/space values into the CMT modulator data registers - * and verify the modulator mark and space. - * For example, to enable the end of cycle, do the following. - * @code - * CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); - * @endcode - * @param base CMT peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. - */ -static inline void CMT_EnableInterrupts(CMT_Type *base, uint32_t mask) -{ - base->MSC |= mask; -} - -/*! - * @brief Disables the CMT interrupt. - * - * This function disables the CMT interrupts according to the provided maskIf enabled. - * The CMT only has the end of the cycle interrupt. - * For example, to disable the end of cycle, do the following. - * @code - * CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); - * @endcode - * - * @param base CMT peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. - */ -static inline void CMT_DisableInterrupts(CMT_Type *base, uint32_t mask) -{ - base->MSC &= ~mask; -} - -/*! - * @brief Gets the end of the cycle status flag. - * - * The flag is set: - * - When the modulator is not currently active and carrier and modulator - * are set to start the initial CMT transmission. - * - At the end of each modulation cycle when the counter is reloaded and - * the carrier and modulator are enabled. - * @param base CMT peripheral base address. - * @return Current status of the end of cycle status flag - * @arg non-zero: End-of-cycle has occurred. - * @arg zero: End-of-cycle has not yet occurred since the flag last cleared. - */ -static inline uint32_t CMT_GetStatusFlags(CMT_Type *base) -{ - return base->MSC & CMT_MSC_EOCF_MASK; -} - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CMT_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_common.c b/third_party/nxp/MKW41Z4/drivers/fsl_common.c deleted file mode 100644 index 3c5048ccf..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_common.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_common.h" -//#include "fsl_debug_console.h" - -#ifndef NDEBUG -#if (defined(__CC_ARM)) || (defined(__ICCARM__)) -void __aeabi_assert(const char *failedExpr, const char *file, int line) -{ - //PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); - for (;;) - { - __BKPT(0); - } -} -#elif(defined(__REDLIB__)) - -#if SDK_DEBUGCONSOLE -void __assertion_failed(char *_Expr) -{ - PRINTF("%s\n", _Expr); - for (;;) - { - __asm("bkpt #0"); - } -} -#endif - -#elif(defined(__GNUC__)) -void __assert_func(const char *file, int line, const char *func, const char *failedExpr) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); - for (;;) - { - __BKPT(0); - } -} -#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ -#endif /* NDEBUG */ - -#ifndef __GIC_PRIO_BITS -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - - return ret; -} -#endif - -#ifndef CPU_QN908X -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - SYSCON->STARTERCLR[index] = 1u << intNumber; -} -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ -#else -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - /* SYSCON->STARTERSET[index] = 1u << intNumber; */ - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - /* SYSCON->STARTERCLR[index] = 1u << intNumber; */ -} -#endif /*CPU_QN908X */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_common.h b/third_party/nxp/MKW41Z4/drivers/fsl_common.h deleted file mode 100644 index f20c09027..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_common.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include - -#if defined(__ICCARM__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable specific interrupt. - * - * Enable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void EnableIRQ(IRQn_Type interrupt) -{ - if (NotAvail_IRQn == interrupt) - { - return; - } - -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) -#endif - { -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - } -} - -/*! - * @brief Disable specific interrupt. - * - * Disable the interrupt not routed from intmux. - * - * @param interrupt The IRQ number. - */ -static inline void DisableIRQ(IRQn_Type interrupt) -{ - if (NotAvail_IRQn == interrupt) - { - return; - } - -#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) - if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) -#endif - { -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - } -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -} - -/*! - * @brief Enaable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -} - -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_cop.c b/third_party/nxp/MKW41Z4/drivers/fsl_cop.c deleted file mode 100644 index 5684daa22..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_cop.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_cop.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -void COP_GetDefaultConfig(cop_config_t *config) -{ - assert(config); - - config->enableWindowMode = false; -#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE - config->timeoutMode = kCOP_LongTimeoutMode; - config->enableStop = false; - config->enableDebug = false; -#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ - config->clockSource = kCOP_LpoClock; - config->timeoutCycles = kCOP_2Power10CyclesOr2Power18Cycles; -} - -void COP_Init(SIM_Type *base, const cop_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - -#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE - value = SIM_COPC_COPW(config->enableWindowMode) | SIM_COPC_COPCLKS(config->timeoutMode) | - SIM_COPC_COPT(config->timeoutCycles) | SIM_COPC_COPSTPEN(config->enableStop) | - SIM_COPC_COPDBGEN(config->enableDebug) | SIM_COPC_COPCLKSEL(config->clockSource); -#else - value = SIM_COPC_COPW(config->enableWindowMode) | SIM_COPC_COPCLKS(config->clockSource) | - SIM_COPC_COPT(config->timeoutCycles); -#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ - base->COPC = value; -} - -void COP_Refresh(SIM_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->SRVCOP = COP_FIRST_BYTE_OF_REFRESH; - base->SRVCOP = COP_SECOND_BYTE_OF_REFRESH; - EnableGlobalIRQ(primaskValue); -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_cop.h b/third_party/nxp/MKW41Z4/drivers/fsl_cop.h deleted file mode 100644 index 1a6fb2141..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_cop.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_COP_H_ -#define _FSL_COP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cop - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief COP driver version 2.0.0. */ -#define FSL_COP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @name COP refresh sequence. */ -/*@{*/ -#define COP_FIRST_BYTE_OF_REFRESH (0x55U) /*!< First byte of refresh sequence */ -#define COP_SECOND_BYTE_OF_REFRESH (0xAAU) /*!< Second byte of refresh sequence */ -/*@}*/ - -/*! @brief COP clock source selection. */ -typedef enum _cop_clock_source -{ - kCOP_LpoClock = 0U, /*!< COP clock sourced from LPO */ -#if defined(FSL_FEATURE_COP_HAS_MORE_CLKSRC) && FSL_FEATURE_COP_HAS_MORE_CLKSRC - kCOP_McgIrClock = 1U, /*!< COP clock sourced from MCGIRCLK */ - kCOP_OscErClock = 2U, /*!< COP clock sourced from OSCERCLK */ -#endif /* FSL_FEATURE_COP_HAS_MORE_CLKSRC */ - kCOP_BusClock = 3U, /*!< COP clock sourced from Bus clock */ -} cop_clock_source_t; - -/*! @brief Define the COP timeout cycles. */ -typedef enum _cop_timeout_cycles -{ - kCOP_2Power5CyclesOr2Power13Cycles = 1U, /*!< 2^5 or 2^13 clock cycles */ - kCOP_2Power8CyclesOr2Power16Cycles = 2U, /*!< 2^8 or 2^16 clock cycles */ - kCOP_2Power10CyclesOr2Power18Cycles = 3U, /*!< 2^10 or 2^18 clock cycles */ -} cop_timeout_cycles_t; - -#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE -/*! @breif Define the COP timeout mode. */ -typedef enum _cop_timeout_mode -{ - kCOP_ShortTimeoutMode = 0U, /*!< COP selects long timeout */ - kCOP_LongTimeoutMode = 1U, /*!< COP selects short timeout */ -} cop_timeout_mode_t; -#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ - -/*! @brief Describes COP configuration structure. */ -typedef struct _cop_config -{ - bool enableWindowMode; /*!< COP run mode: window mode or normal mode */ -#if defined(FSL_FEATURE_COP_HAS_LONGTIME_MODE) && FSL_FEATURE_COP_HAS_LONGTIME_MODE - cop_timeout_mode_t timeoutMode; /*!< COP timeout mode: long timeout or short timeout */ - bool enableStop; /*!< Enable or disable COP in STOP mode */ - bool enableDebug; /*!< Enable or disable COP in DEBUG mode */ -#endif /* FSL_FEATURE_COP_HAS_LONGTIME_MODE */ - cop_clock_source_t clockSource; /*!< Set COP clock source */ - cop_timeout_cycles_t timeoutCycles; /*!< Set COP timeout value */ -} cop_config_t; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @name COP Functional Operation - * @{ - */ - -/*! - * @brief Initializes the COP configuration structure. - * - * This function initializes the COP configuration structure to default values. The default - * values are: - * @code - * copConfig->enableWindowMode = false; - * copConfig->timeoutMode = kCOP_LongTimeoutMode; - * copConfig->enableStop = false; - * copConfig->enableDebug = false; - * copConfig->clockSource = kCOP_LpoClock; - * copConfig->timeoutCycles = kCOP_2Power10CyclesOr2Power18Cycles; - * @endcode - * - * @param config Pointer to the COP configuration structure. - * @see cop_config_t - */ -void COP_GetDefaultConfig(cop_config_t *config); - -/*! - * @brief Initializes the COP module. - * - * This function configures the COP. After it is called, the COP - * starts running according to the configuration. - * Because all COP control registers are write-once only, the COP_Init function - * and the COP_Disable function can be called only once. A second call has no effect. - * - * Example: - * @code - * cop_config_t config; - * COP_GetDefaultConfig(&config); - * config.timeoutCycles = kCOP_2Power8CyclesOr2Power16Cycles; - * COP_Init(sim_base,&config); - * @endcode - * - * @param base SIM peripheral base address. - * @param config The configuration of COP. - */ -void COP_Init(SIM_Type *base, const cop_config_t *config); - -/*! - * @brief De-initializes the COP module. - * This dedicated function is not provided. Instead, the COP_Disable function can be used to disable the COP. - */ - -/*! - * @brief Disables the COP module. - * - * This function disables the COP Watchdog. - * Note: The COP configuration register is a write-once after reset. - * To disable the COP Watchdog, call this function first. - * - * @param base SIM peripheral base address. - */ -static inline void COP_Disable(SIM_Type *base) -{ - base->COPC &= ~SIM_COPC_COPT_MASK; -} - -/*! - * @brief Refreshes the COP timer - * - * This function feeds the COP. - * - * @param base SIM peripheral base address. - */ -void COP_Refresh(SIM_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_COP_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dac.c b/third_party/nxp/MKW41Z4/drivers/fsl_dac.c deleted file mode 100644 index 8d13d6228..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dac.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dac.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for DAC module. - * - * @param base DAC peripheral base address - */ -static uint32_t DAC_GetInstance(DAC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to DAC bases for each instance. */ -static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to DAC clocks for each instance. */ -static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Codes - ******************************************************************************/ -static uint32_t DAC_GetInstance(DAC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++) - { - if (s_dacBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dacBases)); - - return instance; -} - -void DAC_Init(DAC_Type *base, const dac_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure. */ - /* DACx_C0. */ - tmp8 = base->C0 & ~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK); - if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource) - { - tmp8 |= DAC_C0_DACRFS_MASK; - } - if (config->enableLowPowerMode) - { - tmp8 |= DAC_C0_LPEN_MASK; - } - base->C0 = tmp8; - - /* DAC_Enable(base, true); */ - /* Tip: The DAC output can be enabled till then after user sets their own available data in application. */ -} - -void DAC_Deinit(DAC_Type *base) -{ - DAC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void DAC_GetDefaultConfig(dac_config_t *config) -{ - assert(NULL != config); - - config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; - config->enableLowPowerMode = false; -} - -void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - - /* DACx_C0. */ - tmp8 = base->C0 & ~(DAC_C0_DACTRGSEL_MASK); - if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode) - { - tmp8 |= DAC_C0_DACTRGSEL_MASK; - } - base->C0 = tmp8; - - /* DACx_C1. */ - tmp8 = base->C1 & - ~( -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION - DAC_C1_DACBFWM_MASK | -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ - DAC_C1_DACBFMD_MASK); -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION - tmp8 |= DAC_C1_DACBFWM(config->watermark); -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ - tmp8 |= DAC_C1_DACBFMD(config->workMode); - base->C1 = tmp8; - - /* DACx_C2. */ - tmp8 = base->C2 & ~DAC_C2_DACBFUP_MASK; - tmp8 |= DAC_C2_DACBFUP(config->upperLimit); - base->C2 = tmp8; -} - -void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config) -{ - assert(NULL != config); - - config->triggerMode = kDAC_BufferTriggerBySoftwareMode; -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION - config->watermark = kDAC_BufferWatermark1Word; -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ - config->workMode = kDAC_BufferWorkAsNormalMode; - config->upperLimit = DAC_DATL_COUNT - 1U; -} - -void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value) -{ - assert(index < DAC_DATL_COUNT); - - base->DAT[index].DATL = (uint8_t)(0xFFU & value); /* Low 8-bit. */ - base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */ -} - -void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index) -{ - assert(index < DAC_DATL_COUNT); - - uint8_t tmp8 = base->C2 & ~DAC_C2_DACBFRP_MASK; - - tmp8 |= DAC_C2_DACBFRP(index); - base->C2 = tmp8; -} - -void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask) -{ - mask &= ( -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION - DAC_C0_DACBWIEN_MASK | -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); - base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */ -} - -void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask) -{ - mask &= ( -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION - DAC_C0_DACBWIEN_MASK | -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); - base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */ -} - -uint32_t DAC_GetBufferStatusFlags(DAC_Type *base) -{ - return (uint32_t)(base->SR & ( -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION - DAC_SR_DACBFWMF_MASK | -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK)); -} - -void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask) -{ - mask &= ( -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION - DAC_SR_DACBFWMF_MASK | -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK); - base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */ -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dac.h b/third_party/nxp/MKW41Z4/drivers/fsl_dac.h deleted file mode 100644 index b71febf3b..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dac.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DAC_H_ -#define _FSL_DAC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dac - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DAC driver version 2.0.1. */ -#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief DAC buffer flags. - */ -enum _dac_buffer_status_flags -{ -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION - kDAC_BufferWatermarkFlag = DAC_SR_DACBFWMF_MASK, /*!< DAC Buffer Watermark Flag. */ -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - kDAC_BufferReadPointerTopPositionFlag = DAC_SR_DACBFRPTF_MASK, /*!< DAC Buffer Read Pointer Top Position Flag. */ - kDAC_BufferReadPointerBottomPositionFlag = DAC_SR_DACBFRPBF_MASK, /*!< DAC Buffer Read Pointer Bottom Position - Flag. */ -}; - -/*! - * @brief DAC buffer interrupts. - */ -enum _dac_buffer_interrupt_enable -{ -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION - kDAC_BufferWatermarkInterruptEnable = DAC_C0_DACBWIEN_MASK, /*!< DAC Buffer Watermark Interrupt Enable. */ -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ - kDAC_BufferReadPointerTopInterruptEnable = DAC_C0_DACBTIEN_MASK, /*!< DAC Buffer Read Pointer Top Flag Interrupt - Enable. */ - kDAC_BufferReadPointerBottomInterruptEnable = DAC_C0_DACBBIEN_MASK, /*!< DAC Buffer Read Pointer Bottom Flag - Interrupt Enable */ -}; - -/*! - * @brief DAC reference voltage source. - */ -typedef enum _dac_reference_voltage_source -{ - kDAC_ReferenceVoltageSourceVref1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */ - kDAC_ReferenceVoltageSourceVref2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */ -} dac_reference_voltage_source_t; - -/*! - * @brief DAC buffer trigger mode. - */ -typedef enum _dac_buffer_trigger_mode -{ - kDAC_BufferTriggerByHardwareMode = 0U, /*!< The DAC hardware trigger is selected. */ - kDAC_BufferTriggerBySoftwareMode = 1U, /*!< The DAC software trigger is selected. */ -} dac_buffer_trigger_mode_t; - -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION -/*! - * @brief DAC buffer watermark. - */ -typedef enum _dac_buffer_watermark -{ -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD - kDAC_BufferWatermark1Word = 0U, /*!< 1 word away from the upper limit. */ -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */ -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS - kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */ -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS */ -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS - kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */ -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS */ -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS - kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */ -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS */ -} dac_buffer_watermark_t; -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ - -/*! - * @brief DAC buffer work mode. - */ -typedef enum _dac_buffer_work_mode -{ - kDAC_BufferWorkAsNormalMode = 0U, /*!< Normal mode. */ -#if defined(FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE - kDAC_BufferWorkAsSwingMode, /*!< Swing mode. */ -#endif /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */ - kDAC_BufferWorkAsOneTimeScanMode, /*!< One-Time Scan mode. */ -#if defined(FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE - kDAC_BufferWorkAsFIFOMode, /*!< FIFO mode. */ -#endif /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */ -} dac_buffer_work_mode_t; - -/*! - * @brief DAC module configuration. - */ -typedef struct _dac_config -{ - dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */ - bool enableLowPowerMode; /*!< Enable the low-power mode. */ -} dac_config_t; - -/*! - * @brief DAC buffer configuration. - */ -typedef struct _dac_buffer_config -{ - dac_buffer_trigger_mode_t triggerMode; /*!< Select the buffer's trigger mode. */ -#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION - dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */ -#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ - dac_buffer_work_mode_t workMode; /*!< Select the buffer's work mode. */ - uint8_t upperLimit; /*!< Set the upper limit for the buffer index. - Normally, 0-15 is available for a buffer with 16 items. */ -} dac_buffer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the DAC module. - * - * This function initializes the DAC module including the following operations. - * - Enabling the clock for DAC module. - * - Configuring the DAC converter with a user configuration. - * - Enabling the DAC module. - * - * @param base DAC peripheral base address. - * @param config Pointer to the configuration structure. See "dac_config_t". - */ -void DAC_Init(DAC_Type *base, const dac_config_t *config); - -/*! - * @brief De-initializes the DAC module. - * - * This function de-initializes the DAC module including the following operations. - * - Disabling the DAC module. - * - Disabling the clock for the DAC module. - * - * @param base DAC peripheral base address. - */ -void DAC_Deinit(DAC_Type *base); - -/*! - * @brief Initializes the DAC user configuration structure. - * - * This function initializes the user configuration structure to a default value. The default values are as follows. - * @code - * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; - * config->enableLowPowerMode = false; - * @endcode - * @param config Pointer to the configuration structure. See "dac_config_t". - */ -void DAC_GetDefaultConfig(dac_config_t *config); - -/*! - * @brief Enables the DAC module. - * - * @param base DAC peripheral base address. - * @param enable Enables or disables the feature. - */ -static inline void DAC_Enable(DAC_Type *base, bool enable) -{ - if (enable) - { - base->C0 |= DAC_C0_DACEN_MASK; - } - else - { - base->C0 &= ~DAC_C0_DACEN_MASK; - } -} - -/* @} */ - -/*! - * @name Buffer - * @{ - */ - -/*! - * @brief Enables the DAC buffer. - * - * @param base DAC peripheral base address. - * @param enable Enables or disables the feature. - */ -static inline void DAC_EnableBuffer(DAC_Type *base, bool enable) -{ - if (enable) - { - base->C1 |= DAC_C1_DACBFEN_MASK; - } - else - { - base->C1 &= ~DAC_C1_DACBFEN_MASK; - } -} - -/*! - * @brief Configures the CMP buffer. - * - * @param base DAC peripheral base address. - * @param config Pointer to the configuration structure. See "dac_buffer_config_t". - */ -void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config); - -/*! - * @brief Initializes the DAC buffer configuration structure. - * - * This function initializes the DAC buffer configuration structure to default values. The default values are as follows. - * @code - * config->triggerMode = kDAC_BufferTriggerBySoftwareMode; - * config->watermark = kDAC_BufferWatermark1Word; - * config->workMode = kDAC_BufferWorkAsNormalMode; - * config->upperLimit = DAC_DATL_COUNT - 1U; - * @endcode - * @param config Pointer to the configuration structure. See "dac_buffer_config_t". - */ -void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config); - -/*! - * @brief Enables the DMA for DAC buffer. - * - * @param base DAC peripheral base address. - * @param enable Enables or disables the feature. - */ -static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable) -{ - if (enable) - { - base->C1 |= DAC_C1_DMAEN_MASK; - } - else - { - base->C1 &= ~DAC_C1_DMAEN_MASK; - } -} - -/*! - * @brief Sets the value for items in the buffer. - * - * @param base DAC peripheral base address. - * @param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC buffer. - * @param value Setting the value for items in the buffer. 12-bits are available. - */ -void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value); - -/*! - * @brief Triggers the buffer using software and updates the read pointer of the DAC buffer. - * - * This function triggers the function using software. The read pointer of the DAC buffer is updated with one step - * after this function is called. Changing the read pointer depends on the buffer's work mode. - * - * @param base DAC peripheral base address. - */ -static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base) -{ - base->C0 |= DAC_C0_DACSWTRG_MASK; -} - -/*! - * @brief Gets the current read pointer of the DAC buffer. - * - * This function gets the current read pointer of the DAC buffer. - * The current output value depends on the item indexed by the read pointer. It is updated either - * by a software trigger or a hardware trigger. - * - * @param base DAC peripheral base address. - * - * @return The current read pointer of the DAC buffer. - */ -static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base) -{ - return ((base->C2 & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT); -} - -/*! - * @brief Sets the current read pointer of the DAC buffer. - * - * This function sets the current read pointer of the DAC buffer. - * The current output value depends on the item indexed by the read pointer. It is updated either by a - * software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes. - * - * @param base DAC peripheral base address. - * @param index Setting an index value for the pointer. - */ -void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index); - -/*! - * @brief Enables interrupts for the DAC buffer. - * - * @param base DAC peripheral base address. - * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". - */ -void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask); - -/*! - * @brief Disables interrupts for the DAC buffer. - * - * @param base DAC peripheral base address. - * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". - */ -void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask); - -/*! - * @brief Gets the flags of events for the DAC buffer. - * - * @param base DAC peripheral base address. - * - * @return Mask value for the asserted flags. See "_dac_buffer_status_flags". - */ -uint32_t DAC_GetBufferStatusFlags(DAC_Type *base); - -/*! - * @brief Clears the flags of events for the DAC buffer. - * - * @param base DAC peripheral base address. - * @param mask Mask value for flags. See "_dac_buffer_status_flags_t". - */ -void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_DAC_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dmamux.c b/third_party/nxp/MKW41Z4/drivers/fsl_dmamux.c deleted file mode 100644 index 39ce9cfbe..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dmamux.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dmamux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMAMUX. - * - * @param base DMAMUX peripheral base address. - */ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMAMUX instance number to base pointer. */ -static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMAMUX instance number to clock name. */ -static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++) - { - if (s_dmamuxBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dmamuxBases)); - - return instance; -} - -void DMAMUX_Init(DMAMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void DMAMUX_Deinit(DMAMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dmamux.h b/third_party/nxp/MKW41Z4/drivers/fsl_dmamux.h deleted file mode 100644 index 071348b2c..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dmamux.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DMAMUX_H_ -#define _FSL_DMAMUX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dmamux - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMAMUX driver version 2.0.2. */ -#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMAMUX Initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the DMAMUX peripheral. - * - * This function ungates the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - * - */ -void DMAMUX_Init(DMAMUX_Type *base); - -/*! - * @brief Deinitializes the DMAMUX peripheral. - * - * This function gates the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - */ -void DMAMUX_Deinit(DMAMUX_Type *base); - -/* @} */ -/*! - * @name DMAMUX Channel Operation - * @{ - */ - -/*! - * @brief Enables the DMAMUX channel. - * - * This function enables the DMAMUX channel. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Disables the DMAMUX channel. - * - * This function disables the DMAMUX channel. - * - * @note The user must disable the DMAMUX channel before configuring it. - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Configures the DMAMUX channel source. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - * @param source Channel source, which is used to trigger the DMA transfer. - */ -static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); -} - -#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U -/*! - * @brief Enables the DMAMUX period trigger. - * - * This function enables the DMAMUX period trigger feature. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; -} - -/*! - * @brief Disables the DMAMUX period trigger. - * - * This function disables the DMAMUX period trigger. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; -} -#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ - -#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON) -/*! - * @brief Enables the DMA channel to be always ON. - * - * This function enables the DMAMUX channel always ON feature. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled. - */ -static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - if (enable) - { - base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK; - } - else - { - base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK; - } -} -#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /* _FSL_DMAMUX_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dspi.c b/third_party/nxp/MKW41Z4/drivers/fsl_dspi.c deleted file mode 100644 index 5717ada0d..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dspi.c +++ /dev/null @@ -1,1669 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dspi.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Typedef for master interrupt handler. */ -typedef void (*dspi_master_isr_t)(SPI_Type *base, dspi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*dspi_slave_isr_t)(SPI_Type *base, dspi_slave_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for DSPI module. - * - * @param base DSPI peripheral base address. - */ -uint32_t DSPI_GetInstance(SPI_Type *base); - -/*! - * @brief Configures the DSPI peripheral chip select polarity. - * - * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and - * configures the Pcs signal to operate with the desired characteristic. - * - * @param base DSPI peripheral address. - * @param pcs The particular peripheral chip select (parameter value is of type dspi_which_pcs_t) for which we wish to - * apply the active high or active low characteristic. - * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of - * type dspi_pcs_polarity_config_t. - */ -static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh); - -/*! - * @brief Master fill up the TX FIFO with data. - * This is not a public API. - */ -static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief Master finish up a transfer. - * It would call back if there is callback function and set the state to idle. - * This is not a public API. - */ -static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief Slave fill up the TX FIFO with data. - * This is not a public API. - */ -static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - * @brief Slave finish up a transfer. - * It would call back if there is callback function and set the state to idle. - * This is not a public API. - */ -static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - * @brief DSPI common interrupt handler. - * - * @param base DSPI peripheral address. - * @param handle pointer to g_dspiHandle which stores the transfer state. - */ -static void DSPI_CommonIRQHandler(SPI_Type *base, void *param); - -/*! - * @brief Master prepare the transfer. - * Basically it set up dspi_master_handle . - * This is not a public API. - */ -static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ -static const uint32_t s_baudratePrescaler[] = {2, 3, 5, 7}; -static const uint32_t s_baudrateScaler[] = {2, 4, 6, 8, 16, 32, 64, 128, - 256, 512, 1024, 2048, 4096, 8192, 16384, 32768}; - -static const uint32_t s_delayPrescaler[] = {1, 3, 5, 7}; -static const uint32_t s_delayScaler[] = {2, 4, 8, 16, 32, 64, 128, 256, - 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536}; - -/*! @brief Pointers to dspi bases for each instance. */ -static SPI_Type *const s_dspiBases[] = SPI_BASE_PTRS; - -/*! @brief Pointers to dspi IRQ number for each instance. */ -static IRQn_Type const s_dspiIRQ[] = SPI_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to dspi clocks for each instance. */ -static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to dspi handles for each instance. */ -static void *g_dspiHandle[ARRAY_SIZE(s_dspiBases)]; - -/*! @brief Pointer to master IRQ handler for each instance. */ -static dspi_master_isr_t s_dspiMasterIsr; - -/*! @brief Pointer to slave IRQ handler for each instance. */ -static dspi_slave_isr_t s_dspiSlaveIsr; - -/********************************************************************************************************************** -* Code -*********************************************************************************************************************/ -uint32_t DSPI_GetInstance(SPI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dspiBases); instance++) - { - if (s_dspiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dspiBases)); - - return instance; -} - -void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(masterConfig); - - uint32_t temp; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable DSPI clock */ - CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - DSPI_Enable(base, true); - DSPI_StopTransfer(base); - - DSPI_SetMasterSlaveMode(base, kDSPI_Master); - - temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | - SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); - - base->MCR = temp | SPI_MCR_CONT_SCKE(masterConfig->enableContinuousSCK) | - SPI_MCR_MTFE(masterConfig->enableModifiedTimingFormat) | - SPI_MCR_ROOE(masterConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(masterConfig->samplePoint) | - SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); - - DSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); - - if (0 == DSPI_MasterSetBaudRate(base, masterConfig->whichCtar, masterConfig->ctarConfig.baudRate, srcClock_Hz)) - { - assert(false); - } - - temp = base->CTAR[masterConfig->whichCtar] & - ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); - - base->CTAR[masterConfig->whichCtar] = - temp | SPI_CTAR_FMSZ(masterConfig->ctarConfig.bitsPerFrame - 1) | SPI_CTAR_CPOL(masterConfig->ctarConfig.cpol) | - SPI_CTAR_CPHA(masterConfig->ctarConfig.cpha) | SPI_CTAR_LSBFE(masterConfig->ctarConfig.direction); - - DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_PcsToSck, srcClock_Hz, - masterConfig->ctarConfig.pcsToSckDelayInNanoSec); - DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_LastSckToPcs, srcClock_Hz, - masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec); - DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz, - masterConfig->ctarConfig.betweenTransferDelayInNanoSec); - - DSPI_StartTransfer(base); -} - -void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig) -{ - assert(masterConfig); - - masterConfig->whichCtar = kDSPI_Ctar0; - masterConfig->ctarConfig.baudRate = 500000; - masterConfig->ctarConfig.bitsPerFrame = 8; - masterConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - masterConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - masterConfig->ctarConfig.direction = kDSPI_MsbFirst; - - masterConfig->ctarConfig.pcsToSckDelayInNanoSec = 1000; - masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec = 1000; - masterConfig->ctarConfig.betweenTransferDelayInNanoSec = 1000; - - masterConfig->whichPcs = kDSPI_Pcs0; - masterConfig->pcsActiveHighOrLow = kDSPI_PcsActiveLow; - - masterConfig->enableContinuousSCK = false; - masterConfig->enableRxFifoOverWrite = false; - masterConfig->enableModifiedTimingFormat = false; - masterConfig->samplePoint = kDSPI_SckToSin0Clock; -} - -void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - uint32_t temp = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* enable DSPI clock */ - CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - DSPI_Enable(base, true); - DSPI_StopTransfer(base); - - DSPI_SetMasterSlaveMode(base, kDSPI_Slave); - - temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | - SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); - - base->MCR = temp | SPI_MCR_CONT_SCKE(slaveConfig->enableContinuousSCK) | - SPI_MCR_MTFE(slaveConfig->enableModifiedTimingFormat) | - SPI_MCR_ROOE(slaveConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(slaveConfig->samplePoint) | - SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); - - DSPI_SetOnePcsPolarity(base, kDSPI_Pcs0, kDSPI_PcsActiveLow); - - temp = base->CTAR[slaveConfig->whichCtar] & - ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); - - base->CTAR[slaveConfig->whichCtar] = temp | SPI_CTAR_SLAVE_FMSZ(slaveConfig->ctarConfig.bitsPerFrame - 1) | - SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) | - SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha); - - DSPI_StartTransfer(base); -} - -void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - slaveConfig->whichCtar = kDSPI_Ctar0; - slaveConfig->ctarConfig.bitsPerFrame = 8; - slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - - slaveConfig->enableContinuousSCK = false; - slaveConfig->enableRxFifoOverWrite = false; - slaveConfig->enableModifiedTimingFormat = false; - slaveConfig->samplePoint = kDSPI_SckToSin0Clock; -} - -void DSPI_Deinit(SPI_Type *base) -{ - DSPI_StopTransfer(base); - DSPI_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* disable DSPI clock */ - CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh) -{ - uint32_t temp; - - temp = base->MCR; - - if (activeLowOrHigh == kDSPI_PcsActiveLow) - { - temp |= SPI_MCR_PCSIS(pcs); - } - else - { - temp &= ~SPI_MCR_PCSIS(pcs); - } - - base->MCR = temp; -} - -uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz) -{ - /* for master mode configuration, if slave mode detected, return 0*/ - if (!DSPI_IsMaster(base)) - { - return 0; - } - uint32_t temp; - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t dbr, bestDbr; - uint32_t realBaudrate, bestBaudrate; - uint32_t diff, min_diff; - uint32_t baudrate = baudRate_Bps; - - /* find combination of prescaler and scaler resulting in baudrate closest to the requested value */ - min_diff = 0xFFFFFFFFU; - bestPrescaler = 0; - bestScaler = 0; - bestDbr = 1; - bestBaudrate = 0; /* required to avoid compilation warning */ - - /* In all for loops, if min_diff = 0, the exit for loop*/ - for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) - { - for (scaler = 0; (scaler < 16) && min_diff; scaler++) - { - for (dbr = 1; (dbr < 3) && min_diff; dbr++) - { - realBaudrate = ((srcClock_Hz * dbr) / (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler]))); - - /* calculate the baud rate difference based on the conditional statement that states that the calculated - * baud rate must not exceed the desired baud rate. - */ - if (baudrate >= realBaudrate) - { - diff = baudrate - realBaudrate; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestBaudrate = realBaudrate; - bestDbr = dbr; - } - } - } - } - } - - /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ - temp = base->CTAR[whichCtar] & ~(SPI_CTAR_DBR_MASK | SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK); - - base->CTAR[whichCtar] = temp | ((bestDbr - 1) << SPI_CTAR_DBR_SHIFT) | (bestPrescaler << SPI_CTAR_PBR_SHIFT) | - (bestScaler << SPI_CTAR_BR_SHIFT); - - /* return the actual calculated baud rate */ - return bestBaudrate; -} - -void DSPI_MasterSetDelayScaler( - SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay) -{ - /* these settings are only relevant in master mode */ - if (DSPI_IsMaster(base)) - { - switch (whichDelay) - { - case kDSPI_PcsToSck: - base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PCSSCK_MASK) & (~SPI_CTAR_CSSCK_MASK)) | - SPI_CTAR_PCSSCK(prescaler) | SPI_CTAR_CSSCK(scaler); - break; - case kDSPI_LastSckToPcs: - base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PASC_MASK) & (~SPI_CTAR_ASC_MASK)) | - SPI_CTAR_PASC(prescaler) | SPI_CTAR_ASC(scaler); - break; - case kDSPI_BetweenTransfer: - base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PDT_MASK) & (~SPI_CTAR_DT_MASK)) | - SPI_CTAR_PDT(prescaler) | SPI_CTAR_DT(scaler); - break; - default: - break; - } - } -} - -uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - dspi_delay_type_t whichDelay, - uint32_t srcClock_Hz, - uint32_t delayTimeInNanoSec) -{ - /* for master mode configuration, if slave mode detected, return 0 */ - if (!DSPI_IsMaster(base)) - { - return 0; - } - - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t realDelay, bestDelay; - uint32_t diff, min_diff; - uint32_t initialDelayNanoSec; - - /* find combination of prescaler and scaler resulting in the delay closest to the - * requested value - */ - min_diff = 0xFFFFFFFFU; - /* Initialize prescaler and scaler to their max values to generate the max delay */ - bestPrescaler = 0x3; - bestScaler = 0xF; - bestDelay = (((1000000000U * 4) / srcClock_Hz) * s_delayPrescaler[bestPrescaler] * s_delayScaler[bestScaler]) / 4; - - /* First calculate the initial, default delay */ - initialDelayNanoSec = 1000000000U / srcClock_Hz * 2; - - /* If the initial, default delay is already greater than the desired delay, then - * set the delays to their initial value (0) and return the delay. In other words, - * there is no way to decrease the delay value further. - */ - if (initialDelayNanoSec >= delayTimeInNanoSec) - { - DSPI_MasterSetDelayScaler(base, whichCtar, 0, 0, whichDelay); - return initialDelayNanoSec; - } - - /* In all for loops, if min_diff = 0, the exit for loop */ - for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) - { - for (scaler = 0; (scaler < 16) && min_diff; scaler++) - { - realDelay = ((4000000000U / srcClock_Hz) * s_delayPrescaler[prescaler] * s_delayScaler[scaler]) / 4; - - /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the desired delay - */ - if (realDelay >= delayTimeInNanoSec) - { - diff = realDelay - delayTimeInNanoSec; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestDelay = realDelay; - } - } - } - } - - /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ - DSPI_MasterSetDelayScaler(base, whichCtar, bestPrescaler, bestScaler, whichDelay); - - /* return the actual calculated baud rate */ - return bestDelay; -} - -void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command) -{ - assert(command); - - command->isPcsContinuous = false; - command->whichCtar = kDSPI_Ctar0; - command->whichPcs = kDSPI_Pcs0; - command->isEndOfQueue = false; - command->clearTransferCount = false; -} - -void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) -{ - assert(command); - - /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); - - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } - - base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | - SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | - SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - /* Wait till TCF sets */ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) - { - } -} - -void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data) -{ - /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); - - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } - - base->PUSHR = data; - - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - /* Wait till TCF sets */ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) - { - } -} - -void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data) -{ - /* First, clear Transmit Complete Flag (TCF) */ - DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); - - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } - - base->PUSHR_SLAVE = data; - - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - /* Wait till TCF sets */ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) - { - } -} - -void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask) -{ - if (mask & SPI_RSER_TFFF_RE_MASK) - { - base->RSER &= ~SPI_RSER_TFFF_DIRS_MASK; - } - if (mask & SPI_RSER_RFDF_RE_MASK) - { - base->RSER &= ~SPI_RSER_RFDF_DIRS_MASK; - } - base->RSER |= mask; -} - -/*Transactional APIs -- Master*/ - -void DSPI_MasterTransferCreateHandle(SPI_Type *base, - dspi_master_handle_t *handle, - dspi_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - g_dspiHandle[DSPI_GetInstance(base)] = handle; - - handle->callback = callback; - handle->userData = userData; -} - -status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer) -{ - assert(transfer); - - uint16_t wordToSend = 0; - uint16_t wordReceived = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; - uint8_t bitsPerFrame; - - uint32_t command; - uint32_t lastCommand; - - uint8_t *txData; - uint8_t *rxData; - uint32_t remainingSendByteCount; - uint32_t remainingReceiveByteCount; - - uint32_t fifoSize; - dspi_command_data_config_t commandStruct; - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0) - { - return kStatus_InvalidArgument; - } - - DSPI_StopTransfer(base); - DSPI_DisableInterrupts(base, kDSPI_AllInterruptEnable); - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); - - /*Calculate the command and lastCommand*/ - commandStruct.whichPcs = - (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); - commandStruct.isEndOfQueue = false; - commandStruct.clearTransferCount = false; - commandStruct.whichCtar = - (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); - commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); - - command = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - commandStruct.isEndOfQueue = true; - commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); - lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - /*Calculate the bitsPerFrame*/ - bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; - - txData = transfer->txData; - rxData = transfer->rxData; - remainingSendByteCount = transfer->dataSize; - remainingReceiveByteCount = transfer->dataSize; - - if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) - { - fifoSize = 1; - } - else - { - fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); - } - - DSPI_StartTransfer(base); - - if (bitsPerFrame <= 8) - { - while (remainingSendByteCount > 0) - { - if (remainingSendByteCount == 1) - { - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } - - if (txData != NULL) - { - base->PUSHR = (*txData) | (lastCommand); - txData++; - } - else - { - base->PUSHR = (lastCommand) | (dummyData); - } - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - remainingSendByteCount--; - - while (remainingReceiveByteCount > 0) - { - if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) - { - if (rxData != NULL) - { - /* Read data from POPR*/ - *(rxData) = DSPI_ReadData(base); - rxData++; - } - else - { - DSPI_ReadData(base); - } - remainingReceiveByteCount--; - - DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); - } - } - } - else - { - /*Wait until Tx Fifo is not full*/ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } - if (txData != NULL) - { - base->PUSHR = command | (uint16_t)(*txData); - txData++; - } - else - { - base->PUSHR = command | dummyData; - } - remainingSendByteCount--; - - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize) - { - if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) - { - if (rxData != NULL) - { - *(rxData) = DSPI_ReadData(base); - rxData++; - } - else - { - DSPI_ReadData(base); - } - remainingReceiveByteCount--; - - DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); - } - } - } - } - } - else - { - while (remainingSendByteCount > 0) - { - if (remainingSendByteCount <= 2) - { - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } - - if (txData != NULL) - { - wordToSend = *(txData); - ++txData; - - if (remainingSendByteCount > 1) - { - wordToSend |= (unsigned)(*(txData)) << 8U; - ++txData; - } - } - else - { - wordToSend = dummyData; - } - - base->PUSHR = lastCommand | wordToSend; - - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - remainingSendByteCount = 0; - - while (remainingReceiveByteCount > 0) - { - if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) - { - wordReceived = DSPI_ReadData(base); - - if (remainingReceiveByteCount != 1) - { - if (rxData != NULL) - { - *(rxData) = wordReceived; - ++rxData; - *(rxData) = wordReceived >> 8; - ++rxData; - } - remainingReceiveByteCount -= 2; - } - else - { - if (rxData != NULL) - { - *(rxData) = wordReceived; - ++rxData; - } - remainingReceiveByteCount--; - } - DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); - } - } - } - else - { - /*Wait until Tx Fifo is not full*/ - while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } - - if (txData != NULL) - { - wordToSend = *(txData); - ++txData; - wordToSend |= (unsigned)(*(txData)) << 8U; - ++txData; - } - else - { - wordToSend = dummyData; - } - base->PUSHR = command | wordToSend; - remainingSendByteCount -= 2; - - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize) - { - if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) - { - wordReceived = DSPI_ReadData(base); - - if (rxData != NULL) - { - *rxData = wordReceived; - ++rxData; - *rxData = wordReceived >> 8; - ++rxData; - } - remainingReceiveByteCount -= 2; - - DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); - } - } - } - } - } - - return kStatus_Success; -} - -static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - dspi_command_data_config_t commandStruct; - - DSPI_StopTransfer(base); - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); - - commandStruct.whichPcs = - (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); - commandStruct.isEndOfQueue = false; - commandStruct.clearTransferCount = false; - commandStruct.whichCtar = - (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); - commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); - handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - commandStruct.isEndOfQueue = true; - commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); - handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; - - if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) - { - handle->fifoSize = 1; - } - else - { - handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); - } - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; -} - -status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - - handle->state = kDSPI_Busy; - - DSPI_MasterTransferPrepare(base, handle, transfer); - DSPI_StartTransfer(base); - - /* Enable the NVIC for DSPI peripheral. */ - EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); - - DSPI_MasterTransferFillUpTxFifo(base, handle); - - /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt - * Since SPI is a synchronous interface, we only need to enable the RX interrupt. - * The IRQ handler will get the status of RX and TX interrupt flags. - */ - s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ; - - DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); - - return kStatus_Success; -} - -status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->remainingReceiveByteCount; - return kStatus_Success; -} - -static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests*/ - DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); - - status_t status = 0; - if (handle->state == kDSPI_Error) - { - status = kStatus_DSPI_Error; - } - else - { - status = kStatus_Success; - } - - handle->state = kDSPI_Idle; - - if (handle->callback) - { - handle->callback(base, handle, status, handle->userData); - } -} - -static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(handle); - - uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; - - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8) - { - /* Fill the fifo until it is full or until the send word count is 0 or until the difference - * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. - * The reason for checking the difference is to ensure we only send as much as the - * RX FIFO can receive. - * For this case where bitsPerFrame > 8, each entry in the FIFO contains 2 bytes of the - * send data, hence the difference between the remainingReceiveByteCount and - * remainingSendByteCount must be divided by 2 to convert this difference into a - * 16-bit (2 byte) value. - */ - while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && - ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) / 2 < handle->fifoSize)) - { - if (handle->remainingSendByteCount <= 2) - { - if (handle->txData) - { - if (handle->remainingSendByteCount == 1) - { - wordToSend = *(handle->txData); - } - else - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - } - } - else - { - wordToSend = dummyData; - } - handle->remainingSendByteCount = 0; - base->PUSHR = handle->lastCommand | wordToSend; - } - /* For all words except the last word */ - else - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - ++handle->txData; /* increment to next data byte */ - } - else - { - wordToSend = dummyData; - } - handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ - base->PUSHR = handle->command | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - /* exit loop if send count is zero, else update local variables for next loop */ - if (handle->remainingSendByteCount == 0) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - /* Optimized for bits/frame less than or equal to one byte. */ - else - { - /* Fill the fifo until it is full or until the send word count is 0 or until the difference - * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. - * The reason for checking the difference is to ensure we only send as much as the - * RX FIFO can receive. - */ - while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && - ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) < handle->fifoSize)) - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - } - else - { - wordToSend = dummyData; - } - - if (handle->remainingSendByteCount == 1) - { - base->PUSHR = handle->lastCommand | wordToSend; - } - else - { - base->PUSHR = handle->command | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - --handle->remainingSendByteCount; - - /* exit loop if send count is zero, else update local variables for next loop */ - if (handle->remainingSendByteCount == 0) - { - break; - } - } - } -} - -void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(handle); - - DSPI_StopTransfer(base); - - /* Disable interrupt requests*/ - DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); - - handle->state = kDSPI_Idle; -} - -void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) -{ - assert(handle); - - /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */ - if (handle->remainingReceiveByteCount) - { - /* Check read buffer.*/ - uint16_t wordReceived; /* Maximum supported data bit length in master mode is 16-bits */ - - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8) - { - while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) - { - wordReceived = DSPI_ReadData(base); - /* clear the rx fifo drain request, needed for non-DMA applications as this flag - * will remain set even if the rx fifo is empty. By manually clearing this flag, it - * either remain clear if no more data is in the fifo, or it will set if there is - * more data in the fifo. - */ - DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); - - /* Store read bytes into rx buffer only if a buffer pointer was provided */ - if (handle->rxData) - { - /* For the last word received, if there is an extra byte due to the odd transfer - * byte count, only save the last byte and discard the upper byte - */ - if (handle->remainingReceiveByteCount == 1) - { - *handle->rxData = wordReceived; /* Write first data byte */ - --handle->remainingReceiveByteCount; - } - else - { - *handle->rxData = wordReceived; /* Write first data byte */ - ++handle->rxData; /* increment to next data byte */ - *handle->rxData = wordReceived >> 8; /* Write second data byte */ - ++handle->rxData; /* increment to next data byte */ - handle->remainingReceiveByteCount -= 2; - } - } - else - { - if (handle->remainingReceiveByteCount == 1) - { - --handle->remainingReceiveByteCount; - } - else - { - handle->remainingReceiveByteCount -= 2; - } - } - if (handle->remainingReceiveByteCount == 0) - { - break; - } - } /* End of RX FIFO drain while loop */ - } - /* Optimized for bits/frame less than or equal to one byte. */ - else - { - while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) - { - wordReceived = DSPI_ReadData(base); - /* clear the rx fifo drain request, needed for non-DMA applications as this flag - * will remain set even if the rx fifo is empty. By manually clearing this flag, it - * either remain clear if no more data is in the fifo, or it will set if there is - * more data in the fifo. - */ - DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); - - /* Store read bytes into rx buffer only if a buffer pointer was provided */ - if (handle->rxData) - { - *handle->rxData = wordReceived; - ++handle->rxData; - } - - --handle->remainingReceiveByteCount; - - if (handle->remainingReceiveByteCount == 0) - { - break; - } - } /* End of RX FIFO drain while loop */ - } - } - - /* Check write buffer. We always have to send a word in order to keep the transfer - * moving. So if the caller didn't provide a send buffer, we just send a zero. - */ - if (handle->remainingSendByteCount) - { - DSPI_MasterTransferFillUpTxFifo(base, handle); - } - - /* Check if we're done with this transfer.*/ - if ((handle->remainingSendByteCount == 0) && (handle->remainingReceiveByteCount == 0)) - { - /* Complete the transfer and disable the interrupts */ - DSPI_MasterTransferComplete(base, handle); - } -} - -/*Transactional APIs -- Slave*/ -void DSPI_SlaveTransferCreateHandle(SPI_Type *base, - dspi_slave_handle_t *handle, - dspi_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - g_dspiHandle[DSPI_GetInstance(base)] = handle; - - handle->callback = callback; - handle->userData = userData; -} - -status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - /* If receive length is zero */ - if (transfer->dataSize == 0) - { - return kStatus_InvalidArgument; - } - - /* If both send buffer and receive buffer is null */ - if ((!(transfer->txData)) && (!(transfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - handle->state = kDSPI_Busy; - - /* Enable the NVIC for DSPI peripheral. */ - EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); - - /* Store transfer information */ - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->errorCount = 0; - - uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; - handle->bitsPerFrame = - (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; - - DSPI_StopTransfer(base); - - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); - - DSPI_StartTransfer(base); - - /* Prepare data to transmit */ - DSPI_SlaveTransferFillUpTxFifo(base, handle); - - s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ; - - /* Enable RX FIFO drain request, the slave only use this interrupt */ - DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); - - if (handle->rxData) - { - /* RX FIFO overflow request enable */ - DSPI_EnableInterrupts(base, kDSPI_RxFifoOverflowInterruptEnable); - } - if (handle->txData) - { - /* TX FIFO underflow request enable */ - DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable); - } - - return kStatus_Success; -} - -status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - *count = handle->totalByteCount - handle->remainingReceiveByteCount; - return kStatus_Success; -} - -static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(handle); - - uint16_t transmitData = 0; - uint8_t dummyPattern = DSPI_DUMMY_DATA; - - /* Service the transmitter, if transmit buffer provided, transmit the data, - * else transmit dummy pattern - */ - while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) - { - /* Transmit data */ - if (handle->remainingSendByteCount > 0) - { - /* Have data to transmit, update the transmit data and push to FIFO */ - if (handle->bitsPerFrame <= 8) - { - /* bits/frame is 1 byte */ - if (handle->txData) - { - /* Update transmit data and transmit pointer */ - transmitData = *handle->txData; - handle->txData++; - } - else - { - transmitData = dummyPattern; - } - - /* Decrease remaining dataSize */ - --handle->remainingSendByteCount; - } - /* bits/frame is 2 bytes */ - else - { - /* With multibytes per frame transmission, the transmit frame contains data from - * transmit buffer until sent dataSize matches user request. Other bytes will set to - * dummy pattern value. - */ - if (handle->txData) - { - /* Update first byte of transmit data and transmit pointer */ - transmitData = *handle->txData; - handle->txData++; - - if (handle->remainingSendByteCount == 1) - { - /* Decrease remaining dataSize */ - --handle->remainingSendByteCount; - /* Update second byte of transmit data to second byte of dummy pattern */ - transmitData = transmitData | (uint16_t)(((uint16_t)dummyPattern) << 8); - } - else - { - /* Update second byte of transmit data and transmit pointer */ - transmitData = transmitData | (uint16_t)((uint16_t)(*handle->txData) << 8); - handle->txData++; - handle->remainingSendByteCount -= 2; - } - } - else - { - if (handle->remainingSendByteCount == 1) - { - --handle->remainingSendByteCount; - } - else - { - handle->remainingSendByteCount -= 2; - } - transmitData = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; - } - } - } - else - { - break; - } - - /* Write the data to the DSPI data register */ - base->PUSHR_SLAVE = transmitData; - - /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - } -} - -static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests */ - DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | - kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); - - /* The transfer is complete. */ - handle->txData = NULL; - handle->rxData = NULL; - handle->remainingReceiveByteCount = 0; - handle->remainingSendByteCount = 0; - - status_t status = 0; - if (handle->state == kDSPI_Error) - { - status = kStatus_DSPI_Error; - } - else - { - status = kStatus_Success; - } - - handle->state = kDSPI_Idle; - - if (handle->callback) - { - handle->callback(base, handle, status, handle->userData); - } -} - -void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(handle); - - DSPI_StopTransfer(base); - - /* Disable interrupt requests */ - DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | - kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); - - handle->state = kDSPI_Idle; - handle->remainingSendByteCount = 0; - handle->remainingReceiveByteCount = 0; -} - -void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) -{ - assert(handle); - - uint8_t dummyPattern = DSPI_DUMMY_DATA; - uint32_t dataReceived; - uint32_t dataSend = 0; - - /* Because SPI protocol is synchronous, the number of bytes that that slave received from the - * master is the actual number of bytes that the slave transmitted to the master. So we only - * monitor the received dataSize to know when the transfer is complete. - */ - if (handle->remainingReceiveByteCount > 0) - { - while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) - { - /* Have received data in the buffer. */ - dataReceived = base->POPR; - /*Clear the rx fifo drain request, needed for non-DMA applications as this flag - * will remain set even if the rx fifo is empty. By manually clearing this flag, it - * either remain clear if no more data is in the fifo, or it will set if there is - * more data in the fifo. - */ - DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); - - /* If bits/frame is one byte */ - if (handle->bitsPerFrame <= 8) - { - if (handle->rxData) - { - /* Receive buffer is not null, store data into it */ - *handle->rxData = dataReceived; - ++handle->rxData; - } - /* Descrease remaining receive byte count */ - --handle->remainingReceiveByteCount; - - if (handle->remainingSendByteCount > 0) - { - if (handle->txData) - { - dataSend = *handle->txData; - ++handle->txData; - } - else - { - dataSend = dummyPattern; - } - - --handle->remainingSendByteCount; - /* Write the data to the DSPI data register */ - base->PUSHR_SLAVE = dataSend; - } - } - else /* If bits/frame is 2 bytes */ - { - /* With multibytes frame receiving, we only receive till the received dataSize - * matches user request. Other bytes will be ignored. - */ - if (handle->rxData) - { - /* Receive buffer is not null, store first byte into it */ - *handle->rxData = dataReceived; - ++handle->rxData; - - if (handle->remainingReceiveByteCount == 1) - { - /* Decrease remaining receive byte count */ - --handle->remainingReceiveByteCount; - } - else - { - /* Receive buffer is not null, store second byte into it */ - *handle->rxData = dataReceived >> 8; - ++handle->rxData; - handle->remainingReceiveByteCount -= 2; - } - } - /* If no handle->rxData*/ - else - { - if (handle->remainingReceiveByteCount == 1) - { - /* Decrease remaining receive byte count */ - --handle->remainingReceiveByteCount; - } - else - { - handle->remainingReceiveByteCount -= 2; - } - } - - if (handle->remainingSendByteCount > 0) - { - if (handle->txData) - { - dataSend = *handle->txData; - ++handle->txData; - - if (handle->remainingSendByteCount == 1) - { - --handle->remainingSendByteCount; - dataSend |= (uint16_t)((uint16_t)(dummyPattern) << 8); - } - else - { - dataSend |= (uint32_t)(*handle->txData) << 8; - ++handle->txData; - handle->remainingSendByteCount -= 2; - } - } - /* If no handle->txData*/ - else - { - if (handle->remainingSendByteCount == 1) - { - --handle->remainingSendByteCount; - } - else - { - handle->remainingSendByteCount -= 2; - } - dataSend = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; - } - /* Write the data to the DSPI data register */ - base->PUSHR_SLAVE = dataSend; - } - } - /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - if (handle->remainingReceiveByteCount == 0) - { - break; - } - } - } - /* Check if remaining receive byte count matches user request */ - if ((handle->remainingReceiveByteCount == 0) || (handle->state == kDSPI_Error)) - { - /* Other cases, stop the transfer. */ - DSPI_SlaveTransferComplete(base, handle); - return; - } - - /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ - if ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoUnderflowFlag) && (base->RSER & SPI_RSER_TFUF_RE_MASK)) - { - DSPI_ClearStatusFlags(base, kDSPI_TxFifoUnderflowFlag); - /* Change state to error and clear flag */ - if (handle->txData) - { - handle->state = kDSPI_Error; - } - handle->errorCount++; - } - /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ - if ((DSPI_GetStatusFlags(base) & kDSPI_RxFifoOverflowFlag) && (base->RSER & SPI_RSER_RFOF_RE_MASK)) - { - DSPI_ClearStatusFlags(base, kDSPI_RxFifoOverflowFlag); - /* Change state to error and clear flag */ - if (handle->txData) - { - handle->state = kDSPI_Error; - } - handle->errorCount++; - } -} - -static void DSPI_CommonIRQHandler(SPI_Type *base, void *param) -{ - if (DSPI_IsMaster(base)) - { - s_dspiMasterIsr(base, (dspi_master_handle_t *)param); - } - else - { - s_dspiSlaveIsr(base, (dspi_slave_handle_t *)param); - } -} - -#if defined(SPI0) -void SPI0_DriverIRQHandler(void) -{ - assert(g_dspiHandle[0]); - DSPI_CommonIRQHandler(SPI0, g_dspiHandle[0]); -} -#endif - -#if defined(SPI1) -void SPI1_DriverIRQHandler(void) -{ - assert(g_dspiHandle[1]); - DSPI_CommonIRQHandler(SPI1, g_dspiHandle[1]); -} -#endif - -#if defined(SPI2) -void SPI2_DriverIRQHandler(void) -{ - assert(g_dspiHandle[2]); - DSPI_CommonIRQHandler(SPI2, g_dspiHandle[2]); -} -#endif - -#if defined(SPI3) -void SPI3_DriverIRQHandler(void) -{ - assert(g_dspiHandle[3]); - DSPI_CommonIRQHandler(SPI3, g_dspiHandle[3]); -} -#endif - -#if defined(SPI4) -void SPI4_DriverIRQHandler(void) -{ - assert(g_dspiHandle[4]); - DSPI_CommonIRQHandler(SPI4, g_dspiHandle[4]); -} -#endif - -#if defined(SPI5) -void SPI5_DriverIRQHandler(void) -{ - assert(g_dspiHandle[5]); - DSPI_CommonIRQHandler(SPI5, g_dspiHandle[5]); -} -#endif - -#if (FSL_FEATURE_SOC_DSPI_COUNT > 6) -#error "Should write the SPIx_DriverIRQHandler function that instance greater than 5 !" -#endif diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dspi.h b/third_party/nxp/MKW41Z4/drivers/fsl_dspi.h deleted file mode 100644 index 5dd96afcb..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dspi.h +++ /dev/null @@ -1,1180 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_DSPI_H_ -#define _FSL_DSPI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dspi_driver - * @{ - */ - - -/********************************************************************************************************************** - * Definitions - *********************************************************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DSPI driver version 2.1.4. */ -#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) -/*@}*/ - -#ifndef DSPI_DUMMY_DATA -/*! @brief DSPI dummy data if there is no Tx data.*/ -#define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */ -#endif - -/*! @brief Status for the DSPI driver.*/ -enum _dspi_status -{ - kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/ - kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */ - kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/ - kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */ -}; - -/*! @brief DSPI status flags in SPIx_SR register.*/ -enum _dspi_flags -{ - kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ - kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/ - kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/ - kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/ - kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/ - kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/ - kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/ - kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | - SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All statuses above.*/ -}; - -/*! @brief DSPI interrupt source.*/ -enum _dspi_interrupt_enable -{ - kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ - kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/ - kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/ - kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/ - kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/ - kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/ - kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | - SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK - /*!< All above interrupts enable.*/ -}; - -/*! @brief DSPI DMA source.*/ -enum _dspi_dma_enable -{ - kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests. - No Tx interrupt request. */ - kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests. - No Rx interrupt request. */ -}; - -/*! @brief DSPI master or slave mode configuration.*/ -typedef enum _dspi_master_slave_mode -{ - kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/ - kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/ -} dspi_master_slave_mode_t; - -/*! - * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is valid - * only when the CPHA bit in the CTAR register is 0. - */ -typedef enum _dspi_master_sample_point -{ - kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/ - kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/ - kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/ -} dspi_master_sample_point_t; - -/*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/ -typedef enum _dspi_which_pcs_config -{ - kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */ - kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */ - kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */ - kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */ - kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */ - kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */ -} dspi_which_pcs_t; - -/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/ -typedef enum _dspi_pcs_polarity_config -{ - kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */ - kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */ -} dspi_pcs_polarity_config_t; - -/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/ -enum _dspi_pcs_polarity -{ - kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ - kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ - kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ - kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ - kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */ - kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */ - kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ -}; - -/*! @brief DSPI clock polarity configuration for a given CTAR.*/ -typedef enum _dspi_clock_polarity -{ - kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/ - kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/ -} dspi_clock_polarity_t; - -/*! @brief DSPI clock phase configuration for a given CTAR.*/ -typedef enum _dspi_clock_phase -{ - kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the - following edge.*/ - kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the - following edge.*/ -} dspi_clock_phase_t; - -/*! @brief DSPI data shifter direction options for a given CTAR.*/ -typedef enum _dspi_shift_direction -{ - kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ - kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. - Shifting out of LSB is not supported for slave */ -} dspi_shift_direction_t; - -/*! @brief DSPI delay type selection.*/ -typedef enum _dspi_delay_type -{ - kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */ - kDSPI_LastSckToPcs, /*!< The last SCK edge to Pcs delay. */ - kDSPI_BetweenTransfer /*!< Delay between transfers. */ -} dspi_delay_type_t; - -/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/ -typedef enum _dspi_ctar_selection -{ - kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the - same register address. */ - kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */ - kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */ - kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */ - kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */ - kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */ - kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */ - kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */ -} dspi_ctar_selection_t; - -#define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro; used internally. */ -#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */ -#define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro; used internally. */ -#define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro; used internally. */ -/*! @brief Use this enumeration for the DSPI master transfer configFlags. */ -enum _dspi_transfer_config_flag_for_master -{ - kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */ - kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */ - kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */ - kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */ - kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */ - kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */ - kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */ - kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */ - - kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */ - kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */ - kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/ - kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */ - kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */ - kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */ - - kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */ - kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ -}; - -#define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */ -#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */ -/*! @brief Use this enumeration for the DSPI slave transfer configFlags. */ -enum _dspi_transfer_config_flag_for_slave -{ - kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */ - /*!< DSPI slave can only use PCS0. */ -}; - -/*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */ -enum _dspi_transfer_state -{ - kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ - kDSPI_Busy, /*!< Transfer queue is not finished. */ - kDSPI_Error /*!< Transfer error. */ -}; - -/*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/ -typedef struct _dspi_command_data_config -{ - bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/ - dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes - Register (CTAR) to use for CTAS.*/ - dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/ - bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/ - bool clearTransferCount; /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/ -} dspi_command_data_config_t; - -/*! @brief DSPI master ctar configuration structure.*/ -typedef struct _dspi_master_ctar_config -{ - uint32_t baudRate; /*!< Baud Rate for DSPI. */ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ - dspi_clock_polarity_t cpol; /*!< Clock polarity. */ - dspi_clock_phase_t cpha; /*!< Clock phase. */ - dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ - - uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum - delay. It also sets the boundary value if out of range.*/ - uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the - minimum delay. It also sets the boundary value if out of range.*/ - - uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum - delay. It also sets the boundary value if out of range.*/ -} dspi_master_ctar_config_t; - -/*! @brief DSPI master configuration structure.*/ -typedef struct _dspi_master_config -{ - dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ - dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ - - dspi_which_pcs_t whichPcs; /*!< The desired Peripheral Chip Select (pcs). */ - dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */ - - bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only - supported for CPHA = 1.*/ - bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming - data is ignored and the data from the transfer that generated the overflow - is also ignored. If ROOE = 1, the incoming data is shifted to the - shift register. */ - - bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ - dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer - Format. It's valid only when CPHA=0. */ -} dspi_master_config_t; - -/*! @brief DSPI slave ctar configuration structure.*/ -typedef struct _dspi_slave_ctar_config -{ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ - dspi_clock_polarity_t cpol; /*!< Clock polarity. */ - dspi_clock_phase_t cpha; /*!< Clock phase. */ - /*!< Slave only supports MSB and does not support LSB.*/ -} dspi_slave_ctar_config_t; - -/*! @brief DSPI slave configuration structure.*/ -typedef struct _dspi_slave_config -{ - dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ - dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ - - bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only - supported for CPHA = 1.*/ - bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming - data is ignored and the data from the transfer that generated the overflow - is also ignored. If ROOE = 1, the incoming data is shifted to the - shift register. */ - bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ - dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer - Format. It's valid only when CPHA=0. */ -} dspi_slave_config_t; - -/*! -* @brief Forward declaration of the _dspi_master_handle typedefs. -*/ -typedef struct _dspi_master_handle dspi_master_handle_t; - -/*! -* @brief Forward declaration of the _dspi_slave_handle typedefs. -*/ -typedef struct _dspi_slave_handle dspi_slave_handle_t; - -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral address. - * @param handle Pointer to the handle for the DSPI master. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base, - dspi_master_handle_t *handle, - status_t status, - void *userData); -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral address. - * @param handle Pointer to the handle for the DSPI slave. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base, - dspi_slave_handle_t *handle, - status_t status, - void *userData); - -/*! @brief DSPI master/slave transfer structure.*/ -typedef struct _dspi_transfer -{ - uint8_t *txData; /*!< Send buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - volatile size_t dataSize; /*!< Transfer bytes. */ - - uint32_t - configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if the - transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer - is used for slave.*/ -} dspi_transfer_t; - -/*! @brief DSPI master transfer handle structure used for transactional API. */ -struct _dspi_master_handle -{ - uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ - volatile uint32_t command; /*!< The desired data command. */ - volatile uint32_t lastCommand; /*!< The desired last data command. */ - - uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile bool isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ - volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ - volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ - size_t totalByteCount; /*!< A number of transfer bytes*/ - - volatile uint8_t state; /*!< DSPI transfer state, see _dspi_transfer_state.*/ - - dspi_master_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/*! @brief DSPI slave transfer handle structure used for the transactional API. */ -struct _dspi_slave_handle -{ - uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ - volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ - volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ - size_t totalByteCount; /*!< A number of transfer bytes*/ - - volatile uint8_t state; /*!< DSPI transfer state.*/ - - volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ - - dspi_slave_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/********************************************************************************************************************** - * API - *********************************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the DSPI master. - * - * This function initializes the DSPI master configuration. This is an example use case. - * @code - * dspi_master_config_t masterConfig; - * masterConfig.whichCtar = kDSPI_Ctar0; - * masterConfig.ctarConfig.baudRate = 500000000U; - * masterConfig.ctarConfig.bitsPerFrame = 8; - * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; - * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; - * masterConfig.whichPcs = kDSPI_Pcs0; - * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; - * masterConfig.enableContinuousSCK = false; - * masterConfig.enableRxFifoOverWrite = false; - * masterConfig.enableModifiedTimingFormat = false; - * masterConfig.samplePoint = kDSPI_SckToSin0Clock; - * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); - * @endcode - * - * @param base DSPI peripheral address. - * @param masterConfig Pointer to the structure dspi_master_config_t. - * @param srcClock_Hz Module source input clock in Hertz. - */ -void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Sets the dspi_master_config_t structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). - * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure - * before calling the DSPI_MasterInit(). - * Example: - * @code - * dspi_master_config_t masterConfig; - * DSPI_MasterGetDefaultConfig(&masterConfig); - * @endcode - * @param masterConfig pointer to dspi_master_config_t structure - */ -void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig); - -/*! - * @brief DSPI slave configuration. - * - * This function initializes the DSPI slave configuration. This is an example use case. - * @code - * dspi_slave_config_t slaveConfig; - * slaveConfig->whichCtar = kDSPI_Ctar0; - * slaveConfig->ctarConfig.bitsPerFrame = 8; - * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; - * slaveConfig->enableContinuousSCK = false; - * slaveConfig->enableRxFifoOverWrite = false; - * slaveConfig->enableModifiedTimingFormat = false; - * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; - * DSPI_SlaveInit(base, &slaveConfig); - * @endcode - * - * @param base DSPI peripheral address. - * @param slaveConfig Pointer to the structure dspi_master_config_t. - */ -void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig); - -/*! - * @brief Sets the dspi_slave_config_t structure to a default value. - * - * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). - * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure - * before calling the DSPI_SlaveInit(). - * This is an example. - * @code - * dspi_slave_config_t slaveConfig; - * DSPI_SlaveGetDefaultConfig(&slaveConfig); - * @endcode - * @param slaveConfig Pointer to the dspi_slave_config_t structure. - */ -void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig); - -/*! - * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. - * @param base DSPI peripheral address. - */ -void DSPI_Deinit(SPI_Type *base); - -/*! - * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. - * - * @param base DSPI peripheral address. - * @param enable Pass true to enable module, false to disable module. - */ -static inline void DSPI_Enable(SPI_Type *base, bool enable) -{ - if (enable) - { - base->MCR &= ~SPI_MCR_MDIS_MASK; - } - else - { - base->MCR |= SPI_MCR_MDIS_MASK; - } -} - -/*! - *@} -*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the DSPI status flag state. - * @param base DSPI peripheral address. - * @return DSPI status (in SR register). - */ -static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base) -{ - return (base->SR); -} - -/*! - * @brief Clears the DSPI status flag. - * - * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the - * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The - * function uses these bit positions in its algorithm to clear the desired flag state. - * This is an example. - * @code - * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag); - * @endcode - * - * @param base DSPI peripheral address. - * @param statusFlags The status flag used from the type dspi_flags. - */ -static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags) -{ - base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ -} - -/*! - *@} -*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the DSPI interrupts. - * - * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask. - * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. - * - * @code - * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. - */ -void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask); - -/*! - * @brief Disables the DSPI interrupts. - * - * @code - * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. - */ -static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask) -{ - base->RSER &= ~mask; -} - -/*! - *@} -*/ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the DSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. - * @code - * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum dspi_dma_enable. - */ -static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask) -{ - base->RSER |= mask; -} - -/*! - * @brief Disables the DSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. - * @code - * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); - * @endcode - * - * @param base DSPI peripheral address. - * @param mask The interrupt mask; use the enum dspi_dma_enable. - */ -static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask) -{ - base->RSER &= ~mask; -} - -/*! - * @brief Gets the DSPI master PUSHR data register address for the DMA operation. - * - * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation. - * - * @param base DSPI peripheral address. - * @return The DSPI master PUSHR data register address. - */ -static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base) -{ - return (uint32_t) & (base->PUSHR); -} - -/*! - * @brief Gets the DSPI slave PUSHR data register address for the DMA operation. - * - * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation. - * - * @param base DSPI peripheral address. - * @return The DSPI slave PUSHR data register address. - */ -static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base) -{ - return (uint32_t) & (base->PUSHR_SLAVE); -} - -/*! - * @brief Gets the DSPI POPR data register address for the DMA operation. - * - * This function gets the DSPI POPR data register address as this value is needed for the DMA operation. - * - * @param base DSPI peripheral address. - * @return The DSPI POPR data register address. - */ -static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base) -{ - return (uint32_t) & (base->POPR); -} - -/*! - *@} -*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Configures the DSPI for master or slave. - * - * @param base DSPI peripheral address. - * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t. - */ -static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode) -{ - base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode); -} - -/*! - * @brief Returns whether the DSPI module is in master mode. - * - * @param base DSPI peripheral address. - * @return Returns true if the module is in master mode or false if the module is in slave mode. - */ -static inline bool DSPI_IsMaster(SPI_Type *base) -{ - return (bool)((base->MCR) & SPI_MCR_MSTR_MASK); -} -/*! - * @brief Starts the DSPI transfers and clears HALT bit in MCR. - * - * This function sets the module to start data transfer in either master or slave mode. - * - * @param base DSPI peripheral address. - */ -static inline void DSPI_StartTransfer(SPI_Type *base) -{ - base->MCR &= ~SPI_MCR_HALT_MASK; -} -/*! - * @brief Stops DSPI transfers and sets the HALT bit in MCR. - * - * This function stops data transfers in either master or slave modes. - * - * @param base DSPI peripheral address. - */ -static inline void DSPI_StopTransfer(SPI_Type *base) -{ - base->MCR |= SPI_MCR_HALT_MASK; -} - -/*! - * @brief Enables or disables the DSPI FIFOs. - * - * This function allows the caller to disable/enable the Tx and Rx FIFOs independently. - * Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration. To enable, - * pass in a logic 1 (true). - * - * @param base DSPI peripheral address. - * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO - * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO - */ -static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo) -{ - base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) | - SPI_MCR_DIS_RXF(!enableRxFifo); -} - -/*! - * @brief Flushes the DSPI FIFOs. - * - * @param base DSPI peripheral address. - * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO - * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO - */ -static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo) -{ - base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) | - SPI_MCR_CLR_RXF(flushRxFifo); -} - -/*! - * @brief Configures the DSPI peripheral chip select polarity simultaneously. - * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of - * PCSs is specific to the device. - * @code - * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow); - @endcode - * @param base DSPI peripheral address. - * @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity. - */ -static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask) -{ - base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask); -} - -/*! - * @brief Sets the DSPI baud rate in bits per second. - * - * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without - * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the - * caller also provide the frequency of the module source clock (in Hertz). - * - * @param base DSPI peripheral address. - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t - * @param baudRate_Bps The desired baud rate in bits per second - * @param srcClock_Hz Module source input clock in Hertz - * @return The actual calculated baud rate - */ -uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz); - -/*! - * @brief Manually configures the delay prescaler and scaler for a particular CTAR. - * - * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar - * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT). - * - * These delay names are available in the type dspi_delay_type_t. - * - * The user passes the delay to the configuration along with the prescaler and scaler value. - * This allows the user to directly set the prescaler/scaler values if pre-calculated or - * to manually increment either value. - * - * @param base DSPI peripheral address. - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. - * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). - * @param scaler The scaler delay value (can be any integer between 0 to 15). - * @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t - */ -void DSPI_MasterSetDelayScaler( - SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay); - -/*! - * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. - * - * This function calculates the values for the following. - * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or - * After SCK delay pre-scalar (PASC) and scalar (ASC), or - * Delay after transfer pre-scalar (PDT) and scalar (DT). - * - * These delay names are available in the type dspi_delay_type_t. - * - * The user passes which delay to configure along with the desired delay value in nanoseconds. The function - * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact - * delay match may not be possible. In this case, the closest match is calculated without going below the desired - * delay value input. - * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum - * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay - * input. - * - * @param base DSPI peripheral address. - * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. - * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t - * @param srcClock_Hz Module source input clock in Hertz - * @param delayTimeInNanoSec The desired delay value in nanoseconds. - * @return The actual calculated delay value. - */ -uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, - dspi_ctar_selection_t whichCtar, - dspi_delay_type_t whichDelay, - uint32_t srcClock_Hz, - uint32_t delayTimeInNanoSec); - -/*! - * @brief Writes data into the data buffer for master mode. - * - * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion - * provides characteristics of the data, such as the optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). This is an example. - * @code - * dspi_command_data_config_t commandConfig; - * commandConfig.isPcsContinuous = true; - * commandConfig.whichCtar = kDSPICtar0; - * commandConfig.whichPcs = kDSPIPcs0; - * commandConfig.clearTransferCount = false; - * commandConfig.isEndOfQueue = false; - * DSPI_MasterWriteData(base, &commandConfig, dataWord); - @endcode - * - * @param base DSPI peripheral address. - * @param command Pointer to the command structure. - * @param data The data word to be sent. - */ -static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) -{ - base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | - SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | - SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); -} - -/*! - * @brief Sets the dspi_command_data_config_t structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). - * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure - * before calling the DSPI_MasterWrite_xx(). - * This is an example. - * @code - * dspi_command_data_config_t command; - * DSPI_GetDefaultDataCommandConfig(&command); - * @endcode - * @param command Pointer to the dspi_command_data_config_t structure. - */ -void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command); - -/*! - * @brief Writes data into the data buffer master mode and waits till complete to return. - * - * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion - * provides characteristics of the data, such as the optional continuous chip select - * operation between transfers, the desired Clock and Transfer Attributes register to use for the - * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current - * transfer is the last in the queue, and whether to clear the transfer count (normally needed when - * sending the first frame of a data packet). This is an example. - * @code - * dspi_command_config_t commandConfig; - * commandConfig.isPcsContinuous = true; - * commandConfig.whichCtar = kDSPICtar0; - * commandConfig.whichPcs = kDSPIPcs1; - * commandConfig.clearTransferCount = false; - * commandConfig.isEndOfQueue = false; - * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); - * @endcode - * - * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be - * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, - * the received data is available when the transmit completes. - * - * @param base DSPI peripheral address. - * @param command Pointer to the command structure. - * @param data The data word to be sent. - */ -void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data); - -/*! - * @brief Returns the DSPI command word formatted to the PUSHR data register bit field. - * - * This function allows the caller to pass in the data command structure and returns the command word formatted - * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the - * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or - * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps - * improve performance in cases where the command structure is constant. For example, the user calls this function - * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR - * this formatted command word with the desired data to transmit. This process increases transmit performance when - * compared to calling send functions, such as DSPI_HAL_WriteDataMastermode, which format the command word each time a - * data word is to be sent. - * - * @param command Pointer to the command structure. - * @return The command word formatted to the PUSHR data register bit field. - */ -static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command) -{ - /* Format the 16-bit command word according to the PUSHR data register bit field*/ - return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | - SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | - SPI_PUSHR_CTCNT(command->clearTransferCount)); -} - -/*! - * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data - * buffer master mode and waits till complete to return. - * - * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total 32-bit word - * as the data to send. - * The command portion provides characteristics of the data, such as the optional continuous chip select operation - * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS - * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the - * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for - * appending this command with the data to send. This is an example: - * @code - * dataWord = <16-bit command> | <16-bit data>; - * DSPI_MasterWriteCommandDataBlocking(base, dataWord); - * @endcode - * - * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be - * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). - * Because the SPI is a synchronous protocol, the received data is available when the transmit completes. - * - * For a blocking polling transfer, see methods below. - * Option 1: -* uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); -* uint32_t data0 = command_to_send | data_need_to_send_0; -* uint32_t data1 = command_to_send | data_need_to_send_1; -* uint32_t data2 = command_to_send | data_need_to_send_2; -* -* DSPI_MasterWriteCommandDataBlocking(base,data0); -* DSPI_MasterWriteCommandDataBlocking(base,data1); -* DSPI_MasterWriteCommandDataBlocking(base,data2); -* -* Option 2: -* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); -* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); -* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); -* - * @param base DSPI peripheral address. - * @param data The data word (command and data combined) to be sent. - */ -void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data); - -/*! - * @brief Writes data into the data buffer in slave mode. - * - * In slave mode, up to 16-bit words may be written. - * - * @param base DSPI peripheral address. - * @param data The data to send. - */ -static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data) -{ - base->PUSHR_SLAVE = data; -} - -/*! - * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. - * - * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data - * into data register, and finally waits until the data is transmitted. - * - * @param base DSPI peripheral address. - * @param data The data to send. - */ -void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data); - -/*! - * @brief Reads data from the data buffer. - * - * @param base DSPI peripheral address. - * @return The data from the read data buffer. - */ -static inline uint32_t DSPI_ReadData(SPI_Type *base) -{ - return (base->POPR); -} - -/*! - *@} -*/ - -/*! - * @name Transactional - * @{ - */ -/*Transactional APIs*/ - -/*! - * @brief Initializes the DSPI master handle. - * - * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * @param base DSPI peripheral base address. - * @param handle DSPI handle pointer to dspi_master_handle_t. - * @param callback DSPI callback. - * @param userData Callback function parameter. - */ -void DSPI_MasterTransferCreateHandle(SPI_Type *base, - dspi_master_handle_t *handle, - dspi_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief DSPI master transfer data using polling. - * - * This function transfers data using polling. This is a blocking function, which does not return until all transfers - * have been completed. - * - * @param base DSPI peripheral base address. - * @param transfer Pointer to the dspi_transfer_t structure. - * @return status of status_t. - */ -status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer); - -/*! - * @brief DSPI master transfer data using interrupts. - * - * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all - * data is transferred, the callback function is called. - - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * @param transfer Pointer to the dspi_transfer_t structure. - * @return status of status_t. - */ -status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); - -/*! - * @brief Gets the master transfer count. - * - * This function gets the master transfer count. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count); - -/*! - * @brief DSPI master aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - */ -void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief DSPI Master IRQ handler function. - * - * This function processes the DSPI transmit and receive IRQ. - - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - */ -void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle); - -/*! - * @brief Initializes the DSPI slave handle. - * - * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a - * specified DSPI instance, call this API once to get the initialized handle. - * - * @param handle DSPI handle pointer to the dspi_slave_handle_t. - * @param base DSPI peripheral base address. - * @param callback DSPI callback. - * @param userData Callback function parameter. - */ -void DSPI_SlaveTransferCreateHandle(SPI_Type *base, - dspi_slave_handle_t *handle, - dspi_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief DSPI slave transfers data using an interrupt. - * - * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all - * data is transferred, the callback function is called. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - * @param transfer Pointer to the dspi_transfer_t structure. - * @return status of status_t. - */ -status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer); - -/*! - * @brief Gets the slave transfer count. - * - * This function gets the slave transfer count. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. - * @param count The number of bytes transferred by using the non-blocking transaction. - * @return status of status_t. - */ -status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count); - -/*! - * @brief DSPI slave aborts a transfer using an interrupt. - * - * This function aborts a transfer using an interrupt. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - */ -void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - * @brief DSPI Master IRQ handler function. - * - * This function processes the DSPI transmit and receive IRQ. - * - * @param base DSPI peripheral base address. - * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. - */ -void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle); - -/*! - *@} -*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - /*! - *@} - */ - -#endif /*_FSL_DSPI_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dspi_edma.c b/third_party/nxp/MKW41Z4/drivers/fsl_dspi_edma.c deleted file mode 100644 index ef0d15174..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dspi_edma.c +++ /dev/null @@ -1,1248 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dspi_edma.h" - -/*********************************************************************************************************************** -* Definitons -***********************************************************************************************************************/ - -/*! -* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. -*/ -typedef struct _dspi_master_edma_private_handle -{ - SPI_Type *base; /*!< DSPI peripheral base address. */ - dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ -} dspi_master_edma_private_handle_t; - -/*! -* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. -*/ -typedef struct _dspi_slave_edma_private_handle -{ - SPI_Type *base; /*!< DSPI peripheral base address. */ - dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ -} dspi_slave_edma_private_handle_t; - -/*********************************************************************************************************************** -* Prototypes -***********************************************************************************************************************/ -/*! -* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA. -* This is not a public API. -*/ -static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); - -/*! -* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA. -* This is not a public API. -*/ -static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); -/*! -* @brief Get instance number for DSPI module. -* -* This is not a public API and it's extern from fsl_dspi.c. -* -* @param base DSPI peripheral base address -*/ -extern uint32_t DSPI_GetInstance(SPI_Type *base); - -/*********************************************************************************************************************** -* Variables -***********************************************************************************************************************/ - -/*! @brief Pointers to dspi edma handles for each instance. */ -static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; -static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; - -/*********************************************************************************************************************** -* Code -***********************************************************************************************************************/ - -void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, - dspi_master_edma_handle_t *handle, - dspi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToIntermediaryHandle, - edma_handle_t *edmaIntermediaryToTxRegHandle) -{ - assert(handle); - assert(edmaRxRegToRxDataHandle); - assert(edmaTxDataToIntermediaryHandle); - assert(edmaIntermediaryToTxRegHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - uint32_t instance = DSPI_GetInstance(base); - - s_dspiMasterEdmaPrivateHandle[instance].base = base; - s_dspiMasterEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle; - handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle; -} - -status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0) - { - return kStatus_InvalidArgument; - } - - /* If both send buffer and receive buffer is null */ - if ((!(transfer->txData)) && (!(transfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - - handle->state = kDSPI_Busy; - - uint32_t instance = DSPI_GetInstance(base); - uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; - uint8_t dataAlreadyFed = 0; - uint8_t dataFedMax = 2; - - uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); - uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base); - - edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU)); - - edma_transfer_config_t transferConfigA; - edma_transfer_config_t transferConfigB; - edma_transfer_config_t transferConfigC; - - handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA; - - dspi_command_data_config_t commandStruct; - DSPI_StopTransfer(base); - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); - - commandStruct.whichPcs = - (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); - commandStruct.isEndOfQueue = false; - commandStruct.clearTransferCount = false; - commandStruct.whichCtar = - (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); - commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); - handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - commandStruct.isEndOfQueue = true; - commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); - handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); - - handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; - - if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) - { - handle->fifoSize = 1; - } - else - { - handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); - } - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer - * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame - */ - uint32_t limited_size = 0; - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - limited_size = 32767u; - } - else - { - limited_size = 511u; - } - - if (handle->bitsPerFrame > 8) - { - if (transfer->dataSize > (limited_size << 1u)) - { - handle->state = kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - else - { - if (transfer->dataSize > limited_size) - { - handle->state = kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - - /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */ - if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1)) - { - handle->state = kDSPI_Idle; - return kStatus_InvalidArgument; - } - - DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback, - &s_dspiMasterEdmaPrivateHandle[instance]); - - /* - (1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C. - channel_A minor link to channel_B , channel_B minor link to channel_C. - - Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer. - channel_A:SPI_POPR to rxData, - channel_B:next txData to handle->command (low 16 bits), - channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data - (handle->lastCommand to SPI_PUSHR). - - (2)For DSPI instances with separate RX and TX DMA requests: - Rx DMA request -> channel_A - Tx DMA request -> channel_C -> channel_B . - channel_C major link to channel_B. - So need prepare the first data in "intermediary" before the DMA - transfer and then channel_B is used to prepare the next data to "intermediary" - - channel_A:SPI_POPR to rxData, - channel_C: handle->command (32 bits) to SPI_PUSHR, - channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data - (handle->lastCommand to handle->Command). - */ - - /*If dspi has separate dma request , prepare the first data in "intermediary" . - else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/ - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to - * trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel - */ - - /*Prepare the firt data*/ - if (handle->bitsPerFrame > 8) - { - /* If it's the last word */ - if (handle->remainingSendByteCount <= 2) - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - } - else - { - wordToSend = ((uint32_t)dummyData << 8) | dummyData; - } - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; - handle->command = handle->lastCommand; - } - else /* For all words except the last word , frame > 8bits */ - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data byte */ - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - ++handle->txData; /* increment to next data byte */ - } - else - { - wordToSend = ((uint32_t)dummyData << 8) | dummyData; - } - handle->command = (handle->command & 0xffff0000U) | wordToSend; - } - } - else /* Optimized for bits/frame less than or equal to one byte. */ - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* increment to next data word*/ - } - else - { - wordToSend = dummyData; - } - - if (handle->remainingSendByteCount == 1) - { - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; - handle->command = handle->lastCommand; - } - else - { - handle->command = (handle->command & 0xffff0000U) | wordToSend; - } - } - } - - else /*dspi has shared dma request*/ - - { - /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to - * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. - */ - - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8) - { - while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) - { - if (handle->remainingSendByteCount <= 2) - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - } - else - { - wordToSend = ((uint32_t)dummyData << 8) | dummyData; - } - handle->remainingSendByteCount = 0; - base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; - } - /* For all words except the last word */ - else - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - ++handle->txData; - } - else - { - wordToSend = ((uint32_t)dummyData << 8) | dummyData; - } - handle->remainingSendByteCount -= 2; - base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - dataAlreadyFed += 2; - - /* exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - else /* Optimized for bits/frame less than or equal to one byte. */ - { - while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; - } - else - { - wordToSend = dummyData; - } - - if (handle->remainingSendByteCount == 1) - { - base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; - } - else - { - base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; - } - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - --handle->remainingSendByteCount; - - dataAlreadyFed++; - - /* exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - } - - /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/ - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - transferConfigA.srcAddr = (uint32_t)rxAddr; - transferConfigA.srcOffset = 0; - - if (handle->rxData) - { - transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigA.destOffset = 1; - } - else - { - transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigA.destOffset = 0; - } - - transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8) - { - transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigA.minorLoopBytes = 1; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; - } - else - { - transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigA.minorLoopBytes = 2; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; - } - - /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ - handle->nbytes = transferConfigA.minorLoopBytes; - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &transferConfigA, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MajorInterruptEnable); - - /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should - write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the - SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */ - - EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel); - - /*Calculate the last data : handle->lastCommand*/ - if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || - ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || - ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) && - (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))) - { - if (handle->txData) - { - uint32_t bufferIndex = 0; - - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - if (handle->bitsPerFrame <= 8) - { - bufferIndex = handle->remainingSendByteCount - 1; - } - else - { - bufferIndex = handle->remainingSendByteCount - 2; - } - } - else - { - bufferIndex = handle->remainingSendByteCount; - } - - if (handle->bitsPerFrame <= 8) - { - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1]; - } - else - { - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | - ((uint32_t)handle->txData[bufferIndex - 1] << 8) | - handle->txData[bufferIndex - 2]; - } - } - else - { - if (handle->bitsPerFrame <= 8) - { - wordToSend = dummyData; - } - else - { - wordToSend = ((uint32_t)dummyData << 8) | dummyData; - } - handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; - } - } - - /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data - * (handle->lastCommand) to handle->Command*/ - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand); - transferConfigB.destAddr = (uint32_t) & (handle->command); - transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigB.srcOffset = 0; - transferConfigB.destOffset = 0; - transferConfigB.minorLoopBytes = 4; - transferConfigB.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD); - EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL); - } - - /*User_Send_Buffer(txData) to intermediary(handle->command)*/ - if (((((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) || - ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) && - (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || - (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) - { - if (handle->txData) - { - transferConfigB.srcAddr = (uint32_t)(handle->txData); - transferConfigB.srcOffset = 1; - } - else - { - transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigB.srcOffset = 0; - } - - transferConfigB.destAddr = (uint32_t)(&handle->command); - transferConfigB.destOffset = 0; - - transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8) - { - transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigB.minorLoopBytes = 1; - - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2; - } - else - { - /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is - majorlink , the majorlink would not trigger the channel_C*/ - transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1; - } - } - else - { - transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigB.minorLoopBytes = 2; - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 2; - } - else - { - /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is - * majorlink*/ - transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1; - } - } - - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, softwareTCD); - EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, false); - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL); - } - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL); - } - - /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to - handle the last data */ - - EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); - - /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data - * (handle->lastCommand) to SPI_PUSHR*/ - if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0))) - { - transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand); - transferConfigC.destAddr = (uint32_t)txAddr; - transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.srcOffset = 0; - transferConfigC.destOffset = 0; - transferConfigC.minorLoopBytes = 4; - transferConfigC.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD); - EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL); - } - - if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || - ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)) || - (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) - { - transferConfigC.srcAddr = (uint32_t)(&(handle->command)); - transferConfigC.destAddr = (uint32_t)txAddr; - - transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigC.srcOffset = 0; - transferConfigC.destOffset = 0; - transferConfigC.minorLoopBytes = 4; - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - if (handle->bitsPerFrame <= 8) - { - transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1; - } - else - { - transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; - } - - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD); - } - else - { - transferConfigC.majorLoopCounts = 1; - - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL); - } - - EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, false); - } - else - { - EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL); - } - - /*Start the EDMA channel_A , channel_B , channel_C transfer*/ - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle); - EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle); - - /*Set channel priority*/ - uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; - uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel; - uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel; - uint8_t t = 0; - if (channelPriorityLow > channelPriorityMid) - { - t = channelPriorityLow; - channelPriorityLow = channelPriorityMid; - channelPriorityMid = t; - } - - if (channelPriorityLow > channelPriorityHigh) - { - t = channelPriorityLow; - channelPriorityLow = channelPriorityHigh; - channelPriorityHigh = t; - } - - if (channelPriorityMid > channelPriorityHigh) - { - t = channelPriorityMid; - channelPriorityMid = channelPriorityHigh; - channelPriorityHigh = t; - } - edma_channel_Preemption_config_t preemption_config_t; - preemption_config_t.enableChannelPreemption = true; - preemption_config_t.enablePreemptAbility = true; - preemption_config_t.channelPriority = channelPriorityLow; - - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityMid; - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); - } - else - { - EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityMid; - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &preemption_config_t); - } - - /*Set the channel link.*/ - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB - to prepare the next 32bits data (txData to handle->command) */ - if (handle->remainingSendByteCount > 1) - { - EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base, - handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink, - handle->edmaTxDataToIntermediaryHandle->channel); - } - - DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - } - else - { - if (handle->remainingSendByteCount > 0) - { - EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel); - - EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base, - handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink, - handle->edmaIntermediaryToTxRegHandle->channel); - } - - DSPI_EnableDMA(base, kDSPI_RxDmaEnable); - } - - DSPI_StartTransfer(base); - - return kStatus_Success; -} - -static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(edmaHandle); - assert(g_dspiEdmaPrivateHandle); - - dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle; - - dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle; - - DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - - dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; - - if (dspiEdmaPrivateHandle->handle->callback) - { - dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, - kStatus_Success, dspiEdmaPrivateHandle->handle->userData); - } -} - -void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle) -{ - assert(handle); - - DSPI_StopTransfer(base); - - DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle); - EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle); - - handle->state = kDSPI_Idle; -} - -status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - bytes; - - return kStatus_Success; -} - -void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base, - dspi_slave_edma_handle_t *handle, - dspi_slave_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToTxRegHandle) -{ - assert(handle); - assert(edmaRxRegToRxDataHandle); - assert(edmaTxDataToTxRegHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - uint32_t instance = DSPI_GetInstance(base); - - s_dspiSlaveEdmaPrivateHandle[instance].base = base; - s_dspiSlaveEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; -} - -status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - /* If send/receive length is zero */ - if (transfer->dataSize == 0) - { - return kStatus_InvalidArgument; - } - - /* If both send buffer and receive buffer is null */ - if ((!(transfer->txData)) && (!(transfer->rxData))) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kDSPI_Busy) - { - return kStatus_DSPI_Busy; - } - - handle->state = kDSPI_Busy; - - uint32_t instance = DSPI_GetInstance(base); - uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; - handle->bitsPerFrame = - (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; - - /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer - * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame - */ - uint32_t limited_size = 0; - if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - limited_size = 32767u; - } - else - { - limited_size = 511u; - } - - if (handle->bitsPerFrame > 8) - { - if (transfer->dataSize > (limited_size << 1u)) - { - handle->state = kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - else - { - if (transfer->dataSize > limited_size) - { - handle->state = kDSPI_Idle; - return kStatus_DSPI_OutOfRange; - } - } - - /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */ - if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1)) - { - handle->state = kDSPI_Idle; - return kStatus_InvalidArgument; - } - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]); - - /* Store transfer information */ - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->remainingSendByteCount = transfer->dataSize; - handle->remainingReceiveByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - uint16_t wordToSend = 0; - uint8_t dummyData = DSPI_DUMMY_DATA; - uint8_t dataAlreadyFed = 0; - uint8_t dataFedMax = 2; - - uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); - uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base); - - edma_transfer_config_t transferConfigA; - edma_transfer_config_t transferConfigC; - - DSPI_StopTransfer(base); - - DSPI_FlushFifo(base, true, true); - DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); - - DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - - DSPI_StartTransfer(base); - - /*if dspi has separate dma request , need not prepare data first . - else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to - slaveGetTxRegister if there is no fifo*/ - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to - * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. - */ - /* If bits/frame is greater than one byte */ - if (handle->bitsPerFrame > 8) - { - while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) - { - if (handle->txData) - { - wordToSend = *(handle->txData); - ++handle->txData; /* Increment to next data byte */ - - wordToSend |= (unsigned)(*(handle->txData)) << 8U; - ++handle->txData; /* Increment to next data byte */ - } - else - { - wordToSend = ((uint32_t)dummyData << 8) | dummyData; - } - handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ - base->PUSHR_SLAVE = wordToSend; - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - - dataAlreadyFed += 2; - - /* Exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - else /* Optimized for bits/frame less than or equal to one byte. */ - { - while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) - { - if (handle->txData) - { - wordToSend = *(handle->txData); - /* Increment to next data word*/ - ++handle->txData; - } - else - { - wordToSend = dummyData; - } - - base->PUSHR_SLAVE = wordToSend; - - /* Try to clear the TFFF; if the TX FIFO is full this will clear */ - DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); - /* Decrement remainingSendByteCount*/ - --handle->remainingSendByteCount; - - dataAlreadyFed++; - - /* Exit loop if send count is zero, else update local variables for next loop */ - if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) - { - break; - } - } /* End of TX FIFO fill while loop */ - } - } - - /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/ - if (handle->remainingReceiveByteCount > 0) - { - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - transferConfigA.srcAddr = (uint32_t)rxAddr; - transferConfigA.srcOffset = 0; - - if (handle->rxData) - { - transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigA.destOffset = 1; - } - else - { - transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigA.destOffset = 0; - } - - transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8) - { - transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigA.minorLoopBytes = 1; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; - } - else - { - transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigA.minorLoopBytes = 2; - transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; - } - - /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ - handle->nbytes = transferConfigA.minorLoopBytes; - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &transferConfigA, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MajorInterruptEnable); - } - - if (handle->remainingSendByteCount > 0) - { - /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/ - EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); - - transferConfigC.destAddr = (uint32_t)txAddr; - transferConfigC.destOffset = 0; - - if (handle->txData) - { - transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0])); - transferConfigC.srcOffset = 1; - } - else - { - transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigC.srcOffset = 0; - if (handle->bitsPerFrame <= 8) - { - handle->txBuffIfNull = DSPI_DUMMY_DATA; - } - else - { - handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA; - } - } - - transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes; - - if (handle->bitsPerFrame <= 8) - { - transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigC.minorLoopBytes = 1; - transferConfigC.majorLoopCounts = handle->remainingSendByteCount; - } - else - { - transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigC.minorLoopBytes = 2; - transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2; - } - - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigC, NULL); - - EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); - } - - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - - /*Set channel priority*/ - uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; - uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel; - uint8_t t = 0; - - if (channelPriorityLow > channelPriorityHigh) - { - t = channelPriorityLow; - channelPriorityLow = channelPriorityHigh; - channelPriorityHigh = t; - } - - edma_channel_Preemption_config_t preemption_config_t; - preemption_config_t.enableChannelPreemption = true; - preemption_config_t.enablePreemptAbility = true; - preemption_config_t.channelPriority = channelPriorityLow; - - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &preemption_config_t); - } - else - { - EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &preemption_config_t); - - preemption_config_t.channelPriority = channelPriorityHigh; - EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &preemption_config_t); - } - - /*Set the channel link. - For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C. - For DSPI instances with separate RX and TX DMA requests: - Rx DMA request -> channel_A - Tx DMA request -> channel_C */ - if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - if (handle->remainingSendByteCount > 0) - { - EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel); - } - DSPI_EnableDMA(base, kDSPI_RxDmaEnable); - } - else - { - DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - } - - return kStatus_Success; -} - -static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_dspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(edmaHandle); - assert(g_dspiEdmaPrivateHandle); - - dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle; - - dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle; - - DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - - dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; - - if (dspiEdmaPrivateHandle->handle->callback) - { - dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, - kStatus_Success, dspiEdmaPrivateHandle->handle->userData); - } -} - -void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle) -{ - assert(handle); - - DSPI_StopTransfer(base); - - DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); - - handle->state = kDSPI_Idle; -} - -status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kDSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t bytes; - - bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - bytes; - - return kStatus_Success; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dspi_edma.h b/third_party/nxp/MKW41Z4/drivers/fsl_dspi_edma.h deleted file mode 100644 index 23e29ce29..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dspi_edma.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_DSPI_EDMA_H_ -#define _FSL_DSPI_EDMA_H_ - -#include "fsl_dspi.h" -#include "fsl_edma.h" -/*! - * @addtogroup dspi_edma_driver - * @{ - */ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/*! -* @brief Forward declaration of the DSPI eDMA master handle typedefs. -*/ -typedef struct _dspi_master_edma_handle dspi_master_edma_handle_t; - -/*! -* @brief Forward declaration of the DSPI eDMA slave handle typedefs. -*/ -typedef struct _dspi_slave_edma_handle dspi_slave_edma_handle_t; - -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral base address. - * @param handle A pointer to the handle for the DSPI master. - * @param status Success or error code describing whether the transfer completed. - * @param userData An arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base, - dspi_master_edma_handle_t *handle, - status_t status, - void *userData); -/*! - * @brief Completion callback function pointer type. - * - * @param base DSPI peripheral base address. - * @param handle A pointer to the handle for the DSPI slave. - * @param status Success or error code describing whether the transfer completed. - * @param userData An arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base, - dspi_slave_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief DSPI master eDMA transfer handle structure used for the transactional API. */ -struct _dspi_master_edma_handle -{ - uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ - volatile uint32_t command; /*!< The desired data command. */ - volatile uint32_t lastCommand; /*!< The desired last data command. */ - - uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile bool - isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal keeps active after the last frame transfer.*/ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ - volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ - size_t totalByteCount; /*!< A number of transfer bytes*/ - - uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ - uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ - - dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ - - edma_handle_t *edmaRxRegToRxDataHandle; /*!event, &reschedule); - portYIELD_FROM_ISR(reschedule); -} - -status_t DSPI_RTOS_Init(dspi_rtos_handle_t *handle, - SPI_Type *base, - const dspi_master_config_t *masterConfig, - uint32_t srcClock_Hz) -{ - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - if (base == NULL) - { - return kStatus_InvalidArgument; - } - - memset(handle, 0, sizeof(dspi_rtos_handle_t)); - -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->mutex = xSemaphoreCreateMutexStatic(&handle->mutexBuffer); -#else - handle->mutex = xSemaphoreCreateMutex(); -#endif - if (handle->mutex == NULL) - { - return kStatus_Fail; - } -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->event = xSemaphoreCreateBinaryStatic(&handle->semaphoreBuffer); -#else - handle->event = xSemaphoreCreateBinary(); -#endif - if (handle->event == NULL) - { - vSemaphoreDelete(handle->mutex); - return kStatus_Fail; - } - - handle->base = base; - - DSPI_MasterInit(handle->base, masterConfig, srcClock_Hz); - DSPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, DSPI_RTOS_Callback, (void *)handle); - - return kStatus_Success; -} - -status_t DSPI_RTOS_Deinit(dspi_rtos_handle_t *handle) -{ - DSPI_Deinit(handle->base); - vSemaphoreDelete(handle->event); - vSemaphoreDelete(handle->mutex); - - return kStatus_Success; -} - -status_t DSPI_RTOS_Transfer(dspi_rtos_handle_t *handle, dspi_transfer_t *transfer) -{ - status_t status; - - /* Lock resource mutex */ - if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) - { - return kStatus_DSPI_Busy; - } - - status = DSPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); - if (status != kStatus_Success) - { - xSemaphoreGive(handle->mutex); - return status; - } - - /* Wait for transfer to finish */ - xSemaphoreTake(handle->event, portMAX_DELAY); - - /* Unlock resource mutex */ - xSemaphoreGive(handle->mutex); - - /* Return status captured by callback function */ - return handle->async_status; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_dspi_freertos.h b/third_party/nxp/MKW41Z4/drivers/fsl_dspi_freertos.h deleted file mode 100644 index 7e7179b9f..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_dspi_freertos.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_DSPI_FREERTOS_H__ -#define __FSL_DSPI_FREERTOS_H__ - -#include "FreeRTOSConfig.h" -#include "FreeRTOS.h" -#include "portable.h" -#include "semphr.h" - -#include "fsl_dspi.h" - -/*! - * @addtogroup dspi_freertos_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! -* @cond RTOS_PRIVATE -* @brief DSPI FreeRTOS handle -*/ -typedef struct _dspi_rtos_handle -{ - SPI_Type *base; /*!< DSPI base address */ - dspi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ - status_t async_status; /*!< Transactional state of the underlying driver */ - SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a transfer */ - SemaphoreHandle_t event; /*!< Semaphore to notify and unblock a task when a transfer ends */ -#if (configSUPPORT_STATIC_ALLOCATION == 1) - StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ - StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for event */ -#endif -} dspi_rtos_handle_t; -/*! \endcond */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name DSPI RTOS Operation - * @{ - */ - -/*! - * @brief Initializes the DSPI. - * - * This function initializes the DSPI module and the related RTOS context. - * - * @param handle The RTOS DSPI handle, the pointer to an allocated space for RTOS context. - * @param base The pointer base address of the DSPI instance to initialize. - * @param masterConfig A configuration structure to set-up the DSPI in master mode. - * @param srcClock_Hz A frequency of the input clock of the DSPI module. - * @return status of the operation. - */ -status_t DSPI_RTOS_Init(dspi_rtos_handle_t *handle, - SPI_Type *base, - const dspi_master_config_t *masterConfig, - uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the DSPI. - * - * This function deinitializes the DSPI module and the related RTOS context. - * - * @param handle The RTOS DSPI handle. - */ -status_t DSPI_RTOS_Deinit(dspi_rtos_handle_t *handle); - -/*! - * @brief Performs the SPI transfer. - * - * This function performs the SPI transfer according to the data given in the transfer structure. - * - * @param handle The RTOS DSPI handle. - * @param transfer A structure specifying the transfer parameters. - * @return status of the operation. - */ -status_t DSPI_RTOS_Transfer(dspi_rtos_handle_t *handle, dspi_transfer_t *transfer); - -/*! - * @} - */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* __FSL_DSPI_FREERTOS_H__ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_edma.c b/third_party/nxp/MKW41Z4/drivers/fsl_edma.c deleted file mode 100644 index be51f4c1a..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_edma.c +++ /dev/null @@ -1,1754 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define EDMA_TRANSFER_ENABLED_MASK 0x80U - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for EDMA. - * - * @param base EDMA peripheral base address. - */ -static uint32_t EDMA_GetInstance(DMA_Type *base); - -/*! - * @brief Push content of TCD structure into hardware TCD register. - * - * @param base EDMA peripheral base address. - * @param channel EDMA channel number. - * @param tcd Point to TCD structure. - */ -static void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map EDMA instance number to base pointer. */ -static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map EDMA instance number to clock name. */ -static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Array to map EDMA instance number to IRQ number. */ -static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; - -/*! @brief Pointers to transfer handle for each EDMA channel. */ -static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t EDMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) - { - if (s_edmaBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_edmaBases)); - - return instance; -} - -static void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - /* Push tcd into hardware TCD register */ - base->TCD[channel].SADDR = tcd->SADDR; - base->TCD[channel].SOFF = tcd->SOFF; - base->TCD[channel].ATTR = tcd->ATTR; - base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; - base->TCD[channel].SLAST = tcd->SLAST; - base->TCD[channel].DADDR = tcd->DADDR; - base->TCD[channel].DOFF = tcd->DOFF; - base->TCD[channel].CITER_ELINKNO = tcd->CITER; - base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; - /* Clear DONE bit first, otherwise ESG cannot be set */ - base->TCD[channel].CSR = 0; - base->TCD[channel].CSR = tcd->CSR; - base->TCD[channel].BITER_ELINKNO = tcd->BITER; -} - -void EDMA_Init(DMA_Type *base, const edma_config_t *config) -{ - assert(config != NULL); - - uint32_t tmpreg; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate EDMA periphral clock */ - CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Configure EDMA peripheral according to the configuration structure. */ - tmpreg = base->CR; - tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); - tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | - DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); - base->CR = tmpreg; -} - -void EDMA_Deinit(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate EDMA periphral clock */ - CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void EDMA_GetDefaultConfig(edma_config_t *config) -{ - assert(config != NULL); - - config->enableRoundRobinArbitration = false; - config->enableHaltOnError = true; - config->enableContinuousLinkMode = false; - config->enableDebugMode = false; -} - -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); -} - -void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); -} - -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].NBYTES_MLOFFYES; - tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - base->TCD[channel].NBYTES_MLOFFYES = tmpreg; -} - -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); -} - -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Enable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI |= (0x1U << channel); - } - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Disable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI &= ~(0x1U << channel); - } - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdReset(edma_tcd_t *tcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - /* Reset channel TCD */ - tcd->SADDR = 0U; - tcd->SOFF = 0U; - tcd->ATTR = 0U; - tcd->NBYTES = 0U; - tcd->SLAST = 0U; - tcd->DADDR = 0U; - tcd->DOFF = 0U; - tcd->CITER = 0U; - tcd->DLAST_SGA = 0U; - /* Enable auto disable request feature */ - tcd->CSR = DMA_CSR_DREQ(true); - tcd->BITER = 0U; -} - -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - /* source address */ - tcd->SADDR = config->srcAddr; - /* destination address */ - tcd->DADDR = config->destAddr; - /* Source data and destination data transfer size */ - tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); - /* Source address signed offset */ - tcd->SOFF = config->srcOffset; - /* Destination address signed offset */ - tcd->DOFF = config->destOffset; - /* Minor byte transfer count */ - tcd->NBYTES = config->minorLoopBytes; - /* Current major iteration count */ - tcd->CITER = config->majorLoopCounts; - /* Starting major iteration count */ - tcd->BITER = config->majorLoopCounts; - /* Enable scatter/gather processing */ - if (nextTcd != NULL) - { - tcd->DLAST_SGA = (uint32_t)nextTcd; - /* - Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, - user must call EDMA_TcdReset or EDMA_ResetChannel which will set - DREQ, so must use "|" or "&" rather than "=". - - Clear the DREQ bit because scatter gather has been enabled, so the - previous transfer is not the last transfer, and channel request should - be enabled at the next transfer(the next TCD). - */ - tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - } -} - -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->NBYTES & - ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - tcd->NBYTES = tmpreg; -} - -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (type == kEDMA_MinorLink) /* Minor link config */ - { - uint32_t tmpreg; - - /* Enable minor link */ - tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; - /* Set likned channel */ - tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); - tcd->CITER = tmpreg; - tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); - tcd->BITER = tmpreg; - } - else if (type == kEDMA_MajorLink) /* Major link config */ - { - uint32_t tmpreg; - - /* Enable major link */ - tcd->CSR |= DMA_CSR_MAJORELINK_MASK; - /* Set major linked channel */ - tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); - tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); - } - else /* Link none */ - { - tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; - tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; - } -} - -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t remainingCount = 0; - - if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) - { - remainingCount = 0; - } - else - { - /* Calculate the unfinished bytes */ - if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) - { - remainingCount = - (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT; - } - else - { - remainingCount = - (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT; - } - } - - return remainingCount; -} - -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t retval = 0; - - /* Get DONE bit flag */ - retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); - /* Get ERROR bit flag */ - retval |= (((base->ERR >> channel) & 0x1U) << 1U); - /* Get INT bit flag */ - retval |= (((base->INT >> channel) & 0x1U) << 2U); - - return retval; -} - -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Clear DONE bit flag */ - if (mask & kEDMA_DoneFlag) - { - base->CDNE = channel; - } - /* Clear ERROR bit flag */ - if (mask & kEDMA_ErrorFlag) - { - base->CERR = channel; - } - /* Clear INT bit flag */ - if (mask & kEDMA_InterruptFlag) - { - base->CINT = channel; - } -} - -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(handle != NULL); - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t edmaInstance; - uint32_t channelIndex; - edma_tcd_t *tcdRegs; - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - handle->base = base; - handle->channel = channel; - /* Get the DMA instance number */ - edmaInstance = EDMA_GetInstance(base); - channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; - s_EDMAHandle[channelIndex] = handle; - - /* Enable NVIC interrupt */ - EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); - - /* - Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), - CSR will be 0. Because in order to suit EDMA busy check mechanism in - EDMA_SubmitTransfer, CSR must be set 0. - */ - tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - tcdRegs->SADDR = 0; - tcdRegs->SOFF = 0; - tcdRegs->ATTR = 0; - tcdRegs->NBYTES = 0; - tcdRegs->SLAST = 0; - tcdRegs->DADDR = 0; - tcdRegs->DOFF = 0; - tcdRegs->CITER = 0; - tcdRegs->DLAST_SGA = 0; - tcdRegs->CSR = 0; - tcdRegs->BITER = 0; -} - -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) -{ - assert(handle != NULL); - assert(((uint32_t)tcdPool & 0x1FU) == 0); - - /* Initialize tcd queue attibute. */ - handle->header = 0; - handle->tail = 0; - handle->tcdUsed = 0; - handle->tcdSize = tcdSize; - handle->flags = 0; - handle->tcdPool = tcdPool; -} - -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type) -{ - assert(config != NULL); - assert(srcAddr != NULL); - assert(destAddr != NULL); - assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U)); - assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); - assert(transferBytes % bytesEachRequest == 0); - - config->destAddr = (uint32_t)destAddr; - config->srcAddr = (uint32_t)srcAddr; - config->minorLoopBytes = bytesEachRequest; - config->majorLoopCounts = transferBytes / bytesEachRequest; - switch (srcWidth) - { - case 1U: - config->srcTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->srcTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->srcTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->srcTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->srcTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (destWidth) - { - case 1U: - config->destTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->destTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->destTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->destTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->destTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (type) - { - case kEDMA_MemoryToMemory: - config->destOffset = destWidth; - config->srcOffset = srcWidth; - break; - case kEDMA_MemoryToPeripheral: - config->destOffset = 0U; - config->srcOffset = srcWidth; - break; - case kEDMA_PeripheralToMemory: - config->destOffset = destWidth; - config->srcOffset = 0U; - break; - default: - break; - } -} - -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) -{ - assert(handle != NULL); - assert(config != NULL); - - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - if (handle->tcdPool == NULL) - { - /* - Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because - if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit - this check mechanism, EDMA_CreatHandle will clear CSR register. - */ - if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) - { - return kStatus_EDMA_Busy; - } - else - { - EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); - /* Enable auto disable request feature */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; - /* Enable major interrupt */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; - - return kStatus_Success; - } - } - else /* Use the TCD queue. */ - { - uint32_t primask; - uint32_t csr; - int8_t currentTcd; - int8_t previousTcd; - int8_t nextTcd; - - /* Check if tcd pool is full. */ - primask = DisableGlobalIRQ(); - if (handle->tcdUsed >= handle->tcdSize) - { - EnableGlobalIRQ(primask); - - return kStatus_EDMA_QueueFull; - } - currentTcd = handle->tail; - handle->tcdUsed++; - /* Calculate index of next TCD */ - nextTcd = currentTcd + 1U; - if (nextTcd == handle->tcdSize) - { - nextTcd = 0U; - } - /* Advance queue tail index */ - handle->tail = nextTcd; - EnableGlobalIRQ(primask); - /* Calculate index of previous TCD */ - previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; - /* Configure current TCD block. */ - EDMA_TcdReset(&handle->tcdPool[currentTcd]); - EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); - /* Enable major interrupt */ - handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; - /* Link current TCD with next TCD for identification of current TCD */ - handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; - /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ - if (currentTcd != previousTcd) - { - /* Enable scatter/gather feature in the previous TCD block. */ - csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - handle->tcdPool[previousTcd].CSR = csr; - /* - Check if the TCD blcok in the registers is the previous one (points to current TCD block). It - is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to - link the TCD register in case link the current TCD with the dead chain when TCD loading occurs - before link the previous TCD block. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) - { - /* Enable scatter/gather also in the TCD registers. */ - csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ - tcdRegs->CSR = csr; - /* - It is very important to check the ESG bit! - Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can - be used to check if the dynamic TCD link operation is successful. If ESG bit is not set - and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and - the current TCD block has been loaded into TCD registers), it means transfer finished - and TCD link operation fail, so must install TCD content into TCD registers and enable - transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic - link succeed. - */ - if (tcdRegs->CSR & DMA_CSR_ESG_MASK) - { - return kStatus_Success; - } - /* - Check whether the current TCD block is already loaded in the TCD registers. It is another - condition when ESG bit is not set: it means the dynamic TCD link succeed and the current - TCD block has been loaded into TCD registers. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) - { - return kStatus_Success; - } - /* - If go to this, means the previous transfer finished, and the DONE bit is set. - So shall configure TCD registers. - */ - } - else if (tcdRegs->DLAST_SGA != 0) - { - /* The current TCD block has been linked successfully. */ - return kStatus_Success; - } - else - { - /* - DLAST_SGA is 0 and it means the first submit transfer, so shall configure - TCD registers. - */ - } - } - /* There is no live chain, TCD block need to be installed in TCD registers. */ - EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); - /* Enable channel request again. */ - if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - - return kStatus_Success; - } -} - -void EDMA_StartTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - if (handle->tcdPool == NULL) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - else /* Use the TCD queue. */ - { - uint32_t primask; - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - handle->flags |= EDMA_TRANSFER_ENABLED_MASK; - - /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ - if (tcdRegs->DLAST_SGA != 0U) - { - primask = DisableGlobalIRQ(); - /* Check if channel request is actually disable. */ - if ((handle->base->ERQ & (1U << handle->channel)) == 0U) - { - /* Check if transfer is paused. */ - if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) - { - /* - Re-enable channel request must be as soon as possible, so must put it into - critical section to avoid task switching or interrupt service routine. - */ - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - } - EnableGlobalIRQ(primask); - } - } -} - -void EDMA_StopTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); -} - -void EDMA_AbortTransfer(edma_handle_t *handle) -{ - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); - /* - Clear CSR to release channel. Because if the given channel started transfer, - CSR will be not zero. Because if it is the last transfer, DREQ will be set. - If not, ESG will be set. - */ - handle->base->TCD[handle->channel].CSR = 0; - /* Cancel all next TCD transfer. */ - handle->base->TCD[handle->channel].DLAST_SGA = 0; -} - -void EDMA_HandleIRQ(edma_handle_t *handle) -{ - assert(handle != NULL); - - /* Clear EDMA interrupt flag */ - handle->base->CINT = handle->channel; - if ((handle->tcdPool == NULL) && (handle->callback != NULL)) - { - (handle->callback)(handle, handle->userData, true, 0); - } - else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ - { - uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; - uint32_t sga_index; - int32_t tcds_done; - uint8_t new_header; - bool transfer_done; - - /* Check if transfer is already finished. */ - transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); - /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga -= (uint32_t)handle->tcdPool; - /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga_index = sga / sizeof(edma_tcd_t); - /* Adjust header positions. */ - if (transfer_done) - { - /* New header shall point to the next TCD to be loaded (current one is already finished) */ - new_header = sga_index; - } - else - { - /* New header shall point to this descriptor currently loaded (not finished yet) */ - new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; - } - /* Calculate the number of finished TCDs */ - if (new_header == handle->header) - { - if (handle->tcdUsed == handle->tcdSize) - { - tcds_done = handle->tcdUsed; - } - else - { - /* No TCD in the memory are going to be loaded or internal error occurs. */ - tcds_done = 0; - } - } - else - { - tcds_done = new_header - handle->header; - if (tcds_done < 0) - { - tcds_done += handle->tcdSize; - } - } - /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ - handle->header = new_header; - /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ - handle->tcdUsed -= tcds_done; - /* Invoke callback function. */ - if (handle->callback) - { - (handle->callback)(handle, handle->userData, transfer_done, tcds_done); - } - } -} - -/* 8 channels (Shared): kl28 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U - -void DMA0_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } -} - -void DMA0_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } -} - -void DMA0_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } -} - -void DMA0_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } -} - -#if defined(DMA1) -void DMA1_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA1_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA1_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA1_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} -#endif -#endif /* 8 channels (Shared) */ - -/* 16 channels (Shared): K32H844P */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U - -void DMA0_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } -} - -void DMA0_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } -} - -void DMA0_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } -} - -void DMA0_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } -} - -void DMA0_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA0_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA0_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA0_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} - -#if defined(DMA1) -void DMA1_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } -} - -void DMA1_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } -} - -void DMA1_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } -} - -void DMA1_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } -} - -void DMA1_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA1_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA1_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA1_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif -#endif /* 16 channels (Shared) */ - -/* 32 channels (Shared): k80 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_DMA16_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } -} - -void DMA1_DMA17_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } -} - -void DMA2_DMA18_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } -} - -void DMA3_DMA19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } -} - -void DMA4_DMA20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } -} - -void DMA5_DMA21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } -} - -void DMA6_DMA22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } -} - -void DMA7_DMA23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } -} - -void DMA8_DMA24_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } -} - -void DMA9_DMA25_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } -} - -void DMA10_DMA26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } -} - -void DMA11_DMA27_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } -} - -void DMA12_DMA28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA13_DMA29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA14_DMA30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA15_DMA31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif /* 32 channels (Shared) */ - -/* 32 channels (Shared): MCIMX7U5_M4 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_0_4_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } -} - -void DMA0_1_5_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } -} - -void DMA0_2_6_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } -} - -void DMA0_3_7_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } -} - -void DMA0_8_12_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA0_9_13_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA0_10_14_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA0_11_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} - -void DMA0_16_20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } -} - -void DMA0_17_21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } -} - -void DMA0_18_22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } -} - -void DMA0_19_23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } -} - -void DMA0_24_28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA0_25_29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA0_26_30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA0_27_31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif /* 32 channels (Shared): MCIMX7U5 */ - -/* 4 channels (No Shared): kv10 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 - -void DMA0_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[0]); -} - -void DMA1_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[1]); -} - -void DMA2_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[2]); -} - -void DMA3_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[3]); -} - -/* 8 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U - -void DMA4_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[4]); -} - -void DMA5_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[5]); -} - -void DMA6_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[6]); -} - -void DMA7_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[7]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ - -/* 16 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U - -void DMA8_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[8]); -} - -void DMA9_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[9]); -} - -void DMA10_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[10]); -} - -void DMA11_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[11]); -} - -void DMA12_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[12]); -} - -void DMA13_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[13]); -} - -void DMA14_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[14]); -} - -void DMA15_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[15]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ - -/* 32 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U - -void DMA16_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[16]); -} - -void DMA17_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[17]); -} - -void DMA18_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[18]); -} - -void DMA19_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[19]); -} - -void DMA20_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[20]); -} - -void DMA21_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[21]); -} - -void DMA22_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[22]); -} - -void DMA23_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[23]); -} - -void DMA24_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[24]); -} - -void DMA25_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[25]); -} - -void DMA26_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[26]); -} - -void DMA27_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[27]); -} - -void DMA28_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[28]); -} - -void DMA29_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[29]); -} - -void DMA30_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[30]); -} - -void DMA31_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[31]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ - -#endif /* 4/8/16/32 channels (No Shared) */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_edma.h b/third_party/nxp/MKW41Z4/drivers/fsl_edma.h deleted file mode 100644 index f8faf2c44..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_edma.h +++ /dev/null @@ -1,910 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_EDMA_H_ -#define _FSL_EDMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup edma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ -/*@}*/ - -/*! @brief Compute the offset unit from DCHPRI3 */ -#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) - -/*! @brief Get the pointer of DCHPRIn */ -#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] - -/*! @brief eDMA transfer configuration */ -typedef enum _edma_transfer_size -{ - kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ - kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ - kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ - kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ - kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ -} edma_transfer_size_t; - -/*! @brief eDMA modulo configuration */ -typedef enum _edma_modulo -{ - kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ - kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ - kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ - kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ - kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ - kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ - kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ - kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ - kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ - kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ - kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ - kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ - kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ - kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ - kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ - kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ - kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ - kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ - kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ - kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ - kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ - kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ - kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ - kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ - kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ - kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ - kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ - kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ - kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ - kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ - kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ - kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ -} edma_modulo_t; - -/*! @brief Bandwidth control */ -typedef enum _edma_bandwidth -{ - kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ - kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ - kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ -} edma_bandwidth_t; - -/*! @brief Channel link type */ -typedef enum _edma_channel_link_type -{ - kEDMA_LinkNone = 0x0U, /*!< No channel link */ - kEDMA_MinorLink, /*!< Channel link after each minor loop */ - kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ -} edma_channel_link_type_t; - -/*!@brief eDMA channel status flags. */ -enum _edma_channel_status_flags -{ - kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ - kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ - kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ -}; - -/*! @brief eDMA channel error status flags. */ -enum _edma_error_status_flags -{ - kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ - kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ - kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ - kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ - kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ - kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ - kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ - kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ - kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ - kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ - kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ -#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 - kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ -#endif - kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ -}; - -/*! @brief eDMA interrupt source */ -typedef enum _edma_interrupt_enable -{ - kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ - kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ - kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ -} edma_interrupt_enable_t; - -/*! @brief eDMA transfer type */ -typedef enum _edma_transfer_type -{ - kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ - kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ - kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ -} edma_transfer_type_t; - -/*! @brief eDMA transfer status */ -enum _edma_transfer_status -{ - kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ - kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief eDMA global configuration structure.*/ -typedef struct _edma_config -{ - bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel - activates again if that channel has a minor loop channel link enabled and - the link channel is itself. */ - bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. - Subsequently, all service requests are ignored until the HALT bit is cleared.*/ - bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority - arbitration is used for channel selection */ - bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of - a new channel. Executing channels are allowed to complete. */ -} edma_config_t; - -/*! - * @brief eDMA transfer configuration - * - * This structure configures the source/destination transfer attribute. - * This figure shows the eDMA's transfer model: - * _________________________________________________ - * | Transfer Size | | - * Minor Loop |_______________| Major loop Count 1 | - * Bytes | Transfer Size | | - * ____________|_______________|____________________|--> Minor loop complete - * ____________________________________ - * | | | - * |_______________| Major Loop Count 2 | - * | | | - * |_______________|____________________|--> Minor loop Complete - * - * ---------------------------------------------------------> Transfer complete - */ -typedef struct _edma_transfer_config -{ - uint32_t srcAddr; /*!< Source data address. */ - uint32_t destAddr; /*!< Destination data address. */ - edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ - edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ - int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to - form the next-state value as each source read is completed. */ - int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to - form the next-state value as each destination write is completed. */ - uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ - uint32_t majorLoopCounts; /*!< Major loop iteration count. */ -} edma_transfer_config_t; - -/*! @brief eDMA channel priority configuration */ -typedef struct _edma_channel_Preemption_config -{ - bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ - bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ - uint8_t channelPriority; /*!< Channel priority */ -} edma_channel_Preemption_config_t; - -/*! @brief eDMA minor offset configuration */ -typedef struct _edma_minor_offset_config -{ - bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ - bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ - uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ -} edma_minor_offset_config_t; - -/*! - * @brief eDMA TCD. - * - * This structure is same as TCD register which is described in reference manual, - * and is used to configure the scatter/gather feature as a next hardware TCD. - */ -typedef struct _edma_tcd -{ - __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ - __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ - __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ - __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ - __IO uint32_t SLAST; /*!< SLAST register */ - __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ - __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ - __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ - __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ - __IO uint16_t CSR; /*!< CSR register, for TCD control status */ - __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ -} edma_tcd_t; - -/*! @brief Callback for eDMA */ -struct _edma_handle; - -/*! @brief Define callback function for eDMA. */ -typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @brief eDMA transfer handle structure */ -typedef struct _edma_handle -{ - edma_callback callback; /*!< Callback function for major count exhausted. */ - void *userData; /*!< Callback function parameter. */ - DMA_Type *base; /*!< eDMA peripheral base address. */ - edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ - uint8_t channel; /*!< eDMA channel number. */ - volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ - volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ - volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in - the memory. */ - volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ - uint8_t flags; /*!< The status of the current channel. */ -} edma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name eDMA initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the eDMA peripheral. - * - * This function ungates the eDMA clock and configures the eDMA peripheral according - * to the configuration structure. - * - * @param base eDMA peripheral base address. - * @param config A pointer to the configuration structure, see "edma_config_t". - * @note This function enables the minor loop map feature. - */ -void EDMA_Init(DMA_Type *base, const edma_config_t *config); - -/*! - * @brief Deinitializes the eDMA peripheral. - * - * This function gates the eDMA clock. - * - * @param base eDMA peripheral base address. - */ -void EDMA_Deinit(DMA_Type *base); - -/*! - * @brief Gets the eDMA default configuration structure. - * - * This function sets the configuration structure to default values. - * The default configuration is set to the following values. - * @code - * config.enableContinuousLinkMode = false; - * config.enableHaltOnError = true; - * config.enableRoundRobinArbitration = false; - * config.enableDebugMode = false; - * @endcode - * - * @param config A pointer to the eDMA configuration structure. - */ -void EDMA_GetDefaultConfig(edma_config_t *config); - -/* @} */ -/*! - * @name eDMA Channel Operation - * @{ - */ - -/*! - * @brief Sets all TCD registers to default values. - * - * This function sets TCD registers for this channel to default values. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @note This function must not be called while the channel transfer is ongoing - * or it causes unpredictable results. - * @note This function enables the auto stop request feature. - */ -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); - -/*! - * @brief Configures the eDMA transfer attribute. - * - * This function configures the transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the TCD address. - * Example: - * @code - * edma_transfer_t config; - * edma_tcd_t tcd; - * config.srcAddr = ..; - * config.destAddr = ..; - * ... - * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); - * @endcode - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Point to TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note If nextTcd is not NULL, it means scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the eDMA_ResetChannel. - */ -void EDMA_SetTransferConfig(DMA_Type *base, - uint32_t channel, - const edma_transfer_config_t *config, - edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA minor offset feature. - * - * The minor offset means that the signed-extended value is added to the source address or destination - * address after each minor loop. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); - -/*! - * @brief Configures the eDMA channel preemption feature. - * - * This function configures the channel preemption attribute and the priority of the channel. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number - * @param config A pointer to the channel preemption configuration structure. - */ -static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, - uint32_t channel, - const edma_channel_Preemption_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - DMA_DCHPRIn(base, channel) = - (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | - DMA_DCHPRI0_CHPRI(config->channelPriority)); -} - -/*! - * @brief Sets the channel link for the eDMA transfer. - * - * This function configures either the minor link or the major link mode. The minor link means that the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param type A channel link type, which can be one of the following: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - */ -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA transfer. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA transfer. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT -/*! - * @brief Enables an async request for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); -} -#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ - -/*! - * @brief Enables an auto stop request for the eDMA transfer. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of the interrupt source to be set. Use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/* @} */ -/*! - * @name eDMA TCD Operation - * @{ - */ - -/*! - * @brief Sets all fields to default values for the TCD structure. - * - * This function sets all fields for this TCD structure to default value. - * - * @param tcd Pointer to the TCD structure. - * @note This function enables the auto stop request feature. - */ -void EDMA_TcdReset(edma_tcd_t *tcd); - -/*! - * @brief Configures the eDMA TCD transfer attribute. - * - * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. - * The STCD is used in the scatter-gather mode. - * This function configures the TCD transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the next TCD address. - * Example: - * @code - * edma_transfer_t config = { - * ... - * } - * edma_tcd_t tcd __aligned(32); - * edma_tcd_t nextTcd __aligned(32); - * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); - * @endcode - * - * @param tcd Pointer to the TCD structure. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Pointer to the next TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note TCD address should be 32 bytes aligned or it causes an eDMA error. - * @note If the nextTcd is not NULL, the scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the EDMA_TcdReset. - */ -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA TCD minor offset feature. - * - * A minor offset is a signed-extended value added to the source address or a destination - * address after each minor loop. - * - * @param tcd A point to the TCD structure. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); - -/*! - * @brief Sets the channel link for the eDMA TCD. - * - * This function configures either a minor link or a major link. The minor link means the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - * @param tcd Point to the TCD structure. - * @param type Channel link type, it can be one of: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - */ -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA TCD. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * @param tcd A pointer to the TCD structure. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA TCD. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param tcd A pointer to the TCD structure. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -/*! - * @brief Sets the auto stop request for the eDMA TCD. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param tcd A pointer to the TCD structure. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Channel Transfer Operation - * @{ - */ - -/*! - * @brief Enables the eDMA hardware channel request. - * - * This function enables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SERQ = DMA_SERQ_SERQ(channel); -} - -/*! - * @brief Disables the eDMA hardware channel request. - * - * This function disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CERQ = DMA_CERQ_CERQ(channel); -} - -/*! - * @brief Starts the eDMA transfer by using the software trigger. - * - * This function starts a minor loop transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SSRT = DMA_SSRT_SSRT(channel); -} - -/*! @} */ -/*! - * @name eDMA Channel Status Operation - * @{ - */ - -/*! - * @brief Gets the remaining major loop count from the eDMA current channel TCD. - * - * This function checks the TCD (Task Control Descriptor) status for a specified - * eDMA channel and returns the number of major loop count that has not finished. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return Major loop count which has not been transferred yet for the current TCD. - * @note 1. This function can only be used to get unfinished major loop count of transfer without - * the next TCD, or it might be inaccuracy. - * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while - * the channel is running. - * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO - * register is needed while the eDMA IP does not support getting it while a channel is active. - * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine - * is working with while a channel is running. - * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example - * copied before enabling the channel) is needed. The formula to calculate it is shown below: - * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) - */ -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); - -/*! - * @brief Gets the eDMA channel error status flags. - * - * @param base eDMA peripheral base address. - * @return The mask of error status flags. Users need to use the -* _edma_error_status_flags type to decode the return variables. - */ -static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) -{ - return base->ES; -} - -/*! - * @brief Gets the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return The mask of channel status flags. Users need to use the - * _edma_channel_status_flags type to decode the return variables. - */ -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); - -/*! - * @brief Clears the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of channel status to be cleared. Users need to use - * the defined _edma_channel_status_flags type. - */ -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Transactional Operation - */ - -/*! - * @brief Creates the eDMA handle. - * - * This function is called if using the transactional API for eDMA. This function - * initializes the internal state of the eDMA handle. - * - * @param handle eDMA handle pointer. The eDMA handle stores callback function and - * parameters. - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs the TCDs memory pool into the eDMA handle. - * - * This function is called after the EDMA_CreateHandle to use scatter/gather feature. - * - * @param handle eDMA handle pointer. - * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. - * @param tcdSize The number of TCD slots. - */ -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); - -/*! - * @brief Installs a callback function for the eDMA transfer. - * - * This callback is called in the eDMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle eDMA handle pointer. - * @param callback eDMA callback function pointer. - * @param userData A parameter for the callback function. - */ -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); - -/*! - * @brief Prepares the eDMA transfer structure. - * - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type edma_transfer_t. - * @param srcAddr eDMA transfer source address. - * @param srcWidth eDMA transfer source address width(bytes). - * @param destAddr eDMA transfer destination address. - * @param destWidth eDMA transfer destination address width(bytes). - * @param bytesEachRequest eDMA transfer bytes per channel request. - * @param transferBytes eDMA transfer bytes to be transferred. - * @param type eDMA transfer type. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, the source address must be 4 bytes aligned, or it results in - * source address error (SAE). - */ -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type); - -/*! - * @brief Submits the eDMA transfer request. - * - * This function submits the eDMA transfer request according to the transfer configuration structure. - * If submitting the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle eDMA handle pointer. - * @param config Pointer to eDMA transfer configuration structure. - * @retval kStatus_EDMA_Success It means submit transfer request succeed. - * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); - -/*! - * @brief eDMA starts transfer. - * - * This function enables the channel request. Users can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StartTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA stops transfer. - * - * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() - * again to resume the transfer. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StopTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA aborts transfer. - * - * This function disables the channel request and clear transfer status bits. - * Users can submit another transfer after calling this API. - * - * @param handle DMA handle pointer. - */ -void EDMA_AbortTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA IRQ handler for the current major loop transfer completion. - * - * This function clears the channel major interrupt flag and calls - * the callback function if it is not NULL. - * - * Note: - * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. - * These include the final address adjustments and reloading of the BITER field into the CITER. - * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from - * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). - * - * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. - * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index - * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be - * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have - * been loaded into the eDMA engine at this point already.). - * - * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not - * load a new TCD) from the memory pool to the eDMA engine when major loop completes. - * Therefore, ensure that the header and tcdUsed updated are identical for them. - * tcdUsed are both 0 in this case as no TCD to be loaded. - * - * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for - * further details. - * - * @param handle eDMA handle pointer. - */ -void EDMA_HandleIRQ(edma_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_EDMA_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_flash.c b/third_party/nxp/MKW41Z4/drivers/fsl_flash.c deleted file mode 100644 index ef282ab9d..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_flash.c +++ /dev/null @@ -1,3539 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flash.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name Misc utility defines - * @{ - */ -/*! @brief Alignment utility. */ -#ifndef ALIGN_DOWN -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif -#ifndef ALIGN_UP -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -/*! @brief Join bytes to word utility. */ -#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24) -#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16) -#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8) -#define B1P1(b) ((uint32_t)(b)&0xFFU) -#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16) -#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8) -#define B2P1(b) ((uint32_t)(b)&0xFFFFU) -#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8) -#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU) -#define BYTES_JOIN_TO_WORD_1_3(x, y) (B1P4(x) | B3P1(y)) -#define BYTES_JOIN_TO_WORD_2_2(x, y) (B2P3(x) | B2P1(y)) -#define BYTES_JOIN_TO_WORD_3_1(x, y) (B3P2(x) | B1P1(y)) -#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) (B1P4(x) | B1P3(y) | B2P1(z)) -#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) (B1P4(x) | B2P2(y) | B1P1(z)) -#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) (B2P3(x) | B1P2(y) | B1P1(z)) -#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w)) -/*@}*/ - -/*! - * @name Secondary flash configuration - * @{ - */ -/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (0) -#endif - -/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (0) -#endif -/*@}*/ - -/*! - * @name Flash cache ands speculation control defines - * @{ - */ -#if defined(MCM_PLACR_CFCC_MASK) || defined(MCM_CPCR2_CCBC_MASK) -#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1) -#else -#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0) -#endif -#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK) -#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1) -#else -#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0) -#endif -#if defined(MCM_PLACR_DFCS_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0) -#endif -#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0) -#endif -#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0) -#endif -/*@}*/ - -/*! @brief Data flash IFR map Field*/ -#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U -#endif - -/*! - * @name Reserved FlexNVM size (For a variety of purposes) defines - * @{ - */ -#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU -#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU -/*@}*/ - -/*! - * @name Flash Program Once Field defines - * @{ - */ -#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA -/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ - 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ - 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL -/* FTFL parts(eg. K20) only support 4-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 -#endif -/*@}*/ - -/*! - * @name Flash security status defines - * @{ - */ -#define FLASH_SECURITY_STATE_KEYEN 0x80U -#define FLASH_SECURITY_STATE_UNSECURED 0x02U -#define FLASH_NOT_SECURE 0x01U -#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U -#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U -/*@}*/ - -/*! - * @name Flash controller command numbers - * @{ - */ -#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ -#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ -#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ -#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ -#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ -#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ -#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ -#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ -#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ -#define FTFx_GENERATE_CRC 0x0CU /*!< CRCGEN*/ -#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ -#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ -#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ -#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ -#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ -#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ -#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ -#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ -#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ -#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ -#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ - /*@}*/ - -/*! - * @name Common flash register info defines - * @{ - */ -#if defined(FTFA) -#define FTFx FTFA -#define FTFx_BASE FTFA_BASE -#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFE) -#define FTFx FTFE -#define FTFx_BASE FTFE_BASE -#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFL) -#define FTFx FTFL -#define FTFx_BASE FTFL_BASE -#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#else -#error "Unknown flash controller" -#endif -/*@}*/ - -/*! - * @name Common flash register access info defines - * @{ - */ -#if defined(FTFA_FCCOB_CCOBn_MASK) || defined(FTFE_FCCOB_CCOBn_MASK) || defined(FTFL_FCCOB_CCOBn_MASK) -#define FTFx_FCCOB3_REG (FTFx->FCCOB[0]) -#define FTFx_FCCOB5_REG (FTFx->FCCOB[6]) -#define FTFx_FCCOB6_REG (FTFx->FCCOB[5]) -#define FTFx_FCCOB7_REG (FTFx->FCCOB[4]) -#else -#define FTFx_FCCOB3_REG (FTFx->FCCOB3) -#define FTFx_FCCOB5_REG (FTFx->FCCOB5) -#define FTFx_FCCOB6_REG (FTFx->FCCOB6) -#define FTFx_FCCOB7_REG (FTFx->FCCOB7) -#endif - -#if defined(FTFA_FPROT_PROT_MASK) || defined(FTFE_FPROT_PROT_MASK) || defined(FTFL_FPROT_PROT_MASK) -#define FTFx_FPROT_LOW_REG (FTFx->FPROT[4]) -#define FTFx_FPROTL3_REG (FTFx->FPROT[4]) -#define FTFx_FPROTL2_REG (FTFx->FPROT[5]) -#define FTFx_FPROTL1_REG (FTFx->FPROT[6]) -#define FTFx_FPROTL0_REG (FTFx->FPROT[7]) -#define FTFx_FPROT_HIGH_REG (FTFx->FPROT[0]) -#define FTFx_FPROTH3_REG (FTFx->FPROT[0]) -#define FTFx_FPROTH2_REG (FTFx->FPROT[1]) -#define FTFx_FPROTH1_REG (FTFx->FPROT[2]) -#define FTFx_FPROTH0_REG (FTFx->FPROT[3]) -#else -#define FTFx_FPROT_LOW_REG (FTFx->FPROT3) -#define FTFx_FPROTL3_REG (FTFx->FPROT3) -#define FTFx_FPROTL2_REG (FTFx->FPROT2) -#define FTFx_FPROTL1_REG (FTFx->FPROT1) -#define FTFx_FPROTL0_REG (FTFx->FPROT0) -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -#if defined(FTFA_FPROTS_PROTS_MASK) || defined(FTFE_FPROTS_PROTS_MASK) || defined(FTFL_FPROTS_PROTS_MASK) -#define FTFx_FPROTSH_REG (FTFx->FPROTS[1]) -#define FTFx_FPROTSL_REG (FTFx->FPROTS[0]) -#else -#define FTFx_FPROTSH_REG (FTFx->FPROTSH) -#define FTFx_FPROTSL_REG (FTFx->FPROTSL) -#endif -#endif - -#if defined(FTFA_XACC_XA_MASK) || defined(FTFE_XACC_XA_MASK) || defined(FTFL_XACC_XA_MASK) -#define FTFx_XACCH3_REG (FTFx->XACC[0]) -#define FTFx_XACCL3_REG (FTFx->XACC[4]) -#else -#define FTFx_XACCH3_REG (FTFx->XACCH3) -#define FTFx_XACCL3_REG (FTFx->XACCL3) -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER -#if defined(FTFA_XACCS_XA_S_MASK) || defined(FTFE_XACCS_XA_S_MASK) || defined(FTFL_XACCS_XA_S_MASK) -#define FTFx_XACCSH_REG (FTFx->XACCS[1]) -#define FTFx_XACCSL_REG (FTFx->XACCS[0]) -#else -#define FTFx_XACCSH_REG (FTFx->XACCSH) -#define FTFx_XACCSL_REG (FTFx->XACCSL) -#endif -#endif -/*@}*/ - -/*! - * @brief Enumeration for access segment property. - */ -enum _flash_access_segment_property -{ - kFLASH_AccessSegmentBase = 256UL, -}; - -/*! - * @brief Enumeration for flash config area. - */ -enum _flash_config_area_range -{ - kFLASH_ConfigAreaStart = 0x400U, - kFLASH_ConfigAreaEnd = 0x40FU -}; - -/*! - * @name Flash register access type defines - * @{ - */ -#define FTFx_REG8_ACCESS_TYPE volatile uint8_t * -#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * -/*@}*/ - -/*! - * @brief MCM cache register access info defines. - */ -#if defined(MCM_PLACR_CFCC_MASK) -#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK -#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT -#if defined(MCM) -#define MCM0_CACHE_REG MCM->PLACR -#elif defined(MCM0) -#define MCM0_CACHE_REG MCM0->PLACR -#endif -#if defined(MCM1) -#define MCM1_CACHE_REG MCM1->PLACR -#endif -#elif defined(MCM_CPCR2_CCBC_MASK) -#define MCM_CACHE_CLEAR_MASK MCM_CPCR2_CCBC_MASK -#define MCM_CACHE_CLEAR_SHIFT MCM_CPCR2_CCBC_SHIFT -#if defined(MCM) -#define MCM0_CACHE_REG MCM->CPCR2 -#elif defined(MCM0) -#define MCM0_CACHE_REG MCM0->CPCR2 -#endif -#if defined(MCM1) -#define MCM1_CACHE_REG MCM1->CPCR2 -#endif -#endif - -/*! - * @brief MSCM cache register access info defines. - */ -#if defined(MSCM_OCMDR_OCM1_MASK) -#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCM1_MASK -#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCM1_SHIFT -#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCM1(x) -#elif defined(MSCM_OCMDR_OCMC1_MASK) -#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCMC1_MASK -#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCMC1_SHIFT -#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCMC1(x) -#endif - -/*! - * @brief MSCM prefetch speculation defines. - */ -#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) -#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) - -#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) -#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) - -/*! - * @brief Flash size encoding rule. - */ -#define FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2 (0x00U) -#define FLASH_MEMORY_SIZE_ENCODING_RULE_K3 (0x01U) - -#if defined(K32W042S1M2_M0P_SERIES) || defined(K32W042S1M2_M4_SERIES) -#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K3) -#else -#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2) -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Copy flash_run_command() to RAM*/ -static void copy_flash_run_command(uint32_t *flashRunCommand); -/*! @brief Copy flash_cache_clear_command() to RAM*/ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation); -/*! @brief Check whether flash execute-in-ram functions are ready*/ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ -static status_t flash_command_sequence(flash_config_t *config); - -/*! @brief Perform the cache clear to the flash*/ -void flash_cache_clear(flash_config_t *config); - -/*! @brief Process the cache to the flash*/ -static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process); - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline); -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info); -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info); - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info); -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM -/*! @brief Performs the cache clear to the flash by MCM.*/ -void mcm_flash_cache_clear(flash_config_t *config); -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC -/*! @brief Performs the cache clear to the flash by FMC.*/ -void fmc_flash_cache_clear(void); -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM -/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/ -void mscm_flash_prefetch_speculation_enable(bool enable); -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC -/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ -void fmc_flash_prefetch_speculation_clear(void); -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Access to FTFx->FCCOB */ -volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG; -/*! @brief Access to FTFx->FPROT */ -volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG; -#if defined(FTFx_FPROT_HIGH_REG) -volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG; -volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG; -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief A function pointer used to point to relocated flash_run_command() */ -static void (*callFlashRunCommand)(FTFx_REG8_ACCESS_TYPE ftfx_fstat); -/*! @brief A function pointer used to point to relocated flash_common_bit_operation() */ -static void (*callFlashCommonBitOperation)(FTFx_REG32_ACCESS_TYPE base, - uint32_t bitMask, - uint32_t bitShift, - uint32_t bitValue); - -/*! - * @brief Position independent code of flash_run_command() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat) - * { - * // clear CCIF bit - * *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; - * - * // Check CCIF bit of the flash status register, wait till it is set. - * // IP team indicates that this loop will always complete. - * while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) - * { - * } - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -const static uint16_t s_flashRunCommandFunctionCode[] = { - 0x2180, /* MOVS R1, #128 ; 0x80 */ - 0x7001, /* STRB R1, [R0] */ - /* @4: */ - 0x7802, /* LDRB R2, [R0] */ - 0x420a, /* TST R2, R1 */ - 0xd0fc, /* BEQ.N @4 */ - 0x4770 /* BX LR */ -}; - -/*! - * @brief Position independent code of flash_common_bit_operation() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t - * bitValue) - * { - * if (bitMask) - * { - * uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask); - * *base = (*base & (~bitMask)) | value; - * } - * - * __ISB(); - * __DSB(); - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -const static uint16_t s_flashCommonBitOperationFunctionCode[] = { - 0xb510, /* PUSH {R4, LR} */ - 0x2900, /* CMP R1, #0 */ - 0xd005, /* BEQ.N @12 */ - 0x6804, /* LDR R4, [R0] */ - 0x438c, /* BICS R4, R4, R1 */ - 0x4093, /* LSLS R3, R3, R2 */ - 0x4019, /* ANDS R1, R1, R3 */ - 0x4321, /* ORRS R1, R1, R4 */ - 0x6001, /* STR R1, [R0] */ - /* @12: */ - 0xf3bf, 0x8f6f, /* ISB */ - 0xf3bf, 0x8f4f, /* DSB */ - 0xbd10 /* POP {R4, PC} */ -}; -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) -/*! @brief A static buffer used to hold flash_run_command() */ -static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -/*! @brief A static buffer used to hold flash_common_bit_operation() */ -static uint32_t s_flashCommonBitOperation[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -/*! @brief Flash execute-in-ram function information */ -static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; -#endif - -/*! - * @brief Table of pflash sizes. - * - * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. - * - * The values in this table have been right shifted 10 bits so that they will all fit within - * an 16-bit integer. To get the actual flash density, you must left shift the looked up value - * by 10 bits. - * - * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is - * reserved. - * - * Code to use the table: - * @code - * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; - * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - * @endcode - */ -#if (FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2) -const uint16_t kPFlashDensities[] = { - 8, /* 0x0 - 8192, 8KB */ - 16, /* 0x1 - 16384, 16KB */ - 24, /* 0x2 - 24576, 24KB */ - 32, /* 0x3 - 32768, 32KB */ - 48, /* 0x4 - 49152, 48KB */ - 64, /* 0x5 - 65536, 64KB */ - 96, /* 0x6 - 98304, 96KB */ - 128, /* 0x7 - 131072, 128KB */ - 192, /* 0x8 - 196608, 192KB */ - 256, /* 0x9 - 262144, 256KB */ - 384, /* 0xa - 393216, 384KB */ - 512, /* 0xb - 524288, 512KB */ - 768, /* 0xc - 786432, 768KB */ - 1024, /* 0xd - 1048576, 1MB */ - 1536, /* 0xe - 1572864, 1.5MB */ - /* 2048, 0xf - 2097152, 2MB */ -}; -#elif(FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K3) -const uint16_t kPFlashDensities[] = { - 0, /* 0x0 - undefined */ - 0, /* 0x1 - undefined */ - 0, /* 0x2 - undefined */ - 0, /* 0x3 - undefined */ - 0, /* 0x4 - undefined */ - 0, /* 0x5 - undefined */ - 0, /* 0x6 - undefined */ - 0, /* 0x7 - undefined */ - 0, /* 0x8 - undefined */ - 0, /* 0x9 - undefined */ - 256, /* 0xa - 262144, 256KB */ - 0, /* 0xb - undefined */ - 1024, /* 0xc - 1048576, 1MB */ - 0, /* 0xd - undefined */ - 0, /* 0xe - undefined */ - 0, /* 0xf - undefined */ -}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t FLASH_Init(flash_config_t *config) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) - uint32_t flashDensity; - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE1_PFSIZE_MASK) >> SIM_FCFG1_CORE1_PFSIZE_SHIFT; - if (pfsize == 0xf) - { - flashDensity = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - config->PFlashTotalSize = flashDensity; -#else - /* Unused code to solve MISRA-C issue*/ - config->PFlashBlockBase = kPFlashDensities[0]; - config->PFlashTotalSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; -#endif - config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS; - config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT; - config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - { - uint32_t flashDensity; - -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE0_PFSIZE_MASK) >> SIM_FCFG1_CORE0_PFSIZE_SHIFT; -#elif defined(SIM_FCFG1_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; -#else -#error "Unknown flash size" -#endif - /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. - * We just use the pre-defined flash size in feature file here to support pre-production parts */ - if (pfsize == 0xf) - { - flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - - /* fill out a few of the structure members */ - config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; - config->PFlashTotalSize = flashDensity; - config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; - config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE; - } - - { -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSSS; - config->PFlashAccessSegmentCount = FTFx->FACSNS; - } - else -#endif - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS; - config->PFlashAccessSegmentCount = FTFx->FACSN; - } -#else - config->PFlashAccessSegmentSize = 0; - config->PFlashAccessSegmentCount = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - } - - config->PFlashCallback = NULL; - -/* copy required flash commands to RAM */ -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) - if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) - { - s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; - s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; - s_flashExecuteInRamFunctionInfo.flashCommonBitOperation = s_flashCommonBitOperation; - config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; - FLASH_PrepareExecuteInRamFunctions(config); - } -#endif - - config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; - config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - { - status_t returnCode; - config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; - returnCode = flash_update_flexnvm_memory_partition_status(config); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - } -#endif - - return kStatus_FLASH_Success; -} - -status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - config->PFlashCallback = callback; - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); - copy_flash_common_bit_operation(flashExecuteInRamFunctionInfo->flashCommonBitOperation); - flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all flash blocks */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} - -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; - uint32_t endAddress; /* storing end address */ - uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectorCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - - /* calculating Flash end address */ - endAddress = start + lengthInBytes - 1; - - /* re-calculate the endAddress and align it to the start of the next sector - * which will be used in the comparison below */ - if (endAddress % sectorSize) - { - numberOfSectors = endAddress / sectorSize + 1; - endAddress = numberOfSectors * sectorSize - 1; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* the start address will increment to the next sector address - * until it reaches the endAdddress */ - while (start <= endAddress) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - /* checking the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* Increment to the next sector */ - start += sectorSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD -status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Prepare passing parameter to erase all flash blocks (unsecure). */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all unsecure command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ - -status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all execute-only segments - * 1st element for the FCCOB register */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.blockWriteUnitSize); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - while (lengthInBytes > 0) - { - /* preparing passing parameter to program the flash block */ - kFCCOBx[1] = *src++; - if (4 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); - } - else if (8 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[2] = *src++; - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* update start address for next iteration */ - start += flashOperationInfo.blockWriteUnitSize; - - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.blockWriteUnitSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (src == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); - - kFCCOBx[1] = *src; - -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - kFCCOBx[2] = *(src + 1); - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD -status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - bool needSwitchFlexRamMode = false; -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsRamError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - while (lengthInBytes > 0) - { - /* Make sure the write operation doesn't span two sectors */ - uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); - uint32_t lengthTobeProgrammedOfCurrentSector; - uint32_t currentOffset = 0; - - if (endAddressOfCurrentSector == start) - { - endAddressOfCurrentSector += sectorSize; - } - - if (lengthInBytes + start > endAddressOfCurrentSector) - { - lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; - } - else - { - lengthTobeProgrammedOfCurrentSector = lengthInBytes; - } - - /* Program Current Sector */ - while (lengthTobeProgrammedOfCurrentSector > 0) - { - /* Make sure the program size doesn't exceeds Acceleration RAM size */ - uint32_t programSizeOfCurrentPass; - uint32_t numberOfPhases; - - if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize) - { - programSizeOfCurrentPass = kFLASH_AccelerationRamSize; - } - else - { - programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; - } - - /* Copy data to FlexRAM */ - memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); - /* Set start address of the data to be programmed */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); - /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ - numberOfPhases = programSizeOfCurrentPass / flashOperationInfo.sectionCmdAddressAligment; - - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); - - /* Peform command sequence */ - returnCode = flash_command_sequence(config); - - /* calling flash callback function if it is available */ - if (config->PFlashCallback) - { - config->PFlashCallback(); - } - - if (returnCode != kStatus_FLASH_Success) - { - flash_cache_clear(config); - return returnCode; - } - - lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; - currentOffset += programSizeOfCurrentPass; - } - - src += currentOffset / 4; - start += currentOffset; - lengthInBytes -= currentOffset; - } - - flash_cache_clear(config); - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Restore function of FlexRAM if needed. */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsEepromError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - bool needSwitchFlexRamMode = false; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Validates the range of the given address */ - if ((start < config->FlexRAMBlockBase) || - ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) - { - return kStatus_FLASH_AddressError; - } - - returnCode = kStatus_FLASH_Success; - - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsEepromError; - } - } - - /* Write data to FlexRAM when it is used as EEPROM emulator */ - while (lengthInBytes > 0) - { - if ((!(start & 0x3U)) && (lengthInBytes >= 4)) - { - *(uint32_t *)start = *(uint32_t *)src; - start += 4; - src += 4; - lengthInBytes -= 4; - } - else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) - { - *(uint16_t *)start = *(uint16_t *)src; - start += 2; - src += 2; - lengthInBytes -= 2; - } - else - { - *(uint8_t *)start = *src; - start += 1; - src += 1; - lengthInBytes -= 1; - } - /* Wait till EEERDY bit is set */ - while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - } - - /* Check for protection violation error */ - if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - } - - /* Switch function of FlexRAM if needed */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsRamError; - } - } - - return returnCode; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -status_t FLASH_ReadResource( - flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = - flash_check_resource_range(start, lengthInBytes, flashOperationInfo.resourceCmdAddressAligment, option); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - while (lengthInBytes > 0) - { - /* preparing passing parameter */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); - if (flashOperationInfo.resourceCmdAddressAligment == 4) - { - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success != returnCode) - { - break; - } - - /* fetch data */ - *dst++ = kFCCOBx[1]; - if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - *dst++ = kFCCOBx[2]; - } - /* update start address for next iteration */ - start += flashOperationInfo.resourceCmdAddressAligment; - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.resourceCmdAddressAligment; - } - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success == returnCode) - { - *dst = kFCCOBx[1]; -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - *(dst + 1) = kFCCOBx[2]; - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - } - - return returnCode; -} - -status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) -{ - /* store data read from flash register */ - uint8_t registerValue; - - if ((config == NULL) || (state == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* check the status of the flash security bits in the security register */ - if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) - { - /* Flash in unsecured state */ - *state = kFLASH_SecurityStateNotSecure; - } - else - { - /* Flash in secured state - * check for backdoor key security enable bit */ - if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) - { - /* Backdoor key security enabled */ - *state = kFLASH_SecurityStateBackdoorEnabled; - } - else - { - /* Backdoor key security disabled */ - *state = kFLASH_SecurityStateBackdoorDisabled; - } - } - - return (kStatus_FLASH_Success); -} - -status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) -{ - uint8_t registerValue; /* registerValue */ - status_t returnCode; /* return code variable */ - - if ((config == NULL) || (backdoorKey == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* set the default return code as kStatus_Success */ - returnCode = kStatus_FLASH_Success; - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* Check to see if flash is in secure state (any state other than 0x2) - * If not, then skip this since flash is not secure */ - if (0x02 != (registerValue & 0x03)) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) -{ - /* Check arguments. */ - uint32_t blockSize; - flash_operation_config_t flashOperationInfo; - uint32_t nextBlockStartAddress; - uint32_t remainingBytes; - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - start = flashOperationInfo.convertedAddress; - blockSize = flashOperationInfo.activeBlockSize; - - nextBlockStartAddress = ALIGN_UP(start, blockSize); - if (nextBlockStartAddress == start) - { - nextBlockStartAddress += blockSize; - } - - remainingBytes = lengthInBytes; - - while (remainingBytes) - { - uint32_t numberOfPhrases; - uint32_t verifyLength = nextBlockStartAddress - start; - if (verifyLength > remainingBytes) - { - verifyLength = remainingBytes; - } - - numberOfPhrases = verifyLength / flashOperationInfo.sectionCmdAddressAligment; - - /* Fill in verify section command parameters. */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - if (returnCode) - { - return returnCode; - } - - remainingBytes -= verifyLength; - start += verifyLength; - nextBlockStartAddress += blockSize; - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint32_t *expectedData, - flash_margin_value_t margin, - uint32_t *failedAddress, - uint32_t *failedData) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (expectedData == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.checkCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - while (lengthInBytes) - { - /* preparing passing parameter to program check the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); - kFCCOBx[2] = *expectedData; - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - if (failedAddress) - { - *failedAddress = start; - } - if (failedData) - { - *failedData = 0; - } - break; - } - - lengthInBytes -= flashOperationInfo.checkCmdAddressAligment; - expectedData += flashOperationInfo.checkCmdAddressAligment / sizeof(*expectedData); - start += flashOperationInfo.checkCmdAddressAligment; - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify erase all execute-only segments command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_IsProtected(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_protection_state_t *protection_state) -{ - uint32_t endAddress; /* end address for protection check */ - uint32_t regionCheckedCounter; /* increments each time the flash address was checked for - * protection status */ - uint32_t regionCounter; /* incrementing variable used to increment through the flash - * protection regions */ - uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ - - uint8_t flashRegionProtectStatus[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT]; /* array of the protection - * status for each - * protection region */ - uint32_t flashRegionAddress[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT + - 1]; /* array of the start addresses for each flash - * protection region. Note this is REGION_COUNT+1 - * due to requiring the next start address after - * the end of flash for loop-check purposes below */ - flash_protection_config_t flashProtectionInfo; /* flash protection information */ - status_t returnCode; - - if (protection_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - - /* Get necessary flash protection information. */ - returnCode = flash_get_protection_info(config, &flashProtectionInfo); - if (returnCode) - { - return returnCode; - } - - /* calculating Flash end address */ - endAddress = start + lengthInBytes; - - /* populate the flashRegionAddress array with the start address of each flash region */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - - /* populate up to 33rd element of array, this is the next address after end of flash array */ - while (regionCounter <= flashProtectionInfo.regionCount) - { - flashRegionAddress[regionCounter] = - flashProtectionInfo.regionBase + flashProtectionInfo.regionSize * regionCounter; - regionCounter++; - } - - /* populate flashRegionProtectStatus array with status information - * Protection status for each region is stored in the FPROT[3:0] registers - * Each bit represents one region of flash - * 4 registers * 8-bits-per-register = 32-bits (32-regions) - * The convention is: - * FPROT3[bit 0] is the first protection region (start of flash memory) - * FPROT0[bit 7] is the last protection region (end of flash memory) - * regionCounter is used to determine which FPROT[3:0] register to check for protection status - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - while (regionCounter < flashProtectionInfo.regionCount) - { -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u); - } - else - { - break; - } - } - else -#endif - { - /* Note: So far protection region count may be 16/20/24/32/64 */ - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u); - } -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 16) -#if (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) - else if ((regionCounter >= 16) && (regionCounter < 20)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#else - else if ((regionCounter >= 16) && (regionCounter < 24)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#endif /* (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) */ -#endif -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 24) - else if ((regionCounter >= 24) && (regionCounter < 32)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u); - } -#endif -#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && \ - (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 64) - else if (regionCounter < 40) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u); - } - else if (regionCounter < 48) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u); - } - else if (regionCounter < 56) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u); - } - else if (regionCounter < 64) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u); - } -#endif - else - { - break; - } - } - - regionCounter++; - } - - /* loop through the flash regions and check - * desired flash address range for protection status - * loop stops when it is detected that start has exceeded the endAddress */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - regionCheckedCounter = 0; - protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ - while (start < endAddress) - { - /* check to see if the address falls within this protection region - * Note that if the entire flash is to be checked, the last protection - * region checked would consist of the last protection start address and - * the start address following the end of flash */ - if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) - { - /* increment regionCheckedCounter to indicate this region was checked */ - regionCheckedCounter++; - - /* check the protection status of this region - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - if (!flashRegionProtectStatus[regionCounter]) - { - /* increment protectStatusCounter to indicate this region is protected */ - protectStatusCounter++; - } - start += flashProtectionInfo.regionSize; /* increment to an address within the next region */ - } - regionCounter++; /* increment regionCounter to check for the next flash protection region */ - } - - /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ - if (protectStatusCounter == 0) - { - *protection_state = kFLASH_ProtectionStateUnprotected; - } - /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ - else if (protectStatusCounter == regionCheckedCounter) - { - *protection_state = kFLASH_ProtectionStateProtected; - } - /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed - * In other words, some regions are protected while others are unprotected */ - else - { - *protection_state = kFLASH_ProtectionStateMixed; - } - - return (returnCode); -} - -status_t FLASH_IsExecuteOnly(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_execute_only_access_state_t *access_state) -{ -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - flash_access_config_t flashAccessInfo; /* flash Execute-Only information */ -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - status_t returnCode; - - if (access_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - /* Get necessary flash Execute-Only information. */ - returnCode = flash_get_access_info(config, &flashAccessInfo); - if (returnCode) - { - return returnCode; - } - - { - uint32_t executeOnlySegmentCounter = 0; - - /* calculating end address */ - uint32_t endAddress = start + lengthInBytes; - - /* Aligning start address and end address */ - uint32_t alignedStartAddress = ALIGN_DOWN(start, flashAccessInfo.SegmentSize); - uint32_t alignedEndAddress = ALIGN_UP(endAddress, flashAccessInfo.SegmentSize); - - uint32_t segmentIndex = 0; - uint32_t maxSupportedExecuteOnlySegmentCount = - (alignedEndAddress - alignedStartAddress) / flashAccessInfo.SegmentSize; - - while (start < endAddress) - { - uint32_t xacc; - - segmentIndex = (start - flashAccessInfo.SegmentBase) / flashAccessInfo.SegmentSize; - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size. - */ - if (segmentIndex < 8) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG; - segmentIndex -= 8; - } - else - { - break; - } - } - else -#endif - { - /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size. - */ - if (segmentIndex < 32) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG; - segmentIndex -= 32; - } - else - { - break; - } - } - - /* Determine if this address range is in a execute-only protection flash segment. */ - if ((~xacc) & (1u << segmentIndex)) - { - executeOnlySegmentCounter++; - } - - start += flashAccessInfo.SegmentSize; - } - - if (executeOnlySegmentCounter < 1u) - { - *access_state = kFLASH_AccessStateUnLimited; - } - else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) - { - *access_state = kFLASH_AccessStateMixed; - } - else - { - *access_state = kFLASH_AccessStateExecuteOnly; - } - } -#else - *access_state = kFLASH_AccessStateUnLimited; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - - return (returnCode); -} - -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - if ((config == NULL) || (value == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { - case kFLASH_PropertyPflashSectorSize: - *value = config->PFlashSectorSize; - break; - - case kFLASH_PropertyPflashTotalSize: - *value = config->PFlashTotalSize; - break; - - case kFLASH_PropertyPflashBlockSize: - *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; - break; - - case kFLASH_PropertyPflashBlockCount: - *value = (uint32_t)config->PFlashBlockCount; - break; - - case kFLASH_PropertyPflashBlockBaseAddr: - *value = config->PFlashBlockBase; - break; - - case kFLASH_PropertyPflashFacSupport: -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) - *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; -#else - *value = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - break; - - case kFLASH_PropertyPflashAccessSegmentSize: - *value = config->PFlashAccessSegmentSize; - break; - - case kFLASH_PropertyPflashAccessSegmentCount: - *value = config->PFlashAccessSegmentCount; - break; - - case kFLASH_PropertyFlexRamBlockBaseAddr: - *value = config->FlexRAMBlockBase; - break; - - case kFLASH_PropertyFlexRamTotalSize: - *value = config->FlexRAMTotalSize; - break; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - break; - case kFLASH_PropertyDflashTotalSize: - *value = config->DFlashTotalSize; - break; - case kFLASH_PropertyDflashBlockSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; - break; - case kFLASH_PropertyDflashBlockCount: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - break; - case kFLASH_PropertyDflashBlockBaseAddr: - *value = config->DFlashBlockBase; - break; - case kFLASH_PropertyEepromTotalSize: - *value = config->EEpromTotalSize; - break; -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - - default: /* catch inputs that are not recognized */ - return kStatus_FLASH_UnknownProperty; - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value) -{ - status_t status = kStatus_FLASH_Success; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - case kFLASH_PropertyFlashMemoryIndex: - if ((value != (uint32_t)kFLASH_MemoryIndexPrimaryFlash) && - (value != (uint32_t)kFLASH_MemoryIndexSecondaryFlash)) - { - return kStatus_FLASH_InvalidPropertyValue; - } - config->FlashMemoryIndex = (uint8_t)value; - break; -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - - case kFLASH_PropertyFlashCacheControllerIndex: - if ((value != (uint32_t)kFLASH_CacheControllerIndexForCore0) && - (value != (uint32_t)kFLASH_CacheControllerIndexForCore1)) - { - return kStatus_FLASH_InvalidPropertyValue; - } - config->FlashCacheControllerIndex = (uint8_t)value; - break; - - case kFLASH_PropertyPflashSectorSize: - case kFLASH_PropertyPflashTotalSize: - case kFLASH_PropertyPflashBlockSize: - case kFLASH_PropertyPflashBlockCount: - case kFLASH_PropertyPflashBlockBaseAddr: - case kFLASH_PropertyPflashFacSupport: - case kFLASH_PropertyPflashAccessSegmentSize: - case kFLASH_PropertyPflashAccessSegmentCount: - case kFLASH_PropertyFlexRamBlockBaseAddr: - case kFLASH_PropertyFlexRamTotalSize: -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - case kFLASH_PropertyDflashTotalSize: - case kFLASH_PropertyDflashBlockSize: - case kFLASH_PropertyDflashBlockCount: - case kFLASH_PropertyDflashBlockBaseAddr: - case kFLASH_PropertyEepromTotalSize: -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - status = kStatus_FLASH_ReadOnlyProperty; - break; - default: /* catch inputs that are not recognized */ - status = kStatus_FLASH_UnknownProperty; - break; - } - - return status; -} - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) -{ - status_t status; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - status = flasn_check_flexram_function_option_range(option); - if (status != kStatus_FLASH_Success) - { - return status; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -status_t FLASH_SwapControl(flash_config_t *config, - uint32_t address, - flash_swap_control_option_t option, - flash_swap_state_config_t *returnInfo) -{ - status_t returnCode; - - if ((config == NULL) || (returnInfo == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) - { - return kStatus_FLASH_AlignmentError; - } - - /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ - if ((address >= (config->PFlashTotalSize / 2)) || - ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd))) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - /* Check the option. */ - returnCode = flash_check_swap_control_option(option); - if (returnCode) - { - return returnCode; - } - - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - - returnCode = flash_command_sequence(config); - - returnInfo->flashSwapState = (flash_swap_state_t)FTFx_FCCOB5_REG; - returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB6_REG; - returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB7_REG; - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) -{ - flash_swap_state_config_t returnInfo; - status_t returnCode; - - memset(&returnInfo, 0xFFU, sizeof(returnInfo)); - - do - { - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - if (kFLASH_SwapFunctionOptionDisable == option) - { - if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled) - { - return kStatus_FLASH_Success; - } - else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized) - { - /* The swap system changed to the DISABLED state with Program flash block 0 - * located at relative flash address 0x0_0000 */ - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo); - } - else - { - /* Swap disable should be requested only when swap system is in the uninitialized state */ - return kStatus_FLASH_SwapSystemNotInUninitialized; - } - } - else - { - /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, - * the swap procedure should be Uninitialized -> Update-Erased -> Complete. - * After the first swap has been completed, the flash swap inidicator address cannot be modified - * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> - * Complete. */ - switch (returnInfo.flashSwapState) - { - case kFLASH_SwapStateUninitialized: - /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo); - break; - case kFLASH_SwapStateReady: - /* Validate whether the address provided to the swap system is matched to - * swap indicator address in the IFR */ - returnCode = flash_validate_swap_indicator_address(config, address); - if (returnCode == kStatus_FLASH_Success) - { - /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo); - } - break; - case kFLASH_SwapStateUpdate: - /* If current swap mode is Update, Erase indicator sector in non active block - * to proceed swap system to update-erased state */ - returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), - FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey); - break; - case kFLASH_SwapStateUpdateErased: - /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo); - break; - case kFLASH_SwapStateComplete: - break; - case kFLASH_SwapStateDisabled: - /* When swap system is in disabled state, We need to clear swap system back to uninitialized - * by issuing EraseAllBlocks command */ - returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; - break; - default: - returnCode = kStatus_FLASH_InvalidArgument; - break; - } - } - if (returnCode != kStatus_FLASH_Success) - { - break; - } - } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option))); - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD -status_t FLASH_ProgramPartition(flash_config_t *config, - flash_partition_flexram_load_option_t option, - uint32_t eepromDataSizeCode, - uint32_t flexnvmPartitionCode) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 - * or it will cause access error. */ - /* eepromDataSizeCode &= 0x3FU; */ - /* flexnvmPartitionCode &= 0x0FU; */ - - /* preparing passing parameter to program the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be updated by program partition command during reset sequence, - * so we just set reserved values for partitioned FlexNVM size here */ - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ - -status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - *kFPROTSL = protectStatus->valueLow32b.prots16b.protsl; - if (protectStatus->valueLow32b.prots16b.protsl != *kFPROTSL) - { - return kStatus_FLASH_CommandFailure; - } - - *kFPROTSH = protectStatus->valueLow32b.prots16b.protsh; - if (protectStatus->valueLow32b.prots16b.protsh != *kFPROTSH) - { - return kStatus_FLASH_CommandFailure; - } - } - else -#endif - { - *kFPROTL = protectStatus->valueLow32b.protl32b; - if (protectStatus->valueLow32b.protl32b != *kFPROTL) - { - return kStatus_FLASH_CommandFailure; - } - -#if defined(FTFx_FPROT_HIGH_REG) - *kFPROTH = protectStatus->valueHigh32b.proth32b; - if (protectStatus->valueHigh32b.proth32b != *kFPROTH) - { - return kStatus_FLASH_CommandFailure; - } -#endif - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - protectStatus->valueLow32b.prots16b.protsl = *kFPROTSL; - protectStatus->valueLow32b.prots16b.protsh = *kFPROTSH; - } - else -#endif - { - protectStatus->valueLow32b.protl32b = *kFPROTL; -#if defined(FTFx_FPROT_HIGH_REG) - protectStatus->valueHigh32b.proth32b = *kFPROTH; -#endif - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FDPROT = protectStatus; - - if (FTFx->FDPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FDPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FEPROT = protectStatus; - - if (FTFx->FEPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FEPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - void (*flashCommonBitOperationCallback)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue); - uint32_t flashCommonBitOperationBuffer[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; - - assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - memcpy((void *)flashCommonBitOperationBuffer, (void *)s_flashCommonBitOperationFunctionCode, - sizeof(s_flashCommonBitOperationFunctionCode)); - flashCommonBitOperationCallback = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue))((uint32_t)flashCommonBitOperationBuffer + 1); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM - { - FTFx_REG32_ACCESS_TYPE regBase; -#if defined(MCM) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR; -#elif defined(MCM0) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR; -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, MCM_PLACR_DFCS_MASK, MCM_PLACR_DFCS_SHIFT, 1U); -#else - *regBase |= MCM_PLACR_DFCS_MASK; -#endif - } - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, MCM_PLACR_DFCS_MASK, MCM_PLACR_DFCS_SHIFT, 0U); -#else - *regBase &= ~MCM_PLACR_DFCS_MASK; -#endif - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS_SHIFT, 1U); -#else - *regBase |= MCM_PLACR_EFDS_MASK; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS_SHIFT, 0U); -#else - *regBase &= ~MCM_PLACR_EFDS_MASK; -#endif - } - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t b0dpeMask, b0ipeMask; -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - uint32_t b0dpeShift, b0ipeShift; -#endif -#if defined(FMC_PFB01CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - b0dpeShift = FMC_PFB01CR_B0DPE_SHIFT; - b0ipeShift = FMC_PFB01CR_B0IPE_SHIFT; -#endif -#elif defined(FMC_PFB0CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - b0dpeShift = FMC_PFB0CR_B0DPE_SHIFT; - b0ipeShift = FMC_PFB0CR_B0IPE_SHIFT; -#endif -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, b0ipeMask, b0ipeShift, 1U); -#else - *regBase |= b0ipeMask; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, b0ipeMask, b0ipeShift, 0U); -#else - *regBase &= ~b0ipeMask; -#endif - } - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, b0dpeMask, b0dpeShift, 1U); -#else - *regBase |= b0dpeMask; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, b0dpeMask, b0dpeShift, 0U); -#else - *regBase &= ~b0dpeMask; -#endif - } - -/* Invalidate Prefetch Speculation Buffer */ -#if defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; -#endif - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t flashSpeculationMask, dataPrefetchMask; -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - uint32_t flashSpeculationShift, dataPrefetchShift; - flashSpeculationShift = MSCM_OCMDR_OCMC1_DFCS_SHIFT; - dataPrefetchShift = MSCM_OCMDR_OCMC1_DFDS_SHIFT; -#endif - - regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, flashSpeculationMask, flashSpeculationShift, 1U); -#else - *regBase |= flashSpeculationMask; -#endif - } - } - else - { - *regBase &= ~flashSpeculationMask; - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, dataPrefetchMask, dataPrefetchShift, 0U); -#else - *regBase &= ~dataPrefetchMask; -#endif - } - else - { -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback(regBase, dataPrefetchMask, dataPrefetchShift, 1U); -#else - *regBase |= dataPrefetchMask; -#endif - } - } - } -#else -#if FLASH_DRIVER_IS_FLASH_RESIDENT && (!(defined(FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH) && \ - FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH)) - flashCommonBitOperationCallback((FTFx_REG32_ACCESS_TYPE)0, 0, 0, 0); -#endif -#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ - memset(speculationStatus, 0, sizeof(flash_prefetch_speculation_status_t)); - - /* Assuming that all speculation options are enabled. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionEnable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionEnable; - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM - { - uint32_t value; -#if defined(MCM) - value = MCM->PLACR; -#elif defined(MCM0) - value = MCM0->PLACR; -#endif - if (value & MCM_PLACR_DFCS_MASK) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (!(value & MCM_PLACR_EFDS_MASK)) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - { - uint32_t value; - uint32_t b0dpeMask, b0ipeMask; -#if defined(FMC_PFB01CR_B0DPE_MASK) - value = FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#elif defined(FMC_PFB0CR_B0DPE_MASK) - value = FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#endif - if (!(value & b0dpeMask)) - { - /* Do not prefetch in response to data references. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - if (!(value & b0ipeMask)) - { - /* Do not prefetch in response to instruction fetches. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - { - uint32_t value; - uint32_t flashSpeculationMask, dataPrefetchMask; - value = MSCM->OCMDR[0]; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (value & flashSpeculationMask) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (value & dataPrefetchMask) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#endif - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! - * @brief Copy PIC of flash_run_command() to RAM - */ -static void copy_flash_run_command(uint32_t *flashRunCommand) -{ - assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode)); - callFlashRunCommand = (void (*)(FTFx_REG8_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! - * @brief Flash Command Sequence - * - * This function is used to perform the command write sequence to the flash. - * - * @param driver Pointer to storage for the driver runtime state. - * @return An error code or kStatus_FLASH_Success - */ -static status_t flash_command_sequence(flash_config_t *config) -{ - uint8_t registerValue; - -#if FLASH_DRIVER_IS_FLASH_RESIDENT - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return returnCode; - } - - /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using - * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() - * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ - callFlashRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT)); -#else - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - /* clear CCIF bit */ - FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; - - /* Check CCIF bit of the flash status register, wait till it is set. - * IP team indicates that this loop will always complete. */ - while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) - { - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - - /* Check error bits */ - /* Get flash status register value */ - registerValue = FTFx->FSTAT; - - /* checking access error */ - if (registerValue & FTFx_FSTAT_ACCERR_MASK) - { - return kStatus_FLASH_AccessError; - } - /* checking protection error */ - else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - /* checking MGSTAT0 non-correctable error */ - else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) - { - return kStatus_FLASH_CommandFailure; - } - else - { - return kStatus_FLASH_Success; - } -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! - * @brief Copy PIC of flash_common_bit_operation() to RAM - * - */ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation) -{ - assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashCommonBitOperation, (void *)s_flashCommonBitOperationFunctionCode, - sizeof(s_flashCommonBitOperationFunctionCode)); - callFlashCommonBitOperation = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue))((uint32_t)flashCommonBitOperation + 1); - /* Workround for some devices which doesn't need this function */ - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)0, 0, 0, 0); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM -/*! @brief Performs the cache clear to the flash by MCM.*/ -void mcm_flash_cache_clear(flash_config_t *config) -{ - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG; - -#if defined(MCM0) && defined(MCM1) - if (config->FlashCacheControllerIndex == (uint8_t)kFLASH_CacheControllerIndexForCore1) - { - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG; - } -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT - callFlashCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U); -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ - *regBase |= MCM_CACHE_CLEAR_MASK; - - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC -/*! @brief Performs the cache clear to the flash by FMC.*/ -void fmc_flash_cache_clear(void) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_CINV_WAY_MASK, FMC_PFB01CR_CINV_WAY_SHIFT, 0xFU); -#else - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY_SHIFT, 0xFU); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); -#else - FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); -#endif - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM -/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/ -void mscm_flash_prefetch_speculation_enable(bool enable) -{ - uint8_t setValue; - if (enable) - { - setValue = 0x0U; - } - else - { - setValue = 0x3U; - } - -/* The OCMDR[0] is always used to prefetch main Pflash*/ -/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash. - * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0], MSCM_SPECULATION_DISABLE_MASK, - MSCM_SPECULATION_DISABLE_SHIFT, setValue); -#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[1], MSCM_SPECULATION_DISABLE_MASK, - MSCM_SPECULATION_DISABLE_SHIFT, setValue); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ - MSCM->OCMDR[0] |= MSCM_SPECULATION_DISABLE(setValue); - - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH - MSCM->OCMDR[1] |= MSCM_SPECULATION_DISABLE(setValue); - - /* Each cahce clear instaruction should be followed by below code*/ - __ISB(); - __DSB(); -#endif - -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC -/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ -void fmc_flash_prefetch_speculation_clear(void) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; -#if defined(FMC_PFB0CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_INV_MASK, FMC_PFB0CR_S_INV_SHIFT, 1U); -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV_SHIFT, 1U); -#elif defined(FMC_PFB01CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_INV_MASK, FMC_PFB01CR_S_INV_SHIFT, 1U); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ -#if defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; -#elif defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#endif - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ - -/*! - * @brief Flash Cache Clear - * - * This function is used to perform the cache and prefetch speculation clear to the flash. - */ -void flash_cache_clear(flash_config_t *config) -{ - flash_cache_clear_process(config, kFLASH_CacheClearProcessPost); -} - -/*! - * @brief Flash Cache Clear Process - * - * This function is used to perform the cache and prefetch speculation clear process to the flash. - */ -static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return; - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - - /* We pass the ftfx register address as a parameter to flash_common_bit_operation() instead of using - * pre-processed MACROs or a global variable in flash_common_bit_operation() - * to make sure that flash_common_bit_operation() will be compiled into position-independent code (PIC). */ - if (process == kFLASH_CacheClearProcessPost) - { -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM - mcm_flash_cache_clear(config); -#endif -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC - fmc_flash_cache_clear(); -#endif -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - mscm_flash_prefetch_speculation_enable(true); -#endif -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - fmc_flash_prefetch_speculation_clear(); -#endif - } - if (process == kFLASH_CacheClearProcessPre) - { -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - mscm_flash_prefetch_speculation_enable(false); -#endif - } -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Check whether flash execute-in-ram functions are ready */ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - if ((config->flashExecuteInRamFunctionInfo) && - (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_ExecuteInRamFunctionNotReady; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Verify the start and length are alignmentBaseline aligned. */ - if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - /* check for valid range of the target addresses */ - if ( -#if FLASH_SSD_IS_FLEXNVM_ENABLED - ((startAddress >= config->DFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))) || -#endif - ((startAddress >= config->PFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize)))) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_AddressError; -} - -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_operation_config_t)); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) - { - /* When required by the command, address bit 23 selects between program flash memory - * (=0) and data flash memory (=1).*/ - info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; - info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - - info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; - info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; - } - else -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - { - info->convertedAddress = address - config->PFlashBlockBase; - info->activeSectorSize = config->PFlashSectorSize; - info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { -#if FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER || FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - /* When required by the command, address bit 23 selects between main flash memory - * (=0) and secondary flash memory (=1).*/ - info->convertedAddress += 0x800000U; -#endif - info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - { - info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE; - } - - info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; - } - - return kStatus_FLASH_Success; -} - -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key) -{ - /* Validate the user key */ - if (key != kFLASH_ApiEraseKey) - { - return kStatus_FLASH_EraseKeyError; - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) -{ - struct - { - uint32_t reserved0; - uint8_t FlexNVMPartitionCode; - uint8_t EEPROMDataSetSize; - uint16_t reserved1; - } dataIFRReadOut; - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD - /* Get FlexNVM memory partition info from data flash IFR */ - returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, - sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_PartitionStatusUpdateFailure; - } -#else -#error "Cannot get FlexNVM memory partition info" -#endif - - /* Fill out partitioned EEPROM size */ - dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; - switch (dataIFRReadOut.EEPROMDataSetSize) - { - case 0x00U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; - break; - case 0x01U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; - break; - case 0x02U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; - break; - case 0x03U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; - break; - case 0x04U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; - break; - case 0x05U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; - break; - case 0x06U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; - break; - case 0x07U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; - break; - case 0x08U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; - break; - case 0x09U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; - break; - case 0x0AU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; - break; - case 0x0BU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; - break; - case 0x0CU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; - break; - case 0x0DU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; - break; - case 0x0EU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; - break; - case 0x0FU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; - break; - default: - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - break; - } - - /* Fill out partitioned DFlash size */ - dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; - switch (dataIFRReadOut.FlexNVMPartitionCode) - { - case 0x00U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ - break; - case 0x01U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ - break; - case 0x02U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ - break; - case 0x03U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ - break; - case 0x04U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ - break; - case 0x05U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ - break; - case 0x06U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ - break; - case 0x07U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ - break; - case 0x08U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ - break; - case 0x09U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ - break; - case 0x0AU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ - break; - case 0x0BU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ - break; - case 0x0CU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ - break; - case 0x0DU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ - break; - case 0x0EU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ - break; - case 0x0FU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ - break; - default: - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; - break; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option) -{ - status_t status; - uint32_t maxReadbleAddress; - - if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - status = kStatus_FLASH_Success; - - maxReadbleAddress = start + lengthInBytes - 1; - if (option == kFLASH_ResourceOptionVersionId) - { - if ((start != kFLASH_ResourceRangeVersionIdStart) || - ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd)) - { - status = kStatus_FLASH_InvalidArgument; - } - } - else if (option == kFLASH_ResourceOptionFlashIfr) - { - if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes) - { - } -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP - else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd)) - { - } -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - else if ((start >= kFLASH_ResourceRangeDflashIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd)) - { - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - - return status; -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option) -{ - if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) || - (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) || - (option == kFLASH_SwapControlOptionDisableSystem)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_InvalidArgument; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) -{ - flash_swap_ifr_field_data_t flashSwapIfrFieldData; - uint32_t swapIndicatorAddress; - - status_t returnCode; -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD - returnCode = - FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData, - sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr); - - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } -#else - { - /* From RM, the actual info are stored in FCCOB6,7 */ - uint32_t returnValue[2]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapAddr, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress = (uint16_t)returnValue[0]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapEnable, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapEnableWord = (uint16_t)returnValue[0]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapDisable, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapDisableWord = (uint16_t)returnValue[0]; - } -#endif - - /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field, - * the low severval bit value of Swap Indicator Address is always 1'b0 */ - swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress * - FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; - if (address != swapIndicatorAddress) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) -{ - if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) && - (option != kFLASH_FlexramFunctionOptionAvailableForEeprom)) - { - return kStatus_FLASH_InvalidArgument; - } - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info) -{ - uint32_t pflashTotalSize; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_protection_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent protection register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER) - pflashTotalSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE + - FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; - info->regionBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; -#else - pflashTotalSize = config->PFlashTotalSize; - info->regionBase = config->PFlashBlockBase; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - info->regionCount = FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT; - } - else -#endif - { - info->regionCount = FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT; - } - - /* Calculate the size of the flash protection region - * If the flash density is > 32KB, then protection region is 1/32 of total flash density - * Else if flash density is < 32KB, then flash protection region is set to 1KB */ - if (pflashTotalSize > info->regionCount * 1024) - { - info->regionSize = (pflashTotalSize) / info->regionCount; - } - else - { - info->regionSize = 1024; - } - - return kStatus_FLASH_Success; -} - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_access_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent access register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER) - info->SegmentBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; -#else - info->SegmentBase = config->PFlashBlockBase; -#endif - info->SegmentSize = config->PFlashAccessSegmentSize; - info->SegmentCount = config->PFlashAccessSegmentCount; - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_flash.h b/third_party/nxp/MKW41Z4/drivers/fsl_flash.h deleted file mode 100644 index 50d63d217..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_flash.h +++ /dev/null @@ -1,1387 +0,0 @@ -/* - * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FLASH_H_ -#define _FSL_FLASH_H_ - -#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) -#include -#include -#include "fsl_device_registers.h" -#include "bootloader_common.h" -#else -#include "fsl_common.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 3, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 1 /*!< Bugfix for flash driver version.*/ -}; -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Indicates whether to support FlexNVM in the Flash driver */ -#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) -#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enables the FlexNVM support by default. */ -#endif - -/*! @brief Indicates whether the FlexNVM is enabled in the Flash driver */ -#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) - -/*! @brief Indicates whether to support Secondary flash in the Flash driver */ -#if !defined(FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) -#define FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT 1 /*!< Enables the secondary flash support by default. */ -#endif - -/*! @brief Indicates whether the secondary flash is supported in the Flash driver */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) -#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) -#else -#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (0) -#endif - -/*! @brief Flash driver location. */ -#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) -#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) -#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */ -#else -#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */ -#endif -#endif - -/*! @brief Flash Driver Export option */ -#if !defined(FLASH_DRIVER_IS_EXPORTED) -#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) -#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */ -#else -#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for the KSDK application. */ -#endif -#endif -/*@}*/ - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASH) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - kStatus_FLASH_PartitionStatusUpdateFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ - kStatus_FLASH_SetFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/ - kStatus_FLASH_RecoverFlexramAsRamError = - MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/ - kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set FlexRAM as RAM.*/ - kStatus_FLASH_RecoverFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/ - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/ - kStatus_FLASH_SwapSystemNotInUninitialized = - MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in an uninitialzed state.*/ - kStatus_FLASH_SwapIndicatorAddressError = - MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< The swap indicator address is invalid.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 18), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 19), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for supported flash margin levels. - */ -typedef enum _flash_margin_value -{ - kFLASH_MarginValueNormal, /*!< Use the 'normal' read level for 1s.*/ - kFLASH_MarginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ - kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ - kFLASH_MarginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ -} flash_margin_value_t; - -/*! - * @brief Enumeration for the three possible flash security states. - */ -typedef enum _flash_security_state -{ - kFLASH_SecurityStateNotSecure, /*!< Flash is not secure.*/ - kFLASH_SecurityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/ - kFLASH_SecurityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/ -} flash_security_state_t; - -/*! - * @brief Enumeration for the three possible flash protection levels. - */ -typedef enum _flash_protection_state -{ - kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/ - kFLASH_ProtectionStateProtected, /*!< Flash region is protected.*/ - kFLASH_ProtectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ -} flash_protection_state_t; - -/*! - * @brief Enumeration for the three possible flash execute access levels. - */ -typedef enum _flash_execute_only_access_state -{ - kFLASH_AccessStateUnLimited, /*!< Flash region is unlimited.*/ - kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/ - kFLASH_AccessStateMixed /*!< Flash is mixed with unlimited and execute only region.*/ -} flash_execute_only_access_state_t; - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ - kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ - kFLASH_PropertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ - kFLASH_PropertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ - kFLASH_PropertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ - kFLASH_PropertyDflashBlockSize = 0x12U, /*!< Dflash block size property.*/ - kFLASH_PropertyDflashBlockCount = 0x13U, /*!< Dflash block count property.*/ - kFLASH_PropertyDflashBlockBaseAddr = 0x14U, /*!< Dflash block base address property.*/ - kFLASH_PropertyEepromTotalSize = 0x15U, /*!< EEPROM total size property.*/ - kFLASH_PropertyFlashMemoryIndex = 0x20U, /*!< Flash memory index property.*/ - kFLASH_PropertyFlashCacheControllerIndex = 0x21U /*!< Flash cache controller index property.*/ -} flash_property_tag_t; - -/*! - * @brief Constants for execute-in-RAM flash function. - */ -enum _flash_execute_in_ram_function_constants -{ - kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/ - kFLASH_ExecuteInRamFunctionTotalNum = 2U /*!< Total number of execute-in-RAM functions.*/ -}; - -/*! - * @brief Flash execute-in-RAM function information. - */ -typedef struct _flash_execute_in_ram_function_config -{ - uint32_t activeFunctionCount; /*!< Number of available execute-in-RAM functions.*/ - uint32_t *flashRunCommand; /*!< Execute-in-RAM function: flash_run_command.*/ - uint32_t *flashCommonBitOperation; /*!< Execute-in-RAM function: flash_common_bit_operation.*/ -} flash_execute_in_ram_function_config_t; - -/*! - * @brief Enumeration for the two possible options of flash read resource command. - */ -typedef enum _flash_read_resource_option -{ - kFLASH_ResourceOptionFlashIfr = - 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ - kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/ -} flash_read_resource_option_t; - -/*! - * @brief Enumeration for the range of special-purpose flash resource - */ -enum _flash_read_resource_range -{ -#if (FSL_FEATURE_FLASH_IS_FTFE == 1) - kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ - kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/ -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ - kFLASH_ResourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ -#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/ -#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/ -#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/ -#else - kFLASH_ResourceRangePflashSwapIfrStart = 0, -#endif - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/ -#endif - kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ - kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ -}; - -/*! - * @brief Enumeration for the index of read/program once record - */ -enum _k3_flash_read_once_index -{ - kFLASH_RecordIndexSwapAddr = 0xA1U, /*!< Index of Swap indicator address.*/ - kFLASH_RecordIndexSwapEnable = 0xA2U, /*!< Index of Swap system enable.*/ - kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/ -}; - -/*! - * @brief Enumeration for the two possilbe options of set FlexRAM function command. - */ -typedef enum _flash_flexram_function_option -{ - kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ - kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ -} flash_flexram_function_option_t; - -/*! - * @brief Enumeration for acceleration RAM property. - */ -enum _flash_acceleration_ram_property -{ - kFLASH_AccelerationRamSize = 0x400U -}; - -/*! - * @brief Enumeration for the possible options of Swap function - */ -typedef enum _flash_swap_function_option -{ - kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< An option used to enable the Swap function */ - kFLASH_SwapFunctionOptionDisable = 0x01U /*!< An option used to disable the Swap function */ -} flash_swap_function_option_t; - -/*! - * @brief Enumeration for the possible options of Swap control commands - */ -typedef enum _flash_swap_control_option -{ - kFLASH_SwapControlOptionIntializeSystem = 0x01U, /*!< An option used to initialize the Swap system */ - kFLASH_SwapControlOptionSetInUpdateState = 0x02U, /*!< An option used to set the Swap in an update state */ - kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */ - kFLASH_SwapControlOptionReportStatus = 0x08U, /*!< An option used to report the Swap status */ - kFLASH_SwapControlOptionDisableSystem = 0x10U /*!< An option used to disable the Swap status */ -} flash_swap_control_option_t; - -/*! - * @brief Enumeration for the possible flash Swap status. - */ -typedef enum _flash_swap_state -{ - kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/ - kFLASH_SwapStateReady = 0x01U, /*!< Flash Swap system is in a ready state.*/ - kFLASH_SwapStateUpdate = 0x02U, /*!< Flash Swap system is in an update state.*/ - kFLASH_SwapStateUpdateErased = 0x03U, /*!< Flash Swap system is in an updateErased state.*/ - kFLASH_SwapStateComplete = 0x04U, /*!< Flash Swap system is in a complete state.*/ - kFLASH_SwapStateDisabled = 0x05U /*!< Flash Swap system is in a disabled state.*/ -} flash_swap_state_t; - -/*! - * @breif Enumeration for the possible flash Swap block status - */ -typedef enum _flash_swap_block_status -{ - kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero = - 0x00U, /*!< Swap block status is that lower half program block at zero.*/ - kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero = - 0x01U, /*!< Swap block status is that upper half program block at zero.*/ -} flash_swap_block_status_t; - -/*! - * @brief Flash Swap information - */ -typedef struct _flash_swap_state_config -{ - flash_swap_state_t flashSwapState; /*!pinDirection == kGPIO_DigitalInput) - { - base->PDDR &= ~(1U << pin); - } - else - { - GPIO_WritePinOutput(base, pin, config->outputLogic); - base->PDDR |= (1U << pin); - } -} - -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) -{ - uint8_t instance; - PORT_Type *portBase; - instance = GPIO_GetInstance(base); - portBase = s_portBases[instance]; - return portBase->ISFR; -} - -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) -{ - uint8_t instance; - PORT_Type *portBase; - instance = GPIO_GetInstance(base); - portBase = s_portBases[instance]; - portBase->ISFR = mask; -} - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) -{ - base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | - ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT); -} -#endif - -#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT - -/******************************************************************************* - * Variables - ******************************************************************************/ -static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; - -/******************************************************************************* -* Prototypes -******************************************************************************/ -/*! -* @brief Gets the FGPIO instance according to the GPIO base -* -* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) -* @retval FGPIO instance -*/ -static uint32_t FGPIO_GetInstance(FGPIO_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t FGPIO_GetInstance(FGPIO_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++) - { - if (s_fgpioBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_fgpioBases)); - - return instance; -} - -void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) -{ - assert(config); - - if (config->pinDirection == kGPIO_DigitalInput) - { - base->PDDR &= ~(1U << pin); - } - else - { - FGPIO_WritePinOutput(base, pin, config->outputLogic); - base->PDDR |= (1U << pin); - } -} - -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) -{ - uint8_t instance; - instance = FGPIO_GetInstance(base); - PORT_Type *portBase; - portBase = s_portBases[instance]; - return portBase->ISFR; -} - -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) -{ - uint8_t instance; - instance = FGPIO_GetInstance(base); - PORT_Type *portBase; - portBase = s_portBases[instance]; - portBase->ISFR = mask; -} - -#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER -void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) -{ - base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | - (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT); -} -#endif - -#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_gpio.h b/third_party/nxp/MKW41Z4/drivers/fsl_gpio.h deleted file mode 100644 index 410e2b8ee..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_gpio.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_GPIO_H_ -#define _FSL_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gpio - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief GPIO driver version 2.1.1. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -/*! @brief GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -/*! @brief GPIO checker attribute */ -typedef enum _gpio_checker_attribute -{ - kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = - 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = - 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = - 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = - 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = - 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = - 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = - 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ - kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = - 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ - kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */ -} gpio_checker_attribute_t; -#endif - -/*! - * @brief The GPIO pin configuration structure. - * - * Each pin can only be configured as either an output pin or an input pin at a time. - * If configured as an input pin, leave the outputConfig unused. - * Note that in some use cases, the corresponding port property should be configured in advance - * with the PORT_SetPinConfig(). - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations; ignore if configured as an input pin */ - uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ -} gpio_pin_config_t; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup gpio_driver - * @{ - */ - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or an output pin configuration. - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO port pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) -{ - if (output == 0U) - { - base->PCOR = 1U << pin; - } - else - { - base->PSOR = 1U << pin; - } -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PSOR = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PCOR = mask; -} - -/*! - * @brief Reverses the current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PTOR = mask; -} -/*@}*/ - -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO port. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) -{ - return (((base->PDIR) >> pin) & 0x01U); -} -/*@}*/ - -/*! @name GPIO Interrupt */ -/*@{*/ - -/*! - * @brief Reads the GPIO port interrupt status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the - * pin 0 and 17 have the interrupt. - */ -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); - -/*! - * @brief Clears multiple GPIO pin interrupt status flags. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -/*! - * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit - * words. Each 32-bit data port includes a GACR register, which defines the byte-level - * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data - * bytes in the GACR follow a standard little endian - * data convention. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); -#endif - -/*@}*/ -/*! @} */ - -/*! - * @addtogroup fgpio_driver - * @{ - */ - -/* - * Introduces the FGPIO feature. - * - * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT - * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and - * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. - */ - -#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT - -/*! @name FGPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes a FGPIO pin used by the board. - * - * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. - * Then, call the FGPIO_PinInit() function. - * - * This is an example to define an input pin or an output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param pin FGPIO port pin number - * @param config FGPIO pin configuration pointer - */ -void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name FGPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param pin FGPIO pin number - * @param output FGPIOpin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) -{ - if (output == 0U) - { - base->PCOR = 1 << pin; - } - else - { - base->PSOR = 1 << pin; - } -} - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 1. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PSOR = mask; -} - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 0. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PCOR = mask; -} - -/*! - * @brief Reverses the current output logic of the multiple FGPIO pins. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PTOR = mask; -} -/*@}*/ - -/*! @name FGPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the FGPIO port. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param pin FGPIO pin number - * @retval FGPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) -{ - return (((base->PDIR) >> pin) & 0x01U); -} -/*@}*/ - -/*! @name FGPIO Interrupt */ -/*@{*/ - -/*! - * @brief Reads the FGPIO port interrupt status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level-sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the - * pin 0 and 17 have the interrupt. - */ -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); - -/*! - * @brief Clears the multiple FGPIO pin interrupt status flag. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -/*! - * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit - * words. Each 32-bit data port includes a GACR register, which defines the byte-level - * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data - * bytes in the GACR follow a standard little endian - * data convention. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); -#endif - -/*@}*/ - -#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _FSL_GPIO_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_i2c.c b/third_party/nxp/MKW41Z4/drivers/fsl_i2c.c deleted file mode 100644 index 6c9770af2..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_i2c.c +++ /dev/null @@ -1,1757 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_i2c.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief i2c transfer state. */ -enum _i2c_transfer_states -{ - kIdleState = 0x0U, /*!< I2C bus idle. */ - kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ - kSendCommandState = 0x2U, /*!< Send command byte phase. */ - kSendDataState = 0x3U, /*!< Send data transfer phase. */ - kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ - kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ -}; - -/*! @brief Common sets of flags used by the driver. */ -enum _i2c_flag_constants -{ -/*! All flags which are cleared by the driver upon starting a transfer. */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag, - kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable, -#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag, - kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable, -#else - kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, - kIrqFlags = kI2C_GlobalInterruptEnable, -#endif - -}; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for I2C module. - * - * @param base I2C peripheral base address. - */ -uint32_t I2C_GetInstance(I2C_Type *base); - -/*! -* @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the -* closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop -* hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided, -* assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT -* value, then the related SDA hold time, SCL start and SCL stop hold time is used. -* -* @param base I2C peripheral base address. -* @param sourceClock_Hz I2C functional clock frequency in Hertz. -* @param sclStopHoldTime_ns SCL stop hold time in ns. -*/ -static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz); - -/*! - * @brief Set up master transfer, send slave address and decide the initial - * transfer state. - * - * @param base I2C peripheral base address. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. - * @param xfer pointer to i2c_master_transfer_t structure. - */ -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Check and clear status operation. - * - * @param base I2C peripheral base address. - * @param status current i2c hardware status. - * @retval kStatus_Success No error found. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStatus_I2C_Nak Received Nak error. - */ -static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); - -/*! - * @brief Master run transfer state machine to perform a byte of transfer. - * - * @param base I2C peripheral base address. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state - * @param isDone input param to get whether the thing is done, true is done - * @retval kStatus_Success No error found. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStatus_I2C_Nak Received Nak error. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - */ -static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); - -/*! - * @brief I2C common interrupt handler. - * - * @param base I2C peripheral base address. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state - */ -static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to i2c handles for each instance. */ -static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL}; - -/*! @brief SCL clock divider used to calculate baudrate. */ -static const uint16_t s_i2cDividerTable[] = { - 20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, 48, 56, 68, - 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, - 160, 192, 224, 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, - 640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; - -/*! @brief Pointers to i2c bases for each instance. */ -static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; - -/*! @brief Pointers to i2c IRQ number for each instance. */ -static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to i2c clocks for each instance. */ -static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointer to master IRQ handler for each instance. */ -static i2c_isr_t s_i2cMasterIsr; - -/*! @brief Pointer to slave IRQ handler for each instance. */ -static i2c_isr_t s_i2cSlaveIsr; - -/******************************************************************************* - * Codes - ******************************************************************************/ - -uint32_t I2C_GetInstance(I2C_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++) - { - if (s_i2cBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_i2cBases)); - - return instance; -} - -static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz) -{ - uint32_t multiplier; - uint32_t computedSclHoldTime; - uint32_t absError; - uint32_t bestError = UINT32_MAX; - uint32_t bestMult = 0u; - uint32_t bestIcr = 0u; - uint8_t mult; - uint8_t i; - - /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, - * and ranges from 0-2. It selects the multiplier factor for the divider. */ - /* SDA hold time = bus period (s) * mul * SDA hold value. */ - /* SCL start hold time = bus period (s) * mul * SCL start hold value. */ - /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */ - - for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) - { - multiplier = 1u << mult; - - /* Scan table to find best match. */ - for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) - { - /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */ - computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000000U) / sourceClock_Hz; - absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) : - (computedSclHoldTime - sclStopHoldTime_ns); - - if (absError < bestError) - { - bestMult = mult; - bestIcr = i; - bestError = absError; - - /* If the error is 0, then we can stop searching because we won't find a better match. */ - if (absError == 0) - { - break; - } - } - } - } - - /* Set frequency register based on best settings. */ - base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); -} - -static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - status_t result = kStatus_Success; - i2c_direction_t direction = xfer->direction; - - /* Initialize the handle transfer information. */ - handle->transfer = *xfer; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Initial transfer state. */ - if (handle->transfer.subaddressSize > 0) - { - if (xfer->direction == kI2C_Read) - { - direction = kI2C_Write; - } - } - - handle->state = kCheckAddressState; - - /* Clear all status before transfer. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* If repeated start is requested, send repeated start. */ - if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); - } - else /* For normal transfer, send start. */ - { - result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); - } - - return result; -} - -static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check arbitration lost. */ - if (status & kI2C_ArbitrationLostFlag) - { - /* Clear arbitration lost flag. */ - base->S = kI2C_ArbitrationLostFlag; - result = kStatus_I2C_ArbitrationLost; - } - /* Check NAK */ - else if (status & kI2C_ReceiveNakFlag) - { - result = kStatus_I2C_Nak; - } - else - { - } - - return result; -} - -static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) -{ - status_t result = kStatus_Success; - uint32_t statusFlags = base->S; - *isDone = false; - volatile uint8_t dummy = 0; - bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || - ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); - - /* Add this to avoid build warning. */ - dummy++; - - /* Check & clear error flags. */ - result = I2C_CheckAndClearError(base, statusFlags); - - /* Ignore Nak when it's appeared for last byte. */ - if ((result == kStatus_I2C_Nak) && ignoreNak) - { - result = kStatus_Success; - } - - /* Handle Check address state to check the slave address is Acked in slave - probe application. */ - if (handle->state == kCheckAddressState) - { - if (statusFlags & kI2C_ReceiveNakFlag) - { - result = kStatus_I2C_Addr_Nak; - } - else - { - if (handle->transfer.subaddressSize > 0) - { - handle->state = kSendCommandState; - } - else - { - if (handle->transfer.direction == kI2C_Write) - { - /* Next state, send data. */ - handle->state = kSendDataState; - } - else - { - /* Next state, receive data begin. */ - handle->state = kReceiveDataBeginState; - } - } - } - } - - if (result) - { - return result; - } - - /* Run state machine. */ - switch (handle->state) - { - /* Send I2C command. */ - case kSendCommandState: - if (handle->transfer.subaddressSize) - { - handle->transfer.subaddressSize--; - base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); - } - else - { - if (handle->transfer.direction == kI2C_Write) - { - /* Next state, send data. */ - handle->state = kSendDataState; - - /* Send first byte of data. */ - if (handle->transfer.dataSize > 0) - { - base->D = *handle->transfer.data; - handle->transfer.data++; - handle->transfer.dataSize--; - } - } - else - { - /* Send repeated start and slave address. */ - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); - - /* Next state, receive data begin. */ - handle->state = kReceiveDataBeginState; - } - } - break; - - /* Send I2C data. */ - case kSendDataState: - /* Send one byte of data. */ - if (handle->transfer.dataSize > 0) - { - base->D = *handle->transfer.data; - handle->transfer.data++; - handle->transfer.dataSize--; - } - else - { - *isDone = true; - } - break; - - /* Start I2C data receive. */ - case kReceiveDataBeginState: - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Send nak at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Read dummy to release the bus. */ - dummy = base->D; - - /* Next state, receive data. */ - handle->state = kReceiveDataState; - break; - - /* Receive I2C data. */ - case kReceiveDataState: - /* Receive one byte of data. */ - if (handle->transfer.dataSize--) - { - if (handle->transfer.dataSize == 0) - { - *isDone = true; - - /* Send stop if kI2C_TransferNoStop is not asserted. */ - if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) - { - result = I2C_MasterStop(base); - } - else - { - base->C1 |= I2C_C1_TX_MASK; - } - } - - /* Send NAK at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Read the data byte into the transfer buffer. */ - *handle->transfer.data = base->D; - handle->transfer.data++; - } - break; - - default: - break; - } - - return result; -} - -static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) -{ - /* Check if master interrupt. */ - if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK)) - { - s_i2cMasterIsr(base, handle); - } - else - { - s_i2cSlaveIsr(base, handle); - } - __DSB(); -} - -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(masterConfig && srcClock_Hz); - - /* Temporary register for filter read. */ - uint8_t fltReg; -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - uint8_t s2Reg; -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable I2C clock. */ - CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - base->A1 = 0; - base->F = 0; - base->C1 = 0; - base->S = 0xFFU; - base->C2 = 0; -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - base->FLT = 0x50U; -#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - base->FLT = 0x40U; -#endif - base->RA = 0; - - /* Disable I2C prior to configuring it. */ - base->C1 &= ~(I2C_C1_IICEN_MASK); - - /* Clear all flags. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* Configure baud rate. */ - I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); - - /* Read out the FLT register. */ - fltReg = base->FLT; - -#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF - /* Configure the stop / hold enable. */ - fltReg &= ~(I2C_FLT_SHEN_MASK); - fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold); -#endif - - /* Configure the glitch filter value. */ - fltReg &= ~(I2C_FLT_FLT_MASK); - fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth); - - /* Write the register value back to the filter register. */ - base->FLT = fltReg; - -/* Enable/Disable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - s2Reg = base->S2 & (~I2C_S2_DFEN_MASK); - base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering); -#endif - - /* Enable the I2C peripheral based on the configuration. */ - base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); -} - -void I2C_MasterDeinit(I2C_Type *base) -{ - /* Disable I2C module. */ - I2C_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable I2C clock. */ - CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) -{ - assert(masterConfig); - - /* Default baud rate at 100kbps. */ - masterConfig->baudRate_Bps = 100000U; - -/* Default stop hold enable is disabled. */ -#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF - masterConfig->enableStopHold = false; -#endif - - /* Default glitch filter value is no filter. */ - masterConfig->glitchFilterWidth = 0U; - -/* Default enable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - masterConfig->enableDoubleBuffering = true; -#endif - - /* Enable the I2C peripheral. */ - masterConfig->enableMaster = true; -} - -void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) -{ -#ifdef I2C_HAS_STOP_DETECT - uint8_t fltReg; -#endif - - if (mask & kI2C_GlobalInterruptEnable) - { - base->C1 |= I2C_C1_IICIE_MASK; - } - -#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - if (mask & kI2C_StopDetectInterruptEnable) - { - fltReg = base->FLT; - - /* Keep STOPF flag. */ - fltReg &= ~I2C_FLT_STOPF_MASK; - - /* Stop detect enable. */ - fltReg |= I2C_FLT_STOPIE_MASK; - base->FLT = fltReg; - } -#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - if (mask & kI2C_StartStopDetectInterruptEnable) - { - fltReg = base->FLT; - - /* Keep STARTF and STOPF flags. */ - fltReg &= ~(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); - - /* Start and stop detect enable. */ - fltReg |= I2C_FLT_SSIE_MASK; - base->FLT = fltReg; - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -} - -void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) -{ - if (mask & kI2C_GlobalInterruptEnable) - { - base->C1 &= ~I2C_C1_IICIE_MASK; - } - -#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - if (mask & kI2C_StopDetectInterruptEnable) - { - base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK); - } -#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - if (mask & kI2C_StartStopDetectInterruptEnable) - { - base->FLT &= ~(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -} - -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint32_t multiplier; - uint32_t computedRate; - uint32_t absError; - uint32_t bestError = UINT32_MAX; - uint32_t bestMult = 0u; - uint32_t bestIcr = 0u; - uint8_t mult; - uint8_t i; - - /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, - * and ranges from 0-2. It selects the multiplier factor for the divider. */ - for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) - { - multiplier = 1u << mult; - - /* Scan table to find best match. */ - for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i) - { - computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]); - absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); - - if (absError < bestError) - { - bestMult = mult; - bestIcr = i; - bestError = absError; - - /* If the error is 0, then we can stop searching because we won't find a better match. */ - if (absError == 0) - { - break; - } - } - } - } - - /* Set frequency register based on best settings. */ - base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); -} - -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result = kStatus_Success; - uint32_t statusFlags = I2C_MasterGetStatusFlags(base); - - /* Return an error if the bus is already in use. */ - if (statusFlags & kI2C_BusBusyFlag) - { - result = kStatus_I2C_Busy; - } - else - { - /* Send the START signal. */ - base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; - -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING - while (!(base->S2 & I2C_S2_EMPTY_MASK)) - { - } -#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ - - base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); - } - - return result; -} - -status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) -{ - status_t result = kStatus_Success; - uint8_t savedMult; - uint32_t statusFlags = I2C_MasterGetStatusFlags(base); - uint8_t timeDelay = 6; - - /* Return an error if the bus is already in use, but not by us. */ - if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0)) - { - result = kStatus_I2C_Busy; - } - else - { - savedMult = base->F; - base->F = savedMult & (~I2C_F_MULT_MASK); - - /* We are already in a transfer, so send a repeated start. */ - base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK; - - /* Restore the multiplier factor. */ - base->F = savedMult; - - /* Add some delay to wait the Re-Start signal. */ - while (timeDelay--) - { - __NOP(); - } - -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING - while (!(base->S2 & I2C_S2_EMPTY_MASK)) - { - } -#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ - - base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); - } - - return result; -} - -status_t I2C_MasterStop(I2C_Type *base) -{ - status_t result = kStatus_Success; - uint16_t timeout = UINT16_MAX; - - /* Issue the STOP command on the bus. */ - base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Wait until data transfer complete. */ - while ((base->S & kI2C_BusBusyFlag) && (--timeout)) - { - } - - if (timeout == 0) - { - result = kStatus_I2C_Timeout; - } - - return result; -} - -uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) -{ - uint32_t statusFlags = base->S; - -#ifdef I2C_HAS_STOP_DETECT - /* Look up the STOPF bit from the filter register. */ - if (base->FLT & I2C_FLT_STOPF_MASK) - { - statusFlags |= kI2C_StopDetectFlag; - } -#endif - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Look up the STARTF bit from the filter register. */ - if (base->FLT & I2C_FLT_STARTF_MASK) - { - statusFlags |= kI2C_StartDetectFlag; - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - return statusFlags; -} - -status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) -{ - status_t result = kStatus_Success; - uint8_t statusFlags = 0; - - /* Wait until the data register is ready for transmit. */ - while (!(base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Setup the I2C peripheral to transmit data. */ - base->C1 |= I2C_C1_TX_MASK; - - while (txSize--) - { - /* Send a byte of data. */ - base->D = *txBuff++; - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - statusFlags = base->S; - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ - if (statusFlags & kI2C_ArbitrationLostFlag) - { - base->S = kI2C_ArbitrationLostFlag; - result = kStatus_I2C_ArbitrationLost; - } - - if ((statusFlags & kI2C_ReceiveNakFlag) && txSize) - { - base->S = kI2C_ReceiveNakFlag; - result = kStatus_I2C_Nak; - } - - if (result != kStatus_Success) - { - /* Breaking out of the send loop. */ - break; - } - } - - if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) - { - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send stop. */ - result = I2C_MasterStop(base); - } - - return result; -} - -status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) -{ - status_t result = kStatus_Success; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - /* Wait until the data register is ready for transmit. */ - while (!(base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Setup the I2C peripheral to receive data. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* If rxSize equals 1, configure to send NAK. */ - if (rxSize == 1) - { - /* Issue NACK on read. */ - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Do dummy read. */ - dummy = base->D; - - while ((rxSize--)) - { - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Single byte use case. */ - if (rxSize == 0) - { - if (!(flags & kI2C_TransferNoStopFlag)) - { - /* Issue STOP command before reading last byte. */ - result = I2C_MasterStop(base); - } - else - { - /* Change direction to Tx to avoid extra clocks. */ - base->C1 |= I2C_C1_TX_MASK; - } - } - - if (rxSize == 1) - { - /* Issue NACK on read. */ - base->C1 |= I2C_C1_TXAK_MASK; - } - - /* Read from the data register. */ - *rxBuff++ = base->D; - } - - return result; -} - -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) -{ - assert(xfer); - - i2c_direction_t direction = xfer->direction; - status_t result = kStatus_Success; - - /* Clear all status before transfer. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* Wait until ready to complete. */ - while (!(base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Change to send write address when it's a read operation with command. */ - if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) - { - direction = kI2C_Write; - } - - /* If repeated start is requested, send repeated start. */ - if (xfer->flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); - } - else /* For normal transfer, send start. */ - { - result = I2C_MasterStart(base, xfer->slaveAddress, direction); - } - - /* Return if error. */ - if (result) - { - return result; - } - - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - /* Return if error. */ - if (result) - { - if (result == kStatus_I2C_Nak) - { - result = kStatus_I2C_Addr_Nak; - - I2C_MasterStop(base); - } - - return result; - } - - /* Send subaddress. */ - if (xfer->subaddressSize) - { - do - { - /* Clear interrupt pending flag. */ - base->S = kI2C_IntPendingFlag; - - xfer->subaddressSize--; - base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - if (result == kStatus_I2C_Nak) - { - I2C_MasterStop(base); - } - - return result; - } - - } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); - - if (xfer->direction == kI2C_Read) - { - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send repeated start and slave address. */ - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); - - /* Return if error. */ - if (result) - { - return result; - } - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - if (result == kStatus_I2C_Nak) - { - result = kStatus_I2C_Addr_Nak; - - I2C_MasterStop(base); - } - - return result; - } - } - } - - /* Transmit data. */ - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) - { - /* Send Data. */ - result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - - /* Receive Data. */ - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) - { - result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); - } - - return result; -} - -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance = I2C_GetInstance(base); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Save the context in global variables to support the double weak mechanism. */ - s_i2cHandle[instance] = handle; - - /* Save master interrupt handler. */ - s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; - - /* Enable NVIC interrupt. */ - EnableIRQ(s_i2cIrqs[instance]); -} - -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - status_t result = kStatus_Success; - - /* Check if the I2C bus is idle - if not return busy status. */ - if (handle->state != kIdleState) - { - result = kStatus_I2C_Busy; - } - else - { - /* Start up the master transfer state machine. */ - result = I2C_InitTransferStateMachine(base, handle, xfer); - - if (result == kStatus_Success) - { - /* Enable the I2C interrupts. */ - I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); - } - } - - return result; -} - -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) -{ - assert(handle); - - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - /* Disable interrupt. */ - I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); - - /* Reset the state to idle. */ - handle->state = kIdleState; - - /* Send STOP signal. */ - if (handle->transfer.direction == kI2C_Read) - { - base->C1 |= I2C_C1_TXAK_MASK; - while (!(base->S & kI2C_IntPendingFlag)) - { - } - base->S = kI2C_IntPendingFlag; - - base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - dummy = base->D; - } - else - { - while (!(base->S & kI2C_IntPendingFlag)) - { - } - base->S = kI2C_IntPendingFlag; - base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - } -} - -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - *count = handle->transferSize - handle->transfer.dataSize; - - return kStatus_Success; -} - -void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) -{ - assert(i2cHandle); - - i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; - status_t result = kStatus_Success; - bool isDone; - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - /* Check transfer complete flag. */ - result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); - - if (isDone || result) - { - /* Send stop command if transfer done or received Nak. */ - if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) || - (result == kStatus_I2C_Addr_Nak)) - { - /* Ensure stop command is a need. */ - if ((base->C1 & I2C_C1_MST_MASK)) - { - if (I2C_MasterStop(base) != kStatus_Success) - { - result = kStatus_I2C_Timeout; - } - } - } - - /* Restore handle to idle state. */ - handle->state = kIdleState; - - /* Disable interrupt. */ - I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); - - /* Call the callback function after the function has completed. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) -{ - assert(slaveConfig); - - uint8_t tmpReg; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - base->A1 = 0; - base->F = 0; - base->C1 = 0; - base->S = 0xFFU; - base->C2 = 0; -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - base->FLT = 0x50U; -#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - base->FLT = 0x40U; -#endif - base->RA = 0; - - /* Configure addressing mode. */ - switch (slaveConfig->addressingMode) - { - case kI2C_Address7bit: - base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; - break; - - case kI2C_RangeMatch: - assert(slaveConfig->slaveAddress < slaveConfig->upperAddress); - base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; - base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U; - base->C2 |= I2C_C2_RMEN_MASK; - break; - - default: - break; - } - - /* Configure low power wake up feature. */ - tmpReg = base->C1; - tmpReg &= ~I2C_C1_WUEN_MASK; - base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave); - - /* Configure general call & baud rate control. */ - tmpReg = base->C2; - tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK); - tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall); - base->C2 = tmpReg; - -/* Enable/Disable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - tmpReg = base->S2 & (~I2C_S2_DFEN_MASK); - base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering); -#endif - - /* Set hold time. */ - I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz); -} - -void I2C_SlaveDeinit(I2C_Type *base) -{ - /* Disable I2C module. */ - I2C_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable I2C clock. */ - CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - /* By default slave is addressed with 7-bit address. */ - slaveConfig->addressingMode = kI2C_Address7bit; - - /* General call mode is disabled by default. */ - slaveConfig->enableGeneralCall = false; - - /* Slave address match waking up MCU from low power mode is disabled. */ - slaveConfig->enableWakeUp = false; - - /* Independent slave mode baud rate at maximum frequency is disabled. */ - slaveConfig->enableBaudRateCtl = false; - -/* Default enable double buffering. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - slaveConfig->enableDoubleBuffering = true; -#endif - - /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */ - slaveConfig->sclStopHoldTime_ns = 4000; - - /* Enable the I2C peripheral. */ - slaveConfig->enableSlave = true; -} - -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) -{ - status_t result = kStatus_Success; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Check start flag. */ - while (!(base->FLT & I2C_FLT_STARTF_MASK)) - { - } - /* Clear STARTF flag. */ - base->FLT |= I2C_FLT_STARTF_MASK; - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - /* Wait for address match flag. */ - while (!(base->S & kI2C_AddressMatchFlag)) - { - } - - /* Read dummy to release bus. */ - dummy = base->D; - - result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag); - - /* Switch to receive mode. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release bus. */ - dummy = base->D; - - return result; -} - -void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) -{ - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - -/* Wait until address match. */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Check start flag. */ - while (!(base->FLT & I2C_FLT_STARTF_MASK)) - { - } - /* Clear STARTF flag. */ - base->FLT |= I2C_FLT_STARTF_MASK; - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - /* Wait for address match and int pending flag. */ - while (!(base->S & kI2C_AddressMatchFlag)) - { - } - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Read dummy to release bus. */ - dummy = base->D; - - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Setup the I2C peripheral to receive data. */ - base->C1 &= ~(I2C_C1_TX_MASK); - - while (rxSize--) - { - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - /* Clear the IICIF flag. */ - base->S = kI2C_IntPendingFlag; - - /* Read from the data register. */ - *rxBuff++ = base->D; - } -} - -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance = I2C_GetInstance(base); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Save the context in global variables to support the double weak mechanism. */ - s_i2cHandle[instance] = handle; - - /* Save slave interrupt handler. */ - s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; - - /* Enable NVIC interrupt. */ - EnableIRQ(s_i2cIrqs[instance]); -} - -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) -{ - assert(handle); - - /* Check if the I2C bus is idle - if not return busy status. */ - if (handle->isBusy) - { - return kStatus_I2C_Busy; - } - else - { - /* Disable LPI2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kIrqFlags); - - /* Clear transfer in handle. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* Record that we're busy. */ - handle->isBusy = true; - - /* Set up event mask. tx and rx are always enabled. */ - handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveGenaralcallEvent; - - /* Clear all flags. */ - I2C_SlaveClearStatusFlags(base, kClearFlags); - - /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - I2C_EnableInterrupts(base, kIrqFlags); - } - - return kStatus_Success; -} - -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) -{ - assert(handle); - - if (handle->isBusy) - { - /* Disable interrupts. */ - I2C_DisableInterrupts(base, kIrqFlags); - - /* Reset transfer info. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* Reset the state to idle. */ - handle->isBusy = false; - } -} - -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transfer.transferredCount; - - return kStatus_Success; -} - -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) -{ - assert(i2cHandle); - - uint16_t status; - bool doTransmit = false; - i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; - i2c_slave_transfer_t *xfer; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - status = I2C_SlaveGetStatusFlags(base); - xfer = &(handle->transfer); - -#ifdef I2C_HAS_STOP_DETECT - /* Check stop flag. */ - if (status & kI2C_StopDetectFlag) - { - I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag); - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - /* Call slave callback if this is the STOP of the transfer. */ - if (handle->isBusy) - { - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - - if (!(status & kI2C_AddressMatchFlag)) - { - return; - } - } -#endif /* I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - /* Check start flag. */ - if (status & kI2C_StartDetectFlag) - { - I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag); - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - xfer->event = kI2C_SlaveStartEvent; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - - if (!(status & kI2C_AddressMatchFlag)) - { - return; - } - } -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ - - /* Clear the interrupt flag. */ - base->S = kI2C_IntPendingFlag; - - /* Check NAK */ - if (status & kI2C_ReceiveNakFlag) - { - /* Set receive mode. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy. */ - dummy = base->D; - - if (handle->transfer.dataSize != 0) - { - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_I2C_Nak; - handle->isBusy = false; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - else - { -#ifndef I2C_HAS_STOP_DETECT - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } -#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ - } - } - /* Check address match. */ - else if (status & kI2C_AddressMatchFlag) - { - handle->isBusy = true; - xfer->event = kI2C_SlaveAddressMatchEvent; - - /* Slave transmit, master reading from slave. */ - if (status & kI2C_TransferDirectionFlag) - { - /* Change direction to send data. */ - base->C1 |= I2C_C1_TX_MASK; - - doTransmit = true; - } - else - { - /* Slave receive, master writing to slave. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release the bus. */ - dummy = base->D; - - if (dummy == 0) - { - xfer->event = kI2C_SlaveGenaralcallEvent; - } - } - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - /* Check transfer complete flag. */ - else if (status & kI2C_TransferCompleteFlag) - { - /* Slave transmit, master reading from slave. */ - if (status & kI2C_TransferDirectionFlag) - { - doTransmit = true; - } - else - { - /* If we're out of data, invoke callback to get more. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kI2C_SlaveReceiveEvent; - - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - xfer->transferredCount = 0; - } - - /* Slave receive, master writing to slave. */ - uint8_t data = base->D; - - if (handle->transfer.dataSize) - { - /* Receive data. */ - *handle->transfer.data++ = data; - handle->transfer.dataSize--; - xfer->transferredCount++; - if (!handle->transfer.dataSize) - { -#ifndef I2C_HAS_STOP_DETECT - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - /* Proceed receive complete event. */ - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } -#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ - } - } - } - } - else - { - /* Read dummy to release bus. */ - dummy = base->D; - } - - /* Send data if there is the need. */ - if (doTransmit) - { - /* If we're out of data, invoke callback to get more. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kI2C_SlaveTransmitEvent; - - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - xfer->transferredCount = 0; - } - - if (handle->transfer.dataSize) - { - /* Send data. */ - base->D = *handle->transfer.data++; - handle->transfer.dataSize--; - xfer->transferredCount++; - } - else - { - /* Switch to receive mode. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release bus. */ - dummy = base->D; - -#ifndef I2C_HAS_STOP_DETECT - xfer->event = kI2C_SlaveCompletionEvent; - xfer->completionStatus = kStatus_Success; - handle->isBusy = false; - - /* Proceed txdone event. */ - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } -#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ - } - } -} - -#if defined(I2C0) -void I2C0_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]); -} -#endif - -#if defined(I2C1) -void I2C1_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); -} -#endif - -#if defined(I2C2) -void I2C2_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); -} -#endif - -#if defined(I2C3) -void I2C3_DriverIRQHandler(void) -{ - I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); -} -#endif diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_i2c.h b/third_party/nxp/MKW41Z4/drivers/fsl_i2c.h deleted file mode 100644 index d55fd1d8e..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_i2c.h +++ /dev/null @@ -1,794 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_H_ -#define _FSL_I2C_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup i2c_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief I2C driver version 2.0.3. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ - defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) -#define I2C_HAS_STOP_DETECT -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -/*! @brief I2C status return codes. */ -enum _i2c_status -{ - kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ - kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ - kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ - kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ - kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ -}; - -/*! - * @brief I2C peripheral flags - * - * The following status register flags can be cleared: - * - #kI2C_ArbitrationLostFlag - * - #kI2C_IntPendingFlag - * - #kI2C_StartDetectFlag - * - #kI2C_StopDetectFlag - * - * @note These enumerations are meant to be OR'd together to form a bit mask. - * - */ -enum _i2c_flags -{ - kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */ - kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */ - kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */ - kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */ - kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */ - kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */ - kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */ - kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */ -#ifdef I2C_HAS_STOP_DETECT - kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */ -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */ -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -}; - -/*! @brief I2C feature interrupt source. */ -enum _i2c_interrupt_enable -{ - kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */ - -#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT - kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */ -#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ - -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */ -#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ -}; - -/*! @brief The direction of master and slave transfers. */ -typedef enum _i2c_direction -{ - kI2C_Write = 0x0U, /*!< Master transmits to the slave. */ - kI2C_Read = 0x1U, /*!< Master receives from the slave. */ -} i2c_direction_t; - -/*! @brief Addressing mode. */ -typedef enum _i2c_slave_address_mode -{ - kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */ - kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */ -} i2c_slave_address_mode_t; - -/*! @brief I2C transfer control flag. */ -enum _i2c_master_transfer_flags -{ - kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ - kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal. */ - kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ - kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ -}; - -/*! - * @brief Set of events sent to the callback for nonblocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _i2c_slave_transfer_event -{ - kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kI2C_SlaveTransmitEvent = 0x02U, /*!< A callback is requested to provide data to transmit - (slave-transmitter role). */ - kI2C_SlaveReceiveEvent = 0x04U, /*!< A callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kI2C_SlaveTransmitAckEvent = 0x08U, /*!< A callback needs to either transmit an ACK or NACK. */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */ -#endif - kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ - kI2C_SlaveGenaralcallEvent = 0x40U, /*!< Received the general call address after a start or repeated start. */ - - /*! A bit mask of all available events. */ - kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - kI2C_SlaveStartEvent | -#endif - kI2C_SlaveCompletionEvent | kI2C_SlaveGenaralcallEvent, -} i2c_slave_transfer_event_t; - -/*! @brief I2C master user configuration. */ -typedef struct _i2c_master_config -{ - bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ -#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF - bool enableStopHold; /*!< Controls the stop hold enable. */ -#endif -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - bool enableDoubleBuffering; /*!< Controls double buffer enable; notice that - enabling the double buffer disables the clock stretch. */ -#endif - uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ - uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */ -} i2c_master_config_t; - -/*! @brief I2C slave user configuration. */ -typedef struct _i2c_slave_config -{ - bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ - bool enableGeneralCall; /*!< Enables the general call addressing mode. */ - bool enableWakeUp; /*!< Enables/disables waking up MCU from low-power mode. */ -#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE - bool enableDoubleBuffering; /*!< Controls a double buffer enable; notice that - enabling the double buffer disables the clock stretch. */ -#endif - bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */ - uint16_t slaveAddress; /*!< A slave address configuration. */ - uint16_t upperAddress; /*!< A maximum boundary slave address used in a range matching mode. */ - i2c_slave_address_mode_t - addressingMode; /*!< An addressing mode configuration of i2c_slave_address_mode_config_t. */ - uint32_t sclStopHoldTime_ns; /*!< the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C - data) while SCL is high (stop condition), SDA hold time and SCL start hold time - are also configured according to the SCL stop hold time. */ -} i2c_slave_config_t; - -/*! @brief I2C master handle typedef. */ -typedef struct _i2c_master_handle i2c_master_handle_t; - -/*! @brief I2C master transfer callback typedef. */ -typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, - i2c_master_handle_t *handle, - status_t status, - void *userData); - -/*! @brief I2C slave handle typedef. */ -typedef struct _i2c_slave_handle i2c_slave_handle_t; - -/*! @brief I2C master transfer structure. */ -typedef struct _i2c_master_transfer -{ - uint32_t flags; /*!< A transfer flag which controls the transfer. */ - uint8_t slaveAddress; /*!< 7-bit slave address. */ - i2c_direction_t direction; /*!< A transfer direction, read or write. */ - uint32_t subaddress; /*!< A sub address. Transferred MSB first. */ - uint8_t subaddressSize; /*!< A size of the command buffer. */ - uint8_t *volatile data; /*!< A transfer buffer. */ - volatile size_t dataSize; /*!< A transfer size. */ -} i2c_master_transfer_t; - -/*! @brief I2C master handle structure. */ -struct _i2c_master_handle -{ - i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t state; /*!< A transfer state maintained during transfer. */ - i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */ - void *userData; /*!< A callback parameter passed to the callback function. */ -}; - -/*! @brief I2C slave transfer structure. */ -typedef struct _i2c_slave_transfer -{ - i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */ - uint8_t *volatile data; /*!< A transfer buffer. */ - volatile size_t dataSize; /*!< A transfer size. */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kI2C_SlaveCompletionEvent. */ - size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated - start. */ -} i2c_slave_transfer_t; - -/*! @brief I2C slave transfer callback typedef. */ -typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); - -/*! @brief I2C slave handle structure. */ -struct _i2c_slave_handle -{ - volatile bool isBusy; /*!< Indicates whether a transfer is busy. */ - i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ - uint32_t eventMask; /*!< A mask of enabled events. */ - i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */ - void *userData; /*!< A callback parameter passed to the callback. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock - * and configure the I2C with master configuration. - * - * @note This API should be called at the beginning of the application. - * Otherwise, any operation to the I2C module can cause a hard fault - * because the clock is not enabled. The configuration structure can be custom filled - * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). - * After calling this API, the master is ready to transfer. - * This is an example. - * @code - * i2c_master_config_t config = { - * .enableMaster = true, - * .enableStopHold = false, - * .highDrive = false, - * .baudRate_Bps = 100000, - * .glitchFilterWidth = 0 - * }; - * I2C_MasterInit(I2C0, &config, 12000000U); - * @endcode - * - * @param base I2C base pointer - * @param masterConfig A pointer to the master configuration structure - * @param srcClock_Hz I2C peripheral clock frequency in Hz - */ -void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock - * and initialize the I2C with the slave configuration. - * - * @note This API should be called at the beginning of the application. - * Otherwise, any operation to the I2C module can cause a hard fault - * because the clock is not enabled. The configuration structure can partly be set - * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. - * This is an example. - * @code - * i2c_slave_config_t config = { - * .enableSlave = true, - * .enableGeneralCall = false, - * .addressingMode = kI2C_Address7bit, - * .slaveAddress = 0x1DU, - * .enableWakeUp = false, - * .enablehighDrive = false, - * .enableBaudRateCtl = false, - * .sclStopHoldTime_ns = 4000 - * }; - * I2C_SlaveInit(I2C0, &config, 12000000U); - * @endcode - * - * @param base I2C base pointer - * @param slaveConfig A pointer to the slave configuration structure - * @param srcClock_Hz I2C peripheral clock frequency in Hz - */ -void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); - -/*! - * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. - * The I2C master module can't work unless the I2C_MasterInit is called. - * @param base I2C base pointer - */ -void I2C_MasterDeinit(I2C_Type *base); - -/*! - * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. - * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. - * @param base I2C base pointer - */ -void I2C_SlaveDeinit(I2C_Type *base); - -/*! - * @brief Sets the I2C master configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). - * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify - * the structure before calling the I2C_MasterConfigure(). - * This is an example. - * @code - * i2c_master_config_t config; - * I2C_MasterGetDefaultConfig(&config); - * @endcode - * @param masterConfig A pointer to the master configuration structure. -*/ -void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); - -/*! - * @brief Sets the I2C slave configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure(). - * Modify fields of the structure before calling the I2C_SlaveConfigure(). - * This is an example. - * @code - * i2c_slave_config_t config; - * I2C_SlaveGetDefaultConfig(&config); - * @endcode - * @param slaveConfig A pointer to the slave configuration structure. - */ -void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); - -/*! - * @brief Enables or disabless the I2C peripheral operation. - * - * @param base I2C base pointer - * @param enable Pass true to enable and false to disable the module. - */ -static inline void I2C_Enable(I2C_Type *base, bool enable) -{ - if (enable) - { - base->C1 |= I2C_C1_IICEN_MASK; - } - else - { - base->C1 &= ~I2C_C1_IICEN_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the I2C status flags. - * - * @param base I2C base pointer - * @return status flag, use status flag to AND #_i2c_flags to get the related status. - */ -uint32_t I2C_MasterGetStatusFlags(I2C_Type *base); - -/*! - * @brief Gets the I2C status flags. - * - * @param base I2C base pointer - * @return status flag, use status flag to AND #_i2c_flags to get the related status. - */ -static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) -{ - return I2C_MasterGetStatusFlags(base); -} - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag. - * - * @param base I2C base pointer - * @param statusMask The status flag mask, defined in type i2c_status_flag_t. - * The parameter can be any combination of the following values: - * @arg kI2C_StartDetectFlag (if available) - * @arg kI2C_StopDetectFlag (if available) - * @arg kI2C_ArbitrationLostFlag - * @arg kI2C_IntPendingFlagFlag - */ -static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ -/* Must clear the STARTF / STOPF bits prior to clearing IICIF */ -#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT - if (statusMask & kI2C_StartDetectFlag) - { - /* Shift the odd-ball flags back into place. */ - base->FLT |= (uint8_t)(statusMask >> 8U); - } -#endif - -#ifdef I2C_HAS_STOP_DETECT - if (statusMask & kI2C_StopDetectFlag) - { - /* Shift the odd-ball flags back into place. */ - base->FLT |= (uint8_t)(statusMask >> 8U); - } -#endif - - base->S = (uint8_t)statusMask; -} - -/*! - * @brief Clears the I2C status flag state. - * - * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag - * - * @param base I2C base pointer - * @param statusMask The status flag mask, defined in type i2c_status_flag_t. - * The parameter can be any combination of the following values: - * @arg kI2C_StartDetectFlag (if available) - * @arg kI2C_StopDetectFlag (if available) - * @arg kI2C_ArbitrationLostFlag - * @arg kI2C_IntPendingFlagFlag - */ -static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) -{ - I2C_MasterClearStatusFlags(base, statusMask); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables I2C interrupt requests. - * - * @param base I2C base pointer - * @param mask interrupt source - * The parameter can be combination of the following source if defined: - * @arg kI2C_GlobalInterruptEnable - * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable - * @arg kI2C_SdaTimeoutInterruptEnable - */ -void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); - -/*! - * @brief Disables I2C interrupt requests. - * - * @param base I2C base pointer - * @param mask interrupt source - * The parameter can be combination of the following source if defined: - * @arg kI2C_GlobalInterruptEnable - * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable - * @arg kI2C_SdaTimeoutInterruptEnable - */ -void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); - -/*! - * @name DMA Control - * @{ - */ -#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT -/*! - * @brief Enables/disables the I2C DMA interrupt. - * - * @param base I2C base pointer - * @param enable true to enable, false to disable -*/ -static inline void I2C_EnableDMA(I2C_Type *base, bool enable) -{ - if (enable) - { - base->C1 |= I2C_C1_DMAEN_MASK; - } - else - { - base->C1 &= ~I2C_C1_DMAEN_MASK; - } -} - -#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ - -/*! - * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address - * for I2C DMA transfer configuration. - * - * @param base I2C base pointer - * @return data register address - */ -static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base) -{ - return (uint32_t)(&(base->D)); -} - -/* @} */ -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Sets the I2C master transfer baud rate. - * - * @param base I2C base pointer - * @param baudRate_Bps the baud rate value in bps - * @param srcClock_Hz Source clock - */ -void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sends a START on the I2C bus. - * - * This function is used to initiate a new master mode transfer by sending the START signal. - * The slave address is sent following the I2C START signal. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy. - */ -status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * @retval kStatus_Success Successfully send the stop signal. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterStop(I2C_Type *base); - -/*! - * @brief Sends a REPEATED START on the I2C bus. - * - * @param base I2C peripheral base pointer - * @param address 7-bit slave device address. - * @param direction Master transfer directions(transmit/receive). - * @retval kStatus_Success Successfully send the start signal. - * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. - */ -status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); - -/*! - * @brief Performs a polling send transaction on the I2C bus. - * - * @param base The I2C peripheral base pointer. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag -* to issue a stop and kI2C_TransferNoStop to not send a stop. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags); - -/*! - * @brief Performs a polling receive transaction on the I2C bus. - * - * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. - * Without stopping the bus prior for the final read, the bus issues another read, resulting - * in garbage data being read into the data register. - * - * @param base I2C peripheral base pointer. - * @param rxBuff The pointer to the data to store the received data. - * @param rxSize The length in bytes of the data to be received. - * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag -* to issue a stop and kI2C_TransferNoStop to not send a stop. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. - */ -status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags); - -/*! - * @brief Performs a polling send transaction on the I2C bus. - * - * @param base The I2C peripheral base pointer. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transaction on the I2C bus. - * - * @param base I2C peripheral base pointer. - * @param rxBuff The pointer to the data to store the received data. - * @param rxSize The length in bytes of the data to be received. - */ -void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to arbitration lost or receiving a NAK. - * - * @param base I2C peripheral base address. - * @param xfer Pointer to the transfer structure. - * @retval kStatus_Success Successfully complete the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the I2C handle which is used in transactional functions. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure to store the transfer state. - * @param callback pointer to user callback function. - * @param userData user parameter passed to the callback function. - */ -void I2C_MasterTransferCreateHandle(I2C_Type *base, - i2c_master_handle_t *handle, - i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a master interrupt non-blocking transfer on the I2C bus. - * - * @note Calling the API returns immediately after transfer initiates. The user needs - * to call I2C_MasterGetTransferCount to poll the transfer status to check whether - * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer - * is finished. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. - * @param xfer pointer to i2c_master_transfer_t structure. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_I2C_Busy Previous transmission still not finished. - * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. - */ -status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Gets the master transfer status during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Aborts an interrupt non-blocking transfer early. - * - * @note This API can be called at any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_master_handle_t structure which stores the transfer state - */ -void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); - -/*! - * @brief Master interrupt handler. - * - * @param base I2C base pointer. - * @param i2cHandle pointer to i2c_master_handle_t structure. - */ -void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); - -/*! - * @brief Initializes the I2C handle which is used in transactional functions. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. - * @param callback pointer to user callback function. - * @param userData user parameter passed to the callback function. - */ -void I2C_SlaveTransferCreateHandle(I2C_Type *base, - i2c_slave_handle_t *handle, - i2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ -status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Aborts the slave transfer. - * - * @note This API can be called at any time to stop slave for handling the bus events. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. - */ -void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); - -/*! - * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. - * - * @param base I2C base pointer. - * @param handle pointer to i2c_slave_handle_t structure. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); - -/*! - * @brief Slave interrupt handler. - * - * @param base I2C base pointer. - * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state - */ -void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ - -#endif /* _FSL_I2C_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_edma.c b/third_party/nxp/MKW41Z4/drivers/fsl_i2c_edma.c deleted file mode 100644 index 28a415e07..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_edma.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*base, false); - - /* Send stop if kI2C_TransferNoStop flag is not asserted. */ - if (!(i2cPrivateHandle->handle->transfer.flags & kI2C_TransferNoStopFlag)) - { - if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) - { - /* Change to send NAK at the last byte. */ - i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; - - /* Wait the last data to be received. */ - while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Send stop signal. */ - result = I2C_MasterStop(i2cPrivateHandle->base); - - /* Read the last data byte. */ - *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = - i2cPrivateHandle->base->D; - } - else - { - /* Wait the last data to be sent. */ - while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Send stop signal. */ - result = I2C_MasterStop(i2cPrivateHandle->base); - } - } - else - { - if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) - { - /* Change to send NAK at the last byte. */ - i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; - - /* Wait the last data to be received. */ - while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) - { - } - - /* Change direction to send. */ - i2cPrivateHandle->base->C1 |= I2C_C1_TX_MASK; - - /* Read the last data byte. */ - *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = - i2cPrivateHandle->base->D; - } - } - - i2cPrivateHandle->handle->state = kIdleState; - - if (i2cPrivateHandle->handle->completionCallback) - { - i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result, - i2cPrivateHandle->handle->userData); - } -} - -static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check arbitration lost. */ - if (status & kI2C_ArbitrationLostFlag) - { - /* Clear arbitration lost flag. */ - base->S = kI2C_ArbitrationLostFlag; - result = kStatus_I2C_ArbitrationLost; - } - /* Check NAK */ - else if (status & kI2C_ReceiveNakFlag) - { - result = kStatus_I2C_Nak; - } - else - { - } - - return result; -} - -static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base, - i2c_master_edma_handle_t *handle, - i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - status_t result = kStatus_Success; - - if (handle->state != kIdleState) - { - return kStatus_I2C_Busy; - } - else - { - i2c_direction_t direction = xfer->direction; - - /* Init the handle member. */ - handle->transfer = *xfer; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - handle->state = kTransferDataState; - - /* Clear all status before transfer. */ - I2C_MasterClearStatusFlags(base, kClearFlags); - - /* Change to send write address when it's a read operation with command. */ - if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) - { - direction = kI2C_Write; - } - - /* If repeated start is requested, send repeated start. */ - if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); - } - else /* For normal transfer, send start. */ - { - result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); - } - - if (result) - { - return result; - } - - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - /* Return if error. */ - if (result) - { - if (result == kStatus_I2C_Nak) - { - result = kStatus_I2C_Addr_Nak; - - if (I2C_MasterStop(base) != kStatus_Success) - { - result = kStatus_I2C_Timeout; - } - - if (handle->completionCallback) - { - (handle->completionCallback)(base, handle, result, handle->userData); - } - } - - return result; - } - - /* Send subaddress. */ - if (handle->transfer.subaddressSize) - { - do - { - /* Clear interrupt pending flag. */ - base->S = kI2C_IntPendingFlag; - - handle->transfer.subaddressSize--; - base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - return result; - } - - } while ((handle->transfer.subaddressSize > 0) && (result == kStatus_Success)); - - if (handle->transfer.direction == kI2C_Read) - { - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send repeated start and slave address. */ - result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); - - if (result) - { - return result; - } - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Check if there's transfer error. */ - result = I2C_CheckAndClearError(base, base->S); - - if (result) - { - return result; - } - } - } - - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - } - - return result; -} - -static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle) -{ - edma_transfer_config_t transfer_config; - - if (handle->transfer.direction == kI2C_Read) - { - transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base); - transfer_config.destAddr = (uint32_t)(handle->transfer.data); - transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); - transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.srcOffset = 0; - transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.destOffset = 1; - transfer_config.minorLoopBytes = 1; - } - else - { - transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1); - transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base); - transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); - transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.srcOffset = 1; - transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; - transfer_config.destOffset = 0; - transfer_config.minorLoopBytes = 1; - } - - /* Store the initially configured eDMA minor byte transfer count into the I2C handle */ - handle->nbytes = transfer_config.minorLoopBytes; - - EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config); - EDMA_StartTransfer(handle->dmaHandle); -} - -void I2C_MasterCreateEDMAHandle(I2C_Type *base, - i2c_master_edma_handle_t *handle, - i2c_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaHandle) -{ - assert(handle); - assert(edmaHandle); - - uint32_t instance = I2C_GetInstance(base); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set the user callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Set the base for the handle. */ - base = base; - - /* Set the handle for EDMA. */ - handle->dmaHandle = edmaHandle; - - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; - - EDMA_SetCallback(edmaHandle, (edma_callback)I2C_MasterTransferCallbackEDMA, &s_edmaPrivateHandle[instance]); -} - -status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - status_t result; - uint8_t tmpReg; - volatile uint8_t dummy = 0; - - /* Add this to avoid build warning. */ - dummy++; - - /* Disable dma xfer. */ - I2C_EnableDMA(base, false); - - /* Send address and command buffer(if there is), until senddata phase or receive data phase. */ - result = I2C_InitTransferStateMachineEDMA(base, handle, xfer); - - if (result) - { - /* Send stop if received Nak. */ - if (result == kStatus_I2C_Nak) - { - if (I2C_MasterStop(base) != kStatus_Success) - { - result = kStatus_I2C_Timeout; - } - } - - /* Reset the state to idle state. */ - handle->state = kIdleState; - - return result; - } - - /* Configure dma transfer. */ - /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read, - need to send stop before reading the last byte, so the dma transfer size should - be (xSize - 1). */ - if (handle->transfer.dataSize > 1) - { - I2C_MasterTransferEDMAConfig(base, handle); - if (handle->transfer.direction == kI2C_Read) - { - /* Change direction for receive. */ - base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - - /* Read dummy to release the bus. */ - dummy = base->D; - - /* Enabe dma transfer. */ - I2C_EnableDMA(base, true); - } - else - { - /* Enabe dma transfer. */ - I2C_EnableDMA(base, true); - - /* Send the first data. */ - base->D = *handle->transfer.data; - } - } - else /* If transfer size is 1, use polling method. */ - { - if (handle->transfer.direction == kI2C_Read) - { - tmpReg = base->C1; - - /* Change direction to Rx. */ - tmpReg &= ~I2C_C1_TX_MASK; - - /* Configure send NAK */ - tmpReg |= I2C_C1_TXAK_MASK; - - base->C1 = tmpReg; - - /* Read dummy to release the bus. */ - dummy = base->D; - } - else - { - base->D = *handle->transfer.data; - } - - /* Wait until data transfer complete. */ - while (!(base->S & kI2C_IntPendingFlag)) - { - } - - /* Clear pending flag. */ - base->S = kI2C_IntPendingFlag; - - /* Send stop if kI2C_TransferNoStop flag is not asserted. */ - if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) - { - result = I2C_MasterStop(base); - } - else - { - /* Change direction to send. */ - base->C1 |= I2C_C1_TX_MASK; - } - - /* Read the last byte of data. */ - if (handle->transfer.direction == kI2C_Read) - { - *handle->transfer.data = base->D; - } - - /* Reset the state to idle. */ - handle->state = kIdleState; - } - - return result; -} - -status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count) -{ - assert(handle->dmaHandle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - if (kIdleState != handle->state) - { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); - } - else - { - *count = handle->transferSize; - } - - return kStatus_Success; -} - -void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle) -{ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable dma transfer. */ - I2C_EnableDMA(base, false); - - /* Reset the state to idle. */ - handle->state = kIdleState; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_edma.h b/third_party/nxp/MKW41Z4/drivers/fsl_i2c_edma.h deleted file mode 100644 index 40cb648ea..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_edma.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_I2C_DMA_H_ -#define _FSL_I2C_DMA_H_ - -#include "fsl_i2c.h" -#include "fsl_dmamux.h" -#include "fsl_edma.h" - -/*! - * @addtogroup i2c_edma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief I2C master eDMA handle typedef. */ -typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t; - -/*! @brief I2C master eDMA transfer callback typedef. */ -typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base, - i2c_master_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief I2C master eDMA transfer structure. */ -struct _i2c_master_edma_handle -{ - i2c_master_transfer_t transfer; /*!< I2C master transfer structure. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t state; /*!< I2C master transfer status. */ - edma_handle_t *dmaHandle; /*!< The eDMA handler used. */ - i2c_master_edma_transfer_callback_t - completionCallback; /*!< A callback function called after the eDMA transfer is finished. */ - void *userData; /*!< A callback parameter passed to the callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name I2C Block eDMA Transfer Operation - * @{ - */ - -/*! - * @brief Initializes the I2C handle which is used in transcational functions. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - * @param callback A pointer to the user callback function. - * @param userData A user parameter passed to the callback function. - * @param edmaHandle eDMA handle pointer. - */ -void I2C_MasterCreateEDMAHandle(I2C_Type *base, - i2c_master_edma_handle_t *handle, - i2c_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaHandle); - -/*! - * @brief Performs a master eDMA non-blocking transfer on the I2C bus. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - * @param xfer A pointer to the transfer structure of i2c_master_transfer_t. - * @retval kStatus_Success Sucessfully completed the data transmission. - * @retval kStatus_I2C_Busy A previous transmission is still not finished. - * @retval kStatus_I2C_Timeout Transfer error, waits for a signal timeout. - * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. - * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. - */ -status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer); - -/*! - * @brief Gets a master transfer status during the eDMA non-blocking transfer. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - * @param count A number of bytes transferred by the non-blocking transaction. - */ -status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count); - -/*! - * @brief Aborts a master eDMA non-blocking transfer early. - * - * @param base I2C peripheral base address. - * @param handle A pointer to the i2c_master_edma_handle_t structure. - */ -void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle); - -/* @} */ -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ -#endif /*_FSL_I2C_DMA_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_freertos.c b/third_party/nxp/MKW41Z4/drivers/fsl_i2c_freertos.c deleted file mode 100644 index e622fbe8f..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_freertos.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_i2c_freertos.h" - -static void I2C_RTOS_Callback(I2C_Type *base, i2c_master_handle_t *drv_handle, status_t status, void *userData) -{ - i2c_rtos_handle_t *handle = (i2c_rtos_handle_t *)userData; - BaseType_t reschedule; - handle->async_status = status; - xSemaphoreGiveFromISR(handle->semaphore, &reschedule); - portYIELD_FROM_ISR(reschedule); -} - -status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, - I2C_Type *base, - const i2c_master_config_t *masterConfig, - uint32_t srcClock_Hz) -{ - if (handle == NULL) - { - return kStatus_InvalidArgument; - } - - if (base == NULL) - { - return kStatus_InvalidArgument; - } - - memset(handle, 0, sizeof(i2c_rtos_handle_t)); -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->mutex = xSemaphoreCreateMutexStatic(&handle->mutexBuffer); -#else - handle->mutex = xSemaphoreCreateMutex(); -#endif - if (handle->mutex == NULL) - { - return kStatus_Fail; - } -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->semaphore = xSemaphoreCreateBinaryStatic(&handle->semaphoreBuffer); -#else - handle->semaphore = xSemaphoreCreateBinary(); -#endif - if (handle->semaphore == NULL) - { - vSemaphoreDelete(handle->mutex); - return kStatus_Fail; - } - - handle->base = base; - - I2C_MasterInit(handle->base, masterConfig, srcClock_Hz); - I2C_MasterTransferCreateHandle(base, &handle->drv_handle, I2C_RTOS_Callback, (void *)handle); - - return kStatus_Success; -} - -status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle) -{ - I2C_MasterDeinit(handle->base); - - vSemaphoreDelete(handle->semaphore); - vSemaphoreDelete(handle->mutex); - - return kStatus_Success; -} - -status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer) -{ - status_t status; - - /* Lock resource mutex */ - if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) - { - return kStatus_I2C_Busy; - } - - status = I2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); - if (status != kStatus_Success) - { - xSemaphoreGive(handle->mutex); - return status; - } - - /* Wait for transfer to finish */ - xSemaphoreTake(handle->semaphore, portMAX_DELAY); - - /* Unlock resource mutex */ - xSemaphoreGive(handle->mutex); - - /* Return status captured by callback function */ - return handle->async_status; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_freertos.h b/third_party/nxp/MKW41Z4/drivers/fsl_i2c_freertos.h deleted file mode 100644 index 52ed2d0a9..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_i2c_freertos.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_I2C_FREERTOS_H__ -#define __FSL_I2C_FREERTOS_H__ - -#include "FreeRTOSConfig.h" -#include "FreeRTOS.h" -#include "portable.h" -#include "semphr.h" - -#include "fsl_i2c.h" - -/*! - * @addtogroup i2c_freertos_driver I2C FreeRTOS driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @cond RTOS_PRIVATE - * @brief I2C FreeRTOS handle - */ -typedef struct _i2c_rtos_handle -{ - I2C_Type *base; /*!< I2C base address */ - i2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */ - status_t async_status; /*!< Transactional state of the underlying driver */ - SemaphoreHandle_t mutex; /*!< A mutex to lock the handle during a transfer */ - SemaphoreHandle_t semaphore; /*!< A semaphore to notify and unblock task when the transfer ends */ -#if (configSUPPORT_STATIC_ALLOCATION == 1) - StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ - StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */ -#endif -} i2c_rtos_handle_t; -/*! \endcond */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name I2C RTOS Operation - * @{ - */ - -/*! - * @brief Initializes I2C. - * - * This function initializes the I2C module and the related RTOS context. - * - * @param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context. - * @param base The pointer base address of the I2C instance to initialize. - * @param masterConfig The configuration structure to set-up I2C in master mode. - * @param srcClock_Hz The frequency of an input clock of the I2C module. - * @return status of the operation. - */ -status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, - I2C_Type *base, - const i2c_master_config_t *masterConfig, - uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes the I2C. - * - * This function deinitializes the I2C module and the related RTOS context. - * - * @param handle The RTOS I2C handle. - */ -status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle); - -/*! - * @brief Performs the I2C transfer. - * - * This function performs the I2C transfer according to the data given in the transfer structure. - * - * @param handle The RTOS I2C handle. - * @param transfer A structure specifying the transfer parameters. - * @return status of the operation. - */ -status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer); - -/*! - * @} - */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* __FSL_I2C_FREERTOS_H__ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_llwu.c b/third_party/nxp/MKW41Z4/drivers/fsl_llwu.c deleted file mode 100644 index 74b1001a8..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_llwu.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_llwu.h" - -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) -void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - volatile uint32_t *regBase; - uint32_t regOffset; - uint32_t reg; - - switch (pinIndex >> 4U) - { - case 0U: - regBase = &base->PE1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 1U: - regBase = &base->PE2; - break; -#endif - default: - regBase = NULL; - break; - } -#else - volatile uint8_t *regBase; - uint8_t regOffset; - uint8_t reg; - switch (pinIndex >> 2U) - { - case 0U: - regBase = &base->PE1; - break; - case 1U: - regBase = &base->PE2; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 2U: - regBase = &base->PE3; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) - case 3U: - regBase = &base->PE4; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 4U: - regBase = &base->PE5; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) - case 5U: - regBase = &base->PE6; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 6U: - regBase = &base->PE7; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) - case 7U: - regBase = &base->PE8; - break; -#endif - default: - regBase = NULL; - break; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ - - if (regBase) - { - reg = *regBase; -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - regOffset = ((pinIndex & 0x0FU) << 1U); -#else - regOffset = ((pinIndex & 0x03U) << 1U); -#endif - reg &= ~(0x3U << regOffset); - reg |= ((uint32_t)pinMode << regOffset); - *regBase = reg; - } -} - -bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->PF & (1U << pinIndex)); -#else - volatile uint8_t *regBase; - - switch (pinIndex >> 3U) - { -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - case 0U: - regBase = &base->PF1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->PF2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->PF3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->PF4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#else - case 0U: - regBase = &base->F1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->F2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->F3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->F4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_PF */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - return (bool)(*regBase & (1U << pinIndex % 8)); - } - else - { - return false; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - base->PF = (1U << pinIndex); -#else - volatile uint8_t *regBase; - switch (pinIndex >> 3U) - { -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - case 0U: - regBase = &base->PF1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->PF2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->PF3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->PF4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#else - case 0U: - regBase = &base->F1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->F2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->F3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->F4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_PF */ - default: - regBase = NULL; - break; - } - if (regBase) - { - *regBase = (1U << pinIndex % 8U); - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - uint32_t reg; - - reg = base->FILT; - reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U)); - reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT) - /* Clear the Filter Detect Flag */ - | LLWU_FILT_FILTF1_MASK) - << (filterIndex * 8U - 1U)); - base->FILT = reg; -#else - volatile uint8_t *regBase; - uint8_t reg; - - switch (filterIndex) - { - case 1: - regBase = &base->FILT1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - regBase = &base->FILT2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - regBase = &base->FILT3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - regBase = &base->FILT4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - reg = *regBase; - reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK); - reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT); - reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT); - /* Clear the Filter Detect Flag */ - reg |= LLWU_FILT1_FILTF_MASK; - *regBase = reg; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); -#else - bool status = false; - - switch (filterIndex) - { - case 1: - status = (base->FILT1 & LLWU_FILT1_FILTF_MASK); - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - status = (base->FILT2 & LLWU_FILT2_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - break; - } - - return status; -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - uint32_t reg; - - reg = base->FILT; - switch (filterIndex) - { - case 1: - reg |= LLWU_FILT_FILTF1_MASK; - break; - case 2: - reg |= LLWU_FILT_FILTF2_MASK; - break; - case 3: - reg |= LLWU_FILT_FILTF3_MASK; - break; - case 4: - reg |= LLWU_FILT_FILTF4_MASK; - break; - default: - break; - } - base->FILT = reg; -#else - volatile uint8_t *regBase; - uint8_t reg; - - switch (filterIndex) - { - case 1: - regBase = &base->FILT1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - regBase = &base->FILT2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - regBase = &base->FILT3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - regBase = &base->FILT4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - reg = *regBase; - reg |= LLWU_FILT1_FILTF_MASK; - *regBase = reg; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) -{ - uint8_t reg; - - reg = base->RST; - reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); - reg |= - (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); - base->RST = reg; -} -#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_llwu.h b/third_party/nxp/MKW41Z4/drivers/fsl_llwu.h deleted file mode 100644 index d5a0037bb..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_llwu.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LLWU_H_ -#define _FSL_LLWU_H_ - -#include "fsl_common.h" - -/*! @addtogroup llwu */ -/*! @{ */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LLWU driver version 2.0.1. */ -#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief External input pin control modes - */ -typedef enum _llwu_external_pin_mode -{ - kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as a wakeup input. */ - kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with the rising edge detection. */ - kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with the falling edge detection.*/ - kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ -} llwu_external_pin_mode_t; - -/*! - * @brief Digital filter control modes - */ -typedef enum _llwu_pin_filter_mode -{ - kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ - kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ - kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ - kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ -} llwu_pin_filter_mode_t; - -#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) -/*! - * @brief IP version ID definition. - */ -typedef struct _llwu_version_id -{ - uint16_t feature; /*!< A feature specification number. */ - uint8_t minor; /*!< The minor version number. */ - uint8_t major; /*!< The major version number. */ -} llwu_version_id_t; -#endif /* FSL_FEATURE_LLWU_HAS_VERID */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) -/*! - * @brief IP parameter definition. - */ -typedef struct _llwu_param -{ - uint8_t filters; /*!< A number of the pin filter. */ - uint8_t dmas; /*!< A number of the wakeup DMA. */ - uint8_t modules; /*!< A number of the wakeup module. */ - uint8_t pins; /*!< A number of the wake up pin. */ -} llwu_param_t; -#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -/*! - * @brief An external input pin filter control structure - */ -typedef struct _llwu_external_pin_filter_mode -{ - uint32_t pinIndex; /*!< A pin number */ - llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ -} llwu_external_pin_filter_mode_t; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Low-Leakage Wakeup Unit Control APIs - * @{ - */ - -#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) -/*! - * @brief Gets the LLWU version ID. - * - * This function gets the LLWU version ID, including the major version number, - * the minor version number, and the feature specification number. - * - * @param base LLWU peripheral base address. - * @param versionId A pointer to the version ID structure. - */ -static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif /* FSL_FEATURE_LLWU_HAS_VERID */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) -/*! - * @brief Gets the LLWU parameter. - * - * This function gets the LLWU parameter, including a wakeup pin number, a module - * number, a DMA number, and a pin filter number. - * - * @param base LLWU peripheral base address. - * @param param A pointer to the LLWU parameter structure. - */ -static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) -{ - *((uint32_t *)param) = base->PARAM; -} -#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ - -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) -/*! - * @brief Sets the external input pin source mode. - * - * This function sets the external input pin source mode that is used - * as a wake up source. - * - * @param base LLWU peripheral base address. - * @param pinIndex A pin index to be enabled as an external wakeup source starting from 1. - * @param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t. - */ -void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); - -/*! - * @brief Gets the external wakeup source flag. - * - * This function checks the external pin flag to detect whether the MCU is - * woken up by the specific pin. - * - * @param base LLWU peripheral base address. - * @param pinIndex A pin index, which starts from 1. - * @return True if the specific pin is a wakeup source. - */ -bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); - -/*! - * @brief Clears the external wakeup source flag. - * - * This function clears the external wakeup source flag for a specific pin. - * - * @param base LLWU peripheral base address. - * @param pinIndex A pin index, which starts from 1. - */ -void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ - -#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) -/*! - * @brief Enables/disables the internal module source. - * - * This function enables/disables the internal module source mode that is used - * as a wake up source. - * - * @param base LLWU peripheral base address. - * @param moduleIndex A module index to be enabled as an internal wakeup source starting from 1. - * @param enable An enable or a disable setting - */ -static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) -{ - if (enable) - { - base->ME |= 1U << moduleIndex; - } - else - { - base->ME &= ~(1U << moduleIndex); - } -} - -/*! - * @brief Gets the external wakeup source flag. - * - * This function checks the external pin flag to detect whether the system is - * woken up by the specific pin. - * - * @param base LLWU peripheral base address. - * @param moduleIndex A module index, which starts from 1. - * @return True if the specific pin is a wake up source. - */ -static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) -{ -#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->MF & (1U << moduleIndex)); -#else - return (bool)(base->MF5 & (1U << moduleIndex)); -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -#else -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - return (bool)(base->F5 & (1U << moduleIndex)); -#else -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - return (bool)(base->PF3 & (1U << moduleIndex)); -#else - return (bool)(base->F3 & (1U << moduleIndex)); -#endif /* FSL_FEATURE_LLWU_HAS_PF */ -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_MF */ -} -#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ - -#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) -/*! - * @brief Enables/disables the internal module DMA wakeup source. - * - * This function enables/disables the internal DMA that is used as a wake up source. - * - * @param base LLWU peripheral base address. - * @param moduleIndex An internal module index which is used as a DMA request source, starting from 1. - * @param enable Enable or disable the DMA request source - */ -static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) -{ - if (enable) - { - base->DE |= 1U << moduleIndex; - } - else - { - base->DE &= ~(1U << moduleIndex); - } -} -#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -/*! - * @brief Sets the pin filter configuration. - * - * This function sets the pin filter configuration. - * - * @param base LLWU peripheral base address. - * @param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1. - * @param filterMode A filter mode configuration - */ -void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); - -/*! - * @brief Gets the pin filter configuration. - * - * This function gets the pin filter flag. - * - * @param base LLWU peripheral base address. - * @param filterIndex A pin filter index, which starts from 1. - * @return True if the flag is a source of the existing low-leakage power mode. - */ -bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); - -/*! - * @brief Clears the pin filter configuration. - * - * This function clears the pin filter flag. - * - * @param base LLWU peripheral base address. - * @param filterIndex A pin filter index to clear the flag, starting from 1. - */ -void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); - -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) -/*! - * @brief Sets the reset pin mode. - * - * This function determines how the reset pin is used as a low leakage mode exit source. - * - * @param pinEnable Enable reset the pin filter - * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode. - */ -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); -#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ -#endif /* _FSL_LLWU_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lptmr.c b/third_party/nxp/MKW41Z4/drivers/fsl_lptmr.c deleted file mode 100644 index 67b3b9785..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lptmr.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lptmr.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base LPTMR peripheral base address - * - * @return The LPTMR instance - */ -static uint32_t LPTMR_GetInstance(LPTMR_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPTMR bases for each instance. */ -static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPTMR clocks for each instance. */ -static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; - -#if defined(LPTMR_PERIPH_CLOCKS) -/* Array of LPTMR functional clock name. */ -static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPTMR_GetInstance(LPTMR_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lptmrBases); instance++) - { - if (s_lptmrBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lptmrBases)); - - return instance; -} - -void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPTMR_GetInstance(base); - - /* Ungate the LPTMR clock*/ - CLOCK_EnableClock(s_lptmrClocks[instance]); -#if defined(LPTMR_PERIPH_CLOCKS) - CLOCK_EnableClock(s_lptmrPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure the timers operation mode and input pin setup */ - base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | - LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); - - /* Configure the prescale value and clock source */ - base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | - LPTMR_PSR_PCS(config->prescalerClockSource)); -} - -void LPTMR_Deinit(LPTMR_Type *base) -{ - /* Disable the LPTMR and reset the internal logic */ - base->CSR &= ~LPTMR_CSR_TEN_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPTMR_GetInstance(base); - - /* Gate the LPTMR clock*/ - CLOCK_DisableClock(s_lptmrClocks[instance]); -#if defined(LPTMR_PERIPH_CLOCKS) - CLOCK_DisableClock(s_lptmrPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LPTMR_GetDefaultConfig(lptmr_config_t *config) -{ - assert(config); - - /* Use time counter mode */ - config->timerMode = kLPTMR_TimerModeTimeCounter; - /* Use input 0 as source in pulse counter mode */ - config->pinSelect = kLPTMR_PinSelectInput_0; - /* Pulse input pin polarity is active-high */ - config->pinPolarity = kLPTMR_PinPolarityActiveHigh; - /* Counter resets whenever TCF flag is set */ - config->enableFreeRunning = false; - /* Bypass the prescaler */ - config->bypassPrescaler = true; - /* LPTMR clock source */ - config->prescalerClockSource = kLPTMR_PrescalerClock_1; - /* Divide the prescaler clock by 2 */ - config->value = kLPTMR_Prescale_Glitch_0; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lptmr.h b/third_party/nxp/MKW41Z4/drivers/fsl_lptmr.h deleted file mode 100644 index 6cc909b31..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lptmr.h +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPTMR_H_ -#define _FSL_LPTMR_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lptmr - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ -/*@}*/ - -/*! @brief LPTMR pin selection used in pulse counter mode.*/ -typedef enum _lptmr_pin_select -{ - kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ - kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ - kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ - kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ -} lptmr_pin_select_t; - -/*! @brief LPTMR pin polarity used in pulse counter mode.*/ -typedef enum _lptmr_pin_polarity -{ - kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ - kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ -} lptmr_pin_polarity_t; - -/*! @brief LPTMR timer mode selection.*/ -typedef enum _lptmr_timer_mode -{ - kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ - kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ -} lptmr_timer_mode_t; - -/*! @brief LPTMR prescaler/glitch filter values*/ -typedef enum _lptmr_prescaler_glitch_value -{ - kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ - kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ - kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ - kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ - kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ - kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ - kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ - kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ - kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ - kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ - kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ - kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ - kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ - kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ - kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ - kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ -} lptmr_prescaler_glitch_value_t; - -/*! - * @brief LPTMR prescaler/glitch filter clock select. - * @note Clock connections are SoC-specific - */ -typedef enum _lptmr_prescaler_clock_select -{ - kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ - kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ - kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ - kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ -} lptmr_prescaler_clock_select_t; - -/*! @brief List of the LPTMR interrupts */ -typedef enum _lptmr_interrupt_enable -{ - kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ -} lptmr_interrupt_enable_t; - -/*! @brief List of the LPTMR status flags */ -typedef enum _lptmr_status_flags -{ - kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ -} lptmr_status_flags_t; - -/*! - * @brief LPTMR config structure - * - * This structure holds the configuration settings for the LPTMR peripheral. To initialize this - * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a - * pointer to your configuration structure instance. - * - * The configuration struct can be made constant so it resides in flash. - */ -typedef struct _lptmr_config -{ - lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ - lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ - lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ - bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow - False: counter is reset when the compare flag is set */ - bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */ - lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ - lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ -} lptmr_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation. - * - * @note This API should be called at the beginning of the application using the LPTMR driver. - * - * @param base LPTMR peripheral base address - * @param config A pointer to the LPTMR configuration structure. - */ -void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); - -/*! - * @brief Gates the LPTMR clock. - * - * @param base LPTMR peripheral base address - */ -void LPTMR_Deinit(LPTMR_Type *base); - -/*! - * @brief Fills in the LPTMR configuration structure with default settings. - * - * The default values are as follows. - * @code - * config->timerMode = kLPTMR_TimerModeTimeCounter; - * config->pinSelect = kLPTMR_PinSelectInput_0; - * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; - * config->enableFreeRunning = false; - * config->bypassPrescaler = true; - * config->prescalerClockSource = kLPTMR_PrescalerClock_1; - * config->value = kLPTMR_Prescale_Glitch_0; - * @endcode - * @param config A pointer to the LPTMR configuration structure. - */ -void LPTMR_GetDefaultConfig(lptmr_config_t *config); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t - */ -static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg |= mask; - base->CSR = reg; -} - -/*! - * @brief Disables the selected LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t. - */ -static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg &= ~mask; - base->CSR = reg; -} - -/*! - * @brief Gets the enabled LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t - */ -static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) -{ - return (base->CSR & LPTMR_CSR_TIE_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the LPTMR status flags. - * - * @param base LPTMR peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::lptmr_status_flags_t - */ -static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) -{ - return (base->CSR & LPTMR_CSR_TCF_MASK); -} - -/*! - * @brief Clears the LPTMR status flags. - * - * @param base LPTMR peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::lptmr_status_flags_t. - */ -static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) -{ - base->CSR |= mask; -} - -/*! @}*/ - -/*! - * @name Read and write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers counts from 0 until it equals the count value set here. The count value is written to - * the CMR register. - * - * @note - * 1. The TCF flag is set with the CNR equals the count provided here and then increments. - * 2. Call the utility macros provided in the fsl_common.h to convert to ticks. - * - * @param base LPTMR peripheral base address - * @param ticks A timer period in units of ticks, which should be equal or greater than 1. - */ -static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks) -{ - assert(ticks > 0); - base->CMR = ticks - 1; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value in a range from 0 to a - * timer period. - * - * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. - * - * @param base LPTMR peripheral base address - * - * @return The current counter value in ticks - */ -static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) -{ - /* Must first write any value to the CNR. This synchronizes and registers the current value - * of the CNR into a temporary register which can then be read - */ - base->CNR = 0U; - return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT); -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer. - * - * After calling this function, the timer counts up to the CMR register value. - * Each time the timer reaches the CMR value and then increments, it generates a - * trigger pulse and sets the timeout interrupt flag. An interrupt is also - * triggered if the timer interrupt is enabled. - * - * @param base LPTMR peripheral base address - */ -static inline void LPTMR_StartTimer(LPTMR_Type *base) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg |= LPTMR_CSR_TEN_MASK; - base->CSR = reg; -} - -/*! - * @brief Stops the timer. - * - * This function stops the timer and resets the timer's counter register. - * - * @param base LPTMR peripheral base address - */ -static inline void LPTMR_StopTimer(LPTMR_Type *base) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg &= ~LPTMR_CSR_TEN_MASK; - base->CSR = reg; -} - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPTMR_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart.c b/third_party/nxp/MKW41Z4/drivers/fsl_lpuart.c deleted file mode 100644 index 9a83b5698..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart.c +++ /dev/null @@ -1,1297 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpuart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* LPUART transfer state. */ -enum _lpuart_transfer_states -{ - kLPUART_TxIdle, /*!< TX idle. */ - kLPUART_TxBusy, /*!< TX busy. */ - kLPUART_RxIdle, /*!< RX idle. */ - kLPUART_RxBusy /*!< RX busy. */ -}; - -/* Typedef for interrupt handler. */ -typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the LPUART instance from peripheral base address. - * - * @param base LPUART peripheral base address. - * @return LPUART instance. - */ -uint32_t LPUART_GetInstance(LPUART_Type *base); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @userData handle LPUART handle pointer. - * @return Length of received data in RX ring buffer. - */ -static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Check whether the RX ring buffer is full. - * - * @userData handle LPUART handle pointer. - * @retval true RX ring buffer is full. - * @retval false RX ring buffer is not full. - */ -static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Write to TX register using non-blocking method. - * - * This function writes data to the TX register directly, upper layer must make - * sure the TX register is empty or TX FIFO has empty room before calling this function. - * - * @note This function does not check whether all the data has been sent out to bus, - * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is - * finished. - * - * @param base LPUART peripheral base address. - * @param data Start addresss of the data to write. - * @param length Size of the buffer to be sent. - */ -static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX register using non-blocking method. - * - * This function reads data from the TX register directly, upper layer must make - * sure the RX register is full or TX FIFO has data before calling this function. - * - * @param base LPUART peripheral base address. - * @param data Start addresss of the buffer to store the received data. - * @param length Size of the buffer. - */ -static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of LPUART handle. */ -static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT]; -/* Array of LPUART peripheral base address. */ -static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; -/* Array of LPUART IRQ number. */ -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS; -static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS; -#else -static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of LPUART clock name. */ -static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; - -#if defined(LPUART_PERIPH_CLOCKS) -/* Array of LPUART functional clock name. */ -static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* LPUART ISR for transactional APIs. */ -static lpuart_isr_t s_lpuartIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -uint32_t LPUART_GetInstance(LPUART_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpuartBases); instance++) - { - if (s_lpuartBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpuartBases)); - - return instance; -} - -static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - size_t size; - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - - return size; -} - -static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - bool full; - - if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) -{ - assert(data); - - size_t i; - - /* The Non Blocking write data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { - base->DATA = data[i]; - } -} - -static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - size_t i; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - /* The Non Blocking read data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (isSevenDataBits) - { - data[i] = (base->DATA & 0x7F); - } - else - { - data[i] = base->DATA; - } -#else - data[i] = base->DATA; -#endif - } -} - -status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) -{ - assert(config); - assert(config->baudRate_Bps); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); -#endif - - uint32_t temp; - uint16_t sbr, sbrTemp; - uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; - - /* This LPUART instantiation uses a slightly different baud rate calculation - * The idea is to use the best OSR (over-sampling rate) possible - * Note, OSR is typically hard-set to 16 in other LPUART instantiations - * loop to find the best OSR value possible, one that generates minimum baudDiff - * iterate through the rest of the supported values of OSR */ - - baudDiff = config->baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) - { - /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp)); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) - { - sbrTemp = 1; - } - /* Calculate the baud rate based on the temporary OSR and SBR values */ - calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); - - tempDiff = calculatedBaud - config->baudRate_Bps; - - /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) - { - tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); - sbrTemp++; - } - - if (tempDiff <= baudDiff) - { - baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculate OSR value */ - if (baudDiff > ((config->baudRate_Bps / 100) * 3)) - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_LPUART_BaudrateNotSupport; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPUART_GetInstance(base); - - /* Enable lpuart clock */ - CLOCK_EnableClock(s_lpuartClock[instance]); -#if defined(LPUART_PERIPH_CLOCKS) - CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL - /*Reset all internal logic and registers, except the Global Register */ - LPUART_SoftwareReset(base); -#else - /* Disable LPUART TX RX before setting. */ - base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); -#endif - - temp = base->BAUD; - - /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. - * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) - { - temp |= LPUART_BAUD_BOTHEDGE_MASK; - } - - /* program the osr value (bit value is one less than actual value) */ - temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); - - /* write the sbr value to the BAUD registers */ - temp &= ~LPUART_BAUD_SBR_MASK; - base->BAUD = temp | LPUART_BAUD_SBR(sbr); - - /* Set bit count and parity mode. */ - base->BAUD &= ~LPUART_BAUD_M10_MASK; - - temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); - - temp |= (uint8_t)config->parityMode; - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (kLPUART_SevenDataBits == config->dataBitsCount) - { - if (kLPUART_ParityDisabled != config->parityMode) - { - temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ - } - else - { - temp |= LPUART_CTRL_M7_MASK; - } - } - else -#endif - { - if (kLPUART_ParityDisabled != config->parityMode) - { - temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ - } - } - - base->CTRL = temp; - -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - /* set stop bit per char */ - temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; - base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Set tx/rx WATER watermark */ - base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark); - - /* Enable tx/rx FIFO */ - base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); - - /* Flush FIFO */ - base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); -#endif - - /* Clear all status flags */ - temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); - -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp |= LPUART_STAT_LBKDIF_MASK; -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); -#endif - - /* Set data bits order. */ - if (config->isMsb) - { - temp |= LPUART_STAT_MSBF_MASK; - } - else - { - temp &= ~LPUART_STAT_MSBF_MASK; - } - - base->STAT |= temp; - - /* Enable TX/RX base on configure structure. */ - temp = base->CTRL; - if (config->enableTx) - { - temp |= LPUART_CTRL_TE_MASK; - } - - if (config->enableRx) - { - temp |= LPUART_CTRL_RE_MASK; - } - - base->CTRL = temp; - - return kStatus_Success; -} -void LPUART_Deinit(LPUART_Type *base) -{ - uint32_t temp; - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Wait tx FIFO send out*/ - while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) - { - } -#endif - /* Wait last char shoft out */ - while (0 == (base->STAT & LPUART_STAT_TC_MASK)) - { - } - - /* Clear all status flags */ - temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); - -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp |= LPUART_STAT_LBKDIF_MASK; -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); -#endif - - base->STAT |= temp; - - /* Disable the module. */ - base->CTRL = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = LPUART_GetInstance(base); - - /* Disable lpuart clock */ - CLOCK_DisableClock(s_lpuartClock[instance]); - -#if defined(LPUART_PERIPH_CLOCKS) - CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LPUART_GetDefaultConfig(lpuart_config_t *config) -{ - assert(config); - - config->baudRate_Bps = 115200U; - config->parityMode = kLPUART_ParityDisabled; - config->dataBitsCount = kLPUART_EightDataBits; - config->isMsb = false; -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - config->stopBitCount = kLPUART_OneStopBit; -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - config->txFifoWatermark = 0; - config->rxFifoWatermark = 0; -#endif - config->enableTx = false; - config->enableRx = false; -} - -status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - assert(baudRate_Bps); - - uint32_t temp, oldCtrl; - uint16_t sbr, sbrTemp; - uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; - - /* This LPUART instantiation uses a slightly different baud rate calculation - * The idea is to use the best OSR (over-sampling rate) possible - * Note, OSR is typically hard-set to 16 in other LPUART instantiations - * loop to find the best OSR value possible, one that generates minimum baudDiff - * iterate through the rest of the supported values of OSR */ - - baudDiff = baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) - { - /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp)); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) - { - sbrTemp = 1; - } - /* Calculate the baud rate based on the temporary OSR and SBR values */ - calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); - - tempDiff = calculatedBaud - baudRate_Bps; - - /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) - { - tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); - sbrTemp++; - } - - if (tempDiff <= baudDiff) - { - baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculate OSR value */ - if (baudDiff < ((baudRate_Bps / 100) * 3)) - { - /* Store CTRL before disable Tx and Rx */ - oldCtrl = base->CTRL; - - /* Disable LPUART TX RX before setting. */ - base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); - - temp = base->BAUD; - - /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. - * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) - { - temp |= LPUART_BAUD_BOTHEDGE_MASK; - } - - /* program the osr value (bit value is one less than actual value) */ - temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); - - /* write the sbr value to the BAUD registers */ - temp &= ~LPUART_BAUD_SBR_MASK; - base->BAUD = temp | LPUART_BAUD_SBR(sbr); - - /* Restore CTRL. */ - base->CTRL = oldCtrl; - - return kStatus_Success; - } - else - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_LPUART_BaudrateNotSupport; - } -} - -void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) -{ - base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | - ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); -#endif - mask &= 0xFFFFFF00U; - base->CTRL |= mask; -} - -void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) -{ - base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & - ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); -#endif - mask &= 0xFFFFFF00U; - base->CTRL &= ~mask; -} - -uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) -{ - uint32_t temp; - temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; -#endif - temp |= (base->CTRL & 0xFF0C000); - - return temp; -} - -uint32_t LPUART_GetStatusFlags(LPUART_Type *base) -{ - uint32_t temp; - temp = base->STAT; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp |= (base->FIFO & - (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> - 16; -#endif - return temp; -} - -status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) -{ - uint32_t temp; - status_t status; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp = (uint32_t)base->FIFO; - temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); - temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); - base->FIFO = temp; -#endif - temp = (uint32_t)base->STAT; -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK)); - temp |= mask & LPUART_STAT_LBKDIF_MASK; -#endif - temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK)); - temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK)); - temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK); -#endif - base->STAT = temp; - /* If some flags still pending. */ - if (mask & LPUART_GetStatusFlags(base)) - { - /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, - kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, - kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, - kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ - status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ - } - else - { - status = kStatus_Success; - } - - return status; -} - -void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) -{ - assert(data); - - /* This API can only ensure that the data is written into the data buffer but can't - ensure all data in the data buffer are sent into the transmit shift buffer. */ - while (length--) - { - while (!(base->STAT & LPUART_STAT_TDRE_MASK)) - { - } - base->DATA = *(data++); - } -} - -status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - uint32_t statusFlag; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - while (length--) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) -#else - while (!(base->STAT & LPUART_STAT_RDRF_MASK)) -#endif - { - statusFlag = LPUART_GetStatusFlags(base); - - if (statusFlag & kLPUART_RxOverrunFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); - return kStatus_LPUART_RxHardwareOverrun; - } - - if (statusFlag & kLPUART_NoiseErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag); - return kStatus_LPUART_NoiseError; - } - - if (statusFlag & kLPUART_FramingErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag); - return kStatus_LPUART_FramingError; - } - - if (statusFlag & kLPUART_ParityErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag); - return kStatus_LPUART_ParityError; - } - } -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (isSevenDataBits) - { - *(data++) = (base->DATA & 0x7F); - } - else - { - *(data++) = base->DATA; - } -#else - *(data++) = base->DATA; -#endif - } - - return kStatus_Success; -} - -void LPUART_TransferCreateHandle(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - /* Zero the handle. */ - memset(handle, 0, sizeof(lpuart_handle_t)); - - /* Set the TX/RX state. */ - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; - - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - /* Initial seven data bits flag */ - handle->isSevenDataBits = isSevenDataBits; -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Note: - Take care of the RX FIFO, RX interrupt request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - RX interrupt because the water mark is 2. - */ - base->WATER &= (~LPUART_WATER_RXWATER_MASK); -#endif - - /* Get instance from peripheral base address. */ - instance = LPUART_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_lpuartHandle[instance] = handle; - - s_lpuartIsr = LPUART_TransferHandleIRQ; - -/* Enable interrupt in NVIC. */ -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ - EnableIRQ(s_lpuartRxIRQ[instance]); - EnableIRQ(s_lpuartTxIRQ[instance]); -#else - EnableIRQ(s_lpuartIRQ[instance]); -#endif -} - -void LPUART_TransferStartRingBuffer(LPUART_Type *base, - lpuart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize) -{ - assert(handle); - assert(ringBuffer); - - /* Setup the ring buffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - - /* Enable the interrupt to accept the data when user need the ring buffer. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); -} - -void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - if (handle->rxState == kLPUART_RxIdle) - { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - status_t status; - - /* Return error if current TX busy. */ - if (kLPUART_TxBusy == handle->txState) - { - status = kStatus_LPUART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kLPUART_TxBusy; - - /* Enable transmiter interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable); - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable); - - handle->txDataSize = 0; - handle->txState = kLPUART_TxIdle; -} - -status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kLPUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_t *xfer, - size_t *receivedBytes) -{ - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - uint32_t i; - status_t status; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to lpuart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to lpuart handle, receive data - to this empty space and trigger callback when finished. */ - - if (kLPUART_RxBusy == handle->rxState) - { - status = kStatus_LPUART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0; - - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable LPUART RX IRQ, protect ring buffer. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); - - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - - bytesToReceive -= bytesToCopy; - - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to LPUART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; - } - /* Enable LPUART RX IRQ if previously enabled. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); - - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; - - /* Enable RX interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable RX interrupt. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - handle->rxDataSize = 0U; - handle->rxState = kLPUART_RxIdle; -} - -status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kLPUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - uint8_t count; - uint8_t tempCount; - - /* If RX overrun. */ - if (LPUART_STAT_OR_MASK & base->STAT) - { - /* Clear overrun flag, otherwise the RX does not work. */ - base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); - } - } - - /* Receive data register full */ - if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL)) - { -/* Get the size that can be stored into buffer for this interrupt. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); -#else - count = 1; -#endif - - /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ - while ((count) && (handle->rxDataSize)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->rxDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to read the data from the registers. */ - LPUART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData += tempCount; - handle->rxDataSize -= tempCount; - count -= tempCount; - - /* If all the data required for upper layer is ready, trigger callback. */ - if (!handle->rxDataSize) - { - handle->rxState = kLPUART_RxIdle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } - - /* If use RX ring buffer, receive data to ring buffer. */ - if (handle->rxRingBuffer) - { - while (count--) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (LPUART_TransferIsRxRingBufferFull(base, handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); - } - } - - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (LPUART_TransferIsRxRingBufferFull(base, handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - -/* Read data. */ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (handle->isSevenDataBits) - { - handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F); - } - else - { - handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; - } -#else - handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; -#endif - - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - /* If no receive requst pending, stop RX interrupt. */ - else if (!handle->rxDataSize) - { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - else - { - } - } - - /* Send data register empty and the interrupt is enabled. */ - if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK)) - { -/* Get the bytes that available at this moment. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) - - ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); -#else - count = 1; -#endif - - while ((count) && (handle->txDataSize)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->txDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to write the data to the registers. */ - LPUART_WriteNonBlocking(base, handle->txData, tempCount); - handle->txData += tempCount; - handle->txDataSize -= tempCount; - count -= tempCount; - - /* If all the data are written to data register, notify user with the callback, then TX finished. */ - if (!handle->txDataSize) - { - handle->txState = kLPUART_TxIdle; - - /* Disable TX register empty interrupt. */ - base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); - } - } - } - } -} - -void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) -{ - /* To be implemented by User. */ -} - -#if defined(LPUART0) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART0_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -} -void LPUART0_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -} -#else -void LPUART0_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -} -#endif -#endif - -#if defined(LPUART1) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART1_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -} -void LPUART1_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -} -#else -void LPUART1_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -} -#endif -#endif - -#if defined(LPUART2) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART2_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -} -void LPUART2_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -} -#else -void LPUART2_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -} -#endif -#endif - -#if defined(LPUART3) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART3_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -} -void LPUART3_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -} -#else -void LPUART3_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -} -#endif -#endif - -#if defined(LPUART4) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART4_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -} -void LPUART4_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -} -#else -void LPUART4_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -} -#endif -#endif - -#if defined(LPUART5) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART5_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -} -void LPUART5_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -} -#else -void LPUART5_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -} -#endif -#endif diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart.h b/third_party/nxp/MKW41Z4/drivers/fsl_lpuart.h deleted file mode 100644 index 0c60f82d8..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart.h +++ /dev/null @@ -1,814 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPUART_H_ -#define _FSL_LPUART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpuart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPUART driver version 2.2.3. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) -/*@}*/ - -/*! @brief Error codes for the LPUART driver. */ -enum _lpuart_status -{ - kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ - kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ - kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ - kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ - kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ - kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ - kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ - kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ - kStatus_LPUART_RxRingBufferOverrun = - MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ - kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ - kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ - kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ - kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ - kStatus_LPUART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief LPUART parity mode. */ -typedef enum _lpuart_parity_mode -{ - kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} lpuart_parity_mode_t; - -/*! @brief LPUART data bits count. */ -typedef enum _lpuart_data_bits -{ - kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ -#endif -} lpuart_data_bits_t; - -/*! @brief LPUART stop bit count. */ -typedef enum _lpuart_stop_bit_count -{ - kLPUART_OneStopBit = 0U, /*!< One stop bit */ - kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ -} lpuart_stop_bit_count_t; - -/*! - * @brief LPUART interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all LPUART interrupt configurations. - */ -enum _lpuart_interrupt_enable -{ -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ -#endif - kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ - kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ - kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ - kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ - kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ - kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ - kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ - kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ - kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ - kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ -#endif -}; - -/*! - * @brief LPUART status flags. - * - * This provides constants for the LPUART status flags for use in the LPUART functions. - */ -enum _lpuart_flags -{ - kLPUART_TxDataRegEmptyFlag = - (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ - kLPUART_TransmissionCompleteFlag = - (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ - kLPUART_RxDataRegFullFlag = - (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ - kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ - kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is - read from receive register */ - kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these - samples differ, noise flag sets */ - kLPUART_FramingErrorFlag = - (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ - kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char - detected and LIN circuit enabled */ -#endif - kLPUART_RxActiveEdgeFlag = - (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ - kLPUART_RxActiveFlag = - (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ - kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS - kLPUART_NoiseErrorInRxDataRegFlag = - (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ - kLPUART_ParityErrorInRxDataRegFlag = - (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ - kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ - kLPUART_TxFifoOverflowFlag = - (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ - kLPUART_RxFifoUnderflowFlag = - (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ -#endif -}; - -/*! @brief LPUART configuration structure. */ -typedef struct _lpuart_config -{ - uint32_t baudRate_Bps; /*!< LPUART baud rate */ - lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ - bool isMsb; /*!< Data bits order, LSB (default), MSB */ -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - uint8_t txFifoWatermark; /*!< TX FIFO watermark */ - uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ -#endif - bool enableTx; /*!< Enable TX */ - bool enableRx; /*!< Enable RX */ -} lpuart_config_t; - -/*! @brief LPUART transfer structure. */ -typedef struct _lpuart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} lpuart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _lpuart_handle lpuart_handle_t; - -/*! @brief LPUART transfer callback function. */ -typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); - -/*! @brief LPUART handle structure. */ -struct _lpuart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - lpuart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< LPUART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state. */ - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - bool isSevenDataBits; /*!< Seven data bits flag. */ -#endif -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL - -/*! - * @name Software Reset - * @{ - */ - -/*! - * @brief Resets the LPUART using software. - * - * This function resets all internal logic and registers except the Global Register. - * Remains set until cleared by software. - * - * @param base LPUART peripheral base address. - */ -static inline void LPUART_SoftwareReset(LPUART_Type *base) -{ - base->GLOBAL |= LPUART_GLOBAL_RST_MASK; - base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; -} -/* @} */ -#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. - * - * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function - * to configure the configuration structure and get the default configuration. - * The example below shows how to use this API to configure the LPUART. - * @code - * lpuart_config_t lpuartConfig; - * lpuartConfig.baudRate_Bps = 115200U; - * lpuartConfig.parityMode = kLPUART_ParityDisabled; - * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; - * lpuartConfig.isMsb = false; - * lpuartConfig.stopBitCount = kLPUART_OneStopBit; - * lpuartConfig.txFifoWatermark = 0; - * lpuartConfig.rxFifoWatermark = 1; - * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); - * @endcode - * - * @param base LPUART peripheral base address. - * @param config Pointer to a user-defined configuration structure. - * @param srcClock_Hz LPUART clock source frequency in HZ. - * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success LPUART initialize succeed - */ -status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a LPUART instance. - * - * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. - * - * @param base LPUART peripheral base address. - */ -void LPUART_Deinit(LPUART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the LPUART configuration structure to a default value. The default - * values are: - * lpuartConfig->baudRate_Bps = 115200U; - * lpuartConfig->parityMode = kLPUART_ParityDisabled; - * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; - * lpuartConfig->isMsb = false; - * lpuartConfig->stopBitCount = kLPUART_OneStopBit; - * lpuartConfig->txFifoWatermark = 0; - * lpuartConfig->rxFifoWatermark = 1; - * lpuartConfig->enableTx = false; - * lpuartConfig->enableRx = false; - * - * @param config Pointer to a configuration structure. - */ -void LPUART_GetDefaultConfig(lpuart_config_t *config); - -/*! - * @brief Sets the LPUART instance baudrate. - * - * This function configures the LPUART module baudrate. This function is used to update - * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. - * @code - * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); - * @endcode - * - * @param base LPUART peripheral base address. - * @param baudRate_Bps LPUART baudrate to be set. - * @param srcClock_Hz LPUART clock source frequency in HZ. - * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. - * @retval kStatus_Success Set baudrate succeeded. - */ -status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets LPUART status flags. - * - * This function gets all LPUART status flags. The flags are returned as the logical - * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _lpuart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) - * { - * ... - * } - * @endcode - * - * @param base LPUART peripheral base address. - * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. - */ -uint32_t LPUART_GetStatusFlags(LPUART_Type *base); - -/*! - * @brief Clears status flags with a provided mask. - * - * This function clears LPUART status flags with a provided mask. Automatically cleared flags - * can't be cleared by this function. - * Flags that can only cleared or set by hardware are: - * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, - * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, - * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag - * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. - * - * @param base LPUART peripheral base address. - * @param mask the status flags to be cleared. The user can use the enumerators in the - * _lpuart_status_flag_t to do the OR operation and get the mask. - * @return 0 succeed, others failed. - * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but - * it is cleared automatically by hardware. - * @retval kStatus_Success Status in the mask are cleared. - */ -status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables LPUART interrupts according to a provided mask. - * - * This function enables the LPUART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. - * This examples shows how to enable TX empty interrupt and RX full interrupt: - * @code - * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base LPUART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. - */ -void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); - -/*! - * @brief Disables LPUART interrupts according to a provided mask. - * - * This function disables the LPUART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base LPUART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. - */ -void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); - -/*! - * @brief Gets enabled LPUART interrupts. - * - * This function gets the enabled LPUART interrupts. The enabled interrupts are returned - * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check - * a specific interrupt enable status, compare the return value with enumerators - * in @ref _lpuart_interrupt_enable. - * For example, to check whether the TX empty interrupt is enabled: - * @code - * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); - * - * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) - * { - * ... - * } - * @endcode - * - * @param base LPUART peripheral base address. - * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. - */ -uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); - -#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE -/*! - * @brief Gets the LPUART data register address. - * - * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. - * - * @param base LPUART peripheral base address. - * @return LPUART data register addresses which are used both by the transmitter and receiver. - */ -static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) -{ - return (uint32_t) & (base->DATA); -} - -/*! - * @brief Enables or disables the LPUART transmitter DMA request. - * - * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->BAUD |= LPUART_BAUD_TDMAE_MASK; - base->CTRL |= LPUART_CTRL_TIE_MASK; - } - else - { - base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; - base->CTRL &= ~LPUART_CTRL_TIE_MASK; - } -} - -/*! - * @brief Enables or disables the LPUART receiver DMA. - * - * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->BAUD |= LPUART_BAUD_RDMAE_MASK; - base->CTRL |= LPUART_CTRL_RIE_MASK; - } - else - { - base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; - base->CTRL &= ~LPUART_CTRL_RIE_MASK; - } -} - -/* @} */ -#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables or disables the LPUART transmitter. - * - * This function enables or disables the LPUART transmitter. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= LPUART_CTRL_TE_MASK; - } - else - { - base->CTRL &= ~LPUART_CTRL_TE_MASK; - } -} - -/*! - * @brief Enables or disables the LPUART receiver. - * - * This function enables or disables the LPUART receiver. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= LPUART_CTRL_RE_MASK; - } - else - { - base->CTRL &= ~LPUART_CTRL_RE_MASK; - } -} - -/*! - * @brief Writes to the transmitter register. - * - * This function writes data to the transmitter register directly. The upper layer must - * ensure that the TX register is empty or that the TX FIFO has room before calling this function. - * - * @param base LPUART peripheral base address. - * @param data Data write to the TX register. - */ -static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) -{ - base->DATA = data; -} - -/*! - * @brief Reads the receiver register. - * - * This function reads data from the receiver register directly. The upper layer must - * ensure that the receiver register is full or that the RX FIFO has data before calling this function. - * - * @param base LPUART peripheral base address. - * @return Data read from data register. - */ -static inline uint8_t LPUART_ReadByte(LPUART_Type *base) -{ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); - - if (isSevenDataBits) - { - return (base->DATA & 0x7F); - } - else - { - return base->DATA; - } -#else - return base->DATA; -#endif -} - -/*! - * @brief Writes to the transmitter register using a blocking method. - * - * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have - * room, and writes data to the transmitter buffer. - * - * @note This function does not check whether all data has been sent out to the bus. - * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is - * finished. - * - * @param base LPUART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); - -/*! -* @brief Reads the receiver data register using a blocking method. - * - * This function polls the receiver register, waits for the receiver register full or receiver FIFO - * has data, and reads data from the TX register. - * - * @param base LPUART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. - * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. - * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. - * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. - * @retval kStatus_Success Successfully received all data. - */ -status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the LPUART handle. - * - * This function initializes the LPUART handle, which can be used for other LPUART - * transactional APIs. Usually, for a specified LPUART instance, - * call this API once to get the initialized handle. - * - * The LPUART driver supports the "background" receiving, which means that user can set up - * an RX ring buffer optionally. Data received is stored into the ring buffer even when the - * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * The ring buffer is disabled if passing NULL as @p ringBuffer. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -void LPUART_TransferCreateHandle(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_callback_t callback, - void *userData); -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function send data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data written to the transmitter register. When - * all data is written to the TX register in the ISR, the LPUART driver calls the callback - * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. - * - * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written - * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, - * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART transfer structure, see #lpuart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific UART handle. - * - * When the RX ring buffer is used, data received is stored into the ring buffer even when - * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void LPUART_TransferStartRingBuffer(LPUART_Type *base, - lpuart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are not sent out. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Gets the number of bytes that have been written to the LPUART transmitter register. - * - * This function gets the number of bytes that have been written to LPUART TX - * register by an interrupt method. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using the interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function - * which returns without waiting to ensure that all data are received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough for read, the receive - * request is saved by the LPUART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the LPUART driver notifies the upper layer - * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. - * The 5 bytes are copied to xfer->data, which returns with the - * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is - * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to xfer->data. When all data is received, the upper layer is notified. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART transfer structure, see #uart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into the transmit queue. - * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Gets the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); - -/*! - * @brief LPUART IRQ handle function. - * - * This function handles the LPUART transmit and receive IRQ request. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief LPUART Error IRQ handle function. - * - * This function handles the LPUART error IRQ request. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPUART_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_edma.c b/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_edma.c deleted file mode 100644 index 24da48314..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_edma.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpuart_edma.h" -#include "fsl_dmamux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*base, lpuartPrivateHandle->handle); - - if (lpuartPrivateHandle->handle->callback) - { - lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, - kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); - } - } -} - -static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - assert(param); - - lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; - - /* Avoid warning for unused parameters. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Disable transfer. */ - LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); - - if (lpuartPrivateHandle->handle->callback) - { - lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, - kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); - } - } -} - -void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, - lpuart_edma_handle_t *handle, - lpuart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle) -{ - assert(handle); - - uint32_t instance = LPUART_GetInstance(base); - - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; - - memset(handle, 0, sizeof(*handle)); - - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; - - handle->rxEdmaHandle = rxEdmaHandle; - handle->txEdmaHandle = txEdmaHandle; - - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Note: - Take care of the RX FIFO, EDMA request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - EDMA transfer because the water mark is 2. - */ - if (rxEdmaHandle) - { - base->WATER &= (~LPUART_WATER_RXWATER_MASK); - } -#endif - - /* Configure TX. */ - if (txEdmaHandle) - { - EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxEdmaHandle) - { - EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); - } -} - -status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kLPUART_TxBusy == handle->txState) - { - status = kStatus_LPUART_TxBusy; - } - else - { - handle->txState = kLPUART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base), - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->txEdmaHandle); - - /* Enable LPUART TX EDMA. */ - LPUART_EnableTxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous RX not finished. */ - if (kLPUART_RxBusy == handle->rxState) - { - status = kStatus_LPUART_RxBusy; - } - else - { - handle->rxState = kLPUART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->rxEdmaHandle); - - /* Enable LPUART RX EDMA. */ - LPUART_EnableRxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->txEdmaHandle); - - /* Disable LPUART TX EDMA. */ - LPUART_EnableTxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->txEdmaHandle); - - handle->txState = kLPUART_TxIdle; -} - -void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->rxEdmaHandle); - - /* Disable LPUART RX EDMA. */ - LPUART_EnableRxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->rxEdmaHandle); - - handle->rxState = kLPUART_RxIdle; -} - -status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(count); - - if (kLPUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); - - return kStatus_Success; -} - -status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(count); - - if (kLPUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); - - return kStatus_Success; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_edma.h b/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_edma.h deleted file mode 100644 index 79565c688..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_edma.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPUART_EDMA_H_ -#define _FSL_LPUART_EDMA_H_ - -#include "fsl_lpuart.h" -#include "fsl_dmamux.h" -#include "fsl_edma.h" - -/*! - * @addtogroup lpuart_edma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Forward declaration of the handle typedef. */ -typedef struct _lpuart_edma_handle lpuart_edma_handle_t; - -/*! @brief LPUART transfer callback function. */ -typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, - lpuart_edma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief LPUART eDMA handle -*/ -struct _lpuart_edma_handle -{ - lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< LPUART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ - edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA transactional - * @{ - */ - -/*! - * @brief Initializes the LPUART handle which is used in transactional functions. - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txEdmaHandle User requested DMA handle for TX DMA transfer. - * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. - */ -void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, - lpuart_edma_handle_t *handle, - lpuart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle); - -/*! - * @brief Sends data using eDMA. - * - * This function sends data using eDMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_LPUART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Receives data using eDMA. - * - * This function receives data using eDMA. This is non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. - * @retval kStatus_Success if succeed, others fail. - * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using eDMA. - * - * This function aborts the sent data using eDMA. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - */ -void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); - -/*! - * @brief Aborts the received data using eDMA. - * - * This function aborts the received data using eDMA. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - */ -void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); - -/*! - * @brief Gets the number of bytes written to the LPUART TX register. - * - * This function gets the number of bytes written to the LPUART TX - * register by DMA. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); - -/*! - * @brief Gets the number of received bytes. - * - * This function gets the number of received bytes. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPUART_EDMA_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_freertos.c b/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_freertos.c deleted file mode 100644 index 60b677796..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_freertos.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpuart_freertos.h" -#include -#include -#include - -static void LPUART_RTOS_Callback(LPUART_Type *base, lpuart_handle_t *state, status_t status, void *param) -{ - lpuart_rtos_handle_t *handle = (lpuart_rtos_handle_t *)param; - BaseType_t xHigherPriorityTaskWoken, xResult; - - xHigherPriorityTaskWoken = pdFALSE; - xResult = pdFAIL; - - if (status == kStatus_LPUART_RxIdle) - { - xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_COMPLETE, &xHigherPriorityTaskWoken); - } - else if (status == kStatus_LPUART_TxIdle) - { - xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_LPUART_COMPLETE, &xHigherPriorityTaskWoken); - } - else if (status == kStatus_LPUART_RxRingBufferOverrun) - { - xResult = - xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); - } - else if (status == kStatus_LPUART_RxHardwareOverrun) - { - /* Clear Overrun flag (OR) in LPUART STAT register */ - LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); - xResult = - xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); - } - - if (xResult != pdFAIL) - { - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_RTOS_Init - * Description : Initializes the LPUART instance for application - * - *END**************************************************************************/ -int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg) -{ - lpuart_config_t defcfg; - - if (NULL == handle) - { - return kStatus_InvalidArgument; - } - if (NULL == t_handle) - { - return kStatus_InvalidArgument; - } - if (NULL == cfg) - { - return kStatus_InvalidArgument; - } - if (NULL == cfg->base) - { - return kStatus_InvalidArgument; - } - if (0 == cfg->srcclk) - { - return kStatus_InvalidArgument; - } - if (0 == cfg->baudrate) - { - return kStatus_InvalidArgument; - } - - handle->base = cfg->base; - handle->t_state = t_handle; -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->txSemaphore = xSemaphoreCreateMutexStatic(&handle->txSemaphoreBuffer); -#else - handle->txSemaphore = xSemaphoreCreateMutex(); -#endif - if (NULL == handle->txSemaphore) - { - return kStatus_Fail; - } -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->rxSemaphore = xSemaphoreCreateMutexStatic(&handle->rxSemaphoreBuffer); -#else - handle->rxSemaphore = xSemaphoreCreateMutex(); -#endif - if (NULL == handle->rxSemaphore) - { - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->txEvent = xEventGroupCreateStatic(&handle->txEventBuffer); -#else - handle->txEvent = xEventGroupCreate(); -#endif - if (NULL == handle->txEvent) - { - vSemaphoreDelete(handle->rxSemaphore); - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } -#if (configSUPPORT_STATIC_ALLOCATION == 1) - handle->rxEvent = xEventGroupCreateStatic(&handle->rxEventBuffer); -#else - handle->rxEvent = xEventGroupCreate(); -#endif - if (NULL == handle->rxEvent) - { - vEventGroupDelete(handle->txEvent); - vSemaphoreDelete(handle->rxSemaphore); - vSemaphoreDelete(handle->txSemaphore); - return kStatus_Fail; - } - LPUART_GetDefaultConfig(&defcfg); - - defcfg.baudRate_Bps = cfg->baudrate; - defcfg.parityMode = cfg->parity; - defcfg.stopBitCount = cfg->stopbits; - - LPUART_Init(handle->base, &defcfg, cfg->srcclk); - LPUART_TransferCreateHandle(handle->base, handle->t_state, LPUART_RTOS_Callback, handle); - LPUART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size); - - LPUART_EnableTx(handle->base, true); - LPUART_EnableRx(handle->base, true); - - return 0; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_RTOS_Deinit - * Description : Deinitializes the LPUART instance and frees resources - * - *END**************************************************************************/ -int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle) -{ - LPUART_Deinit(handle->base); - - vEventGroupDelete(handle->txEvent); - vEventGroupDelete(handle->rxEvent); - - /* Give the semaphore. This is for functional safety */ - xSemaphoreGive(handle->txSemaphore); - xSemaphoreGive(handle->rxSemaphore); - - vSemaphoreDelete(handle->txSemaphore); - vSemaphoreDelete(handle->rxSemaphore); - - /* Invalidate the handle */ - handle->base = NULL; - handle->t_state = NULL; - - return 0; -} - -/*FUNCTION********************************************************************** - * - * Function Name : UART_RTOS_Send - * Description : Initializes the UART instance for application - * - *END**************************************************************************/ -int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, const uint8_t *buffer, uint32_t length) -{ - EventBits_t ev; - int retval = kStatus_Success; - - if (NULL == handle->base) - { - /* Invalid handle. */ - return kStatus_Fail; - } - if (0 == length) - { - return 0; - } - if (NULL == buffer) - { - return kStatus_InvalidArgument; - } - - if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0)) - { - /* We could not take the semaphore, exit with 0 data received */ - return kStatus_Fail; - } - - handle->txTransfer.data = (uint8_t *)buffer; - handle->txTransfer.dataSize = (uint32_t)length; - - /* Non-blocking call */ - LPUART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer); - - ev = xEventGroupWaitBits(handle->txEvent, RTOS_LPUART_COMPLETE, pdTRUE, pdFALSE, portMAX_DELAY); - if (!(ev & RTOS_LPUART_COMPLETE)) - { - retval = kStatus_Fail; - } - - if (pdFALSE == xSemaphoreGive(handle->txSemaphore)) - { - /* We could not post the semaphore, exit with error */ - retval = kStatus_Fail; - } - - return retval; -} - -/*FUNCTION********************************************************************** - * - * Function Name : LPUART_RTOS_Recv - * Description : Receives chars for the application - * - *END**************************************************************************/ -int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received) -{ - EventBits_t ev; - size_t n = 0; - int retval = kStatus_Fail; - size_t local_received = 0; - - if (NULL == handle->base) - { - /* Invalid handle. */ - return kStatus_Fail; - } - if (0 == length) - { - if (received != NULL) - { - *received = n; - } - return 0; - } - if (NULL == buffer) - { - return kStatus_InvalidArgument; - } - - /* New transfer can be performed only after current one is finished */ - if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY)) - { - /* We could not take the semaphore, exit with 0 data received */ - return kStatus_Fail; - } - - handle->rxTransfer.data = buffer; - handle->rxTransfer.dataSize = (uint32_t)length; - - /* Non-blocking call */ - LPUART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n); - - ev = xEventGroupWaitBits( - handle->rxEvent, RTOS_LPUART_COMPLETE | RTOS_LPUART_RING_BUFFER_OVERRUN | RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, - pdTRUE, pdFALSE, portMAX_DELAY); - if (ev & RTOS_LPUART_HARDWARE_BUFFER_OVERRUN) - { - /* Stop data transfer to application buffer, ring buffer is still active */ - LPUART_TransferAbortReceive(handle->base, handle->t_state); - /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. - RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ - xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_COMPLETE); - retval = kStatus_LPUART_RxHardwareOverrun; - local_received = 0; - } - else if (ev & RTOS_LPUART_RING_BUFFER_OVERRUN) - { - /* Stop data transfer to application buffer, ring buffer is still active */ - LPUART_TransferAbortReceive(handle->base, handle->t_state); - /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. - RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ - xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_COMPLETE); - retval = kStatus_LPUART_RxRingBufferOverrun; - local_received = 0; - } - else if (ev & RTOS_LPUART_COMPLETE) - { - retval = kStatus_Success; - local_received = length; - } - - /* Prevent repetitive NULL check */ - if (received != NULL) - { - *received = local_received; - } - - /* Enable next transfer. Current one is finished */ - if (pdFALSE == xSemaphoreGive(handle->rxSemaphore)) - { - /* We could not post the semaphore, exit with error */ - retval = kStatus_Fail; - } - return retval; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_freertos.h b/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_freertos.h deleted file mode 100644 index 56b45f77d..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_lpuart_freertos.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_LPUART_RTOS_H__ -#define __FSL_LPUART_RTOS_H__ - -#include "FreeRTOSConfig.h" -#include "fsl_lpuart.h" -#include -#include -#include - -/*! - * @addtogroup lpuart_freertos_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief LPUART RTOS configuration structure. */ -typedef struct _lpuart_rtos_config -{ - LPUART_Type *base; /*!< UART base address */ - uint32_t srcclk; /*!< UART source clock in Hz*/ - uint32_t baudrate; /*!< Desired communication speed */ - lpuart_parity_mode_t parity; /*!< Parity setting */ - lpuart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */ - uint8_t *buffer; /*!< Buffer for background reception */ - uint32_t buffer_size; /*!< Size of buffer for background reception */ -} lpuart_rtos_config_t; - -/*! -* @cond RTOS_PRIVATE -* @name LPUART event flags -* -* This are only valid states for txEvent and rxEvent (lpuart_rtos_handle_t). -*/ -/*@{*/ -/*! @brief Event flag - transfer complete. */ -#define RTOS_LPUART_COMPLETE 0x1 -/*! @brief Event flag - ring buffer overrun. */ -#define RTOS_LPUART_RING_BUFFER_OVERRUN 0x2 -/*! @brief Event flag - hardware buffer overrun. */ -#define RTOS_LPUART_HARDWARE_BUFFER_OVERRUN 0x4 -/*@}*/ - -/*! @brief LPUART FreeRTOS transfer structure. */ -typedef struct _lpuart_rtos_handle -{ - LPUART_Type *base; /*!< UART base address */ - lpuart_transfer_t txTransfer; /*!< TX transfer structure */ - lpuart_transfer_t rxTransfer; /*!< RX transfer structure */ - SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */ - SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */ - EventGroupHandle_t rxEvent; /*!< RX completion event */ - EventGroupHandle_t txEvent; /*!< TX completion event */ - void *t_state; /*!< Transactional state of the underlying driver */ -#if (configSUPPORT_STATIC_ALLOCATION == 1) - StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */ - StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */ - StaticEventGroup_t txEventBuffer; /*!< Statically allocated memory for txEvent */ - StaticEventGroup_t rxEventBuffer; /*!< Statically allocated memory for rxEvent */ -#endif -} lpuart_rtos_handle_t; -/*! \endcond */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name LPUART RTOS Operation - * @{ - */ - -/*! - * @brief Initializes an LPUART instance for operation in RTOS. - * - * @param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context. - * @param t_handle The pointer to an allocated space to store the transactional layer internal state. - * @param cfg The pointer to the parameters required to configure the LPUART after initialization. - * @return 0 succeed, others failed - */ -int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg); - -/*! - * @brief Deinitializes an LPUART instance for operation. - * - * This function deinitializes the LPUART module, sets all register value to the reset value, - * and releases the resources. - * - * @param handle The RTOS LPUART handle. - */ -int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle); - -/*! - * @name LPUART transactional Operation - * @{ - */ - -/*! - * @brief Sends data in the background. - * - * This function sends data. It is an synchronous API. - * If the hardware buffer is full, the task is in the blocked state. - * - * @param handle The RTOS LPUART handle. - * @param buffer The pointer to buffer to send. - * @param length The number of bytes to send. - */ -int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, const uint8_t *buffer, uint32_t length); - -/*! - * @brief Receives data. - * - * This function receives data from LPUART. It is an synchronous API. If any data is immediately available - * it is returned immediately and the number of bytes received. - * - * @param handle The RTOS LPUART handle. - * @param buffer The pointer to buffer where to write received data. - * @param length The number of bytes to receive. - * @param received The pointer to a variable of size_t where the number of received data is filled. - */ -int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_LPUART_RTOS_H__ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_ltc.c b/third_party/nxp/MKW41Z4/drivers/fsl_ltc.c deleted file mode 100644 index 9b67a7465..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_ltc.c +++ /dev/null @@ -1,4316 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_ltc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! Full word representing the actual bit values for the LTC mode register. */ -typedef uint32_t ltc_mode_t; - -#define LTC_FIFO_SZ_MAX_DOWN_ALGN (0xff0u) -#define LTC_MD_ALG_AES (0x10U) /*!< Bit field value for LTC_MD_ALG: AES */ -#define LTC_MD_ALG_DES (0x20U) /*!< Bit field value for LTC_MD_ALG: DES */ -#define LTC_MD_ALG_TRIPLE_DES (0x21U) /*!< Bit field value for LTC_MD_ALG: 3DES */ -#define LTC_MD_ALG_SHA1 (0x41U) /*!< Bit field value for LTC_MD_ALG: SHA-1 */ -#define LTC_MD_ALG_SHA224 (0x42U) /*!< Bit field value for LTC_MD_ALG: SHA-224 */ -#define LTC_MD_ALG_SHA256 (0x43U) /*!< Bit field value for LTC_MD_ALG: SHA-256 */ -#define LTC_MDPK_ALG_PKHA (0x80U) /*!< Bit field value for LTC_MDPK_ALG: PKHA */ -#define LTC_MD_ENC_DECRYPT (0U) /*!< Bit field value for LTC_MD_ENC: Decrypt. */ -#define LTC_MD_ENC_ENCRYPT (0x1U) /*!< Bit field value for LTC_MD_ENC: Encrypt. */ -#define LTC_MD_AS_UPDATE (0U) /*!< Bit field value for LTC_MD_AS: Update */ -#define LTC_MD_AS_INITIALIZE (0x1U) /*!< Bit field value for LTC_MD_AS: Initialize */ -#define LTC_MD_AS_FINALIZE (0x2U) /*!< Bit field value for LTC_MD_AS: Finalize */ -#define LTC_MD_AS_INIT_FINAL (0x3U) /*!< Bit field value for LTC_MD_AS: Initialize/Finalize */ - -#define LTC_AES_GCM_TYPE_AAD 55 -#define LTC_AES_GCM_TYPE_IV 0 - -#define LTC_CCM_TAG_IDX 8 /*! For CCM encryption, the encrypted final MAC is written to the context word 8-11 */ -#define LTC_GCM_TAG_IDX 0 /*! For GCM encryption, the encrypted final MAC is written to the context word 0-3 */ - -enum _ltc_md_dk_bit_shift -{ - kLTC_ModeRegBitShiftDK = 12U, -}; - -typedef enum _ltc_algorithm -{ -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - kLTC_AlgorithmPKHA = LTC_MDPK_ALG_PKHA << LTC_MD_ALG_SHIFT, -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ - kLTC_AlgorithmAES = LTC_MD_ALG_AES << LTC_MD_ALG_SHIFT, -#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES - kLTC_AlgorithmDES = LTC_MD_ALG_DES << LTC_MD_ALG_SHIFT, - kLTC_Algorithm3DES = LTC_MD_ALG_TRIPLE_DES << LTC_MD_ALG_SHIFT, -#endif /* FSL_FEATURE_LTC_HAS_DES */ -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - kLTC_AlgorithmSHA1 = LTC_MD_ALG_SHA1 << LTC_MD_ALG_SHIFT, - kLTC_AlgorithmSHA224 = LTC_MD_ALG_SHA224 << LTC_MD_ALG_SHIFT, - kLTC_AlgorithmSHA256 = LTC_MD_ALG_SHA256 << LTC_MD_ALG_SHIFT, -#endif /* FSL_FEATURE_LTC_HAS_SHA */ -} ltc_algorithm_t; - -typedef enum _ltc_mode_symmetric_alg -{ - kLTC_ModeCTR = 0x00U << LTC_MD_AAI_SHIFT, - kLTC_ModeCBC = 0x10U << LTC_MD_AAI_SHIFT, - kLTC_ModeECB = 0x20U << LTC_MD_AAI_SHIFT, - kLTC_ModeCFB = 0x30U << LTC_MD_AAI_SHIFT, - kLTC_ModeOFB = 0x40U << LTC_MD_AAI_SHIFT, - kLTC_ModeCMAC = 0x60U << LTC_MD_AAI_SHIFT, - kLTC_ModeXCBCMAC = 0x70U << LTC_MD_AAI_SHIFT, - kLTC_ModeCCM = 0x80U << LTC_MD_AAI_SHIFT, - kLTC_ModeGCM = 0x90U << LTC_MD_AAI_SHIFT, -} ltc_mode_symmetric_alg_t; - -typedef enum _ltc_mode_encrypt -{ - kLTC_ModeDecrypt = LTC_MD_ENC_DECRYPT << LTC_MD_ENC_SHIFT, - kLTC_ModeEncrypt = LTC_MD_ENC_ENCRYPT << LTC_MD_ENC_SHIFT, -} ltc_mode_encrypt_t; - -typedef enum _ltc_mode_algorithm_state -{ - kLTC_ModeUpdate = LTC_MD_AS_UPDATE << LTC_MD_AS_SHIFT, - kLTC_ModeInit = LTC_MD_AS_INITIALIZE << LTC_MD_AS_SHIFT, - kLTC_ModeFinalize = LTC_MD_AS_FINALIZE << LTC_MD_AS_SHIFT, - kLTC_ModeInitFinal = LTC_MD_AS_INIT_FINAL << LTC_MD_AS_SHIFT -} ltc_mode_algorithm_state_t; - -/*! @brief LTC status flags */ -enum _ltc_status_flag -{ - kLTC_StatusAesBusy = 1U << LTC_STA_AB_SHIFT, -#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES - kLTC_StatusDesBusy = 1U << LTC_STA_DB_SHIFT, -#endif /* FSL_FEATURE_LTC_HAS_DES */ -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - kLTC_StatusPkhaBusy = 1U << LTC_STA_PB_SHIFT, -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - kLTC_StatusMdhaBusy = 1U << LTC_STA_MB_SHIFT, -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - kLTC_StatusDoneIsr = 1U << LTC_STA_DI_SHIFT, - kLTC_StatusErrorIsr = 1U << LTC_STA_EI_SHIFT, -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - kLTC_StatusPublicKeyPrime = 1U << LTC_STA_PKP_SHIFT, - kLTC_StatusPublicKeyOpOne = 1U << LTC_STA_PKO_SHIFT, - kLTC_StatusPublicKeyOpZero = 1U << LTC_STA_PKZ_SHIFT, -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ - kLTC_StatusAll = LTC_STA_AB_MASK | -#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES - LTC_STA_DB_MASK | -#endif /* FSL_FEATURE_LTC_HAS_DES */ -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - LTC_STA_MB_MASK | -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - LTC_STA_DI_MASK | LTC_STA_EI_MASK -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - | - LTC_STA_PB_MASK | LTC_STA_PKP_MASK | LTC_STA_PKO_MASK | LTC_STA_PKZ_MASK -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ -}; - -/*! @brief LTC clear register */ -typedef enum _ltc_clear_written -{ - kLTC_ClearMode = 1U << LTC_CW_CM_SHIFT, - kLTC_ClearDataSize = 1U << LTC_CW_CDS_SHIFT, - kLTC_ClearIcvSize = 1U << LTC_CW_CICV_SHIFT, - kLTC_ClearContext = 1U << LTC_CW_CCR_SHIFT, - kLTC_ClearKey = 1U << LTC_CW_CKR_SHIFT, -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - kLTC_ClearPkhaSizeA = 1U << LTC_CW_CPKA_SHIFT, - kLTC_ClearPkhaSizeB = 1U << LTC_CW_CPKB_SHIFT, - kLTC_ClearPkhaSizeN = 1U << LTC_CW_CPKN_SHIFT, - kLTC_ClearPkhaSizeE = 1U << LTC_CW_CPKE_SHIFT, - kLTC_ClearAllSize = (int)kLTC_ClearPkhaSizeA | kLTC_ClearPkhaSizeB | kLTC_ClearPkhaSizeN | kLTC_ClearPkhaSizeE, -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ - kLTC_ClearOutputFifo = 1U << LTC_CW_COF_SHIFT, - kLTC_ClearInputFifo = (int)(1U << LTC_CW_CIF_SHIFT), - kLTC_ClearAll = (int)(LTC_CW_CM_MASK | LTC_CW_CDS_MASK | LTC_CW_CICV_MASK | LTC_CW_CCR_MASK | LTC_CW_CKR_MASK | -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - LTC_CW_CPKA_MASK | LTC_CW_CPKB_MASK | LTC_CW_CPKN_MASK | LTC_CW_CPKE_MASK | -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ - LTC_CW_COF_MASK | LTC_CW_CIF_MASK) -} ltc_clear_written_t; - -enum _ltc_ctrl_swap -{ - kLTC_CtrlSwapAll = - LTC_CTL_IFS_MASK | LTC_CTL_OFS_MASK | LTC_CTL_KIS_MASK | LTC_CTL_KOS_MASK | LTC_CTL_CIS_MASK | LTC_CTL_COS_MASK, -}; - -/*! @brief Type used in GCM and CCM modes. - - Content of a block is established via individual bytes and moved to LTC - IFIFO by moving 32-bit words. -*/ -typedef union _ltc_xcm_block_t -{ - uint32_t w[4]; /*!< LTC context register is 16 bytes written as four 32-bit words */ - uint8_t b[16]; /*!< 16 octets block for CCM B0 and CTR0 and for GCM */ -} ltc_xcm_block_t; - -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - -/*! @brief PKHA functions - arithmetic, copy/clear memory. */ -typedef enum _ltc_pkha_func_t -{ - kLTC_PKHA_ClearMem = 1U, - kLTC_PKHA_ArithModAdd = 2U, /*!< (A + B) mod N */ - kLTC_PKHA_ArithModSub1 = 3U, /*!< (A - B) mod N */ - kLTC_PKHA_ArithModSub2 = 4U, /*!< (B - A) mod N */ - kLTC_PKHA_ArithModMul = 5U, /*!< (A x B) mod N */ - kLTC_PKHA_ArithModExp = 6U, /*!< (A^E) mod N */ - kLTC_PKHA_ArithModRed = 7U, /*!< (A) mod N */ - kLTC_PKHA_ArithModInv = 8U, /*!< (A^-1) mod N */ - kLTC_PKHA_ArithEccAdd = 9U, /*!< (P1 + P2) */ - kLTC_PKHA_ArithEccDouble = 10U, /*!< (P2 + P2) */ - kLTC_PKHA_ArithEccMul = 11U, /*!< (E x P1) */ - kLTC_PKHA_ArithModR2 = 12U, /*!< (R^2 mod N) */ - kLTC_PKHA_ArithGcd = 14U, /*!< GCD (A, N) */ - kLTC_PKHA_ArithPrimalityTest = 15U, /*!< Miller-Rabin */ - kLTC_PKHA_CopyMemSizeN = 16U, - kLTC_PKHA_CopyMemSizeSrc = 17U, -} ltc_pkha_func_t; - -/*! @brief Register areas for PKHA clear memory operations. */ -typedef enum _ltc_pkha_reg_area -{ - kLTC_PKHA_RegA = 8U, - kLTC_PKHA_RegB = 4U, - kLTC_PKHA_RegE = 2U, - kLTC_PKHA_RegN = 1U, - kLTC_PKHA_RegAll = kLTC_PKHA_RegA | kLTC_PKHA_RegB | kLTC_PKHA_RegE | kLTC_PKHA_RegN, -} ltc_pkha_reg_area_t; - -/*! @brief Quadrant areas for 2048-bit registers for PKHA copy memory - * operations. */ -typedef enum _ltc_pkha_quad_area_t -{ - kLTC_PKHA_Quad0 = 0U, - kLTC_PKHA_Quad1 = 1U, - kLTC_PKHA_Quad2 = 2U, - kLTC_PKHA_Quad3 = 3U, -} ltc_pkha_quad_area_t; - -/*! @brief User-supplied (R^2 mod N) input or LTC should calculate. */ -typedef enum _ltc_pkha_r2_t -{ - kLTC_PKHA_CalcR2 = 0U, /*!< Calculate (R^2 mod N) */ - kLTC_PKHA_InputR2 = 1U /*!< (R^2 mod N) supplied as input */ -} ltc_pkha_r2_t; - -/*! @brief LTC PKHA parameters */ -typedef struct _ltc_pkha_mode_params_t -{ - ltc_pkha_func_t func; - ltc_pkha_f2m_t arithType; - ltc_pkha_montgomery_form_t montFormIn; - ltc_pkha_montgomery_form_t montFormOut; - ltc_pkha_reg_area_t srcReg; - ltc_pkha_quad_area_t srcQuad; - ltc_pkha_reg_area_t dstReg; - ltc_pkha_quad_area_t dstQuad; - ltc_pkha_timing_t equalTime; - ltc_pkha_r2_t r2modn; -} ltc_pkha_mode_params_t; - -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA -static status_t ltc_pkha_clear_regabne(LTC_Type *base, bool A, bool B, bool N, bool E); -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/******************************************************************************* - * LTC Common code static - ******************************************************************************/ -/*! - * @brief Tests the correct key size. - * - * This function tests the correct key size. - * @param keySize Input key length in bytes. - * @return True if the key length is supported, false if not. - */ -bool ltc_check_key_size(const uint32_t keySize) -{ - return ((keySize == 16u) -#if defined(FSL_FEATURE_LTC_HAS_AES192) && FSL_FEATURE_LTC_HAS_AES192 - || ((keySize == 24u)) -#endif /* FSL_FEATURE_LTC_HAS_AES192 */ -#if defined(FSL_FEATURE_LTC_HAS_AES256) && FSL_FEATURE_LTC_HAS_AES256 - || ((keySize == 32u)) -#endif /* FSL_FEATURE_LTC_HAS_AES256 */ - ); -} - -/*! @brief LTC driver wait mechanism. */ -status_t ltc_wait(LTC_Type *base) -{ - status_t status; - - bool error = false; - bool done = false; - - /* Wait for 'done' or 'error' flag. */ - while ((!error) && (!done)) - { - uint32_t temp32 = base->STA; - error = temp32 & LTC_STA_EI_MASK; - done = temp32 & LTC_STA_DI_MASK; - } - - if (error) - { - base->COM = LTC_COM_ALL_MASK; /* Reset all engine to clear the error flag */ - status = kStatus_Fail; - } - else /* 'done' */ - { - status = kStatus_Success; - - base->CW = kLTC_ClearDataSize; - /* Clear 'done' interrupt status. This also clears the mode register. */ - base->STA = kLTC_StatusDoneIsr; - } - - return status; -} - -/*! - * @brief Clears the LTC module. - * This function can be used to clear all sensitive data from theLTC module, such as private keys. It is called - * internally by the LTC driver in case of an error or operation complete. - * @param base LTC peripheral base address - * @param pkha Include LTC PKHA register clear. If there is no PKHA, the argument is ignored. - */ -void ltc_clear_all(LTC_Type *base, bool addPKHA) -{ - base->CW = (uint32_t)kLTC_ClearAll; -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA - if (addPKHA) - { - ltc_pkha_clear_regabne(base, true, true, true, true); - } -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ -} - -void ltc_memcpy(void *dst, const void *src, size_t size) -{ -#if defined(__cplusplus) - register uint8_t *to = (uint8_t *)dst; - register const uint8_t *from = (const uint8_t *)src; -#else - register uint8_t *to = dst; - register const uint8_t *from = src; -#endif - while (size) - { - *to = *from; - size--; - to++; - from++; - } -} - -/*! - * @brief Reads an unaligned word. - * - * This function creates a 32-bit word from an input array of four bytes. - * - * @param src Input array of four bytes. The array can start at any address in memory. - * @return 32-bit unsigned int created from the input byte array. - */ -static inline uint32_t ltc_get_word_from_unaligned(const uint8_t *srcAddr) -{ -#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) - register const uint8_t *src = srcAddr; - /* Cortex M0 does not support misaligned loads */ - if ((uint32_t)src & 0x3u) - { - union _align_bytes_t - { - uint32_t word; - uint8_t byte[sizeof(uint32_t)]; - } my_bytes; - - my_bytes.byte[0] = *src; - my_bytes.byte[1] = *(src + 1); - my_bytes.byte[2] = *(src + 2); - my_bytes.byte[3] = *(src + 3); - return my_bytes.word; - } - else - { - /* addr aligned to 0-modulo-4 so it is safe to type cast */ - return *((const uint32_t *)src); - } -#elif defined(__CC_ARM) - /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0}) - * which is wrong, because srcAddr might be unaligned. - * LDM on unaligned address causes hard-fault. in contrary, - * LDR supports unaligned address on Cortex M4 */ - register uint32_t retVal; - __asm - { - LDR retVal, [srcAddr] - } - return retVal; -#else - return *((const uint32_t *)srcAddr); -#endif -} - -/*! - * @brief Converts a 32-bit word into a byte array. - * - * This function creates an output array of four bytes from an input 32-bit word. - * - * @param srcWord Input 32-bit unsigned integer. - * @param dst Output array of four bytes. The array can start at any address in memory. - */ -static inline void ltc_set_unaligned_from_word(uint32_t srcWord, uint8_t *dstAddr) -{ -#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) - register uint8_t *dst = dstAddr; - /* Cortex M0 does not support misaligned stores */ - if ((uint32_t)dst & 0x3u) - { - *dst++ = (srcWord & 0x000000FFU); - *dst++ = (srcWord & 0x0000FF00U) >> 8; - *dst++ = (srcWord & 0x00FF0000U) >> 16; - *dst++ = (srcWord & 0xFF000000U) >> 24; - } - else - { - *((uint32_t *)dstAddr) = srcWord; /* addr aligned to 0-modulo-4 so it is safe to type cast */ - } -#elif defined(__CC_ARM) - __asm - { - STR srcWord, [dstAddr] - } - return; -#else - *((uint32_t *)dstAddr) = srcWord; -#endif -} - -/*! - * @brief Sets the LTC keys. - * - * This function writes the LTC keys into the key register. The keys should - * be written before the key size. - * - * @param base LTC peripheral base address - * @param key Key - * @param keySize Number of bytes for all keys to be loaded (maximum 32, must be a - * multiple of 4). - * @returns Key set status - */ -static status_t ltc_set_key(LTC_Type *base, const uint8_t *key, uint8_t keySize) -{ - int32_t i; - - for (i = 0; i < (keySize / 4); i++) - { - base->KEY[i] = ltc_get_word_from_unaligned(key + i * sizeof(uint32_t)); - } - - return kStatus_Success; -} - -/*! - * @brief Gets the LTC keys. - * - * This function retrieves the LTC keys from the key register. - * - * @param base LTC peripheral base address - * @param key Array of data to store keys - * @param keySize Number of bytes of keys to retrieve - * @returns Key set status - */ -static status_t ltc_get_key(LTC_Type *base, uint8_t *key, uint8_t keySize) -{ - int32_t i; - - for (i = 0; i < (keySize / 4); i++) - { - ltc_set_unaligned_from_word(base->KEY[i], key + i * sizeof(uint32_t)); - } - - return kStatus_Success; -} - -/*! - * @brief Writes the LTC context register; - * - * The LTC context register is a 512 bit (64 byte) register that holds - * internal context for the crypto engine. The meaning varies based on the - * algorithm and operating state being used. This register is written by the - * driver/application to load state such as IV, counter, and so on. Then, it is - * updated by the internal crypto engine as needed. - * - * @param base LTC peripheral base address - * @param data Data to write - * @param dataSize Size of data to write in bytes - * @param startIndex Starting word (4-byte) index into the 16-word register. - * @return Status of write - */ -status_t ltc_set_context(LTC_Type *base, const uint8_t *data, uint8_t dataSize, uint8_t startIndex) -{ - int32_t i; - int32_t j; - int32_t szLeft; - - /* Context register is 16 words in size (64 bytes). Ensure we are only - * writing a valid amount of data. */ - if (startIndex + (dataSize / 4) >= 16) - { - return kStatus_InvalidArgument; - } - - j = 0; - szLeft = dataSize % 4; - for (i = startIndex; i < (startIndex + dataSize / 4); i++) - { - base->CTX[i] = ltc_get_word_from_unaligned(data + j); - j += sizeof(uint32_t); - } - - if (szLeft) - { - uint32_t context_data = {0}; - ltc_memcpy(&context_data, data + j, szLeft); - base->CTX[i] = context_data; - } - return kStatus_Success; -} - -/*! - * @brief Reads the LTC context register. - * - * The LTC context register is a 512 bit (64 byte) register that holds - * internal context for the crypto engine. The meaning varies based on the - * algorithm and operating state being used. This register is written by the - * driver/application to load state such as IV, counter, and so on. Then, it is - * updated by the internal crypto engine as needed. - * - * @param base LTC peripheral base address - * @param data Destination of read data - * @param dataSize Size of data to read in bytes - * @param startIndex Starting word (4-byte) index into the 16-word register. - * @return Status of read - */ -status_t ltc_get_context(LTC_Type *base, uint8_t *dest, uint8_t dataSize, uint8_t startIndex) -{ - int32_t i; - int32_t j; - int32_t szLeft; - uint32_t rdCtx; - - /* Context register is 16 words in size (64 bytes). Ensure we are only - * writing a valid amount of data. */ - if (startIndex + (dataSize / 4) >= 16) - { - return kStatus_InvalidArgument; - } - - j = 0; - szLeft = dataSize % 4; - for (i = startIndex; i < (startIndex + dataSize / 4); i++) - { - ltc_set_unaligned_from_word(base->CTX[i], dest + j); - j += sizeof(uint32_t); - } - - if (szLeft) - { - rdCtx = 0; - rdCtx = base->CTX[i]; - ltc_memcpy(dest + j, &rdCtx, szLeft); - } - return kStatus_Success; -} - -static status_t ltc_symmetric_alg_state(LTC_Type *base, - const uint8_t *key, - uint8_t keySize, - ltc_algorithm_t alg, - ltc_mode_symmetric_alg_t mode, - ltc_mode_encrypt_t enc, - ltc_mode_algorithm_state_t as) -{ - ltc_mode_t modeReg; - - /* Clear internal register states. */ - base->CW = (uint32_t)kLTC_ClearAll; - - /* Set byte swap on for several registers we will be reading and writing - * user data to/from. */ - base->CTL |= kLTC_CtrlSwapAll; - - /* Write the key in place. */ - ltc_set_key(base, key, keySize); - - /* Write the key size. This must be done after writing the key, and this - * action locks the ability to modify the key registers. */ - base->KS = keySize; - - /* Clear the 'done' interrupt. */ - base->STA = kLTC_StatusDoneIsr; - - /* Set the proper block and algorithm mode. */ - modeReg = (uint32_t)alg | (uint32_t)enc | (uint32_t)as | (uint32_t)mode; - - /* Write the mode register to the hardware. */ - base->MD = modeReg; - - return kStatus_Success; -} - -/*! - * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to UPDATE. - * - * @param base LTC peripheral base address - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32. - * @param alg Symmetric algorithm - * @param mode Symmetric block mode - * @param enc Encrypt/decrypt control - * @return Status - */ -status_t ltc_symmetric_update(LTC_Type *base, - const uint8_t *key, - uint8_t keySize, - ltc_algorithm_t alg, - ltc_mode_symmetric_alg_t mode, - ltc_mode_encrypt_t enc) -{ - return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeUpdate); -} - -#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM -/*! - * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to FINALIZE. - * - * @param base LTC peripheral base address - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32. - * @param alg Symmetric algorithm - * @param mode Symmetric block mode - * @param enc Encrypt/decrypt control - * @return Status - */ -static status_t ltc_symmetric_final(LTC_Type *base, - const uint8_t *key, - uint8_t keySize, - ltc_algorithm_t alg, - ltc_mode_symmetric_alg_t mode, - ltc_mode_encrypt_t enc) -{ - return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeFinalize); -} -#endif /* FSL_FEATURE_LTC_HAS_GCM */ - -/*! - * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to INITIALIZE. - * - * @param base LTC peripheral base address - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32. - * @param alg Symmetric algorithm - * @param mode Symmetric block mode - * @param enc Encrypt/decrypt control - * @return Status - */ -static status_t ltc_symmetric_init(LTC_Type *base, - const uint8_t *key, - uint8_t keySize, - ltc_algorithm_t alg, - ltc_mode_symmetric_alg_t mode, - ltc_mode_encrypt_t enc) -{ - return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeInit); -} - -/*! - * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to INITIALIZE/FINALIZE. - * - * @param base LTC peripheral base address - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32. - * @param alg Symmetric algorithm - * @param mode Symmetric block mode - * @param enc Encrypt/decrypt control - * @return Status - */ -static status_t ltc_symmetric_init_final(LTC_Type *base, - const uint8_t *key, - uint8_t keySize, - ltc_algorithm_t alg, - ltc_mode_symmetric_alg_t mode, - ltc_mode_encrypt_t enc) -{ - return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeInitFinal); -} - -void ltc_symmetric_process(LTC_Type *base, uint32_t inSize, const uint8_t **inData, uint8_t **outData) -{ - uint32_t outSize; - uint32_t fifoData; - uint32_t fifoStatus; - - register const uint8_t *in = *inData; - register uint8_t *out = *outData; - - outSize = inSize; - while ((outSize > 0) || (inSize > 0)) - { - fifoStatus = base->FIFOSTA; - - /* Check output FIFO level to make sure there is at least an entry - * ready to be read. */ - if (fifoStatus & LTC_FIFOSTA_OFL_MASK) - { - /* Read data from the output FIFO. */ - if (outSize > 0) - { - if (outSize >= sizeof(uint32_t)) - { - ltc_set_unaligned_from_word(base->OFIFO, out); - out += sizeof(uint32_t); - outSize -= sizeof(uint32_t); - } - else /* (outSize > 0) && (outSize < 4) */ - { - fifoData = base->OFIFO; - ltc_memcpy(out, &fifoData, outSize); - out += outSize; - outSize = 0; - } - } - } - - /* Check input FIFO status to see if it is full. We can - * only write more data when both input and output FIFOs are not at a full state. - * At the same time we are sure Output FIFO is not full because we have poped at least one entry - * by the while loop above. - */ - if (!(fifoStatus & LTC_FIFOSTA_IFF_MASK)) - { - /* Copy data to the input FIFO. - * Data can only be copied one word at a time, so pad the data - * appropriately if it is less than this size. */ - if (inSize > 0) - { - if (inSize >= sizeof(uint32_t)) - { - base->IFIFO = ltc_get_word_from_unaligned(in); - inSize -= sizeof(uint32_t); - in += sizeof(uint32_t); - } - else /* (inSize > 0) && (inSize < 4) */ - { - fifoData = 0; - ltc_memcpy(&fifoData, in, inSize); - base->IFIFO = fifoData; - in += inSize; - inSize = 0; - } - } - } - } - *inData = in; - *outData = out; -} - -/*! - * @brief Processes symmetric data through LTC AES and DES engines. - * - * @param base LTC peripheral base address - * @param inData Input data - * @param inSize Size of input data, in bytes - * @param outData Output data - * @return Status from encrypt/decrypt operation - */ -status_t ltc_symmetric_process_data(LTC_Type *base, const uint8_t *inData, uint32_t inSize, uint8_t *outData) -{ - uint32_t lastSize; - - if ((!inData) || (!outData)) - { - return kStatus_InvalidArgument; - } - - /* Write the data size. */ - base->DS = inSize; - - /* Split the inSize into full 16-byte chunks and last incomplete block due to LTC AES OFIFO errata */ - if (inSize <= 16u) - { - lastSize = inSize; - inSize = 0; - } - else - { - /* Process all 16-byte data chunks. */ - lastSize = inSize % 16u; - if (lastSize == 0) - { - lastSize = 16; - inSize -= 16; - } - else - { - inSize -= lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in lastSize */ - } - } - - ltc_symmetric_process(base, inSize, &inData, &outData); - ltc_symmetric_process(base, lastSize, &inData, &outData); - return ltc_wait(base); -} - -/*! - * @brief Splits the LTC job into sessions. Used for CBC, CTR, CFB, OFB cipher block modes. - * - * @param base LTC peripheral base address - * @param inData Input data to process. - * @param inSize Input size of the input buffer. - * @param outData Output data buffer. - */ -static status_t ltc_process_message_in_sessions(LTC_Type *base, - const uint8_t *inData, - uint32_t inSize, - uint8_t *outData) -{ - uint32_t sz; - status_t retval; - ltc_mode_t modeReg; /* read and write LTC mode register */ - - sz = LTC_FIFO_SZ_MAX_DOWN_ALGN; - modeReg = base->MD; - retval = kStatus_Success; - - while (inSize) - { - if (inSize <= sz) - { - retval = ltc_symmetric_process_data(base, inData, inSize, outData); - if (kStatus_Success != retval) - { - return retval; - } - inSize = 0; - } - else - { - retval = ltc_symmetric_process_data(base, inData, sz, outData); - if (kStatus_Success != retval) - { - return retval; - } - inData += sz; - inSize -= sz; - outData += sz; - base->MD = modeReg; - } - } - return retval; -} - -static void ltc_move_block_to_ififo(LTC_Type *base, const ltc_xcm_block_t *blk, uint32_t num_bytes) -{ - uint32_t i = 0; - uint32_t words; - - words = num_bytes / 4u; - if (num_bytes % 4u) - { - words++; - } - - if (words > 4) - { - words = 4; - } - - while (i < words) - { - if (0U == (base->FIFOSTA & LTC_FIFOSTA_IFF_MASK)) - { - /* Copy data to the input FIFO. */ - base->IFIFO = blk->w[i++]; - } - } -} - -static void ltc_move_to_ififo(LTC_Type *base, const uint8_t *data, uint32_t dataSize) -{ - ltc_xcm_block_t blk; - ltc_xcm_block_t blkZero = {{0x0u, 0x0u, 0x0u, 0x0u}}; - - while (dataSize) - { - if (dataSize > 16u) - { - ltc_memcpy(&blk, data, 16u); - dataSize -= 16u; - data += 16u; - } - else - { - ltc_memcpy(&blk, &blkZero, sizeof(ltc_xcm_block_t)); /* memset blk to zeroes */ - ltc_memcpy(&blk, data, dataSize); - dataSize = 0; - } - ltc_move_block_to_ififo(base, &blk, sizeof(ltc_xcm_block_t)); - } -} - -/*! - * @brief Processes symmetric data through LTC AES in multiple sessions. - * - * Specific for AES CCM and GCM modes as they need to update mode register. - * - * @param base LTC peripheral base address - * @param inData Input data - * @param inSize Size of input data, in bytes - * @param outData Output data - * @param lastAs The LTC Algorithm state to be set sup for last block during message processing in multiple sessions. - * For CCM it is kLTC_ModeFinalize. For GCM it is kLTC_ModeInitFinal. - * @return Status from encrypt/decrypt operation - */ -static status_t ltc_symmetric_process_data_multiple(LTC_Type *base, - const uint8_t *inData, - uint32_t inSize, - uint8_t *outData, - ltc_mode_t modeReg, - ltc_mode_algorithm_state_t lastAs) -{ - uint32_t fifoConsumed; - uint32_t lastSize; - uint32_t sz; - uint32_t max_ltc_fifo_size; - ltc_mode_algorithm_state_t fsm; - status_t status; - - if ((!inData) || (!outData)) - { - return kStatus_InvalidArgument; - } - - if (!((kLTC_ModeFinalize == lastAs) || (kLTC_ModeInitFinal == lastAs))) - { - return kStatus_InvalidArgument; - } - - if (0 == inSize) - { - return kStatus_Success; - } - - if (inSize <= 16u) - { - fsm = lastAs; - lastSize = inSize; - } - else - { - fsm = (ltc_mode_algorithm_state_t)( - modeReg & - LTC_MD_AS_MASK); /* this will be either kLTC_ModeInit or kLTC_ModeUpdate, based on prior processing */ - - /* Process all 16-byte data chunks. */ - lastSize = inSize % 16u; - if (lastSize == 0u) - { - lastSize = 16u; - inSize -= 16u; - } - else - { - inSize -= lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in lastSize */ - } - } - - max_ltc_fifo_size = LTC_FIFO_SZ_MAX_DOWN_ALGN; - fifoConsumed = base->DS; - - while (lastSize) - { - switch (fsm) - { - case kLTC_ModeUpdate: - case kLTC_ModeInit: - while (inSize) - { - if (inSize > (max_ltc_fifo_size - fifoConsumed)) - { - sz = (max_ltc_fifo_size - fifoConsumed); - } - else - { - sz = inSize; - } - base->DS = sz; - ltc_symmetric_process(base, sz, &inData, &outData); - inSize -= sz; - fifoConsumed = 0; - - /* after we completed INITIALIZE job, are there still any data left? */ - if (inSize) - { - fsm = kLTC_ModeUpdate; - status = ltc_wait(base); - if (kStatus_Success != status) - { - return status; - } - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= (uint32_t)fsm; - base->MD = modeReg; - } - else - { - fsm = lastAs; - } - } - break; - - case kLTC_ModeFinalize: - case kLTC_ModeInitFinal: - /* process last block in FINALIZE */ - - status = ltc_wait(base); - if (kStatus_Success != status) - { - return status; - } - - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= (uint32_t)lastAs; - base->MD = modeReg; - - base->DS = lastSize; - ltc_symmetric_process(base, lastSize, &inData, &outData); - lastSize = 0; - break; - - default: - break; - } - } - - status = ltc_wait(base); - return status; -} - -/*! - * @brief Receives MAC compare. - * - * This function is a sub-process of CCM and GCM decryption. - * It compares received MAC with the MAC computed during decryption. - * - * @param base LTC peripheral base address - * @param tag Received MAC. - * @param tagSize Number of bytes in the received MAC. - * @param modeReg LTC Mode Register current value. It is modified and written to LTC Mode Register. - */ -static status_t ltc_aes_received_mac_compare(LTC_Type *base, const uint8_t *tag, uint32_t tagSize, ltc_mode_t modeReg) -{ - ltc_xcm_block_t blk = {{0x0u, 0x0u, 0x0u, 0x0u}}; - - base->CW = kLTC_ClearDataSize; - base->STA = kLTC_StatusDoneIsr; - - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= (uint32_t)kLTC_ModeUpdate | LTC_MD_ICV_TEST_MASK; - base->MD = modeReg; - - base->DS = 0u; - base->ICVS = tagSize; - ltc_memcpy(&blk.b[0], &tag[0], tagSize); - - ltc_move_block_to_ififo(base, &blk, tagSize); - return ltc_wait(base); -} - -/*! - * @brief Processes tag during AES GCM and CCM. - * - * This function is a sub-process of CCM and GCM encryption and decryption. - * For encryption, it writes computed MAC to the output tag. - * For decryption, it compares the received MAC with the computed MAC. - * - * @param base LTC peripheral base address - * @param[in,out] tag Output computed MAC during encryption or Input received MAC during decryption. - * @param tagSize Size of MAC buffer in bytes. - * @param modeReg LTC Mode Register current value. It is checked to read Enc/Dec bit. - * It is modified and written to LTC Mode Register during decryption. - * @param ctx Index to LTC context registers with computed MAC for encryption process. - */ -static status_t ltc_aes_process_tag(LTC_Type *base, uint8_t *tag, uint32_t tagSize, ltc_mode_t modeReg, uint32_t ctx) -{ - status_t status = kStatus_Success; - if (tag) - { - /* For decrypt, compare received MAC with the computed MAC. */ - if (kLTC_ModeDecrypt == (modeReg & LTC_MD_ENC_MASK)) - { - status = ltc_aes_received_mac_compare(base, tag, tagSize, modeReg); - } - else /* FSL_AES_GCM_TYPE_ENCRYPT */ - { - /* For encryption, write the computed and encrypted MAC to user buffer */ - ltc_get_context(base, &tag[0], tagSize, ctx); - } - } - return status; -} - -/******************************************************************************* - * LTC Common code public - ******************************************************************************/ -void LTC_Init(LTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* ungate clock */ - CLOCK_EnableClock(kCLOCK_Ltc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LTC_Deinit(LTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* gate clock */ - CLOCK_DisableClock(kCLOCK_Ltc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if defined(FSL_FEATURE_LTC_HAS_DPAMS) && FSL_FEATURE_LTC_HAS_DPAMS -void LTC_SetDpaMaskSeed(LTC_Type *base, uint32_t mask) -{ - base->DPAMS = mask; - /* second write as workaround for DPA mask re-seed errata */ - base->DPAMS = mask; -} -#endif /* FSL_FEATURE_LTC_HAS_DPAMS */ - -/******************************************************************************* - * AES Code static - ******************************************************************************/ -static status_t ltc_aes_decrypt_ecb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType) -{ - status_t retval; - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeDecrypt); - - /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */ - if (keyType == kLTC_DecryptKey) - { - base->MD |= (1U << kLTC_ModeRegBitShiftDK); - } - - /* Process data and return status. */ - retval = ltc_process_message_in_sessions(base, &ciphertext[0], size, &plaintext[0]); - return retval; -} - -/******************************************************************************* - * AES Code public - ******************************************************************************/ -status_t LTC_AES_GenerateDecryptKey(LTC_Type *base, const uint8_t *encryptKey, uint8_t *decryptKey, uint32_t keySize) -{ - uint8_t plaintext[LTC_AES_BLOCK_SIZE]; - uint8_t ciphertext[LTC_AES_BLOCK_SIZE]; - status_t status; - - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - - /* ECB decrypt with encrypt key will convert the key in LTC context into decrypt form of the key */ - status = ltc_aes_decrypt_ecb(base, ciphertext, plaintext, LTC_AES_BLOCK_SIZE, encryptKey, keySize, kLTC_EncryptKey); - /* now there is decrypt form of the key in the LTC context, so take it */ - ltc_get_key(base, decryptKey, keySize); - - ltc_clear_all(base, false); - - return status; -} - -status_t LTC_AES_EncryptEcb( - LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t *key, uint32_t keySize) -{ - status_t retval; - - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - /* ECB mode, size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeEncrypt); - - /* Process data and return status. */ - retval = ltc_process_message_in_sessions(base, &plaintext[0], size, &ciphertext[0]); - ltc_clear_all(base, false); - return retval; -} - -status_t LTC_AES_DecryptEcb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType) -{ - status_t status; - - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - /* ECB mode, size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - status = ltc_aes_decrypt_ecb(base, ciphertext, plaintext, size, key, keySize, keyType); - ltc_clear_all(base, false); - return status; -} - -status_t LTC_AES_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize) -{ - status_t retval; - - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - - /* CBC mode, size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeEncrypt); - - /* Write IV data to the context register. */ - ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0); - - /* Process data and return status. */ - retval = ltc_process_message_in_sessions(base, &plaintext[0], size, &ciphertext[0]); - ltc_clear_all(base, false); - return retval; -} - -status_t LTC_AES_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType) -{ - status_t retval; - - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - /* CBC mode, size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */ - if (keyType == kLTC_DecryptKey) - { - base->MD |= (1U << kLTC_ModeRegBitShiftDK); - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeDecrypt); - - /* Write IV data to the context register. */ - ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0); - - /* Process data and return status. */ - retval = ltc_process_message_in_sessions(base, &ciphertext[0], size, &plaintext[0]); - ltc_clear_all(base, false); - return retval; -} - -status_t LTC_AES_CryptCtr(LTC_Type *base, - const uint8_t *input, - uint8_t *output, - uint32_t size, - uint8_t counter[LTC_AES_BLOCK_SIZE], - const uint8_t *key, - uint32_t keySize, - uint8_t counterlast[LTC_AES_BLOCK_SIZE], - uint32_t *szLeft) -{ - status_t retval; - uint32_t lastSize; - - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - - lastSize = 0U; - if (counterlast != NULL) - { - /* Split the size into full 16-byte chunks and last incomplete block due to LTC AES OFIFO errata */ - if (size <= 16U) - { - lastSize = size; - size = 0U; - } - else - { - /* Process all 16-byte data chunks. */ - lastSize = size % 16U; - if (lastSize == 0U) - { - lastSize = 16U; - size -= 16U; - } - else - { - size -= lastSize; /* size will be rounded down to 16 byte boundary. remaining bytes in lastSize */ - } - } - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCTR, kLTC_ModeEncrypt); - - /* Write initial counter data to the context register. - * NOTE the counter values start at 4-bytes offset into the context. */ - ltc_set_context(base, &counter[0], 16U, 4U); - - /* Process data and return status. */ - retval = ltc_process_message_in_sessions(base, input, size, output); - if (kStatus_Success != retval) - { - return retval; - } - - input += size; - output += size; - - if ((counterlast != NULL) && lastSize) - { - uint8_t zeroes[16] = {0}; - ltc_mode_t modeReg; - - modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeCTR | (uint32_t)kLTC_ModeEncrypt; - /* Write the mode register to the hardware. */ - base->MD = modeReg | (uint32_t)kLTC_ModeFinalize; - - /* context is re-used (CTRi) */ - - /* Process data and return status. */ - retval = ltc_symmetric_process_data(base, input, lastSize, output); - if (kStatus_Success != retval) - { - return retval; - } - if (szLeft) - { - *szLeft = 16U - lastSize; - } - - /* Initialize algorithm state. */ - base->MD = modeReg | (uint32_t)kLTC_ModeUpdate; - - /* context is re-used (CTRi) */ - - /* Process data and return status. */ - retval = ltc_symmetric_process_data(base, zeroes, 16U, counterlast); - } - ltc_get_context(base, &counter[0], 16U, 4U); - ltc_clear_all(base, false); - return retval; -} - -#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM -/******************************************************************************* - * GCM Code static - ******************************************************************************/ -static status_t ltc_aes_gcm_check_input_args(LTC_Type *base, - const uint8_t *src, - const uint8_t *iv, - const uint8_t *aad, - const uint8_t *key, - uint8_t *dst, - uint32_t inputSize, - uint32_t ivSize, - uint32_t aadSize, - uint32_t keySize, - uint32_t tagSize) -{ - if (!base) - { - return kStatus_InvalidArgument; - } - - /* tag can be NULL to skip tag processing */ - if ((!key) || (ivSize && (!iv)) || (aadSize && (!aad)) || (inputSize && ((!src) || (!dst)))) - { - return kStatus_InvalidArgument; - } - - /* octet length of tag (tagSize) must be element of 4,8,12,13,14,15,16 */ - if (((tagSize > 16u) || (tagSize < 12u)) && (tagSize != 4u) && (tagSize != 8u)) - { - return kStatus_InvalidArgument; - } - - /* check if keySize is supported */ - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - - /* no IV AAD DATA makes no sense */ - if (0 == (inputSize + ivSize + aadSize)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Process Wrapper for void (*pfunc)(LTC_Type*, uint32_t, bool). Sets IV Size register. - */ -static void ivsize_next(LTC_Type *base, uint32_t ivSize, bool iv_only) -{ - base->IVSZ = LTC_IVSZ_IL(iv_only) | ((ivSize)<C_DS_DS_MASK); -} - -/*! - * @brief Process Wrapper for void (*pfunc)(LTC_Type*, uint32_t, bool). Sets AAD Size register. - */ -static void aadsize_next(LTC_Type *base, uint32_t aadSize, bool aad_only) -{ - base->AADSZ = LTC_AADSZ_AL(aad_only) | ((aadSize)<C_DS_DS_MASK); -} - -/*! - * @brief Process IV or AAD string in multi-session. - * - * @param base LTC peripheral base address - * @param iv IV or AAD data - * @param ivSize Size in bytes of IV or AAD data - * @param modeReg LTC peripheral Mode register value - * @param iv_only IV only or AAD only flag - * @param type selects between IV or AAD - */ -static status_t ltc_aes_gcm_process_iv_aad( - LTC_Type *base, const uint8_t *iv, uint32_t ivSize, ltc_mode_t modeReg, bool iv_only, int type, ltc_mode_t modeLast) -{ - uint32_t sz; - status_t retval; - void (*next_size_func)(LTC_Type *ltcBase, uint32_t nextSize, bool authOnly); - - if ((NULL == iv) || (ivSize == 0)) - { - return kStatus_InvalidArgument; - } - - sz = LTC_FIFO_SZ_MAX_DOWN_ALGN; - next_size_func = type == LTC_AES_GCM_TYPE_AAD ? aadsize_next : ivsize_next; - - while (ivSize) - { - if (ivSize < sz) - { - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= modeLast; - base->MD = modeReg; - next_size_func(base, ivSize, iv_only); - ltc_move_to_ififo(base, iv, ivSize); - ivSize = 0; - } - else - { - /* set algorithm state to UPDATE */ - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= kLTC_ModeUpdate; - base->MD = modeReg; - - next_size_func(base, (uint16_t)sz, true); - ltc_move_to_ififo(base, iv, sz); - ivSize -= sz; - iv += sz; - } - - retval = ltc_wait(base); - if (kStatus_Success != retval) - { - return retval; - } - } /* end while */ - return kStatus_Success; -} - -static status_t ltc_aes_gcm_process(LTC_Type *base, - ltc_mode_encrypt_t encryptMode, - const uint8_t *src, - uint32_t inputSize, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *dst, - uint8_t *tag, - uint32_t tagSize) -{ - status_t retval; /* return value */ - uint32_t max_ltc_fifo_sz; /* maximum data size that we can put to LTC FIFO in one session. 12-bit limit. */ - ltc_mode_t modeReg; /* read and write LTC mode register */ - - bool single_ses_proc_all; /* iv, aad and src data can be processed in one session */ - bool iv_only; - bool aad_only; - - retval = ltc_aes_gcm_check_input_args(base, src, iv, aad, key, dst, inputSize, ivSize, aadSize, keySize, tagSize); - - /* API input validation */ - if (kStatus_Success != retval) - { - return retval; - } - - max_ltc_fifo_sz = LTC_DS_DS_MASK; /* 12-bit field limit */ - - /* - * Write value to LTC AADSIZE (rounded up to next 16 byte boundary) - * plus the write value to LTC IV (rounded up to next 16 byte boundary) - * plus the inputSize. If the result is less than max_ltc_fifo_sz - * then all can be processed in one session FINALIZE. - * Otherwise, we have to split into multiple session, going through UPDATE(s), INITIALIZE, UPDATE(s) and FINALIZE. - */ - single_ses_proc_all = - (((aadSize + 15u) & 0xfffffff0u) + ((ivSize + 15u) & 0xfffffff0u) + inputSize) <= max_ltc_fifo_sz; - - /* setup key, algorithm and set the alg.state */ - if (single_ses_proc_all) - { - ltc_symmetric_final(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeGCM, encryptMode); - modeReg = base->MD; - - iv_only = (aadSize == 0) && (inputSize == 0); - aad_only = (inputSize == 0); - - /* DS_MASK here is not a bug. IV size field can be written with more than 4-bits, - * as the IVSZ write value, aligned to next 16 bytes boundary, is written also to the Data Size. - * For example, I can write 22 to IVSZ, 32 will be written to Data Size and IVSZ will have value 6, which is 22 - * mod 16. - */ - base->IVSZ = LTC_IVSZ_IL(iv_only) | ((ivSize)<C_DS_DS_MASK); - ltc_move_to_ififo(base, iv, ivSize); - if (iv_only && ivSize) - { - retval = ltc_wait(base); - if (kStatus_Success != retval) - { - return retval; - } - } - base->AADSZ = LTC_AADSZ_AL(aad_only) | ((aadSize)<C_DS_DS_MASK); - ltc_move_to_ififo(base, aad, aadSize); - if (aad_only && aadSize) - { - retval = ltc_wait(base); - if (kStatus_Success != retval) - { - return retval; - } - } - - if (inputSize) - { - /* Workaround for the LTC Data Size register update errata TKT261180 */ - while (16U < base->DS) - { - } - - ltc_symmetric_process_data(base, &src[0], inputSize, &dst[0]); - } - } - else - { - ltc_symmetric_init(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeGCM, encryptMode); - modeReg = base->MD; - - /* process IV */ - if (ivSize) - { - /* last chunk of IV is always INITIALIZE (for GHASH to occur) */ - retval = ltc_aes_gcm_process_iv_aad(base, iv, ivSize, modeReg, true, LTC_AES_GCM_TYPE_IV, kLTC_ModeInit); - if (kStatus_Success != retval) - { - return retval; - } - } - - /* process AAD */ - if (aadSize) - { - /* AS mode to process last chunk of AAD. it differs if we are in GMAC or GCM */ - ltc_mode_t lastModeReg; - if (0 == inputSize) - { - /* if there is no DATA, set mode to compute final MAC. this is GMAC mode */ - lastModeReg = kLTC_ModeInitFinal; - } - else - { - /* there are confidential DATA. so process last chunk of AAD in UPDATE mode */ - lastModeReg = kLTC_ModeUpdate; - } - retval = ltc_aes_gcm_process_iv_aad(base, aad, aadSize, modeReg, true, LTC_AES_GCM_TYPE_AAD, lastModeReg); - if (kStatus_Success != retval) - { - return retval; - } - } - - /* there are DATA. */ - if (inputSize) - { - /* set algorithm state to UPDATE */ - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= kLTC_ModeUpdate; - base->MD = modeReg; - retval = - ltc_symmetric_process_data_multiple(base, &src[0], inputSize, &dst[0], modeReg, kLTC_ModeInitFinal); - } - } - if (kStatus_Success != retval) - { - return retval; - } - retval = ltc_aes_process_tag(base, tag, tagSize, modeReg, LTC_GCM_TAG_IDX); - return retval; -} - -/******************************************************************************* - * GCM Code public - ******************************************************************************/ -status_t LTC_AES_EncryptTagGcm(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *tag, - uint32_t tagSize) -{ - status_t status; - - status = ltc_aes_gcm_process(base, kLTC_ModeEncrypt, plaintext, size, iv, ivSize, aad, aadSize, key, keySize, - ciphertext, tag, tagSize); - - ltc_clear_all(base, false); - return status; -} - -status_t LTC_AES_DecryptTagGcm(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - const uint8_t *tag, - uint32_t tagSize) -{ - uint8_t temp_tag[16] = {0}; /* max. octet length of Integrity Check Value ICV (tag) is 16 */ - uint8_t *tag_ptr; - status_t status; - - tag_ptr = NULL; - if (tag) - { - ltc_memcpy(temp_tag, tag, tagSize); - tag_ptr = &temp_tag[0]; - } - status = ltc_aes_gcm_process(base, kLTC_ModeDecrypt, ciphertext, size, iv, ivSize, aad, aadSize, key, keySize, - plaintext, tag_ptr, tagSize); - - ltc_clear_all(base, false); - return status; -} -#endif /* FSL_FEATURE_LTC_HAS_GCM */ - -/******************************************************************************* - * CCM Code static - ******************************************************************************/ -static status_t ltc_aes_ccm_check_input_args(LTC_Type *base, - const uint8_t *src, - const uint8_t *iv, - const uint8_t *key, - uint8_t *dst, - uint32_t ivSize, - uint32_t aadSize, - uint32_t keySize, - uint32_t tagSize) -{ - if (!base) - { - return kStatus_InvalidArgument; - } - - /* tag can be NULL to skip tag processing */ - if ((!src) || (!iv) || (!key) || (!dst)) - { - return kStatus_InvalidArgument; - } - - /* size of Nonce (ivSize) must be element of 7,8,9,10,11,12,13 */ - if ((ivSize < 7u) || (ivSize > 13u)) - { - return kStatus_InvalidArgument; - } - /* octet length of MAC (tagSize) must be element of 4,6,8,10,12,14,16 for tag processing or zero to skip tag - * processing */ - if (((tagSize > 0) && (tagSize < 4u)) || (tagSize > 16u) || (tagSize & 1u)) - { - return kStatus_InvalidArgument; - } - - /* check if keySize is supported */ - if (!ltc_check_key_size(keySize)) - { - return kStatus_InvalidArgument; - } - - /* LTC does not support more AAD than this */ - if (aadSize >= 65280u) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -static uint32_t swap_bytes(uint32_t in) -{ - return (((in & 0x000000ffu) << 24) | ((in & 0x0000ff00u) << 8) | ((in & 0x00ff0000u) >> 8) | - ((in & 0xff000000u) >> 24)); -} - -static void ltc_aes_ccm_context_init( - LTC_Type *base, uint32_t inputSize, const uint8_t *iv, uint32_t ivSize, uint32_t aadSize, uint32_t tagSize) -{ - ltc_xcm_block_t blk; - ltc_xcm_block_t blkZero = {{0x0u, 0x0u, 0x0u, 0x0u}}; - - int q; /* octet length of binary representation of the octet length of the payload. computed as (15 - n), where n is - length of nonce(=ivSize) */ - uint8_t flags; /* flags field in B0 and CTR0 */ - - /* compute B0 */ - ltc_memcpy(&blk, &blkZero, sizeof(blk)); - /* tagSize - size of output MAC */ - q = 15 - ivSize; - flags = (uint8_t)(8 * ((tagSize - 2) / 2) + q - 1); /* 8*M' + L' */ - if (aadSize) - { - flags |= 0x40; /* Adata */ - } - blk.b[0] = flags; /* flags field */ - blk.w[3] = swap_bytes(inputSize); /* message size, most significant byte first */ - ltc_memcpy(&blk.b[1], iv, ivSize); /* nonce field */ - - /* Write B0 data to the context register. - */ - ltc_set_context(base, &blk.b[0], 16, 0); - - /* Write CTR0 to the context register. - */ - ltc_memcpy(&blk, &blkZero, sizeof(blk)); /* ctr(0) field = zero */ - blk.b[0] = q - 1; /* flags field */ - ltc_memcpy(&blk.b[1], iv, ivSize); /* nonce field */ - ltc_set_context(base, &blk.b[0], 16, 4); -} - -static status_t ltc_aes_ccm_process_aad( - LTC_Type *base, uint32_t inputSize, const uint8_t *aad, uint32_t aadSize, ltc_mode_t *modeReg) -{ - ltc_xcm_block_t blk = {{0x0u, 0x0u, 0x0u, 0x0u}}; - uint32_t swapped; /* holds byte swap of uint32_t */ - status_t retval; - - if (aadSize) - { - bool aad_only; - bool aad_single_session; - - uint32_t sz = 0; - - aad_only = inputSize == 0u; - aad_single_session = (((aadSize + 2u) + 15u) & 0xfffffff0u) <= LTC_FIFO_SZ_MAX_DOWN_ALGN; - - /* limit by CCM spec: 2^16 - 2^8 = 65280 */ - - /* encoding is two octets, msbyte first */ - swapped = swap_bytes(aadSize); - ltc_memcpy(&blk.b[0], ((uint8_t *)&swapped) + sizeof(uint16_t), sizeof(uint16_t)); - - sz = aadSize > 14u ? 14u : aadSize; /* limit aad to the end of 16 bytes blk */ - ltc_memcpy(&blk.b[2], aad, sz); /* fill B1 with aad */ - - if (aad_single_session) - { - base->AADSZ = LTC_AADSZ_AL(aad_only) | ((aadSize + 2U) & LTC_DS_DS_MASK); - /* move first AAD block (16 bytes block B1) to FIFO */ - ltc_move_block_to_ififo(base, &blk, sizeof(blk)); - } - else - { - base->AADSZ = LTC_AADSZ_AL(true) | (16U); - /* move first AAD block (16 bytes block B1) to FIFO */ - ltc_move_block_to_ififo(base, &blk, sizeof(blk)); - } - - /* track consumed AAD. sz bytes have been moved to fifo. */ - aadSize -= sz; - aad += sz; - - if (aad_single_session) - { - /* move remaining AAD to FIFO, then return, to continue with MDATA */ - ltc_move_to_ififo(base, aad, aadSize); - } - else if (aadSize == 0u) - { - retval = ltc_wait(base); - if (kStatus_Success != retval) - { - return retval; - } - } - else - { - while (aadSize) - { - retval = ltc_wait(base); - if (kStatus_Success != retval) - { - return retval; - } - - *modeReg &= ~LTC_MD_AS_MASK; - *modeReg |= (uint32_t)kLTC_ModeUpdate; - base->MD = *modeReg; - - sz = LTC_FIFO_SZ_MAX_DOWN_ALGN; - if (aadSize < sz) - { - base->AADSZ = LTC_AADSZ_AL(aad_only) | (aadSize & LTC_DS_DS_MASK); - ltc_move_to_ififo(base, aad, aadSize); - aadSize = 0; - } - else - { - base->AADSZ = LTC_AADSZ_AL(true) | (sz & LTC_DS_DS_MASK); - ltc_move_to_ififo(base, aad, sz); - aadSize -= sz; - aad += sz; - } - } /* end while */ - } /* end else */ - } /* end if */ - return kStatus_Success; -} - -static status_t ltc_aes_ccm_process(LTC_Type *base, - ltc_mode_encrypt_t encryptMode, - const uint8_t *src, - uint32_t inputSize, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *dst, - uint8_t *tag, - uint32_t tagSize) -{ - status_t retval; /* return value */ - uint32_t max_ltc_fifo_sz; /* maximum data size that we can put to LTC FIFO in one session. 12-bit limit. */ - ltc_mode_t modeReg; /* read and write LTC mode register */ - - bool single_ses_proc_all; /* aad and src data can be processed in one session */ - - retval = ltc_aes_ccm_check_input_args(base, src, iv, key, dst, ivSize, aadSize, keySize, tagSize); - - /* API input validation */ - if (kStatus_Success != retval) - { - return retval; - } - - max_ltc_fifo_sz = LTC_DS_DS_MASK; /* 12-bit field limit */ - - /* Write value to LTC AADSIZE will be (aadSize+2) value. - * The value will be rounded up to next 16 byte boundary and added to Data Size register. - * We then add inputSize to Data Size register. If the resulting Data Size is less than max_ltc_fifo_sz - * then all can be processed in one session INITIALIZE/FINALIZE. - * Otherwise, we have to split into multiple session, going through INITIALIZE, UPDATE (if required) and FINALIZE. - */ - single_ses_proc_all = ((((aadSize + 2) + 15u) & 0xfffffff0u) + inputSize) <= max_ltc_fifo_sz; - - /* setup key, algorithm and set the alg.state to INITIALIZE */ - if (single_ses_proc_all) - { - ltc_symmetric_init_final(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCCM, encryptMode); - } - else - { - ltc_symmetric_init(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCCM, encryptMode); - } - modeReg = base->MD; - - /* Initialize LTC context for AES CCM: block B0 and initial counter CTR0 */ - ltc_aes_ccm_context_init(base, inputSize, iv, ivSize, aadSize, tagSize); - - /* Process additional authentication data, if there are any. - * Need to split the job into individual sessions of up to 4096 bytes, due to LTC IFIFO data size limit. - */ - retval = ltc_aes_ccm_process_aad(base, inputSize, aad, aadSize, &modeReg); - if (kStatus_Success != retval) - { - return retval; - } - - /* Workaround for the LTC Data Size register update errata TKT261180 */ - if (inputSize) - { - while (16u < base->DS) - { - } - } - - /* Process message */ - if (single_ses_proc_all) - { - retval = ltc_symmetric_process_data(base, &src[0], inputSize, &dst[0]); - } - else - { - retval = ltc_symmetric_process_data_multiple(base, &src[0], inputSize, &dst[0], modeReg, kLTC_ModeFinalize); - } - if (kStatus_Success != retval) - { - return retval; - } - retval = ltc_aes_process_tag(base, tag, tagSize, modeReg, LTC_CCM_TAG_IDX); - return retval; -} - -/******************************************************************************* - * CCM Code public - ******************************************************************************/ -status_t LTC_AES_EncryptTagCcm(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *tag, - uint32_t tagSize) -{ - status_t status; - status = ltc_aes_ccm_process(base, kLTC_ModeEncrypt, plaintext, size, iv, ivSize, aad, aadSize, key, keySize, - ciphertext, tag, tagSize); - - ltc_clear_all(base, false); - return status; -} - -status_t LTC_AES_DecryptTagCcm(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - const uint8_t *tag, - uint32_t tagSize) -{ - uint8_t temp_tag[16] = {0}; /* max. octet length of MAC (tag) is 16 */ - uint8_t *tag_ptr; - status_t status; - - tag_ptr = NULL; - if (tag) - { - ltc_memcpy(temp_tag, tag, tagSize); - tag_ptr = &temp_tag[0]; - } - - status = ltc_aes_ccm_process(base, kLTC_ModeDecrypt, ciphertext, size, iv, ivSize, aad, aadSize, key, keySize, - plaintext, tag_ptr, tagSize); - - ltc_clear_all(base, false); - return status; -} - -#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES -/******************************************************************************* - * DES / 3DES Code static - ******************************************************************************/ -static status_t ltc_des_process(LTC_Type *base, - const uint8_t *input, - uint8_t *output, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE], - ltc_mode_symmetric_alg_t modeAs, - ltc_mode_encrypt_t modeEnc) -{ - status_t retval; - - /* all but OFB, size must be 8-byte multiple */ - if ((modeAs != kLTC_ModeOFB) && ((size < 8u) || (size % 8u))) - { - return kStatus_InvalidArgument; - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, &key[0], LTC_DES_KEY_SIZE, kLTC_AlgorithmDES, modeAs, modeEnc); - - if ((modeAs != kLTC_ModeECB)) - { - ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0); - } - - /* Process data and return status. */ - retval = ltc_process_message_in_sessions(base, input, size, output); - ltc_clear_all(base, false); - return retval; -} - -status_t ltc_3des_check_input_args(ltc_mode_symmetric_alg_t modeAs, - uint32_t size, - const uint8_t *key1, - const uint8_t *key2) -{ - /* all but OFB, size must be 8-byte multiple */ - if ((modeAs != kLTC_ModeOFB) && ((size < 8u) || (size % 8u))) - { - return kStatus_InvalidArgument; - } - - if ((key1 == NULL) || (key2 == NULL)) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -static status_t ltc_3des_process(LTC_Type *base, - const uint8_t *input, - uint8_t *output, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE], - ltc_mode_symmetric_alg_t modeAs, - ltc_mode_encrypt_t modeEnc) -{ - status_t retval; - uint8_t key[LTC_DES_KEY_SIZE * 3]; - uint8_t keySize = LTC_DES_KEY_SIZE * 2; - - retval = ltc_3des_check_input_args(modeAs, size, key1, key2); - if (kStatus_Success != retval) - { - return retval; - } - - ltc_memcpy(&key[0], &key1[0], LTC_DES_KEY_SIZE); - ltc_memcpy(&key[LTC_DES_KEY_SIZE], &key2[0], LTC_DES_KEY_SIZE); - if (key3) - { - ltc_memcpy(&key[LTC_DES_KEY_SIZE * 2], &key3[0], LTC_DES_KEY_SIZE); - keySize = sizeof(key); - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, &key[0], keySize, kLTC_Algorithm3DES, modeAs, modeEnc); - - if ((modeAs != kLTC_ModeECB)) - { - ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0); - } - - /* Process data and return status. */ - retval = ltc_process_message_in_sessions(base, input, size, output); - ltc_clear_all(base, false); - return retval; -} -/******************************************************************************* - * DES / 3DES Code public - ******************************************************************************/ -status_t LTC_DES_EncryptEcb( - LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, plaintext, ciphertext, size, NULL, key, kLTC_ModeECB, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptEcb( - LTC_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, ciphertext, plaintext, size, NULL, key, kLTC_ModeECB, kLTC_ModeDecrypt); -} - -status_t LTC_DES_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, plaintext, ciphertext, size, iv, key, kLTC_ModeCBC, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, ciphertext, plaintext, size, iv, key, kLTC_ModeCBC, kLTC_ModeDecrypt); -} - -status_t LTC_DES_EncryptCfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, plaintext, ciphertext, size, iv, key, kLTC_ModeCFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptCfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, ciphertext, plaintext, size, iv, key, kLTC_ModeCFB, kLTC_ModeDecrypt); -} - -status_t LTC_DES_EncryptOfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, plaintext, ciphertext, size, iv, key, kLTC_ModeOFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptOfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process(base, ciphertext, plaintext, size, iv, key, kLTC_ModeOFB, kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptEcb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, NULL, key1, key2, NULL, kLTC_ModeECB, kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptEcb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, NULL, key1, key2, key3, kLTC_ModeECB, kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptEcb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, NULL, key1, key2, NULL, kLTC_ModeECB, kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptEcb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, NULL, key1, key2, key3, kLTC_ModeECB, kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCBC, kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCBC, kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCBC, kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCBC, kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptCfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptCfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptCfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCFB, kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptCfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCFB, kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptOfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeOFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptOfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeOFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptOfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeOFB, kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptOfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeOFB, kLTC_ModeDecrypt); -} -#endif /* FSL_FEATURE_LTC_HAS_DES */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA -#define LTC_SHA_BLOCK_SIZE 64 /*!< SHA-1, SHA-224 & SHA-256 block size */ -#define LTC_HASH_BLOCK_SIZE LTC_SHA_BLOCK_SIZE /*!< LTC hash block size */ - -enum _ltc_sha_digest_len -{ - kLTC_RunLenSha1 = 28u, - kLTC_OutLenSha1 = 20u, - kLTC_RunLenSha224 = 40u, - kLTC_OutLenSha224 = 28u, - kLTC_RunLenSha256 = 40u, - kLTC_OutLenSha256 = 32u, -}; -#else -#define LTC_HASH_BLOCK_SIZE LTC_AES_BLOCK_SIZE /*!< LTC hash block size */ -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - -/*! Internal states of the HASH creation process */ -typedef enum _ltc_hash_algo_state -{ - kLTC_HashInit = 1u, /*!< Key in the HASH context is the input key. */ - kLTC_HashUpdate, /*!< HASH context has algorithm specific context: MAC, K2 and K3 (XCBC-MAC), MAC and L (CMAC), - running digest (MDHA). Key in the HASH context is the derived key. */ -} ltc_hash_algo_state_t; - -/*! 16/64-byte block represented as byte array or 4/16 32-bit words */ -typedef union _ltc_hash_block -{ - uint32_t w[LTC_HASH_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[LTC_HASH_BLOCK_SIZE]; /*!< byte array */ -} ltc_hash_block_t; - -/*! Definitions of indexes into hash context array */ -typedef enum _ltc_hash_ctx_indexes -{ - kLTC_HashCtxKeyStartIdx = 12, /*!< context word array index where key is stored */ - kLTC_HashCtxKeySize = 20, /*!< context word array index where key size is stored */ - kLTC_HashCtxNumWords = 21, /*!< number of context array 32-bit words */ -} ltc_hash_ctx_indexes; - -typedef struct _ltc_hash_ctx_internal -{ - ltc_hash_block_t blk; /*!< memory buffer. only full 64/16-byte blocks are written to LTC during hash updates */ - uint32_t blksz; /*!< number of valid bytes in memory buffer */ - LTC_Type *base; /*!< LTC peripheral base address */ - ltc_hash_algo_t algo; /*!< selected algorithm from the set of supported algorithms in ltc_drv_hash_algo */ - ltc_hash_algo_state_t state; /*!< finite machine state of the hash software process */ - uint32_t word[kLTC_HashCtxNumWords]; /*!< LTC module context that needs to be saved/restored between LTC jobs */ -} ltc_hash_ctx_internal_t; - -/******************************************************************************* - * HASH Code static - ******************************************************************************/ -static status_t ltc_hash_check_input_alg(ltc_hash_algo_t algo) -{ - if ((algo != kLTC_XcbcMac) && (algo != kLTC_Cmac) -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - && (algo != kLTC_Sha1) && (algo != kLTC_Sha224) && (algo != kLTC_Sha256) -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - ) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -static inline bool ltc_hash_alg_is_cmac(ltc_hash_algo_t algo) -{ - return ((algo == kLTC_XcbcMac) || (algo == kLTC_Cmac)); -} - -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA -static inline bool ltc_hash_alg_is_sha(ltc_hash_algo_t algo) -{ - return ((algo == kLTC_Sha1) || (algo == kLTC_Sha224) || (algo == kLTC_Sha256)); -} -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - -static status_t ltc_hash_check_input_args( - LTC_Type *base, ltc_hash_ctx_t *ctx, ltc_hash_algo_t algo, const uint8_t *key, uint32_t keySize) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != ltc_hash_check_input_alg(algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - if (ltc_hash_alg_is_cmac(algo)) - { - if ((NULL == key) || (!ltc_check_key_size(keySize))) - { - return kStatus_InvalidArgument; - } - } - - return kStatus_Success; -} - -static status_t ltc_hash_check_context(ltc_hash_ctx_internal_t *ctxInternal, const uint8_t *data) -{ - if ((NULL == data) || (NULL == ctxInternal) || (NULL == ctxInternal->base) || - (kStatus_Success != ltc_hash_check_input_alg(ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -static uint32_t ltc_hash_algo2mode(ltc_hash_algo_t algo, ltc_mode_algorithm_state_t asMode, uint32_t *algOutSize) -{ - uint32_t modeReg = 0u; - uint32_t outSize = 0u; - - /* Set LTC algorithm */ - switch (algo) - { - case kLTC_XcbcMac: - modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeXCBCMAC; - outSize = 16u; - break; - case kLTC_Cmac: - modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeCMAC; - outSize = 16u; - break; -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - case kLTC_Sha1: - modeReg = (uint32_t)kLTC_AlgorithmSHA1; - outSize = kLTC_OutLenSha1; - break; - case kLTC_Sha224: - modeReg = (uint32_t)kLTC_AlgorithmSHA224; - outSize = kLTC_OutLenSha224; - break; - case kLTC_Sha256: - modeReg = (uint32_t)kLTC_AlgorithmSHA256; - outSize = kLTC_OutLenSha256; - break; -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - default: - break; - } - - modeReg |= (uint32_t)asMode; - if (algOutSize) - { - *algOutSize = outSize; - } - - return modeReg; -} - -static void ltc_hash_engine_init(ltc_hash_ctx_internal_t *ctx) -{ - uint8_t *key; - uint32_t keySize; - LTC_Type *base; - ltc_mode_symmetric_alg_t algo; - - base = ctx->base; -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - if (ltc_hash_alg_is_cmac(ctx->algo)) - { -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - /* - * word[kLtcCmacCtxKeySize] = key_length - * word[1-8] = key - */ - keySize = ctx->word[kLTC_HashCtxKeySize]; - key = (uint8_t *)&ctx->word[kLTC_HashCtxKeyStartIdx]; - - /* set LTC mode register to INITIALIZE */ - algo = (ctx->algo == kLTC_XcbcMac) ? kLTC_ModeXCBCMAC : kLTC_ModeCMAC; - ltc_symmetric_init(base, key, keySize, kLTC_AlgorithmAES, algo, kLTC_ModeEncrypt); -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - } - else if (ltc_hash_alg_is_sha(ctx->algo)) - { - /* Clear internal register states. */ - base->CW = (uint32_t)kLTC_ClearAll; - - /* Set byte swap on for several registers we will be reading and writing - * user data to/from. */ - base->CTL |= kLTC_CtrlSwapAll; - } - else - { - /* do nothing in this case */ - } -#endif /* FSL_FEATURE_LTC_HAS_SHA */ -} - -static void ltc_hash_save_context(ltc_hash_ctx_internal_t *ctx) -{ - uint32_t sz; - LTC_Type *base; - - base = ctx->base; - /* Get context size */ - switch (ctx->algo) - { - case kLTC_XcbcMac: - /* - * word[0-3] = mac - * word[3-7] = k3 - * word[8-11] = k2 - * word[kLtcCmacCtxKeySize] = keySize - */ - sz = 12 * sizeof(uint32_t); - break; - case kLTC_Cmac: - /* - * word[0-3] = mac - * word[3-7] = L */ - sz = 8 * sizeof(uint32_t); - break; -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - case kLTC_Sha1: - sz = (kLTC_RunLenSha1); - break; - case kLTC_Sha224: - sz = (kLTC_RunLenSha224); - break; - case kLTC_Sha256: - sz = (kLTC_RunLenSha256); - break; -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - default: - sz = 0; - break; - } - - ltc_get_context(base, (uint8_t *)&ctx->word[0], sz, 0); - - if (true == ltc_hash_alg_is_cmac(ctx->algo)) - { - /* word[12-19] = key */ - ltc_get_key(base, (uint8_t *)&ctx->word[kLTC_HashCtxKeyStartIdx], ctx->word[kLTC_HashCtxKeySize]); - } -} - -static void ltc_hash_restore_context(ltc_hash_ctx_internal_t *ctx) -{ - uint32_t sz; - uint32_t keySize; - LTC_Type *base; - - base = ctx->base; - /* Get context size */ - switch (ctx->algo) - { - case kLTC_XcbcMac: - /* - * word[0-3] = mac - * word[3-7] = k3 - * word[8-11] = k2 - * word[kLtcCmacCtxKeySize] = keySize - */ - sz = 12 * sizeof(uint32_t); - break; - case kLTC_Cmac: - /* - * word[0-3] = mac - * word[3-7] = L */ - sz = 8 * sizeof(uint32_t); - break; -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - case kLTC_Sha1: - sz = (kLTC_RunLenSha1); - break; - case kLTC_Sha224: - sz = (kLTC_RunLenSha224); - break; - case kLTC_Sha256: - sz = (kLTC_RunLenSha256); - break; -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - default: - sz = 0; - break; - } - - ltc_set_context(base, (const uint8_t *)&ctx->word[0], sz, 0); - - if (ltc_hash_alg_is_cmac(ctx->algo)) - { - /* - * word[12-19] = key - * word[kLtcCmacCtxKeySize] = keySize - */ - base->CW = kLTC_ClearKey; /* clear Key and Key Size registers */ - - keySize = ctx->word[kLTC_HashCtxKeySize]; - /* Write the key in place. */ - ltc_set_key(base, (const uint8_t *)&ctx->word[kLTC_HashCtxKeyStartIdx], keySize); - - /* Write the key size. This must be done after writing the key, and this - * action locks the ability to modify the key registers. */ - base->KS = keySize; - } -} - -static void ltc_hash_prepare_context_switch(LTC_Type *base) -{ - base->CW = (uint32_t)kLTC_ClearDataSize | (uint32_t)kLTC_ClearMode; - base->STA = kLTC_StatusDoneIsr; -} - -static uint32_t ltc_hash_get_block_size(ltc_hash_algo_t algo) -{ - if ((algo == kLTC_XcbcMac) || (algo == kLTC_Cmac)) - { - return (uint32_t)LTC_AES_BLOCK_SIZE; - } -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - else if ((algo == kLTC_Sha1) || (algo == kLTC_Sha224) || (algo == kLTC_Sha256)) - { - return (uint32_t)LTC_SHA_BLOCK_SIZE; - } - else - { - return 0; - } -#else - return 0; -#endif -} - -static void ltc_hash_block_to_ififo(LTC_Type *base, const ltc_hash_block_t *blk, uint32_t numBytes, uint32_t blockSize) -{ - uint32_t i = 0; - uint32_t words; - - words = numBytes / 4u; - if (numBytes % 4u) - { - words++; - } - - if (words > blockSize / 4u) - { - words = blockSize / 4u; - } - - while (i < words) - { - if (0U == (base->FIFOSTA & LTC_FIFOSTA_IFF_MASK)) - { - /* Copy data to the input FIFO. */ - base->IFIFO = blk->w[i++]; - } - } -} - -static void ltc_hash_move_to_ififo(ltc_hash_ctx_internal_t *ctx, - const uint8_t *data, - uint32_t dataSize, - uint32_t blockSize) -{ - ltc_hash_block_t blkZero; - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(blkZero.w); i++) - { - blkZero.w[i] = 0; - } - - while (dataSize) - { - if (dataSize >= blockSize) - { - ltc_memcpy(&ctx->blk, data, blockSize); - ltc_hash_block_to_ififo(ctx->base, &ctx->blk, blockSize, blockSize); - dataSize -= blockSize; - data += blockSize; - } - else - { - /* last incomplete 16/64-bytes block of this message chunk */ - ltc_memcpy(&ctx->blk, &blkZero, sizeof(ctx->blk)); - ltc_memcpy(&ctx->blk, data, dataSize); - ctx->blksz = dataSize; - dataSize = 0; - } - } -} - -static status_t ltc_hash_merge_and_flush_buf(ltc_hash_ctx_internal_t *ctx, - const uint8_t *input, - uint32_t inputSize, - ltc_mode_t modeReg, - uint32_t blockSize, - uint32_t *consumedSize) -{ - uint32_t sz; - LTC_Type *base; - status_t status = kStatus_Success; - - base = ctx->base; - sz = 0; - if (ctx->blksz) - { - sz = blockSize - ctx->blksz; - if (sz > inputSize) - { - sz = inputSize; - } - ltc_memcpy(ctx->blk.b + ctx->blksz, input, sz); - input += sz; - inputSize -= sz; - ctx->blksz += sz; - - if (ctx->blksz == blockSize) - { - base->DS = blockSize; - ltc_hash_block_to_ififo(base, &ctx->blk, blockSize, blockSize); - ctx->blksz = 0; - - status = ltc_wait(base); - if (kStatus_Success != status) - { - return status; - } - - /* if there is still inputSize left, make sure LTC alg.state is set to UPDATE and continue */ - if (inputSize) - { - /* set algorithm state to UPDATE */ - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= kLTC_ModeUpdate; - base->MD = modeReg; - } - } - } - if (consumedSize) - { - *consumedSize = sz; - } - return status; -} - -static status_t ltc_hash_move_rest_to_context( - ltc_hash_ctx_internal_t *ctx, const uint8_t *data, uint32_t dataSize, ltc_mode_t modeReg, uint32_t blockSize) -{ - status_t status = kStatus_Success; - ltc_hash_block_t blkZero; - uint32_t i; - - /* make blkZero clear */ - for (i = 0; i < ARRAY_SIZE(blkZero.w); i++) - { - blkZero.w[i] = 0; - } - - while (dataSize) - { - if (dataSize > blockSize) - { - dataSize -= blockSize; - data += blockSize; - } - else - { - if (dataSize + ctx->blksz > blockSize) - { - uint32_t sz; - status = ltc_hash_merge_and_flush_buf(ctx, data, dataSize, modeReg, blockSize, &sz); - if (kStatus_Success != status) - { - return status; - } - data += sz; - dataSize -= sz; - } - /* last incomplete 16/64-bytes block of this message chunk */ - ltc_memcpy(&ctx->blk, &blkZero, blockSize); - ltc_memcpy(&ctx->blk, data, dataSize); - ctx->blksz = dataSize; - dataSize = 0; - } - } - return status; -} - -static status_t ltc_hash_process_input_data(ltc_hash_ctx_internal_t *ctx, - const uint8_t *input, - uint32_t inputSize, - ltc_mode_t modeReg) -{ - uint32_t sz = 0; - LTC_Type *base; - uint32_t blockSize = 0; - status_t status = kStatus_Success; - - blockSize = ltc_hash_get_block_size(ctx->algo); - base = ctx->base; - - /* fill context struct blk and flush to LTC ififo in case it is full block */ - status = ltc_hash_merge_and_flush_buf(ctx, input, inputSize, modeReg, blockSize, &sz); - if (kStatus_Success != status) - { - return status; - } - input += sz; - inputSize -= sz; - - /* if there is still more than or equal to 64 bytes, move each 64 bytes through LTC */ - sz = LTC_DS_DS_MASK + 1u - LTC_HASH_BLOCK_SIZE; - while (inputSize) - { - if (inputSize < sz) - { - uint32_t lastSize; - - lastSize = inputSize % blockSize; - if (lastSize == 0) - { - lastSize = blockSize; - } - inputSize -= lastSize; - if (inputSize) - { - /* move all complete blocks to ififo. */ - base->DS = inputSize; - ltc_hash_move_to_ififo(ctx, input, inputSize, blockSize); - - status = ltc_wait(base); - if (kStatus_Success != status) - { - return status; - } - - input += inputSize; - } - /* keep last (in)complete 16-bytes block in context struct. */ - /* when 3rd argument of cmac_move_to_ififo() is <= 16 bytes, it only stores the data to context struct */ - status = ltc_hash_move_rest_to_context(ctx, input, lastSize, modeReg, blockSize); - if (kStatus_Success != status) - { - return status; - } - inputSize = 0; - } - else - { - base->DS = sz; - ltc_hash_move_to_ififo(ctx, input, sz, blockSize); - inputSize -= sz; - input += sz; - - status = ltc_wait(base); - if (kStatus_Success != status) - { - return status; - } - - /* set algorithm state to UPDATE */ - modeReg &= ~LTC_MD_AS_MASK; - modeReg |= kLTC_ModeUpdate; - base->MD = modeReg; - } - } /* end while */ - - return status; -} - -/******************************************************************************* - * HASH Code public - ******************************************************************************/ -status_t LTC_HASH_Init(LTC_Type *base, ltc_hash_ctx_t *ctx, ltc_hash_algo_t algo, const uint8_t *key, uint32_t keySize) -{ - status_t ret; - ltc_hash_ctx_internal_t *ctxInternal; - uint32_t i; - - ret = ltc_hash_check_input_args(base, ctx, algo, key, keySize); - if (ret != kStatus_Success) - { - return ret; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (ltc_hash_ctx_internal_t *)ctx; - ctxInternal->algo = algo; - for (i = 0; i < kLTC_HashCtxNumWords; i++) - { - ctxInternal->word[i] = 0u; - } - - /* Steps required only using AES engine */ - if (ltc_hash_alg_is_cmac(algo)) - { - /* store input key and key length in context struct for later use */ - ctxInternal->word[kLTC_HashCtxKeySize] = keySize; - ltc_memcpy(&ctxInternal->word[kLTC_HashCtxKeyStartIdx], key, keySize); - } - ctxInternal->blksz = 0u; - for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[0] = 0u; - } - ctxInternal->state = kLTC_HashInit; - ctxInternal->base = base; - - return kStatus_Success; -} - -status_t LTC_HASH_Update(ltc_hash_ctx_t *ctx, const uint8_t *input, uint32_t inputSize) -{ - bool isUpdateState; - ltc_mode_t modeReg = 0; /* read and write LTC mode register */ - LTC_Type *base; - status_t status; - ltc_hash_ctx_internal_t *ctxInternal; - uint32_t blockSize; - - ctxInternal = (ltc_hash_ctx_internal_t *)ctx; - status = ltc_hash_check_context(ctxInternal, input); - if (kStatus_Success != status) - { - return status; - } - - base = ctxInternal->base; - blockSize = ltc_hash_get_block_size(ctxInternal->algo); - /* if we are still less than 64 bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - ltc_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return status; - } - else - { - isUpdateState = ctxInternal->state == kLTC_HashUpdate; - if (ctxInternal->state == kLTC_HashInit) - { - /* set LTC mode register to INITIALIZE job */ - ltc_hash_engine_init(ctxInternal); - -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - if (ltc_hash_alg_is_cmac(ctxInternal->algo)) - { -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - ctxInternal->state = kLTC_HashUpdate; - isUpdateState = true; - base->DS = 0u; - status = ltc_wait(base); -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - } - else - { - /* Set the proper block and algorithm mode. */ - modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeInit, NULL); - base->MD = modeReg; - - ctxInternal->state = kLTC_HashUpdate; - status = ltc_hash_process_input_data(ctxInternal, input, inputSize, modeReg); - ltc_hash_save_context(ctxInternal); - } -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - } - else if (isUpdateState) - { - /* restore LTC context from context struct */ - ltc_hash_restore_context(ctxInternal); - } - else - { - /* nothing special at this place */ - } - } - - if (kStatus_Success != status) - { - return status; - } - - if (isUpdateState) - { - /* set LTC mode register to UPDATE job */ - ltc_hash_prepare_context_switch(base); - base->CW = kLTC_ClearDataSize; - modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeUpdate, NULL); - base->MD = modeReg; - - /* process input data and save LTC context to context structure */ - status = ltc_hash_process_input_data(ctxInternal, input, inputSize, modeReg); - ltc_hash_save_context(ctxInternal); - } - ltc_clear_all(base, false); - return status; -} - -status_t LTC_HASH_Finish(ltc_hash_ctx_t *ctx, uint8_t *output, uint32_t *outputSize) -{ - ltc_mode_t modeReg; /* read and write LTC mode register */ - LTC_Type *base; - uint32_t algOutSize = 0; - status_t status; - ltc_hash_ctx_internal_t *ctxInternal; - uint32_t *ctxW; - uint32_t i; - - ctxInternal = (ltc_hash_ctx_internal_t *)ctx; - status = ltc_hash_check_context(ctxInternal, output); - if (kStatus_Success != status) - { - return status; - } - - base = ctxInternal->base; - ltc_hash_prepare_context_switch(base); - - base->CW = kLTC_ClearDataSize; - if (ctxInternal->state == kLTC_HashInit) - { - ltc_hash_engine_init(ctxInternal); -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - if (ltc_hash_alg_is_cmac(ctxInternal->algo)) - { -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - base->DS = 0u; - status = ltc_wait(base); - if (kStatus_Success != status) - { - return status; - } - modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeFinalize, &algOutSize); -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - } - else - { - modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeInitFinal, &algOutSize); - } -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - base->MD = modeReg; - } - else - { - modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeFinalize, &algOutSize); - base->MD = modeReg; - - /* restore LTC context from context struct */ - ltc_hash_restore_context(ctxInternal); - } - - /* flush message last incomplete block, if there is any, or write zero to data size register. */ - base->DS = ctxInternal->blksz; - ltc_hash_block_to_ififo(base, &ctxInternal->blk, ctxInternal->blksz, ltc_hash_get_block_size(ctxInternal->algo)); - /* Wait for finish of the encryption */ - status = ltc_wait(base); - - if (outputSize) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - ltc_get_context(base, &output[0], algOutSize, 0u); - - ctxW = (uint32_t *)ctx; - for (i = 0; i < LTC_HASH_CTX_SIZE; i++) - { - ctxW[i] = 0u; - } - - ltc_clear_all(base, false); - return status; -} - -status_t LTC_HASH(LTC_Type *base, - ltc_hash_algo_t algo, - const uint8_t *input, - uint32_t inputSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *output, - uint32_t *outputSize) -{ - status_t status; - ltc_hash_ctx_t ctx; - - status = LTC_HASH_Init(base, &ctx, algo, key, keySize); - if (status != kStatus_Success) - { - return status; - } - status = LTC_HASH_Update(&ctx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - status = LTC_HASH_Finish(&ctx, output, outputSize); - return status; -} - -/******************************************************************************* - * PKHA Code static - ******************************************************************************/ -#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA -static status_t ltc_pkha_clear_regabne(LTC_Type *base, bool A, bool B, bool N, bool E) -{ - ltc_mode_t mode; - - /* Set the PKHA algorithm and the appropriate function. */ - mode = (uint32_t)kLTC_AlgorithmPKHA | 1U; - - /* Set ram area to clear. Clear all. */ - if (A) - { - mode |= 1U << 19U; - } - if (B) - { - mode |= 1U << 18U; - } - if (N) - { - mode |= 1U << 16U; - } - if (E) - { - mode |= 1U << 17U; - } - - /* Write the mode register to the hardware. - * NOTE: This will begin the operation. */ - base->MDPK = mode; - - /* Wait for 'done' */ - return ltc_wait(base); -} - -static void ltc_pkha_default_parms(ltc_pkha_mode_params_t *params) -{ - params->func = (ltc_pkha_func_t)0; - params->arithType = kLTC_PKHA_IntegerArith; - params->montFormIn = kLTC_PKHA_NormalValue; - params->montFormOut = kLTC_PKHA_NormalValue; - params->srcReg = kLTC_PKHA_RegAll; - params->srcQuad = kLTC_PKHA_Quad0; - params->dstReg = kLTC_PKHA_RegAll; - params->dstQuad = kLTC_PKHA_Quad0; - params->equalTime = kLTC_PKHA_NoTimingEqualized; - params->r2modn = kLTC_PKHA_CalcR2; -} - -static void ltc_pkha_write_word(LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t index, uint32_t data) -{ - switch (reg) - { - case kLTC_PKHA_RegA: - base->PKA[index] = data; - break; - - case kLTC_PKHA_RegB: - base->PKB[index] = data; - break; - - case kLTC_PKHA_RegN: - base->PKN[index] = data; - break; - - case kLTC_PKHA_RegE: - base->PKE[index] = data; - break; - - default: - break; - } -} - -static uint32_t ltc_pkha_read_word(LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t index) -{ - uint32_t retval; - - switch (reg) - { - case kLTC_PKHA_RegA: - retval = base->PKA[index]; - break; - - case kLTC_PKHA_RegB: - retval = base->PKB[index]; - break; - - case kLTC_PKHA_RegN: - retval = base->PKN[index]; - break; - - case kLTC_PKHA_RegE: - retval = base->PKE[index]; - break; - - default: - retval = 0; - break; - } - return retval; -} - -static status_t ltc_pkha_write_reg( - LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t quad, const uint8_t *data, uint16_t dataSize) -{ - /* Select the word-based start index for each quadrant of 64 bytes. */ - uint8_t startIndex = (quad * 16u); - uint32_t outWord; - - while (dataSize > 0) - { - if (dataSize >= sizeof(uint32_t)) - { - ltc_pkha_write_word(base, reg, startIndex++, ltc_get_word_from_unaligned(data)); - dataSize -= sizeof(uint32_t); - data += sizeof(uint32_t); - } - else /* (dataSize > 0) && (dataSize < 4) */ - { - outWord = 0; - ltc_memcpy(&outWord, data, dataSize); - ltc_pkha_write_word(base, reg, startIndex, outWord); - dataSize = 0; - } - } - - return kStatus_Success; -} - -static void ltc_pkha_read_reg(LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t quad, uint8_t *data, uint16_t dataSize) -{ - /* Select the word-based start index for each quadrant of 64 bytes. */ - uint8_t startIndex = (quad * 16u); - uint16_t calcSize; - uint32_t word; - - while (dataSize > 0) - { - word = ltc_pkha_read_word(base, reg, startIndex++); - - calcSize = (dataSize >= sizeof(uint32_t)) ? sizeof(uint32_t) : dataSize; - ltc_memcpy(data, &word, calcSize); - - data += calcSize; - dataSize -= calcSize; - } -} - -static void ltc_pkha_init_data(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - const uint8_t *E, - uint16_t sizeE) -{ - uint32_t clearMask = kLTC_ClearMode; /* clear Mode Register */ - - /* Clear internal register states. */ - if (sizeA) - { - clearMask |= kLTC_ClearPkhaSizeA; - } - if (sizeB) - { - clearMask |= kLTC_ClearPkhaSizeB; - } - if (sizeN) - { - clearMask |= kLTC_ClearPkhaSizeN; - } - if (sizeE) - { - clearMask |= kLTC_ClearPkhaSizeE; - } - - base->CW = clearMask; - base->STA = kLTC_StatusDoneIsr; - ltc_pkha_clear_regabne(base, A, B, N, E); - - /* Write register sizes. */ - /* Write modulus (N) and A and B register arguments. */ - if (sizeN) - { - base->PKNSZ = sizeN; - if (N) - { - ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, sizeN); - } - } - - if (sizeA) - { - base->PKASZ = sizeA; - if (A) - { - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 0, A, sizeA); - } - } - - if (sizeB) - { - base->PKBSZ = sizeB; - if (B) - { - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, B, sizeB); - } - } - - if (sizeE) - { - base->PKESZ = sizeE; - if (E) - { - ltc_pkha_write_reg(base, kLTC_PKHA_RegE, 0, E, sizeE); - } - } -} - -static void ltc_pkha_mode_set_src_reg_copy(ltc_mode_t *outMode, ltc_pkha_reg_area_t reg) -{ - int i = 0; - - do - { - reg = (ltc_pkha_reg_area_t)(((uint32_t)reg) >> 1u); - i++; - } while (reg); - - i = 4 - i; - /* Source register must not be E. */ - if (i != 2) - { - *outMode |= ((uint32_t)i << 17u); - } -} - -static void ltc_pkha_mode_set_dst_reg_copy(ltc_mode_t *outMode, ltc_pkha_reg_area_t reg) -{ - int i = 0; - - do - { - reg = (ltc_pkha_reg_area_t)(((uint32_t)reg) >> 1u); - i++; - } while (reg); - - i = 4 - i; - *outMode |= ((uint32_t)i << 10u); -} - -static void ltc_pkha_mode_set_src_seg_copy(ltc_mode_t *outMode, const ltc_pkha_quad_area_t quad) -{ - *outMode |= ((uint32_t)quad << 8u); -} - -static void ltc_pkha_mode_set_dst_seg_copy(ltc_mode_t *outMode, const ltc_pkha_quad_area_t quad) -{ - *outMode |= ((uint32_t)quad << 6u); -} - -/*! - * @brief Starts the PKHA operation. - * - * This function starts an operation configured by the params parameter. - * - * @param base LTC peripheral base address - * @param params Configuration structure containing all settings required for PKHA operation. - */ -static status_t ltc_pkha_init_mode(LTC_Type *base, const ltc_pkha_mode_params_t *params) -{ - ltc_mode_t modeReg; - status_t retval; - - /* Set the PKHA algorithm and the appropriate function. */ - modeReg = kLTC_AlgorithmPKHA; - modeReg |= (uint32_t)params->func; - - if ((params->func == kLTC_PKHA_CopyMemSizeN) || (params->func == kLTC_PKHA_CopyMemSizeSrc)) - { - /* Set source and destination registers and quads. */ - ltc_pkha_mode_set_src_reg_copy(&modeReg, params->srcReg); - ltc_pkha_mode_set_dst_reg_copy(&modeReg, params->dstReg); - ltc_pkha_mode_set_src_seg_copy(&modeReg, params->srcQuad); - ltc_pkha_mode_set_dst_seg_copy(&modeReg, params->dstQuad); - } - else - { - /* Set the arithmetic type - integer or binary polynomial (F2m). */ - modeReg |= ((uint32_t)params->arithType << 17u); - - /* Set to use Montgomery form of inputs and/or outputs. */ - modeReg |= ((uint32_t)params->montFormIn << 19u); - modeReg |= ((uint32_t)params->montFormOut << 18u); - - /* Set to use pre-computed R2modN */ - modeReg |= ((uint32_t)params->r2modn << 16u); - } - - modeReg |= ((uint32_t)params->equalTime << 10u); - - /* Write the mode register to the hardware. - * NOTE: This will begin the operation. */ - base->MDPK = modeReg; - - retval = ltc_wait(base); - return (retval); -} - -static status_t ltc_pkha_modR2( - LTC_Type *base, const uint8_t *N, uint16_t sizeN, uint8_t *result, uint16_t *resultSize, ltc_pkha_f2m_t arithType) -{ - status_t status; - ltc_pkha_mode_params_t params; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModR2; - params.arithType = arithType; - - ltc_pkha_init_data(base, NULL, 0, NULL, 0, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - return status; -} - -static status_t ltc_pkha_modmul(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType, - ltc_pkha_montgomery_form_t montIn, - ltc_pkha_montgomery_form_t montOut, - ltc_pkha_timing_t equalTime) -{ - ltc_pkha_mode_params_t params; - status_t status; - - if (arithType == kLTC_PKHA_IntegerArith) - { - if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - - if (LTC_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModMul; - params.arithType = arithType; - params.montFormIn = montIn; - params.montFormOut = montOut; - params.equalTime = equalTime; - - ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - return status; -} - -/******************************************************************************* - * PKHA Code public - ******************************************************************************/ -int LTC_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB) -{ - int retval = 0; - - /* skip zero msbytes - integer a */ - while ((sizeA) && (0u == a[sizeA - 1])) - { - sizeA--; - } - - /* skip zero msbytes - integer b */ - while ((sizeB) && (0u == b[sizeB - 1])) - { - sizeB--; - } - - if (sizeA > sizeB) - { - retval = 1; - } /* int a has more non-zero bytes, thus it is bigger than b */ - else if (sizeA < sizeB) - { - retval = -1; - } /* int b has more non-zero bytes, thus it is bigger than a */ - else if (sizeA == 0) - { - retval = 0; - } /* sizeA = sizeB = 0 */ - else - { - int n; - int i; - int val; - uint32_t equal; - - n = sizeA - 1; - i = 0; - equal = 0; - - while (n >= 0) - { - uint32_t chXor = a[i] ^ b[i]; - - equal |= chXor; - val = (int)chXor * (a[i] - b[i]); - - if (val < 0) - { - retval = -1; - } - - if (val > 0) - { - retval = 1; - } - - if (val == 0) - { - val = 1; - } - - if (val) - { - i++; - n--; - } - } - - if (0 == equal) - { - retval = 0; - } - } - return (retval); -} - -status_t LTC_PKHA_NormalToMontgomery(LTC_Type *base, - const uint8_t *N, - uint16_t sizeN, - uint8_t *A, - uint16_t *sizeA, - uint8_t *B, - uint16_t *sizeB, - uint8_t *R2, - uint16_t *sizeR2, - ltc_pkha_timing_t equalTime, - ltc_pkha_f2m_t arithType) -{ - status_t status; - - /* need to convert our Integer inputs into Montgomery format */ - if (N && sizeN && R2 && sizeR2) - { - /* 1. R2 = MOD_R2(N) */ - status = ltc_pkha_modR2(base, N, sizeN, R2, sizeR2, arithType); - if (status != kStatus_Success) - { - return status; - } - - /* 2. A(Montgomery) = MOD_MUL_IM_OM(A, R2, N) */ - if (A && sizeA) - { - status = ltc_pkha_modmul(base, A, *sizeA, R2, *sizeR2, N, sizeN, A, sizeA, arithType, - kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime); - if (status != kStatus_Success) - { - return status; - } - } - - /* 2. B(Montgomery) = MOD_MUL_IM_OM(B, R2, N) */ - if (B && sizeB) - { - status = ltc_pkha_modmul(base, B, *sizeB, R2, *sizeR2, N, sizeN, B, sizeB, arithType, - kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime); - if (status != kStatus_Success) - { - return status; - } - } - - ltc_clear_all(base, true); - } - else - { - status = kStatus_InvalidArgument; - } - - return status; -} - -status_t LTC_PKHA_MontgomeryToNormal(LTC_Type *base, - const uint8_t *N, - uint16_t sizeN, - uint8_t *A, - uint16_t *sizeA, - uint8_t *B, - uint16_t *sizeB, - ltc_pkha_timing_t equalTime, - ltc_pkha_f2m_t arithType) -{ - uint8_t one = 1; - status_t status = kStatus_InvalidArgument; - - /* A = MOD_MUL_IM_OM(A(Montgomery), 1, N) */ - if (A && sizeA) - { - status = ltc_pkha_modmul(base, A, *sizeA, &one, sizeof(one), N, sizeN, A, sizeA, arithType, - kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime); - if (kStatus_Success != status) - { - return status; - } - } - - /* B = MOD_MUL_IM_OM(B(Montgomery), 1, N) */ - if (B && sizeB) - { - status = ltc_pkha_modmul(base, B, *sizeB, &one, sizeof(one), N, sizeN, B, sizeB, arithType, - kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime); - if (kStatus_Success != status) - { - return status; - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModAdd(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType) -{ - ltc_pkha_mode_params_t params; - status_t status; - - if (arithType == kLTC_PKHA_IntegerArith) - { - if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - - if (LTC_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModAdd; - params.arithType = arithType; - - ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModSub1(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize) -{ - ltc_pkha_mode_params_t params; - status_t status; - - if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - - if (LTC_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModSub1; - ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModSub2(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize) -{ - ltc_pkha_mode_params_t params; - status_t status; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModSub2; - - ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModMul(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType, - ltc_pkha_montgomery_form_t montIn, - ltc_pkha_montgomery_form_t montOut, - ltc_pkha_timing_t equalTime) -{ - status_t status; - - status = - ltc_pkha_modmul(base, A, sizeA, B, sizeB, N, sizeN, result, resultSize, arithType, montIn, montOut, equalTime); - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModExp(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - const uint8_t *E, - uint16_t sizeE, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType, - ltc_pkha_montgomery_form_t montIn, - ltc_pkha_timing_t equalTime) -{ - ltc_pkha_mode_params_t params; - status_t status; - - if (arithType == kLTC_PKHA_IntegerArith) - { - if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModExp; - params.arithType = arithType; - params.montFormIn = montIn; - params.equalTime = equalTime; - - ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, E, sizeE); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModRed(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType) -{ - ltc_pkha_mode_params_t params; - status_t status; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModRed; - params.arithType = arithType; - - ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModInv(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType) -{ - ltc_pkha_mode_params_t params; - status_t status; - - /* A must be less than N -> LTC_PKHA_CompareBigNum() must return -1 */ - if (arithType == kLTC_PKHA_IntegerArith) - { - if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithModInv; - params.arithType = arithType; - - ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ModR2( - LTC_Type *base, const uint8_t *N, uint16_t sizeN, uint8_t *result, uint16_t *resultSize, ltc_pkha_f2m_t arithType) -{ - status_t status; - status = ltc_pkha_modR2(base, N, sizeN, result, resultSize, arithType); - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_GCD(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType) -{ - ltc_pkha_mode_params_t params; - status_t status; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithGcd; - params.arithType = arithType; - - ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize); - } - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_PrimalityTest(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - bool *res) -{ - uint8_t result; - ltc_pkha_mode_params_t params; - status_t status; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithPrimalityTest; - ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, &result, 1); - - *res = (bool)result; - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ECC_PointAdd(LTC_Type *base, - const ltc_pkha_ecc_point_t *A, - const ltc_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - uint8_t size, - ltc_pkha_f2m_t arithType, - ltc_pkha_ecc_point_t *result) -{ - ltc_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithEccAdd; - params.arithType = arithType; - params.r2modn = R2modN ? kLTC_PKHA_InputR2 : kLTC_PKHA_CalcR2; - - clearMask = kLTC_ClearMode; - - /* Clear internal register states. */ - clearMask |= kLTC_ClearPkhaSizeA; - clearMask |= kLTC_ClearPkhaSizeB; - clearMask |= kLTC_ClearPkhaSizeN; - clearMask |= kLTC_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kLTC_StatusDoneIsr; - ltc_pkha_clear_regabne(base, true, true, true, false); - - /* sizeN should be less than 64 bytes. */ - base->PKNSZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, size); - - base->PKASZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 0, A->X, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 1, A->Y, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, bCurveParam, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 1, B->X, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 2, B->Y, size); - if (R2modN) - { - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 3, R2modN, size); - } - - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 1, result->X, size); - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 2, result->Y, size); - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ECC_PointDouble(LTC_Type *base, - const ltc_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - uint8_t size, - ltc_pkha_f2m_t arithType, - ltc_pkha_ecc_point_t *result) -{ - ltc_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithEccDouble; - params.arithType = arithType; - - clearMask = kLTC_ClearMode; - - /* Clear internal register states. */ - clearMask |= kLTC_ClearPkhaSizeA; - clearMask |= kLTC_ClearPkhaSizeB; - clearMask |= kLTC_ClearPkhaSizeN; - clearMask |= kLTC_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kLTC_StatusDoneIsr; - ltc_pkha_clear_regabne(base, true, true, true, false); - - /* sizeN should be less than 64 bytes. */ - base->PKNSZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, size); - - base->PKASZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, bCurveParam, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 1, B->X, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 2, B->Y, size); - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 1, result->X, size); - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 2, result->Y, size); - } - - ltc_clear_all(base, true); - return status; -} - -status_t LTC_PKHA_ECC_PointMul(LTC_Type *base, - const ltc_pkha_ecc_point_t *A, - const uint8_t *E, - uint8_t sizeE, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - uint8_t size, - ltc_pkha_timing_t equalTime, - ltc_pkha_f2m_t arithType, - ltc_pkha_ecc_point_t *result, - bool *infinity) -{ - ltc_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - - ltc_pkha_default_parms(¶ms); - params.func = kLTC_PKHA_ArithEccMul; - params.equalTime = equalTime; - params.arithType = arithType; - params.r2modn = R2modN ? kLTC_PKHA_InputR2 : kLTC_PKHA_CalcR2; - - clearMask = kLTC_ClearMode; - - /* Clear internal register states. */ - clearMask |= kLTC_ClearPkhaSizeA; - clearMask |= kLTC_ClearPkhaSizeB; - clearMask |= kLTC_ClearPkhaSizeN; - clearMask |= kLTC_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kLTC_StatusDoneIsr; - ltc_pkha_clear_regabne(base, true, true, true, true); - - /* sizeN should be less than 64 bytes. */ - base->PKNSZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, size); - - base->PKESZ = sizeE; - ltc_pkha_write_reg(base, kLTC_PKHA_RegE, 0, E, sizeE); - - base->PKASZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 0, A->X, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 1, A->Y, size); - ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, bCurveParam, size); - if (R2modN) - { - ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 1, R2modN, size); - } - - status = ltc_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 1, result->X, size); - ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 2, result->Y, size); - - if (infinity) - { - *infinity = (bool)(base->STA & kLTC_StatusPublicKeyOpZero); - } - } - - ltc_clear_all(base, true); - return status; -} - -#endif /* FSL_FEATURE_LTC_HAS_PKHA */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_ltc.h b/third_party/nxp/MKW41Z4/drivers/fsl_ltc.h deleted file mode 100644 index 119ef181b..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_ltc.h +++ /dev/null @@ -1,1584 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LTC_H_ -#define _FSL_LTC_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup ltc - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief LTC driver version. Version 2.0.4. - * - * Current version: 2.0.4 - * - * Change log: - * - Version 2.0.1 - * - fixed warning during g++ compilation - * - * - Version 2.0.2 - * - fixed [KPSDK-10932][LTC][SHA] LTC_HASH() blocks indefinitely when message size exceeds 4080 bytes - * - * - Version 2.0.3 - * - fixed LTC_PKHA_CompareBigNum() in case an integer argument is an array of all zeroes - * - * - Version 2.0.4 - * - constant LTC_PKHA_CompareBigNum() processing time - */ -#define FSL_LTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ -/*! - * @addtogroup ltc_driver_aes - * @{ - */ -/*! AES block size in bytes */ -#define LTC_AES_BLOCK_SIZE 16 -/*! AES Input Vector size in bytes */ -#define LTC_AES_IV_SIZE 16 - -/*! @brief Type of AES key for ECB and CBC decrypt operations. */ -typedef enum _ltc_aes_key_t -{ - kLTC_EncryptKey = 0U, /*!< Input key is an encrypt key */ - kLTC_DecryptKey = 1U, /*!< Input key is a decrypt key */ -} ltc_aes_key_t; - -/*! - *@} - */ - -/******************************************************************************* - * DES Definitions - *******************************************************************************/ -/*! - * @addtogroup ltc_driver_des - * @{ - */ - -/*! @brief LTC DES key size - 64 bits. */ -#define LTC_DES_KEY_SIZE 8 - -/*! @brief LTC DES IV size - 8 bytes */ -#define LTC_DES_IV_SIZE 8 - -/*! - *@} - */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup ltc_driver_hash - * @{ - */ -/*! Supported cryptographic block cipher functions for HASH creation */ -typedef enum _ltc_hash_algo_t -{ - kLTC_XcbcMac = 0, /*!< XCBC-MAC (AES engine) */ - kLTC_Cmac, /*!< CMAC (AES engine) */ -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA - kLTC_Sha1, /*!< SHA_1 (MDHA engine) */ - kLTC_Sha224, /*!< SHA_224 (MDHA engine) */ - kLTC_Sha256, /*!< SHA_256 (MDHA engine) */ -#endif /* FSL_FEATURE_LTC_HAS_SHA */ -} ltc_hash_algo_t; - -/*! @brief LTC HASH Context size. */ -#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA -#define LTC_HASH_CTX_SIZE 41 -#else -#define LTC_HASH_CTX_SIZE 29 -#endif /* FSL_FEATURE_LTC_HAS_SHA */ - -/*! @brief Storage type used to save hash context. */ -typedef uint32_t ltc_hash_ctx_t[LTC_HASH_CTX_SIZE]; - -/*! - *@} - */ -/******************************************************************************* - * PKHA Definitions - ******************************************************************************/ -/*! - * @addtogroup ltc_driver_pkha - * @{ - */ -/*! PKHA ECC point structure */ -typedef struct _ltc_pkha_ecc_point_t -{ - uint8_t *X; /*!< X coordinate (affine) */ - uint8_t *Y; /*!< Y coordinate (affine) */ -} ltc_pkha_ecc_point_t; - -/*! @brief Use of timing equalized version of a PKHA function. */ -typedef enum _ltc_pkha_timing_t -{ - kLTC_PKHA_NoTimingEqualized = 0U, /*!< Normal version of a PKHA operation */ - kLTC_PKHA_TimingEqualized = 1U /*!< Timing-equalized version of a PKHA operation */ -} ltc_pkha_timing_t; - -/*! @brief Integer vs binary polynomial arithmetic selection. */ -typedef enum _ltc_pkha_f2m_t -{ - kLTC_PKHA_IntegerArith = 0U, /*!< Use integer arithmetic */ - kLTC_PKHA_F2mArith = 1U /*!< Use binary polynomial arithmetic */ -} ltc_pkha_f2m_t; - -/*! @brief Montgomery or normal PKHA input format. */ -typedef enum _ltc_pkha_montgomery_form_t -{ - kLTC_PKHA_NormalValue = 0U, /*!< PKHA number is normal integer */ - kLTC_PKHA_MontgomeryFormat = 1U /*!< PKHA number is in montgomery format */ -} ltc_pkha_montgomery_form_t; - -/*! - *@} - */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup ltc - * @{ - */ - -/*! - * @brief Initializes the LTC driver. - * This function initializes the LTC driver. - * @param base LTC peripheral base address - */ -void LTC_Init(LTC_Type *base); - -/*! - * @brief Deinitializes the LTC driver. - * This function deinitializes the LTC driver. - * @param base LTC peripheral base address - */ -void LTC_Deinit(LTC_Type *base); - -#if defined(FSL_FEATURE_LTC_HAS_DPAMS) && FSL_FEATURE_LTC_HAS_DPAMS -/*! - * @brief Sets the DPA Mask Seed register. - * - * The DPA Mask Seed register reseeds the mask that provides resistance against DPA (differential power analysis) - * attacks on AES or DES keys. - * - * Differential Power Analysis Mask (DPA) resistance uses a randomly changing mask that introduces - * "noise" into the power consumed by the AES or DES. This reduces the signal-to-noise ratio that differential - * power analysis attacks use to "guess" bits of the key. This randomly changing mask should be - * seeded at POR, and continues to provide DPA resistance from that point on. However, to provide even more - * DPA protection it is recommended that the DPA mask be reseeded after every 50,000 blocks have - * been processed. At that time, software can opt to write a new seed (preferably obtained from an RNG) - * into the DPA Mask Seed register (DPAMS), or software can opt to provide the new seed earlier or - * later, or not at all. DPA resistance continues even if the DPA mask is never reseeded. - * - * @param base LTC peripheral base address - * @param mask The DPA mask seed. - */ -void LTC_SetDpaMaskSeed(LTC_Type *base, uint32_t mask); -#endif /* FSL_FEATURE_LTC_HAS_DPAMS */ - -/*! - *@} - */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup ltc_driver_aes - * @{ - */ - -/*! - * @brief Transforms an AES encrypt key (forward AES) into the decrypt key (inverse AES). - * - * Transforms the AES encrypt key (forward AES) into the decrypt key (inverse AES). - * The key derived by this function can be used as a direct load decrypt key - * for AES ECB and CBC decryption operations (keyType argument). - * - * @param base LTC peripheral base address - * @param encryptKey Input key for decrypt key transformation - * @param[out] decryptKey Output key, the decrypt form of the AES key. - * @param keySize Size of the input key and output key in bytes. Must be 16, 24, or 32. - * @return Status from key generation operation - */ -status_t LTC_AES_GenerateDecryptKey(LTC_Type *base, const uint8_t *encryptKey, uint8_t *decryptKey, uint32_t keySize); - -/*! - * @brief Encrypts AES using the ECB block mode. - * - * Encrypts AES using the ECB block mode. - * - * @param base LTC peripheral base address - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @return Status from encrypt operation - */ -status_t LTC_AES_EncryptEcb( - LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t *key, uint32_t keySize); - -/*! - * @brief Decrypts AES using ECB block mode. - * - * Decrypts AES using ECB block mode. - * - * @param base LTC peripheral base address - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param key Input key. - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param keyType Input type of the key (allows to directly load decrypt key for AES ECB decrypt operation.) - * @return Status from decrypt operation - */ -status_t LTC_AES_DecryptEcb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * @param base LTC peripheral base address - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @return Status from encrypt operation - */ -status_t LTC_AES_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * @param base LTC peripheral base address - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @param key Input key to use for decryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param keyType Input type of the key (allows to directly load decrypt key for AES CBC decrypt operation.) - * @return Status from decrypt operation - */ -status_t LTC_AES_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType); - -/*! - * @brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base LTC peripheral base address - * @param input Input data for CTR block mode - * @param[out] output Output data for CTR block mode - * @param size Size of input and output data in bytes - * @param[in,out] counter Input counter (updates on return) - * @param key Input key to use for forward AES cipher - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param[out] counterlast Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are - * not used. - * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * @return Status from encrypt operation - */ -status_t LTC_AES_CryptCtr(LTC_Type *base, - const uint8_t *input, - uint8_t *output, - uint32_t size, - uint8_t counter[LTC_AES_BLOCK_SIZE], - const uint8_t *key, - uint32_t keySize, - uint8_t counterlast[LTC_AES_BLOCK_SIZE], - uint32_t *szLeft); - -/*! AES CTR decrypt is mapped to the AES CTR generic operation */ -#define LTC_AES_DecryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft) \ - LTC_AES_CryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft) - -/*! AES CTR encrypt is mapped to the AES CTR generic operation */ -#define LTC_AES_EncryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft) \ - LTC_AES_CryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft) - -#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM -/*! - * @brief Encrypts AES and tags using GCM block mode. - * - * Encrypts AES and optionally tags using GCM block mode. If plaintext is NULL, only the GHASH is calculated and output - * in the 'tag' field. - * - * @param base LTC peripheral base address - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text. - * @param size Size of input and output data in bytes - * @param iv Input initial vector - * @param ivSize Size of the IV - * @param aad Input additional authentication data - * @param aadSize Input size in bytes of AAD - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param[out] tag Output hash tag. Set to NULL to skip tag processing. - * @param tagSize Input size of the tag to generate, in bytes. Must be 4,8,12,13,14,15 or 16. - * @return Status from encrypt operation - */ -status_t LTC_AES_EncryptTagGcm(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *tag, - uint32_t tagSize); - -/*! - * @brief Decrypts AES and authenticates using GCM block mode. - * - * Decrypts AES and optionally authenticates using GCM block mode. If ciphertext is NULL, only the GHASH is calculated - * and compared with the received GHASH in 'tag' field. - * - * @param base LTC peripheral base address - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text. - * @param size Size of input and output data in bytes - * @param iv Input initial vector - * @param ivSize Size of the IV - * @param aad Input additional authentication data - * @param aadSize Input size in bytes of AAD - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param tag Input hash tag to compare. Set to NULL to skip tag processing. - * @param tagSize Input size of the tag, in bytes. Must be 4, 8, 12, 13, 14, 15, or 16. - * @return Status from decrypt operation - */ -status_t LTC_AES_DecryptTagGcm(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - const uint8_t *tag, - uint32_t tagSize); -#endif /* FSL_FEATURE_LTC_HAS_GCM */ - -/*! - * @brief Encrypts AES and tags using CCM block mode. - * - * Encrypts AES and optionally tags using CCM block mode. - * - * @param base LTC peripheral base address - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text. - * @param size Size of input and output data in bytes. Zero means authentication only. - * @param iv Nonce - * @param ivSize Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13. - * @param aad Input additional authentication data. Can be NULL if aadSize is zero. - * @param aadSize Input size in bytes of AAD. Zero means data mode only (authentication skipped). - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param[out] tag Generated output tag. Set to NULL to skip tag processing. - * @param tagSize Input size of the tag to generate, in bytes. Must be 4, 6, 8, 10, 12, 14, or 16. - * @return Status from encrypt operation - */ -status_t LTC_AES_EncryptTagCcm(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *tag, - uint32_t tagSize); - -/*! - * @brief Decrypts AES and authenticates using CCM block mode. - * - * Decrypts AES and optionally authenticates using CCM block mode. - * - * @param base LTC peripheral base address - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text. - * @param size Size of input and output data in bytes. Zero means authentication only. - * @param iv Nonce - * @param ivSize Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13. - * @param aad Input additional authentication data. Can be NULL if aadSize is zero. - * @param aadSize Input size in bytes of AAD. Zero means data mode only (authentication skipped). - * @param key Input key to use for decryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param tag Received tag. Set to NULL to skip tag processing. - * @param tagSize Input size of the received tag to compare with the computed tag, in bytes. Must be 4, 6, 8, 10, 12, - * 14, or 16. - * @return Status from decrypt operation - */ -status_t LTC_AES_DecryptTagCcm(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *iv, - uint32_t ivSize, - const uint8_t *aad, - uint32_t aadSize, - const uint8_t *key, - uint32_t keySize, - const uint8_t *tag, - uint32_t tagSize); - -/*! - *@} - */ - -/******************************************************************************* - * DES API - ******************************************************************************/ -/*! - * @addtogroup ltc_driver_des - * @{ - */ -/*! - * @brief Encrypts DES using ECB block mode. - * - * Encrypts DES using ECB block mode. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key Input key to use for encryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptEcb( - LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using ECB block mode. - * - * Decrypts DES using ECB block mode. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptEcb( - LTC_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts DES using CBC block mode. - * - * Encrypts DES using CBC block mode. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Ouput ciphertext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key Input key to use for encryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using CBC block mode. - * - * Decrypts DES using CBC block mode. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts DES using CFB block mode. - * - * Encrypts DES using CFB block mode. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param size Size of input data in bytes - * @param iv Input initial block. - * @param key Input key to use for encryption - * @param[out] ciphertext Output ciphertext - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptCfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using CFB block mode. - * - * Decrypts DES using CFB block mode. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial block. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptCfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts DES using OFB block mode. - * - * Encrypts DES using OFB block mode. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key Input key to use for encryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptOfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using OFB block mode. - * - * Decrypts DES using OFB block mode. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptOfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using ECB block mode with two keys. - * - * Encrypts triple DES using ECB block mode with two keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptEcb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using ECB block mode with two keys. - * - * Decrypts triple DES using ECB block mode with two keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptEcb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CBC block mode with two keys. - * - * Encrypts triple DES using CBC block mode with two keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CBC block mode with two keys. - * - * Decrypts triple DES using CBC block mode with two keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CFB block mode with two keys. - * - * Encrypts triple DES using CFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptCfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CFB block mode with two keys. - * - * Decrypts triple DES using CFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptCfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using OFB block mode with two keys. - * - * Encrypts triple DES using OFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptOfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using OFB block mode with two keys. - * - * Decrypts triple DES using OFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptOfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using ECB block mode with three keys. - * - * Encrypts triple DES using ECB block mode with three keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptEcb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using ECB block mode with three keys. - * - * Decrypts triple DES using ECB block mode with three keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptEcb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CBC block mode with three keys. - * - * Encrypts triple DES using CBC block mode with three keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptCbc(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CBC block mode with three keys. - * - * Decrypts triple DES using CBC block mode with three keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptCbc(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CFB block mode with three keys. - * - * Encrypts triple DES using CFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and ouput data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptCfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CFB block mode with three keys. - * - * Decrypts triple DES using CFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptCfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using OFB block mode with three keys. - * - * Encrypts triple DES using OFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptOfb(LTC_Type *base, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using OFB block mode with three keys. - * - * Decrypts triple DES using OFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptOfb(LTC_Type *base, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - *@} - */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup ltc_driver_hash - * @{ - */ -/*! - * @brief Initialize HASH context - * - * This function initialize the HASH. - * Key shall be supplied if the underlaying algoritm is AES XCBC-MAC or CMAC. - * Key shall be NULL if the underlaying algoritm is SHA. - * - * For XCBC-MAC, the key length must be 16. For CMAC, the key length can be - * the AES key lengths supported by AES engine. For MDHA the key length argument - * is ignored. - * - * @param base LTC peripheral base address - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @param key Input key (NULL if underlaying algorithm is SHA) - * @param keySize Size of input key in bytes - * @return Status of initialization - */ -status_t LTC_HASH_Init(LTC_Type *base, ltc_hash_ctx_t *ctx, ltc_hash_algo_t algo, const uint8_t *key, uint32_t keySize); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. - * - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t LTC_HASH_Update(ltc_hash_ctx_t *ctx, const uint8_t *input, uint32_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash and erases the context. - * - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the hash finish operation - */ -status_t LTC_HASH_Finish(ltc_hash_ctx_t *ctx, uint8_t *output, uint32_t *outputSize); - -/*! - * @brief Create HASH on given data - * - * Perform the full keyed HASH in one function call. - * - * @param base LTC peripheral base address - * @param algo Block cipher algorithm to use for CMAC creation - * @param input Input data - * @param inputSize Size of input data in bytes - * @param key Input key - * @param keySize Size of input key in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t LTC_HASH(LTC_Type *base, - ltc_hash_algo_t algo, - const uint8_t *input, - uint32_t inputSize, - const uint8_t *key, - uint32_t keySize, - uint8_t *output, - uint32_t *outputSize); -/*! - *@} - */ - -/******************************************************************************* - * PKHA API - ******************************************************************************/ -/*! - * @addtogroup ltc_driver_pkha - * @{ - */ - -/*! - * @brief Compare two PKHA big numbers. - * - * Compare two PKHA big numbers. Return 1 for a > b, -1 for a < b and 0 if they are same. - * PKHA big number is lsbyte first. Thus the comparison starts at msbyte which is the last member of tested arrays. - * - * @param a First integer represented as an array of bytes, lsbyte first. - * @param sizeA Size in bytes of the first integer. - * @param b Second integer represented as an array of bytes, lsbyte first. - * @param sizeB Size in bytes of the second integer. - * @return 1 if a > b. - * @return -1 if a < b. - * @return 0 if a = b. - */ -int LTC_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB); - -/*! - * @brief Converts from integer to Montgomery format. - * - * This function computes R2 mod N and optionally converts A or B into Montgomery format of A or B. - * - * @param base LTC peripheral base address - * @param N modulus - * @param sizeN size of N in bytes - * @param[in,out] A The first input in non-Montgomery format. Output Montgomery format of the first input. - * @param[in,out] sizeA pointer to size variable. On input it holds size of input A in bytes. On output it holds size of - * Montgomery format of A in bytes. - * @param[in,out] B Second input in non-Montgomery format. Output Montgomery format of the second input. - * @param[in,out] sizeB pointer to size variable. On input it holds size of input B in bytes. On output it holds size of - * Montgomery format of B in bytes. - * @param[out] R2 Output Montgomery factor R2 mod N. - * @param[out] sizeR2 pointer to size variable. On output it holds size of Montgomery factor R2 mod N in bytes. - * @param equalTime Run the function time equalized or no timing equalization. - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t LTC_PKHA_NormalToMontgomery(LTC_Type *base, - const uint8_t *N, - uint16_t sizeN, - uint8_t *A, - uint16_t *sizeA, - uint8_t *B, - uint16_t *sizeB, - uint8_t *R2, - uint16_t *sizeR2, - ltc_pkha_timing_t equalTime, - ltc_pkha_f2m_t arithType); - -/*! - * @brief Converts from Montgomery format to int. - * - * This function converts Montgomery format of A or B into int A or B. - * - * @param base LTC peripheral base address - * @param N modulus. - * @param sizeN size of N modulus in bytes. - * @param[in,out] A Input first number in Montgomery format. Output is non-Montgomery format. - * @param[in,out] sizeA pointer to size variable. On input it holds size of the input A in bytes. On output it holds - * size of non-Montgomery A in bytes. - * @param[in,out] B Input first number in Montgomery format. Output is non-Montgomery format. - * @param[in,out] sizeB pointer to size variable. On input it holds size of the input B in bytes. On output it holds - * size of non-Montgomery B in bytes. - * @param equalTime Run the function time equalized or no timing equalization. - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t LTC_PKHA_MontgomeryToNormal(LTC_Type *base, - const uint8_t *N, - uint16_t sizeN, - uint8_t *A, - uint16_t *sizeA, - uint8_t *B, - uint16_t *sizeB, - ltc_pkha_timing_t equalTime, - ltc_pkha_f2m_t arithType); - -/*! - * @brief Performs modular addition - (A + B) mod N. - * - * This function performs modular addition of (A + B) mod N, with either - * integer or binary polynomial (F2m) inputs. In the F2m form, this function is - * equivalent to a bitwise XOR and it is functionally the same as subtraction. - * - * @param base LTC peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus. For F2m operation this can be NULL, as N is ignored during F2m polynomial addition. - * @param sizeN Size of N in bytes. This must be given for both integer and F2m polynomial additions. - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t LTC_PKHA_ModAdd(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType); - -/*! - * @brief Performs modular subtraction - (A - B) mod N. - * - * This function performs modular subtraction of (A - B) mod N with - * integer inputs. - * - * @param base LTC peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @return Operation status. - */ -status_t LTC_PKHA_ModSub1(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize); - -/*! - * @brief Performs modular subtraction - (B - A) mod N. - * - * This function performs modular subtraction of (B - A) mod N, - * with integer inputs. - * - * @param base LTC peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @return Operation status. - */ -status_t LTC_PKHA_ModSub2(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize); - -/*! - * @brief Performs modular multiplication - (A x B) mod N. - * - * This function performs modular multiplication with either integer or - * binary polynomial (F2m) inputs. It can optionally specify whether inputs - * and/or outputs will be in Montgomery form or not. - * - * @param base LTC peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus. - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param montIn Format of inputs - * @param montOut Format of output - * @param equalTime Run the function time equalized or no timing equalization. This argument is ignored for F2m modular - * multiplication. - * @return Operation status. - */ -status_t LTC_PKHA_ModMul(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType, - ltc_pkha_montgomery_form_t montIn, - ltc_pkha_montgomery_form_t montOut, - ltc_pkha_timing_t equalTime); - -/*! - * @brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation with either integer or - * binary polynomial (F2m) inputs. - * - * @param base LTC peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param E exponent - * @param sizeE Size of E in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param montIn Format of A input (normal or Montgomery) - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param equalTime Run the function time equalized or no timing equalization. - * @return Operation status. - */ -status_t LTC_PKHA_ModExp(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - const uint8_t *E, - uint16_t sizeE, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType, - ltc_pkha_montgomery_form_t montIn, - ltc_pkha_timing_t equalTime); - -/*! - * @brief Performs modular reduction - (A) mod N. - * - * This function performs modular reduction with either integer or - * binary polynomial (F2m) inputs. - * - * @param base LTC peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t LTC_PKHA_ModRed(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType); - -/*! - * @brief Performs modular inversion - (A^-1) mod N. - * - * This function performs modular inversion with either integer or - * binary polynomial (F2m) inputs. - * - * @param base LTC peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t LTC_PKHA_ModInv(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType); - -/*! - * @brief Computes integer Montgomery factor R^2 mod N. - * - * This function computes a constant to assist in converting operands - * into the Montgomery residue system representation. - * - * @param base LTC peripheral base address - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t LTC_PKHA_ModR2( - LTC_Type *base, const uint8_t *N, uint16_t sizeN, uint8_t *result, uint16_t *resultSize, ltc_pkha_f2m_t arithType); - -/*! - * @brief Calculates the greatest common divisor - GCD (A, N). - * - * This function calculates the greatest common divisor of two inputs with - * either integer or binary polynomial (F2m) inputs. - * - * @param base LTC peripheral base address - * @param A first value (must be smaller than or equal to N) - * @param sizeA Size of A in bytes - * @param N second value (must be non-zero) - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t LTC_PKHA_GCD(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *N, - uint16_t sizeN, - uint8_t *result, - uint16_t *resultSize, - ltc_pkha_f2m_t arithType); - -/*! - * @brief Executes Miller-Rabin primality test. - * - * This function calculates whether or not a candidate prime number is likely - * to be a prime. - * - * @param base LTC peripheral base address - * @param A initial random seed - * @param sizeA Size of A in bytes - * @param B number of trial runs - * @param sizeB Size of B in bytes - * @param N candidate prime integer - * @param sizeN Size of N in bytes - * @param[out] res True if the value is likely prime or false otherwise - * @return Operation status. - */ -status_t LTC_PKHA_PrimalityTest(LTC_Type *base, - const uint8_t *A, - uint16_t sizeA, - const uint8_t *B, - uint16_t sizeB, - const uint8_t *N, - uint16_t sizeN, - bool *res); - -/*! - * @brief Adds elliptic curve points - A + B. - * - * This function performs ECC point addition over a prime field (Fp) or binary field (F2m) using - * affine coordinates. - * - * @param base LTC peripheral base address - * @param A Left-hand point - * @param B Right-hand point - * @param N Prime modulus of the field - * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from - * LTC_PKHA_ModR2() function). - * @param aCurveParam A parameter from curve equation - * @param bCurveParam B parameter from curve equation (constant) - * @param size Size in bytes of curve points and parameters - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param[out] result Result point - * @return Operation status. - */ -status_t LTC_PKHA_ECC_PointAdd(LTC_Type *base, - const ltc_pkha_ecc_point_t *A, - const ltc_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - uint8_t size, - ltc_pkha_f2m_t arithType, - ltc_pkha_ecc_point_t *result); - -/*! - * @brief Doubles elliptic curve points - B + B. - * - * This function performs ECC point doubling over a prime field (Fp) or binary field (F2m) using - * affine coordinates. - * - * @param base LTC peripheral base address - * @param B Point to double - * @param N Prime modulus of the field - * @param aCurveParam A parameter from curve equation - * @param bCurveParam B parameter from curve equation (constant) - * @param size Size in bytes of curve points and parameters - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param[out] result Result point - * @return Operation status. - */ -status_t LTC_PKHA_ECC_PointDouble(LTC_Type *base, - const ltc_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - uint8_t size, - ltc_pkha_f2m_t arithType, - ltc_pkha_ecc_point_t *result); - -/*! - * @brief Multiplies an elliptic curve point by a scalar - E x (A0, A1). - * - * This function performs ECC point multiplication to multiply an ECC point by - * a scalar integer multiplier over a prime field (Fp) or a binary field (F2m). - * - * @param base LTC peripheral base address - * @param A Point as multiplicand - * @param E Scalar multiple - * @param sizeE The size of E, in bytes - * @param N Modulus, a prime number for the Fp field or Irreducible polynomial for F2m field. - * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from - * LTC_PKHA_ModR2() function). - * @param aCurveParam A parameter from curve equation - * @param bCurveParam B parameter from curve equation (C parameter for operation over F2m). - * @param size Size in bytes of curve points and parameters - * @param equalTime Run the function time equalized or no timing equalization. - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param[out] result Result point - * @param[out] infinity Output true if the result is point of infinity, and false otherwise. Writing of this output will - * be ignored if the argument is NULL. - * @return Operation status. - */ -status_t LTC_PKHA_ECC_PointMul(LTC_Type *base, - const ltc_pkha_ecc_point_t *A, - const uint8_t *E, - uint8_t sizeE, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - uint8_t size, - ltc_pkha_timing_t equalTime, - ltc_pkha_f2m_t arithType, - ltc_pkha_ecc_point_t *result, - bool *infinity); - -/*! - *@} - */ - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_LTC_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_ltc_edma.c b/third_party/nxp/MKW41Z4/drivers/fsl_ltc_edma.c deleted file mode 100644 index 6c343dd50..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_ltc_edma.c +++ /dev/null @@ -1,1247 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_ltc_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*modeReg = base->MD; - retval = kStatus_Success; - - if ((!handle->inData) || (!handle->outData)) - { - handle->state = LTC_SM_STATE_FINISH; /* END */ - retval = kStatus_InvalidArgument; - } - - while (exit_sm == false) - { - switch (handle->state) - { - case LTC_SM_STATE_START: - if (handle->size) - { - uint32_t sz; - - if (handle->size <= LTC_FIFO_SZ_MAX_DOWN_ALGN) - { - sz = handle->size; - } - else - { - sz = LTC_FIFO_SZ_MAX_DOWN_ALGN; - } - - /* retval = ltc_symmetric_process_data_EDMA(base, handle->inData, sz, handle->outData); */ - { - uint32_t lastSize; - uint32_t inSize = sz; - - /* Write the data size. */ - base->DS = inSize; - - /* Split the inSize into full 16-byte chunks and last incomplete block due to LTC AES OFIFO - * errata */ - if (inSize <= 16u) - { - lastSize = inSize; - inSize = 0; - } - else - { - /* Process all 16-byte data chunks. */ - lastSize = inSize % 16u; - if (lastSize == 0) - { - lastSize = 16; - inSize -= 16; - } - else - { - inSize -= - lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in - lastSize */ - } - } - - if (inSize) - { - handle->size -= inSize; - ltc_symmetric_process_EDMA(base, inSize, &handle->inData, &handle->outData); - exit_sm = true; - } - else if (lastSize) - { - ltc_symmetric_process(base, lastSize, &handle->inData, &handle->outData); - retval = ltc_wait(base); - handle->size -= lastSize; - } - else - { - } - } - } - else - { - handle->state = LTC_SM_STATE_FINISH; - } - break; - case LTC_SM_STATE_FINISH: - default: - base->MD = handle->modeReg; - - ltc_clear_all(base, false); - - if (handle->callback) - { - handle->callback(base, handle, retval, handle->userData); - } - exit_sm = true; - break; - } - } - - return retval; -} - -/*! - * @brief Splits the LTC job into sessions. Used for CBC, CTR, CFB, OFB cipher block modes. - * - * @param base LTC peripheral base address - * @param inData Input data to process. - * @param inSize Input size of the input buffer. - * @param outData Output data buffer. - */ -static status_t ltc_process_message_in_sessions_ctr_EDMA(LTC_Type *base, ltc_edma_handle_t *handle) -{ - status_t retval; - bool exit_sm = false; - - handle->modeReg = base->MD; - retval = kStatus_Success; - - if ((!handle->inData) || (!handle->outData)) - { - handle->state = LTC_SM_STATE_FINISH; - retval = kStatus_InvalidArgument; - } - - while (exit_sm == false) - { - switch (handle->state) - { - case LTC_SM_STATE_START: - if (handle->size) - { - uint32_t sz; - - if (handle->size <= LTC_FIFO_SZ_MAX_DOWN_ALGN) - { - sz = handle->size; - } - else - { - sz = LTC_FIFO_SZ_MAX_DOWN_ALGN; - } - - /* retval = ltc_symmetric_process_data_EDMA(base, handle->inData, sz, handle->outData); */ - { - uint32_t lastSize; - uint32_t inSize = sz; - - /* Write the data size. */ - base->DS = inSize; - - /* Split the inSize into full 16-byte chunks and last incomplete block due to LTC AES OFIFO - * errata */ - if (inSize <= 16u) - { - lastSize = inSize; - inSize = 0; - } - else - { - /* Process all 16-byte data chunks. */ - lastSize = inSize % 16u; - if (lastSize == 0) - { - lastSize = 16; - inSize -= 16; - } - else - { - inSize -= - lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in - lastSize */ - } - } - - if (inSize) - { - handle->size -= inSize; - ltc_symmetric_process_EDMA(base, inSize, &handle->inData, &handle->outData); - exit_sm = true; - } - else if (lastSize) - { - ltc_symmetric_process(base, lastSize, &handle->inData, &handle->outData); - retval = ltc_wait(base); - handle->size -= lastSize; - } - else - { - } - } - } - else - { - handle->state = LTC_SM_STATE_FINISH; - } - break; - case LTC_SM_STATE_FINISH: - default: - base->MD = handle->modeReg; - - /* CTR final phase.*/ - if (kStatus_Success == retval) - { - const uint8_t *input = handle->inData; - uint8_t *output = handle->outData; - - if ((handle->counterlast != NULL) && (handle->lastSize)) - { - uint8_t zeroes[16] = {0}; - ltc_mode_t modeReg; - - modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeCTR | (uint32_t)kLTC_ModeEncrypt; - /* Write the mode register to the hardware. */ - base->MD = modeReg | (uint32_t)kLTC_ModeFinalize; - - /* context is re-used (CTRi) */ - - /* Process data and return status. */ - retval = ltc_symmetric_process_data(base, input, handle->lastSize, output); - if (kStatus_Success == retval) - { - if (handle->szLeft) - { - *handle->szLeft = 16U - handle->lastSize; - } - - /* Initialize algorithm state. */ - base->MD = modeReg | (uint32_t)kLTC_ModeUpdate; - - /* context is re-used (CTRi) */ - - /* Process data and return status. */ - retval = ltc_symmetric_process_data(base, zeroes, 16U, handle->counterlast); - } - } - if (kStatus_Success == retval) - { - ltc_get_context(base, &handle->counter[0], 16U, 4U); - - ltc_clear_all(base, false); - } - } - - if (handle->callback) - { - handle->callback(base, handle, retval, handle->userData); - } - - exit_sm = true; - break; - } - } - - return retval; -} - -/******************************************************************************* - * AES Code public - ******************************************************************************/ - -status_t LTC_AES_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t *key, - uint32_t keySize) -{ - status_t retval; - - if ((ltc_check_key_size(keySize) == 0) || (size < 16u) || - (size % 16u)) /* ECB mode, size must be 16-byte multiple */ - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_InvalidArgument, handle->userData); - } - - return kStatus_InvalidArgument; - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeEncrypt); - - /* Process data and return status. */ - handle->inData = &plaintext[0]; - handle->outData = &ciphertext[0]; - handle->size = size; - handle->state = LTC_SM_STATE_START; - handle->state_machine = ltc_process_message_in_sessions_EDMA; - retval = handle->state_machine(base, handle); - return retval; -} - -status_t LTC_AES_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType) -{ - status_t status; - - if ((ltc_check_key_size(keySize) == 0) || (size < 16u) || - (size % 16u)) /* ECB mode, size must be 16-byte multiple */ - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_InvalidArgument, handle->userData); - } - - return kStatus_InvalidArgument; - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeDecrypt); - - /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */ - if (keyType == kLTC_DecryptKey) - { - base->MD |= (1U << kLTC_ModeRegBitShiftDK); - } - - /* Process data and return status. */ - handle->inData = &ciphertext[0]; - handle->outData = &plaintext[0]; - handle->size = size; - handle->state = LTC_SM_STATE_START; - handle->state_machine = ltc_process_message_in_sessions_EDMA; - status = handle->state_machine(base, handle); - - return status; -} - -status_t LTC_AES_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize) -{ - status_t retval; - - if ((ltc_check_key_size(keySize) == 0) || (size < 16u) || - (size % 16u)) /* CBC mode, size must be 16-byte multiple */ - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_InvalidArgument, handle->userData); - } - - return kStatus_InvalidArgument; - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeEncrypt); - - /* Write IV data to the context register. */ - ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0); - - /* Process data and return status. */ - handle->inData = &plaintext[0]; - handle->outData = &ciphertext[0]; - handle->size = size; - handle->state = LTC_SM_STATE_START; - handle->state_machine = ltc_process_message_in_sessions_EDMA; - retval = handle->state_machine(base, handle); - return retval; -} - -status_t LTC_AES_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType) -{ - status_t retval; - - if ((ltc_check_key_size(keySize) == 0) || (size < 16u) || - (size % 16u)) /* CBC mode, size must be 16-byte multiple */ - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_InvalidArgument, handle->userData); - } - - return kStatus_InvalidArgument; - } - - /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */ - if (keyType == kLTC_DecryptKey) - { - base->MD |= (1U << kLTC_ModeRegBitShiftDK); - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeDecrypt); - - /* Write IV data to the context register. */ - ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0); - - /* Process data and return status. */ - handle->inData = &ciphertext[0]; - handle->outData = &plaintext[0]; - handle->size = size; - handle->state = LTC_SM_STATE_START; - handle->state_machine = ltc_process_message_in_sessions_EDMA; - retval = handle->state_machine(base, handle); - return retval; -} - -status_t LTC_AES_CryptCtrEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *input, - uint8_t *output, - uint32_t size, - uint8_t counter[LTC_AES_BLOCK_SIZE], - const uint8_t *key, - uint32_t keySize, - uint8_t counterlast[LTC_AES_BLOCK_SIZE], - uint32_t *szLeft) -{ - status_t retval; - uint32_t lastSize; - - if (!ltc_check_key_size(keySize)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_InvalidArgument, handle->userData); - } - return kStatus_InvalidArgument; - } - - lastSize = 0U; - if (counterlast != NULL) - { - /* Split the size into full 16-byte chunks and last incomplete block due to LTC AES OFIFO errata */ - if (size <= 16U) - { - lastSize = size; - size = 0U; - } - else - { - /* Process all 16-byte data chunks. */ - lastSize = size % 16U; - if (lastSize == 0U) - { - lastSize = 16U; - size -= 16U; - } - else - { - size -= lastSize; /* size will be rounded down to 16 byte boundary. remaining bytes in lastSize */ - } - } - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCTR, kLTC_ModeEncrypt); - - /* Write initial counter data to the context register. - * NOTE the counter values start at 4-bytes offset into the context. */ - ltc_set_context(base, &counter[0], 16U, 4U); - - /* Process data and return status. */ - handle->inData = &input[0]; - handle->outData = &output[0]; - handle->size = size; - handle->state = LTC_SM_STATE_START; - handle->state_machine = ltc_process_message_in_sessions_ctr_EDMA; - - handle->counter = counter; - handle->key = key; - handle->keySize = keySize; - handle->counterlast = counterlast; - handle->szLeft = szLeft; - handle->lastSize = lastSize; - retval = handle->state_machine(base, handle); - - return retval; -} - -#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES -/******************************************************************************* - * DES / 3DES Code static - ******************************************************************************/ -static status_t ltc_des_process_EDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *input, - uint8_t *output, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE], - ltc_mode_symmetric_alg_t modeAs, - ltc_mode_encrypt_t modeEnc) -{ - status_t retval; - - /* all but OFB, size must be 8-byte multiple */ - if ((modeAs != kLTC_ModeOFB) && ((size < 8u) || (size % 8u))) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_InvalidArgument, handle->userData); - } - return kStatus_InvalidArgument; - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, &key[0], LTC_DES_KEY_SIZE, kLTC_AlgorithmDES, modeAs, modeEnc); - - if ((modeAs != kLTC_ModeECB)) - { - ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0); - } - - /* Process data and return status. */ - handle->inData = input; - handle->outData = output; - handle->size = size; - handle->state = LTC_SM_STATE_START; - handle->state_machine = ltc_process_message_in_sessions_EDMA; - retval = handle->state_machine(base, handle); - - return retval; -} - -static status_t ltc_3des_process_EDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *input, - uint8_t *output, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE], - ltc_mode_symmetric_alg_t modeAs, - ltc_mode_encrypt_t modeEnc) -{ - status_t retval; - uint8_t key[LTC_DES_KEY_SIZE * 3]; - uint8_t keySize = LTC_DES_KEY_SIZE * 2; - - retval = ltc_3des_check_input_args(modeAs, size, key1, key2); - if (kStatus_Success != retval) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_InvalidArgument, handle->userData); - } - return retval; - } - - ltc_memcpy(&key[0], &key1[0], LTC_DES_KEY_SIZE); - ltc_memcpy(&key[LTC_DES_KEY_SIZE], &key2[0], LTC_DES_KEY_SIZE); - if (key3) - { - ltc_memcpy(&key[LTC_DES_KEY_SIZE * 2], &key3[0], LTC_DES_KEY_SIZE); - keySize = sizeof(key); - } - - /* Initialize algorithm state. */ - ltc_symmetric_update(base, &key[0], keySize, kLTC_Algorithm3DES, modeAs, modeEnc); - - if ((modeAs != kLTC_ModeECB)) - { - ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0); - } - - /* Process data and return status. */ - handle->inData = input; - handle->outData = output; - handle->size = size; - handle->state = LTC_SM_STATE_START; - handle->state_machine = ltc_process_message_in_sessions_EDMA; - retval = handle->state_machine(base, handle); - - return retval; -} -/******************************************************************************* - * DES / 3DES Code public - ******************************************************************************/ -status_t LTC_DES_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, NULL, key, kLTC_ModeECB, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, NULL, key, kLTC_ModeECB, kLTC_ModeDecrypt); -} - -status_t LTC_DES_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key, kLTC_ModeCBC, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key, kLTC_ModeCBC, kLTC_ModeDecrypt); -} - -status_t LTC_DES_EncryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key, kLTC_ModeCFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key, kLTC_ModeCFB, kLTC_ModeDecrypt); -} - -status_t LTC_DES_EncryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key, kLTC_ModeOFB, kLTC_ModeEncrypt); -} - -status_t LTC_DES_DecryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]) -{ - return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key, kLTC_ModeOFB, kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, NULL, key1, key2, NULL, kLTC_ModeECB, - kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, NULL, key1, key2, key3, kLTC_ModeECB, - kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, NULL, key1, key2, NULL, kLTC_ModeECB, - kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, NULL, key1, key2, key3, kLTC_ModeECB, - kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCBC, - kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCBC, - kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCBC, - kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCBC, - kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCFB, - kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCFB, - kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCFB, - kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCFB, - kLTC_ModeDecrypt); -} - -status_t LTC_DES2_EncryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeOFB, - kLTC_ModeEncrypt); -} - -status_t LTC_DES3_EncryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeOFB, - kLTC_ModeEncrypt); -} - -status_t LTC_DES2_DecryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeOFB, - kLTC_ModeDecrypt); -} - -status_t LTC_DES3_DecryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]) -{ - return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeOFB, - kLTC_ModeDecrypt); -} -#endif /* FSL_FEATURE_LTC_HAS_DES */ - -/*********************** LTC EDMA tools ***************************************/ - -static uint32_t LTC_GetInstance(LTC_Type *base) -{ - uint32_t instance = 0; - uint32_t i; - - for (i = 0; i < FSL_FEATURE_SOC_LTC_COUNT; i++) - { - if (s_ltcBase[instance] == base) - { - instance = i; - break; - } - } - return instance; -} - -/*! - * @brief Enable or disable LTC Input FIFO DMA request. - * - * This function enables or disables DMA request and done signals for Input FIFO. - * - * @param base LTC peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LTC_EnableInputFifoDMA(LTC_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= LTC_CTL_IFE_MASK; - } - else - { - base->CTL &= ~LTC_CTL_IFE_MASK; - } -} - -/*! - * @brief Enable or disable LTC Output FIFO DMA request. - * - * This function enables or disables DMA request and done signals for Output FIFO. - * - * @param base LTC peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LTC_EnableOutputFifoDMA(LTC_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= LTC_CTL_OFE_MASK; - } - else - { - base->CTL &= ~LTC_CTL_OFE_MASK; - } -} - -static void LTC_InputFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - ltc_edma_private_handle_t *ltcPrivateHandle = (ltc_edma_private_handle_t *)param; - - /* Avoid the warning for unused variables. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Stop DMA channel. */ - EDMA_StopTransfer(ltcPrivateHandle->handle->inputFifoEdmaHandle); - - /* Disable Input Fifo DMA */ - LTC_EnableInputFifoDMA(ltcPrivateHandle->base, false); - } -} - -static void LTC_OutputFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - ltc_edma_private_handle_t *ltcPrivateHandle = (ltc_edma_private_handle_t *)param; - - /* Avoid the warning for unused variables. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Stop DMA channel. */ - EDMA_StopTransfer(ltcPrivateHandle->handle->outputFifoEdmaHandle); - - /* Disable Output Fifo DMA */ - LTC_EnableOutputFifoDMA(ltcPrivateHandle->base, false); - - if (ltcPrivateHandle->handle->state_machine) - { - ltcPrivateHandle->handle->state_machine(ltcPrivateHandle->base, ltcPrivateHandle->handle); - } - } -} - -/* @brief Copy data to Input FIFO and reading from Ouput FIFO using eDMA. */ -static void ltc_symmetric_process_EDMA(LTC_Type *base, uint32_t inSize, const uint8_t **inData, uint8_t **outData) -{ - const uint8_t *in = *inData; - uint8_t *out = *outData; - uint32_t instance = LTC_GetInstance(base); - uint32_t entry_number = inSize / sizeof(uint32_t); - const uint8_t *inputBuffer = *inData; - uint8_t *outputBuffer = *outData; - edma_transfer_config_t config; - - if (entry_number) - { - /* =========== Init Input FIFO DMA ======================*/ - memset(&config, 0, sizeof(config)); - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&config, (void *)inputBuffer, 1, (void *)(&((base)->IFIFO)), 4U, 4U, entry_number * 4, - kEDMA_MemoryToPeripheral); - /* Submit transfer. */ - EDMA_SubmitTransfer(s_edmaPrivateHandle[instance].handle->inputFifoEdmaHandle, &config); - - /* Set request size.*/ - base->CTL &= ~LTC_CTL_IFR_MASK; /* 1 entry */ - /* Enable Input Fifo DMA */ - LTC_EnableInputFifoDMA(base, true); - - /* Start the DMA channel */ - EDMA_StartTransfer(s_edmaPrivateHandle[instance].handle->inputFifoEdmaHandle); - - /* =========== Init Output FIFO DMA ======================*/ - memset(&config, 0, sizeof(config)); - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&config, (void *)(&((base)->OFIFO)), 4U, (void *)outputBuffer, 1U, 4U, entry_number * 4, - kEDMA_PeripheralToMemory); - /* Submit transfer. */ - EDMA_SubmitTransfer(s_edmaPrivateHandle[instance].handle->outputFifoEdmaHandle, &config); - - /* Set request size.*/ - base->CTL &= ~LTC_CTL_OFR_MASK; /* 1 entry */ - - /* Enable Output Fifo DMA */ - LTC_EnableOutputFifoDMA(base, true); - - /* Start the DMA channel */ - EDMA_StartTransfer(s_edmaPrivateHandle[instance].handle->outputFifoEdmaHandle); - - { /* Dummy read of LTC register. Do not delete.*/ - volatile uint32_t status_reg; - - status_reg = (base)->STA; - - (void)status_reg; - } - - out += entry_number * sizeof(uint32_t); - in += entry_number * sizeof(uint32_t); - - *inData = in; - *outData = out; - } -} - -void LTC_CreateHandleEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - ltc_edma_callback_t callback, - void *userData, - edma_handle_t *inputFifoEdmaHandle, - edma_handle_t *outputFifoEdmaHandle) -{ - assert(handle); - assert(inputFifoEdmaHandle); - assert(outputFifoEdmaHandle); - - uint32_t instance = LTC_GetInstance(base); - - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; - - memset(handle, 0, sizeof(*handle)); - - handle->inputFifoEdmaHandle = inputFifoEdmaHandle; - handle->outputFifoEdmaHandle = outputFifoEdmaHandle; - - handle->callback = callback; - handle->userData = userData; - - /* Register DMA callback functions */ - EDMA_SetCallback(handle->inputFifoEdmaHandle, LTC_InputFifoEDMACallback, &s_edmaPrivateHandle[instance]); - EDMA_SetCallback(handle->outputFifoEdmaHandle, LTC_OutputFifoEDMACallback, &s_edmaPrivateHandle[instance]); - - /* Set request size. DMA request size is 1 entry.*/ - base->CTL &= ~LTC_CTL_IFR_MASK; - base->CTL &= ~LTC_CTL_OFR_MASK; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_ltc_edma.h b/third_party/nxp/MKW41Z4/drivers/fsl_ltc_edma.h deleted file mode 100644 index 593306cc4..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_ltc_edma.h +++ /dev/null @@ -1,850 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LTC_EDMA_H_ -#define _FSL_LTC_EDMA_H_ - -#include "fsl_common.h" - -#include "fsl_ltc.h" -#include "fsl_dmamux.h" -#include "fsl_edma.h" - -/*! - * @addtogroup ltc_edma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* @brief The LTC eDMA handle type. */ -typedef struct _ltc_edma_handle ltc_edma_handle_t; - -/*! @brief LTC eDMA callback function. */ -typedef void (*ltc_edma_callback_t)(LTC_Type *base, ltc_edma_handle_t *handle, status_t status, void *userData); - -/*! @brief LTC eDMA state machine function. It is defined only for private usage inside LTC eDMA driver. */ -typedef status_t (*ltc_edma_state_machine_t)(LTC_Type *base, ltc_edma_handle_t *handle); - -/*! -* @brief LTC eDMA handle. It is defined only for private usage inside LTC eDMA driver. -*/ -struct _ltc_edma_handle -{ - ltc_edma_callback_t callback; /*!< Callback function. */ - void *userData; /*!< LTC callback function parameter.*/ - - edma_handle_t *inputFifoEdmaHandle; /*!< The eDMA TX channel used. */ - edma_handle_t *outputFifoEdmaHandle; /*!< The eDMA RX channel used. */ - - ltc_edma_state_machine_t state_machine; /*!< State machine. */ - uint32_t state; /*!< Internal state. */ - const uint8_t *inData; /*!< Input data. */ - uint8_t *outData; /*!< Output data. */ - uint32_t size; /*!< Size of input and output data in bytes.*/ - uint32_t modeReg; /*!< LTC mode register.*/ - /* Used by AES CTR*/ - uint8_t *counter; /*!< Input counter (updates on return)*/ - const uint8_t *key; /*!< Input key to use for forward AES cipher*/ - uint32_t keySize; /*!< Size of the input key, in bytes. Must be 16, 24, or 32.*/ - uint8_t - *counterlast; /*!< Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are - not used.*/ - uint32_t *szLeft; /*!< Output number of bytes in left unused in counterlast block. NULL can be passed if chained - calls are not used.*/ - uint32_t lastSize; /*!< Last size.*/ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Init the LTC eDMA handle which is used in transcational functions - * @param base LTC module base address - * @param handle Pointer to ltc_edma_handle_t structure - * @param callback Callback function, NULL means no callback. - * @param userData Callback function parameter. - * @param inputFifoEdmaHandle User requested eDMA handle for Input FIFO eDMA. - * @param outputFifoEdmaHandle User requested eDMA handle for Output FIFO eDMA. - */ -void LTC_CreateHandleEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - ltc_edma_callback_t callback, - void *userData, - edma_handle_t *inputFifoEdmaHandle, - edma_handle_t *outputFifoEdmaHandle); - -/*! @}*/ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup ltc_edma_driver_aes - * @{ - */ - -/*! - * @brief Encrypts AES using the ECB block mode. - * - * Encrypts AES using the ECB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @return Status from encrypt operation - */ -status_t LTC_AES_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t *key, - uint32_t keySize); - -/*! - * @brief Decrypts AES using ECB block mode. - * - * Decrypts AES using ECB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param key Input key. - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param keyType Input type of the key (allows to directly load decrypt key for AES ECB decrypt operation.) - * @return Status from decrypt operation - */ -status_t LTC_AES_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @param key Input key to use for encryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @return Status from encrypt operation - */ -status_t LTC_AES_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @param key Input key to use for decryption - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param keyType Input type of the key (allows to directly load decrypt key for AES CBC decrypt operation.) - * @return Status from decrypt operation - */ -status_t LTC_AES_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_AES_IV_SIZE], - const uint8_t *key, - uint32_t keySize, - ltc_aes_key_t keyType); - -/*! - * @brief Encrypts or decrypts AES using CTR block mode. - * - * Encrypts or decrypts AES using CTR block mode. - * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. - * The only difference between encryption and decryption is that, for encryption, the input argument - * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text - * and the output argument is plain text. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param input Input data for CTR block mode - * @param[out] output Output data for CTR block mode - * @param size Size of input and output data in bytes - * @param[in,out] counter Input counter (updates on return) - * @param key Input key to use for forward AES cipher - * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32. - * @param[out] counterlast Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are - * not used. - * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls - * are not used. - * @return Status from encrypt operation - */ -status_t LTC_AES_CryptCtrEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *input, - uint8_t *output, - uint32_t size, - uint8_t counter[LTC_AES_BLOCK_SIZE], - const uint8_t *key, - uint32_t keySize, - uint8_t counterlast[LTC_AES_BLOCK_SIZE], - uint32_t *szLeft); - -/*! AES CTR decrypt is mapped to the AES CTR generic operation */ -#define LTC_AES_DecryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft) \ - LTC_AES_CryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft) - -/*! AES CTR encrypt is mapped to the AES CTR generic operation */ -#define LTC_AES_EncryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft) \ - LTC_AES_CryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft) - -/*! - *@} - */ - -/******************************************************************************* - * DES API - ******************************************************************************/ -/*! - * @addtogroup ltc_edma_driver_des - * @{ - */ -/*! - * @brief Encrypts DES using ECB block mode. - * - * Encrypts DES using ECB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key Input key to use for encryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using ECB block mode. - * - * Decrypts DES using ECB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts DES using CBC block mode. - * - * Encrypts DES using CBC block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Ouput ciphertext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key Input key to use for encryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using CBC block mode. - * - * Decrypts DES using CBC block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts DES using CFB block mode. - * - * Encrypts DES using CFB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param size Size of input data in bytes - * @param iv Input initial block. - * @param key Input key to use for encryption - * @param[out] ciphertext Output ciphertext - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using CFB block mode. - * - * Decrypts DES using CFB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial block. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts DES using OFB block mode. - * - * Encrypts DES using OFB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key Input key to use for encryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_EncryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts DES using OFB block mode. - * - * Decrypts DES using OFB block mode. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key Input key to use for decryption - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES_DecryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using ECB block mode with two keys. - * - * Encrypts triple DES using ECB block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using ECB block mode with two keys. - * - * Decrypts triple DES using ECB block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CBC block mode with two keys. - * - * Encrypts triple DES using CBC block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CBC block mode with two keys. - * - * Decrypts triple DES using CBC block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CFB block mode with two keys. - * - * Encrypts triple DES using CFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CFB block mode with two keys. - * - * Decrypts triple DES using CFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using OFB block mode with two keys. - * - * Encrypts triple DES using OFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_EncryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using OFB block mode with two keys. - * - * Decrypts triple DES using OFB block mode with two keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES2_DecryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using ECB block mode with three keys. - * - * Encrypts triple DES using ECB block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using ECB block mode with three keys. - * - * Decrypts triple DES using ECB block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes. Must be multiple of 8 bytes. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptEcbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CBC block mode with three keys. - * - * Encrypts triple DES using CBC block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CBC block mode with three keys. - * - * Decrypts triple DES using CBC block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input initial vector to combine with the first plaintext block. - * The iv does not need to be secret, but it must be unpredictable. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptCbcEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using CFB block mode with three keys. - * - * Encrypts triple DES using CFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and ouput data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using CFB block mode with three keys. - * - * Decrypts triple DES using CFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input data in bytes - * @param iv Input initial block. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptCfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Encrypts triple DES using OFB block mode with three keys. - * - * Encrypts triple DES using OFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param plaintext Input plaintext to encrypt - * @param[out] ciphertext Output ciphertext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_EncryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - * @brief Decrypts triple DES using OFB block mode with three keys. - * - * Decrypts triple DES using OFB block mode with three keys. - * - * @param base LTC peripheral base address - * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state. - * @param ciphertext Input ciphertext to decrypt - * @param[out] plaintext Output plaintext - * @param size Size of input and output data in bytes - * @param iv Input unique input vector. The OFB mode requires that the IV be unique - * for each execution of the mode under the given key. - * @param key1 First input key for key bundle - * @param key2 Second input key for key bundle - * @param key3 Third input key for key bundle - * @return Status from encrypt/decrypt operation - */ -status_t LTC_DES3_DecryptOfbEDMA(LTC_Type *base, - ltc_edma_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - uint32_t size, - const uint8_t iv[LTC_DES_IV_SIZE], - const uint8_t key1[LTC_DES_KEY_SIZE], - const uint8_t key2[LTC_DES_KEY_SIZE], - const uint8_t key3[LTC_DES_KEY_SIZE]); - -/*! - *@} - */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_LTC_EDMA_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_pit.c b/third_party/nxp/MKW41Z4/drivers/fsl_pit.c deleted file mode 100644 index e5c3c4e01..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_pit.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pit.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base PIT peripheral base address - * - * @return The PIT instance - */ -static uint32_t PIT_GetInstance(PIT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PIT bases for each instance. */ -static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PIT clocks for each instance. */ -static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PIT_GetInstance(PIT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++) - { - if (s_pitBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_pitBases)); - - return instance; -} - -void PIT_Init(PIT_Type *base, const pit_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the PIT clock*/ - CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Enable PIT timers */ - base->MCR &= ~PIT_MCR_MDIS_MASK; - - /* Config timer operation when in debug mode */ - if (config->enableRunInDebug) - { - base->MCR &= ~PIT_MCR_FRZ_MASK; - } - else - { - base->MCR |= PIT_MCR_FRZ_MASK; - } -} - -void PIT_Deinit(PIT_Type *base) -{ - /* Disable PIT timers */ - base->MCR |= PIT_MCR_MDIS_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the PIT clock*/ - CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER - -uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) -{ - uint32_t valueH = 0U; - uint32_t valueL = 0U; - - /* LTMR64H should be read before LTMR64L */ - valueH = base->LTMR64H; - valueL = base->LTMR64L; - - return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); -} - -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_pit.h b/third_party/nxp/MKW41Z4/drivers/fsl_pit.h deleted file mode 100644 index 99c30e1e4..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_pit.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PIT_H_ -#define _FSL_PIT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pit - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! - * @brief List of PIT channels - * @note Actual number of available channels is SoC dependent - */ -typedef enum _pit_chnl -{ - kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ - kPIT_Chnl_1, /*!< PIT channel number 1 */ - kPIT_Chnl_2, /*!< PIT channel number 2 */ - kPIT_Chnl_3, /*!< PIT channel number 3 */ -} pit_chnl_t; - -/*! @brief List of PIT interrupts */ -typedef enum _pit_interrupt_enable -{ - kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ -} pit_interrupt_enable_t; - -/*! @brief List of PIT status flags */ -typedef enum _pit_status_flags -{ - kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ -} pit_status_flags_t; - -/*! - * @brief PIT configuration structure - * - * This structure holds the configuration settings for the PIT peripheral. To initialize this - * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _pit_config -{ - bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ -} pit_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. - * - * @note This API should be called at the beginning of the application using the PIT driver. - * - * @param base PIT peripheral base address - * @param config Pointer to the user's PIT config structure - */ -void PIT_Init(PIT_Type *base, const pit_config_t *config); - -/*! - * @brief Gates the PIT clock and disables the PIT module. - * - * @param base PIT peripheral base address - */ -void PIT_Deinit(PIT_Type *base); - -/*! - * @brief Fills in the PIT configuration structure with the default settings. - * - * The default values are as follows. - * @code - * config->enableRunInDebug = false; - * @endcode - * @param config Pointer to the onfiguration structure. - */ -static inline void PIT_GetDefaultConfig(pit_config_t *config) -{ - assert(config); - - /* Timers are stopped in Debug mode */ - config->enableRunInDebug = false; -} - -#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE - -/*! - * @brief Enables or disables chaining a timer with the previous timer. - * - * When a timer has a chain mode enabled, it only counts after the previous - * timer has expired. If the timer n-1 has counted down to 0, counter n - * decrements the value by one. Each timer is 32-bits, which allows the developers - * to chain timers together and form a longer timer (64-bits and larger). The first timer - * (timer 0) can't be chained to any other timer. - * - * @param base PIT peripheral base address - * @param channel Timer channel number which is chained with the previous timer - * @param enable Enable or disable chain. - * true: Current timer is chained with the previous timer. - * false: Timer doesn't chain with other timers. - */ -static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) -{ - if (enable) - { - base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; - } - else - { - base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; - } -} - -#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TCTRL |= mask; -} - -/*! - * @brief Disables the selected PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TCTRL &= ~mask; -} - -/*! - * @brief Gets the enabled PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) -{ - return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the PIT status flags. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::pit_status_flags_t - */ -static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) -{ - return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); -} - -/*! - * @brief Clears the PIT status flags. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::pit_status_flags_t - */ -static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TFLG = mask; -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers begin counting from the value set by this function until it reaches 0, - * then it generates an interrupt and load this register value again. - * Writing a new value to this register does not restart the timer. Instead, the value - * is loaded after the timer expires. - * - * @note Users can call the utility macros provided in fsl_common.h to convert to ticks. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - */ -static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) -{ - base->CHANNEL[channel].LDVAL = count; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) -{ - return base->CHANNEL[channel].CVAL; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, count down to 0 and - * then load the respective start value again. Each time a timer reaches 0, - * it generates a trigger pulse and sets the timeout interrupt flag. - * - * @param base PIT peripheral base address - * @param channel Timer channel number. - */ -static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) -{ - base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops every timer counting. Timers reload their periods - * respectively after the next time they call the PIT_DRV_StartTimer. - * - * @param base PIT peripheral base address - * @param channel Timer channel number. - */ -static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) -{ - base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; -} - -/*! @}*/ - -#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER - -/*! - * @brief Reads the current lifetime counter value. - * - * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. - * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. - * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". - * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit - * has the value of timer 0. - * - * @param base PIT peripheral base address - * - * @return Current lifetime timer value - */ -uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); - -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PIT_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_pmc.c b/third_party/nxp/MKW41Z4/drivers/fsl_pmc.c deleted file mode 100644 index bcdd5cb82..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_pmc.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_pmc.h" - -#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) -void PMC_GetParam(PMC_Type *base, pmc_param_t *param) -{ - uint32_t reg = base->PARAM; - ; - param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK); - param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK); -} -#endif /* FSL_FEATURE_PMC_HAS_PARAM */ - -void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) -{ - base->LVDSC1 = (0U | -#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) - ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) | -#endif - ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) | - ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT) - /* Clear the Low Voltage Detect Flag with previouse power detect setting */ - | PMC_LVDSC1_LVDACK_MASK); -} - -void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) -{ - base->LVDSC2 = (0U | -#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) - ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) | -#endif - ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT) - /* Clear the Low Voltage Warning Flag with previouse power detect setting */ - | PMC_LVDSC2_LVWACK_MASK); -} - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) -{ - base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | - ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) | - ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT) - /* Clear the High Voltage Detect Flag with previouse power detect setting */ - | PMC_HVDSC1_HVDACK_MASK); -} -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ - (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ - (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) -void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) -{ - base->REGSC = (0U -#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) - | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT) -#endif /* FSL_FEATURE_PMC_HAS_BGBE */ -#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) - | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT)) -#endif /* FSL_FEATURE_PMC_HAS_BGEN */ -#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) - | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT) -#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ - ); -} -#endif diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_pmc.h b/third_party/nxp/MKW41Z4/drivers/fsl_pmc.h deleted file mode 100644 index 99fc149fc..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_pmc.h +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PMC_H_ -#define _FSL_PMC_H_ - -#include "fsl_common.h" - -/*! @addtogroup pmc */ -/*! @{ */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PMC driver version */ -#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) -/*! - * @brief Low-voltage Detect Voltage Select - */ -typedef enum _pmc_low_volt_detect_volt_select -{ - kPMC_LowVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/ - kPMC_LowVoltDetectHighTrip = 1U /*!< High-trip point selected (VLVD = VLVDH )*/ -} pmc_low_volt_detect_volt_select_t; -#endif - -#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) -/*! - * @brief Low-voltage Warning Voltage Select - */ -typedef enum _pmc_low_volt_warning_volt_select -{ - kPMC_LowVoltWarningLowTrip = 0U, /*!< Low-trip point selected (VLVW = VLVW1)*/ - kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ - kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ - kPMC_LowVoltWarningHighTrip = 3U /*!< High-trip point selected (VLVW = VLVW4)*/ -} pmc_low_volt_warning_volt_select_t; -#endif - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -/*! - * @brief High-voltage Detect Voltage Select - */ -typedef enum _pmc_high_volt_detect_volt_select -{ - kPMC_HighVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/ - kPMC_HighVoltDetectHighTrip = 1U /*!< High-trip point selected (VHVD = VHVDH )*/ -} pmc_high_volt_detect_volt_select_t; -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) -/*! - * @brief Bandgap Buffer Drive Select. - */ -typedef enum _pmc_bandgap_buffer_drive_select -{ - kPMC_BandgapBufferDriveLow = 0U, /*!< Low-drive. */ - kPMC_BandgapBufferDriveHigh = 1U /*!< High-drive. */ -} pmc_bandgap_buffer_drive_select_t; -#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ - -#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO) -/*! - * @brief VLPx Option - */ -typedef enum _pmc_vlp_freq_option -{ - kPMC_FreqRestrict = 0U, /*!< Frequency is restricted in VLPx mode. */ - kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */ -} pmc_vlp_freq_mode_t; -#endif /* FSL_FEATURE_PMC_HAS_VLPO */ - -#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) -/*! - @brief IP version ID definition. - */ -typedef struct _pmc_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} pmc_version_id_t; -#endif /* FSL_FEATURE_PMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) -/*! @brief IP parameter definition. */ -typedef struct _pmc_param -{ - bool vlpoEnable; /*!< VLPO enable. */ - bool hvdEnable; /*!< HVD enable. */ -} pmc_param_t; -#endif /* FSL_FEATURE_PMC_HAS_PARAM */ - -/*! - * @brief Low-voltage Detect Configuration Structure - */ -typedef struct _pmc_low_volt_detect_config -{ - bool enableInt; /*!< Enable interrupt when Low-voltage detect*/ - bool enableReset; /*!< Enable system reset when Low-voltage detect*/ -#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) - pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/ -#endif -} pmc_low_volt_detect_config_t; - -/*! - * @brief Low-voltage Warning Configuration Structure - */ -typedef struct _pmc_low_volt_warning_config -{ - bool enableInt; /*!< Enable interrupt when low-voltage warning*/ -#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) - pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/ -#endif -} pmc_low_volt_warning_config_t; - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -/*! - * @brief High-voltage Detect Configuration Structure - */ -typedef struct _pmc_high_volt_detect_config -{ - bool enableInt; /*!< Enable interrupt when high-voltage detect*/ - bool enableReset; /*!< Enable system reset when high-voltage detect*/ - pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/ -} pmc_high_volt_detect_config_t; -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ - (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ - (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) -/*! - * @brief Bandgap Buffer configuration. - */ -typedef struct _pmc_bandgap_buffer_config -{ -#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) - bool enable; /*!< Enable bandgap buffer. */ -#endif -#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) - bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */ -#endif /* FSL_FEATURE_PMC_HAS_BGEN */ -#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) - pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ -#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ -} pmc_bandgap_buffer_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Power Management Controller Control APIs*/ -/*@{*/ - -#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) -/*! - * @brief Gets the PMC version ID. - * - * This function gets the PMC version ID, including major version number, - * minor version number, and a feature specification number. - * - * @param base PMC peripheral base address. - * @param versionId Pointer to version ID structure. - */ -static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif /* FSL_FEATURE_PMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) -/*! - * @brief Gets the PMC parameter. - * - * This function gets the PMC parameter including the VLPO enable and the HVD enable. - * - * @param base PMC peripheral base address. - * @param param Pointer to PMC param structure. - */ -void PMC_GetParam(PMC_Type *base, pmc_param_t *param); -#endif - -/*! - * @brief Configures the low-voltage detect setting. - * - * This function configures the low-voltage detect setting, including the trip - * point voltage setting, enables or disables the interrupt, enables or disables the system reset. - * - * @param base PMC peripheral base address. - * @param config Low-voltage detect configuration structure. - */ -void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config); - -/*! - * @brief Gets the Low-voltage Detect Flag status. - * - * This function reads the current LVDF status. If it returns 1, a low-voltage event is detected. - * - * @param base PMC peripheral base address. - * @return Current low-voltage detect flag - * - true: Low-voltage detected - * - false: Low-voltage not detected - */ -static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base) -{ - return (bool)(base->LVDSC1 & PMC_LVDSC1_LVDF_MASK); -} - -/*! - * @brief Acknowledges clearing the Low-voltage Detect flag. - * - * This function acknowledges the low-voltage detection errors (write 1 to - * clear LVDF). - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base) -{ - base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; -} - -/*! - * @brief Configures the low-voltage warning setting. - * - * This function configures the low-voltage warning setting, including the trip - * point voltage setting and enabling or disabling the interrupt. - * - * @param base PMC peripheral base address. - * @param config Low-voltage warning configuration structure. - */ -void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config); - -/*! - * @brief Gets the Low-voltage Warning Flag status. - * - * This function polls the current LVWF status. When 1 is returned, it - * indicates a low-voltage warning event. LVWF is set when V Supply transitions - * below the trip point or after reset and V Supply is already below the V LVW. - * - * @param base PMC peripheral base address. - * @return Current LVWF status - * - true: Low-voltage Warning Flag is set. - * - false: the Low-voltage Warning does not happen. - */ -static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base) -{ - return (bool)(base->LVDSC2 & PMC_LVDSC2_LVWF_MASK); -} - -/*! - * @brief Acknowledges the Low-voltage Warning flag. - * - * This function acknowledges the low voltage warning errors (write 1 to - * clear LVWF). - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base) -{ - base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; -} - -#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) -/*! - * @brief Configures the high-voltage detect setting. - * - * This function configures the high-voltage detect setting, including the trip - * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset. - * - * @param base PMC peripheral base address. - * @param config High-voltage detect configuration structure. - */ -void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config); - -/*! - * @brief Gets the High-voltage Detect Flag status. - * - * This function reads the current HVDF status. If it returns 1, a low - * voltage event is detected. - * - * @param base PMC peripheral base address. - * @return Current high-voltage detect flag - * - true: High-voltage detected - * - false: High-voltage not detected - */ -static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base) -{ - return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK); -} - -/*! - * @brief Acknowledges clearing the High-voltage Detect flag. - * - * This function acknowledges the high-voltage detection errors (write 1 to - * clear HVDF). - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base) -{ - base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK; -} -#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ - -#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ - (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ - (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) -/*! - * @brief Configures the PMC bandgap. - * - * This function configures the PMC bandgap, including the drive select and - * behavior in low-power mode. - * - * @param base PMC peripheral base address. - * @param config Pointer to the configuration structure - */ -void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config); -#endif - -#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO) -/*! - * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. - * - * This function reads the Acknowledge Isolation setting that indicates - * whether certain peripherals and the I/O pads are in a latched state as - * a result of having been in the VLLS mode. - * - * @param base PMC peripheral base address. - * @param base Base address for current PMC instance. - * @return ACK isolation - * 0 - Peripherals and I/O pads are in a normal run state. - * 1 - Certain peripherals and I/O pads are in an isolated and - * latched state. - */ -static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base) -{ - return (bool)(base->REGSC & PMC_REGSC_ACKISO_MASK); -} - -/*! - * @brief Acknowledges the isolation flag to Peripherals and I/O pads. - * - * This function clears the ACK Isolation flag. Writing one to this setting - * when it is set releases the I/O pads and certain peripherals to their normal - * run mode state. - * - * @param base PMC peripheral base address. - */ -static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base) -{ - base->REGSC |= PMC_REGSC_ACKISO_MASK; -} -#endif /* FSL_FEATURE_PMC_HAS_ACKISO */ - -#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS) -/*! - * @brief Gets the regulator regulation status. - * - * This function returns the regulator to run a regulation status. It provides - * the current status of the internal voltage regulator. - * - * @param base PMC peripheral base address. - * @param base Base address for current PMC instance. - * @return Regulation status - * 0 - Regulator is in a stop regulation or in transition to/from the regulation. - * 1 - Regulator is in a run regulation. - * - */ -static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base) -{ - return (bool)(base->REGSC & PMC_REGSC_REGONS_MASK); -} -#endif /* FSL_FEATURE_PMC_HAS_REGONS */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_PMC_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_port.h b/third_party/nxp/MKW41Z4/drivers/fsl_port.h deleted file mode 100644 index eb8e77e6d..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_port.h +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PORT_H_ -#define _FSL_PORT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup port - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! Version 2.0.2. */ -#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE -/*! @brief Internal resistor pull feature selection */ -enum _port_pull -{ - kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */ - kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */ - kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ - -#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE -/*! @brief Slew rate selection */ -enum _port_slew_rate -{ - kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */ - kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ - -#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN -/*! @brief Open Drain feature enable/disable */ -enum _port_open_drain_enable -{ - kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */ - kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ - -#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER -/*! @brief Passive filter feature enable/disable */ -enum _port_passive_filter_enable -{ - kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */ - kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */ -}; -#endif - -#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH -/*! @brief Configures the drive strength. */ -enum _port_drive_strength -{ - kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */ - kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */ - -#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK -/*! @brief Unlock/lock the pin control register field[15:0] */ -enum _port_lock_register -{ - kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ - kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH -/*! @brief Pin mux selection */ -typedef enum _port_mux -{ - kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ - kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ - kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ - kPORT_MuxAlt3 = 3U, /*!< Chip-specific */ - kPORT_MuxAlt4 = 4U, /*!< Chip-specific */ - kPORT_MuxAlt5 = 5U, /*!< Chip-specific */ - kPORT_MuxAlt6 = 6U, /*!< Chip-specific */ - kPORT_MuxAlt7 = 7U, /*!< Chip-specific */ - kPORT_MuxAlt8 = 8U, /*!< Chip-specific */ - kPORT_MuxAlt9 = 9U, /*!< Chip-specific */ - kPORT_MuxAlt10 = 10U, /*!< Chip-specific */ - kPORT_MuxAlt11 = 11U, /*!< Chip-specific */ - kPORT_MuxAlt12 = 12U, /*!< Chip-specific */ - kPORT_MuxAlt13 = 13U, /*!< Chip-specific */ - kPORT_MuxAlt14 = 14U, /*!< Chip-specific */ - kPORT_MuxAlt15 = 15U, /*!< Chip-specific */ -} port_mux_t; -#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ - -/*! @brief Configures the interrupt generation condition. */ -typedef enum _port_interrupt -{ - kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ -#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST - kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ - kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ - kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ -#endif -#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG - kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ - kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ - kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ -#endif - kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ - kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ - kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ - kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ - kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ -#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER - kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ - kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ -#endif -} port_interrupt_t; - -#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER -/*! @brief Digital filter clock source selection */ -typedef enum _port_digital_filter_clock_source -{ - kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ - kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ -} port_digital_filter_clock_source_t; - -/*! @brief PORT digital filter feature configuration definition */ -typedef struct _port_digital_filter_config -{ - uint32_t digitalFilterWidth; /*!< Set digital filter width */ - port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ -} port_digital_filter_config_t; -#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH -/*! @brief PORT pin configuration structure */ -typedef struct _port_pin_config -{ -#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE - uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */ -#else - uint16_t : 2; -#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ - -#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE - uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ - - uint16_t : 1; - -#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER - uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */ - -#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN - uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ - -#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH - uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */ -#else - uint16_t : 1; -#endif - - uint16_t : 1; - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH - uint16_t mux : 3; /*!< Pin mux Configure */ -#else - uint16_t : 3; -#endif - - uint16_t : 4; - -#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK - uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ -} port_pin_config_t; -#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ - -/******************************************************************************* -* API -******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH -/*! @name Configuration */ -/*@{*/ - -/*! - * @brief Sets the port PCR register. - * - * This is an example to define an input pin or output pin PCR configuration. - * @code - * // Define a digital input pin PCR configuration - * port_pin_config_t config = { - * kPORT_PullUp, - * kPORT_FastSlewRate, - * kPORT_PassiveFilterDisable, - * kPORT_OpenDrainDisable, - * kPORT_LowDriveStrength, - * kPORT_MuxAsGpio, - * kPORT_UnLockRegister, - * }; - * @endcode - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param config PORT PCR register configuration structure. - */ -static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) -{ - assert(config); - uint32_t addr = (uint32_t)&base->PCR[pin]; - *(volatile uint16_t *)(addr) = *((const uint16_t *)config); -} - -/*! - * @brief Sets the port PCR register for multiple pins. - * - * This is an example to define input pins or output pins PCR configuration. - * @code - * // Define a digital input pin PCR configuration - * port_pin_config_t config = { - * kPORT_PullUp , - * kPORT_PullEnable, - * kPORT_FastSlewRate, - * kPORT_PassiveFilterDisable, - * kPORT_OpenDrainDisable, - * kPORT_LowDriveStrength, - * kPORT_MuxAsGpio, - * kPORT_UnlockRegister, - * }; - * @endcode - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - * @param config PORT PCR register configuration structure. - */ -static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) -{ - assert(config); - - uint16_t pcrl = *((const uint16_t *)config); - - if (mask & 0xffffU) - { - base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; - } - if (mask >> 16) - { - base->GPCHR = (mask & 0xffff0000U) | pcrl; - } -} - -/*! - * @brief Configures the pin muxing. - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param mux pin muxing slot selection. - * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. - * - #kPORT_MuxAsGpio : Set as GPIO. - * - #kPORT_MuxAlt2 : chip-specific. - * - #kPORT_MuxAlt3 : chip-specific. - * - #kPORT_MuxAlt4 : chip-specific. - * - #kPORT_MuxAlt5 : chip-specific. - * - #kPORT_MuxAlt6 : chip-specific. - * - #kPORT_MuxAlt7 : chip-specific. - * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because - * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is - * reset to zero : kPORT_PinDisabledOrAnalog). - * This function is recommended to use to reset the pin mux - * - */ -static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) -{ - base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); -} -#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ - -#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER - -/*! - * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - */ -static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) -{ - if (enable == true) - { - base->DFER |= mask; - } - else - { - base->DFER &= ~mask; - } -} - -/*! - * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. - * - * @param base PORT peripheral base pointer. - * @param config PORT digital filter configuration structure. - */ -static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) -{ - assert(config); - - base->DFCR = PORT_DFCR_CS(config->clockSource); - base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); -} - -#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ - -/*@}*/ - -/*! @name Interrupt */ -/*@{*/ - -/*! - * @brief Configures the port pin interrupt/DMA request. - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param config PORT pin interrupt configuration. - * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. - * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). - * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). - * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). - * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). - * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). - * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). - * - #kPORT_InterruptLogicZero : Interrupt when logic zero. - * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. - * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. - * - #kPORT_InterruptEitherEdge : Interrupt on either edge. - * - #kPORT_InterruptLogicOne : Interrupt when logic one. - * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). - * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). - */ -static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) -{ - base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); -} - -/*! - * @brief Reads the whole port status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base PORT peripheral base pointer. - * @return Current port interrupt status flags, for example, 0x00010001 means the - * pin 0 and 16 have the interrupt. - */ -static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) -{ - return base->ISFR; -} - -/*! - * @brief Clears the multiple pin interrupt status flag. - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - */ -static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) -{ - base->ISFR = mask; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PORT_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_rcm.c b/third_party/nxp/MKW41Z4/drivers/fsl_rcm.c deleted file mode 100644 index 0d738643b..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_rcm.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rcm.h" - -void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) -{ - assert(config); - -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - uint32_t reg; - - reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait); - if (config->filterInRunWait == kRCM_FilterBusClock) - { - reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT); - } - base->RPC = reg; -#else - base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait); - if (config->filterInRunWait == kRCM_FilterBusClock) - { - base->RPFW = config->busClockFilterCount; - } -#endif /* FSL_FEATURE_RCM_REG_WIDTH */ -} - -#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) -void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) -{ - uint32_t reg; - - reg = base->FM; - reg &= ~RCM_FM_FORCEROM_MASK; - reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT); - base->FM = reg; -} -#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_rcm.h b/third_party/nxp/MKW41Z4/drivers/fsl_rcm.h deleted file mode 100644 index 99b843aaf..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_rcm.h +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RCM_H_ -#define _FSL_RCM_H_ - -#include "fsl_common.h" - -/*! @addtogroup rcm */ -/*! @{*/ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief RCM driver version 2.0.1. */ -#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief System Reset Source Name definitions - */ -typedef enum _rcm_reset_source -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) -/* RCM register bit width is 32. */ -#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) - kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ -#endif - kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */ -#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) - kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOC */ -#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) - kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOL */ - kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ - kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ - kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ -#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) - kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ -#endif /* FSL_FEATURE_RCM_HAS_JTAG */ - kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ - kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ -#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) - kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ -#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ -#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) - kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ -#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ - kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ - -#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -/* RCM register bit width is 8. */ -#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) - kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ -#endif - kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */ -#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) - kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOC */ -#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) - kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ -#endif /* FSL_FEATURE_RCM_HAS_LOL */ - kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ - kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ - kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ -#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) - kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ -#endif /* FSL_FEATURE_RCM_HAS_JTAG */ - kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ - kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */ -#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) - kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ -#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ -#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) - kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ -#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ - kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ - kRCM_SourceAll = 0xffffffffU, -} rcm_reset_source_t; - -/*! - * @brief Reset pin filter select in Run and Wait modes. - */ -typedef enum _rcm_run_wait_filter_mode -{ - kRCM_FilterDisable = 0U, /*!< All filtering disabled */ - kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ - kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ -} rcm_run_wait_filter_mode_t; - -#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) -/*! - * @brief Boot from ROM configuration. - */ -typedef enum _rcm_boot_rom_config -{ - kRCM_BootFlash = 0U, /*!< Boot from flash */ - kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ - kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ - kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ -} rcm_boot_rom_config_t; -#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ - -#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) -/*! - * @brief Maximum delay time from interrupt asserts to system reset. - */ -typedef enum _rcm_reset_delay -{ - kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ - kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ - kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ - kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ -} rcm_reset_delay_t; - -/*! - * @brief System reset interrupt enable bit definitions. - */ -typedef enum _rcm_interrupt_enable -{ - kRCM_IntNone = 0U, /*!< No interrupt enabled. */ - kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ - kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ - kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ - kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ - kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ - kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ - kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ - kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ -#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) - kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ -#endif - kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ - | - RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | - RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK -#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) - | - RCM_SRIE_CORE1_MASK -#endif -} rcm_interrupt_enable_t; -#endif /* FSL_FEATURE_RCM_HAS_SRIE */ - -#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) -/*! - * @brief IP version ID definition. - */ -typedef struct _rcm_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} rcm_version_id_t; -#endif - -/*! - * @brief Reset pin filter configuration. - */ -typedef struct _rcm_reset_pin_filter_config -{ - bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ - rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ - uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ -} rcm_reset_pin_filter_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name Reset Control Module APIs*/ -/*@{*/ - -#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) -/*! - * @brief Gets the RCM version ID. - * - * This function gets the RCM version ID including the major version number, - * the minor version number, and the feature specification number. - * - * @param base RCM peripheral base address. - * @param versionId Pointer to the version ID structure. - */ -static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif - -#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) -/*! - * @brief Gets the reset source implemented status. - * - * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. - * Use source masks defined in the rcm_reset_source_t to get the desired source status. - * - * This is an example. - @code - uint32_t status; - - // To test whether the MCU is reset using Watchdog. - status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @return All reset source implemented status bit map. - */ -static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) -{ - return base->PARAM; -} -#endif /* FSL_FEATURE_RCM_HAS_PARAM */ - -/*! - * @brief Gets the reset source status which caused a previous reset. - * - * This function gets the current reset source status. Use source masks - * defined in the rcm_reset_source_t to get the desired source status. - * - * This is an example. - @code - uint32_t resetStatus; - - // To get all reset source statuses. - resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; - - // To test whether the MCU is reset using Watchdog. - resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; - - // To test multiple reset sources. - resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @return All reset source status bit map. - */ -static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - return base->SRS; -#else - return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U)); -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -} - -#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) -/*! - * @brief Gets the sticky reset source status. - * - * This function gets the current reset source status that has not been cleared - * by software for a specific source. - * - * This is an example. - @code - uint32_t resetStatus; - - // To get all reset source statuses. - resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; - - // To test whether the MCU is reset using Watchdog. - resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; - - // To test multiple reset sources. - resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @return All reset source status bit map. - */ -static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - return base->SSRS; -#else - return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -} - -/*! - * @brief Clears the sticky reset source status. - * - * This function clears the sticky system reset flags indicated by source masks. - * - * This is an example. - @code - // Clears multiple reset sources. - RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); - @endcode - * - * @param base RCM peripheral base address. - * @param sourceMasks reset source status bit map - */ -static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) -{ -#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) - base->SSRS = sourceMasks; -#else - base->SSRS0 = (sourceMasks & 0xffU); - base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); -#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ -} -#endif /* FSL_FEATURE_RCM_HAS_SSRS */ - -/*! - * @brief Configures the reset pin filter. - * - * This function sets the reset pin filter including the filter source, filter - * width, and so on. - * - * @param base RCM peripheral base address. - * @param config Pointer to the configuration structure. - */ -void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); - -#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) -/*! - * @brief Gets the EZP_MS_B pin assert status. - * - * This function gets the easy port mode status (EZP_MS_B) pin assert status. - * - * @param base RCM peripheral base address. - * @return status true - asserted, false - reasserted - */ -static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) -{ - return (bool)(base->MR & RCM_MR_EZP_MS_MASK); -} -#endif /* FSL_FEATURE_RCM_HAS_EZPMS */ - -#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) -/*! - * @brief Gets the ROM boot source. - * - * This function gets the ROM boot source during the last chip reset. - * - * @param base RCM peripheral base address. - * @return The ROM boot source. - */ -static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) -{ - return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); -} - -/*! - * @brief Clears the ROM boot source flag. - * - * This function clears the ROM boot source flag. - * - * @param base Register base address of RCM - */ -static inline void RCM_ClearBootRomSource(RCM_Type *base) -{ - base->MR |= RCM_MR_BOOTROM_MASK; -} - -/*! - * @brief Forces the boot from ROM. - * - * This function forces booting from ROM during all subsequent system resets. - * - * @param base RCM peripheral base address. - * @param config Boot configuration. - */ -void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); -#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ - -#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) -/*! - * @brief Sets the system reset interrupt configuration. - * - * For a graceful shut down, the RCM supports delaying the assertion of the system - * reset for a period of time when the reset interrupt is generated. This function - * can be used to enable the interrupt and the delay period. The interrupts - * are passed in as bit mask. See rcm_int_t for details. For example, to - * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, - * configure as follows: - * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); - * - * @param base RCM peripheral base address. - * @param intMask Bit mask of the system reset interrupts to enable. See - * rcm_interrupt_enable_t for details. - * @param Delay Bit mask of the system reset interrupts to enable. - */ -static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) -{ - base->SRIE = (intMask | delay); -} -#endif /* FSL_FEATURE_RCM_HAS_SRIE */ -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_RCM_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_rtc.c b/third_party/nxp/MKW41Z4/drivers/fsl_rtc.c deleted file mode 100644 index d68055a26..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_rtc.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -void RTC_Init(RTC_Type *base, const rtc_config_t *config) -{ - assert(config); - - uint32_t reg; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rtc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Issue a software reset if timer is invalid */ - if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) - { - RTC_Reset(RTC); - } - - reg = base->CR; - /* Setup the update mode and supervisor access mode */ - reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); - reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); -#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION - /* Setup the wakeup pin select */ - reg &= ~(RTC_CR_WPS_MASK); - reg |= RTC_CR_WPS(config->wakeupSelect); -#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ - base->CR = reg; - - /* Configure the RTC time compensation register */ - base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); -} - -void RTC_GetDefaultConfig(rtc_config_t *config) -{ - assert(config); - - /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ - config->wakeupSelect = false; - /* Registers cannot be written when locked */ - config->updateMode = false; - /* Non-supervisor mode write accesses are not supported and will generate a bus error */ - config->supervisorAccess = false; - /* Compensation interval used by the crystal compensation logic */ - config->compensationInterval = 0; - /* Compensation time used by the crystal compensation logic */ - config->compensationTime = 0; -} - -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->TSR = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = base->TSR; - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = base->TSR; - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->TAR = alarmSeconds; - - return kStatus_Success; -} - -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->TAR; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} - -void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - /* The alarm flag is cleared by writing to the TAR register */ - if (mask & kRTC_AlarmFlag) - { - base->TAR = 0U; - } - - /* The timer overflow flag is cleared by initializing the TSR register. - * The time counter should be disabled for this write to be successful - */ - if (mask & kRTC_TimeOverflowFlag) - { - base->TSR = 1U; - } - - /* The timer overflow flag is cleared by initializing the TSR register. - * The time counter should be disabled for this write to be successful - */ - if (mask & kRTC_TimeInvalidFlag) - { - base->TSR = 1U; - } -} - -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - -void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) -{ - assert(counter); - - *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); -} - -void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) -{ - /* Prepare to initialize the register with the new value written */ - base->MER &= ~RTC_MER_MCE_MASK; - - base->MCHR = (uint32_t)((counter) >> 32); - base->MCLR = (uint32_t)(counter); -} - -status_t RTC_IncrementMonotonicCounter(RTC_Type *base) -{ - if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) - { - return kStatus_Fail; - } - - /* Prepare to switch to increment mode */ - base->MER |= RTC_MER_MCE_MASK; - /* Write anything so the counter increments*/ - base->MCLR = 1U; - - return kStatus_Success; -} - -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_rtc.h b/third_party/nxp/MKW41Z4/drivers/fsl_rtc.h deleted file mode 100644 index 99effc6dc..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_rtc.h +++ /dev/null @@ -1,414 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/ - kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/ - kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/ - kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */ - kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */ - kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/ -} rtc_status_flags_t; - -#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) - -/*! @brief List of RTC Oscillator capacitor load settings */ -typedef enum _rtc_osc_cap_load -{ - kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ - kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ - kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ - kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16 pF capacitor load */ -} rtc_osc_cap_load_t; - -#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -/*! - * @brief RTC config structure - * - * This structure holds the configuration settings for the RTC peripheral. To initialize this - * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _rtc_config -{ - bool wakeupSelect; /*!< true: Wakeup pin outputs the 32 KHz clock; - false:Wakeup pin used to wakeup the chip */ - bool updateMode; /*!< true: Registers can be written even when locked under certain - conditions, false: No writes allowed when registers are locked */ - bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed; - false: Non-supervisor accesses are not supported */ - uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */ - uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */ -} rtc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the RTC clock and configures the peripheral for basic operation. - * - * This function issues a software reset if the timer invalid flag is set. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - * @param config Pointer to the user's RTC configuration structure. - */ -void RTC_Init(RTC_Type *base, const rtc_config_t *config); - -/*! - * @brief Stops the timer and gate the RTC clock. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->SR &= ~RTC_SR_TCE_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Fills in the RTC config struct with the default settings. - * - * The default values are as follows. - * @code - * config->wakeupSelect = false; - * config->updateMode = false; - * config->supervisorAccess = false; - * config->compensationInterval = 0; - * config->compensationTime = 0; - * @endcode - * @param config Pointer to the user's RTC configuration structure. - */ -void RTC_GetDefaultConfig(rtc_config_t *config); - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function because writes to the RTC - * seconds register fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Gets the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Sets the RTC alarm time. - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to the structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Returns the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to the structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! - * @brief Disables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/*! - * @brief Gets the enabled RTC interrupts. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK)); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the RTC status flags. - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK)); -} - -/*! - * @brief Clears the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the RTC time counter. - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->SR |= RTC_SR_TCE_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->SR &= ~RTC_SR_TCE_MASK; -} - -/*! @}*/ - -#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) - -/*! - * @brief This function sets the specified capacitor configuration for the RTC oscillator. - * - * @param base RTC peripheral base address - * @param capLoad Oscillator loads to enable. This is a logical OR of members of the - * enumeration ::rtc_osc_cap_load_t - */ -static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad) -{ - uint32_t reg = base->CR; - - reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); - reg |= capLoad; - - base->CR = reg; -} - -#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ - -/*! - * @brief Performs a software reset on the RTC module. - * - * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR - * registers. The SWR bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CR |= RTC_CR_SWR_MASK; - base->CR &= ~RTC_CR_SWR_MASK; - - /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */ - base->TSR = 1U; -} - -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - -/*! - * @name Monotonic counter functions - * @{ - */ - -/*! - * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns - * them as a single value. - * - * @param base RTC peripheral base address - * @param counter Pointer to variable where the value is stored. - */ -void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); - -/*! - * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing - * the given single value. - * - * @param base RTC peripheral base address - * @param counter Counter value - */ -void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter); - -/*! - * @brief Increments the Monotonic Counter by one. - * - * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting - * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the - * monotonic counter low that causes it to overflow also increments the monotonic counter high. - * - * @param base RTC peripheral base address - * - * @return kStatus_Success: success - * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found - */ -status_t RTC_IncrementMonotonicCounter(RTC_Type *base); - -/*! @}*/ - -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_sim.c b/third_party/nxp/MKW41Z4/drivers/fsl_sim.c deleted file mode 100644 index ade512f03..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_sim.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sim.h" - -/******************************************************************************* - * Codes - ******************************************************************************/ -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) -{ - SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); - - SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask; -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ - -void SIM_GetUniqueId(sim_uid_t *uid) -{ -#if defined(SIM_UIDH) - uid->H = SIM->UIDH; -#endif - uid->MH = SIM->UIDMH; - uid->ML = SIM->UIDML; - uid->L = SIM->UIDL; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_sim.h b/third_party/nxp/MKW41Z4/drivers/fsl_sim.h deleted file mode 100644 index 0a0e4fb30..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_sim.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SIM_H_ -#define _FSL_SIM_H_ - -#include "fsl_common.h" - -/*! @addtogroup sim */ -/*! @{*/ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ -/*@}*/ - -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -/*!@brief USB voltage regulator enable setting. */ -enum _sim_usb_volt_reg_enable_mode -{ - kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ - kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ - kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ - kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | - SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ -}; -#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ - -/*!@brief Unique ID. */ -typedef struct _sim_uid -{ -#if defined(SIM_UIDH) - uint32_t H; /*!< UIDH. */ -#endif - uint32_t MH; /*!< UIDMH. */ - uint32_t ML; /*!< UIDML. */ - uint32_t L; /*!< UIDL. */ -} sim_uid_t; - -/*!@brief Flash enable mode. */ -enum _sim_flash_mode -{ - kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode. */ - kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK /*!< Disable flash in normal mode. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -/*! - * @brief Sets the USB voltage regulator setting. - * - * This function configures whether the USB voltage regulator is enabled in - * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations - * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable - * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, - * use: - * - * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); - * - * @param mask USB voltage regulator enable setting. - */ -void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask); -#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ - -/*! - * @brief Gets the unique identification register value. - * - * @param uid Pointer to the structure to save the UID value. - */ -void SIM_GetUniqueId(sim_uid_t *uid); - -/*! - * @brief Sets the flash enable mode. - * - * @param mode The mode to set; see \ref _sim_flash_mode for mode details. - */ -static inline void SIM_SetFlashMode(uint8_t mode) -{ - SIM->FCFG1 = mode; -} - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_SIM_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_smc.c b/third_party/nxp/MKW41Z4/drivers/fsl_smc.c deleted file mode 100644 index dacf19347..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_smc.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_smc.h" -#include "fsl_flash.h" - -#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) -void SMC_GetParam(SMC_Type *base, smc_param_t *param) -{ - uint32_t reg = base->PARAM; - param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); - param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); - param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); - param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); -} -#endif /* FSL_FEATURE_SMC_HAS_PARAM */ - -void SMC_PreEnterStopModes(void) -{ - flash_prefetch_speculation_status_t speculationStatus = - { - kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/ - kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/ - }; - - __disable_irq(); - __ISB(); - - /* - * Before enter stop modes, the flash cache prefetch should be disabled. - * Otherwise the prefetch might be interrupted by stop, then the data and - * and instruction from flash are wrong. - */ - FLASH_PflashSetPrefetchSpeculation(&speculationStatus); -} - -void SMC_PostExitStopModes(void) -{ - flash_prefetch_speculation_status_t speculationStatus = - { - kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/ - kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/ - }; - - FLASH_PflashSetPrefetchSpeculation(&speculationStatus); - - __enable_irq(); - __ISB(); -} - -status_t SMC_SetPowerModeRun(SMC_Type *base) -{ - uint8_t reg; - - reg = base->PMCTRL; - /* configure Normal RUN mode */ - reg &= ~SMC_PMCTRL_RUNM_MASK; - reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} - -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) -status_t SMC_SetPowerModeHsrun(SMC_Type *base) -{ - uint8_t reg; - - reg = base->PMCTRL; - /* configure High Speed RUN mode */ - reg &= ~SMC_PMCTRL_RUNM_MASK; - reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - -status_t SMC_SetPowerModeWait(SMC_Type *base) -{ - /* configure Normal Wait mode */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} - -status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) -{ - uint8_t reg; - -#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) - /* configure the Partial Stop mode in Noraml Stop mode */ - reg = base->STOPCTRL; - reg &= ~SMC_STOPCTRL_PSTOPO_MASK; - reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); - base->STOPCTRL = reg; -#endif - - /* configure Normal Stop mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - - /* check whether the power mode enter Stop mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} - -status_t SMC_SetPowerModeVlpr(SMC_Type *base -#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) - , - bool wakeupMode -#endif - ) -{ - uint8_t reg; - - reg = base->PMCTRL; -#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) - /* configure whether the system remains in VLP mode on an interrupt */ - if (wakeupMode) - { - /* exits to RUN mode on an interrupt */ - reg |= SMC_PMCTRL_LPWUI_MASK; - } - else - { - /* remains in VLP mode on an interrupt */ - reg &= ~SMC_PMCTRL_LPWUI_MASK; - } -#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ - - /* configure VLPR mode */ - reg &= ~SMC_PMCTRL_RUNM_MASK; - reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} - -status_t SMC_SetPowerModeVlpw(SMC_Type *base) -{ - /* configure VLPW mode */ - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} - -status_t SMC_SetPowerModeVlps(SMC_Type *base) -{ - uint8_t reg; - - /* configure VLPS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - - /* check whether the power mode enter VLPS mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} - -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) -status_t SMC_SetPowerModeLls(SMC_Type *base -#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ - (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) - , - const smc_power_mode_lls_config_t *config -#endif - ) -{ - uint8_t reg; - - /* configure to LLS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - -/* configure LLS sub-mode*/ -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - reg = base->STOPCTRL; - reg &= ~SMC_STOPCTRL_LLSM_MASK; - reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); - base->STOPCTRL = reg; -#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ - -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - if (config->enableLpoClock) - { - base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; - } - else - { - base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; - } -#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - - /* check whether the power mode enter LLS mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) -status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) -{ - uint8_t reg; - -#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ - (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ - (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - if (config->subMode == kSMC_StopSub0) -#endif - { - /* configure whether the Por Detect work in Vlls0 mode */ - if (config->enablePorDetectInVlls0) - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; -#else - base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK; -#endif - } - else - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; -#else - base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; -#endif - } - } -#endif /* FSL_FEATURE_SMC_HAS_PORPO */ - -#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) - else if (config->subMode == kSMC_StopSub2) - { - /* configure whether the Por Detect work in Vlls0 mode */ - if (config->enableRam2InVlls2) - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; -#else - base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; -#endif - } - else - { -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; -#else - base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK; -#endif - } - } - else - { - } -#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ - - /* configure to VLLS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - -/* configure the VLLS sub-mode */ -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) - reg = base->VLLSCTRL; - reg &= ~SMC_VLLSCTRL_VLLSM_MASK; - reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); - base->VLLSCTRL = reg; -#else -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - reg = base->STOPCTRL; - reg &= ~SMC_STOPCTRL_LLSM_MASK; - reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); - base->STOPCTRL = reg; -#else - reg = base->STOPCTRL; - reg &= ~SMC_STOPCTRL_VLLSM_MASK; - reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); - base->STOPCTRL = reg; -#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ -#endif - -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - if (config->enableLpoClock) - { - base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; - } - else - { - base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; - } -#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - - /* check whether the power mode enter LLS mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -} -#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_smc.h b/third_party/nxp/MKW41Z4/drivers/fsl_smc.h deleted file mode 100644 index 168ce8350..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_smc.h +++ /dev/null @@ -1,456 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SMC_H_ -#define _FSL_SMC_H_ - -#include "fsl_common.h" - -/*! @addtogroup smc */ -/*! @{ */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SMC driver version 2.0.3. */ -#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ - -/*! - * @brief Power Modes Protection - */ -typedef enum _smc_power_mode_protection -{ -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode. */ -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode. */ -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode. */ -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - kSMC_AllowPowerModeAll = (0U -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - | - SMC_PMPROT_AVLLS_MASK -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - | - SMC_PMPROT_ALLS_MASK -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - | - SMC_PMPROT_AVLP_MASK -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - | - kSMC_AllowPowerModeHsrun -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - ) /*!< Allow all power mode. */ -} smc_power_mode_protection_t; - -/*! - * @brief Power Modes in PMSTAT - */ -typedef enum _smc_power_state -{ - kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */ - kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */ - kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ - kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */ - kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */ -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */ -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ -} smc_power_state_t; - -/*! - * @brief Run mode definition - */ -typedef enum _smc_run_mode -{ - kSMC_RunNormal = 0U, /*!< Normal RUN mode. */ - kSMC_RunVlpr = 2U, /*!< Very-low-power RUN mode. */ -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) - kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */ -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ -} smc_run_mode_t; - -/*! - * @brief Stop mode definition - */ -typedef enum _smc_stop_mode -{ - kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ - kSMC_StopVlps = 2U, /*!< Very-low-power STOP mode. */ -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) - kSMC_StopLls = 3U, /*!< Low-leakage Stop mode. */ -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) - kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */ -#endif -} smc_stop_mode_t; - -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ - (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ - (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) -/*! - * @brief VLLS/LLS stop sub mode definition - */ -typedef enum _smc_stop_submode -{ - kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */ - kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */ - kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */ - kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */ -} smc_stop_submode_t; -#endif - -/*! - * @brief Partial STOP option - */ -typedef enum _smc_partial_stop_mode -{ - kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ - kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ - kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ -} smc_partial_stop_option_t; - -/*! - * @brief SMC configuration status. - */ -enum _smc_status -{ - kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/ -}; - -#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) -/*! - * @brief IP version ID definition. - */ -typedef struct _smc_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} smc_version_id_t; -#endif /* FSL_FEATURE_SMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) -/*! - * @brief IP parameter definition. - */ -typedef struct _smc_param -{ - bool hsrunEnable; /*!< HSRUN mode enable. */ - bool llsEnable; /*!< LLS mode enable. */ - bool lls2Enable; /*!< LLS2 mode enable. */ - bool vlls0Enable; /*!< VLLS0 mode enable. */ -} smc_param_t; -#endif /* FSL_FEATURE_SMC_HAS_PARAM */ - -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ - (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) -/*! - * @brief SMC Low-Leakage Stop power mode configuration. - */ -typedef struct _smc_power_mode_lls_config -{ -#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - bool enableLpoClock; /*!< Enable LPO clock in LLS mode */ -#endif -} smc_power_mode_lls_config_t; -#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */ - -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) -/*! - * @brief SMC Very Low-Leakage Stop power mode configuration. - */ -typedef struct _smc_power_mode_vlls_config -{ -#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ - (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ - (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) - smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) - bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) - bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */ -#endif -#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) - bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */ -#endif -} smc_power_mode_vlls_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! @name System mode controller APIs*/ -/*@{*/ - -#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) -/*! - * @brief Gets the SMC version ID. - * - * This function gets the SMC version ID, including major version number, - * minor version number, and feature specification number. - * - * @param base SMC peripheral base address. - * @param versionId Pointer to the version ID structure. - */ -static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif /* FSL_FEATURE_SMC_HAS_VERID */ - -#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) -/*! - * @brief Gets the SMC parameter. - * - * This function gets the SMC parameter including the enabled power mdoes. - * - * @param base SMC peripheral base address. - * @param param Pointer to the SMC param structure. - */ -void SMC_GetParam(SMC_Type *base, smc_param_t *param); -#endif - -/*! - * @brief Configures all power mode protection settings. - * - * This function configures the power mode protection settings for - * supported power modes in the specified chip family. The available power modes - * are defined in the smc_power_mode_protection_t. This should be done at an early - * system level initialization stage. See the reference manual for details. - * This register can only write once after the power reset. - * - * The allowed modes are passed as bit map. For example, to allow LLS and VLLS, - * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps). - * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). - * - * @param base SMC peripheral base address. - * @param allowedModes Bitmap of the allowed power modes. - */ -static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) -{ - base->PMPROT = allowedModes; -} - -/*! - * @brief Gets the current power mode status. - * - * This function returns the current power mode status. After the application - * switches the power mode, it should always check the status to check whether it - * runs into the specified mode or not. The application should check - * this mode before switching to a different mode. The system requires that - * only certain modes can switch to other specific modes. See the - * reference manual for details and the smc_power_state_t for information about - * the power status. - * - * @param base SMC peripheral base address. - * @return Current power mode status. - */ -static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) -{ - return (smc_power_state_t)base->PMSTAT; -} - -/*! - * @brief Prepares to enter stop modes. - * - * This function should be called before entering STOP/VLPS/LLS/VLLS modes. - */ -void SMC_PreEnterStopModes(void); - -/*! - * @brief Recovers after wake up from stop modes. - * - * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. - * It is used with @ref SMC_PreEnterStopModes. - */ -void SMC_PostExitStopModes(void); - -/*! - * @brief Prepares to enter wait modes. - * - * This function should be called before entering WAIT/VLPW modes. - */ -static inline void SMC_PreEnterWaitModes(void) -{ - __disable_irq(); - __ISB(); -} - -/*! - * @brief Recovers after wake up from stop modes. - * - * This function should be called after wake up from WAIT/VLPW modes. - * It is used with @ref SMC_PreEnterWaitModes. - */ -static inline void SMC_PostExitWaitModes(void) -{ - __enable_irq(); - __ISB(); -} - -/*! - * @brief Configures the system to RUN power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeRun(SMC_Type *base); - -#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) -/*! - * @brief Configures the system to HSRUN power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeHsrun(SMC_Type *base); -#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ - -/*! - * @brief Configures the system to WAIT power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeWait(SMC_Type *base); - -/*! - * @brief Configures the system to Stop power mode. - * - * @param base SMC peripheral base address. - * @param option Partial Stop mode option. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); - -#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) -/*! - * @brief Configures the system to VLPR power mode. - * - * @param base SMC peripheral base address. - * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode); -#else -/*! - * @brief Configures the system to VLPR power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpr(SMC_Type *base); -#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ - -/*! - * @brief Configures the system to VLPW power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpw(SMC_Type *base); - -/*! - * @brief Configures the system to VLPS power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlps(SMC_Type *base); - -#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) -#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ - (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) -/*! - * @brief Configures the system to LLS power mode. - * - * @param base SMC peripheral base address. - * @param config The LLS power mode configuration structure - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config); -#else -/*! - * @brief Configures the system to LLS power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeLls(SMC_Type *base); -#endif -#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ - -#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) -/*! - * @brief Configures the system to VLLS power mode. - * - * @param base SMC peripheral base address. - * @param config The VLLS power mode configuration structure. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config); -#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_SMC_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_tpm.c b/third_party/nxp/MKW41Z4/drivers/fsl_tpm.c deleted file mode 100644 index 9a390a2be..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_tpm.c +++ /dev/null @@ -1,766 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_tpm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define TPM_COMBINE_SHIFT (8U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base TPM peripheral base address - * - * @return The TPM instance - */ -static uint32_t TPM_GetInstance(TPM_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to TPM bases for each instance. */ -static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to TPM clocks for each instance. */ -static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t TPM_GetInstance(TPM_Type *base) -{ - uint32_t instance; - uint32_t tpmArrayCount = (sizeof(s_tpmBases) / sizeof(s_tpmBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < tpmArrayCount; instance++) - { - if (s_tpmBases[instance] == base) - { - break; - } - } - - assert(instance < tpmArrayCount); - - return instance; -} - -void TPM_Init(TPM_Type *base, const tpm_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the module clock */ - CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL - /* TPM reset is available on certain SoC's */ - TPM_Reset(base); -#endif - - /* Set the clock prescale factor */ - base->SC = TPM_SC_PS(config->prescale); - - /* Setup the counter operation */ - base->CONF = TPM_CONF_DOZEEN(config->enableDoze) | TPM_CONF_GTBEEN(config->useGlobalTimeBase) | - TPM_CONF_CROT(config->enableReloadOnTrigger) | TPM_CONF_CSOT(config->enableStartOnTrigger) | - TPM_CONF_CSOO(config->enableStopOnOverflow) | -#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - TPM_CONF_CPOT(config->enablePauseOnTrigger) | -#endif -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - TPM_CONF_TRGSRC(config->triggerSource) | -#endif - TPM_CONF_TRGSEL(config->triggerSelect); - if (config->enableDebugMode) - { - base->CONF |= TPM_CONF_DBGMODE_MASK; - } - else - { - base->CONF &= ~TPM_CONF_DBGMODE_MASK; - } -} - -void TPM_Deinit(TPM_Type *base) -{ - /* Stop the counter */ - base->SC &= ~TPM_SC_CMOD_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the TPM clock */ - CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void TPM_GetDefaultConfig(tpm_config_t *config) -{ - assert(config); - - /* TPM clock divide by 1 */ - config->prescale = kTPM_Prescale_Divide_1; - /* Use internal TPM counter as timebase */ - config->useGlobalTimeBase = false; - /* TPM counter continues in doze mode */ - config->enableDoze = false; - /* TPM counter pauses when in debug mode */ - config->enableDebugMode = false; - /* TPM counter will not be reloaded on input trigger */ - config->enableReloadOnTrigger = false; - /* TPM counter continues running after overflow */ - config->enableStopOnOverflow = false; - /* TPM counter starts immediately once it is enabled */ - config->enableStartOnTrigger = false; -#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - config->enablePauseOnTrigger = false; -#endif - /* Choose trigger select 0 as input trigger for controlling counter operation */ - config->triggerSelect = kTPM_Trigger_Select_0; -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - /* Choose external trigger source to control counter operation */ - config->triggerSource = kTPM_TriggerSource_External; -#endif -} - -status_t TPM_SetupPwm(TPM_Type *base, - const tpm_chnl_pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - tpm_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz) -{ - assert(chnlParams); - assert(pwmFreq_Hz); - assert(numOfChnls); - assert(srcClock_Hz); -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if(mode == kTPM_CombinedPwm) - { - assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); - } -#endif - - uint32_t mod; - uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK))); - uint16_t cnv; - uint8_t i; - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/ - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } -#endif - - switch (mode) - { - case kTPM_EdgeAlignedPwm: -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - case kTPM_CombinedPwm: -#endif - base->SC &= ~TPM_SC_CPWMS_MASK; - mod = (tpmClock / pwmFreq_Hz) - 1; - break; - case kTPM_CenterAlignedPwm: - base->SC |= TPM_SC_CPWMS_MASK; - mod = tpmClock / (pwmFreq_Hz * 2); - break; - default: - return kStatus_Fail; - } - - /* Return an error in case we overflow the registers, probably would require changing - * clock source to get the desired frequency */ - if (mod > 65535U) - { - return kStatus_Fail; - } - /* Set the PWM period */ - base->MOD = mod; - - /* Setup each TPM channel */ - for (i = 0; i < numOfChnls; i++) - { - /* Return error if requested dutycycle is greater than the max allowed */ - if (chnlParams->dutyCyclePercent > 100) - { - return kStatus_Fail; - } -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if (mode == kTPM_CombinedPwm) - { - uint16_t cnvFirstEdge; - - /* This check is added for combined mode as the channel number should be the pair number */ - if (chnlParams->chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) - { - return kStatus_Fail; - } - - /* Return error if requested value is greater than the max allowed */ - if (chnlParams->firstEdgeDelayPercent > 100) - { - return kStatus_Fail; - } - /* Configure delay of the first edge */ - if (chnlParams->firstEdgeDelayPercent == 0) - { - /* No delay for the first edge */ - cnvFirstEdge = 0; - } - else - { - cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; - } - /* Configure dutycycle */ - if (chnlParams->dutyCyclePercent == 0) - { - /* Signal stays low */ - cnv = 0; - cnvFirstEdge = 0; - } - else - { - cnv = (mod * chnlParams->dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - } - - /* Set the combine bit for the channel pair */ - base->COMBINE |= (1U << (TPM_COMBINE_COMBINE0_SHIFT + (TPM_COMBINE_SHIFT * chnlParams->chnlNumber))); - - /* When switching mode, disable channel n first */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested PWM mode for channel n, PWM output requires mode select to be set to 2 */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnSC |= - ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - /* Set the channel pair values */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; - - /* When switching mode, disable channel n + 1 first */ - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested PWM mode for channel n + 1, PWM output requires mode select to be set to 2 */ - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC |= - ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - /* Set the channel pair values */ - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; - } - else - { -#endif - if (chnlParams->dutyCyclePercent == 0) - { - /* Signal stays low */ - cnv = 0; - } - else - { - cnv = (mod * chnlParams->dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - } - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlParams->chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlParams->chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested PWM mode, PWM output requires mode select to be set to 2 */ - base->CONTROLS[chnlParams->chnlNumber].CnSC |= - ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlParams->chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - } -#endif - - chnlParams++; - } - - return kStatus_Success; -} - -void TPM_UpdatePwmDutycycle(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_pwm_mode_t currentPwmMode, - uint8_t dutyCyclePercent) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if(currentPwmMode == kTPM_CombinedPwm) - { - assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); - } -#endif - - uint16_t cnv, mod; - - mod = base->MOD; -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if (currentPwmMode == kTPM_CombinedPwm) - { - uint16_t cnvFirstEdge; - - /* This check is added for combined mode as the channel number should be the pair number */ - if (chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) - { - return; - } - cnv = (mod * dutyCyclePercent) / 100; - cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; - } - else - { -#endif - cnv = (mod * dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - base->CONTROLS[chnlNumber].CnV = cnv; -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - } -#endif -} - -void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); - - uint32_t reg = base->CONTROLS[chnlNumber].CnSC & ~(TPM_CnSC_CHF_MASK); - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Clear the field and write the new level value */ - reg &= ~(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - reg |= ((uint32_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - base->CONTROLS[chnlNumber].CnSC = reg; - - /* Wait till mode change is acknowledged */ - reg &= (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - while (reg != (base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} - -void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode for channel 0 or 1*/ - if ((chnlNumber == 0) || (chnlNumber == 1)) - { - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } - } -#endif - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - /* The TPM's COMBINE register required to be effective */ - if( FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base) ) - { - /* Clear the combine bit for chnlNumber */ - base->COMBINE &= ~(1U << TPM_COMBINE_SHIFT * (chnlNumber / 2)); - } -#endif - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested input capture mode */ - base->CONTROLS[chnlNumber].CnSC |= captureMode; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} - -void TPM_SetupOutputCompare(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_output_compare_mode_t compareMode, - uint32_t compareValue) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode for channel 0 or 1 */ - if ((chnlNumber == 0) || (chnlNumber == 1)) - { - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } - } -#endif - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Setup the channel output behaviour when a match occurs with the compare value */ - base->CONTROLS[chnlNumber].CnSC |= compareMode; - - /* Setup the compare value */ - base->CONTROLS[chnlNumber].CnV = compareValue; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE -void TPM_SetupDualEdgeCapture(TPM_Type *base, - tpm_chnl_t chnlPairNumber, - const tpm_dual_edge_capture_param_t *edgeParam, - uint32_t filterValue) -{ - assert(edgeParam); - assert(chnlPairNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2); - assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); - - uint32_t reg; - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode for channel 0 or 1*/ - if (chnlPairNumber == 0) - { - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } - } -#endif - - /* Unlock: When switching mode, disable channel first */ - base->CONTROLS[chnlPairNumber * 2].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlPairNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlPairNumber * 2 + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Now, the registers for input mode can be operated. */ - if (edgeParam->enableSwap) - { - /* Set the combine and swap bits for the channel pair */ - base->COMBINE |= (TPM_COMBINE_COMBINE0_MASK | TPM_COMBINE_COMSWAP0_MASK) - << (TPM_COMBINE_SHIFT * chnlPairNumber); - - /* Input filter setup for channel n+1 input */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); - reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); - base->FILTER = reg; - } - else - { - reg = base->COMBINE; - /* Clear the swap bit for the channel pair */ - reg &= ~(TPM_COMBINE_COMSWAP0_MASK << (TPM_COMBINE_COMSWAP0_SHIFT * chnlPairNumber)); - - /* Set the combine bit for the channel pair */ - reg |= TPM_COMBINE_COMBINE0_MASK << (TPM_COMBINE_SHIFT * chnlPairNumber); - base->COMBINE = reg; - - /* Input filter setup for channel n input */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); - reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); - base->FILTER = reg; - } - - /* Setup the edge detection from channel n */ - base->CONTROLS[chnlPairNumber * 2].CnSC |= edgeParam->currChanEdgeMode; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlPairNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Setup the edge detection from channel n+1 */ - base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC |= edgeParam->nextChanEdgeMode; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} -#endif - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL -void TPM_SetupQuadDecode(TPM_Type *base, - const tpm_phase_params_t *phaseAParams, - const tpm_phase_params_t *phaseBParams, - tpm_quad_decode_mode_t quadMode) -{ - assert(phaseAParams); - assert(phaseBParams); - assert(FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base)); - - base->CONTROLS[0].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[0].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - uint32_t reg; - - /* Set Phase A filter value */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH0FVAL_MASK); - reg |= TPM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); - base->FILTER = reg; - -#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL - /* Set Phase A polarity */ - if (phaseAParams->phasePolarity) - { - base->POL |= TPM_POL_POL0_MASK; - } - else - { - base->POL &= ~TPM_POL_POL0_MASK; - } -#endif - - base->CONTROLS[1].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[1].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - /* Set Phase B filter value */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH1FVAL_MASK); - reg |= TPM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); - base->FILTER = reg; -#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL - /* Set Phase B polarity */ - if (phaseBParams->phasePolarity) - { - base->POL |= TPM_POL_POL1_MASK; - } - else - { - base->POL &= ~TPM_POL_POL1_MASK; - } -#endif - - /* Set Quadrature mode */ - reg = base->QDCTRL; - reg &= ~(TPM_QDCTRL_QUADMODE_MASK); - reg |= TPM_QDCTRL_QUADMODE(quadMode); - base->QDCTRL = reg; - - /* Enable Quad decode */ - base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK; -} - -#endif - -void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask) -{ - uint32_t chnlInterrupts = (mask & 0xFF); - uint8_t chnlNumber = 0; - - /* Enable the timer overflow interrupt */ - if (mask & kTPM_TimeOverflowInterruptEnable) - { - base->SC |= TPM_SC_TOIE_MASK; - } - - /* Enable the channel interrupts */ - while (chnlInterrupts) - { - if (chnlInterrupts & 0x1) - { - base->CONTROLS[chnlNumber].CnSC |= TPM_CnSC_CHIE_MASK; - } - chnlNumber++; - chnlInterrupts = chnlInterrupts >> 1U; - } -} - -void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask) -{ - uint32_t chnlInterrupts = (mask & 0xFF); - uint8_t chnlNumber = 0; - - /* Disable the timer overflow interrupt */ - if (mask & kTPM_TimeOverflowInterruptEnable) - { - base->SC &= ~TPM_SC_TOIE_MASK; - } - - /* Disable the channel interrupts */ - while (chnlInterrupts) - { - if (chnlInterrupts & 0x1) - { - base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHIE_MASK; - } - chnlNumber++; - chnlInterrupts = chnlInterrupts >> 1U; - } -} - -uint32_t TPM_GetEnabledInterrupts(TPM_Type *base) -{ - uint32_t enabledInterrupts = 0; - int8_t chnlCount = FSL_FEATURE_TPM_CHANNEL_COUNTn(base); - - /* The CHANNEL_COUNT macro returns -1 if it cannot match the TPM instance */ - assert(chnlCount != -1); - - /* Check if timer overflow interrupt is enabled */ - if (base->SC & TPM_SC_TOIE_MASK) - { - enabledInterrupts |= kTPM_TimeOverflowInterruptEnable; - } - - /* Check if the channel interrupts are enabled */ - while (chnlCount > 0) - { - chnlCount--; - if (base->CONTROLS[chnlCount].CnSC & TPM_CnSC_CHIE_MASK) - { - enabledInterrupts |= (1U << chnlCount); - } - } - - return enabledInterrupts; -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_tpm.h b/third_party/nxp/MKW41Z4/drivers/fsl_tpm.h deleted file mode 100644 index a1694b37d..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_tpm.h +++ /dev/null @@ -1,629 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_TPM_H_ -#define _FSL_TPM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup tpm - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ -/*@}*/ - -/*! - * @brief List of TPM channels. - * @note Actual number of available channels is SoC dependent - */ -typedef enum _tpm_chnl -{ - kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/ - kTPM_Chnl_1, /*!< TPM channel number 1 */ - kTPM_Chnl_2, /*!< TPM channel number 2 */ - kTPM_Chnl_3, /*!< TPM channel number 3 */ - kTPM_Chnl_4, /*!< TPM channel number 4 */ - kTPM_Chnl_5, /*!< TPM channel number 5 */ - kTPM_Chnl_6, /*!< TPM channel number 6 */ - kTPM_Chnl_7 /*!< TPM channel number 7 */ -} tpm_chnl_t; - -/*! @brief TPM PWM operation modes */ -typedef enum _tpm_pwm_mode -{ - kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */ - kTPM_CenterAlignedPwm, /*!< Center aligned PWM */ -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - kTPM_CombinedPwm /*!< Combined PWM */ -#endif -} tpm_pwm_mode_t; - -/*! @brief TPM PWM output pulse mode: high-true, low-true or no output */ -typedef enum _tpm_pwm_level_select -{ - kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */ - kTPM_LowTrue, /*!< Low true pulses */ - kTPM_HighTrue /*!< High true pulses */ -} tpm_pwm_level_select_t; - -/*! @brief Options to configure a TPM channel's PWM signal */ -typedef struct _tpm_chnl_pwm_signal_param -{ - tpm_chnl_t chnlNumber; /*!< TPM channel to configure. - In combined mode (available in some SoC's, this represents the - channel pair number */ - tpm_pwm_level_select_t level; /*!< PWM output active level select */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0=inactive signal(0% duty cycle)... - 100=always active signal (100% duty cycle)*/ -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM. - Specifies the delay to the first edge in a PWM period. - If unsure, leave as 0; Should be specified as - percentage of the PWM period */ -#endif -} tpm_chnl_pwm_signal_param_t; - -/*! - * @brief Trigger options available. - * - * This is used for both internal & external trigger sources (external option available in certain SoC's) - * - * @note The actual trigger options available is SoC-specific. - */ -typedef enum _tpm_trigger_select -{ - kTPM_Trigger_Select_0 = 0U, - kTPM_Trigger_Select_1, - kTPM_Trigger_Select_2, - kTPM_Trigger_Select_3, - kTPM_Trigger_Select_4, - kTPM_Trigger_Select_5, - kTPM_Trigger_Select_6, - kTPM_Trigger_Select_7, - kTPM_Trigger_Select_8, - kTPM_Trigger_Select_9, - kTPM_Trigger_Select_10, - kTPM_Trigger_Select_11, - kTPM_Trigger_Select_12, - kTPM_Trigger_Select_13, - kTPM_Trigger_Select_14, - kTPM_Trigger_Select_15 -} tpm_trigger_select_t; - -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION -/*! - * @brief Trigger source options available - * - * @note This selection is available only on some SoC's. For SoC's without this selection, the only - * trigger source available is internal triger. - */ -typedef enum _tpm_trigger_source -{ - kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */ - kTPM_TriggerSource_Internal /*!< Use internal trigger */ -} tpm_trigger_source_t; -#endif - -/*! @brief TPM output compare modes */ -typedef enum _tpm_output_compare_mode -{ - kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ - kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ - kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */ - kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */ - kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */ - kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */ -} tpm_output_compare_mode_t; - -/*! @brief TPM input capture edge */ -typedef enum _tpm_input_capture_edge -{ - kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */ - kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */ - kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ -} tpm_input_capture_edge_t; - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE -/*! - * @brief TPM dual edge capture parameters - * - * @note This mode is available only on some SoC's. - */ -typedef struct _tpm_dual_edge_capture_param -{ - bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored; - false: Use channel n input, channel n+1 input is ignored */ - tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ - tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ -} tpm_dual_edge_capture_param_t; -#endif - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL -/*! - * @brief TPM quadrature decode modes - * - * @note This mode is available only on some SoC's. - */ -typedef enum _tpm_quad_decode_mode -{ - kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ - kTPM_QuadCountAndDir /*!< Count and direction encoding mode */ -} tpm_quad_decode_mode_t; - -/*! @brief TPM quadrature phase polarities */ -typedef enum _tpm_phase_polarity -{ - kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ - kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */ -} tpm_phase_polarity_t; - -/*! @brief TPM quadrature decode phase parameters */ -typedef struct _tpm_phase_param -{ - uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */ - tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */ -} tpm_phase_params_t; -#endif - -/*! @brief TPM clock source selection*/ -typedef enum _tpm_clock_source -{ - kTPM_SystemClock = 1U, /*!< System clock */ - kTPM_ExternalClock /*!< External clock */ -} tpm_clock_source_t; - -/*! @brief TPM prescale value selection for the clock source*/ -typedef enum _tpm_clock_prescale -{ - kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ - kTPM_Prescale_Divide_2, /*!< Divide by 2 */ - kTPM_Prescale_Divide_4, /*!< Divide by 4 */ - kTPM_Prescale_Divide_8, /*!< Divide by 8 */ - kTPM_Prescale_Divide_16, /*!< Divide by 16 */ - kTPM_Prescale_Divide_32, /*!< Divide by 32 */ - kTPM_Prescale_Divide_64, /*!< Divide by 64 */ - kTPM_Prescale_Divide_128 /*!< Divide by 128 */ -} tpm_clock_prescale_t; - -/*! - * @brief TPM config structure - * - * This structure holds the configuration settings for the TPM peripheral. To initialize this - * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _tpm_config -{ - tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */ - bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled; - false: disabled */ - tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */ -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */ -#endif - bool enableDoze; /*!< true: TPM counter is paused in doze mode; - false: TPM counter continues in doze mode */ - bool enableDebugMode; /*!< true: TPM counter continues in debug mode; - false: TPM counter is paused in debug mode */ - bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger; - false: TPM counter not reloaded */ - bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow; - false: TPM counter continues running after overflow */ - bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected; - false: TPM counter starts immediately */ -#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted; - false: TPM counter continues running */ -#endif -} tpm_config_t; - -/*! @brief List of TPM interrupts */ -typedef enum _tpm_interrupt_enable -{ - kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/ - kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/ - kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/ - kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/ - kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/ - kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/ - kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/ - kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/ - kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/ -} tpm_interrupt_enable_t; - -/*! @brief List of TPM flags */ -typedef enum _tpm_status_flags -{ - kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */ - kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */ - kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */ - kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */ - kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */ - kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */ - kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */ - kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */ - kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */ -} tpm_status_flags_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the TPM clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the TPM driver. - * - * @param base TPM peripheral base address - * @param config Pointer to user's TPM config structure. - */ -void TPM_Init(TPM_Type *base, const tpm_config_t *config); - -/*! - * @brief Stops the counter and gates the TPM clock - * - * @param base TPM peripheral base address - */ -void TPM_Deinit(TPM_Type *base); - -/*! - * @brief Fill in the TPM config struct with the default settings - * - * The default values are: - * @code - * config->prescale = kTPM_Prescale_Divide_1; - * config->useGlobalTimeBase = false; - * config->dozeEnable = false; - * config->dbgMode = false; - * config->enableReloadOnTrigger = false; - * config->enableStopOnOverflow = false; - * config->enableStartOnTrigger = false; - *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - * config->enablePauseOnTrigger = false; - *#endif - * config->triggerSelect = kTPM_Trigger_Select_0; - *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - * config->triggerSource = kTPM_TriggerSource_External; - *#endif - * @endcode - * @param config Pointer to user's TPM config structure. - */ -void TPM_GetDefaultConfig(tpm_config_t *config); - -/*! @}*/ - -/*! - * @name Channel mode operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters - * - * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this - * function to configure all the TPM channels that will be used to output a PWM signal - * - * @param base TPM peripheral base address - * @param chnlParams Array of PWM channel parameters to configure the channel(s) - * @param numOfChnls Number of channels to configure, this should be the size of the array passed in - * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz TPM counter clock in Hz - * - * @return kStatus_Success if the PWM setup was successful, - * kStatus_Error on failure - */ -status_t TPM_SetupPwm(TPM_Type *base, - const tpm_chnl_pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - tpm_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz); - -/*! - * @brief Update the duty cycle of an active PWM signal - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number. In combined mode, this represents - * the channel pair number - * @param currentPwmMode The current PWM mode set during PWM setup - * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 - * 0=inactive signal(0% duty cycle)... - * 100=active signal (100% duty cycle) - */ -void TPM_UpdatePwmDutycycle(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_pwm_mode_t currentPwmMode, - uint8_t dutyCyclePercent); - -/*! - * @brief Update the edge level selection for a channel - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number - * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11. - * See the appropriate SoC reference manual for details about this field. - */ -void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level); - -/*! - * @brief Enables capturing an input signal on the channel using the function parameters. - * - * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into - * the CnV register. The user has to read the CnV register separately to get this value. - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number - * @param captureMode Specifies which edge to capture - */ -void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode); - -/*! - * @brief Configures the TPM to generate timed pulses. - * - * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel - * output is changed based on what is specified in the compareMode argument. - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number - * @param compareMode Action to take on the channel output when the compare condition is met - * @param compareValue Value to be programmed in the CnV register. - */ -void TPM_SetupOutputCompare(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_output_compare_mode_t compareMode, - uint32_t compareValue); - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE -/*! - * @brief Configures the dual edge capture mode of the TPM. - * - * This function allows to measure a pulse width of the signal on the input of channel of a - * channel pair. The filter function is disabled if the filterVal argument passed is zero. - * - * @param base TPM peripheral base address - * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3 - * @param edgeParam Sets up the dual edge capture function - * @param filterValue Filter value, specify 0 to disable filter. - */ -void TPM_SetupDualEdgeCapture(TPM_Type *base, - tpm_chnl_t chnlPairNumber, - const tpm_dual_edge_capture_param_t *edgeParam, - uint32_t filterValue); -#endif - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL -/*! - * @brief Configures the parameters and activates the quadrature decode mode. - * - * @param base TPM peripheral base address - * @param phaseAParams Phase A configuration parameters - * @param phaseBParams Phase B configuration parameters - * @param quadMode Selects encoding mode used in quadrature decoder mode - */ -void TPM_SetupQuadDecode(TPM_Type *base, - const tpm_phase_params_t *phaseAParams, - const tpm_phase_params_t *phaseBParams, - tpm_quad_decode_mode_t quadMode); -#endif - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected TPM interrupts. - * - * @param base TPM peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::tpm_interrupt_enable_t - */ -void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask); - -/*! - * @brief Disables the selected TPM interrupts. - * - * @param base TPM peripheral base address - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::tpm_interrupt_enable_t - */ -void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask); - -/*! - * @brief Gets the enabled TPM interrupts. - * - * @param base TPM peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::tpm_interrupt_enable_t - */ -uint32_t TPM_GetEnabledInterrupts(TPM_Type *base); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the TPM status flags - * - * @param base TPM peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::tpm_status_flags_t - */ -static inline uint32_t TPM_GetStatusFlags(TPM_Type *base) -{ - return base->STATUS; -} - -/*! - * @brief Clears the TPM status flags - * - * @param base TPM peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::tpm_status_flags_t - */ -static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask) -{ - /* Clear the status flags */ - base->STATUS = mask; -} - -/*! @}*/ - -/*! - * @name Read and write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of ticks. - * - * Timers counts from 0 until it equals the count value set here. The count value is written to - * the MOD register. - * - * @note - * 1. This API allows the user to use the TPM module as a timer. Do not mix usage - * of this API with TPM's PWM setup API's. - * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks. - * - * @param base TPM peripheral base address - * @param ticks A timer period in units of ticks, which should be equal or greater than 1. - */ -static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks) -{ - base->MOD = ticks; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value in a range from 0 to a - * timer period. - * - * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. - * - * @param base TPM peripheral base address - * - * @return The current counter value in ticks - */ -static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base) -{ - return (uint32_t)((base->CNT & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT); -} - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the TPM counter. - * - * - * @param base TPM peripheral base address - * @param clockSource TPM clock source; once clock source is set the counter will start running - */ -static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource) -{ - uint32_t reg = base->SC; - - reg &= ~(TPM_SC_CMOD_MASK); - reg |= TPM_SC_CMOD(clockSource); - base->SC = reg; -} - -/*! - * @brief Stops the TPM counter. - * - * @param base TPM peripheral base address - */ -static inline void TPM_StopTimer(TPM_Type *base) -{ - /* Set clock source to none to disable counter */ - base->SC &= ~(TPM_SC_CMOD_MASK); - - /* Wait till this reads as zero acknowledging the counter is disabled */ - while (base->SC & TPM_SC_CMOD_MASK) - { - } -} - -/*! @}*/ - -#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL -/*! - * @brief Performs a software reset on the TPM module. - * - * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.. - * - * @note TPM software reset is available on certain SoC's only - * - * @param base TPM peripheral base address - */ -static inline void TPM_Reset(TPM_Type *base) -{ - base->GLOBAL |= TPM_GLOBAL_RST_MASK; - base->GLOBAL &= ~TPM_GLOBAL_RST_MASK; -} -#endif - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_TPM_H_ */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_trng.c b/third_party/nxp/MKW41Z4/drivers/fsl_trng.c deleted file mode 100644 index e460bb607..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_trng.c +++ /dev/null @@ -1,1650 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_trng.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/******************************************************************************* - * Definitions - *******************************************************************************/ -/* Default values for user configuration structure.*/ -#if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ - defined(MCIMX7U5_M4_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8 -#elif(defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ - defined(KL82Z7_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4 -#elif defined(K81F25615_SERIES) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2 -#else -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0 -#endif - -#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 -#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200 -#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500 -#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63 -#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1 -#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34 - -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384 -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912 -#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467) -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 25600 -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600 - -/*! @brief TRNG work mode */ -typedef enum _trng_work_mode -{ - kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ - kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ -} trng_work_mode_t; - -/*! @brief TRNG statistical check type*/ -typedef enum _trng_statistical_check -{ - kTRNG_StatisticalCheckMonobit = - 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */ - kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during - entropy generation. */ - kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */ - kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */ -} trng_statistical_check_t; - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ -/*! - * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW) - * - * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation, - * the RTY_CT value indicates the number of times a retry should occur before - * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This - * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing - * the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */ -#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT) - -/*! @brief Set the RTY_CT field to a new value. */ -#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCML - RNG Statistical Check Monobit Limit Register - ******************************************************************************/ -/*! - * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW) - * - * Reset value: 0x010C0568U - * - * The RNG Statistical Check Monobit Limit Register defines the allowable - * maximum and minimum number of ones/zero detected during entropy generation. To pass - * the test, the number of ones/zeroes generated must be less than the programmed - * maximum value, and the number of ones/zeroes generated must be greater than - * (maximum - range). If this test fails, the Retry Counter in SCMISC will be - * decremented, and a retry will occur if the Retry Count has not reached zero. If - * the Retry Count has reached zero, an error will be generated. Note that this - * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, - * this offset is used as SCMC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCML register - */ -/*@{*/ -#define TRNG_SCML_REG(base) ((base)->SCML) -#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base)) -#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) -#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW) - * - * Monobit Maximum Limit. Defines the maximum allowable count taken during - * entropy generation. The number of ones/zeroes detected during entropy generation - * must be less than MONO_MAX, else a retry or error will occur. This register is - * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */ -#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT) - -/*! @brief Set the MONO_MAX field to a new value. */ -#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW) - * - * Monobit Range. The number of ones/zeroes detected during entropy generation - * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur. - * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */ -#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT) - -/*! @brief Set the MONO_RNG field to a new value. */ -#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW) - * - * Reset value: 0x00B20195U - * - * The RNG Statistical Check Run Length 1 Limit Register defines the allowable - * maximum and minimum number of runs of length 1 detected during entropy - * generation. To pass the test, the number of runs of length 1 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 1 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR1L register - */ -/*@{*/ -#define TRNG_SCR1L_REG(base) ((base)->SCR1L) -#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base)) -#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) -#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW) - * - * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 1 detected during entropy generation must be less than RUN1_MAX, else a - * retry or error will occur. This register is cleared to 01E5h (decimal 485) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */ -#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT) - -/*! @brief Set the RUN1_MAX field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW) - * - * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1) - * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a - * retry or error will occur. This register is cleared to 0102h (decimal 258) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */ -#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT) - -/*! @brief Set the RUN1_RNG field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW) - * - * Reset value: 0x007A00DCU - * - * The RNG Statistical Check Run Length 2 Limit Register defines the allowable - * maximum and minimum number of runs of length 2 detected during entropy - * generation. To pass the test, the number of runs of length 2 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 2 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR2L register - */ -/*@{*/ -#define TRNG_SCR2L_REG(base) ((base)->SCR2L) -#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base)) -#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) -#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR2L bitfields - */ - -/*! - * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW) - * - * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 2 detected during entropy generation must be less than RUN2_MAX, else a - * retry or error will occur. This register is cleared to 00DCh (decimal 220) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */ -#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT) - -/*! @brief Set the RUN2_MAX field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW) - * - * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1) - * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a - * retry or error will occur. This register is cleared to 007Ah (decimal 122) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */ -#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT) - -/*! @brief Set the RUN2_RNG field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW) - * - * Reset value: 0x0058007DU - * - * The RNG Statistical Check Run Length 3 Limit Register defines the allowable - * maximum and minimum number of runs of length 3 detected during entropy - * generation. To pass the test, the number of runs of length 3 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 3 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR3L register - */ -/*@{*/ -#define TRNG_SCR3L_REG(base) ((base)->SCR3L) -#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base)) -#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value)) -#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR3L bitfields - */ - -/*! - * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW) - * - * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 3 detected during entropy generation must be less than RUN3_MAX, else a - * retry or error will occur. This register is cleared to 007Dh (decimal 125) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */ -#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT) - -/*! @brief Set the RUN3_MAX field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW) - * - * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1) - * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a - * retry or error will occur. This register is cleared to 0058h (decimal 88) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */ -#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT) - -/*! @brief Set the RUN3_RNG field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW) - * - * Reset value: 0x0040004BU - * - * The RNG Statistical Check Run Length 4 Limit Register defines the allowable - * maximum and minimum number of runs of length 4 detected during entropy - * generation. To pass the test, the number of runs of length 4 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 4 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR4L register - */ -/*@{*/ -#define TRNG_SCR4L_REG(base) ((base)->SCR4L) -#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base)) -#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value)) -#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR4L bitfields - */ - -/*! - * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW) - * - * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 4 detected during entropy generation must be less than RUN4_MAX, else a - * retry or error will occur. This register is cleared to 004Bh (decimal 75) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */ -#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT) - -/*! @brief Set the RUN4_MAX field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW) - * - * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1) - * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a - * retry or error will occur. This register is cleared to 0040h (decimal 64) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */ -#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT) - -/*! @brief Set the RUN4_RNG field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 5 Limit Register defines the allowable - * maximum and minimum number of runs of length 5 detected during entropy - * generation. To pass the test, the number of runs of length 5 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 5 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR5L register - */ -/*@{*/ -#define TRNG_SCR5L_REG(base) ((base)->SCR5L) -#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base)) -#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value)) -#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR5L bitfields - */ - -/*! - * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW) - * - * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 5 detected during entropy generation must be less than RUN5_MAX, else a - * retry or error will occur. This register is cleared to 002Fh (decimal 47) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */ -#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT) - -/*! @brief Set the RUN5_MAX field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW) - * - * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1) - * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a - * retry or error will occur. This register is cleared to 002Eh (decimal 46) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */ -#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT) - -/*! @brief Set the RUN5_RNG field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable - * maximum and minimum number of runs of length 6 or more detected during entropy - * generation. To pass the test, the number of runs of length 6 or more (for - * samples of both 0 and 1) must be less than the programmed maximum value, and the - * number of runs of length 6 or more must be greater than (maximum - range). If - * this test fails, the Retry Counter in SCMISC will be decremented, and a retry - * will occur if the Retry Count has not reached zero. If the Retry Count has - * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is - * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is - * used as SCR6PC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR6PL register - */ -/*@{*/ -#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL) -#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base)) -#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value)) -#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR6PL bitfields - */ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW) - * - * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6 - * or more (for both 0 and 1) detected during entropy generation. The number of - * runs of length 6 or more detected during entropy generation must be less than - * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh - * (decimal 47) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */ -#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT) - -/*! @brief Set the RUN6P_MAX field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW) - * - * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and - * 1) detected during entropy generation must be greater than RUN6P_MAX - - * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh - * (decimal 46) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */ -#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT) - -/*! @brief Set the RUN6P_RNG field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_PKRMAX - RNG Poker Maximum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW) - * - * Reset value: 0x00006920U - * - * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during - * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is - * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used - * as the PKRSQ readback register. - */ -/*! - * @name Constants and macros for entire TRNG_PKRMAX register - */ -/*@{*/ -#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX) -#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base)) -#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value)) -#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRMAX bitfields - */ - -/*! - * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW) - * - * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is - * run which requires a maximum and minimum limit. The maximum allowable result is - * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if - * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by - * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers - * combined are used to define the minimum allowable Poker result, which is PKR_MAX - - * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used - * to read the Poker Test Square Calculation result in register PKRSQ, as defined - * in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */ -#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT) - -/*! @brief Set the PKR_MAX field to a new value. */ -#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \ - (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_PKRRNG - RNG Poker Range Register - ******************************************************************************/ - -/*! - * @brief TRNG_PKRRNG - RNG Poker Range Register (RW) - * - * Reset value: 0x000009A3U - * - * The RNG Poker Range Register defines the difference between the TRNG Poker - * Maximum Limit and the minimum limit. These limits are used during the TRNG - * Statistical Check Poker Test. - */ -/*! - * @name Constants and macros for entire TRNG_PKRRNG register - */ -/*@{*/ -#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG) -#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base)) -#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value)) -#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRRNG bitfields - */ - -/*! - * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW) - * - * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which - * requires a maximum and minimum limit. The maximum is programmed in the - * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG - * value from the programmed maximum value. This field is writable only if - * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is - * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that - * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */ -#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT) - -/*! @brief Set the PKR_RNG field to a new value. */ -#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \ - (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW) - * - * Reset value: 0x00006400U - * - * The RNG Frequency Count Maximum Limit Register defines the maximum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is greater than this programmed maximum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note - * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as FRQCNT readback register. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMAX register - */ -/*@{*/ -#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX) -#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base)) -#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value)) -#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMAX bitfields - */ - -/*! - * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW) - * - * Frequency Counter Maximum Limit. Defines the maximum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1. - * Note that if MCTL[PRGM] bit is 0, this register address is used to read the - * Frequency Count result in register FRQCNT, as defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */ -#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT) - -/*! @brief Set the FRQ_MAX field to a new value. */ -#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \ - (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW) - * - * Reset value: 0x00000640U - * - * The RNG Frequency Count Minimum Limit Register defines the minimum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is less than this programmed minimum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMIN register - */ -/*@{*/ -#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN) -#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base)) -#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value)) -#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMIN bitfields - */ - -/*! - * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW) - * - * Frequency Count Minimum Limit. Defines the minimum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64 - * by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */ -#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT) - -/*! @brief Set the FRQ_MIN field to a new value. */ -#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \ - (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_MCTL - RNG Miscellaneous Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW) - * - * Reset value: 0x00012001U - * - * This register is intended to be used for programming, configuring and testing - * the RNG. It is the main register to read/write, in order to enable Entropy - * generation, to stop entropy generation and to block access to entropy registers. - * This is done via the special TRNG_ACC and PRGM bits below. The RNG - * Miscellaneous Control Register is a read/write register used to control the RNG's True - * Random Number Generator (TRNG) access, operation and test. Note that in many - * cases two RNG registers share the same address, and a particular register at the - * shared address is selected based upon the value in the PRGM field of the MCTL - * register. - */ -/*! - * @name Constants and macros for entire TRNG_MCTL register - */ -/*@{*/ -#define TRNG_MCTL_REG(base) ((base)->MCTL) -#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base)) -#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value)) -#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW) - * - * Force System Clock. If set, the system clock is used to operate the TRNG, - * instead of the ring oscillator. This is for test use only, and indeterminate - * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is - * being written to 1 simultaneously to writing this bit. This bit is cleared by - * writing the RST_DEF bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */ -#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT) - -/*! @brief Set the FOR_SCLK field to a new value. */ -#define TRNG_WR_MCTL_FOR_SCLK(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW) - * - * Oscillator Divide. Determines the amount of dividing done to the ring - * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is - * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This - * field is cleared to 00 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use ring oscillator with no divide - * - 0b01 - use ring oscillator divided-by-2 - * - 0b10 - use ring oscillator divided-by-4 - * - 0b11 - use ring oscillator divided-by-8 - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */ -#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT) - -/*! @brief Set the OSC_DIV field to a new value. */ -#define TRNG_WR_MCTL_OSC_DIV(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW) - * - * Sample Mode. Determines the method of sampling the ring oscillator while - * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM - * bit is being written to 1 simultaneously with writing this field. This field - * is cleared to 01 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical - * Checker - * - 0b01 - use raw data into both Entropy shifter and Statistical Checker - * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into - * Statistical Checker - * - 0b11 - reserved. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */ -#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT) - -/*! @brief Set the SAMP_MODE field to a new value. */ -#define TRNG_WR_MCTL_SAMP_MODE(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field PRGM[16] (RW) - * - * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode, - * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is - * in Program Mode. Note that different RNG registers are accessible at the same - * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG - * register descriptions. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_PRGM field. */ -#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT) - -/*! @brief Set the PRGM field to a new value. */ -#define TRNG_WR_MCTL_PRGM(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field RST_DEF[6] (WO) - * - * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and - * bits within registers, to their default state. This bit is writable only if PRGM - * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this - * bit. Reading this bit always produces a 0. - */ -/*@{*/ -/*! @brief Set the RST_DEF field to a new value. */ -#define TRNG_WR_MCTL_RST_DEF(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW) - * - * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy - * value that can be read via the ENT0-ENT15 registers. The Entropy value may be - * read once the ENT VAL bit is asserted. Also see ENTa register descriptions - * (For a = 0 to 15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */ -#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT) - -/*! @brief Set the TRNG_ACC field to a new value. */ -#define TRNG_WR_MCTL_TRNG_ACC(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO) - * - * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before - * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG - * free-running ring oscillator whenever new entropy is being generated and turns off the - * ring oscillator when entropy generation is complete. If the RNG clock is - * stopped while the TRNG ring oscillator is running, the oscillator will continue - * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG - * ring oscillator is not running. and therefore it is ok to stop the RNG clock. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */ -#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ENT_VAL[10] (RO) - * - * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then - * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0 - * through ENT14 should be read before reading ENT15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */ -#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ERR[12] (W1C) - * - * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear - * errors. Writing 0 has no effect. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ERR field. */ -#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT) - -/*! @brief Set the ERR field to a new value. */ -#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SDCTL - RNG Seed Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_SDCTL - RNG Seed Control Register (RW) - * - * Reset value: 0x0C8009C4U - * - * The RNG Seed Control Register contains two fields. One field defines the - * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field - * indicates the number of samples that will taken during each TRNG Entropy - * generation (SAMP_SIZE). - */ -/*! - * @name Constants and macros for entire TRNG_SDCTL register - */ -/*@{*/ -#define TRNG_SDCTL_REG(base) ((base)->SDCTL) -#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base)) -#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value)) -#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SDCTL bitfields - */ - -/*! - * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW) - * - * Sample Size. Defines the total number of Entropy samples that will be taken - * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h - * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */ -#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT) - -/*! @brief Set the SAMP_SIZE field to a new value. */ -#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \ - (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value))) -/*@}*/ - -/*! - * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW) - * - * Entropy Delay. Defines the length (in system clocks) of each Entropy sample - * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read - * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */ -#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT) - -/*! @brief Set the ENT_DLY field to a new value. */ -#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SBLIM - RNG Sparse Bit Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW) - * - * Reset value: 0x0000003FU - * - * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is - * selected during Entropy Generation. It defines the maximum number of consecutive Von - * Neumann samples which may be discarded before an error is generated. Note - * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as TOTSAM readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SBLIM register - */ -/*@{*/ -#define TRNG_SBLIM_REG(base) ((base)->SBLIM) -#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base)) -#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value)) -#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SBLIM bitfields - */ - -/*! - * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW) - * - * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE], - * samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. The Sparse Bit Limit defines the maximum number of - * consecutive samples that may be discarded before an error is generated. This field - * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by - * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this - * register address is used to read the Total Samples count in register TOTSAM, as - * defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */ -#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT) - -/*! @brief Set the SB_LIM field to a new value. */ -#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW) - * - * Reset value: 0x0001001FU - * - * The RNG Statistical Check Miscellaneous Register contains the Long Run - * Maximum Limit value and the Retry Count value. This register is accessible only when - * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot - * be written. - */ -/*! - * @name Constants and macros for entire TRNG_SCMISC register - */ -/*@{*/ -#define TRNG_SCMISC_REG(base) ((base)->SCMISC) -#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base)) -#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value)) -#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCMISC bitfields - */ - -/*! - * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW) - * - * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive - * samples of all 1, or all 0, that is allowed during the Entropy generation. - * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes - * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */ -#define TRNG_RD_SCMISC_LRUN_MAX(base) \ - ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT) - -/*! @brief Set the LRUN_MAX field to a new value. */ -#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \ - (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_ENT - RNG TRNG Entropy Read Register - ******************************************************************************/ - -/*! - * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO) - * - * Reset value: 0x00000000U - * - * The RNG TRNG can be programmed to generate an entropy value that is readable - * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the - * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this - * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value. - * Note that once ENT15 is read, the entropy value will be cleared and a new - * value will begin generation, so it is important that ENT15 be read last. These - * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1 - * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read. - */ -/*! - * @name Constants and macros for entire TRNG_ENT register - */ -/*@{*/ -#define TRNG_ENT_REG(base, index) ((base)->ENT[index]) -#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index)) -/*@}*/ - -/******************************************************************************* - * TRNG_SEC_CFG - RNG Security Configuration Register - ******************************************************************************/ - -/*! - * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW) - * - * Reset value: 0x00000000U - * - * The RNG Security Configuration Register is a read/write register used to - * control the test mode, programmability and state modes of the RNG. Many bits are - * place holders for this version. More configurability will be added here. Clears - * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0 - * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use - * these registers, if hard coded. - */ -/*! - * @name Constants and macros for entire TRNG_SEC_CFG register - */ -/*@{*/ -#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG) -#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base)) -#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value)) -#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW) - * - * If set the TRNG registers cannot be programmed. That is, regardless of the - * TRNG access mode in the SA-TRNG Miscellaneous Control Register. - * - * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous - * Control Register's access mode bit. - * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents - * TRNG register programming. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */ -#define TRNG_RD_SEC_CFG_NO_PRGM(base) \ - ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT) - -/*! @brief Set the NO_PRGM field to a new value. */ -#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \ - (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value))) -/*@}*/ - -/*! @brief Array to map TRNG instance number to base pointer. */ -static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clock array name */ -static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig); -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count); -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit); -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index); -static uint32_t trng_GetInstance(TRNG_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t trng_GetInstance(TRNG_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++) - { - if (s_trngBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_trngBases)); - - return instance; -} - -/*FUNCTION********************************************************************* - * - * Function Name : TRNG_InitUserConfigDefault - * Description : Initializes user configuration structure to default settings. - * - *END*************************************************************************/ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) -{ - status_t result; - - if (userConfig != 0) - { - userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK; - userConfig->clockMode = kTRNG_ClockModeRingOscillator; - userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; - userConfig->sampleMode = kTRNG_SampleModeRaw; - userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; - userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; - userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - - /* Statistical Check Parameters.*/ - userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; - userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT; - - userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; - userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; - userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; - userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; - userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; - userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; - userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; - userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; - userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; - userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; - userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; - userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; - userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; - userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; - userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; - userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; - userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM; - userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM; - - result = kStatus_Success; - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -/*! - * @brief Sets the TRNG retry count. - * - * This function sets the retry counter which defines the number of times a - * statistical check may fails during the TRNG Entropy Generation before - * generating an error. -*/ -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count) -{ - status_t status; - - if ((retry_count >= 1u) && (retry_count <= 15u)) - { - /* Set retry count.*/ - TRNG_WR_SCMISC_RTY_CT(base, retry_count); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical check limits. - * - * This function is used to set minimum and maximum limits of statistical checks. - * - */ -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit) -{ - uint32_t range; - status_t status = kStatus_Success; - - if (limit && (limit->maximum > limit->minimum)) - { - range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/ - - switch (statistical_check) - { - case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during - entropy generation. */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffu)) - { - TRNG_WR_SCML_MONO_MAX(base, limit->maximum); - TRNG_WR_SCML_MONO_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected - during entropy generation. */ - if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu)) - { - TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum); - TRNG_WR_SCR1L_RUN1_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected - during entropy generation. */ - if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu)) - { - TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum); - TRNG_WR_SCR2L_RUN2_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected - during entropy generation. */ - if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu)) - { - TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum); - TRNG_WR_SCR3L_RUN3_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected - during entropy generation. */ - if ((range <= 0xfffu) && (limit->maximum <= 0xfffu)) - { - TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum); - TRNG_WR_SCR4L_RUN4_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected - during entropy generation. */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum); - TRNG_WR_SCR5L_RUN5_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected - during entropy generation */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum); - TRNG_WR_SCR6PL_RUN6P_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during - entropy generation . */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu)) - { - TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum); - TRNG_WR_PKRRNG_PKR_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency - count during entropy generation . */ - if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu)) - { - TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum); - TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum); - } - else - { - status = kStatus_InvalidArgument; - } - break; - default: - status = kStatus_InvalidArgument; - break; - } - } - - return status; -} - -/*FUNCTION********************************************************************* - * - * Function Name : trng_ApplyUserConfig - * Description : Apply user configuration settings to TRNG module. - * - *END*************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t status; - - if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, - &userConfig->runBit6PlusLimit)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, - &userConfig->frequencyCountLimit)) == kStatus_Success)) - { - TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); - TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); - TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); - TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); - TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); - TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); - TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); - } - - return status; -} - -/*! - * @brief Gets a entry data from the TRNG. - * - * This function gets an entropy data from TRNG. - * Entropy data is spread over TRNG_ENT_COUNT registers. - * Read register number is defined by index parameter. -*/ -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) -{ - uint32_t data; - - index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/ - - data = TRNG_RD_ENT(base, index); - - if (index == (TRNG_ENT_COUNT - 1)) - { - /* Dummy read. Defect workaround. - * TRNG could not clear ENT_VAL flag automatically, application - * had to do a dummy reading operation for anyone TRNG register - * to clear it firstly, then to read the RTENT0 to RTENT15 again */ - index = TRNG_RD_ENT(base, 0); - } - - return data; -} - -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t result; - - /* Check input parameters.*/ - if ((base != 0) && (userConfig != 0)) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock gate. */ - CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the registers of TRNG module to reset state. */ - /* Must be in program mode.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); - /* Reset Defaults.*/ - TRNG_WR_MCTL_RST_DEF(base, 1); - - /* Set configuration.*/ - if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success) - { - /* Start entropy generation.*/ - /* Set to Run mode.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun); - /* Enable TRNG Access Mode. To generate an Entropy - * value that can be read via the true0-true15 registers.*/ - TRNG_WR_MCTL_TRNG_ACC(base, 1); - - if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */ - { - TRNG_WR_SEC_CFG_NO_PRGM(base, 1); - } - - result = kStatus_Success; - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -void TRNG_Deinit(TRNG_Type *base) -{ - /* Check input parameters.*/ - if (base) - { - /* Move to program mode. Stop entropy generation.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); - - /* Check before clock stop. - TRNG turns on the TRNG free-running ring oscillator whenever new entropy - is being generated and turns off the ring oscillator when entropy generation - is complete. If the TRNG clock is stopped while the TRNG ring oscillator - is running, the oscillator continues running though the RNG clock. - is stopped. */ - while (TRNG_RD_MCTL_TSTOP_OK(base) == 0) - { - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable Clock*/ - CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } -} - -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Success; - uint32_t random_32; - uint8_t *random_p; - uint32_t random_size; - uint8_t *data_p = (uint8_t *)data; - uint32_t i; - int index = 0; - - /* Check input parameters.*/ - if (base && data && dataSize) - { - do - { - /* Wait for Valid or Error flag*/ - while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0)) - { - } - - /* Check HW error.*/ - if (TRNG_RD_MCTL_ERR(base)) - { - result = kStatus_Fail; /* TRNG module error occurred */ - /* Clear error.*/ - TRNG_WR_MCTL_ERR(base, 1); - break; /* No sense stay here.*/ - } - - /* Read Entropy.*/ - random_32 = trng_ReadEntropy(base, index++); - - random_p = (uint8_t *)&random_32; - - if (dataSize < sizeof(random_32)) - { - random_size = dataSize; - } - else - { - random_size = sizeof(random_32); - } - - for (i = 0U; i < random_size; i++) - { - *data_p++ = *random_p++; - } - - dataSize -= random_size; - } while (dataSize > 0); - - /* Start a new entropy generation. - It is done by reading of the last entropy register.*/ - if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1)) - { - trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1)); - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_trng.h b/third_party/nxp/MKW41Z4/drivers/fsl_trng.h deleted file mode 100644 index 5d349a3c2..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_trng.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_TRNG_DRIVER_H_ -#define _FSL_TRNG_DRIVER_H_ - -#include "fsl_common.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/*! - * @addtogroup trng - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief TRNG driver version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.1 - * - add support for KL8x and KL28Z - * - update default OSCDIV for K81 to divide by 2 - */ -#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief TRNG sample mode. Used by trng_config_t. */ -typedef enum _trng_sample_mode -{ - kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeVonNeumannRaw = - 2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */ -} trng_sample_mode_t; - -/*! @brief TRNG clock mode. Used by trng_config_t. */ -typedef enum _trng_clock_mode -{ - kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */ - kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and - indeterminate results may occur. */ -} trng_clock_mode_t; - -/*! @brief TRNG ring oscillator divide. Used by trng_config_t. */ -typedef enum _trng_ring_osc_div -{ - kTRNG_RingOscDiv0 = 0U, /*!< Ring oscillator with no divide */ - kTRNG_RingOscDiv2 = 1U, /*!< Ring oscillator divided-by-2. */ - kTRNG_RingOscDiv4 = 2U, /*!< Ring oscillator divided-by-4. */ - kTRNG_RingOscDiv8 = 3U /*!< Ring oscillator divided-by-8. */ -} trng_ring_osc_div_t; - -/*! @brief Data structure for definition of statistical check limits. Used by trng_config_t. */ -typedef struct _trng_statistical_check_limit -{ - uint32_t maximum; /*!< Maximum limit.*/ - uint32_t minimum; /*!< Minimum limit.*/ -} trng_statistical_check_limit_t; - -/*! - * @brief Data structure for the TRNG initialization - * - * This structure initializes the TRNG by calling the TRNG_Init() function. - * It contains all TRNG configurations. - */ -typedef struct _trng_user_config -{ - bool lock; /*!< @brief Disable programmability of TRNG registers. */ - trng_clock_mode_t clockMode; /*!< @brief Clock mode used to operate TRNG.*/ - trng_ring_osc_div_t ringOscDiv; /*!< @brief Ring oscillator divide used by TRNG. */ - trng_sample_mode_t sampleMode; /*!< @brief Sample mode of the TRNG ring oscillator. */ - /* Seed Control*/ - uint16_t - entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */ - uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during - Entropy generation. */ - uint16_t - sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of - * consecutive samples that may be discarded before an error is generated. - * This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()). - * Samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. */ - /* Statistical Check Parameters.*/ - uint8_t retryCount; /*!< @brief Retry count. It defines the number of times a statistical check may fails - * during the TRNG Entropy Generation before generating an error. */ - uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0, - * that is allowed during the Entropy generation. */ - trng_statistical_check_limit_t - monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number of ones/zero detected - during entropy generation. */ - trng_statistical_check_limit_t - runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 1 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 2 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 3 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 4 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 5 - detected during entropy generation. */ - trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of - number of runs of length 6 or more detected during entropy - generation. */ - trng_statistical_check_limit_t - pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */ - trng_statistical_check_limit_t - frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of entropy sample frequency - count. */ -} trng_config_t; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the user configuration structure to default values. - * - * This function initializes the configuration structure to default values. The default - * values are as follows. - * @code - * user_config->lock = 0; - * user_config->clockMode = kTRNG_ClockModeRingOscillator; - * user_config->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. - * user_config->sampleMode = kTRNG_SampleModeRaw; - * user_config->entropyDelay = 3200; - * user_config->sampleSize = 2500; - * user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - * user_config->retryCount = 63; - * user_config->longRunMaxLimit = 34; - * user_config->monobitLimit.maximum = 1384; - * user_config->monobitLimit.minimum = 1116; - * user_config->runBit1Limit.maximum = 405; - * user_config->runBit1Limit.minimum = 227; - * user_config->runBit2Limit.maximum = 220; - * user_config->runBit2Limit.minimum = 98; - * user_config->runBit3Limit.maximum = 125; - * user_config->runBit3Limit.minimum = 37; - * user_config->runBit4Limit.maximum = 75; - * user_config->runBit4Limit.minimum = 11; - * user_config->runBit5Limit.maximum = 47; - * user_config->runBit5Limit.minimum = 1; - * user_config->runBit6PlusLimit.maximum = 47; - * user_config->runBit6PlusLimit.minimum = 1; - * user_config->pokerLimit.maximum = 26912; - * user_config->pokerLimit.minimum = 24445; - * user_config->frequencyCountLimit.maximum = 25600; - * user_config->frequencyCountLimit.minimum = 1600; - * @endcode - * - * @param user_config User configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig); - -/*! - * @brief Initializes the TRNG. - * - * This function initializes the TRNG. - * When called, the TRNG entropy generation starts immediately. - * - * @param base TRNG base address - * @param userConfig Pointer to the initialization configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig); - -/*! - * @brief Shuts down the TRNG. - * - * This function shuts down the TRNG. - * - * @param base TRNG base address. - */ -void TRNG_Deinit(TRNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the TRNG. - * - * @param base TRNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ -#endif /*_FSL_TRNG_H_*/ diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.c b/third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.c deleted file mode 100644 index c299c90f6..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_tsi_v4.h" - -void TSI_Init(TSI_Type *base, const tsi_config_t *config) -{ - assert(config != NULL); - - bool is_module_enabled = false; - bool is_int_enabled = false; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Tsi0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - if (base->GENCS & TSI_GENCS_TSIEN_MASK) - { - is_module_enabled = true; - TSI_EnableModule(base, false); - } - if (base->GENCS & TSI_GENCS_TSIIEN_MASK) - { - is_int_enabled = true; - TSI_DisableInterrupts(base, kTSI_GlobalInterruptEnable); - } - - if(config->mode == kTSI_AnalogModeSel_Capacitive) - { - TSI_SetHighThreshold(base, config->thresh); - TSI_SetLowThreshold(base, config->thresl); - TSI_SetElectrodeOSCPrescaler(base, config->prescaler); - TSI_SetReferenceChargeCurrent(base, config->refchrg); - TSI_SetElectrodeChargeCurrent(base, config->extchrg); - TSI_SetNumberOfScans(base, config->nscn); - TSI_SetAnalogMode(base, config->mode); - TSI_SetOscVoltageRails(base, config->dvolt); - } - else /* For noise modes */ - { - TSI_SetHighThreshold(base, config->thresh); - TSI_SetLowThreshold(base, config->thresl); - TSI_SetElectrodeOSCPrescaler(base, config->prescaler); - TSI_SetReferenceChargeCurrent(base, config->refchrg); - TSI_SetNumberOfScans(base, config->nscn); - TSI_SetAnalogMode(base, config->mode); - TSI_SetOscVoltageRails(base, config->dvolt); - TSI_SetElectrodeSeriesResistor(base, config->resistor); - TSI_SetFilterBits(base, config->filter); - } - - if (is_module_enabled) - { - TSI_EnableModule(base, true); - } - if (is_int_enabled) - { - TSI_EnableInterrupts(base, kTSI_GlobalInterruptEnable); - } -} - -void TSI_Deinit(TSI_Type *base) -{ - base->GENCS = 0U; - base->DATA = 0U; - base->TSHD = 0U; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Tsi0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig) -{ - userConfig->thresh = 0U; - userConfig->thresl = 0U; - userConfig->prescaler = kTSI_ElecOscPrescaler_2div; - userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA; - userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA; - userConfig->nscn = kTSI_ConsecutiveScansNumber_5time; - userConfig->mode = kTSI_AnalogModeSel_Capacitive; - userConfig->dvolt = kTSI_OscVolRailsOption_0; -} - -void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig) -{ - userConfig->thresh = 400U; - userConfig->thresl = 0U; - userConfig->prescaler = kTSI_ElecOscPrescaler_2div; - userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA; - userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA; - userConfig->nscn = kTSI_ConsecutiveScansNumber_5time; - userConfig->mode = kTSI_AnalogModeSel_Capacitive; - userConfig->dvolt = kTSI_OscVolRailsOption_0; -} - -void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff) -{ - assert(calBuff != NULL); - - uint8_t i = 0U; - bool is_int_enabled = false; - - if (base->GENCS & TSI_GENCS_TSIIEN_MASK) - { - is_int_enabled = true; - TSI_DisableInterrupts(base, kTSI_GlobalInterruptEnable); - } - for (i = 0U; i < FSL_FEATURE_TSI_CHANNEL_COUNT; i++) - { - TSI_SetMeasuredChannelNumber(base, i); - TSI_StartSoftwareTrigger(base); - while (!(TSI_GetStatusFlags(base) & kTSI_EndOfScanFlag)) - { - } - calBuff->calibratedData[i] = TSI_GetCounter(base); - TSI_ClearStatusFlags(base, kTSI_EndOfScanFlag); - } - if (is_int_enabled) - { - TSI_EnableInterrupts(base, kTSI_GlobalInterruptEnable); - } -} - -void TSI_EnableInterrupts(TSI_Type *base, uint32_t mask) -{ - uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); - - if (mask & kTSI_GlobalInterruptEnable) - { - regValue |= TSI_GENCS_TSIIEN_MASK; - } - if (mask & kTSI_OutOfRangeInterruptEnable) - { - regValue &= (~TSI_GENCS_ESOR_MASK); - } - if (mask & kTSI_EndOfScanInterruptEnable) - { - regValue |= TSI_GENCS_ESOR_MASK; - } - - base->GENCS = regValue; /* write value to register */ -} - -void TSI_DisableInterrupts(TSI_Type *base, uint32_t mask) -{ - uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); - - if (mask & kTSI_GlobalInterruptEnable) - { - regValue &= (~TSI_GENCS_TSIIEN_MASK); - } - if (mask & kTSI_OutOfRangeInterruptEnable) - { - regValue |= TSI_GENCS_ESOR_MASK; - } - if (mask & kTSI_EndOfScanInterruptEnable) - { - regValue &= (~TSI_GENCS_ESOR_MASK); - } - - base->GENCS = regValue; /* write value to register */ -} - -void TSI_ClearStatusFlags(TSI_Type *base, uint32_t mask) -{ - uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK); - - if (mask & kTSI_EndOfScanFlag) - { - regValue |= TSI_GENCS_EOSF_MASK; - } - if (mask & kTSI_OutOfRangeFlag) - { - regValue |= TSI_GENCS_OUTRGF_MASK; - } - - base->GENCS = regValue; /* write value to register */ -} diff --git a/third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.h b/third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.h deleted file mode 100644 index fef5b7a16..000000000 --- a/third_party/nxp/MKW41Z4/drivers/fsl_tsi_v4.h +++ /dev/null @@ -1,706 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_TSI_V4_H_ -#define _FSL_TSI_V4_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup tsi_v4_driver - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief TSI driver version */ -#define FSL_TSI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -/*! @brief TSI status flags macro collection */ -#define ALL_FLAGS_MASK (TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK) - -/*! @brief resistor bit shift in EXTCHRG bit-field */ -#define TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT TSI_GENCS_EXTCHRG_SHIFT - -/*! @brief filter bits shift in EXTCHRG bit-field */ -#define TSI_V4_EXTCHRG_FILTER_BITS_SHIFT (1U + TSI_GENCS_EXTCHRG_SHIFT) - -/*! @brief macro of clearing the resistor bit in EXTCHRG bit-field */ -#define TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR \ - ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (3U << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT))) - -/*! @brief macro of clearing the filter bits in EXTCHRG bit-field */ -#define TSI_V4_EXTCHRG_FILTER_BITS_CLEAR \ - ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (1U << TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT))) - -/*! - * @brief TSI number of scan intervals for each electrode. - * - * These constants define the tsi number of consecutive scans in a TSI instance for each electrode. - */ -typedef enum _tsi_n_consecutive_scans -{ - kTSI_ConsecutiveScansNumber_1time = 0U, /*!< Once per electrode */ - kTSI_ConsecutiveScansNumber_2time = 1U, /*!< Twice per electrode */ - kTSI_ConsecutiveScansNumber_3time = 2U, /*!< 3 times consecutive scan */ - kTSI_ConsecutiveScansNumber_4time = 3U, /*!< 4 times consecutive scan */ - kTSI_ConsecutiveScansNumber_5time = 4U, /*!< 5 times consecutive scan */ - kTSI_ConsecutiveScansNumber_6time = 5U, /*!< 6 times consecutive scan */ - kTSI_ConsecutiveScansNumber_7time = 6U, /*!< 7 times consecutive scan */ - kTSI_ConsecutiveScansNumber_8time = 7U, /*!< 8 times consecutive scan */ - kTSI_ConsecutiveScansNumber_9time = 8U, /*!< 9 times consecutive scan */ - kTSI_ConsecutiveScansNumber_10time = 9U, /*!< 10 times consecutive scan */ - kTSI_ConsecutiveScansNumber_11time = 10U, /*!< 11 times consecutive scan */ - kTSI_ConsecutiveScansNumber_12time = 11U, /*!< 12 times consecutive scan */ - kTSI_ConsecutiveScansNumber_13time = 12U, /*!< 13 times consecutive scan */ - kTSI_ConsecutiveScansNumber_14time = 13U, /*!< 14 times consecutive scan */ - kTSI_ConsecutiveScansNumber_15time = 14U, /*!< 15 times consecutive scan */ - kTSI_ConsecutiveScansNumber_16time = 15U, /*!< 16 times consecutive scan */ - kTSI_ConsecutiveScansNumber_17time = 16U, /*!< 17 times consecutive scan */ - kTSI_ConsecutiveScansNumber_18time = 17U, /*!< 18 times consecutive scan */ - kTSI_ConsecutiveScansNumber_19time = 18U, /*!< 19 times consecutive scan */ - kTSI_ConsecutiveScansNumber_20time = 19U, /*!< 20 times consecutive scan */ - kTSI_ConsecutiveScansNumber_21time = 20U, /*!< 21 times consecutive scan */ - kTSI_ConsecutiveScansNumber_22time = 21U, /*!< 22 times consecutive scan */ - kTSI_ConsecutiveScansNumber_23time = 22U, /*!< 23 times consecutive scan */ - kTSI_ConsecutiveScansNumber_24time = 23U, /*!< 24 times consecutive scan */ - kTSI_ConsecutiveScansNumber_25time = 24U, /*!< 25 times consecutive scan */ - kTSI_ConsecutiveScansNumber_26time = 25U, /*!< 26 times consecutive scan */ - kTSI_ConsecutiveScansNumber_27time = 26U, /*!< 27 times consecutive scan */ - kTSI_ConsecutiveScansNumber_28time = 27U, /*!< 28 times consecutive scan */ - kTSI_ConsecutiveScansNumber_29time = 28U, /*!< 29 times consecutive scan */ - kTSI_ConsecutiveScansNumber_30time = 29U, /*!< 30 times consecutive scan */ - kTSI_ConsecutiveScansNumber_31time = 30U, /*!< 31 times consecutive scan */ - kTSI_ConsecutiveScansNumber_32time = 31U /*!< 32 times consecutive scan */ -} tsi_n_consecutive_scans_t; - -/*! - * @brief TSI electrode oscillator prescaler. - * - * These constants define the TSI electrode oscillator prescaler in a TSI instance. - */ -typedef enum _tsi_electrode_osc_prescaler -{ - kTSI_ElecOscPrescaler_1div = 0U, /*!< Electrode oscillator frequency divided by 1 */ - kTSI_ElecOscPrescaler_2div = 1U, /*!< Electrode oscillator frequency divided by 2 */ - kTSI_ElecOscPrescaler_4div = 2U, /*!< Electrode oscillator frequency divided by 4 */ - kTSI_ElecOscPrescaler_8div = 3U, /*!< Electrode oscillator frequency divided by 8 */ - kTSI_ElecOscPrescaler_16div = 4U, /*!< Electrode oscillator frequency divided by 16 */ - kTSI_ElecOscPrescaler_32div = 5U, /*!< Electrode oscillator frequency divided by 32 */ - kTSI_ElecOscPrescaler_64div = 6U, /*!< Electrode oscillator frequency divided by 64 */ - kTSI_ElecOscPrescaler_128div = 7U /*!< Electrode oscillator frequency divided by 128 */ -} tsi_electrode_osc_prescaler_t; - -/*! - * @brief TSI analog mode select. - * - * Set up TSI analog modes in a TSI instance. - */ -typedef enum _tsi_analog_mode -{ - kTSI_AnalogModeSel_Capacitive = 0U, /*!< Active TSI capacitive sensing mode */ - kTSI_AnalogModeSel_NoiseNoFreqLim = 4U, /*!< Single threshold noise detection mode with no freq. limitation. */ - kTSI_AnalogModeSel_NoiseFreqLim = 8U, /*!< Single threshold noise detection mode with freq. limitation. */ - kTSI_AnalogModeSel_AutoNoise = 12U /*!< Active TSI analog in automatic noise detection mode */ -} tsi_analog_mode_t; - -/*! - * @brief TSI Reference oscillator charge and discharge current select. - * - * These constants define the TSI Reference oscillator charge current select in a TSI (REFCHRG) instance. - */ -typedef enum _tsi_reference_osc_charge_current -{ - kTSI_RefOscChargeCurrent_500nA = 0U, /*!< Reference oscillator charge current is 500 µA */ - kTSI_RefOscChargeCurrent_1uA = 1U, /*!< Reference oscillator charge current is 1 µA */ - kTSI_RefOscChargeCurrent_2uA = 2U, /*!< Reference oscillator charge current is 2 µA */ - kTSI_RefOscChargeCurrent_4uA = 3U, /*!< Reference oscillator charge current is 4 µA */ - kTSI_RefOscChargeCurrent_8uA = 4U, /*!< Reference oscillator charge current is 8 µA */ - kTSI_RefOscChargeCurrent_16uA = 5U, /*!< Reference oscillator charge current is 16 µA */ - kTSI_RefOscChargeCurrent_32uA = 6U, /*!< Reference oscillator charge current is 32 µA */ - kTSI_RefOscChargeCurrent_64uA = 7U /*!< Reference oscillator charge current is 64 µA */ -} tsi_reference_osc_charge_current_t; - -/*! - * @brief TSI oscilator's voltage rails. - * - * These bits indicate the oscillator's voltage rails. - */ -typedef enum _tsi_osc_voltage_rails -{ - kTSI_OscVolRailsOption_0 = 0U, /*!< DVOLT value option 0, the value may differ on different platforms */ - kTSI_OscVolRailsOption_1 = 1U, /*!< DVOLT value option 1, the value may differ on different platforms */ - kTSI_OscVolRailsOption_2 = 2U, /*!< DVOLT value option 2, the value may differ on different platforms */ - kTSI_OscVolRailsOption_3 = 3U /*!< DVOLT value option 3, the value may differ on different platforms */ -} tsi_osc_voltage_rails_t; - -/*! - * @brief TSI External oscillator charge and discharge current select. - * - * These bits indicate the electrode oscillator charge and discharge current value - * in TSI (EXTCHRG) instance. - */ -typedef enum _tsi_external_osc_charge_current -{ - kTSI_ExtOscChargeCurrent_500nA = 0U, /*!< External oscillator charge current is 500 µA */ - kTSI_ExtOscChargeCurrent_1uA = 1U, /*!< External oscillator charge current is 1 µA */ - kTSI_ExtOscChargeCurrent_2uA = 2U, /*!< External oscillator charge current is 2 µA */ - kTSI_ExtOscChargeCurrent_4uA = 3U, /*!< External oscillator charge current is 4 µA */ - kTSI_ExtOscChargeCurrent_8uA = 4U, /*!< External oscillator charge current is 8 µA */ - kTSI_ExtOscChargeCurrent_16uA = 5U, /*!< External oscillator charge current is 16 µA */ - kTSI_ExtOscChargeCurrent_32uA = 6U, /*!< External oscillator charge current is 32 µA */ - kTSI_ExtOscChargeCurrent_64uA = 7U /*!< External oscillator charge current is 64 µA */ -} tsi_external_osc_charge_current_t; - -/*! - * @brief TSI series resistance RS value select. - * - * These bits indicate the electrode RS series resistance for the noise mode - * in TSI (EXTCHRG) instance. - */ -typedef enum _tsi_series_resistance -{ - kTSI_SeriesResistance_32k = 0U, /*!< Series Resistance is 32 kilo ohms */ - kTSI_SeriesResistance_187k = 1U /*!< Series Resistance is 18 7 kilo ohms */ -} tsi_series_resistor_t; - -/*! - * @brief TSI series filter bits select. - * - * These bits indicate the count of the filter bits - * in TSI noise mode EXTCHRG[2:1] bits - */ -typedef enum _tsi_filter_bits -{ - kTSI_FilterBits_3 = 0U, /*!< 3 filter bits, 8 peaks increments the cnt+1 */ - kTSI_FilterBits_2 = 1U, /*!< 2 filter bits, 4 peaks increments the cnt+1 */ - kTSI_FilterBits_1 = 2U, /*!< 1 filter bits, 2 peaks increments the cnt+1 */ - kTSI_FilterBits_0 = 3U /*!< no filter bits,1 peak increments the cnt+1 */ -} tsi_filter_bits_t; - -/*! @brief TSI status flags. */ -typedef enum _tsi_status_flags -{ - kTSI_EndOfScanFlag = TSI_GENCS_EOSF_MASK, /*!< End-Of-Scan flag */ - kTSI_OutOfRangeFlag = TSI_GENCS_OUTRGF_MASK /*!< Out-Of-Range flag */ -} tsi_status_flags_t; - -/*! @brief TSI feature interrupt source.*/ -typedef enum _tsi_interrupt_enable -{ - kTSI_GlobalInterruptEnable = 1U, /*!< TSI module global interrupt */ - kTSI_OutOfRangeInterruptEnable = 2U, /*!< Out-Of-Range interrupt */ - kTSI_EndOfScanInterruptEnable = 4U /*!< End-Of-Scan interrupt */ -} tsi_interrupt_enable_t; - -/*! @brief TSI calibration data storage. */ -typedef struct _tsi_calibration_data -{ - uint16_t calibratedData[FSL_FEATURE_TSI_CHANNEL_COUNT]; /*!< TSI calibration data storage buffer */ -} tsi_calibration_data_t; - -/*! - * @brief TSI configuration structure. - * - * This structure contains the settings for the most common TSI configurations including - * the TSI module charge currents, number of scans, thresholds, and so on. - */ -typedef struct _tsi_config -{ - uint16_t thresh; /*!< High threshold. */ - uint16_t thresl; /*!< Low threshold. */ - tsi_electrode_osc_prescaler_t prescaler; /*!< Prescaler */ - tsi_external_osc_charge_current_t extchrg; /*!< Electrode charge current */ - tsi_reference_osc_charge_current_t refchrg; /*!< Reference charge current */ - tsi_n_consecutive_scans_t nscn; /*!< Number of scans. */ - tsi_analog_mode_t mode; /*!< TSI mode of operation. */ - tsi_osc_voltage_rails_t dvolt; /*!< Oscillator's voltage rails. */ - tsi_series_resistor_t resistor; /*!< Series resistance value */ - tsi_filter_bits_t filter; /*!< Noise mode filter bits */ -} tsi_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @brief Initializes hardware. - * - * @details Initializes the peripheral to the targeted state specified by parameter configuration, - * such as sets prescalers, number of scans, clocks, delta voltage - * series resistor, filter bits, reference, and electrode charge current and threshold. - * @param base TSI peripheral base address. - * @param config Pointer to TSI module configuration structure. - * @return none - */ -void TSI_Init(TSI_Type *base, const tsi_config_t *config); - -/*! - * @brief De-initializes hardware. - * - * @details De-initializes the peripheral to default state. - * - * @param base TSI peripheral base address. - * @return none - */ -void TSI_Deinit(TSI_Type *base); - -/*! - * @brief Gets the TSI normal mode user configuration structure. - * This interface sets userConfig structure to a default value. The configuration structure only - * includes the settings for the whole TSI. - * The user configure is set to these values: - * @code - userConfig->prescaler = kTSI_ElecOscPrescaler_2div; - userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA; - userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA; - userConfig->nscn = kTSI_ConsecutiveScansNumber_10time; - userConfig->mode = kTSI_AnalogModeSel_Capacitive; - userConfig->dvolt = kTSI_OscVolRailsOption_0; - userConfig->thresh = 0U; - userConfig->thresl = 0U; - @endcode - * - * @param userConfig Pointer to the TSI user configuration structure. - */ -void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig); - -/*! - * @brief Gets the TSI low power mode default user configuration structure. - * This interface sets userConfig structure to a default value. The configuration structure only - * includes the settings for the whole TSI. - * The user configure is set to these values: - * @code - userConfig->prescaler = kTSI_ElecOscPrescaler_2div; - userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA; - userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA; - userConfig->nscn = kTSI_ConsecutiveScansNumber_10time; - userConfig->mode = kTSI_AnalogModeSel_Capacitive; - userConfig->dvolt = kTSI_OscVolRailsOption_0; - userConfig->thresh = 400U; - userConfig->thresl = 0U; - @endcode - * - * @param userConfig Pointer to the TSI user configuration structure. - */ -void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig); - -/*! - * @brief Hardware calibration. - * - * @details Calibrates the peripheral to fetch the initial counter value of - * the enabled electrodes. - * This API is mostly used at initial application setup. Call - * this function after the \ref TSI_Init API and use the calibrated - * counter values to set up applications (such as to determine - * under which counter value we can confirm a touch event occurs). - * - * @param base TSI peripheral base address. - * @param calBuff Data buffer that store the calibrated counter value. - * @return none - * - */ -void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff); - -/*! - * @brief Enables the TSI interrupt requests. - * @param base TSI peripheral base address. - * @param mask interrupt source - * The parameter can be combination of the following source if defined: - * @arg kTSI_GlobalInterruptEnable - * @arg kTSI_EndOfScanInterruptEnable - * @arg kTSI_OutOfRangeInterruptEnable - */ -void TSI_EnableInterrupts(TSI_Type *base, uint32_t mask); - -/*! - * @brief Disables the TSI interrupt requests. - * @param base TSI peripheral base address. - * @param mask interrupt source - * The parameter can be combination of the following source if defined: - * @arg kTSI_GlobalInterruptEnable - * @arg kTSI_EndOfScanInterruptEnable - * @arg kTSI_OutOfRangeInterruptEnable - */ -void TSI_DisableInterrupts(TSI_Type *base, uint32_t mask); - -/*! -* @brief Gets an interrupt flag. -* This function gets the TSI interrupt flags. -* -* @param base TSI peripheral base address. -* @return The mask of these status flags combination. -*/ -static inline uint32_t TSI_GetStatusFlags(TSI_Type *base) -{ - return (base->GENCS & (kTSI_EndOfScanFlag | kTSI_OutOfRangeFlag)); -} - -/*! - * @brief Clears the interrupt flag. - * - * This function clears the TSI interrupt flag, - * automatically cleared flags can't be cleared by this function. - * - * @param base TSI peripheral base address. - * @param mask The status flags to clear. - */ -void TSI_ClearStatusFlags(TSI_Type *base, uint32_t mask); - -/*! -* @brief Gets the TSI scan trigger mode. -* -* @param base TSI peripheral base address. -* @return Scan trigger mode. -*/ -static inline uint32_t TSI_GetScanTriggerMode(TSI_Type *base) -{ - return (base->GENCS & TSI_GENCS_STM_MASK); -} - -/*! -* @brief Gets the scan in progress flag. -* -* @param base TSI peripheral base address. -* @return True - scan is in progress. -* False - scan is not in progress. -*/ -static inline bool TSI_IsScanInProgress(TSI_Type *base) -{ - return (base->GENCS & TSI_GENCS_SCNIP_MASK); -} - -/*! -* @brief Sets the prescaler. -* -* @param base TSI peripheral base address. -* @param prescaler Prescaler value. -* @return none. -*/ -static inline void TSI_SetElectrodeOSCPrescaler(TSI_Type *base, tsi_electrode_osc_prescaler_t prescaler) -{ - base->GENCS = (base->GENCS & ~(TSI_GENCS_PS_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_PS(prescaler)); -} - -/*! -* @brief Sets the number of scans (NSCN). -* -* @param base TSI peripheral base address. -* @param number Number of scans. -* @return none. -*/ -static inline void TSI_SetNumberOfScans(TSI_Type *base, tsi_n_consecutive_scans_t number) -{ - base->GENCS = (base->GENCS & ~(TSI_GENCS_NSCN_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_NSCN(number)); -} - -/*! -* @brief Enables/disables the TSI module. -* -* @param base TSI peripheral base address. -* @param enable Choose whether to enable or disable module; -* - true Enable TSI module; -* - false Disable TSI module; -* @return none. -*/ -static inline void TSI_EnableModule(TSI_Type *base, bool enable) -{ - if (enable) - { - base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_TSIEN_MASK; /* Enable module */ - } - else - { - base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_TSIEN_MASK); /* Disable module */ - } -} - -/*! -* @brief Sets the TSI low power STOP mode as enabled or disabled. -* This enables the TSI module function in low power modes. -* -* @param base TSI peripheral base address. -* @param enable Choose to enable or disable STOP mode. -* - true Enable module in STOP mode; -* - false Disable module in STOP mode; -* @return none. -*/ -static inline void TSI_EnableLowPower(TSI_Type *base, bool enable) -{ - if (enable) - { - base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STPE_MASK; /* Module enabled in low power stop modes */ - } - else - { - base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STPE_MASK); /* Module disabled in low power stop modes */ - } -} - -/*! -* @brief Enables/disables the hardware trigger scan. -* -* @param base TSI peripheral base address. -* @param enable Choose to enable hardware trigger or software trigger scan. -* - true Enable hardware trigger scan; -* - false Enable software trigger scan; -* @return none. -*/ -static inline void TSI_EnableHardwareTriggerScan(TSI_Type *base, bool enable) -{ - if (enable) - { - base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STM_MASK; /* Enable hardware trigger scan */ - } - else - { - base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STM_MASK); /* Enable software trigger scan */ - } -} - -/*! -* @brief Starts a software trigger measurement (triggers a new measurement). -* -* @param base TSI peripheral base address. -* @return none. -*/ -static inline void TSI_StartSoftwareTrigger(TSI_Type *base) -{ - base->DATA |= TSI_DATA_SWTS_MASK; -} - -/*! -* @brief Sets the measured channel number. -* -* @param base TSI peripheral base address. -* @param channel Channel number 0 ... 15. -* @return none. -*/ -static inline void TSI_SetMeasuredChannelNumber(TSI_Type *base, uint8_t channel) -{ - assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT); - - base->DATA = ((base->DATA) & ~TSI_DATA_TSICH_MASK) | (TSI_DATA_TSICH(channel)); -} - -/*! -* @brief Gets the current measured channel number. -* -* @param base TSI peripheral base address. -* @return uint8_t Channel number 0 ... 15. -*/ -static inline uint8_t TSI_GetMeasuredChannelNumber(TSI_Type *base) -{ - return (uint8_t)((base->DATA & TSI_DATA_TSICH_MASK) >> TSI_DATA_TSICH_SHIFT); -} - -/*! -* @brief Enables/disables the DMA transfer. -* -* @param base TSI peripheral base address. -* @param enable Choose to enable DMA transfer or not. -* - true Enable DMA transfer; -* - false Disable DMA transfer; -* @return none. -*/ -static inline void TSI_EnableDmaTransfer(TSI_Type *base, bool enable) -{ - if (enable) - { - base->DATA |= TSI_DATA_DMAEN_MASK; /* Enable DMA transfer */ - } - else - { - base->DATA &= ~TSI_DATA_DMAEN_MASK; /* Disable DMA transfer */ - } -} - -#if defined(FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE) && (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1) -/*! -* @brief Decides whether to enable end of scan DMA transfer request only. -* -* @param base TSI peripheral base address. -* @param enable Choose whether to enable End of Scan DMA transfer request only. -* - true Enable End of Scan DMA transfer request only; -* - false Both End-of-Scan and Out-of-Range can generate DMA transfer request. -* @return none. -*/ -static inline void TSI_EnableEndOfScanDmaTransferOnly(TSI_Type *base, bool enable) -{ - if (enable) - { - base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_EOSDMEO_MASK; /* Enable End of Scan DMA transfer request only; */ - } - else - { - base->GENCS = - (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_EOSDMEO_MASK); /* Both End-of-Scan and Out-of-Range can generate DMA transfer request. */ - } -} -#endif /* End of (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1)*/ - -/*! -* @brief Gets the conversion counter value. -* -* @param base TSI peripheral base address. -* @return Accumulated scan counter value ticked by the reference clock. -*/ -static inline uint16_t TSI_GetCounter(TSI_Type *base) -{ - return (uint16_t)(base->DATA & TSI_DATA_TSICNT_MASK); -} - -/*! -* @brief Sets the TSI wake-up channel low threshold. -* -* @param base TSI peripheral base address. -* @param low_threshold Low counter threshold. -* @return none. -*/ -static inline void TSI_SetLowThreshold(TSI_Type *base, uint16_t low_threshold) -{ - assert(low_threshold < 0xFFFFU); - - base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold)); -} - -/*! -* @brief Sets the TSI wake-up channel high threshold. -* -* @param base TSI peripheral base address. -* @param high_threshold High counter threshold. -* @return none. -*/ -static inline void TSI_SetHighThreshold(TSI_Type *base, uint16_t high_threshold) -{ - assert(high_threshold < 0xFFFFU); - - base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold)); -} - -/*! -* @brief Sets the analog mode of the TSI module. -* -* @param base TSI peripheral base address. -* @param mode Mode value. -* @return none. -*/ -static inline void TSI_SetAnalogMode(TSI_Type *base, tsi_analog_mode_t mode) -{ - base->GENCS = (base->GENCS & ~(TSI_GENCS_MODE_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_MODE(mode)); -} - -/*! -* @brief Gets the noise mode result of the TSI module. -* -* @param base TSI peripheral base address. -* @return Value of the GENCS[MODE] bit-fields. -*/ -static inline uint8_t TSI_GetNoiseModeResult(TSI_Type *base) -{ - return (base->GENCS & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT; -} - -/*! -* @brief Sets the reference oscillator charge current. -* -* @param base TSI peripheral base address. -* @param current The reference oscillator charge current. -* @return none. -*/ -static inline void TSI_SetReferenceChargeCurrent(TSI_Type *base, tsi_reference_osc_charge_current_t current) -{ - base->GENCS = (base->GENCS & ~(TSI_GENCS_REFCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_REFCHRG(current)); -} - -/*! -* @brief Sets the external electrode charge current. -* -* @param base TSI peripheral base address. -* @param current External electrode charge current. -* @return none. -*/ -static inline void TSI_SetElectrodeChargeCurrent(TSI_Type *base, tsi_external_osc_charge_current_t current) -{ - base->GENCS = (base->GENCS & ~(TSI_GENCS_EXTCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_EXTCHRG(current)); -} - -/*! -* @brief Sets the oscillator's voltage rails. -* -* @param base TSI peripheral base address. -* @param dvolt The voltage rails. -* @return none. -*/ -static inline void TSI_SetOscVoltageRails(TSI_Type *base, tsi_osc_voltage_rails_t dvolt) -{ - base->GENCS = (base->GENCS & ~(TSI_GENCS_DVOLT_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_DVOLT(dvolt)); -} - -/*! -* @brief Sets the electrode series resistance value in EXTCHRG[0] bit. -* -* @param base TSI peripheral base address. -* @param resistor Series resistance. -* @return none. -*/ -static inline void TSI_SetElectrodeSeriesResistor(TSI_Type *base, tsi_series_resistor_t resistor) -{ - base->GENCS = (base->GENCS & TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR) | TSI_GENCS_EXTCHRG(resistor); -} - -/*! -* @brief Sets the electrode filter bits value in EXTCHRG[2:1] bits. -* -* @param base TSI peripheral base address. -* @param filter Series resistance. -* @return none. -*/ -static inline void TSI_SetFilterBits(TSI_Type *base, tsi_filter_bits_t filter) -{ - base->GENCS = (base->GENCS & TSI_V4_EXTCHRG_FILTER_BITS_CLEAR) | (filter << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT); -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_TSI_V4_H_ */ diff --git a/third_party/nxp/MKW41Z4/fsl_device_registers.h b/third_party/nxp/MKW41Z4/fsl_device_registers.h deleted file mode 100644 index b08e1667c..000000000 --- a/third_party/nxp/MKW41Z4/fsl_device_registers.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512CAT4) || defined(CPU_MKW41Z512VHT4)) - -#define KW41Z4_SERIES - -/* CMSIS-style register definitions */ -#include "MKW41Z4.h" -/* CPU specific feature definitions */ -#include "MKW41Z4_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/third_party/nxp/MKW41Z4/startup_MKW41Z4.S b/third_party/nxp/MKW41Z4/startup_MKW41Z4.S deleted file mode 100644 index b42ba0f13..000000000 --- a/third_party/nxp/MKW41Z4/startup_MKW41Z4.S +++ /dev/null @@ -1,365 +0,0 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_MKW41Z4.s */ -/* @purpose: CMSIS Cortex-M0P Core Device Startup File */ -/* MKW41Z4 */ -/* @version: 1.0 */ -/* @date: 2015-9-23 */ -/* @build: b170113 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. */ -/* Copyright 2016 - 2017 NXP */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted provided that the following conditions are met: */ -/* */ -/* o Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* o Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* o Neither the name of the copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv6-m - - .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ - .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ - .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ - .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ - .long Reserved20_IRQHandler /* Reserved interrupt*/ - .long FTFA_IRQHandler /* Command complete and read collision*/ - .long LVD_LVW_DCDC_IRQHandler /* Low-voltage detect, low-voltage warning, DCDC*/ - .long LLWU_IRQHandler /* Low leakage wakeup Unit*/ - .long I2C0_IRQHandler /* I2C0 interrupt*/ - .long I2C1_IRQHandler /* I2C1 interrupt*/ - .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ - .long TSI0_IRQHandler /* TSI0 single interrupt vector for all sources*/ - .long LPUART0_IRQHandler /* LPUART0 status and error*/ - .long TRNG0_IRQHandler /* TRNG0 interrupt*/ - .long CMT_IRQHandler /* CMT interrupt*/ - .long ADC0_IRQHandler /* ADC0 interrupt*/ - .long CMP0_IRQHandler /* CMP0 interrupt*/ - .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ - .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ - .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ - .long RTC_IRQHandler /* RTC alarm*/ - .long RTC_Seconds_IRQHandler /* RTC seconds*/ - .long PIT_IRQHandler /* PIT interrupt*/ - .long LTC0_IRQHandler /* LTC0 interrupt*/ - .long Radio_0_IRQHandler /* BTLE, ZIGBEE, ANT, GENFSK interrupt 0*/ - .long DAC0_IRQHandler /* DAC0 interrupt*/ - .long Radio_1_IRQHandler /* BTLE, ZIGBEE, ANT, GENFSK interrupt 1*/ - .long MCG_IRQHandler /* MCG interrupt*/ - .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ - .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ - .long PORTA_IRQHandler /* PORTA Pin detect*/ - .long PORTB_PORTC_IRQHandler /* PORTB and PORTC Pin detect*/ - - .size __isr_vector, . - __isr_vector - -/* Flash Configuration */ - .section .FlashConfig, "a" - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFE - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__isr_vector - str r1, [r0] - ldr r2, [r1] - msr msp, r2 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC0 - -.LC1: - subs r3, 4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .LC1 -.LC0: - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - subs r2, r1 - ble .LC3 - - movs r0, 0 -.LC2: - str r0, [r1, r2] - subs r2, 4 - bge .LC2 -.LC3: -#endif - cpsie i /* Unmask interrupts */ -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - ldr r0, =DefaultISR - bx r0 - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_IRQHandler - .type DMA1_IRQHandler, %function -DMA1_IRQHandler: - ldr r0,=DMA1_DriverIRQHandler - bx r0 - .size DMA1_IRQHandler, . - DMA1_IRQHandler - - .align 1 - .thumb_func - .weak DMA2_IRQHandler - .type DMA2_IRQHandler, %function -DMA2_IRQHandler: - ldr r0,=DMA2_DriverIRQHandler - bx r0 - .size DMA2_IRQHandler, . - DMA2_IRQHandler - - .align 1 - .thumb_func - .weak DMA3_IRQHandler - .type DMA3_IRQHandler, %function -DMA3_IRQHandler: - ldr r0,=DMA3_DriverIRQHandler - bx r0 - .size DMA3_IRQHandler, . - DMA3_IRQHandler - - .align 1 - .thumb_func - .weak I2C0_IRQHandler - .type I2C0_IRQHandler, %function -I2C0_IRQHandler: - ldr r0,=I2C0_DriverIRQHandler - bx r0 - .size I2C0_IRQHandler, . - I2C0_IRQHandler - - .align 1 - .thumb_func - .weak I2C1_IRQHandler - .type I2C1_IRQHandler, %function -I2C1_IRQHandler: - ldr r0,=I2C1_DriverIRQHandler - bx r0 - .size I2C1_IRQHandler, . - I2C1_IRQHandler - - .align 1 - .thumb_func - .weak SPI0_IRQHandler - .type SPI0_IRQHandler, %function -SPI0_IRQHandler: - ldr r0,=SPI0_DriverIRQHandler - bx r0 - .size SPI0_IRQHandler, . - SPI0_IRQHandler - - .align 1 - .thumb_func - .weak LPUART0_IRQHandler - .type LPUART0_IRQHandler, %function -LPUART0_IRQHandler: - ldr r0,=LPUART0_DriverIRQHandler - bx r0 - .size LPUART0_IRQHandler, . - LPUART0_IRQHandler - - .align 1 - .thumb_func - .weak SPI1_IRQHandler - .type SPI1_IRQHandler, %function -SPI1_IRQHandler: - ldr r0,=SPI1_DriverIRQHandler - bx r0 - .size SPI1_IRQHandler, . - SPI1_IRQHandler - - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler DMA0_DriverIRQHandler - def_irq_handler DMA1_DriverIRQHandler - def_irq_handler DMA2_DriverIRQHandler - def_irq_handler DMA3_DriverIRQHandler - def_irq_handler Reserved20_IRQHandler - def_irq_handler FTFA_IRQHandler - def_irq_handler LVD_LVW_DCDC_IRQHandler - def_irq_handler LLWU_IRQHandler - def_irq_handler I2C0_DriverIRQHandler - def_irq_handler I2C1_DriverIRQHandler - def_irq_handler SPI0_DriverIRQHandler - def_irq_handler TSI0_IRQHandler - def_irq_handler LPUART0_DriverIRQHandler - def_irq_handler TRNG0_IRQHandler - def_irq_handler CMT_IRQHandler - def_irq_handler ADC0_IRQHandler - def_irq_handler CMP0_IRQHandler - def_irq_handler TPM0_IRQHandler - def_irq_handler TPM1_IRQHandler - def_irq_handler TPM2_IRQHandler - def_irq_handler RTC_IRQHandler - def_irq_handler RTC_Seconds_IRQHandler - def_irq_handler PIT_IRQHandler - def_irq_handler LTC0_IRQHandler - def_irq_handler Radio_0_IRQHandler - def_irq_handler DAC0_IRQHandler - def_irq_handler Radio_1_IRQHandler - def_irq_handler MCG_IRQHandler - def_irq_handler LPTMR0_IRQHandler - def_irq_handler SPI1_DriverIRQHandler - def_irq_handler PORTA_IRQHandler - def_irq_handler PORTB_PORTC_IRQHandler - - .end diff --git a/third_party/nxp/MKW41Z4/system_MKW41Z4.c b/third_party/nxp/MKW41Z4/system_MKW41Z4.c deleted file mode 100644 index 299de698b..000000000 --- a/third_party/nxp/MKW41Z4/system_MKW41Z4.c +++ /dev/null @@ -1,186 +0,0 @@ -/* -** ################################################################### -** Processors: MKW41Z256VHT4 -** MKW41Z512CAT4 -** MKW41Z512VHT4 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 -** Version: rev. 1.0, 2015-09-23 -** Build: b170213 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2015-09-23) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file MKW41Z4 - * @version 1.0 - * @date 2015-09-23 - * @brief Device specific configuration file for MKW41Z4 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { - -#if (DISABLE_WDOG) - /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */ - SIM->COPC = (uint32_t)0x00u; -#endif /* (DISABLE_WDOG) */ - -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint16_t Divider; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { - /* External reference clock is selected */ - if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } - if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { - switch (MCG->C1 & MCG_C1_FRDIV_MASK) { - case 0x38U: - Divider = 1536U; - break; - case 0x30U: - Divider = 1280U; - break; - default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - break; - } - } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - } - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x00U: - MCGOUTClock *= 640U; - break; - case 0x20U: - MCGOUTClock *= 1280U; - break; - case 0x40U: - MCGOUTClock *= 1920U; - break; - case 0x60U: - MCGOUTClock *= 2560U; - break; - case 0x80U: - MCGOUTClock *= 732U; - break; - case 0xA0U: - MCGOUTClock *= 1464U; - break; - case 0xC0U: - MCGOUTClock *= 2197U; - break; - case 0xE0U: - MCGOUTClock *= 2929U; - break; - default: - break; - } - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); - MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { - /* External reference clock is selected */ - if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - /* Reserved value */ - return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ - SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); - -} - -//__extension__ typedef int __guard __attribute__((mode(__DI__))); -//int __cxa_guard_acquire(__guard *g) { return !*(char *)(g); } -//void __cxa_guard_release(__guard *g) { *(char *)g = 1; } -//void __cxa_guard_abort(__guard *g) { (void)g; } -void __cxa_pure_virtual(void) { while (1); } \ No newline at end of file diff --git a/third_party/nxp/MKW41Z4/system_MKW41Z4.h b/third_party/nxp/MKW41Z4/system_MKW41Z4.h deleted file mode 100644 index e6ab1470e..000000000 --- a/third_party/nxp/MKW41Z4/system_MKW41Z4.h +++ /dev/null @@ -1,134 +0,0 @@ -/* -** ################################################################### -** Processors: MKW41Z256VHT4 -** MKW41Z512CAT4 -** MKW41Z512VHT4 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016 -** Version: rev. 1.0, 2015-09-23 -** Build: b170213 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2015-09-23) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file MKW41Z4 - * @version 1.0 - * @date 2015-09-23 - * @brief Device specific configuration file for MKW41Z4 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_MKW41Z4_H_ -#define _SYSTEM_MKW41Z4_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 32000000u /* Value of the external crystal or oscillator clock frequency in Hz */ -#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ -#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - -/* RF oscillator setting */ -#define SYSTEM_RSIM_CONTROL_VALUE 0xC00100U /* Enable RF oscillator in Run/Wait mode */ - -/* Low power mode enable */ - -/* SMC_PMPROT: ?=0,?=0,AVLP=1,?=0,?=0,?=0,AVLLS=1,?=0 */ -#define SYSTEM_SMC_PMPROT_VALUE (SMC_PMPROT_AVLP_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLLS_MASK) /* Mask of allowed low power modes used to initialize power modes protection register */ - -#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_MKW41Z4_H_ */