[examples] add NXP JN5189 platform (#4642)

This commit contains all the new files required by the JN5189 platform as well as
the implementation of the platform files required by OpenThread.

Signed-off-by: Doru Gucea <[email protected]>

configure.ac

@@ -788,14 +788,14 @@ AC_MSG_CHECKING([whether to build examples])
 AC_ARG_WITH(examples,
     [AS_HELP_STRING([--with-examples=TARGET],
         [Build example applications for one of: simulation, cc1352, cc2538, cc2650, cc2652, efr32mg12, efr32mg13, efr32mg21,
-         gp712, kw41z, nrf52811, nrf52833, nrf52840, qpg6095, samr21 @<:@default=no@:>@.
+         gp712, jn5189, kw41z, nrf52811, nrf52833, nrf52840, qpg6095, samr21 @<:@default=no@:>@.
          Note that building example applications also builds the associated OpenThread platform libraries
          and any third_party libraries needed to support the examples.])],
     [
         case "${with_examples}" in
         no)
             ;;
-        simulation|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|kw41z|nrf52811|nrf52833|nrf52840|qpg6095|samr21)
+        simulation|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|jn5189|kw41z|nrf52811|nrf52833|nrf52840|qpg6095|samr21)
             ;;
         *)
             AC_MSG_RESULT(ERROR)
@@ -816,6 +816,7 @@ AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG12], [test "${with_examples}" = "efr3
 AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG13], [test "${with_examples}" = "efr32mg13"])
 AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG21], [test "${with_examples}" = "efr32mg21"])
 AM_CONDITIONAL([OPENTHREAD_EXAMPLES_GP712],     [test "${with_examples}" = "gp712"])
+AM_CONDITIONAL([OPENTHREAD_EXAMPLES_JN5189],    [test "${with_examples}" = "jn5189"])
 AM_CONDITIONAL([OPENTHREAD_EXAMPLES_KW41Z],     [test "${with_examples}" = "kw41z"])
 AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52811],  [test "${with_examples}" = "nrf52811"])
 AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52833],  [test "${with_examples}" = "nrf52833"])
@@ -845,11 +846,11 @@ AC_MSG_CHECKING([whether to build platform libraries])
 AC_ARG_WITH(platform,
     [AS_HELP_STRING([--with-platform=TARGET],
         [Build OpenThread platform libraries for one of: cc1352, cc2538, cc2650, cc2652,
-         efr32mg12, efr32mg13, efr32mg21, gp712, kw41z, nrf52811, nrf52833, nrf52840, posix, qpg6095, samr21, simulation @<:@default=simulation@:>@.])],
+         efr32mg12, efr32mg13, efr32mg21, gp712, jn5189, kw41z, nrf52811, nrf52833, nrf52840, posix, qpg6095, samr21, simulation @<:@default=simulation@:>@.])],
     [
         # Make sure the given target is valid.
         case "${with_platform}" in
-        no|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|kw41z|nrf52811|nrf52833|nrf52840|posix|qpg6095|samr21|simulation)
+        no|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|jn5189|kw41z|nrf52811|nrf52833|nrf52840|posix|qpg6095|samr21|simulation)
             ;;
         *)
             AC_MSG_RESULT(ERROR)
@@ -888,6 +889,7 @@ AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG12], [test "${with_platform}" = "efr3
 AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG13], [test "${with_platform}" = "efr32mg13"])
 AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG21], [test "${with_platform}" = "efr32mg21"])
 AM_CONDITIONAL([OPENTHREAD_PLATFORM_GP712],     [test "${with_platform}" = "gp712"])
+AM_CONDITIONAL([OPENTHREAD_PLATFORM_JN5189],    [test "${with_platform}" = "jn5189"])
 AM_CONDITIONAL([OPENTHREAD_PLATFORM_KW41Z],     [test "${with_platform}" = "kw41z"])
 AM_CONDITIONAL([OPENTHREAD_PLATFORM_NRF52811],  [test "${with_platform}" = "nrf52811"])
 AM_CONDITIONAL([OPENTHREAD_PLATFORM_NRF52833],  [test "${with_platform}" = "nrf52833"])
@@ -1053,6 +1055,7 @@ examples/platforms/efr32mg21/sleepy-demo/Makefile
 examples/platforms/efr32mg21/sleepy-demo/sleepy-demo-ftd/Makefile
 examples/platforms/efr32mg21/sleepy-demo/sleepy-demo-mtd/Makefile
 examples/platforms/gp712/Makefile
+examples/platforms/jn5189/Makefile
 examples/platforms/kw41z/Makefile
 examples/platforms/nrf528xx/Makefile
 examples/platforms/qpg6095/Makefile

examples/Makefile-jn5189

@@ -0,0 +1,293 @@
+#
+#  Copyright (c) 2019, The OpenThread Authors.
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#  1. Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#  3. Neither the name of the copyright holder nor the
+#     names of its contributors may be used to endorse or promote products
+#     derived from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+
+.NOTPARALLEL:
+
+AR                              = arm-none-eabi-ar
+CCAS                            = arm-none-eabi-as
+CPP                             = arm-none-eabi-cpp
+CC                              = arm-none-eabi-gcc
+CXX                             = arm-none-eabi-g++
+LD                              = arm-none-eabi-ld
+STRIP                           = arm-none-eabi-strip
+NM                              = arm-none-eabi-nm
+RANLIB                          = arm-none-eabi-ranlib
+OBJCOPY                         = arm-none-eabi-objcopy
+
+BuildJobs                      ?= 10
+
+configure_OPTIONS               = \
+    --enable-cli                  \
+    --enable-diag                 \
+    --enable-ftd                  \
+    --enable-mtd                  \
+    --enable-ncp                  \
+    --with-ncp-bus=uart           \
+    --enable-radio-only           \
+    --enable-linker-map           \
+    --with-examples=jn5189        \
+    $(NULL)
+
+ifneq ($(DISABLE_BUILTIN_MBEDTLS), 1)
+configure_OPTIONS              += MBEDTLS_CPPFLAGS="$(JN5189_MBEDTLS_CPPFLAGS)"
+endif
+
+JN5189_MBEDTLS_CPPFLAGS  = -DMBEDTLS_CONFIG_FILE='\"mbedtls-config.h\"'
+JN5189_MBEDTLS_CPPFLAGS += -DMBEDTLS_USER_CONFIG_FILE='\"jn5189-mbedtls-config.h\"'
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/include/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/crypto
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/aes/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/sha/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/rom_apis/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/dk6_jn5180/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/CMSIS/Include/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/mbedtls/
+
+TopSourceDir                    := $(dir $(shell readlink $(firstword $(MAKEFILE_LIST))))..
+AbsTopSourceDir                 := $(dir $(realpath $(firstword $(MAKEFILE_LIST))))..
+
+CONFIG_FILE      = OPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-jn5189-config.h\"'
+CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/jn5189/
+SIGN_IMAGE_PATH = $(AbsTopSourceDir)/third_party/nxp/JN5189/ImageSigning/
+
+COMMONCFLAGS                          := \
+    -fdata-sections                      \
+    -ffunction-sections                  \
+    -Os                                  \
+    -g                                   \
+    -DCPU_JN518X                         \
+    -DCPU_JN518X_REV=2                   \
+    -DJENNIC_CHIP_FAMILY_JN518x          \
+    -DJENNIC_CHIP_FAMILY_NAME=_JN518x    \
+    -DSDK_DEBUGCONSOLE=0                 \
+    -D$(CONFIG_FILE)                     \
+    -I$(CONFIG_FILE_PATH)                \
+    $(NULL)
+
+include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/common-switches.mk
+
+CPPFLAGS                       += \
+    $(COMMONCFLAGS)               \
+    $(target_CPPFLAGS)            \
+    $(NULL)
+
+CFLAGS                         += \
+    $(COMMONCFLAGS)               \
+    $(target_CFLAGS)              \
+    $(NULL)
+
+CXXFLAGS                       += \
+    $(COMMONCFLAGS)               \
+    $(target_CXXFLAGS)            \
+    -fno-exceptions               \
+    -fno-rtti                     \
+    $(NULL)
+
+LDFLAGS                        += \
+    $(COMMONCFLAGS)               \
+    $(target_LDFLAGS)             \
+    -specs=nano.specs             \
+    -specs=nosys.specs            \
+    -Wl,--gc-sections             \
+    $(NULL)
+
+ECHO                            := @echo
+MAKE                            := make
+MKDIR_P                         := mkdir -p
+LN_S                            := ln -s
+RM_F                            := rm -f
+
+INSTALL                         := /usr/bin/install
+INSTALLFLAGS                    := -p
+
+BuildPath                       = build
+TopBuildDir                     = $(BuildPath)
+AbsTopBuildDir                  = $(PWD)/$(TopBuildDir)
+
+ResultPath                      = output
+TopResultDir                    = $(ResultPath)
+AbsTopResultDir                 = $(PWD)/$(TopResultDir)
+
+TargetTuple                     = jn5189
+
+ARCHS                           = cortex-m4
+
+TopTargetLibDir                 = $(TopResultDir)/$(TargetTuple)/lib
+TopTargetBinDir                 = $(TopResultDir)/$(TargetTuple)/bin
+
+ifndef BuildJobs
+BuildJobs := $(shell getconf _NPROCESSORS_ONLN)
+endif
+JOBSFLAG := -j$(BuildJobs)
+
+#
+# configure-arch <arch>
+#
+# Configure OpenThread for the specified architecture.
+#
+#   arch - The architecture to configure.
+#
+define configure-arch
+$(ECHO) "  CONFIG   $(TargetTuple)..."
+(cd $(BuildPath)/$(TargetTuple) && $(AbsTopSourceDir)/configure \
+INSTALL="$(INSTALL) $(INSTALLFLAGS)" \
+CPP="$(CPP)" CC="$(CC)" CXX="$(CXX)" OBJC="$(OBJC)" OBJCXX="$(OBJCXX)" AR="$(AR)" RANLIB="$(RANLIB)" NM="$(NM)" STRIP="$(STRIP)" CPPFLAGS="$(CPPFLAGS)" CFLAGS="$(CFLAGS)" CXXFLAGS="$(CXXFLAGS)" LDFLAGS="$(LDFLAGS)" \
+--host=arm-none-eabi \
+--prefix=/ \
+--exec-prefix=/$(TargetTuple) \
+$(configure_OPTIONS))
+endef # configure-arch
+
+#
+# build-arch <arch>
+#
+# Build the OpenThread intermediate build products for the specified
+# architecture.
+#
+#   arch - The architecture to build.
+#
+define build-arch
+$(ECHO) "  BUILD    $(TargetTuple)"
+$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \
+all
+endef # build-arch
+
+#
+# stage-arch <arch>
+#
+# Stage (install) the OpenThread final build products for the specified
+# architecture.
+#
+#   arch - The architecture to stage.
+#
+define stage-arch
+$(ECHO) "  STAGE    $(TargetTuple)"
+$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \
+DESTDIR=$(AbsTopResultDir) \
+install
+endef # stage-arch
+
+#
+# ARCH_template <arch>
+#
+# Define macros, targets and rules to configure, build, and stage the
+# OpenThread for a single architecture.
+#
+#   arch - The architecture to instantiate the template for.
+#
+define ARCH_template
+CONFIGURE_TARGETS += configure-$(1)
+BUILD_TARGETS     += do-build-$(1)
+STAGE_TARGETS     += stage-$(1)
+BUILD_DIRS        += $(BuildPath)/$(TargetTuple)
+DIRECTORIES       += $(BuildPath)/$(TargetTuple)
+
+configure-$(1): target_CPPFLAGS=$($(1)_target_CPPFLAGS)
+configure-$(1): target_CFLAGS=$($(1)_target_CFLAGS)
+configure-$(1): target_CXXFLAGS=$($(1)_target_CXXFLAGS)
+configure-$(1): target_LDFLAGS=$($(1)_target_LDFLAGS)
+
+configure-$(1): $(BuildPath)/$(TargetTuple)/config.status
+
+$(BuildPath)/$(TargetTuple)/config.status: | $(BuildPath)/$(TargetTuple)
+	$$(call configure-arch,$(1))
+
+do-build-$(1): configure-$(1)
+
+do-build-$(1):
+	+$$(call build-arch,$(1))
+
+stage-$(1): do-build-$(1)
+
+stage-$(1): | $(TopResultDir)
+	$$(call stage-arch,$(1))
+
+$(1): stage-$(1)
+endef # ARCH_template
+
+.DEFAULT_GOAL := all
+
+all: stage
+
+#
+# cortex-m4
+#
+
+cortex-m4_target_ABI                  = cortex-m4
+cortex-m4_target_CPPFLAGS             = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+cortex-m4_target_CFLAGS               = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+cortex-m4_target_CXXFLAGS             = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+cortex-m4_target_LDFLAGS              = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+
+# Instantiate an architecture-specific build template for each target
+# architecture.
+
+$(foreach arch,$(ARCHS),$(eval $(call ARCH_template,$(arch))))
+
+#
+# Common / Finalization
+#
+
+configure: $(CONFIGURE_TARGETS)
+
+build: $(BUILD_TARGETS)
+
+stage: $(STAGE_TARGETS)
+
+DIRECTORIES     = $(TopResultDir) $(TopResultDir)/$(TargetTuple)/lib $(BUILD_DIRS)
+
+CLEAN_DIRS      = $(TopResultDir) $(BUILD_DIRS)
+
+all: stage post-build-step
+
+$(DIRECTORIES):
+	$(ECHO) "  MKDIR    $@"
+	@$(MKDIR_P) "$@"
+
+post-build-step:
+	$(SIGN_IMAGE_PATH)/sign_images.sh $(TopTargetBinDir)
+
+clean:
+	$(ECHO) "  CLEAN"
+	@$(RM_F) -r $(CLEAN_DIRS)
+
+help:
+	$(ECHO) "Simply type 'make -f $(firstword $(MAKEFILE_LIST))' to build OpenThread for the following "
+	$(ECHO) "architectures: "
+	$(ECHO) ""
+	$(ECHO) "    $(ARCHS)"
+	$(ECHO) ""
+	$(ECHO) "To build only a particular architecture, specify: "
+	$(ECHO) ""
+	$(ECHO) "    make -f $(firstword $(MAKEFILE_LIST)) <architecture>"
+	$(ECHO) ""

examples/platforms/Makefile.am

@@ -39,6 +39,7 @@ DIST_SUBDIRS                            = \
     efr32mg13                             \
     efr32mg21                             \
     gp712                                 \
+    jn5189                                \
     kw41z                                 \
     nrf528xx                              \
     simulation                            \
@@ -85,6 +86,10 @@ if OPENTHREAD_PLATFORM_GP712
 SUBDIRS                                += gp712
 endif
 
+if OPENTHREAD_PLATFORM_JN5189
+SUBDIRS                                += jn5189
+endif
+
 if OPENTHREAD_PLATFORM_KW41Z
 SUBDIRS                                += kw41z
 endif

examples/platforms/Makefile.platform.am

@@ -73,6 +73,10 @@ if OPENTHREAD_EXAMPLES_GP712
 include $(top_srcdir)/examples/platforms/gp712/Makefile.platform.am
 endif
 
+if OPENTHREAD_EXAMPLES_JN5189
+include $(top_srcdir)/examples/platforms/jn5189/Makefile.platform.am
+endif
+
 if OPENTHREAD_EXAMPLES_KW41Z
 include $(top_srcdir)/examples/platforms/kw41z/Makefile.platform.am
 endif

examples/platforms/jn5189/Makefile.am

@@ -0,0 +1,128 @@
+#
+#  Copyright (c) 2019, The OpenThread Authors.
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#  1. Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#  3. Neither the name of the copyright holder nor the
+#     names of its contributors may be used to endorse or promote products
+#     derived from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(abs_top_nlbuild_autotools_dir)/automake/pre.am
+
+lib_LIBRARIES                                                                                      = \
+    libopenthread-jn5189_plat.a                                                                      \
+    libopenthread-jn5189_sdk.a
+    $(NULL)
+
+# Do not enable -pedantic-errors for jn5189 driver library
+override CFLAGS                                      := $(filter-out -pedantic-errors,$(CFLAGS))
+override CXXFLAGS                                    := $(filter-out -pedantic-errors,$(CXXFLAGS))
+
+# Do not enable -Wundef for jn5189 driver library
+override CFLAGS    := $(filter-out -Wundef,$(CFLAGS))
+override CXXFLAGS  := $(filter-out -Wundef,$(CXXFLAGS))
+
+LIB_FLAGS                                                                                          = \
+    -DCPU_JN518X                                                                                     \
+    -DCPU_JN518X_REV=2                                                                               \
+    -DJENNIC_CHIP_FAMILY_JN518x                                                                      \
+    -DJENNIC_CHIP_FAMILY_NAME=_JN518x                                                                \
+    -I$(top_srcdir)/include                                                                          \
+    -I$(top_srcdir)/examples/platforms                                                               \
+    -I$(top_srcdir)/src/core                                                                         \
+    -I$(top_srcdir)/third_party/nxp                                                                  \
+    -I$(top_srcdir)/third_party/nxp/JN5189                                                           \
+    -I$(top_srcdir)/third_party/nxp/JN5189/crypto                                                    \
+    -I$(top_srcdir)/third_party/nxp/JN5189/drivers                                                   \
+    -I$(top_srcdir)/third_party/nxp/JN5189/rom_apis                                                  \
+    -I$(top_srcdir)/third_party/nxp/JN5189/dk6_jn5180                                                \
+    -I$(top_srcdir)/third_party/nxp/CMSIS/Include                                                    \
+    -I$(top_srcdir)/third_party/nxp/JN5189/uMac/Include                                              \
+    -I$(top_srcdir)/third_party/nxp/JN5189/Radio_JN5189/Include                                      \
+    -I$(top_srcdir)/third_party/nxp/JN5189/JennicCommon/Include                                      \
+    -I$(top_srcdir)/third_party/nxp/JN5189/MicroSpecific/Include                                     \
+    -Wno-unknown-pragmas                                                                             \
+    -Wno-sign-compare                                                                                \
+    -Wno-unused-function                                                                             \
+    -Wno-unused-parameter                                                                            \
+    -Wno-empty-body                                                                                  \
+    $(NULL)
+
+libopenthread_jn5189_sdk_a_CPPFLAGS                                                                = \
+    $(LIB_FLAGS)                                                                                     \
+	$(NULL)
+
+libopenthread_jn5189_plat_a_CPPFLAGS                                                               = \
+    $(LIB_FLAGS)                                                                                     \
+	$(NULL)
+
+PLATFORM_SOURCES                                                                                   = \
+    alarm.c                                                                                          \
+    diag.c                                                                                           \
+    flash.c                                                                                          \
+    logging.c                                                                                        \
+    misc.c                                                                                           \
+    radio.c                                                                                          \
+    entropy.c                                                                                        \
+    system.c                                                                                         \
+    uart.c                                                                                           \
+    settings_jn5189.c                                                                                \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_assert.c                                       \
+    @top_builddir@/third_party/nxp/JN5189/crypto/aes_alt.c                                           \
+    @top_builddir@/third_party/nxp/JN5189/crypto/ksdk_mbedtls.c                                      \
+    $(NULL)
+
+libopenthread_jn5189_sdk_a_SOURCES                                                                 = \
+    @top_builddir@/third_party/nxp/JN5189/startup_JN5189.c                                           \
+    @top_builddir@/third_party/nxp/JN5189/system_JN5189.c                                            \
+    @top_builddir@/third_party/nxp/JN5189/dk6_jn5180/pin_mux.c                                       \
+    @top_builddir@/third_party/nxp/JN5189/dk6_jn5180/clock_config.c                                  \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_gpio.c                                         \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_clock.c                                        \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_ctimer.c                                       \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_wtimer.c                                       \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_flash.c                                        \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_usart.c                                        \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_rng.c                                          \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_flexcomm.c                                     \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_reset.c                                        \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_power.c                                        \
+    @top_builddir@/third_party/nxp/JN5189/drivers/fsl_debug_console.c                                \
+    @top_builddir@/third_party/nxp/JN5189/drivers/aes/fsl_aes.c                                      \
+    @top_builddir@/third_party/nxp/JN5189/drivers/sha/fsl_sha.c                                      \
+    $(NULL)
+
+libopenthread_jn5189_plat_a_SOURCES                                                                = \
+    $(PLATFORM_SOURCES)                                                                              \
+    $(NULL)
+
+PRETTY_FILES                                                                                       = \
+    $(PLATFORM_SOURCES)                                                                              \
+    $(NULL)
+
+Dash                                                                                                = -
+libopenthread_jn5189_sdk_a_LIBADD                                                                   = \
+    $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
+libopenthread_jn5189_plat_a_LIBADD                                                                  = \
+    $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
+
+include $(abs_top_nlbuild_autotools_dir)/automake/post.am

examples/platforms/jn5189/Makefile.platform.am

@@ -0,0 +1,43 @@
+#
+#  Copyright (c) 2019, The OpenThread Authors.
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#  1. Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#  3. Neither the name of the copyright holder nor the
+#     names of its contributors may be used to endorse or promote products
+#     derived from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# JN5189 platform-specific Makefile
+#
+
+LDADD_COMMON                                                               += \
+    $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_plat.a     \
+    $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_sdk.a      \
+    $(top_srcdir)/third_party/nxp/JN5189/libraries/libMiniMac.a               \
+    $(top_srcdir)/third_party/nxp/JN5189/libraries/libRadio.a                 \
+    $(top_srcdir)/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a  \
+    $(NULL)
+
+LDFLAGS_COMMON                                                        += \
+    -T $(top_srcdir)/examples/platforms/jn5189/jn5189.ld                 \
+    $(NULL)

examples/platforms/jn5189/README.md

@@ -0,0 +1,138 @@
+# OpenThread on NXP JN5189 Example
+
+This directory contains example platform drivers for the [NXP JN5189][https://www.nxp.com/products/wireless/thread/jn5189-88-t-high-performance-and-ultra-low-power-mcus-for-zigbee-and-thread-with-built-in-nfc-option:JN5189_88_T]
+based on [JN5189-DK006][https://www.nxp.com/products/wireless/zigbee/advanced-development-kit-for-jn5189-88:JN5189-DK006] hardware platform.
+
+The example platform drivers are intended to present the minimal code
+necessary to support OpenThread.  As a result, the example platform
+drivers do not necessarily highlight the platform's full capabilities.
+
+## Toolchain
+OpenThread environment is suited to be run on a Linux-based OS. Recommended OS is Ubuntu 18.04.2 LTS.
+Download and install the [MCUXpresso IDE][mcuxpresso ide].
+
+[mcuxpresso ide]: https://www.nxp.com/support/developer-resources/software-development-tools/mcuxpresso-software-and-tools/mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDE
+
+In a Bash terminal (found, for example, in Ubuntu OS), follow these instructions to install the GNU toolchain and
+other dependencies.
+
+```bash
+$ cd <path-to-openthread>
+$ ./script/bootstrap
+```
+If a network connection timeout is encountered, re-run the script.
+
+Python-pip is also required for the build. User can install it by running "sudo apt-get install Python-pip" in bash.
+After installing Python-pip, execute "pip install PyCryptodome" in bash. This is needed for signing the built binary in order to load it on the board.
+Also, pycrypto "pip install pycrypto" is required for PKCS1.
+
+Windows 10 offers the possibility of running bash by installing "Ubuntu on Windows" from Microsoft Store. This application allows the user to use Ubuntu Terminal and run Ubuntu command line utilities including bash, ssh, git, apt and many more.
+If this option is used, it is recommended to add instructions for the path mapping in MCUXpresso IDE. This can be done after adding the project to the workspace by going to Run->"Debug Configuration"->"C/C++(NXP Semiconductors) MCU Application"->Source->Add. Then the user should create a path mapping such that MCUXpresso IDE will find the mount point for the "Ubuntu in Windows" subsystem.
+For example, user can enter compilation path recognized by Ubuntu as /mnt/c/<path-to-openthread>, while equivalent "Local file system path" is C:/<path-to-openthread>. This example assumes that the openthread package is installed on the C drive.
+
+## Build Examples
+
+```bash
+$ cd <path-to-openthread>
+$ ./bootstrap
+$ make -f examples/Makefile-jn5189
+```
+
+After a successful build, the `elf` files are found in
+`<path-to-openthread>/output/jn5189/bin`.
+
+## Flash Binaries
+
+Connect to the board by plugging a mini-USB cable to the connector marked with TARGET on the DK6 board. This connector is situated on the same side with the power connector.
+
+OpenThread example application compiled binaries can be found in `<path-to-openthread>/output/jn5189/bin` and include FTD (Full Thread Device) and MTD (Minimal Thread Device) variants of CLI and NCP applications.
+The compiled binaries can be flashed onto the JN5189 using MCUXpresso IDE. This requires the following steps:
+1. Import the JN5189 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_JN5189DK6 can be downloaded from https://mcuxpresso.nxp.com.
+2. In MCUXpresso IDE, go to File->Import->C/C++->"Existing Code as Makefile Project" and click Next.
+3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to "none". Click Finish.
+4. Right click on the newly created openthread project in the Workspace and go to Properties->"C/C++ Build"->"MCU Settings". Select the JN518x from the SDK MCUs list.
+5. Go to C/C++ Build->"Tool Chain Editor" and untick the "Display compatible toolchains only" checkbox. In the drop-down menu named "Current toolchain", select "NXP MCU Tools". Click "Apply and Close".
+6. Right click on the openthread project and select "Debug As"->"MCUXpresso IDE LinkServer (inc. CMSIS-DAP) probes"
+7. A window to select the binary will appear. Select "output/jn5189/bin/ot-<application>" and click Ok. Ignore the error message.
+8. Under the menu bar, towards the center of the screen, there is a green bug icon with a drop-down arrow next to it. Click on the arrow and select "Debug Configurations".
+9. In the right side of the Debug Configurations window, go to "C/C++ (NXP Semiconductors) MCU Application"->"openthread LinkServer Default".
+10. Make sure that in the "C/C++ Application:" text box contains "output\jn5189\bin\ot-<application>" path.
+11. Go to "GUI Flash Tool" tab. In "Target Operations"->Program->Options, select "bin" as the "Format to use for programming". Make sure the "Base address" is 0x0.
+12. Click Debug.
+13. A pop-up window entitled "Errors in Workspace" will appear. Click Proceed.
+14. The board is now flashed.
+
+[cmsis-dap]: https://os.mbed.com/handbook/CMSIS-DAP
+
+## Running the example
+
+1. Prepare two boards with the flashed `CLI Example` (as shown above). Make sure that the JN4 jumper is set to RX and the JN7 jumper is set to TX, connecting the LPC and JN UART0 pins.
+2. The CLI example uses UART connection. To view raw UART output, start a terminal
+   emulator like PuTTY and connect to the used COM port with the following UART settings:
+    - Baud rate: 115200
+    - 8 data bits
+    - 1 stop bit
+    - No parity
+    - No flow control
+
+3. Open a terminal connection on the first board and start a new Thread network.
+
+ ```bash
+ > panid 0xabcd
+ Done
+ > ifconfig up
+ Done
+ > thread start
+ Done
+ ```
+
+4. After a couple of seconds the node will become a Leader of the network.
+
+ ```bash
+ > state
+ Leader
+ ```
+
+5. Open a terminal connection on the second board and attach a node to the network.
+
+ ```bash
+ > panid 0xabcd
+ Done
+ > ifconfig up
+ Done
+ > thread start
+ Done
+ ```
+
+6. After a couple of seconds the second node will attach and become a Child.
+
+ ```bash
+ > state
+ Child
+ ```
+
+7. List all IPv6 addresses of the first board.
+
+ ```bash
+ > ipaddr
+ fdde:ad00:beef:0:0:ff:fe00:fc00
+ fdde:ad00:beef:0:0:ff:fe00:9c00
+ fdde:ad00:beef:0:4bcb:73a5:7c28:318e
+ fe80:0:0:0:5c91:c61:b67c:271c
+ ```
+
+8. Choose one of them and send an ICMPv6 ping from the second board.
+
+ ```bash
+ > ping fdde:ad00:beef:0:0:ff:fe00:fc00
+ 16 bytes from fdde:ad00:beef:0:0:ff:fe00:fc00: icmp_seq=1 hlim=64 time=8ms
+ ```
+
+For a list of all available commands, visit [OpenThread CLI Reference README.md][CLI].
+
+[CLI]: https://github.com/openthread/openthread/blob/master/src/cli/README.md
+
+## Known limitations
+
+While running the build process in "Ubuntu on Windows" bash, user can encounter build errors from unknown reasons. The current workaround is to re-run the "make -f examples/Makefile-jn5189" command.
+NCP applications have not been tested.

examples/platforms/jn5189/alarm.c

@@ -0,0 +1,231 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file implements the OpenThread platform abstraction for the alarm.
+ *
+ */
+
+#include "fsl_clock.h"
+#include "fsl_ctimer.h"
+#include "fsl_device_registers.h"
+#include "fsl_wtimer.h"
+#include <openthread/platform/alarm-milli.h>
+#include <openthread/platform/diag.h>
+
+#define ALARM_USE_CTIMER 0
+#define ALARM_USE_WTIMER 1
+
+/* Timer frequency in Hz needed for 1ms tick */
+#define TARGET_FREQ 1000U
+/* Wake Timer max count value that is loaded in the register */
+#define TIMER0_MAX_COUNT_VALUE 0xffffffff
+#define TIMER1_MAX_COUNT_VALUE 0x0fffffff
+
+static bool     sEventFired = false;
+static uint32_t refClk;
+
+#if ALARM_USE_CTIMER
+/* Match Configuration for Channel 0 */
+static ctimer_match_config_t sMatchConfig = {.enableCounterReset = false,
+                                             .enableCounterStop  = false,
+                                             .matchValue         = 0x00,
+                                             .outControl         = kCTIMER_Output_NoAction,
+                                             .outPinInitState    = false,
+                                             .enableInterrupt    = true};
+#else
+static uint32_t sRemainingTicks;
+#endif
+
+void JN5189AlarmInit(void)
+{
+#if ALARM_USE_CTIMER
+    ctimer_config_t config;
+    CTIMER_GetDefaultConfig(&config);
+
+    /* Get clk frequency and use prescale to lower it */
+    refClk = CLOCK_GetFreq(kCLOCK_Timer0);
+
+    config.prescale = refClk / TARGET_FREQ;
+    CTIMER_Init(CTIMER0, &config);
+    CTIMER_StartTimer(CTIMER0);
+
+    CTIMER_EnableInterrupts(CTIMER0, kCTIMER_Match0InterruptEnable);
+    NVIC_ClearPendingIRQ(Timer0_IRQn);
+    NVIC_EnableIRQ(Timer0_IRQn);
+
+#else
+    RESET_PeripheralReset(kWKT_RST_SHIFT_RSTn);
+    WTIMER_Init();
+
+    /* Get clk frequency and use prescale to lower it */
+    refClk = CLOCK_GetFreq(kCLOCK_Xtal32k);
+
+    /* Wake timer 0 is 41 bits long and is used for keepig the timestamp */
+    WTIMER_EnableInterrupts(WTIMER_TIMER0_ID);
+    /* Wake timer 1 is 28 bits long and is used for alarm events, including waking up the MCU
+       from sleep */
+    WTIMER_EnableInterrupts(WTIMER_TIMER1_ID);
+
+    /* Start wake timer 0 counter for timestamp - the counter counts down to 0 so a simple
+       substracion from TIMER0_MAX_COUNT_VALUE will give us the timestamp */
+    WTIMER_StartTimer(WTIMER_TIMER0_ID, TIMER0_MAX_COUNT_VALUE);
+#endif
+}
+
+void JN5189AlarmClean(void)
+{
+#if ALARM_USE_CTIMER
+    CTIMER_StopTimer(CTIMER0);
+    CTIMER_Deinit(CTIMER0);
+    CTIMER_DisableInterrupts(CTIMER0, kCTIMER_Match0InterruptEnable);
+    NVIC_ClearPendingIRQ(Timer0_IRQn);
+#else
+    WTIMER_StopTimer(WTIMER_TIMER0_ID);
+    WTIMER_StopTimer(WTIMER_TIMER1_ID);
+    WTIMER_DeInit();
+
+    NVIC_DisableIRQ(WAKE_UP_TIMER0_IRQn);
+    NVIC_ClearPendingIRQ(WAKE_UP_TIMER0_IRQn);
+    NVIC_DisableIRQ(WAKE_UP_TIMER1_IRQn);
+    NVIC_ClearPendingIRQ(WAKE_UP_TIMER1_IRQn);
+#endif
+}
+
+void JN5189AlarmProcess(otInstance *aInstance)
+{
+    if (sEventFired)
+    {
+#if OPENTHREAD_ENABLE_DIAG
+
+        if (otPlatDiagModeGet())
+        {
+            otPlatDiagAlarmFired(aInstance);
+        }
+        else
+#endif
+        {
+            otPlatAlarmMilliFired(aInstance);
+        }
+    }
+}
+
+void otPlatAlarmMilliStartAt(otInstance *aInstance, uint32_t aT0, uint32_t aDt)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+#if ALARM_USE_CTIMER
+    /* Load match register with current counter + app time */
+    sMatchConfig.matchValue = aT0 + aDt;
+
+    CTIMER_SetupMatch(CTIMER0, kCTIMER_Match_0, &sMatchConfig);
+#else
+    /* Calculate the difference between now and the requested timestamp aT0 - this time will be
+       substracted from the total time until the event needs to fire */
+    uint32_t timestamp = otPlatAlarmMilliGetNow();
+    timestamp          = timestamp - aT0;
+
+    uint64_t targetTicks = ((aDt - timestamp) * refClk) / TARGET_FREQ;
+
+    /* Because timer 1 is only 28 bits long we need to take into account and event longer than this
+       so we arm the timer with the maximum value and re-arm with the remaing time once it fires */
+    if (targetTicks < TIMER1_MAX_COUNT_VALUE)
+    {
+        WTIMER_StartTimer(WTIMER_TIMER1_ID, targetTicks);
+        sRemainingTicks = 0;
+    }
+    else
+    {
+        WTIMER_StartTimer(WTIMER_TIMER1_ID, TIMER1_MAX_COUNT_VALUE);
+        sRemainingTicks = targetTicks - TIMER1_MAX_COUNT_VALUE;
+    }
+
+#endif
+}
+
+void otPlatAlarmMilliStop(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    sEventFired = false;
+
+#if ALARM_USE_CTIMER
+    sMatchConfig.matchValue = 0;
+    CTIMER_SetupMatch(CTIMER0, kCTIMER_Match_0, &sMatchConfig);
+#else
+    sRemainingTicks = 0;
+    WTIMER_StopTimer(WTIMER_TIMER1_ID);
+#endif
+}
+
+uint32_t otPlatAlarmMilliGetNow(void)
+{
+#if ALARM_USE_CTIMER
+    return CTIMER0->TC;
+#else
+    uint32_t timestamp  = WTIMER_ReadTimerSafe(WTIMER_TIMER0_ID);
+    uint64_t tempTstamp = (TIMER0_MAX_COUNT_VALUE - timestamp);
+
+    tempTstamp *= TARGET_FREQ;
+    tempTstamp /= refClk;
+    return (uint32_t)tempTstamp;
+#endif
+}
+
+#if ALARM_USE_CTIMER
+/**
+ * Timer interrupt handler function.
+ *
+ */
+void CTIMER0_IRQHandler(void)
+{
+    uint32_t flags = CTIMER_GetStatusFlags(CTIMER0);
+    CTIMER_ClearStatusFlags(CTIMER0, flags);
+    sEventFired = true;
+}
+#else
+void WAKE_UP_TIMER0_DriverIRQHandler()
+{
+    WTIMER_ClearStatusFlags(WTIMER_TIMER0_ID);
+    WTIMER_StartTimer(WTIMER_TIMER0_ID, TIMER0_MAX_COUNT_VALUE);
+}
+void WAKE_UP_TIMER1_DriverIRQHandler()
+{
+    WTIMER_ClearStatusFlags(WTIMER_TIMER1_ID);
+    if (sRemainingTicks)
+    {
+        WTIMER_StartTimer(WTIMER_TIMER1_ID, sRemainingTicks);
+        sRemainingTicks = 0;
+    }
+    else
+    {
+        sEventFired = true;
+    }
+}
+#endif

examples/platforms/jn5189/diag.c

@@ -0,0 +1,89 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file implements the OpenThread platform abstraction for the diagnostics.
+ *
+ */
+
+#include <stdio.h>
+#include <openthread/config.h>
+#include <openthread/platform/alarm-milli.h>
+#include <openthread/platform/radio.h>
+
+#if OPENTHREAD_ENABLE_DIAG
+
+/**
+ * Diagnostics mode variables.
+ *
+ */
+static bool sDiagMode = false;
+
+void otPlatDiagProcess(otInstance *aInstance, int argc, char *argv[], char *aOutput, size_t aOutputMaxLen)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+    OT_UNUSED_VARIABLE(argc);
+
+    // Add more platform specific diagnostics features here.
+    snprintf(aOutput, aOutputMaxLen, "diag feature '%s' is not supported\r\n", argv[0]);
+}
+
+void otPlatDiagModeSet(bool aMode)
+{
+    sDiagMode = aMode;
+}
+
+bool otPlatDiagModeGet()
+{
+    return sDiagMode;
+}
+
+void otPlatDiagChannelSet(uint8_t aChannel)
+{
+    OT_UNUSED_VARIABLE(aChannel);
+}
+
+void otPlatDiagTxPowerSet(int8_t aTxPower)
+{
+    OT_UNUSED_VARIABLE(aTxPower);
+}
+
+void otPlatDiagRadioReceived(otInstance *aInstance, otRadioFrame *aFrame, otError aError)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+    OT_UNUSED_VARIABLE(aFrame);
+    OT_UNUSED_VARIABLE(aError);
+}
+
+void otPlatDiagAlarmCallback(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+}
+
+#endif // OPENTHREAD_ENABLE_DIAG

examples/platforms/jn5189/entropy.c

@@ -0,0 +1,70 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file implements an entropy source based on TRNG.
+ *
+ */
+
+#include "openthread/platform/entropy.h"
+#include "fsl_device_registers.h"
+#include "fsl_rng.h"
+#include <stdint.h>
+#include <stdlib.h>
+#include <utils/code_utils.h>
+
+void JN5189RandomInit(void)
+{
+    trng_config_t config;
+    uint32_t      seed;
+
+    TRNG_GetDefaultConfig(&config);
+    config.mode = trng_FreeRunning;
+
+    otEXPECT(TRNG_Init(RNG, &config) == kStatus_Success);
+
+    otEXPECT(TRNG_GetRandomData(RNG, &seed, sizeof(seed)) == kStatus_Success);
+
+    srand(seed);
+
+exit:
+    return;
+}
+
+otError otPlatEntropyGet(uint8_t *aOutput, uint16_t aOutputLength)
+{
+    otError status = OT_ERROR_NONE;
+
+    otEXPECT_ACTION((aOutput != NULL), status = OT_ERROR_INVALID_ARGS);
+
+    otEXPECT_ACTION(TRNG_GetRandomData(RNG, aOutput, aOutputLength) == kStatus_Success, status = OT_ERROR_FAILED);
+
+exit:
+    return status;
+}

examples/platforms/jn5189/flash.c

@@ -0,0 +1,295 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_flash.h"
+#include "openthread-core-jn5189-config.h"
+#include <utils/code_utils.h>
+#include <utils/flash.h>
+#include "openthread/platform/alarm-milli.h"
+
+#define USE_MEM_COPY_FOR_READ 0
+
+#define NUMBER_OF_INTEGERS 4
+#define ONE_READ 1
+#define BYTES_IN_ONE_READ (NUMBER_OF_INTEGERS * sizeof(uint32_t))
+#define NORMAL_READ_MODE 0
+#define ONE_PAGE 1
+#define BYTES_ALINGMENT 16
+
+uint8_t         pageBuffer[FLASH_PAGE_SIZE] __attribute__((aligned(4))) = {0};
+static uint32_t sNvFlashStartAddr;
+static uint32_t sNvFlashEndAddr;
+
+static bool     mapToNvFlashAddress(uint32_t *aAddress);
+static void     copyFromFlash(uint8_t *pDst, uint8_t *pSrc, uint32_t cBytes);
+static uint32_t blankCheckAndErase(uint8_t *pageAddr);
+
+otError utilsFlashInit(void)
+{
+    extern uint32_t __nv_storage_start_address;
+    extern uint32_t __nv_storage_end_address;
+
+    FLASH_Init(FLASH);
+
+    sNvFlashStartAddr = (uint32_t)&__nv_storage_start_address;
+    sNvFlashEndAddr   = (uint32_t)&__nv_storage_end_address;
+
+    return OT_ERROR_NONE;
+}
+
+uint32_t utilsFlashGetSize(void)
+{
+    return sNvFlashEndAddr - sNvFlashStartAddr;
+}
+
+otError utilsFlashErasePage(uint32_t aAddress)
+{
+    otError  error = OT_ERROR_INVALID_ARGS;
+    status_t status;
+    uint32_t address = aAddress;
+
+    /* Map address to NV Flash space and check boundaries */
+    if (mapToNvFlashAddress(&address))
+    {
+        /* If address is aligned to page size */
+        if ((address % FLASH_PAGE_SIZE) == 0)
+        {
+            error = OT_ERROR_NONE;
+
+            status = blankCheckAndErase((uint8_t *)address);
+            otEXPECT_ACTION((status & FLASH_DONE), error = OT_ERROR_FAILED);
+        }
+    }
+
+exit:
+    return error;
+}
+
+otError utilsFlashStatusWait(uint32_t aTimeout)
+{
+    otError  error = OT_ERROR_BUSY;
+    uint32_t start = otPlatAlarmMilliGetNow();
+
+    do
+    {
+        if (FLASH->INT_STATUS & FLASH_DONE)
+        {
+            error = OT_ERROR_NONE;
+            break;
+        }
+    } while (aTimeout && ((otPlatAlarmMilliGetNow() - start) < aTimeout));
+
+    return error;
+}
+
+uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
+{
+    uint32_t result = 0;
+    status_t status;
+    uint32_t address = aAddress;
+    uint32_t alignAddr;
+    uint32_t bytes;
+
+    /* Map address to NV Flash space and check boundaries */
+    if (mapToNvFlashAddress(&address))
+    {
+        /* Check to see if data is written outside NV Flash space */
+        if ((address + aSize) <= sNvFlashEndAddr)
+        {
+            alignAddr = address - (address % FLASH_PAGE_SIZE);
+            bytes     = (address - alignAddr);
+            result    = aSize;
+
+            if (bytes)
+            {
+                uint32_t unalignedBytes = FLASH_PAGE_SIZE - bytes;
+
+                if (unalignedBytes > aSize)
+                {
+                    unalignedBytes = aSize;
+                }
+
+                copyFromFlash(pageBuffer, (void *)alignAddr, FLASH_PAGE_SIZE);
+                memcpy(&pageBuffer[bytes], aData, unalignedBytes);
+
+                status = blankCheckAndErase((uint8_t *)alignAddr);
+                otEXPECT_ACTION((status & FLASH_DONE), result = 0);
+
+                status = FLASH_Program(FLASH, (uint32_t *)alignAddr, (uint32_t *)pageBuffer, FLASH_PAGE_SIZE);
+                otEXPECT_ACTION((status & FLASH_DONE), result = 0);
+
+                address += unalignedBytes;
+                /* if size is less than the distance to the end of program block
+                   unalignedBytes has been shrunk , after size is decremented it will become 0 */
+                aData += unalignedBytes;
+                aSize -= unalignedBytes;
+            }
+
+            bytes = aSize & ~(FLASH_PAGE_SIZE - 1U);
+
+            /* Now dest is on an aligned boundary */
+            /* bytes is an integer number of program blocks (pages) */
+            while (bytes)
+            {
+                status = blankCheckAndErase((uint8_t *)address);
+                otEXPECT_ACTION((status & FLASH_DONE), result = 0);
+
+                status = FLASH_Program(FLASH, (uint32_t *)address, (uint32_t *)aData, FLASH_PAGE_SIZE);
+                otEXPECT_ACTION((status & FLASH_DONE), result = 0);
+
+                address += FLASH_PAGE_SIZE;
+                aData += FLASH_PAGE_SIZE;
+                aSize -= FLASH_PAGE_SIZE;
+                bytes -= FLASH_PAGE_SIZE;
+            }
+
+            /* dest is still aligned because we have increased it by a multiple of the program block (page) */
+            if (aSize)
+            {
+                status = blankCheckAndErase((uint8_t *)address);
+                otEXPECT_ACTION((status & FLASH_DONE), result = 0);
+
+                status = FLASH_Program(FLASH, (uint32_t *)address, (uint32_t *)aData, aSize);
+                otEXPECT_ACTION((status & FLASH_DONE), result = 0);
+            }
+        }
+    }
+
+exit:
+    return result;
+}
+
+uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
+{
+    uint32_t address = aAddress;
+    uint32_t result  = 0;
+
+    /* Map address to NV Flash space and check boundaries */
+    if (mapToNvFlashAddress(&address))
+    {
+        /* Check to see if data is read outside NV Flash space */
+        if ((address + aSize) <= sNvFlashEndAddr)
+        {
+            copyFromFlash(aData, (uint8_t *)address, aSize);
+            result = aSize;
+        }
+    }
+
+    return result;
+}
+
+static bool mapToNvFlashAddress(uint32_t *aAddress)
+{
+    bool     status  = true;
+    uint32_t address = *aAddress + sNvFlashStartAddr;
+
+    if ((address < sNvFlashStartAddr) || (address > sNvFlashEndAddr))
+    {
+        status = false;
+    }
+    else
+    {
+        *aAddress = address;
+    }
+
+    return status;
+}
+
+uint32_t blankCheckAndErase(uint8_t *pageAddr)
+{
+    uint32_t status = FLASH_BlankCheck(FLASH, pageAddr, pageAddr + FLASH_PAGE_SIZE - 1);
+    if (status & FLASH_FAIL)
+    {
+        status = FLASH_Erase(FLASH, pageAddr, (pageAddr + FLASH_PAGE_SIZE - 1));
+    }
+    else
+    {
+        status = FLASH_DONE;
+    }
+
+    return status;
+}
+
+static void copyFromFlash(uint8_t *pDst, uint8_t *pSrc, uint32_t cBytes)
+{
+#if !USE_MEM_COPY_FOR_READ
+
+    uint32_t nbOfReads;
+    uint32_t aligningOffset;
+    uint32_t temp[NUMBER_OF_INTEGERS];
+    uint32_t bytesLeft   = cBytes;
+    uint32_t bytesToRead = 0;
+
+    /* Flash driver reads 16 bytes in one run, so calculating the number of reads from Flash
+       is needed */
+    nbOfReads = cBytes / BYTES_IN_ONE_READ;
+    if (cBytes % BYTES_IN_ONE_READ)
+    {
+        nbOfReads++;
+    }
+
+    /* calculate aligning offset -> the number of bytes from a 16 byte aligned address the
+       read address is located */
+    aligningOffset = (uint32_t)pSrc % BYTES_ALINGMENT;
+
+    for (uint32_t i = 0; i < nbOfReads; i++)
+    {
+        /* Read from Flash */
+        FLASH_Read(FLASH, (uint8_t *)(pSrc - aligningOffset + i * BYTES_IN_ONE_READ), NORMAL_READ_MODE,
+                   (uint32_t *)temp);
+
+        if (0 == i)
+        {
+            bytesToRead =
+                (bytesLeft < BYTES_IN_ONE_READ - aligningOffset) ? bytesLeft : BYTES_IN_ONE_READ - aligningOffset;
+
+            /* first read must take into account align offset */
+            memcpy((void *)pDst, (void *)temp + aligningOffset, bytesToRead);
+            bytesLeft -= bytesToRead;
+            pDst += bytesToRead;
+        }
+        else
+        {
+            bytesToRead = (bytesLeft < BYTES_IN_ONE_READ) ? bytesLeft : BYTES_IN_ONE_READ;
+            memcpy((void *)pDst, (void *)temp, bytesToRead);
+            bytesLeft -= bytesToRead;
+            pDst += bytesToRead;
+        }
+    }
+
+#else
+    while (cBytes)
+    {
+        *(pDst) = *(pSrc);
+        pDst    = pDst + 1;
+        pSrc    = pSrc + 1;
+        cBytes--;
+    }
+#endif
+}

examples/platforms/jn5189/jn5189-mbedtls-config.h

@@ -0,0 +1,248 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef JN5189_MBEDTLS_CONFIG_H
+#define JN5189_MBEDTLS_CONFIG_H
+
+#if defined(MBEDTLS_ECP_WINDOW_SIZE)
+#undef MBEDTLS_ECP_WINDOW_SIZE
+#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */
+#endif
+
+#if defined(MBEDTLS_ECP_FIXED_POINT_OPTIM)
+#undef MBEDTLS_ECP_FIXED_POINT_OPTIM
+#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */
+#endif
+
+/**
+ * \def MBEDTLS_AES_ALT
+ *
+ * Enable hardware acceleration for the AES block cipher
+ *
+ * See MBEDTLS_AES_C for more information.
+ */
+#define MBEDTLS_AES_ALT
+
+#if defined(MBEDTLS_AES_ALT)
+/**************************** KSDK ********************************************/
+#include "fsl_device_registers.h"
+
+/* Enable LTC use in library if there is LTC on chip. */
+#if defined(FSL_FEATURE_SOC_LTC_COUNT) && (FSL_FEATURE_SOC_LTC_COUNT > 0)
+#include "fsl_ltc.h"
+
+#define LTC_INSTANCE LTC0 /* LTC base register.*/
+
+#if FSL_FEATURE_LTC_HAS_SHA
+#define MBEDTLS_FREESCALE_LTC_SHA1   /* Enable use of LTC SHA.*/
+#define MBEDTLS_FREESCALE_LTC_SHA256 /* Enable use of LTC SHA256.*/
+#endif
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+#define MBEDTLS_FREESCALE_LTC_DES /* Enable use of LTC DES.*/
+#endif
+#define MBEDTLS_FREESCALE_LTC_AES /* Enable use of LTC AES.*/
+#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM
+#define MBEDTLS_FREESCALE_LTC_AES_GCM /* Enable use of LTC AES GCM.*/
+#endif
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+#define MBEDTLS_FREESCALE_LTC_PKHA /* Enable use of LTC PKHA.*/
+#define FREESCALE_PKHA_INT_MAX_BYTES 256
+#endif
+#endif
+
+/* Enable MMCAU use in library if there is MMCAU on chip. */
+#if defined(FSL_FEATURE_SOC_MMCAU_COUNT) && (FSL_FEATURE_SOC_MMCAU_COUNT > 0)
+#include "fsl_mmcau.h"
+
+#define MBEDTLS_FREESCALE_MMCAU_MD5    /* Enable use of MMCAU MD5.*/
+#define MBEDTLS_FREESCALE_MMCAU_SHA1   /* Enable use of MMCAU SHA1.*/
+#define MBEDTLS_FREESCALE_MMCAU_SHA256 /* Enable use of MMCAU SHA256.*/
+#define MBEDTLS_FREESCALE_MMCAU_DES    /* Enable use of MMCAU DES, when LTC is disabled.*/
+#define MBEDTLS_FREESCALE_MMCAU_AES    /* Enable use of MMCAU AES, when LTC is disabled.*/
+#endif
+
+/* Enable CAU3 use in library if there is CAU3 on chip. */
+#if defined(FSL_FEATURE_SOC_CAU3_COUNT) && (FSL_FEATURE_SOC_CAU3_COUNT > 0)
+#include "cau3_pkha.h"
+#include "fsl_cau3.h"
+
+#define MBEDTLS_CAU3_COMPLETION_SIGNAL CAU3_CC_CMD_EVT
+#define MBEDTLS_SHA256_ALT_NO_224
+
+#define MBEDTLS_FREESCALE_CAU3_AES    /* Enable use of CAU3 AES.*/
+#define MBEDTLS_FREESCALE_CAU3_SHA256 /* Enable use of CAU3 SHA256.*/
+#define MBEDTLS_FREESCALE_CAU3_PKHA   /* Enable use of CAU3 PKHA.*/
+#define FREESCALE_PKHA_INT_MAX_BYTES 512
+#endif
+
+#if defined(MBEDTLS_FREESCALE_LTC_PKHA) || defined(MBEDTLS_FREESCALE_CAU3_PKHA)
+/*
+ * This FREESCALE_PKHA_LONG_OPERANDS_ENABLE macro can be defined.
+ * In such a case both software and hardware algorithm for TFM is linked in.
+ * The decision for which algorithm is used is determined at runtime
+ * from size of inputs. If inputs and result can fit into LTC (see FREESCALE_PKHA_INT_MAX_BYTES)
+ * then we call hardware algorithm, otherwise we call software algorithm.
+ *
+ * Note that mbedTLS algorithms break modular operations unefficiently into two steps.
+ * First is normal operation, for example non-modular multiply, which can produce number
+ * with greater size than operands. Second is modular reduction.
+ * The implication of this is that if for example FREESCALE_PKHA_INT_MAX_BYTES is 256 (2048 bits),
+ * RSA-2048 still requires the FREESCALE_PKHA_LONG_OPERANDS_ENABLE macro to be defined,
+ * otherwise it fails at runtime.
+ */
+//#define FREESCALE_PKHA_LONG_OPERANDS_ENABLE
+#endif
+
+/* Enable AES use in library if there is AES on chip. */
+#if defined(FSL_FEATURE_SOC_AES_COUNT) && (FSL_FEATURE_SOC_AES_COUNT > 0)
+#include "fsl_aes.h"
+
+#define AES_INSTANCE AES0             /* AES base register.*/
+#define MBEDTLS_FREESCALE_LPC_AES     /* Enable use of LPC AES.*/
+#define MBEDTLS_FREESCALE_LPC_AES_GCM /* Enable use of LPC AES GCM.*/
+
+#endif
+
+/* Enable SHA use in library if there is SHA on chip. */
+#if defined(FSL_FEATURE_SOC_SHA_COUNT) && (FSL_FEATURE_SOC_SHA_COUNT > 0)
+#include "fsl_sha.h"
+
+//#define SHA_INSTANCE SHA0            /* AES base register.*/
+#define MBEDTLS_FREESCALE_LPC_SHA1 /* Enable use of LPC SHA.*/
+//#define MBEDTLS_FREESCALE_LPC_SHA256 /* Enable use of LPC SHA256.*/
+
+#endif
+
+/* Define ALT MMCAU & LTC functions. Do not change it. */
+#if defined(MBEDTLS_FREESCALE_MMCAU_DES) || defined(MBEDTLS_FREESCALE_LTC_DES)
+#define MBEDTLS_DES_SETKEY_ENC_ALT
+#define MBEDTLS_DES_SETKEY_DEC_ALT
+#define MBEDTLS_DES_CRYPT_ECB_ALT
+#define MBEDTLS_DES3_CRYPT_ECB_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_DES)
+#define MBEDTLS_DES_CRYPT_CBC_ALT
+#define MBEDTLS_DES3_CRYPT_CBC_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES) || defined(MBEDTLS_FREESCALE_MMCAU_AES) || \
+    defined(MBEDTLS_FREESCALE_LPC_AES) || defined(MBEDTLS_FREESCALE_CAU3_AES)
+#define MBEDTLS_AES_SETKEY_ENC_ALT
+#define MBEDTLS_AES_SETKEY_DEC_ALT
+#define MBEDTLS_AES_ENCRYPT_ALT
+#define MBEDTLS_AES_DECRYPT_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES)
+#define MBEDTLS_AES_CRYPT_CBC_ALT
+#define MBEDTLS_AES_CRYPT_CTR_ALT
+#define MBEDTLS_CCM_CRYPT_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES_GCM) || defined(MBEDTLS_FREESCALE_LPC_AES_GCM)
+#define MBEDTLS_GCM_CRYPT_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_PKHA) || defined(MBEDTLS_FREESCALE_CAU3_PKHA)
+#define MBEDTLS_MPI_ADD_ABS_ALT
+#define MBEDTLS_MPI_SUB_ABS_ALT
+#define MBEDTLS_MPI_MUL_MPI_ALT
+#define MBEDTLS_MPI_MOD_MPI_ALT
+#define MBEDTLS_MPI_EXP_MOD_ALT
+#define MBEDTLS_MPI_GCD_ALT
+#define MBEDTLS_MPI_INV_MOD_ALT
+#define MBEDTLS_MPI_IS_PRIME_ALT
+#if defined(MBEDTLS_FREESCALE_LTC_PKHA)
+#define MBEDTLS_ECP_MUL_COMB_ALT
+#define MBEDTLS_ECP_ADD_ALT
+#endif
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_SHA1) || defined(MBEDTLS_FREESCALE_LPC_SHA1)
+#define MBEDTLS_SHA1_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_SHA256) || defined(MBEDTLS_FREESCALE_LPC_SHA256)
+//#define MBEDTLS_SHA256_ALT
+/*
+ * LPC SHA module does not support SHA-224.
+ *
+ * Since mbed TLS does not provide separate APIs for SHA-224 and SHA-256
+ * and SHA-224 is not widely used, this implementation provides HW accelerated SHA-256 only
+ * and SHA-224 is not available at all (calls will fail).
+ *
+ * To use SHA-224 on LPC, do not define MBEDTLS_SHA256_ALT and both SHA-224 and SHA-256 will use
+ * original mbed TLS software implementation.
+ */
+#if defined(MBEDTLS_FREESCALE_LPC_SHA256)
+#define MBEDTLS_SHA256_ALT_NO_224
+#endif
+#endif
+#if defined(MBEDTLS_FREESCALE_MMCAU_MD5)
+#define MBEDTLS_MD5_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_MMCAU_SHA1)
+#define MBEDTLS_SHA1_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_MMCAU_SHA256)
+#define MBEDTLS_SHA256_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_CAU3_SHA256)
+#define MBEDTLS_SHA256_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_CAU3_AES)
+#define MBEDTLS_AES_ALT_NO_192
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES)
+#if !defined(FSL_FEATURE_LTC_HAS_AES192) || !FSL_FEATURE_LTC_HAS_AES192
+#define MBEDTLS_AES_ALT_NO_192
+#endif
+#if !defined(FSL_FEATURE_LTC_HAS_AES256) || !FSL_FEATURE_LTC_HAS_AES256
+#define MBEDTLS_AES_ALT_NO_256
+#endif
+#endif
+#if defined(MBEDTLS_FREESCALE_LPC_AES)
+#define MBEDTLS_AES_CRYPT_CBC_ALT
+#define MBEDTLS_AES_CRYPT_CFB_ALT
+#define MBEDTLS_AES_CRYPT_CTR_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LPC_SHA1)
+#define MBEDTLS_SHA1_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LPC_SHA256)
+#define MBEDTLS_SHA256_PROCESS_ALT
+#endif
+
+#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
+#include "FreeRTOS.h"
+
+void *pvPortCalloc(size_t num, size_t size); /*Calloc for HEAP3.*/
+
+#define MBEDTLS_PLATFORM_MEMORY
+#define MBEDTLS_PLATFORM_STD_CALLOC pvPortCalloc
+#define MBEDTLS_PLATFORM_STD_FREE vPortFree
+
+#endif /* USE_RTOS*/
+/**************************** KSDK end ****************************************/
+#endif /* MBEDTLS_AES_ALT || MBEDTLS_SHA256_ALT */
+
+#endif // JN5189_MBEDTLS_CONFIG_H

examples/platforms/jn5189/jn5189.ld

@@ -0,0 +1,303 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   GCC linker script for JN5189.
+ */
+
+/*
+ * stack size for the boot rom during warm boot and application
+ * 256 is sufficient (pwrm_test) but keep it large to 1024
+ */
+BOOT_RESUME_STACK_SIZE = 1024;
+
+/* Set Stack size to 4K minus 32Bytes reserved for ROM code at end of BANK7 so
+   the stack fits in BANK7. In practice the active stack size at the time of
+   going to sleep is more important than the total available stack size */
+STACK_SIZE             = (4096 - 32);
+
+MEM_RAM0_BASE = 0x4000400;
+MEM_RAM0_SIZE = 0x0015c00;
+
+MEMORY
+{
+  /* Define each memory region. RAM0 definition leaves the first 1kB for the
+     boot code */
+  Flash640 (rx) : ORIGIN = 0, LENGTH = 0x00a0000            /* 640K bytes (alias Flash) */
+  RAM0 (rwx)    : ORIGIN = 0x4000400,  LENGTH = 0x0015c00   /* 87K bytes (alias RAM) */
+  RAM1 (rwx)    : ORIGIN = 0x4020000,      LENGTH = 0x10000 /* 64K bytes (alias RAM2) */
+}
+
+/* Define a symbol for the top of each memory region */
+__top_RAM0      = MEM_RAM0_BASE + MEM_RAM0_SIZE; /* 87K bytes */
+
+HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x2F4;
+
+/*** flash memory characteristics definitions required for OTA ***/
+m_flash_start   = 0x00000000;
+m_flash_end     = 0x0009FFFF;
+m_flash_size    = 0x000A0000;
+m_sector_size   = 512;
+m_fsl_prodInfo_size = m_sector_size;
+
+m_fsl_prodInfo_end                             = m_flash_size - 17 * m_sector_size - 1;
+m_fsl_prodInfo_start                           = m_fsl_prodInfo_end - m_fsl_prodInfo_size + 1;
+
+NV_STORAGE_MAX_SECTORS                         = 64;
+NV_STORAGE_SIZE                                = NV_STORAGE_MAX_SECTORS * m_sector_size;
+NV_STORAGE_END_ADDRESS                         = m_fsl_prodInfo_start - 1;
+NV_STORAGE_START_ADDRESS                       = NV_STORAGE_END_ADDRESS - NV_STORAGE_SIZE + 1;
+
+INT_STORAGE_END                                = NV_STORAGE_START_ADDRESS - 1;
+INT_STORAGE_START                              = 0x48000;
+INT_STORAGE_SIZE                               = INT_STORAGE_END - INT_STORAGE_START;
+
+FREESCALE_PROD_DATA_BASE_ADDR                  = m_fsl_prodInfo_start;
+INT_STORAGE_SECTOR_SIZE                        = m_sector_size;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+    /* MAIN TEXT SECTION */
+    .header : ALIGN(4)
+    {
+        _flash_start = ABSOLUTE(.);
+        _flash_beg = ABSOLUTE(.);
+
+        FILL(0xff)
+        __vectors_start__ = ABSOLUTE(.) ;
+        KEEP(*(.isr_vector))
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data));
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2));
+        LONG(  SIZEOF(.data_RAM2));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+
+        FILL(0xff)
+        . = ALIGN (0x10);
+    } >Flash640
+
+    .ro_nonce : ALIGN(0x10)
+    {
+        _FlsNonceStart = ABSOLUTE(.);
+        *(.ro_nonce) /* nonce value is 16 bytes.*/
+        FILL(0xff)
+        . = ALIGN (0x10);
+    } > Flash640
+
+    .ro_ota_header : ALIGN(0x10)
+    {
+        _enc_start = ABSOLUTE(.);
+        _enc_offset = (_enc_start & 0x0000000F);
+        _FlsOtaHeader = ABSOLUTE(.);
+        *(.ro_ota_header) /* Ota Header 69 bytes*/
+        FILL(0xff)
+        . = ALIGN (0x10);
+    } > Flash640
+
+    .ro_se_lnkKey (ALIGN((. - _enc_offset), 16) + _enc_offset):
+    {
+        _FlsLinkKey = ABSOLUTE(.);
+        *(.ro_se_lnkKey)  /* Link Key 16 bytes*/
+        FILL(0xff)
+        . = ALIGN (0x10);
+    } > Flash640
+
+    .filler :
+    {
+        BYTE(0xff)
+        FILL(0xff);
+        . = ALIGN(0x40);
+    } > Flash640
+
+    .text : ALIGN(0x40)
+    {
+        FILL(0xff)
+
+       *(.after_vectors*)
+       *(.text*)
+        *(.rodata .rodata.* .constdata .constdata.*)
+        . = ALIGN(4);
+    } > Flash640
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+       FILL(0xff)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > Flash640
+    __exidx_start = .;
+
+    .ARM.exidx : ALIGN(4)
+    {
+       FILL(0xff)
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > Flash640
+    __exidx_end = .;
+
+    _etext = .;
+
+    /* RAM1/RAM2 (different names for same thing) SECTION */
+    /* RAM1 contents are specified before RAM0 as they have specific input
+       sections and we do not want the RAM0 wildcards to catch them */
+    /* DATA section for RAM1 */
+    .data_RAM2 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM2 = .) ;
+        *(.ramfunc.$RAM2)
+        *(.ramfunc.$RAM1)
+        *(.data.$RAM2*)
+        *(.data.$RAM1*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM2 = .) ;
+     } > RAM1 AT>Flash640
+
+    /* MAIN DATA SECTION */
+    .uninit_RESERVED : ALIGN(4)
+    {
+        KEEP(*(.bss.$RESERVED*))
+        . = ALIGN(4) ;
+        _end_uninit_RESERVED = .;
+    } > RAM0
+
+    /* Main DATA section (RAM0) */
+    .data : ALIGN(4)
+    {
+       FILL(0xff)
+       _data = . ;
+       *(vtable)
+       *(.ramfunc*)
+       *(.data*)
+       . = ALIGN(4) ;
+       _edata = . ;
+    } > RAM0 AT>Flash640
+
+
+    /* BSS section for RAM1 */
+    .bss_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM2 = .) ;
+       *(.bss.$RAM2*)
+       *(.bss.$RAM1*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM2 = .) ;
+    } > RAM1
+
+    /* MAIN BSS SECTION */
+    .bss (NOLOAD) : ALIGN(4)
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        *(g_u32NwkFrameCounter)
+        . = ALIGN(4) ;
+        _ebss = .;
+
+        PROVIDE(end = .);
+    } > RAM0
+
+    /* BSS section for MAC buffers */
+    .bss_MAC (NOLOAD) : ALIGN(4)
+    {
+       /* MAC buffer section: must be within 128kB block. __mac_buffer_base is
+          defined further down to be on 128kB alignment */
+        __mac_buffer_start = .;
+       *(.mac_buffer)
+
+        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+    } > RAM0
+
+    /* HEAP */
+    .heap (NOLOAD): ALIGN(4)
+    {
+        _heap = .;
+        . += HEAP_SIZE;
+        . = ALIGN(4) ;
+        _end_heap = .;
+    } > RAM0
+
+    /* NOINIT section for RAM1 */
+    .noinit_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       *(.noinit.$RAM2*)
+       *(.noinit.$RAM1*)
+       . = ALIGN(4) ;
+    } > RAM1
+
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        *(.noinit*)
+        . = ALIGN(4) ;
+        _end_noinit = .;
+    } > RAM0
+
+    /* stack for rom boot during warm resume */
+    .boot_resume_stack (NOLOAD): ALIGN(4)
+    {
+        _boot_resume_stack = .;
+        *(.boot_resume_stack*)
+        . += BOOT_RESUME_STACK_SIZE;
+        . = ALIGN(4) ;
+        _end_boot_resume_stack = .;
+    } > RAM0
+
+    __nv_storage_end_address = NV_STORAGE_END_ADDRESS;
+    __nv_storage_start_address = NV_STORAGE_START_ADDRESS;
+
+    PROVIDE(_vStackTop = __top_RAM0 - 32);
+    PROVIDE(__mac_buffer_base = (__mac_buffer_start & 0xfffe0000));
+    PROVIDE(BOOT_GetStartPowerMode = 0x03000e9d);
+    PROVIDE(ROM_GetFlash = 0x03000e0d);
+    PROVIDE(pmc_reset_get_cause = 0x030046e9);
+    PROVIDE(psector_ReadIeee802_15_4_MacId1 = 0x030053b1);
+    PROVIDE(Chip_LOWPOWER_ChipSoftwareReset = 0x03003fa1);
+
+    __StackLimit = _vStackTop - STACK_SIZE;
+    ASSERT(__StackLimit >= _end_boot_resume_stack, "Possible stack corruption with data/bss/boot_stack")
+}

examples/platforms/jn5189/logging.c

@@ -0,0 +1,92 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file logging.c
+ * Platform abstraction for the logging
+ *
+ */
+
+#include "platform-jn5189.h"
+#include <openthread-core-config.h>
+#include <utils/code_utils.h>
+#include <openthread/config.h>
+#include <openthread/platform/logging.h>
+#include <openthread/platform/toolchain.h>
+#include <openthread/platform/uart.h>
+
+#include "stdio.h"
+#include "string.h"
+
+#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED) || \
+    (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_NCP_SPINEL)
+
+/* defines */
+#define TX_BUFFER_SIZE 256 /* Length of the send buffer */
+#define EOL_CHARS "\r\n"   /* End of Line Characters */
+#define EOL_CHARS_LEN 2    /* Length of EOL */
+
+/* static functions */
+static void JN5189LogOutput(const char *aFormat, va_list ap);
+
+/* static variables */
+static char sTxBuffer[TX_BUFFER_SIZE + 1]; /* Transmit Buffer */
+
+OT_TOOL_WEAK void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, ...)
+{
+    OT_UNUSED_VARIABLE(aLogLevel);
+    OT_UNUSED_VARIABLE(aLogRegion);
+    va_list ap;
+
+    va_start(ap, aFormat);
+    JN5189LogOutput(aFormat, ap);
+    va_end(ap);
+}
+
+/**
+ * Write Blocking data
+ *
+ * @param[in]    aFormat*     A pointer to the format string
+ * @param[in]    ap           Variable List Argument
+ *
+ */
+static void JN5189LogOutput(const char *aFormat, va_list ap)
+{
+    int len = 0;
+
+    len = vsnprintf(sTxBuffer, TX_BUFFER_SIZE - EOL_CHARS_LEN, aFormat, ap);
+    otEXPECT(len >= 0);
+    memcpy(sTxBuffer + len, EOL_CHARS, EOL_CHARS_LEN);
+    len += EOL_CHARS_LEN;
+    JN5189WriteBlocking((const uint8_t *)sTxBuffer, len);
+
+exit:
+    return;
+}
+
+#endif

examples/platforms/jn5189/misc.c

@@ -0,0 +1,93 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "openthread/platform/misc.h"
+#include "fsl_device_registers.h"
+#include "fsl_power.h"
+#include "fsl_reset.h"
+
+void otPlatReset(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    RESET_SystemReset();
+
+    while (1)
+    {
+    }
+}
+
+otPlatResetReason otPlatGetResetReason(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    otPlatResetReason reason;
+    reset_cause_t     cause = POWER_GetResetCause();
+
+    if (cause & RESET_POR)
+    {
+        reason = OT_PLAT_RESET_REASON_POWER_ON;
+    }
+    else if ((cause & RESET_SYS_REQ) || (cause & RESET_SW_REQ))
+    {
+        reason = OT_PLAT_RESET_REASON_SOFTWARE;
+    }
+    else if (cause & RESET_WDT)
+    {
+        reason = OT_PLAT_RESET_REASON_WATCHDOG;
+    }
+    else if (cause & RESET_EXT_PIN)
+    {
+        reason = OT_PLAT_RESET_REASON_EXTERNAL;
+    }
+    else if (cause & RESET_BOR)
+    {
+        reason = OT_PLAT_RESET_REASON_FAULT;
+    }
+    else if ((cause & RESET_WAKE_DEEP_PD) || (cause & RESET_WAKE_PD))
+    {
+        reason = OT_PLAT_RESET_REASON_ASSERT;
+    }
+    else
+    {
+        reason = OT_PLAT_RESET_REASON_OTHER;
+    }
+
+    return reason;
+}
+
+void otPlatAssertFail(const char *aFilename, int aLineNumber)
+{
+    OT_UNUSED_VARIABLE(aFilename);
+    OT_UNUSED_VARIABLE(aLineNumber);
+}
+
+void otPlatWakeHost(void)
+{
+    /* TODO */
+}

examples/platforms/jn5189/openthread-core-jn5189-config-check.h

@@ -0,0 +1,42 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OPENTHREAD_CORE_JN5189_CONFIG_CHECK_H_
+#define OPENTHREAD_CORE_JN5189_CONFIG_CHECK_H_
+
+#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
+#error "Platform jn5189 doesn't support configuration option: OPENTHREAD_CONFIG_TIME_SYNC_ENABLE"
+#endif
+
+#ifndef RADIO_CONFIG_915MHZ_OQPSK_SUPPORT
+#if OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT
+#error "Platform jn5189 not configured to support configuration option: OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT"
+#endif
+#endif
+
+#endif /* OPENTHREAD_CORE_JN5189_CONFIG_CHECK_H_ */

examples/platforms/jn5189/openthread-core-jn5189-config.h

@@ -0,0 +1,194 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file includes jn5189 compile-time configuration constants
+ *   for OpenThread.
+ */
+
+#ifndef OPENTHREAD_CORE_JN5189_CONFIG_H_
+#define OPENTHREAD_CORE_JN5189_CONFIG_H_
+
+/**
+ * @def OPENTHREAD_CONFIG_LOG_OUTPUT
+ *
+ * The emsk platform provides an otPlatLog() function.
+ */
+#ifndef OPENTHREAD_CONFIG_LOG_OUTPUT /* allow command line override */
+#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED
+#endif
+
+/**
+ * @def OPENTHREAD_CONFIG_PLATFORM_INFO
+ *
+ * The platform-specific string to insert into the OpenThread version string.
+ *
+ */
+#define OPENTHREAD_CONFIG_PLATFORM_INFO "JN5189"
+
+/**
+ * @def SETTINGS_CONFIG_BASE_ADDRESS
+ *
+ * The base address of settings.
+ *
+ */
+#define SETTINGS_CONFIG_BASE_ADDRESS 0
+
+/**
+ * @def SETTINGS_CONFIG_PAGE_SIZE
+ *
+ * The page size of settings.
+ *
+ */
+#define SETTINGS_CONFIG_PAGE_SIZE 0x200
+
+/**
+ * @def SETTINGS_CONFIG_PAGE_NUM
+ *
+ * The page number of settings.
+ *
+ */
+
+#define SETTINGS_CONFIG_PAGE_NUM 64
+
+/**
+ * @def RADIO_CONFIG_SRC_MATCH_ENTRY_NUM
+ *
+ * The number of source address table entries.
+ *
+ */
+#define RADIO_CONFIG_SRC_MATCH_ENTRY_NUM 128
+
+/**
+ * @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_RETRANSMIT
+ *
+ * Define to 1 if you want to enable software retransmission logic.
+ *
+ */
+/* TODO */
+
+/**
+ * @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_CSMA_BACKOFF
+ *
+ * Define to 1 if you want to enable software CSMA-CA backoff logic.
+ *
+ */
+/* TODO */
+
+/**
+ * @def OPENTHREAD_CONFIG_NCP_UART_ENABLE
+ *
+ * Define to 1 to enable NCP UART support.
+ *
+ */
+#define OPENTHREAD_CONFIG_NCP_UART_ENABLE 1
+
+/**
+ * @def OPENTHREAD_SETTINGS_RAM
+ *
+ * Define to 1 if you want to use JN589 Flash implementation.
+ *
+ */
+#ifdef OPENTHREAD_SETTINGS_RAM
+#undef OPENTHREAD_SETTINGS_RAM
+#endif
+#define OPENTHREAD_SETTINGS_RAM 1
+
+/**
+ * @def OPENTHREAD_CONFIG_NCP_TX_BUFFER_SIZE
+ *
+ * The size of NCP message buffer in bytes.
+ *
+ */
+#define OPENTHREAD_CONFIG_NCP_TX_BUFFER_SIZE 1024
+
+/**
+ * @def OPENTHREAD_CONFIG_COAP_API_ENABLE
+ *
+ * Define to 1 to enable the CoAP API.
+ *
+ */
+#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE
+ *
+ * Define to 1 to enable the CoAP Secure API.
+ *
+ */
+#define OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_JOINER_ENABLE
+ *
+ * Define to 1 to enable Joiner support.
+ *
+ */
+#define OPENTHREAD_CONFIG_JOINER_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_COMMISSIONER_ENABLE
+ *
+ * Define to 1 to enable Commissioner support.
+ *
+ */
+#define OPENTHREAD_CONFIG_COMMISSIONER_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE
+ *
+ * Define to 1 to enable UDP forward support.
+ *
+ */
+#define OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE
+ *
+ * Define to 1 to enable the Border Router service.
+ *
+ */
+#define OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE
+ *
+ * Define to 1 to enable the DHCP CLIENT service.
+ *
+ */
+#define OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE
+ *
+ * Define to 1 to enable the DHCP SERVER service.
+ *
+ */
+#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 1
+#endif // OPENTHREAD_CORE_JN5189_CONFIG_H_

examples/platforms/jn5189/platform-jn5189.h

@@ -0,0 +1,93 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file includes the platform-specific initializers.
+ *
+ */
+
+#ifndef PLATFORM_KWJN5189_H_
+#define PLATFORM_KWJN5189_H_
+
+#include <openthread-core-config.h>
+#include <openthread/config.h>
+
+#include <stdint.h>
+
+#include <openthread/instance.h>
+
+/**
+ * This function initializes the alarm service used by OpenThread.
+ *
+ */
+void JN5189AlarmInit(void);
+
+/**
+ * This function performs alarm driver processing.
+ *
+ * @param[in]  aInstance  The OpenThread instance structure.
+ *
+ */
+void JN5189AlarmProcess(otInstance *aInstance);
+
+/**
+ * This function initializes the radio service used by OpenThread.
+ *
+ */
+void JN5189RadioInit(void);
+
+/**
+ * This function performs radio driver processing.
+ *
+ * @param[in]  aInstance  The OpenThread instance structure.
+ *
+ */
+void JN5189RadioProcess(otInstance *aInstance);
+
+/**
+ * This function initializes the random number service used by OpenThread.
+ *
+ */
+void JN5189RandomInit(void);
+
+/**
+ * This function performs UART driver processing.
+ *
+ */
+void JN5189UartProcess(void);
+
+/**
+ * This function performs UART Blocking Send
+ *
+ * @param[in]  aBuf  Buffer to be sent over UART
+ * @param[in]  len   Length of the above buffer
+ *
+ */
+void JN5189WriteBlocking(const uint8_t *aBuf, uint32_t len);
+#endif // PLATFORM_JN5189_H_

examples/platforms/jn5189/random.c

@@ -0,0 +1,75 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file implements a random number generator.
+ *
+ */
+
+#include "openthread/platform/random.h"
+#include "fsl_device_registers.h"
+#include "fsl_rng.h"
+#include <stdint.h>
+#include <stdlib.h>
+#include <utils/code_utils.h>
+
+void JN5189RandomInit(void)
+{
+    trng_config_t config;
+    uint32_t      seed;
+
+    TRNG_GetDefaultConfig(&config);
+    config.mode = trng_FreeRunning;
+
+    otEXPECT(TRNG_Init(RNG, &config) == kStatus_Success);
+
+    otEXPECT(TRNG_GetRandomData(RNG, &seed, sizeof(seed)) == kStatus_Success);
+
+    srand(seed);
+
+exit:
+    return;
+}
+
+uint32_t otPlatRandomGet(void)
+{
+    return (uint32_t)rand();
+}
+
+otError otPlatRandomGetTrue(uint8_t *aOutput, uint16_t aOutputLength)
+{
+    otError status = OT_ERROR_NONE;
+
+    otEXPECT_ACTION((aOutput != NULL), status = OT_ERROR_INVALID_ARGS);
+
+    otEXPECT_ACTION(TRNG_GetRandomData(RNG, aOutput, aOutputLength) == kStatus_Success, status = OT_ERROR_FAILED);
+
+exit:
+    return status;
+}

examples/platforms/jn5189/settings_jn5189.c

@@ -0,0 +1,621 @@
+/*
+ *  Copyright (c) 2016, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file implements the OpenThread platform abstraction for non-volatile storage of
+ *   settings on JN5189 platform. It has been modified and optimized from the original
+ *   Open Thread settings implementation to work with JN5189's flash particularities.
+ *
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdlib.h>
+
+#include <openthread-core-config.h>
+
+#include <openthread/instance.h>
+#include <openthread/platform/settings.h>
+
+#include "utils/code_utils.h"
+#include "utils/wrap_string.h"
+
+#include "utils/flash.h"
+
+#define OT_FLASH_BLOCK_ADD_BEGIN_FLAG (1 << 0)
+#define OT_FLASH_BLOCK_ADD_COMPLETE_FLAG (1 << 1)
+#define OT_FLASH_BLOCK_DELETE_FLAG (1 << 2)
+#define OT_FLASH_BLOCK_INDEX_0_FLAG (1 << 3)
+/* Compact flag is used to indicate that the next settings block follows at the next 16 bytes
+ * aligned address after the data portion of the current one. Otherwise the next block will be
+ * placed in the next flash page */
+#define OT_FLASH_BLOCK_COMPACT_FLAG (1 << 4)
+
+#define OT_SETTINGS_FLAG_SIZE 16
+#define OT_SETTINGS_BLOCK_DATA_SIZE 256
+
+/* JN5189 erases the flash to value 0x00 */
+#define FLASH_ERASE_VALUE 0x00
+#define FLASH_ALIGN_SIZE 16
+#define FLASH_BLOCK_PAD1_SIZE 10
+#define FLASH_BLOCK_PAD2_SIZE 15
+
+#define OT_SETTINGS_IN_USE 0xbe5cc5ee
+
+/* Added padding to make settings block structure align to minimum flash write size of 16 bytes.
+ * The delFlag field has an offset of 16 bytes from the beginning of the structure to allow a new
+ * write on the field. */
+
+OT_TOOL_PACKED_BEGIN
+struct settingsBlock
+{
+    uint16_t key;
+    uint16_t flag;
+    uint16_t length;
+    uint8_t  padding1[FLASH_BLOCK_PAD1_SIZE];
+    uint8_t  delFlag;
+    uint8_t  padding2[FLASH_BLOCK_PAD2_SIZE];
+} OT_TOOL_PACKED_END;
+
+/**
+ * @def SETTINGS_CONFIG_BASE_ADDRESS
+ *
+ * The base address of settings.
+ *
+ */
+#ifndef SETTINGS_CONFIG_BASE_ADDRESS
+#define SETTINGS_CONFIG_BASE_ADDRESS 0
+#endif // SETTINGS_CONFIG_BASE_ADDRESS
+
+/**
+ * @def SETTINGS_CONFIG_PAGE_SIZE
+ *
+ * The page size of settings.
+ *
+ */
+#ifndef SETTINGS_CONFIG_PAGE_SIZE
+#define SETTINGS_CONFIG_PAGE_SIZE 0x800
+#endif // SETTINGS_CONFIG_PAGE_SIZE
+
+/**
+ * @def SETTINGS_CONFIG_PAGE_NUM
+ *
+ * The page number of settings.
+ *
+ */
+#ifndef SETTINGS_CONFIG_PAGE_NUM
+#define SETTINGS_CONFIG_PAGE_NUM 2
+#endif // SETTINGS_CONFIG_PAGE_NUM
+
+#if (SETTINGS_CONFIG_PAGE_NUM <= 1)
+#error "Invalid value for `SETTINGS_CONFIG_PAGE_NUM` (should be >= 2)"
+#endif
+
+/**
+ * @def FLASH_ERASE_VALUE
+ *
+ * The value a byte in flash takes after an erase operation.
+ *
+ */
+#ifndef FLASH_ERASE_VALUE
+#define FLASH_ERASE_VALUE 0xFF
+#endif // FLASH_ERASE_VALUE
+
+/* macros for setting/clearing bits in a flash byte depending on flash erase value */
+#if (FLASH_ERASE_VALUE == 0xFF)
+#define SET_FLASH_BLOCK_FLAG(aVar, aFlag) ((aVar) &= (~(aFlag)))
+#define FLASH_BLOCK_FLAG_IS_SET(aVar, aFlag) (!((aVar) & (aFlag)))
+
+#else
+// FLASH_ERASE_VALUE = 0x00
+#define SET_FLASH_BLOCK_FLAG(aVar, aFlag) ((aVar) |= (aFlag))
+#define FLASH_BLOCK_FLAG_IS_SET(aVar, aFlag) ((aVar) & (aFlag))
+
+#endif
+
+static uint32_t sSettingsBaseAddress;
+static uint32_t sSettingsUsedSize;
+static uint32_t sSettingsPageNum;
+
+/* linker file symbol for the number of flash sectors used for NVM */
+extern uint32_t NV_STORAGE_MAX_SECTORS;
+extern uint8_t  pageBuffer[];
+
+/**
+ * Calculates the aligned length of data for current settings block based on Compact flag
+ *
+ * @param[in] currentPos     Offset from the beginning of settings base address where the current
+ *                           block is located
+ * @param[in] blockFlag      Settings block flags value
+ * @param[in] length         Length of current block data
+
+ * @return uint16_t  Length of aligned data
+ */
+static uint16_t getAlignLength(uint16_t currentPos, uint8_t blockFlag, uint16_t length)
+{
+    uint16_t alignLen;
+    /* in case the compact flag is set length is calculated based on real one aligned to
+     * FLASH_ALIGN_SIZE(16 in this case) */
+    if (FLASH_BLOCK_FLAG_IS_SET(blockFlag, OT_FLASH_BLOCK_COMPACT_FLAG))
+    {
+        alignLen = (length + 1) & 0xfffe;
+    }
+    else
+    {
+        /* if the block is not compacted the length will be calculated so that the next block starts
+         * in the next flash page */
+        uint16_t pageOffset = currentPos % SETTINGS_CONFIG_PAGE_SIZE;
+        alignLen            = SETTINGS_CONFIG_PAGE_SIZE - pageOffset - sizeof(struct settingsBlock);
+    }
+
+    return alignLen;
+}
+
+static void setSettingsFlag(uint32_t aBase, uint32_t aFlag)
+{
+    utilsFlashWrite(aBase, (uint8_t *)&aFlag, sizeof(aFlag));
+}
+
+static void eraseSettings(uint32_t aBase)
+{
+    uint32_t address      = aBase;
+    uint32_t settingsSize = SETTINGS_CONFIG_PAGE_SIZE * sSettingsPageNum / 2;
+
+    while (address < (aBase + settingsSize))
+    {
+        utilsFlashErasePage(address);
+        address += SETTINGS_CONFIG_PAGE_SIZE;
+    }
+}
+
+static void initSettings(uint32_t aBase, uint32_t aFlag)
+{
+    eraseSettings(aBase);
+    setSettingsFlag(aBase, aFlag);
+}
+
+static uint32_t swapSettingsBlock(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    uint32_t oldBase        = sSettingsBaseAddress;
+    uint32_t swapAddress    = oldBase;
+    uint32_t usedSize       = sSettingsUsedSize;
+    uint32_t settingsSize   = SETTINGS_CONFIG_PAGE_SIZE * sSettingsPageNum / 2;
+    bool     pageBufferUsed = true;
+    uint8_t  tempFlag;
+
+    /* New settings base address */
+    sSettingsBaseAddress =
+        (swapAddress == SETTINGS_CONFIG_BASE_ADDRESS) ? (swapAddress + settingsSize) : SETTINGS_CONFIG_BASE_ADDRESS;
+
+    /* Erase new settings */
+    eraseSettings(sSettingsBaseAddress);
+    /* Erase the page buffer used to accumulate data that will be written to a flash page once it is
+     * full */
+    memset(pageBuffer, FLASH_ERASE_VALUE, SETTINGS_CONFIG_PAGE_SIZE);
+
+    *((uint32_t *)pageBuffer) = OT_SETTINGS_IN_USE;
+    sSettingsUsedSize         = OT_SETTINGS_FLAG_SIZE;
+    swapAddress += OT_SETTINGS_FLAG_SIZE;
+
+    while (swapAddress < (oldBase + usedSize))
+    {
+        OT_TOOL_PACKED_BEGIN
+        struct addSettingsBlock
+        {
+            struct settingsBlock block;
+            uint8_t              data[OT_SETTINGS_BLOCK_DATA_SIZE];
+        } OT_TOOL_PACKED_END addBlock;
+        bool                 valid = true;
+
+        utilsFlashRead(swapAddress, (uint8_t *)(&addBlock.block), sizeof(struct settingsBlock));
+        swapAddress += sizeof(struct settingsBlock);
+        tempFlag = addBlock.block.flag;
+
+        if ((FLASH_BLOCK_FLAG_IS_SET(addBlock.block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG)) &&
+            (0 == FLASH_BLOCK_FLAG_IS_SET(addBlock.block.delFlag, OT_FLASH_BLOCK_DELETE_FLAG)))
+
+        {
+            uint32_t address = swapAddress + getAlignLength(swapAddress - sizeof(struct settingsBlock),
+                                                            addBlock.block.flag, addBlock.block.length);
+
+            while (address < (oldBase + usedSize))
+            {
+                struct settingsBlock block;
+
+                utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
+
+                if ((FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG)) &&
+                    (0 == FLASH_BLOCK_FLAG_IS_SET(block.delFlag, OT_FLASH_BLOCK_DELETE_FLAG)) &&
+                    (FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_INDEX_0_FLAG)) &&
+                    (block.key == addBlock.block.key))
+
+                {
+                    valid = false;
+                    break;
+                }
+
+                address += (getAlignLength(address, block.flag, block.length) + sizeof(struct settingsBlock));
+            }
+
+            if (valid)
+            {
+                /* Calculate the size of data(block + settings data) that will be written to the
+                 * page buffer */
+                uint32_t writeSize = sizeof(struct settingsBlock);
+
+                if (!FLASH_BLOCK_FLAG_IS_SET(addBlock.block.flag, OT_FLASH_BLOCK_COMPACT_FLAG))
+                {
+                    /* Once a swap is initiated every settings block is compacted in the new flash
+                     * region */
+                    SET_FLASH_BLOCK_FLAG(addBlock.block.flag, OT_FLASH_BLOCK_COMPACT_FLAG);
+                }
+
+                /* current pos parameter doesn't count in this case */
+                writeSize += getAlignLength(0, OT_FLASH_BLOCK_COMPACT_FLAG, addBlock.block.length);
+
+                utilsFlashRead(swapAddress, addBlock.data, addBlock.block.length);
+                /* contents fits in current page - we can copy it to page buffer until there is
+                 * enough data to program a page */
+                if ((sSettingsUsedSize % SETTINGS_CONFIG_PAGE_SIZE) + writeSize <= SETTINGS_CONFIG_PAGE_SIZE)
+                {
+                    pageBufferUsed = false;
+                    memcpy(pageBuffer + (sSettingsUsedSize % SETTINGS_CONFIG_PAGE_SIZE), (uint8_t *)(&addBlock),
+                           writeSize);
+                }
+                else
+                {
+                    /* Page buffer is full and can be written to a flash page */
+                    pageBufferUsed = true;
+
+                    uint32_t remPageSize = SETTINGS_CONFIG_PAGE_SIZE - (sSettingsUsedSize % SETTINGS_CONFIG_PAGE_SIZE);
+                    memcpy(pageBuffer + (sSettingsUsedSize % SETTINGS_CONFIG_PAGE_SIZE), (uint8_t *)(&addBlock),
+                           remPageSize);
+
+                    /* calculate page address that we are going to write */
+                    uint32_t alignAddress = sSettingsBaseAddress + sSettingsUsedSize;
+                    alignAddress          = alignAddress - (alignAddress % SETTINGS_CONFIG_PAGE_SIZE);
+                    utilsFlashWrite(alignAddress, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
+
+                    /* After the page buffer is erased copy what dind't fit the previous page */
+                    memset(pageBuffer, FLASH_ERASE_VALUE, SETTINGS_CONFIG_PAGE_SIZE);
+                    memcpy(pageBuffer, (uint8_t *)(&addBlock) + remPageSize, writeSize - remPageSize);
+                }
+
+                sSettingsUsedSize += writeSize;
+            }
+        }
+        else if (addBlock.block.flag == FLASH_ERASE_VALUE)
+        {
+            break;
+        }
+        swapAddress += getAlignLength(swapAddress - sizeof(struct settingsBlock), tempFlag, addBlock.block.length);
+    }
+
+    if (false == pageBufferUsed)
+    {
+        /* If the page buffer has been used and it's not full write to flash at the end */
+        uint32_t alignAddr = sSettingsBaseAddress + sSettingsUsedSize;
+        alignAddr          = alignAddr - (alignAddr % SETTINGS_CONFIG_PAGE_SIZE);
+        utilsFlashWrite(alignAddr, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
+    }
+    /* Clear the old settings zone */
+    eraseSettings(oldBase);
+
+    return settingsSize - sSettingsUsedSize;
+}
+
+static otError addSetting(otInstance *   aInstance,
+                          uint16_t       aKey,
+                          bool           aIndex0,
+                          const uint8_t *aValue,
+                          uint16_t       aValueLength)
+{
+    otError error = OT_ERROR_NONE;
+    OT_TOOL_PACKED_BEGIN
+    struct addSettingsBlock
+    {
+        struct settingsBlock block;
+        uint8_t              data[OT_SETTINGS_BLOCK_DATA_SIZE];
+    } OT_TOOL_PACKED_END addBlock;
+    uint32_t             settingsSize = SETTINGS_CONFIG_PAGE_SIZE * sSettingsPageNum / 2;
+
+    /* Add all the settings flags once and optimize for one write to flash */
+    addBlock.block.flag    = FLASH_ERASE_VALUE;
+    addBlock.block.delFlag = FLASH_ERASE_VALUE;
+    addBlock.block.key     = aKey;
+    memset(addBlock.block.padding1, FLASH_ERASE_VALUE, FLASH_BLOCK_PAD1_SIZE);
+    memset(addBlock.block.padding2, FLASH_ERASE_VALUE, FLASH_BLOCK_PAD2_SIZE);
+
+    if (aIndex0)
+    {
+        SET_FLASH_BLOCK_FLAG(addBlock.block.flag, OT_FLASH_BLOCK_INDEX_0_FLAG);
+    }
+
+    SET_FLASH_BLOCK_FLAG(addBlock.block.flag, OT_FLASH_BLOCK_ADD_BEGIN_FLAG);
+    addBlock.block.length = aValueLength;
+
+    if ((sSettingsUsedSize + getAlignLength(sSettingsUsedSize, addBlock.block.flag, addBlock.block.length) +
+         sizeof(struct settingsBlock)) >= settingsSize)
+    {
+        otEXPECT_ACTION(swapSettingsBlock(aInstance) >=
+                            (getAlignLength(sSettingsUsedSize, addBlock.block.flag, addBlock.block.length) +
+                             sizeof(struct settingsBlock)),
+                        error = OT_ERROR_NO_BUFS);
+    }
+
+    memset(addBlock.data, FLASH_ERASE_VALUE, OT_SETTINGS_BLOCK_DATA_SIZE);
+    memcpy(addBlock.data, aValue, addBlock.block.length);
+
+    SET_FLASH_BLOCK_FLAG(addBlock.block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG);
+    utilsFlashWrite(sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&addBlock.block),
+                    sizeof(struct settingsBlock) + addBlock.block.length);
+    /* The next settings block will be written to the next flash page to optimize the number of
+     * writes made to a page */
+    sSettingsUsedSize +=
+        (sizeof(struct settingsBlock) + getAlignLength(sSettingsUsedSize, addBlock.block.flag, addBlock.block.length));
+
+exit:
+    return error;
+}
+
+// settings API
+void otPlatSettingsInit(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    uint8_t              index;
+    struct settingsBlock block;
+
+    /* exported symbol from linker file */
+    sSettingsPageNum      = (uint32_t)&NV_STORAGE_MAX_SECTORS;
+    uint32_t settingsSize = SETTINGS_CONFIG_PAGE_SIZE * sSettingsPageNum / 2;
+
+    sSettingsBaseAddress = SETTINGS_CONFIG_BASE_ADDRESS;
+
+    utilsFlashInit();
+
+    for (index = 0; index < 2; index++)
+    {
+        uint32_t blockFlag;
+
+        sSettingsBaseAddress += settingsSize * index;
+        utilsFlashRead(sSettingsBaseAddress, (uint8_t *)(&blockFlag), sizeof(blockFlag));
+
+        if (blockFlag == OT_SETTINGS_IN_USE)
+        {
+            break;
+        }
+    }
+
+    if (index == 2)
+    {
+        initSettings(sSettingsBaseAddress, (uint32_t)OT_SETTINGS_IN_USE);
+    }
+
+    sSettingsUsedSize = OT_SETTINGS_FLAG_SIZE;
+
+    while (sSettingsUsedSize < settingsSize)
+    {
+        utilsFlashRead(sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&block), sizeof(block));
+
+        if (FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_BEGIN_FLAG))
+        {
+            sSettingsUsedSize +=
+                (getAlignLength(sSettingsUsedSize, block.flag, block.length) + sizeof(struct settingsBlock));
+        }
+        else
+        {
+            break;
+        }
+    }
+}
+
+void otPlatSettingsDeinit(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+}
+
+otError otPlatSettingsBeginChange(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    return OT_ERROR_NONE;
+}
+
+otError otPlatSettingsCommitChange(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    return OT_ERROR_NONE;
+}
+
+otError otPlatSettingsAbandonChange(otInstance *aInstance)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    return OT_ERROR_NONE;
+}
+
+otError otPlatSettingsGet(otInstance *aInstance, uint16_t aKey, int aIndex, uint8_t *aValue, uint16_t *aValueLength)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    otError  error       = OT_ERROR_NOT_FOUND;
+    uint32_t address     = sSettingsBaseAddress + OT_SETTINGS_FLAG_SIZE;
+    uint16_t valueLength = 0;
+    int      index       = 0;
+
+    while (address < (sSettingsBaseAddress + sSettingsUsedSize))
+    {
+        struct settingsBlock block;
+
+        utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
+
+        if (block.key == aKey)
+        {
+            if (FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_INDEX_0_FLAG))
+            {
+                index = 0;
+            }
+
+            if ((FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG)) &&
+                (0 == FLASH_BLOCK_FLAG_IS_SET(block.delFlag, OT_FLASH_BLOCK_DELETE_FLAG)))
+            {
+                if (index == aIndex)
+                {
+                    uint16_t readLength = block.length;
+
+                    // only perform read if an input buffer was passed in
+                    if (aValue != NULL && aValueLength != NULL)
+                    {
+                        // adjust read length if input buffer length is smaller
+                        if (readLength > *aValueLength)
+                        {
+                            readLength = *aValueLength;
+                        }
+
+                        utilsFlashRead(address + sizeof(struct settingsBlock), aValue, readLength);
+                    }
+
+                    valueLength = block.length;
+                    error       = OT_ERROR_NONE;
+                }
+
+                index++;
+            }
+        }
+
+        address += (getAlignLength(address, block.flag, block.length) + sizeof(struct settingsBlock));
+    }
+
+    if (aValueLength != NULL)
+    {
+        *aValueLength = valueLength;
+    }
+
+    return error;
+}
+
+otError otPlatSettingsSet(otInstance *aInstance, uint16_t aKey, const uint8_t *aValue, uint16_t aValueLength)
+{
+    return addSetting(aInstance, aKey, true, aValue, aValueLength);
+}
+
+otError otPlatSettingsAdd(otInstance *aInstance, uint16_t aKey, const uint8_t *aValue, uint16_t aValueLength)
+{
+    uint16_t length;
+    bool     index0;
+
+    index0 = (otPlatSettingsGet(aInstance, aKey, 0, NULL, &length) == OT_ERROR_NOT_FOUND ? true : false);
+    return addSetting(aInstance, aKey, index0, aValue, aValueLength);
+}
+
+otError otPlatSettingsDelete(otInstance *aInstance, uint16_t aKey, int aIndex)
+{
+    OT_UNUSED_VARIABLE(aInstance);
+
+    otError  error   = OT_ERROR_NOT_FOUND;
+    uint32_t address = sSettingsBaseAddress + OT_SETTINGS_FLAG_SIZE;
+    int      index   = 0;
+
+    while (address < (sSettingsBaseAddress + sSettingsUsedSize))
+    {
+        struct settingsBlock block;
+
+        utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
+
+        if (block.key == aKey)
+        {
+            if (FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_INDEX_0_FLAG))
+            {
+                index = 0;
+            }
+
+            if ((FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG)) &&
+                (0 == FLASH_BLOCK_FLAG_IS_SET(block.delFlag, OT_FLASH_BLOCK_DELETE_FLAG)))
+            {
+                bool flashWrite = false;
+
+                if (aIndex == index || aIndex == -1)
+                {
+                    error = OT_ERROR_NONE;
+                    SET_FLASH_BLOCK_FLAG(block.delFlag, OT_FLASH_BLOCK_DELETE_FLAG);
+                    flashWrite = true;
+                }
+
+                if (index == 1 && aIndex == 0)
+                {
+                    SET_FLASH_BLOCK_FLAG(block.flag, OT_FLASH_BLOCK_INDEX_0_FLAG);
+                    flashWrite = true;
+                }
+
+                if (flashWrite)
+                {
+                    utilsFlashWrite(address, (uint8_t *)(&block), sizeof(block));
+                }
+
+                index++;
+            }
+        }
+
+        address += (getAlignLength(address, block.flag, block.length) + sizeof(struct settingsBlock));
+    }
+
+    return error;
+}
+
+void otPlatSettingsWipe(otInstance *aInstance)
+{
+    uint32_t address = SETTINGS_CONFIG_BASE_ADDRESS;
+
+    /* Clears all the flash pages during a factory reset */
+    for (uint32_t i = 0; i < sSettingsPageNum; i++)
+    {
+        /* This function protects against erasing an already erased page so we can just erase all
+         * pages to have and have all the settings storage clean */
+        utilsFlashErasePage(address);
+        address += SETTINGS_CONFIG_PAGE_SIZE;
+    }
+
+    /* Each time a factory reset is invoked start the settings zone in the alternate region to
+     * maximize wear leveling */
+    if (SETTINGS_CONFIG_BASE_ADDRESS == sSettingsBaseAddress)
+    {
+        sSettingsBaseAddress = SETTINGS_CONFIG_BASE_ADDRESS + (SETTINGS_CONFIG_PAGE_SIZE * sSettingsPageNum / 2);
+    }
+    else
+    {
+        sSettingsBaseAddress = SETTINGS_CONFIG_BASE_ADDRESS;
+    }
+    setSettingsFlag(sSettingsBaseAddress, OT_SETTINGS_IN_USE);
+
+    otPlatSettingsInit(aInstance);
+}

examples/platforms/jn5189/system.c

@@ -0,0 +1,88 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file includes the platform-specific initializers.
+ *
+ */
+#include "board.h"
+#include "pin_mux.h"
+#include "platform-jn5189.h"
+#include "openthread/platform/uart.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+otInstance *sInstance;
+
+void otSysInit(int argc, char *argv[])
+{
+    bool bHwInit = true;
+
+    if ((argc == 1) && (!strcmp(argv[0], "app")))
+    {
+        bHwInit = false;
+    }
+
+    if (bHwInit)
+    {
+        /* Security code to allow debug access */
+        SYSCON->CODESECURITYPROT = 0x87654320;
+
+        BOARD_BootClockRUN();
+        BOARD_InitPins();
+    }
+
+    JN5189AlarmInit();
+    JN5189RandomInit();
+    JN5189RadioInit();
+}
+
+bool otSysPseudoResetWasRequested(void)
+{
+    /* TODO */
+    return false;
+}
+
+void otSysDeinit(void)
+{
+    /* TODO */
+}
+
+void otSysProcessDrivers(otInstance *aInstance)
+{
+    JN5189RadioProcess(aInstance);
+    JN5189UartProcess();
+    JN5189AlarmProcess(aInstance);
+}
+
+void otSysEventSignalPending(void)
+{
+    /* TODO */
+}

examples/platforms/jn5189/uart.c

@@ -0,0 +1,333 @@
+/*
+ *  Copyright (c) 2019, The OpenThread Authors.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of the copyright holder nor the
+ *     derived from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ *   This file implements the OpenThread platform abstraction for UART communication.
+ *
+ */
+
+/* NXP UART includes */
+#include "board.h"
+#include "fsl_clock.h"
+#include "fsl_flexcomm.h"
+#include "fsl_reset.h"
+#include "fsl_usart.h"
+
+/* Openthread general includes */
+#include <utils/code_utils.h>
+#include "openthread/platform/uart.h"
+
+/* Defines */
+#define JN5189_UART_RX_BUFFERS 256
+#define JN5189_UART_BAUD_RATE 115200
+
+/* Structures */
+typedef struct
+{
+    uint8_t buffer[JN5189_UART_RX_BUFFERS];
+    uint8_t head;
+    uint8_t tail;
+    bool    isFull;
+} rxRingBuffer;
+
+/* Enums */
+typedef enum
+{
+    UART_IDLE, /* TX idle. */
+    UART_BUSY, /* TX busy. */
+} jn5189UartStates;
+
+/* Private functions declaration */
+static void     JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing);
+static uint8_t *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing);
+static bool     JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
+static void     JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter);
+static void     JN5189ProcessReceive();
+static void     JN5189ProcessTransmit();
+static void     USART0_IRQHandler(USART_Type *base, usart_handle_t *handle);
+
+/* Private variables declaration */
+static bool           sIsUartInitialized; /* Is UART module initialized? */
+static bool           sIsTransmitDone;    /* Transmit done for the latest user-data buffer */
+static usart_handle_t sUartHandle;        /* Handle to the UART module */
+static rxRingBuffer   sUartRxRing;        /* Receive Ring Buffer */
+
+void JN5189UartProcess(void)
+{
+    if (sIsUartInitialized)
+    {
+        JN5189ProcessTransmit();
+        JN5189ProcessReceive();
+    }
+}
+
+otError otPlatUartEnable(void)
+{
+    status_t uartStatus;
+    otError  error = OT_ERROR_NONE;
+
+    usart_config_t config;
+    uint32_t       kPlatformClock = CLOCK_GetFreq(kCLOCK_Fro32M);
+
+    /* attach clock for USART0 */
+    CLOCK_AttachClk(kOSC32M_to_USART_CLK);
+
+    /* reset FLEXCOMM0 for USART0 */
+    RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+
+    memset(&sUartHandle, 0, sizeof(sUartHandle));
+    sUartHandle.txState = UART_IDLE;
+
+    USART_GetDefaultConfig(&config);
+    config.baudRate_Bps = JN5189_UART_BAUD_RATE;
+    config.enableTx     = true;
+    config.enableRx     = true;
+    config.rxWatermark  = kUSART_RxFifo1;
+
+    uartStatus = USART_Init(USART0, &config, kPlatformClock);
+    otEXPECT_ACTION(uartStatus == kStatus_Success, error = OT_ERROR_INVALID_ARGS);
+
+    JN5189ResetRxRingBuffer(&sUartRxRing);
+
+    FLEXCOMM_SetIRQHandler(USART0, (flexcomm_irq_handler_t)USART0_IRQHandler, &sUartHandle);
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(USART0_IRQn);
+
+    /* Enable RX interrupt. */
+    USART_EnableInterrupts(USART0, kUSART_RxLevelInterruptEnable | kUSART_RxErrorInterruptEnable);
+
+    sIsUartInitialized = true;
+
+exit:
+    return error;
+}
+
+otError otPlatUartDisable(void)
+{
+    sIsUartInitialized = false;
+    USART_Deinit(USART0);
+
+    return OT_ERROR_NONE;
+}
+
+otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength)
+{
+    otError error = OT_ERROR_NONE;
+
+    otEXPECT_ACTION(!sUartHandle.txData, error = OT_ERROR_BUSY);
+    sUartHandle.txData        = (uint8_t *)aBuf;
+    sUartHandle.txDataSize    = aBufLength;
+    sUartHandle.txDataSizeAll = aBufLength;
+
+    /* Enable transmitter interrupt. */
+    USART_EnableInterrupts(USART0, kUSART_TxLevelInterruptEnable);
+
+exit:
+    return error;
+}
+
+otError otPlatUartFlush(void)
+{
+    return OT_ERROR_NOT_IMPLEMENTED;
+}
+
+/**
+ * Function used for blocking-write to the UART module.
+ *
+ * @param[in] aBuf             Pointer to the character buffer
+ * @param[in] len              Length of the character buffer
+ */
+void JN5189WriteBlocking(const uint8_t *aBuf, uint32_t len)
+{
+    otEXPECT(sIsUartInitialized && sUartHandle.txState != UART_BUSY);
+
+    sUartHandle.txState = UART_BUSY;
+    USART_WriteBlocking(USART0, aBuf, len);
+    sUartHandle.txState = UART_IDLE;
+
+exit:
+    return;
+}
+
+/**
+ * Process TX characters in process context and call the upper layer call-backs.
+ */
+static void JN5189ProcessTransmit(void)
+{
+    if (sIsTransmitDone)
+    {
+        sIsTransmitDone = false;
+        otPlatUartSendDone();
+    }
+}
+
+/**
+ * Process RX characters in process context and call the upper layer call-backs.
+ */
+static void JN5189ProcessReceive(void)
+{
+    uint8_t  rx[JN5189_UART_RX_BUFFERS];
+    uint16_t rxIndex = 0;
+    uint8_t *pCharacter;
+
+    while ((pCharacter = JN5189PopRxRingBuffer(&sUartRxRing)) != NULL)
+    {
+        rx[rxIndex] = *pCharacter;
+        rxIndex++;
+    }
+    otPlatUartReceived(rx, rxIndex);
+}
+
+static void USART0_IRQHandler(USART_Type *base, usart_handle_t *handle)
+{
+    (void)base;
+    (void)handle;
+
+    bool isReceiveEnabled = true;
+    bool isSendEnabled    = (sUartHandle.txDataSize != 0);
+
+    /* If RX overrun. */
+    if (USART0->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+    {
+        /* Clear RX error state. */
+        USART0->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear RX FIFO */
+        USART0->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+    while ((isReceiveEnabled && (USART0->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||
+           (isSendEnabled && (USART0->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))
+    {
+        /* RX: an interrupt is fired for each received character */
+        if (isReceiveEnabled && (USART0->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+            volatile uint8_t rx_data = USART_ReadByte(USART0);
+
+            {
+                JN5189PushRxRingBuffer(&sUartRxRing, rx_data);
+            }
+        }
+
+        /* There are times when the UART interrupt fires unnecessarily
+         * having the TXNOTFULL and TXEMPY bits set. Disable this!
+         */
+        if ((!sUartHandle.txDataSize) && (USART0->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) &&
+            (USART0->FIFOSTAT & USART_FIFOSTAT_TXEMPTY_MASK))
+        {
+            USART0->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+        }
+
+        /* TX: an interrupt is fired for each sent character */
+        if (isSendEnabled && (USART0->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+            USART0->FIFOWR = *sUartHandle.txData;
+            sUartHandle.txDataSize--;
+            sUartHandle.txData++;
+            isSendEnabled = (sUartHandle.txDataSize != 0);
+
+            if (!isSendEnabled)
+            {
+                USART0->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+                sUartHandle.txData   = NULL;
+                sIsTransmitDone      = true;
+            }
+        }
+    }
+}
+
+/**
+ * Function used to push a received character to the RX Ring buffer.
+ * In case the ring buffer is full, the oldest address is overwritten.
+ *
+ * @param[in] aRxRing             Pointer to the RX Ring Buffer
+ * @param[in] aCharacter          The received character
+ */
+static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter)
+{
+    aRxRing->buffer[aRxRing->head] = aCharacter;
+
+    if (aRxRing->isFull)
+    {
+        aRxRing->tail = (aRxRing->tail + 1) % JN5189_UART_RX_BUFFERS;
+    }
+
+    aRxRing->head   = (aRxRing->head + 1) % JN5189_UART_RX_BUFFERS;
+    aRxRing->isFull = (aRxRing->head == aRxRing->tail);
+}
+
+/**
+ * Function used to pop the address of a received character from the RX Ring buffer
+ * Process Context: the consumer will pop frames with the interrupts disabled
+ *                  to make sure the interrupt context(ISR) doesn't push in
+ *                  the middle of a pop.
+ *
+ * @param[in] aRxRing           Pointer to the RX Ring Buffer
+ *
+ * @return    tsRxFrameFormat   Pointer to a received character
+ * @return    NULL              In case the RX Ring buffer is empty
+ */
+static uint8_t *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing)
+{
+    uint8_t *pCharacter = NULL;
+
+    DisableIRQ(USART0_IRQn);
+    if (!JN5189IsEmptyRxRingBuffer(aRxRing))
+    {
+        pCharacter      = &(aRxRing->buffer[aRxRing->tail]);
+        aRxRing->isFull = false;
+        aRxRing->tail   = (aRxRing->tail + 1) % JN5189_UART_RX_BUFFERS;
+    }
+    EnableIRQ(USART0_IRQn);
+
+    return pCharacter;
+}
+
+/**
+ * Function used to check if an RX Ring buffer is empty
+ *
+ * @param[in] aRxRing           Pointer to the RX Ring Buffer
+ *
+ * @return    TRUE              RX Ring Buffer is not empty
+ * @return    FALSE             RX Ring Buffer is empty
+ */
+static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
+{
+    return (!aRxRing->isFull && (aRxRing->head == aRxRing->tail));
+}
+
+/**
+ * Function used to init/reset an RX Ring Buffer
+ *
+ * @param[in] aRxRing         Pointer to an RX Ring Buffer
+ */
+static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing)
+{
+    aRxRing->head   = 0;
+    aRxRing->tail   = 0;
+    aRxRing->isFull = false;
+}

third_party/nxp/JN5189/ImageSigning/jn518x_image_tool.py

@@ -0,0 +1,353 @@
+"""
+* Copyright 2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+"""
+
+#!python
+
+from collections import namedtuple
+import re
+import argparse
+import subprocess
+import struct
+from Crypto.Signature import pkcs1_15
+from Crypto.PublicKey import RSA
+from Crypto.Hash import SHA256
+from Crypto.Util import number
+import binascii
+import os
+
+parser = argparse.ArgumentParser(description='JN518x Image Header Generator')
+parser.add_argument('in_file', help="Binary to be post-processed: generating header and optionally appending certificate and/or signature.")
+parser.add_argument('out_file', nargs='?')
+parser.add_argument('-g', '--signature_path', help="Sets directory from which certificate and private key are to be retrieved")
+parser.add_argument('-k', '--key', action='store_true', help="2048 bits RSA private key in PEM format used to sign the full image. If -c option is used the full image includes the certificate + the signature of the certificate. The key shall be located in the same directory as the image_tool script. See priv_key.pem example.")
+parser.add_argument('-p', '--password',help="This is the pass phrase from which the encryption key is derived. This parameter is only required if key provided through the -k option is a PEM encrypted key.")
+parser.add_argument('-c', '--certificate', action='store_true', help="When option is selected, the certificate cert.bin is appended to the image.")
+parser.add_argument('-a', '--appcore_image', action='store_true',help="This parameter is only relevant if dual application (app1 image) shall reside in flash. Do not use in conjunction with -i option.")
+parser.add_argument('-i', '--image_identifier', type=int, default=0, help="This parameter is to set the archive identifier. 0: SSBL or legacy JN518x/QN9090 applications, loaded at 0x00000000. 1: ZigBee  application loaded at address 0x00004000 by default. 2: BLE image loaded at address 0x00054000 by default")
+parser.add_argument('-t', '--target_addr', type=int, help="Target address of image. Used in conjucntion with -i option to override the default set by image identifier, or with -a option to specify address of the appcore image (app1 image).")
+parser.add_argument('-r', '--rev', type=int, default=2, help="This is the revision of the JN5189 chip. Set 1 for ES1 and 2 for ES2. Default is ES2.")
+parser.add_argument('-s', '--stated_size', type=int, default=0x48000, help="This is the stated size of the image in bytes. Default is 0x48000.")
+parser.add_argument('-v', '--version', type=int, default=0, help="Image version. Default is 0.")
+parser.add_argument('-b', '--verbose', type=int, default=0, help="verbosity level. Default is 0.")
+
+args = parser.parse_args()
+
+elf_file_name = args.in_file
+bin_file_name = elf_file_name.split(".")[0]+'_temp.bin'
+
+if args.out_file is None:
+    args.out_file = elf_file_name
+
+verbose = args.verbose != 0
+
+
+
+def parse_sections(file):
+    sections = {}
+
+    Section = namedtuple('Section', ['idx', 'name', 'size', 'vma', 'lma', 'offset', 'align', 'flags'])
+
+    objdump = subprocess.check_output(['arm-none-eabi-objdump', '-h', file])
+
+    section_re = re.compile(r'(?P<idx>\d*)\s'
+                            r'(?P<name>[.\w]*)\s*'
+                            r'(?P<size>[0-9a-f]{8})\s*'
+                            r'(?P<vma>[0-9a-f]{8})\s*'
+                            r'(?P<lma>[0-9a-f]{8})\s*'
+                            r'(?P<offset>[0-9a-f]{8})\s*'
+                            r'(?P<align>[0-9*]*)\s*'
+                            r'(?P<flags>(?:[ \t]*[\w,]*)*)')
+
+    for match in re.finditer(section_re, objdump):
+        sec_dict = match.groupdict()
+
+        sec_dict['idx'] = int(sec_dict['idx'])
+
+        for attr in ['vma', 'lma', 'size', 'offset']:
+            sec_dict[attr] = int(sec_dict[attr], 16)
+
+        sec_dict['align'] = eval(sec_dict['align'])
+
+        sections[sec_dict['name']] = Section(**sec_dict)
+
+    return sections
+
+
+#
+# JN518x ES1 version
+######################
+if args.rev == 1:
+
+    BOOT_BLOCK_MARKER = 0xBB0110BB
+
+    header_struct     = struct.Struct('<7LLLLL')
+    boot_block_struct = struct.Struct('<6LQ')
+
+    sections = parse_sections(args.in_file)
+
+    last_section = None
+
+    for name, section in sections.iteritems():
+        if 'LOAD' in section.flags:
+            if last_section is None or section.lma > last_section.lma:
+                if section.size > 0:
+                    last_section = section
+
+    if args.appcore_image is True:
+        image_size = last_section.lma + last_section.size - args.target_appcore_addr
+    else:
+        image_size = last_section.lma + last_section.size
+
+    dump_section = subprocess.check_output(['arm-none-eabi-objcopy', '--dump-section', '%s=data.bin' % last_section.name, args.in_file])
+
+    if args.appcore_image is True:
+        boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 1, args.target_appcore_addr, image_size + boot_block_struct.size, 0, 0, 0)
+    else:
+        boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 0, 0, image_size + boot_block_struct.size, 0, 0, 0)
+
+    with open('data.bin', 'ab') as out_file:
+        out_file.write(boot_block)
+
+    update_section = subprocess.check_output(['arm-none-eabi-objcopy', '--update-section', '%s=data.bin' % last_section.name, args.in_file, args.out_file])
+
+    first_section = None
+
+    for name, section in sections.iteritems():
+        if 'LOAD' in section.flags:
+            if first_section is None or section.lma < first_section.lma:
+                first_section = section
+
+    with open(args.out_file, 'r+b') as elf_file:
+        elf_file.seek(first_section.offset)
+        vectors = elf_file.read(header_struct.size)
+
+        fields = list(header_struct.unpack(vectors))
+
+        vectsum = 0
+
+        for x in range(7):
+            vectsum += fields[x]
+
+        fields[7]  = (~vectsum & 0xFFFFFFFF) + 1
+        if args.appcore_image is True:
+            fields[9]  = 0x02794498
+        else:
+            fields[9]  = 0x98447902
+        #fields[9]  = 0x98447902
+        fields[10] = image_size
+
+        print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
+
+        elf_file.seek(first_section.offset)
+        elf_file.write(header_struct.pack(*fields))
+
+#
+# JN518x ES2 version
+######################
+else:
+    is_signature = False
+    if args.signature_path is not None:
+        sign_dir_path = os.path.join(os.path.dirname(__file__), args.signature_path)
+        priv_key_file_path = os.path.join(sign_dir_path, 'priv_key.pem')
+        cert_file_path = os.path.join(sign_dir_path, 'cert.bin')
+    else:
+        sign_dir_path = os.path.join(os.path.dirname(__file__), '')
+        priv_key_file_path = os.path.join(sign_dir_path, 'testkey_es2.pem')
+        cert_file_path = os.path.join(sign_dir_path, 'certif_es2')
+
+    if args.key is True:
+        key_file_path = priv_key_file_path
+        if verbose:
+            print "key path is " + key_file_path
+        if (os.path.isfile(key_file_path)):
+            key_file=open(key_file_path, 'r')
+            key = RSA.importKey(key_file.read(), args.password)
+            print "Private RSA key processing..."
+            is_signature = True
+
+    bin_output = subprocess.check_output(['arm-none-eabi-objcopy', '-O', 'binary', elf_file_name, bin_file_name])
+
+    with open(bin_file_name, 'rb') as in_file:
+        input_file = in_file.read()
+
+    BOOT_BLOCK_MARKER      = 0xBB0110BB
+    IMAGE_HEADER_MARKER    = 0x98447902
+    IMAGE_HEADER_APP_CORE  = 0x02794498
+    IMAGE_HEADER_ESCORE    = IMAGE_HEADER_MARKER
+    SSBL_OR_LEGACY_ADDRESS = 0x00000000
+    SSBL_STATED_SIZE       = 0x3000
+    ZB_TARGET_ADDRESS      = SSBL_STATED_SIZE * 2
+    ZB_STATED_SIZE         = 0x4f000
+    BLE_TARGET_ADDRESS     = ZB_TARGET_ADDRESS + ZB_STATED_SIZE
+    BLE_STATED_SIZE        = 0x3b000
+
+    header_struct     = struct.Struct('<7LLLLL')
+    boot_block_struct = struct.Struct('<8L')
+
+    boot_block_marker = BOOT_BLOCK_MARKER
+    if args.image_identifier is not None:
+        image_iden = args.image_identifier
+    else:
+        image_iden = 0
+
+    # Set header marker and image address based on image identifier (-i option)
+    if verbose:
+        print "Image Identifier is {:d}".format(image_iden)
+    if image_iden == 0:
+        img_header_marker = IMAGE_HEADER_MARKER + image_iden
+        image_addr = SSBL_OR_LEGACY_ADDRESS
+        stated_size = SSBL_STATED_SIZE
+    elif image_iden == 1:
+        img_header_marker = IMAGE_HEADER_MARKER + image_iden
+        image_addr = ZB_TARGET_ADDRESS
+        stated_size = ZB_STATED_SIZE
+    elif image_iden == 2:
+        img_header_marker = IMAGE_HEADER_MARKER + image_iden
+        image_addr = BLE_TARGET_ADDRESS
+        stated_size = BLE_STATED_SIZE
+    else:
+        image_addr = 0
+        stated_size = 0
+
+    # Overwrite defaults for image address, stated size and header marker (-t, -s, -a options)
+    if args.target_addr is not None:
+        image_addr = args.target_addr
+
+    if args.stated_size is not None:
+        stated_size = args.stated_size
+
+    if args.appcore_image is True:
+        img_header_marker  = IMAGE_HEADER_APP_CORE
+
+    if verbose:
+        print "image_iden=%d image_addr=%x" % (image_iden, image_addr)
+        print "boot_block_marker=%x" % (boot_block_marker)
+
+    sections = parse_sections(elf_file_name)
+
+    last_section = None
+    for name, section in sections.iteritems():
+        if 'LOAD' in section.flags:
+            if last_section is None or section.lma > last_section.lma:
+                if section.size > 0:
+                    last_section = section
+
+    image_size = last_section.lma + last_section.size - image_addr
+    if verbose:
+        print "Last Section LMA={:08x} Size={:08x}".format(last_section.lma, last_section.size)
+        print "ImageAddress={:08x}".format(image_addr)
+
+    first_section = None
+
+    for name, section in sections.iteritems():
+        # print "Section: {:s} {:s} {:x} {:x}".format(name, section.flags, section.lma, section.size)
+        if 'LOAD' in section.flags:
+            if first_section is None or section.lma < first_section.lma:
+                first_section = section
+
+    header=""
+    with open(args.out_file, 'r+b') as elf_file:
+        elf_file.seek(first_section.offset)
+        vectors = elf_file.read(header_struct.size)
+
+        fields = list(header_struct.unpack(vectors))
+
+        vectsum = 0
+        for x in range(7):
+            vectsum += fields[x]
+
+        fields[7]  = (~vectsum & 0xFFFFFFFF) + 1
+        fields[8]  = img_header_marker
+        fields[9]  = image_size                    #offset of boot block structure
+
+        #Compute crc
+        head_struct     = struct.Struct('<10L')
+        if verbose:
+            for i in range(10):
+                print "Header[{:d}]= {:08x}".format(i, fields[i])
+        values = head_struct.pack(fields[0],
+                                  fields[1],
+                                  fields[2],
+                                  fields[3],
+                                  fields[4],
+                                  fields[5],
+                                  fields[6],
+                                  fields[7],
+                                  fields[8],
+                                  fields[9])
+        fields[10] = binascii.crc32(values) & 0xFFFFFFFF
+
+        print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
+        print "Writing CRC32 of header {:08x} to file {:s}".format(fields[10], args.out_file)
+
+
+        elf_file.seek(first_section.offset)
+        header = header_struct.pack(*fields);
+        elf_file.write(header)
+
+    dump_section = subprocess.check_output(['arm-none-eabi-objcopy',
+                                            '--dump-section',
+                                            '%s=data.bin' % last_section.name,
+                                            args.out_file])
+
+    certificate = ""
+    certificate_offset = 0
+    signature = ""
+
+    if (args.certificate is True):
+        certificate_offset = image_size + boot_block_struct.size
+        certif_file_path = cert_file_path
+        if verbose:
+            print "Cert key path is " + cert_file_path
+        if (os.path.isfile(certif_file_path)):
+            certif_file=open(certif_file_path, 'rb')
+            certificate = certif_file.read()
+
+        print "Certificate processing..."
+        if len(certificate) != (40+256+256):
+            print "Certificate error"
+
+    if verbose:
+        print "stated size is {:08x}".format(stated_size)
+
+    if args.appcore_image is True:
+        boot_block_id = 1
+    else:
+        boot_block_id = 0
+
+    boot_block = boot_block_struct.pack(boot_block_marker,
+                                        boot_block_id,
+                                        image_addr,
+                                        image_size + boot_block_struct.size + len(certificate),
+                                        stated_size,
+                                        certificate_offset, 0, args.version)
+
+    if (is_signature == True):
+        # Sign the complete image
+        message = header + input_file[header_struct.size:] + boot_block + certificate
+        hash = SHA256.new(message)
+
+        out_file_path = os.path.join(os.path.dirname(__file__), 'dump_python.bin')
+        file_out=open(out_file_path, 'wb')
+        file_out.write(message)
+
+        signer = pkcs1_15.new(key)
+        signature = signer.sign(hash)
+
+        print "Signature processing..."
+
+
+    with open('data.bin', 'ab') as out_file:
+        out_file.write(boot_block+certificate+signature)
+
+    update_section = subprocess.check_output(['arm-none-eabi-objcopy',
+                                              '--update-section',
+                                              '%s=data.bin' % last_section.name,
+                                              args.out_file,
+                                              args.out_file])
+
+    os.remove(bin_file_name)

third_party/nxp/JN5189/ImageSigning/sign_images.sh

@@ -0,0 +1,57 @@
+#!/bin/bash
+
+# Copyright 2019 NXP
+# All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Script gets as first command line argument the directory
+# containing the ELF files which will be signed using
+# $SIGNING_TOOL. After the signing process, the binary
+# is extracted from the ELF file and placed in an equivalent
+# filename with the .bin extension.
+
+
+function is_linux_package_installed()
+{
+	dpkg -s ${1} &> /dev/null
+
+	if [ $? -ne 0 ]; then
+        echo "Linux package ** ${1} ** is not installed! Please install it then recompile."
+        echo "Installation command (Debian-based Linux system): sudo apt-get install ${1}"
+		exit 1
+	fi
+}
+
+function is_python_package_installed()
+{
+	pip list --format=columns | grep -F ${1} &> /dev/null
+
+	if [ $? -ne 0 ]; then
+        echo "Python package ** ${1} ** is not installed! Please install it then recompile."
+        echo "Installation command: pip install ${1}"
+		exit 1
+	fi
+}
+
+is_linux_package_installed "python"
+is_linux_package_installed "python-pip"
+is_python_package_installed "pycrypto"
+is_python_package_installed "pycryptodome"
+
+CURR_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
+SIGNING_TOOL=$CURR_DIR/jn518x_image_tool.py
+MIME_PATTERN="application/x-executable"
+
+if [ "$#" -eq 1 ]; then
+	DIR_WITH_ELFS=$1
+
+	for FILENAME in $DIR_WITH_ELFS/*; do
+		MIME_SET="$(file -ib $FILENAME)"
+
+		if [[ $MIME_SET == *"$MIME_PATTERN"* ]]; then
+			python $SIGNING_TOOL $FILENAME
+			arm-none-eabi-objcopy -O binary $FILENAME $FILENAME.bin
+		fi
+	done
+fi

third_party/nxp/JN5189/JN5189_features.h

@@ -0,0 +1,220 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2016-05-09
+**     Build:               b160714
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-05-09)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _JN518X_FEATURES_H_
+#define _JN518X_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief Number of DMA channels on the SOC. */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (19)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (7)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_GPIO_COUNT (1)
+#define FSL_FEATURE_SOC_GPIO_COUNT FSL_FEATURE_SOC_LPC_GPIO_COUNT
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (3)
+/* @brief I2C are FLEXCOMM on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_I2C_COUNT FSL_FEATURE_SOC_I2C_COUNT
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MAILBOX availability on the SoC. */
+#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief SPI are FLEXCOMM on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_SPI_COUNT FSL_FEATURE_SOC_SPI_COUNT
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (2)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (2)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_USART_COUNT FSL_FEATURE_SOC_USART_COUNT
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+/* @brief IRB availability on the SoC. */
+#define FSL_FEATURE_SOC_CIC_IRB_COUNT (1)
+/* @brief reduced functionality FLEXCOMM  for low power JN518x family */
+#define FSL_REDUCED_FUNCTION_FLEXCOMM
+/* @brief PWM availability on the Soc */
+#define FSL_FEATURE_SOC_PWM_COUNT (10)
+
+/* @brief HASH/SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (1)
+/* @brief AES availability on the SoC. */
+#define FSL_FEATURE_SOC_AES_COUNT (1)
+
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+
+/* SPIFI module features */
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
+/* @brief SPIFI DATALEN bitfile in CMD register*/
+#define FSL_FEATURE_SPIFI_DATALEN_CTRL (1)
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+
+/* PINT module features */
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
+/* @brief Number of PIOs  */
+#define FSL_FEATURE_GPIO_PIO_COUNT (22)
+
+/* PMC module features */
+/* @brief FRO1M trim address */
+#define FSL_FEATURE_PMC_FRO1M_ADDRESS (0x9FCD0U)
+/* @brief FRO1M trim valid mask */
+#define FSL_FEATURE_PMC_FRO1M_VALID_MASK (0x1U)
+
+/* SPI module features */
+/* @brief SPI SIZE bitfile in FIFOCFG register */
+#define FSL_FEATURE_SPI_FIFOSIZE_CFG (1)
+/* @brief SPI has only three SSEL pins */
+#define FSL_FEATURE_IS_SPI_SSEL_PIN_COUNT_EQUAL_TO_THREE (1)
+
+/* ADC module features */
+/* @brief ADC data alignment mode */
+#define FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT (1)
+/* @brief ADC synchronous mode do not modify CTRL.TSAMP [14:12] */
+#define FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL (1)
+/* @brief ADC temp cal flash addr */
+#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x9FC80)
+/* @brief ADC temp cal flash data vaild mask*/
+#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID (0x1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has RESOL bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
+/* @brief Has BYPASSCAL bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
+/* @brief Has TSAMP bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
+/* @brief ADC NO calibration*/
+#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
+/* @brief ADC TEMPSENSORCTRL in ASYNC_SYSCON*/
+#define FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP (1)
+/* @brief ADC require a delay*/
+#define FSL_FEATURE_ADC_REQUIRE_DELAY (1)
+/* @brief Has LDO_POWER_EN bitfile in GPADC_CTRL0 register. */
+#define FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN (1)
+/* @brief Has OFFSET_CAL bitfile in GPADC_CTRL1 register. */
+#define FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL (1)
+/* @brief Has ADC_INIT bitfile in STARTUP register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT (0)
+/* @brief ADC has single SEQ */
+#define FSL_FEATURE_ADC_HAS_SINGLE_SEQ (1)
+/* SYSCON module features */
+
+/* FLASH module features */
+/* @brief P-Flash write unit size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (512U)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (512U)
+/* @brief P-Flash block count */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+/* @brief P-Flash block size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0xA0000U)
+
+/* CTIMER module features */
+/* @brief CTIMER capture channel 3. */
+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+
+/* WWDT module features */
+/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
+#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (1)
+/* @brief WWDT NO PDCFG*/
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
+/* I2C module features */
+/* @brief I2C peripheral clock frequency 8MHz */
+#define FSL_FEATURE_I2C_PREPCLKFRG_8MHZ (1)
+
+/* GPIO module feature */
+/* @brief GPIO DIRSET and DIRCLR register */
+#define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1)
+
+/* FMEAS module feature */
+/* @brief FMEAS FMEAS_INDEX is 20 */
+#define FSL_FEATURE_FMEAS_INDEX_20 (1)
+/* @brief FMEAS FREQMECTRL in ASYNC_SYSCON */
+#define FSL_FEATURE_FMEAS_ASYNC_SYSCON_FREQMECTRL (1)
+/* @brief FMEAS SYSCON use ASYNC_SYSCON */
+#define FSL_FEATURE_FMEAS_USE_ASYNC_SYSCON (1)
+/* @brief FMEAS start frequency with ASYNC_SYSCON */
+#define FSL_FEATURE_FMEAS_START_FRG_ASYNC_SYSCON (1)
+/* @brief FMEAS get frequency with ASYNC_SYSCON */
+#define FSL_FEATURE_FMEAS_GET_FRG_ASYNC_SYSCON (1)
+/* @brief FMEAS get clock count with scale */
+#define FSL_FEATURE_FMEAS_GET_COUNT_SCALE (1)
+/* @brief FMEAS start measure with scale */
+#define FSL_FEATURE_FMEAS_STARTMEAS_SCALE (1)
+
+/* RTC module features */
+/* @brief Has no separate RTC OSC PD in CTRL register. */
+#define FSL_FEATURE_RTC_HAS_NO_OSC_PD (1)
+
+/* FLEXCOMM module features */
+/* @brief Has no reset in FLEXCOMM register. */
+#define FSL_FEATURE_FLEXCOMM_HAS_NO_RESET (1)
+
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (1)
+#endif /* _JN518X_FEATURES_H_ */

third_party/nxp/JN5189/JennicCommon/Include/jendefs.h

@@ -0,0 +1,314 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef  JENDEFS_INCLUDED
+#define  JENDEFS_INCLUDED
+
+/****************************************************************************/
+/***        Include Files                                                 ***/
+/****************************************************************************/
+
+#include <stdint.h>
+
+#ifndef __KERNEL__
+#include <stdarg.h>
+#include <stdio.h>
+#endif
+
+#ifdef ECOS
+#include <cyg/infra/cyg_type.h>
+#endif
+
+/****************************************************************************/
+/***        Macro Definitions                                             ***/
+/****************************************************************************/
+
+/*--------------------------------------------------------------------------*/
+/*          Compiler Constants for GCC compiler                             */
+/*--------------------------------------------------------------------------*/
+
+#if defined(__GNUC__)
+
+/* The following 5 macros force the compiler to align the specified object  */
+/* on a given byte boundary.                                                */
+/* Example:                                                                 */
+/*     int  iVar  ALIGN_(16);  Force iVar to be aligned on the next         */
+/*                             16 byte boundary                             */
+
+#define PACK      __attribute__ ((packed))        /* align to byte boundary  */
+#define ALIGN_2   __attribute__ ((aligned (2)))   /* 16-bit boundary (2 byte)*/
+#define ALIGN_4   __attribute__ ((aligned (4)))   /* 32-bit boundary (4 byte)*/
+#define ALIGN_8   __attribute__ ((aligned (8)))   /* 64-bit boundary (8 byte)*/
+#define ALIGN_(x) __attribute__ (((aligned (x)))) /* arbitrary alignment     */
+
+/* force an unused variable not to be elided */
+#define USED      __attribute__ ((used))
+
+#if __GNUC__ < 5
+#define INLINE    extern inline
+#else
+#if (defined JENNIC_CHIP_FAMILY_JN516x) || (defined JENNIC_CHIP_FAMILY_JN517x)
+#pragma message ( "Unsupported version of GCC is being used!!" )
+#endif
+#define INLINE    inline
+#endif
+
+#define ALWAYS_INLINE __attribute__((always_inline))
+
+#ifndef WEAK
+#define WEAK      __attribute__ ((weak))
+#endif
+#define ALIAS(f)  __attribute__ ((weak, alias (#f)))
+
+#elif defined(_MSC_VER)
+
+#define PACK
+#define USED
+#define __attribute__(x)
+#define ALWAYS_INLINE
+#define INLINE __inline
+
+#else
+#error "Unsupported compiler"
+#endif
+
+/*--------------------------------------------------------------------------*/
+/*          Alignment masks                                                 */
+/*--------------------------------------------------------------------------*/
+
+#define ALIGNMENT_MASK_4_BYTE     ((uint32)0x00000003)
+#define ALIGNMENT_MASK_16_BYTE    ((uint32)0x0000000F)
+
+/* Test for alignment on an arbitrary byte boundary - TRUE if aligned */
+
+#define IS_ALIGNED(addr, mask) (((((uint32)addr) & mask) ? FALSE : TRUE))
+
+/*--------------------------------------------------------------------------*/
+/*          Boolean Constants                                               */
+/*--------------------------------------------------------------------------*/
+
+#if !defined FALSE && !defined TRUE
+#define TRUE            (1)   /* page 207 K+R 2nd Edition */
+#define FALSE           (0)
+#endif /* !defined FALSE && #if !defined TRUE */
+
+/*     Note that WINDOWS.H also defines TRUE and FALSE                 */
+
+/*--------------------------------------------------------------------------*/
+/*          Null pointers                                                   */
+/*--------------------------------------------------------------------------*/
+
+/* NULL data pointer */
+#if !defined NULL
+#define NULL                    ( (void *) 0 )
+#endif
+
+/* NULL routine pointer */
+#if !defined RNULL
+#define RNULL                   ((void *) 0 ())
+#endif
+
+/*--------------------------------------------------------------------------*/
+/*          Macros for setting/clearing bits efficiently                    */
+/*--------------------------------------------------------------------------*/
+
+#define U8_CLR_BITS( P, B )   (( *(uint8 *)P ) &= ~( B ))
+#define U8_SET_BITS( P, B )   (( *(uint8 *)P ) |=  ( B ))
+#define U16_CLR_BITS( P, B )  (( *(uint16 *)P ) &= ~( B ))
+#define U16_SET_BITS( P, B )  (( *(uint16 *)P ) |=  ( B ))
+#define U32_CLR_BITS( P, B )  (( *(uint32 *)P ) &= ~( B ))
+#define U32_SET_BITS( P, B )  (( *(uint32 *)P ) |=  ( B ))
+#define U64_CLR_BITS( P, B )  (( *(uint64 *)P ) &= ~( B ))
+#define U64_SET_BITS( P, B )  (( *(uint64 *)P ) |=  ( B ))
+
+/*--------------------------------------------------------------------------*/
+/*          Macros for obtaining maximum/minimum values                     */
+/*--------------------------------------------------------------------------*/
+#ifndef MAX
+#define MAX(A,B)                ( ( ( A ) > ( B ) ) ? ( A ) : ( B ) )
+#endif
+#ifndef MIN
+#define MIN(A,B)                ( ( ( A ) < ( B ) ) ? ( A ) : ( B ) )
+#endif
+
+/*--------------------------------------------------------------------------*/
+/*          Number of bits in quantities                                    */
+/*--------------------------------------------------------------------------*/
+
+#define BITS_PER_U32            (32)
+#define BITS_PER_U16            (16)
+#define BITS_PER_U8             (8)
+#define BITS_PER_NIBBLE         (4)
+
+/*--------------------------------------------------------------------------*/
+/*          Masking macros                                                  */
+/*--------------------------------------------------------------------------*/
+
+#define U8_LOW_NIBBLE_MASK      (0x0F)
+#define U8_HIGH_NIBBLE_MASK     (0xF0)
+
+#define U16_LOW_U8_MASK         (0x00FF)
+#define U16_HIGH_U8_MASK        (0xFF00)
+
+#define U32_LOWEST_U8_MASK      (0x000000FFL)
+#define U32_LOW_U8_MASK         (0x0000FF00L)
+#define U32_HIGH_U8_MASK        (0x00FF0000L)
+#define U32_HIGHEST_U8_MASK     (0xFF000000L)
+
+#define U32_LOWEST_U16_MASK     (0x0000FFFFL)
+#define U32_HIGHEST_U16_MASK    (0xFFFF0000L)
+
+#define U64_LOWEST_U32_MASK     (0x00000000FFFFFFFFLL)
+#define U64_HIGHEST_U32_MASK    (0xFFFFFFFF00000000LL)
+
+/*--------------------------------------------------------------------------*/
+/*          Macros for extracting uint8s from a uint16                      */
+/*--------------------------------------------------------------------------*/
+
+/* NOTE: U16_UPPER_U8 is only safe for an unsigned U16 as >> fills with the sign bit for signed variables */
+#define U16_UPPER_U8( x )      ((uint8) ((x) >> BITS_PER_U8))
+#define U16_LOWER_U8( x )      ((uint8) (((x) & U16_LOW_U8_MASK)))
+
+/*--------------------------------------------------------------------------*/
+/*          Macros for extracting uint8s from a uint32                      */
+/*--------------------------------------------------------------------------*/
+
+#define U32_HIGHEST_U8( x ) ((uint8)(((x) & U32_HIGHEST_U8_MASK) >> (BITS_PER_U16 + BITS_PER_U8)))
+
+#define U32_HIGH_U8( x ) ((uint8)( ( ( x ) & U32_HIGH_U8_MASK ) >> BITS_PER_U16 ))
+
+#define U32_LOW_U8( x ) ((uint8)( ( ( x ) & U32_LOW_U8_MASK ) >> BITS_PER_U8 ))
+
+#define U32_LOWEST_U8( x ) ((uint8)( ( ( x ) & U32_LOWEST_U8_MASK ) ))
+
+/*--------------------------------------------------------------------------*/
+/*          Macros for extracting uint16s from a uint32                     */
+/*--------------------------------------------------------------------------*/
+
+#define U32_UPPER_U16( x )     ((uint16)( ( ( x ) & U32_HIGHEST_U16_MASK ) >> ( BITS_PER_U16 ) ))
+#define U32_LOWER_U16( x )     ((uint16)( ( ( x ) & U32_LOWEST_U16_MASK ) ))
+
+/*--------------------------------------------------------------------------*/
+/*          Macros for extracting uint32s from a uint64                     */
+/*--------------------------------------------------------------------------*/
+
+#define U64_UPPER_U32( x )     ((uint32)( ( ( x ) & U64_HIGHEST_U32_MASK ) >> ( BITS_PER_U32 ) ))
+#define U64_LOWER_U32( x )     ((uint32)( ( ( x ) & U64_LOWEST_U32_MASK ) ))
+
+/*--------------------------------------------------------------------------*/
+/*         Macros for assembling byte sequences into various word sizes     */
+/*--------------------------------------------------------------------------*/
+
+/* B0 - LSB, B3 - MSB */
+
+#ifdef HOST_PROCESSOR_BIG_ENDIAN
+/* BIG ENDIAN DEFINITIONS */
+#define BYTE_ORDER_32(B3, B2, B1, B0)   ((B0) + (B1<<8) + (B2<<16) + (B3<<24))
+
+#define BYTE_ORDER_24(B2, B1, B0)       ((B0) + (B1<<8) + (B2<<16))
+
+#define BYTE_ORDER_16(B1, B0)           (uint16)(((B0) + (B1<<8)))
+
+#define BYTE_ORDER_8(B0)                (B0)
+
+#define BYTE_ORDER_4(B0)                (B0)
+#else
+/* LITTLE ENDIAN DEFINITIONS */
+#define BYTE_ORDER_32(B3, B2, B1, B0)   ((B3) + (B2<<8) + (B1<<16) + (B0<<24))
+
+#define BYTE_ORDER_24(B2, B1, B0)       ((B2) + (B1<<8) + (B0<<16))
+
+#define BYTE_ORDER_16(B1, B0)           (uint16)(((B1) + (B0<<8)))
+
+#define BYTE_ORDER_8(B0)                (B0)
+
+#define BYTE_ORDER_4(B0)                (B0)
+#endif
+
+/*--------------------------------------------------------------------------*/
+/*          Storage classes                                                 */
+/*--------------------------------------------------------------------------*/
+
+#if !defined PUBLIC
+#define PUBLIC
+#endif
+
+#if !defined MODULE
+#define MODULE
+#endif
+
+#if !defined PRIVATE
+#define PRIVATE static
+#endif
+
+#if !defined BANKED
+#define BANKED
+#endif
+
+/*--------------------------------------------------------------------------*/
+/* Useful macro for variables that are not currently referenced             */
+/* Prevents compiler warnings and should not produce any code               */
+/*--------------------------------------------------------------------------*/
+
+#define VARIABLE_INTENTIONALLY_NOT_REFERENCED(x) (x=x);
+#define CONST_POINTER_INTENTIONALLY_NOT_REFERENCED(p) (*p);
+#define CONST_VARIABLE_INTENTIONALLY_NOT_REFERENCED(x) (x);
+
+/*--------------------------------------------------------------------------*/
+/* Offset of field m in a struct s                                          */
+/*--------------------------------------------------------------------------*/
+
+#if !defined(__GNUC__) && !defined(ECOS) && !defined(offsetof)
+#define offsetof(type, tag)     ( (int)&( (type *)0 )->tag )
+#endif
+
+/*--------------------------------------------------------------------------*/
+/*          Diagnostics                                                     */
+/*--------------------------------------------------------------------------*/
+
+/****************************************************************************/
+/***        Type Definitions                                              ***/
+/****************************************************************************/
+
+    #ifndef __cplusplus /* microsoft specific */
+        #ifndef bool /* Seems to need this in for certain M$ builds*/
+            typedef int                     bool;     /* boolean type */
+        #endif
+    #endif
+
+    typedef uint8_t                 BOOL_T;     /* boolean type nothing to do with C++ */
+    typedef uint8_t                 bool_t;     /* boolean type nothing to do with C++ */
+
+    typedef int8_t                  int8;
+    typedef int16_t                 int16;
+    typedef int32_t                 int32;
+    typedef int64_t                 int64;
+    typedef uint8_t                 uint8;
+    typedef uint16_t                uint16;
+    typedef uint32_t                uint32;
+    typedef uint64_t                uint64;
+
+    typedef char *                  string;
+
+    typedef volatile uint8          u8Register;
+    typedef volatile uint16         u16Register;
+    typedef volatile uint32         u32Register;
+
+/****************************************************************************/
+/***        Exported Functions                                            ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Exported Variables                                            ***/
+/****************************************************************************/
+
+#endif  /* JENDEFS_INCLUDED */
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/MicroSpecific/Include/MicroInt.h

@@ -0,0 +1,80 @@
+/*****************************************************************************
+ *
+ * MODULE:              Nested interrupt enabler
+ *
+ * COMPONENT:           $RCSfile: MicroInt.h,v $
+ *
+ * VERSION:             $Name:  $
+ *
+ * REVISION:            $Revision: 1.3 $
+ *
+ * DATED:               $Date: 2009/07/15 10:44:32 $
+ *
+ * STATUS:              $State: Exp $
+ *
+ * AUTHOR:              CJG
+ *
+ * DESCRIPTION:
+ * Nested interrupt functions and macros
+ *
+ ****************************************************************************
+ *
+ *  (c) Copyright JENNIC Ltd 2008
+ *
+ ****************************************************************************
+ *
+ * This software is owned by Jennic and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on Jennic products. You, and any third parties must reproduce
+ * the copyright and warranty notice and any other legend of ownership on each
+ * copy or partial copy of the software.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". JENNIC MAKES NO WARRANTIES, WHETHER
+ * EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE,
+ * ACCURACY OR LACK OF NEGLIGENCE. JENNIC SHALL NOT, IN ANY CIRCUMSTANCES,
+ * BE LIABLE FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO, SPECIAL,
+ * INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER.
+ *
+ * Copyright Jennic Ltd 2008. All rights reserved
+ *
+ ****************************************************************************/
+
+#ifndef  MICRO_INT_INCLUDED
+#define  MICRO_INT_INCLUDED
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/***        Include Files                                                 ***/
+/****************************************************************************/
+#include "MicroSpecific.h"
+
+/****************************************************************************/
+/***        Macro Definitions                                             ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Type Definitions                                              ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Exported Functions                                            ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Exported Variables                                            ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif  /* MICRO_INT_INCLUDED */
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific.h

@@ -0,0 +1,24 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/****************************************************************************/
+/***        Include files                                                 ***/
+/****************************************************************************/
+
+#define EXPAND1(x) x
+#define EXPAND2(x, y)    EXPAND1(x)y
+#define EXPAND3(x, y, z) EXPAND2(x, y)z
+
+/* Convoluted way to #include <MicroSpecific_JN51xx.h> */
+#undef INCLUDE_NAME
+#define INCLUDE_NAME <EXPAND3(MicroSpecific,JENNIC_CHIP_FAMILY_NAME,.h)>
+#include INCLUDE_NAME
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_JN518x.h

@@ -0,0 +1,17 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/****************************************************************************/
+/***        Include files                                                 ***/
+/****************************************************************************/
+
+#include "MicroSpecific_arm_sdk2.h"
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_arm_sdk2.h

@@ -0,0 +1,363 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef  MICRO_SPECIFIC_INCLUDED
+#define  MICRO_SPECIFIC_INCLUDED
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/***        Include Files                                                 ***/
+/****************************************************************************/
+#include <jendefs.h>
+#include "JN5189.h"
+
+extern void (*isr_handlers[])(void);
+
+/****************************************************************************/
+/***        Macro Definitions                                             ***/
+/****************************************************************************/
+
+/** @{ Defined system call numbers */
+#define SYSCALL_SEMIHOSTING   						0xAB
+
+#define SEMIHOSTING_WRITE0      					0x04
+#define SEMIHOSTING_READC       0x07
+/** @} */
+
+#define MICRO_INTERRUPT_EXCEPTION_OFFSET            16
+
+// number of bits are defined by the hardware
+#define MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS     __NVIC_PRIO_BITS
+
+// this macro depends on the setting of the priority group in the NVIC, setting G=3 in this case
+#define MICRO_INTERRUPT_MAX_PRIORITY                ((1 << MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS) - 1)
+// half way
+#define MICRO_INTERRUPT_MID_PRIORITY                (MICRO_INTERRUPT_MAX_PRIORITY/2)
+
+// Priority levels in the arm are higher for lower values - B-Semi chips were the other way around
+#define MICRO_INTERRUPT_ELEVATED_PRIORITY           (11)
+#define MICRO_INTERRUPT_MEDIUM_PRIORITY             (12)
+
+// priority/sub priority register 8-bits wide
+// read/write priority
+#define MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(W)     ((W) << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
+#define MICRO_INTERRUPT_READ_PRIORITY_VALUE(R)      ((R) >> (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
+// read/write sub-priority
+#define MICRO_INTERRUPT_SUBPRIORITY_MASK            ((1  << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS)) -1)
+#define MICRO_INTERRUPT_SUBPRIORITY_VALUE(S)        ((S) & (MICRO_INTERRUPT_SUBPRIORITY_MASK))
+
+#define asm					    __asm__
+
+#if 0 /* CJGTODO */
+// JN5172 interrupt mappings
+
+#define MICRO_ISR_NUM_TMR2                          0
+#define MICRO_ISR_NUM_TMR3                          1
+#define MICRO_ISR_NUM_TMR4                          2
+#define MICRO_ISR_NUM_TMR5                          3
+#define MICRO_ISR_NUM_TMR6                          4
+#define MICRO_ISR_NUM_TMR7                          5
+#define MICRO_ISR_NUM_SYSCTRL                       6
+#define MICRO_ISR_NUM_BBC                           7       // MAC
+#define MICRO_ISR_NUM_AES                           8
+#define MICRO_ISR_NUM_PHY                           9
+#define MICRO_ISR_NUM_UART0                         10
+#define MICRO_ISR_NUM_UART1                         11
+#define MICRO_ISR_NUM_SPIS                          12
+#define MICRO_ISR_NUM_SPIM                          13
+#define MICRO_ISR_NUM_I2C                           14
+#define MICRO_ISR_NUM_TMR0                          15
+#define MICRO_ISR_NUM_TMR1                          16
+#define MICRO_ISR_NUM_TMR8                          17     // TIMER_ADC
+#define MICRO_ISR_NUM_ANPER                         18
+#define MICRO_ISR_NUM_WDOG                          19
+// number of interrupts
+#define MICRO_ISR_NUM                               20
+// mask
+#define MICRO_ISR_EN_MASK                           ((1 << MICRO_ISR_NUM) - 1)
+
+/* NOTE: Following are based on values above. Not all are defined for all
+   chips. So if an error is raised by the MICRO_ISR_MASK_* macros below, look
+   to see if the corresponding MICRO_ISR_NUM_* macro is defined above. If it
+   isn't, that peripheral is not present on the defined chip */
+#define MICRO_ISR_MASK_SYSCTRL  (1 << MICRO_ISR_NUM_SYSCTRL)
+#define MICRO_ISR_MASK_BBC      (1 << MICRO_ISR_NUM_BBC)
+#define MICRO_ISR_MASK_AES      (1 << MICRO_ISR_NUM_AES)
+#define MICRO_ISR_MASK_PHY      (1 << MICRO_ISR_NUM_PHY)
+#define MICRO_ISR_MASK_UART0    (1 << MICRO_ISR_NUM_UART0)
+#define MICRO_ISR_MASK_UART1    (1 << MICRO_ISR_NUM_UART1)
+#define MICRO_ISR_MASK_TMR0     (1 << MICRO_ISR_NUM_TMR0)
+#define MICRO_ISR_MASK_TMR1     (1 << MICRO_ISR_NUM_TMR1)
+#define MICRO_ISR_MASK_TMR2     (1 << MICRO_ISR_NUM_TMR2)
+#define MICRO_ISR_MASK_TMR3     (1 << MICRO_ISR_NUM_TMR3)
+#define MICRO_ISR_MASK_TMR4     (1 << MICRO_ISR_NUM_TMR4)
+#define MICRO_ISR_MASK_I2C      (1 << MICRO_ISR_NUM_I2C)
+#define MICRO_ISR_MASK_SPIM     (1 << MICRO_ISR_NUM_SPIM)
+#define MICRO_ISR_MASK_SPIS     (1 << MICRO_ISR_NUM_SPIS)
+#define MICRO_ISR_MASK_INTPER   (1 << MICRO_ISR_NUM_INTPER)
+#define MICRO_ISR_MASK_ANPER    (1 << MICRO_ISR_NUM_ANPER)
+#define MICRO_ISR_MASK_WDOG     (1 << MICRO_ISR_NUM_WDOG)
+#endif
+
+/* Handy macros for controlling interrupts, PIC, interrupt levels */
+
+#define MICRO_ENABLE_INTERRUPTS()                                           \
+        asm volatile ("CPSIE I;" : : );
+
+#define MICRO_DISABLE_INTERRUPTS()                                          \
+        asm volatile ("CPSID I;" : : );
+
+extern void vAHI_InterruptSetPriority(uint32 u32Mask, uint8 u8Level);
+extern uint8 u8AHI_InterruptGetPriority(uint32 u32InterruptNumber);
+extern void vAHI_InterruptDisable(uint32 u32EnableMask);
+extern void vAHI_TickTimerIntEnable(bool_t bIntEnable);
+extern void vAHI_InterruptSetActivePriorityLevel(uint8 u8Level);
+extern uint8 u8AHI_InterruptReadActivePriorityLevel(void);
+
+#define MICRO_ENABLE_TICK_TIMER_INTERRUPT();                                \
+        vAHI_TickTimerIntEnable(TRUE);
+
+// use same value as Jennic/BA devices
+#define MICRO_SET_PIC_ENABLE(A)                                             \
+    vAHI_InterruptSetPriority(A, 8);
+
+#define MICRO_CLEAR_PIC_ENABLE(A)                                           \
+    vAHI_InterruptDisable(A)
+
+#define MICRO_SET_PIC_PRIORITY_LEVEL(A,B)                                   \
+    vAHI_InterruptSetPriority(A, B);
+
+#define MICRO_GET_PIC_PRIORITY_LEVEL(A)                                     \
+    u8AHI_InterruptGetPriority(A);
+
+/* MRS Move to register from status */
+/* MSR Move to status register */
+#define MICRO_SET_ACTIVE_INT_LEVEL(A)                                       \
+   ({                                                                       \
+       register uint32 __u32interruptLevelStore  = A;                       \
+        asm volatile ("MSR BASEPRI, %[intlevelstore];"                      \
+            :                                                               \
+            :[intlevelstore] "r"(__u32interruptLevelStore)                  \
+            );                                                              \
+   })
+
+#define MICRO_SET_ACTIVE_INT_LEVEL_MAX(A)                                   \
+   ({                                                                       \
+       register uint32 __u32interruptLevelStore  = A;                       \
+        asm volatile ("MSR BASEPRI_MAX, %[intlevelstore];"                  \
+            :                                                               \
+            :[intlevelstore] "r"(__u32interruptLevelStore)                  \
+            );                                                              \
+   })
+
+#define MICRO_GET_ACTIVE_INT_LEVEL()                                        \
+    ({                                                                      \
+        register uint32 __u32interruptActiveLevel;                          \
+        asm volatile ("MRS %[activelevelstore], BASEPRI;"                   \
+            :[activelevelstore] "=r"(__u32interruptActiveLevel)             \
+            : );                                                            \
+        __u32interruptActiveLevel;                                          \
+    })
+
+#define MICRO_SET_PRIMASK_LEVEL(A)                                          \
+   ({                                                                       \
+        register uint32 __u32primaskLevelStore  = A;                        \
+        asm volatile ("MSR PRIMASK, %[primasklevelstore];"                  \
+            :                                                               \
+            :[primasklevelstore] "r"(__u32primaskLevelStore)                \
+            );                                                              \
+   })
+
+#define MICRO_GET_PRIMASK_LEVEL()                                           \
+   ({                                                                       \
+        register uint32 __u32primaskLevelStore;                             \
+        asm volatile ("MRS %[primasklevelstore], PRIMASK;"                  \
+            :[primasklevelstore] "=r"(__u32primaskLevelStore)               \
+            :                                                               \
+            );                                                              \
+        __u32primaskLevelStore;                                             \
+   })
+
+// read back PRIMASK status into u32Store variable then disable the interrupts
+#define MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store)                         \
+   ({                                                                       \
+        asm volatile ("MRS %[primasklevelstore], PRIMASK;"                  \
+                :[primasklevelstore] "=r"(u32Store)                         \
+                :                                                           \
+                );                                                          \
+        asm volatile ("CPSID I;" : : );                                     \
+   })
+
+#define MICRO_RESTORE_INTERRUPTS(u32Store)                                  \
+   ({                                                                       \
+        asm volatile ("MSR PRIMASK, %[primasklevelstore];"                  \
+                :                                                           \
+                :[primasklevelstore] "r"(u32Store)                          \
+                );                                                          \
+   })
+
+// using AAPCS the parameter (the stack frame) will map to r0
+#define MICRO_GET_EXCEPTION_STACK_FRAME()                                   \
+   {                                                                        \
+        asm volatile("MRS R0, MSP");                                        \
+   }
+
+// macro using privilege/non�privilege model
+#define MICRO_GET_EXCEPTION_STACK_FRAME_PNPM()                              \
+   ({                                                                       \
+        asm volatile("TST LR, #4");                                         \
+        asm volatile("ITE EQ");                                             \
+        asm volatile("MRSEQ R0, MSP");                                      \
+        asm volatile("MRSNE R0, PSP");                                      \
+    })
+
+#define FF1(__input)                                                        \
+     ({ register uint32 __reverse, __result, __return;                      \
+        asm volatile ("RBIT %[reverse], %[input];"                          \
+            : [reverse] "=r" (__reverse)                                    \
+            : [input]  "r"  (__input)                                       \
+                     );                                                     \
+        asm volatile ("CLZ %[result], %[reverse];"                          \
+            : [result] "=r" (__result)                                      \
+            : [reverse]  "r"  (__reverse)                                   \
+            );                                                              \
+        __return = ((__result == 32) ? 0 : __result+1);                  \
+        __return; })
+
+#if 0 /* In chip_jn518x\inc/core_cmInstr.h */
+/* Reverse byte order */
+#define __REV(A)                                        \
+     ({                                                 \
+        register uint32 __reverse, __input = A;         \
+        asm volatile ("REV %[reverse], %[input];"       \
+            : [reverse] "=r" (__reverse)                \
+            : [input]  "r"  (__input)                   \
+                     );                                 \
+        __reverse;                                      \
+        })
+#endif
+
+#define MICRO_GET_LX()                                                      \
+   ({                                                                       \
+        register uint32 __u32lxRegister;                                    \
+        asm volatile ("MOV %[lxRegister], R14;"                             \
+            :[lxRegister] "=r"(__u32lxRegister)                             \
+            :                                                               \
+            );                                                              \
+        __u32lxRegister;                                                    \
+   })
+
+#define MICRO_GET_STACK_LEVEL()                                             \
+   ({                                                                       \
+        register uint32 __u32stackRegister;                                 \
+        asm volatile ("MOV %[stackRegister], SP;"                           \
+            :[stackRegister] "=r"(__u32stackRegister)                       \
+            :                                                               \
+            );                                                              \
+        __u32stackRegister;                                                 \
+   })
+
+/* Interrupt Handler registration - only useful if you're putting the handlers
+ * in RAM */
+
+/* Location of isr_handlers is no longer at a known location, but we can link
+   to it directly instead */
+#define MICRO_SET_INT_HANDLER(INT, FUNC);                                   \
+    isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)] = (void *)(FUNC);
+
+#define MICRO_GET_INT_HANDLER(INT)                                          \
+    (isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)])
+
+/* Nested interrupt control */
+#define MICRO_INT_STORAGE         tsMicroIntStorage sIntStorage
+#define MICRO_INT_ENABLE_ONLY(A)  vMicroIntEnableOnly(&sIntStorage, A)
+#define MICRO_INT_RESTORE_STATE() vMicroIntRestoreState(&sIntStorage)
+
+/* Exception Handlers */
+#define MICRO_ESR_NUM_RESETISR                    1
+#define MICRO_ESR_NUM_NMI                         2
+#define MICRO_ESR_NUM_HARDFAULT                   3
+#define MICRO_ESR_NUM_MEMMANAGE                   4
+#define MICRO_ESR_NUM_BUSFAULT                    5
+#define MICRO_ESR_NUM_USGFAULT                    6
+// 4 reserved handlers here
+#define MICRO_ESR_NUM_SVCALL                      11
+#define MICRO_ESR_NUM_DEBUGMON                    12
+// 1 reserved handler here
+#define MICRO_ESR_NUM_PENDSV                      14
+#define MICRO_ESR_NUM_SYSTICK                     15
+
+/* Location of exception_handlers is no longer at a known location, but we can link
+   to it directly instead - only useful if you're putting the handlers
+ * in RAM */
+#define MICRO_SET_EXCEPTION_HANDLER(EXCEPTION, FUNC)                        \
+    isr_handlers[EXCEPTION] = (void *)(FUNC);
+
+#define MICRO_GET_EXCEPTION_HANDLER(INT)                                    \
+    (isr_handlers[EXCEPTION])
+
+/* NOP instruction */
+#define MICRO_NOP()                                                         \
+    {                                                                       \
+        asm volatile ("nop;");                                              \
+    }
+
+/* TRAP instruction */
+#define MICRO_TRAP()                                                        \
+    {                                                                       \
+        asm volatile("BKPT 0;");                                            \
+    }
+
+#define MICRO_JUMP_TO_ADDRESS(ADDRESS)                                      \
+   ({                                                                       \
+       register uint32 __u32programAddressStore = ADDRESS | 0x1;            \
+       asm volatile ("BLX %[programAddressStore];"                           \
+           :                                                                \
+           :[programAddressStore] "r"(__u32programAddressStore));           \
+    })
+
+/****************************************************************************/
+/***        Type Definitions                                              ***/
+/****************************************************************************/
+/* Nested interrupt control */
+typedef struct
+{
+    uint8 u8Level;
+} tsMicroIntStorage;
+
+/****************************************************************************/
+/***        Exported Functions                                            ***/
+/****************************************************************************/
+PUBLIC void vAHI_InitialiseInterruptController(uint32 *pu32InterruptVectorTable);
+
+/* Nested interrupt control */
+PUBLIC void vMicroIntSetGlobalEnable(uint32 u32EnableMask);
+PUBLIC void vMicroIntEnableOnly(tsMicroIntStorage *, uint32 u32EnableMask);
+PUBLIC void vMicroIntRestoreState(tsMicroIntStorage *);
+/* Default Exception Handler */
+PUBLIC void vIntDefaultHandler(void);
+
+PUBLIC void __attribute__((noinline)) vMicroSyscall(volatile uint32 u32SysCallNumber, ...);
+PUBLIC void __attribute__((noinline)) vMicroSemihost(volatile uint32 u32SemihostNumber, ...);
+
+/****************************************************************************/
+/***        Exported Variables                                            ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif  /* MICRO_SPECIFIC_INCLUDED */
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/Radio_JN5189/.cproject

@@ -0,0 +1,389 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.crt.advproject.config.lib.debug.1561772805">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.lib.debug.1561772805" moduleId="org.eclipse.cdt.core.settings" name="Radio_Lib_Debug">
+				<macros>
+					<stringMacro name="JENNIC_CHIP_FAMILY" type="VALUE_TEXT" value="JN518x"/>
+					<stringMacro name="SDK_BASE_DIR" type="VALUE_TEXT" value="../../../.."/>
+				</macros>
+				<externalSettings>
+					<externalSetting>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/Radio"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/Radio/Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/Radio/Radio Lib Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/Radio/Radio_Lib Debug"/>
+						<entry flags="RESOLVED" kind="libraryFile" name="Radio_JN518x" srcPrefixMapping="" srcRootPath=""/>
+					</externalSetting>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="a" artifactName="${ProjName}_${JENNIC_CHIP_FAMILY}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib" cleanCommand="rm -rf" description="Debug Lib for ES2 (default)" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.lib.debug.1561772805" name="Radio_Lib_Debug" parent="com.crt.advproject.config.lib.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;lib${BuildArtifactFileName}&quot; ; cp &quot;lib${BuildArtifactFileName}&quot; ../../Library">
+					<folderInfo id="com.crt.advproject.config.lib.debug.1561772805." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.lib.debug.49333772" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.lib.debug">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.lib.debug.819349249" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.lib.debug"/>
+							<builder buildPath="${workspace_loc:/Radio}/Debug" id="com.crt.advproject.builder.lib.debug.1594045844" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.lib.debug"/>
+							<tool id="com.crt.advproject.cpp.lib.debug.1636231222" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.lib.debug"/>
+							<tool id="com.crt.advproject.gcc.lib.debug.1370863409" name="MCU C Compiler" superClass="com.crt.advproject.gcc.lib.debug">
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+									<listOptionValue builtIn="false" value="__JN518X__"/>
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+									<listOptionValue builtIn="false" value="JENNIC_CHIP_FAMILY_JN518x"/>
+									<listOptionValue builtIn="false" value="__REDLIB__"/>
+									<listOptionValue builtIn="false" value="__CODE_RED"/>
+									<listOptionValue builtIn="false" value="CORE_M4"/>
+									<listOptionValue builtIn="false" value="CPU_JN518X"/>
+								</option>
+								<option id="gnu.c.compiler.option.misc.other.1645646958" name="Other flags" superClass="gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections" valueType="string"/>
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+									<listOptionValue builtIn="false" value="${SDK_BASE_DIR}/devices/JN5180"/>
+									<listOptionValue builtIn="false" value="../Include"/>
+									<listOptionValue builtIn="false" value="${SDK_BASE_DIR}/platform/drivers/common"/>
+								</option>
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+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="Source/radio_jn518x_review.c|Source/radio_jn518x_SiteSurveyPerTest.c|Source/radio_test_jn518x.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.crt.advproject.config.lib.debug.1561772805.625814887">
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+				<macros>
+					<stringMacro name="JENNIC_CHIP_FAMILY" type="VALUE_TEXT" value="JN518x"/>
+					<stringMacro name="SDK_BASE_DIR" type="VALUE_TEXT" value="../../../.."/>
+				</macros>
+				<externalSettings>
+					<externalSetting>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/Radio"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/Radio/Release"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/Radio/Radio Lib Release"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/Radio/Radio_Lib Release"/>
+						<entry flags="RESOLVED" kind="libraryFile" name="Radio_JN518x" srcPrefixMapping="" srcRootPath=""/>
+					</externalSetting>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="a" artifactName="${ProjName}_${JENNIC_CHIP_FAMILY}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib" cleanCommand="rm -rf" description="Release Lib for ES2 (default)" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.lib.debug.1561772805.625814887" name="Radio_Lib_Release" parent="com.crt.advproject.config.lib.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;lib${BuildArtifactFileName}&quot; ; cp &quot;lib${BuildArtifactFileName}&quot; ../../Library">
+					<folderInfo id="com.crt.advproject.config.lib.debug.1561772805.625814887." name="/" resourcePath="">
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+							<builder buildPath="${workspace_loc:/Radio}/Debug" id="com.crt.advproject.builder.lib.debug.1213270011" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.lib.debug"/>
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+	<storageModule moduleId="com.crt.config">
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+		<configuration configurationName="Debug Untrimmed and no MAC"/>
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+		<configuration configurationName="Radio Lib Debug Untrimmed and no MAC">
+			<resource resourceType="PROJECT" workspacePath="/Radio"/>
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third_party/nxp/JN5189/Radio_JN5189/.project

@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>Radio</name>
+	<comment></comment>
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+			<triggers>full,incremental,</triggers>
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+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>SDK_BASE_DIR</name>
+			<value>$%7BPARENT-1-WORKSPACE_LOC%7D</value>
+		</variable>
+	</variableList>
+</projectDescription>

third_party/nxp/JN5189/Radio_JN5189/Include/BbcAndPhyRegs.h

@@ -0,0 +1,365 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef BBC_AND_PHY_REGS_H
+#define BBC_AND_PHY_REGS_H
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+
+/****************************************************************************/
+/***        Include Files                                                 ***/
+/****************************************************************************/
+#include "jn518x.h"
+#include "jn518x_zb_mac.h"
+#include "jn518x_zb_modem.h"
+#include "jn518x_rfp_modem.h"
+
+/****************************************************************************/
+/***        Macro/Type Definitions                                        ***/
+/****************************************************************************/
+#define vREG_BbcWrite(REG, VAL)     JN518X_ZBMAC->REG = (VAL)
+#define u32REG_BbcRead(REG)         (JN518X_ZBMAC->REG)
+#define vREG_PhyWrite(REG, VAL)     JN518X_ZBMODEM->REG = (VAL)
+#define u32REG_PhyRead(REG)         (JN518X_ZBMODEM->REG)
+#define vREG_XcvrPhyWrite(REG, VAL) JN518X_ZBMODEM->REG = (VAL)
+#define u32REG_XcvrPhyRead(REG)     (JN518X_ZBMODEM->REG)
+
+#define vREG_PhyReadModWrite32(eOffset, u32Mask, u32Data)              \
+    vREG_PhyWrite(eOffset, (((u32Mask) & (u32Data))                    \
+                           | (~(u32Mask) & (u32REG_PhyRead(eOffset)))))
+
+#define vREG_BbcReadModWrite32(eOffset, u32Mask, u32Data)              \
+    vREG_BbcWrite(eOffset, (((u32Mask) & (u32Data))                    \
+                           | (~(u32Mask) & (u32REG_BbcRead(eOffset)))))
+
+#ifndef BIT_W_1
+#define BIT_W_1                                     0x00000001UL
+#define BIT_W_2                                     0x00000003UL
+#define BIT_W_3                                     0x00000007UL
+#define BIT_W_4                                     0x0000000FUL
+#define BIT_W_5                                     0x0000001FUL
+#define BIT_W_6                                     0x0000003FUL
+#define BIT_W_7                                     0x0000007FUL
+#define BIT_W_8                                     0x000000FFUL
+#define BIT_W_10                                    0x000003FFUL
+#define BIT_W_12                                    0x00000FFFUL
+#define BIT_W_15                                    0x00007FFFUL
+#define BIT_W_16                                    0x0000FFFFUL
+#define BIT_W_17                                    0x0001FFFFUL
+#define BIT_W_18                                    0x0003FFFFUL
+#define BIT_W_19                                    0x0007FFFFUL
+#define BIT_W_20                                    0x000FFFFFUL
+#define BIT_W_21                                    0x001FFFFFUL
+#define BIT_W_25                                    0x01FFFFFFUL
+#endif
+
+/**** BBC IER/ISR ****/
+#define REG_BBC_INT_TX_BIT      0
+#define REG_BBC_INT_TX_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_TX_BIT))
+#define REG_BBC_INT_RX_H_BIT    1
+#define REG_BBC_INT_RX_H_MASK   ((uint32)(BIT_W_1 << REG_BBC_INT_RX_H_BIT))
+#define REG_BBC_INT_RX_BIT      2
+#define REG_BBC_INT_RX_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_RX_BIT))
+#define REG_BBC_INT_M0_BIT      4
+#define REG_BBC_INT_M0_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_M0_BIT))
+#define REG_BBC_INT_M1_BIT      5
+#define REG_BBC_INT_M1_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_M1_BIT))
+#define REG_BBC_INT_M2_BIT      6
+#define REG_BBC_INT_M2_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_M2_BIT))
+#define REG_BBC_INT_M3_BIT      7
+#define REG_BBC_INT_M3_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_M3_BIT))
+#define REG_BBC_INT_T0_BIT      8
+#define REG_BBC_INT_T0_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_T0_BIT))
+#define REG_BBC_INT_T1_BIT      9
+#define REG_BBC_INT_T1_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_T1_BIT))
+#define REG_BBC_INT_T2_BIT      10
+#define REG_BBC_INT_T2_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_T2_BIT))
+#define REG_BBC_INT_T3_BIT      11
+#define REG_BBC_INT_T3_MASK     ((uint32)(BIT_W_1 << REG_BBC_INT_T3_BIT))
+#define REG_BBC_INT_TIMER_MASK  ((uint32)(BIT_W_6 << REG_BBC_INT_M0_BIT))
+
+/**** REG_BBC_TXMBEBT ****/
+#define REG_BBC_TXMBEBT_MINBE_BIT     (0)
+#define REG_BBC_TXMBEBT_MINBE_MASK    ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_MINBE_BIT))
+#define REG_BBC_TXMBEBT_MAXBO_BIT     (4)
+#define REG_BBC_TXMBEBT_MAXBO_MASK    ((uint32)(BIT_W_3 << REG_BBC_TXMBEBT_MAXBO_BIT))
+#define REG_BBC_TXMBEBT_BLE_BIT       (7)
+#define REG_BBC_TXMBEBT_MAXBE_BIT     (8)
+#define REG_BBC_TXMBEBT_MAXBE_MASK    ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_MAXBE_BIT))
+#define REG_BBC_TXMBEBT_CSMA_DLY_BIT  (12)
+#define REG_BBC_TXMBEBT_CSMA_DLY_MASK ((uint32)(BIT_W_1 << REG_BBC_TXMBEBT_CSMA_DLY_BIT))
+#define REG_BBC_TXMBEBT_DIR_DLY_BIT   (13)
+#define REG_BBC_TXMBEBT_DIR_DLY_MASK  ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_DIR_DLY_BIT))
+
+#define REG_BBC_TXMBEBT_FORMAT(dir_dly, min_be, ble, max_boffs, max_be) \
+    (((min_be)     & BIT_W_4) | \
+     (((ble)       & BIT_W_1) << REG_BBC_TXMBEBT_BLE_BIT)     | \
+     (((max_be)    & BIT_W_4) << REG_BBC_TXMBEBT_MAXBE_BIT)   | \
+     (((max_boffs) & BIT_W_3) << REG_BBC_TXMBEBT_MAXBO_BIT)   | \
+     (((dir_dly)   & BIT_W_4) << REG_BBC_TXMBEBT_DIR_DLY_BIT)   \
+    )
+
+/**** REG_TXSTAT ****/
+
+#define REG_BBC_TXSTAT_CCAE_BIT    0
+#define REG_BBC_TXSTAT_CCAE_MASK   ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_CCAE_BIT))
+#define REG_BBC_TXSTAT_ACKE_BIT    1
+#define REG_BBC_TXSTAT_ACKE_MASK   ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_ACKE_BIT))
+#define REG_BBC_TXSTAT_OOTE_BIT    2
+#define REG_BBC_TXSTAT_OOTE_MASK   ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_OOTE_BIT))
+#define REG_BBC_TXSTAT_RXABT_BIT   3
+#define REG_BBC_TXSTAT_RXABT_MASK  ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_RXABT_BIT))
+#define REG_BBC_TXSTAT_RXFP_BIT    4
+#define REG_BBC_TXSTAT_RXFP_MASK   ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_RXFP_BIT))
+#define REG_BBC_TXSTAT_TXTO_BIT    5
+#define REG_BBC_TXSTAT_TXTO_MASK   ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_TXTO_BIT))
+#define REG_BBC_TXSTAT_TXPCTO_BIT  6
+#define REG_BBC_TXSTAT_TXPCTO_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_TXPCTO_BIT))
+
+/**** TXCTL ****/
+
+#define REG_BBC_TXCTL_SCH_BIT   0
+#define REG_BBC_TXCTL_SCH_MASK  ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SCH_BIT))
+#define REG_BBC_TXCTL_SS_BIT    1
+#define REG_BBC_TXCTL_SS_MASK   ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SS_BIT))
+#define REG_BBC_TXCTL_SOVR_BIT  2
+#define REG_BBC_TXCTL_SOVR_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SOVR_BIT))
+#define REG_BBC_TXCTL_AA_BIT    3
+#define REG_BBC_TXCTL_AA_MASK   ((uint32)(BIT_W_1 << REG_BBC_TXCTL_AA_BIT))
+#define REG_BBC_TXCTL_MODE_BIT  4
+#define REG_BBC_TXCTL_MODE_MASK ((uint32)(BIT_W_2 << REG_BBC_TXCTL_MODE_BIT))
+
+#define REG_BBC_TXCTL_VALUE(sched_basis, sched_ss, slot_override, auto_ack, mode) \
+   (((sched_basis)    & BIT_W_1) | \
+    (((sched_ss)      & BIT_W_1) << REG_BBC_TXCTL_SS_BIT) | \
+    (((slot_override) & BIT_W_1) << REG_BBC_TXCTL_SOVR_BIT) | \
+    (((auto_ack)      & BIT_W_1) << REG_BBC_TXCTL_AA_BIT) | \
+    (((mode)          & BIT_W_2) << REG_BBC_TXCTL_MODE_BIT))
+
+#define REG_BBC_TXCTL_SEND_AT(mode) REG_BBC_TXCTL_VALUE(1, 1, 0, 1, (mode))
+#define REG_BBC_TXCTL_SEND_NOW(mode) REG_BBC_TXCTL_VALUE(0, 1, 0, 1, (mode))
+
+/**** RXMPID ****/
+#define REG_BBC_RXMPID_PAN_ID_BIT  0
+#define REG_BBC_RXMPID_PAN_ID_MASK ((uint32)(BIT_W_16 << REG_BBC_RXMPID_PAN_ID_BIT))
+#define REG_BBC_RXMPID_COORD_BIT   16
+#define REG_BBC_RXMPID_COORD_MASK  ((uint32)(BIT_W_1 << REG_BBC_RXMPID_COORD_BIT))
+
+/**** RXPROM ****/
+#define REG_BBC_RXPROM_AM_BIT    0
+#define REG_BBC_RXPROM_AM_MASK   ((uint32)(BIT_W_1 << REG_BBC_RXPROM_AM_BIT))
+#define REG_BBC_RXPROM_FCSE_BIT  1
+#define REG_BBC_RXPROM_FCSE_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_FCSE_BIT))
+#define REG_BBC_RXPROM_AMAL_BIT  2
+#define REG_BBC_RXPROM_AMAL_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_AMAL_BIT))
+
+/**** REG_RXSTAT ****/
+#define REG_BBC_RXSTAT_FCSE_BIT   0
+#define REG_BBC_RXSTAT_FCSE_MASK  ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_FCSE_BIT))
+#define REG_BBC_RXSTAT_ABORT_BIT  1
+#define REG_BBC_RXSTAT_ABORT_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_ABORT_BIT))
+#define REG_BBC_RXSTAT_INPKT_BIT  4
+#define REG_BBC_RXSTAT_INPKT_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_INPKT_BIT))
+#define REG_BBC_RXSTAT_MAL_BIT    5
+#define REG_BBC_RXSTAT_MAL_MASK   ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_MAL_BIT))
+
+
+/**** RXCTL ****/
+
+#define REG_BBC_RXCTL_SCH_BIT   0
+#define REG_BBC_RXCTL_SCH_MASK  ((uint32)(BIT_W_1 << REG_BBC_RXCTL_SCH_BIT))
+#define REG_BBC_RXCTL_SS_BIT    1
+#define REG_BBC_RXCTL_SS_MASK   ((uint32)(BIT_W_1 << REG_BBC_RXCTL_SS_BIT))
+#define REG_BBC_RXCTL_ICAP_BIT  2
+#define REG_BBC_RXCTL_ICAP_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_ICAP_BIT))
+#define REG_BBC_RXCTL_AA_BIT    3
+#define REG_BBC_RXCTL_AA_MASK   ((uint32)(BIT_W_1 << REG_BBC_RXCTL_AA_BIT))
+#define REG_BBC_RXCTL_PRSP_BIT  4
+#define REG_BBC_RXCTL_PRSP_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_PRSP_BIT))
+
+#define REG_BBC_RXCTL_FORMAT(sched_basis, sched_ss, in_cap, auto_ack) \
+   (((sched_basis) & BIT_W_1) | \
+    (((sched_ss)   & BIT_W_1) << REG_BBC_RXCTL_SS_BIT) | \
+    (((in_cap)     & BIT_W_1) << REG_BBC_RXCTL_ICAP_BIT) | \
+    (((auto_ack)   & BIT_W_1) << REG_BBC_RXCTL_AA_BIT))
+
+/**** SM_STATE ****/
+#define REG_BBC_SM_STATE_SUP_BIT   0
+#define REG_BBC_SM_STATE_SUP_MASK  ((uint32)(BIT_W_4 << REG_BBC_SM_STATE_SUP_BIT))
+#define REG_BBC_SM_STATE_CSMA_BIT  4
+#define REG_BBC_SM_STATE_CSMA_MASK ((uint32)(BIT_W_3 << REG_BBC_SM_STATE_CSMA_BIT))
+#define REG_BBC_SM_STATE_ISA_BIT   8
+#define REG_BBC_SM_STATE_ISA_MASK  ((uint32)(BIT_W_5 << REG_BBC_SM_STATE_ISA_BIT))
+
+/**** SCTCR ****/
+
+#define REG_BBC_SCTCR_E0_BIT    0
+#define REG_BBC_SCTCR_E0_MASK   ((uint32)(BIT_W_1 << REG_BBC_SCTCR_E0_BIT))
+#define REG_BBC_SCTCR_E1_BIT    1
+#define REG_BBC_SCTCR_E1_MASK   ((uint32)(BIT_W_1 << REG_BBC_SCTCR_E1_BIT))
+
+/**** SCTL ****/
+#define REG_BBC_SCTL_USE_BIT    0
+#define REG_BBC_SCTL_USE_MASK   ((uint32)(BIT_W_1 << REG_BBC_SCTL_USE_BIT))
+#define REG_BBC_SCTL_SNAP_BIT   1
+#define REG_BBC_SCTL_SNAP_MASK  ((uint32)(BIT_W_1 << REG_BBC_SCTL_SNAP_BIT))
+#define REG_BBC_SCTL_CO_BIT     2
+#define REG_BBC_SCTL_CO_MASK    ((uint32)(BIT_W_1 << REG_BBC_SCTL_CO_BIT))
+// bit name changed
+#define REG_BBC_SCTL_CE_BIT     2
+#define REG_BBC_SCTL_CE_MASK    ((uint32)(BIT_W_1 << REG_BBC_SCTL_CE_BIT))
+#define REG_BBC_SCTL_PHYON_BIT  3
+#define REG_BBC_SCTL_PHYON_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_PHYON_BIT))
+
+/**** RXFCTL/TXFCTL ****/
+
+/* Operations on Frame header */
+#define REG_BBC_FCTL_TYPE_BIT           0
+#define REG_BBC_FCTL_TYPE_MASK          ((uint32)(BIT_W_3/* << REG_BBC_FCTL_TYPE_BIT*/)) /* Optimised bit 0 */
+
+#define REG_BBC_FCTL_SEC_BIT            3
+#define REG_BBC_FCTL_SEC_MASK           ((uint32)(BIT_W_1 << REG_BBC_FCTL_SEC_BIT))
+
+#define REG_BBC_FCTL_FP_BIT             4
+#define REG_BBC_FCTL_FP_MASK            ((uint32)(BIT_W_1 << REG_BBC_FCTL_FP_BIT))
+
+#define REG_BBC_FCTL_ACK_BIT            5
+#define REG_BBC_FCTL_ACK_MASK           ((uint32)(BIT_W_1 << REG_BBC_FCTL_ACK_BIT))
+
+#define REG_BBC_FCTL_IP_BIT             6
+#define REG_BBC_FCTL_IP_MASK            ((uint32)(BIT_W_1 << REG_BBC_FCTL_IP_BIT))
+
+#define REG_BBC_FCTL_DAM_BIT            10
+#define REG_BBC_FCTL_DAM_MASK           ((uint32)(BIT_W_2 << REG_BBC_FCTL_DAM_BIT))
+#define REG_BBC_FCTL_DAM(x)             (((x) & REG_BBC_FCTL_DAM_MASK) >> REG_BBC_FCTL_DAM_BIT)
+
+#define REG_BBC_FCTL_SAM_BIT            14
+#define REG_BBC_FCTL_SAM_MASK           ((uint32)(BIT_W_2 << REG_BBC_FCTL_SAM_BIT))
+#define REG_BBC_FCTL_SAM(x)             (((x) & REG_BBC_FCTL_SAM_MASK) >> REG_BBC_FCTL_SAM_BIT)
+
+/* Frame types */
+#define REG_BBC_FCTL_TYPE_BEACON        0
+#define REG_BBC_FCTL_TYPE_DATA          1
+#define REG_BBC_FCTL_TYPE_ACK           2
+#define REG_BBC_FCTL_TYPE_CMD           3
+
+/* Addr modes */
+#define REG_BBC_FCTL_AM_NONE            0
+#define REG_BBC_FCTL_AM_RSVD            1
+#define REG_BBC_FCTL_AM_SHORT           2
+#define REG_BBC_FCTL_AM_EXT             3
+
+
+#define REG_BBC_FCTL_FORMAT(type, sec, fp, ack, ip, dam, sam) \
+    (((type) & BIT_W_3) | \
+     (((sec) & BIT_W_1) << REG_BBC_FCTL_SEC_BIT) | \
+     (((fp) & BIT_W_1) << REG_BBC_FCTL_FP_BIT) | \
+     (((ack) & BIT_W_1) << REG_BBC_FCTL_ACK_BIT) | \
+     (((ip) & BIT_W_1) << REG_BBC_FCTL_IP_BIT) | \
+     (((dam) & BIT_W_2) << REG_BBC_FCTL_DAM_BIT) | \
+     (((sam) & BIT_W_2) << REG_BBC_FCTL_SAM_BIT))
+
+
+/**** MCCA_CTRL ****/
+#define REG_PHY_MCCA_CCAM_BIT           0
+#define REG_PHY_MCCA_CCAM_MASK          ((uint32)(BIT_W_2 << REG_PHY_MCCA_CCAM_BIT))
+#define REG_PHY_MCCA_CCA_ED_THR_BIT     2
+#define REG_PHY_MCCA_CCA_ED_THR_MASK    ((uint32)(BIT_W_10 << REG_PHY_MCCA_CCA_ED_THR_BIT))
+
+/**** MSTAT ****/
+#define REG_PHY_MSTAT_ED_BIT           6
+#define REG_PHY_MSTAT_ED_MASK          ((uint32)(BIT_W_10 << REG_PHY_MSTAT_ED_BIT))
+#define REG_PHY_MSTAT_SQI_BIT          16
+#define REG_PHY_MSTAT_SQI_MASK         ((uint32)(BIT_W_8 << REG_PHY_MSTAT_SQI_BIT))
+#define REG_PHY_MSTAT_MCCAS_BIT        24
+#define REG_PHY_MSTAT_MCCAS_MASK       ((uint32)(BIT_W_1 << REG_PHY_MSTAT_MCCAS_BIT))
+
+/**** PHY_MCTRL ****/
+#define REG_PHY_MCTRL_MIOM_BIT          1
+#define REG_PHY_MCTRL_MIOM_MASK         ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MIOM_BIT))
+#define REG_PHY_MCTRL_MPHYON_BIT        2
+#define REG_PHY_MCTRL_MPHYON_MASK       ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MPHYON_BIT))
+#define REG_PHY_MCTRL_MPHYTX_BIT        3
+#define REG_PHY_MCTRL_MPHYTX_MASK       ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MPHYTX_BIT))
+#define REG_PHY_MCTRL_MCCAT_BIT         4
+#define REG_PHY_MCTRL_MCCAT_MASK        ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MCCAT_BIT))
+#define REG_PHY_MCTRL_MEDT_BIT          5
+#define REG_PHY_MCTRL_MEDT_MASK         ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MEDT_BIT))
+
+/**** PHY_PWR ****/
+#define REG_PHY_PWR_BIT                 0
+#define REG_PHY_PWR_MASK                ((uint32)(BIT_W_1 << REG_PHY_PWR_BIT))
+
+/**** PHY IER/ISR ****/
+#define REG_PHY_INT_ED_BIT               3
+#define REG_PHY_INT_ED_MASK              ((uint32)(BIT_W_1 << REG_PHY_INT_ED_BIT))
+#define REG_PHY_INT_CCA_BIT              4
+#define REG_PHY_INT_CCA_MASK             ((uint32)(BIT_W_1 << REG_PHY_INT_CCA_BIT))
+
+/* Register equivalents, mapping from old names to new ones */
+#define REG_BBC_ISR             ISR
+#define REG_BBC_IER             IER
+#define REG_BBC_RXCTL           RXCTL
+#define REG_BBC_SM_STATE        SM_STATE
+#define REG_BBC_MISR            MISR
+#define REG_BBC_SCFRC           SCFRC
+#define REG_BBC_SCESL           SCESL
+#define REG_BBC_RXMPID          RXMPID
+#define REG_BBC_RXMSAD          RXMSAD
+#define REG_BBC_RXMEADL         RXMEADL
+#define REG_BBC_RXMEADH         RXMEADH
+#define REG_BBC_RXETST          RXETST
+#define REG_BBC_TXCTL           TXCTL
+#define REG_BBC_SCTL            SCTL
+#define REG_BBC_RXBUFAD         RXBUFAD
+#define REG_BBC_RXPROM          RXPROM
+#define REG_BBC_RXSTAT          RXSTAT
+#define REG_BBC_RXTSTP          RXTSTP
+#define REG_BBC_TXRETRY         TXTRIES
+#define REG_BBC_TXMBEBT         TXMBEBT
+#define REG_BBC_TXTSTP          TXTSTP
+#define REG_BBC_TXCSMAC         TXCSMAC
+#define REG_BBC_TXBUFAD         TXBUFAD
+#define REG_BBC_TXSTAT          TXSTAT
+#define REG_BBC_TXASC           TXASC
+#define REG_BBC_PRBSS           PRBS_SEED
+#define REG_BBC_SCMR0           SCMR0
+#define REG_BBC_SCTR1           SCTR1
+#define REG_BBC_SCTCR           SCTCR
+#define REG_BBC_TXPEND          TXPEND
+#define REG_BBC_PRTT            PHYRXTUNETIME
+#define REG_BBC_TAT             TURNAROUNDTIME
+#define REG_BBC_LIFS_TURNAROUND LIFSTURNAROUNDTIME
+#define REG_BBC_SCTR0           SCTR0
+
+#define REG_PHY_CHAN            PHY_CHAN
+#define REG_PHY_MCTRL           PHY_MCTRL
+#define REG_PHY_MSTAT0          MSTAT
+#define REG_PHY_MCCA            MCCA_CTRL
+
+/****************************************************************************/
+/***        Exported Functions                                            ***/
+/****************************************************************************/
+
+
+/****************************************************************************/
+/***        Exported Variables                                            ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* #ifndef BBC_AND_PHY_REGS_H */
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/Radio_JN5189/Include/jn518x.h

@@ -0,0 +1,6 @@
+#include "JN5189.h"
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+#include "jn518xHW_ES1.h"
+#else
+#include "jn518xHW.h"
+#endif

third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_ble_link.h

@@ -0,0 +1,870 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef __BLE_LINK_IF_H__
+#define __BLE_LINK_IF_H__
+
+  typedef  struct {
+        /* Address 0x000 */
+        union {
+           __IO uint32_t RW_BLE_RWBLECNTL;
+
+        struct {
+           __IO uint32_t  rw_ble_rwblecntl : 32;
+          } RW_BLE_RWBLECNTL_b;
+        };
+        /* Address 0x004 */
+        union {
+           __IO uint32_t RW_BLE_VERSION;
+
+        struct {
+           __IO uint32_t  rw_ble_version : 32;
+          } RW_BLE_VERSION_b;
+        };
+        /* Address 0x008 */
+        union {
+           __IO uint32_t RW_BLE_RWBLECONF;
+
+        struct {
+           __IO uint32_t  rw_ble_rwbleconf : 32;
+          } RW_BLE_RWBLECONF_b;
+        };
+        /* Address 0x00C */
+        union {
+           __IO uint32_t RW_BLE_INTCNTL;
+
+        struct {
+           __IO uint32_t  rw_ble_intcntl : 32;
+          } RW_BLE_INTCNTL_b;
+        };
+        /* Address 0x010 */
+        union {
+           __IO uint32_t RW_BLE_INTSTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_intstat : 32;
+          } RW_BLE_INTSTAT_b;
+        };
+        /* Address 0x014 */
+        union {
+           __IO uint32_t RW_BLE_INTRAWSTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_intrawstat : 32;
+          } RW_BLE_INTRAWSTAT_b;
+        };
+        /* Address 0x018 */
+        union {
+           __IO uint32_t RW_BLE_INTACK;
+
+        struct {
+           __IO uint32_t  rw_ble_intack : 32;
+          } RW_BLE_INTACK_b;
+        };
+        /* Address 0x01C */
+        union {
+           __IO uint32_t RW_BLE_BASETIMECNT;
+
+        struct {
+           __IO uint32_t  rw_ble_basetimecnt : 32;
+          } RW_BLE_BASETIMECNT_b;
+        };
+        /* Address 0x020 */
+        union {
+           __IO uint32_t RW_BLE_FINETIMECNT;
+
+        struct {
+           __IO uint32_t  rw_ble_finetimecnt : 32;
+          } RW_BLE_FINETIMECNT_b;
+        };
+        /* Address 0x024 */
+        union {
+           __IO uint32_t RW_BLE_BDADDRL;
+
+        struct {
+           __IO uint32_t  rw_ble_bdaddrl : 32;
+          } RW_BLE_BDADDRL_b;
+        };
+        /* Address 0x028 */
+        union {
+           __IO uint32_t RW_BLE_BDADDRU;
+
+        struct {
+           __IO uint32_t  rw_ble_bdaddru : 32;
+          } RW_BLE_BDADDRU_b;
+        };
+        /* Address 0x02C */
+        union {
+           __IO uint32_t RW_BLE_ET_CURRENTRXDESCPTR;
+
+        struct {
+           __IO uint32_t  rw_ble_et_currentrxdescptr : 32;
+          } RW_BLE_ET_CURRENTRXDESCPTR_b;
+        };
+        /* Address 0x030 */
+        union {
+           __IO uint32_t RW_BLE_DEEPSLCNTL;
+
+        struct {
+           __IO uint32_t  rw_ble_deepslcntl : 32;
+          } RW_BLE_DEEPSLCNTL_b;
+        };
+        /* Address 0x034 */
+        union {
+           __IO uint32_t RW_BLE_DEEPSLWKUP;
+
+        struct {
+           __IO uint32_t  rw_ble_deepslwkup : 32;
+          } RW_BLE_DEEPSLWKUP_b;
+        };
+        /* Address 0x038 */
+        union {
+           __IO uint32_t RW_BLE_DEEPSLSTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_deepslstat : 32;
+          } RW_BLE_DEEPSLSTAT_b;
+        };
+        /* Address 0x03C */
+        union {
+           __IO uint32_t RW_BLE_ENBPRESET;
+
+        struct {
+           __IO uint32_t  rw_ble_enbpreset : 32;
+          } RW_BLE_ENBPRESET_b;
+        };
+        /* Address 0x040 */
+        union {
+           __IO uint32_t RW_BLE_FINECNTCORR;
+
+        struct {
+           __IO uint32_t  rw_ble_finecntcorr : 32;
+          } RW_BLE_FINECNTCORR_b;
+        };
+        /* Address 0x044 */
+        union {
+           __IO uint32_t RW_BLE_BASETIMECNTCORR;
+
+        struct {
+           __IO uint32_t  rw_ble_basetimecntcorr : 32;
+          } RW_BLE_BASETIMECNTCORR_b;
+        };
+        /* Addresses 0x048 - 0x04C */
+        __O  uint32_t  RESERVED048[2];
+        /* Address 0x050 */
+        union {
+           __IO uint32_t RW_BLE_DIAGCNTL;
+
+        struct {
+           __IO uint32_t  rw_ble_diagcntl : 32;
+          } RW_BLE_DIAGCNTL_b;
+        };
+        /* Address 0x054 */
+        union {
+           __IO uint32_t RW_BLE_DIAGSTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_diagstat : 32;
+          } RW_BLE_DIAGSTAT_b;
+        };
+        /* Address 0x058 */
+        union {
+           __IO uint32_t RW_BLE_DEBUGADDMAX;
+
+        struct {
+           __IO uint32_t  rw_ble_debugaddmax : 32;
+          } RW_BLE_DEBUGADDMAX_b;
+        };
+        /* Address 0x05C */
+        union {
+           __IO uint32_t RW_BLE_DEBUGADDMIN;
+
+        struct {
+           __IO uint32_t  rw_ble_debugaddmin : 32;
+          } RW_BLE_DEBUGADDMIN_b;
+        };
+        /* Address 0x060 */
+        union {
+           __IO uint32_t RW_BLE_ERRORTYPESTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_errortypestat : 32;
+          } RW_BLE_ERRORTYPESTAT_b;
+        };
+        /* Address 0x064 */
+        union {
+           __IO uint32_t RW_BLE_SWPROFILING;
+
+        struct {
+           __IO uint32_t  rw_ble_swprofiling : 32;
+          } RW_BLE_SWPROFILING_b;
+        };
+        /* Addresses 0x068 - 0x06C */
+        __O  uint32_t  RESERVED068[2];
+        /* Address 0x070 */
+        union {
+           __IO uint32_t RW_BLE_RADIOCNTL0;
+
+        struct {
+           __IO uint32_t  rw_ble_radiocntl0 : 32;
+          } RW_BLE_RADIOCNTL0_b;
+        };
+        /* Address 0x074 */
+        union {
+           __IO uint32_t RW_BLE_RADIOCNTL1;
+
+        struct {
+           __IO uint32_t  rw_ble_radiocntl1 : 32;
+          } RW_BLE_RADIOCNTL1_b;
+        };
+        /* Address 0x078 */
+        union {
+           __IO uint32_t RW_BLE_RADIOCNTL2;
+
+        struct {
+           __IO uint32_t  rw_ble_radiocntl2 : 32;
+          } RW_BLE_RADIOCNTL2_b;
+        };
+        /* Address 0x07C */
+        union {
+           __IO uint32_t RW_BLE_RADIOCNTL3;
+
+        struct {
+           __IO uint32_t  rw_ble_radiocntl3 : 32;
+          } RW_BLE_RADIOCNTL3_b;
+        };
+        /* Address 0x080 */
+        union {
+           __IO uint32_t RW_BLE_RADIOPWRUPDN;
+
+        struct {
+           __IO uint32_t  rw_ble_radiopwrupdn : 32;
+          } RW_BLE_RADIOPWRUPDN_b;
+        };
+        /* Address 0x084 */
+        union {
+           __IO uint32_t RW_BLE_SPIPTRCNTL0;
+
+        struct {
+           __IO uint32_t  rw_ble_spiptrcntl0 : 32;
+          } RW_BLE_SPIPTRCNTL0_b;
+        };
+        /* Address 0x088 */
+        union {
+           __IO uint32_t RW_BLE_SPIPTRCNTL1;
+
+        struct {
+           __IO uint32_t  rw_ble_spiptrcntl1 : 32;
+          } RW_BLE_SPIPTRCNTL1_b;
+        };
+        /* Address 0x08C */
+        union {
+           __IO uint32_t RW_BLE_SPIPTRCNTL2;
+
+        struct {
+           __IO uint32_t  rw_ble_spiptrcntl2 : 32;
+          } RW_BLE_SPIPTRCNTL2_b;
+        };
+        /* Address 0x090 */
+        union {
+           __IO uint32_t RW_BLE_ADVCHMAP;
+
+        struct {
+           __IO uint32_t  rw_ble_advchmap : 32;
+          } RW_BLE_ADVCHMAP_b;
+        };
+        /* Addresses 0x094 - 0x09C */
+        __O  uint32_t  RESERVED094[3];
+        /* Address 0x0A0 */
+        union {
+           __IO uint32_t RW_BLE_ADVTIM;
+
+        struct {
+           __IO uint32_t  rw_ble_advtim : 32;
+          } RW_BLE_ADVTIM_b;
+        };
+        /* Address 0x0A4 */
+        union {
+           __IO uint32_t RW_BLE_ACTSCANSTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_actscanstat : 32;
+          } RW_BLE_ACTSCANSTAT_b;
+        };
+        /* Addresses 0x0A8 - 0x0AC */
+        __O  uint32_t  RESERVED0A8[2];
+        /* Address 0x0B0 */
+        union {
+           __IO uint32_t RW_BLE_WLPUBADDPTR;
+
+        struct {
+           __IO uint32_t  rw_ble_wlpubaddptr : 32;
+          } RW_BLE_WLPUBADDPTR_b;
+        };
+        /* Address 0x0B4 */
+        union {
+           __IO uint32_t RW_BLE_WLPRIVADDPTR;
+
+        struct {
+           __IO uint32_t  rw_ble_wlprivaddptr : 32;
+          } RW_BLE_WLPRIVADDPTR_b;
+        };
+        /* Address 0x0B8 */
+        union {
+           __IO uint32_t RW_BLE_WLNBDEV;
+
+        struct {
+           __IO uint32_t  rw_ble_wlnbdev : 32;
+          } RW_BLE_WLNBDEV_b;
+        };
+        /* Address 0x0BC */
+        __O  uint32_t  RESERVED0BC[1];
+        /* Address 0x0C0 */
+        union {
+           __IO uint32_t RW_BLE_AESCNTL;
+
+        struct {
+           __IO uint32_t  rw_ble_aescntl : 32;
+          } RW_BLE_AESCNTL_b;
+        };
+        /* Address 0x0C4 */
+        union {
+           __IO uint32_t RW_BLE_AESKEY31_0;
+
+        struct {
+           __IO uint32_t  rw_ble_aeskey31_0 : 32;
+          } RW_BLE_AESKEY31_0_b;
+        };
+        /* Address 0x0C8 */
+        union {
+           __IO uint32_t RW_BLE_AESKEY63_32;
+
+        struct {
+           __IO uint32_t  rw_ble_aeskey63_32 : 32;
+          } RW_BLE_AESKEY63_32_b;
+        };
+        /* Address 0x0CC */
+        union {
+           __IO uint32_t RW_BLE_AESKEY95_64;
+
+        struct {
+           __IO uint32_t  rw_ble_aeskey95_64 : 32;
+          } RW_BLE_AESKEY95_64_b;
+        };
+        /* Address 0x0D0 */
+        union {
+           __IO uint32_t RW_BLE_AESKEY127_96;
+
+        struct {
+           __IO uint32_t  rw_ble_aeskey127_96 : 32;
+          } RW_BLE_AESKEY127_96_b;
+        };
+        /* Address 0x0D4 */
+        union {
+           __IO uint32_t RW_BLE_AESPTR;
+
+        struct {
+           __IO uint32_t  rw_ble_aesptr : 32;
+          } RW_BLE_AESPTR_b;
+        };
+        /* Address 0x0D8 */
+        union {
+           __IO uint32_t RW_BLE_TXMICVAL;
+
+        struct {
+           __IO uint32_t  rw_ble_txmicval : 32;
+          } RW_BLE_TXMICVAL_b;
+        };
+        /* Address 0x0DC */
+        union {
+           __IO uint32_t RW_BLE_RXMICVAL;
+
+        struct {
+           __IO uint32_t  rw_ble_rxmicval : 32;
+          } RW_BLE_RXMICVAL_b;
+        };
+        /* Address 0x0E0 */
+        union {
+           __IO uint32_t RW_BLE_RFTESTCNTL;
+
+        struct {
+           __IO uint32_t  rw_ble_rftestcntl : 32;
+          } RW_BLE_RFTESTCNTL_b;
+        };
+        /* Address 0x0E4 */
+        union {
+           __IO uint32_t RW_BLE_RFTESTTXSTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_rftesttxstat : 32;
+          } RW_BLE_RFTESTTXSTAT_b;
+        };
+        /* Address 0x0E8 */
+        union {
+           __IO uint32_t RW_BLE_RFTESTRXSTAT;
+
+        struct {
+           __IO uint32_t  rw_ble_rftestrxstat : 32;
+          } RW_BLE_RFTESTRXSTAT_b;
+        };
+        /* Address 0x0EC */
+        __O  uint32_t  RESERVED0EC[1];
+        /* Address 0x0F0 */
+        union {
+           __IO uint32_t RW_BLE_TIMGENCNTL;
+
+        struct {
+           __IO uint32_t  rw_ble_timgencntl : 32;
+          } RW_BLE_TIMGENCNTL_b;
+        };
+        /* Address 0x0F4 */
+        union {
+           __IO uint32_t RW_BLE_GROSSTIMTGT;
+
+        struct {
+           __IO uint32_t  rw_ble_grosstimtgt : 32;
+          } RW_BLE_GROSSTIMTGT_b;
+        };
+        /* Address 0x0F8 */
+        union {
+           __IO uint32_t RW_BLE_FINETIMTGT;
+
+        struct {
+           __IO uint32_t  rw_ble_finetimtgt : 32;
+          } RW_BLE_FINETIMTGT_b;
+        };
+        /* Address 0x0FC */
+        __O  uint32_t  RESERVED0FC[1];
+        /* Address 0x100 */
+        union {
+           __IO uint32_t RW_BLE_COEXIFCNTL0;
+
+        struct {
+           __IO uint32_t  rw_ble_coexifcntl0 : 32;
+          } RW_BLE_COEXIFCNTL0_b;
+        };
+        /* Address 0x104 */
+        union {
+           __IO uint32_t RW_BLE_COEXIFCNTL1;
+
+        struct {
+           __IO uint32_t  rw_ble_coexifcntl1 : 32;
+          } RW_BLE_COEXIFCNTL1_b;
+        };
+        /* Address 0x108 */
+        union {
+           __IO uint32_t RW_BLE_COEXIFCNTL2;
+
+        struct {
+           __IO uint32_t  rw_ble_coexifcntl2 : 32;
+          } RW_BLE_COEXIFCNTL2_b;
+        };
+        /* Address 0x10C */
+        union {
+           __IO uint32_t RW_BLE_BLEMPRIO0;
+
+        struct {
+           __IO uint32_t  rw_ble_blemprio0 : 32;
+          } RW_BLE_BLEMPRIO0_b;
+        };
+        /* Address 0x110 */
+        union {
+           __IO uint32_t RW_BLE_BLEMPRIO1;
+
+        struct {
+           __IO uint32_t  rw_ble_blemprio1 : 32;
+          } RW_BLE_BLEMPRIO1_b;
+        };
+        /* Addresses 0x114 - 0x11C */
+        __O  uint32_t  RESERVED114[3];
+        /* Address 0x120 */
+        union {
+           __IO uint32_t RW_BLE_RALPTR;
+
+        struct {
+           __IO uint32_t  rw_ble_ralptr : 32;
+          } RW_BLE_RALPTR_b;
+        };
+        /* Address 0x124 */
+        union {
+           __IO uint32_t RW_BLE_RALNBDEV;
+
+        struct {
+           __IO uint32_t  rw_ble_ralnbdev : 32;
+          } RW_BLE_RALNBDEV_b;
+        };
+        /* Address 0x128 */
+        union {
+           __IO uint32_t RW_BLE_RAL_LOCAL_RND;
+
+        struct {
+           __IO uint32_t  rw_ble_ral_local_rnd : 32;
+          } RW_BLE_RAL_LOCAL_RND_b;
+        };
+        /* Address 0x12C */
+        union {
+           __IO uint32_t RW_BLE_RAL_PEER_RND;
+
+        struct {
+           __IO uint32_t  rw_ble_ral_peer_rnd : 32;
+          } RW_BLE_RAL_PEER_RND_b;
+        };
+        /* Address 0x130 */
+        union {
+           __IO uint32_t RW_BLE_ISOCHANCNTL0;
+
+        struct {
+           __IO uint32_t  rw_ble_isochancntl0 : 32;
+          } RW_BLE_ISOCHANCNTL0_b;
+        };
+        /* Address 0x134 */
+        union {
+           __IO uint32_t RW_BLE_ISOMUTECNTL0;
+
+        struct {
+           __IO uint32_t  rw_ble_isomutecntl0 : 32;
+          } RW_BLE_ISOMUTECNTL0_b;
+        };
+        /* Address 0x138 */
+        union {
+           __IO uint32_t RW_BLE_ISOCURRENTTXPTR0;
+
+        struct {
+           __IO uint32_t  rw_ble_isocurrenttxptr0 : 32;
+          } RW_BLE_ISOCURRENTTXPTR0_b;
+        };
+        /* Address 0x13C */
+        union {
+           __IO uint32_t RW_BLE_ISOCURRENTRXPTR0;
+
+        struct {
+           __IO uint32_t  rw_ble_isocurrentrxptr0 : 32;
+          } RW_BLE_ISOCURRENTRXPTR0_b;
+        };
+        /* Address 0x140 */
+        union {
+           __IO uint32_t RW_BLE_ISOTRCNL0;
+
+        struct {
+           __IO uint32_t  rw_ble_isotrcnl0 : 32;
+          } RW_BLE_ISOTRCNL0_b;
+        };
+        /* Address 0x144 */
+        union {
+           __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL0;
+
+        struct {
+           __IO uint32_t  rw_ble_isoevtcntloffsetl0 : 32;
+          } RW_BLE_ISOEVTCNTLOFFSETL0_b;
+        };
+        /* Address 0x148 */
+        union {
+           __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU0;
+
+        struct {
+           __IO uint32_t  rw_ble_isoevtcntloffsetu0 : 32;
+          } RW_BLE_ISOEVTCNTLOFFSETU0_b;
+        };
+        /* Address 0x14C */
+        __O  uint32_t  RESERVED14C[1];
+        /* Address 0x150 */
+        union {
+           __IO uint32_t RW_BLE_ISOCHANCNTL1;
+
+        struct {
+           __IO uint32_t  rw_ble_isochancntl1 : 32;
+          } RW_BLE_ISOCHANCNTL1_b;
+        };
+        /* Address 0x154 */
+        union {
+           __IO uint32_t RW_BLE_ISOMUTECNTL1;
+
+        struct {
+           __IO uint32_t  rw_ble_isomutecntl1 : 32;
+          } RW_BLE_ISOMUTECNTL1_b;
+        };
+        /* Address 0x158 */
+        union {
+           __IO uint32_t RW_BLE_ISOCURRENTTXPTR1;
+
+        struct {
+           __IO uint32_t  rw_ble_isocurrenttxptr1 : 32;
+          } RW_BLE_ISOCURRENTTXPTR1_b;
+        };
+        /* Address 0x15C */
+        union {
+           __IO uint32_t RW_BLE_ISOCURRENTRXPTR1;
+
+        struct {
+           __IO uint32_t  rw_ble_isocurrentrxptr1 : 32;
+          } RW_BLE_ISOCURRENTRXPTR1_b;
+        };
+        /* Address 0x160 */
+        union {
+           __IO uint32_t RW_BLE_ISOTRCNL1;
+
+        struct {
+           __IO uint32_t  rw_ble_isotrcnl1 : 32;
+          } RW_BLE_ISOTRCNL1_b;
+        };
+        /* Address 0x164 */
+        union {
+           __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL1;
+
+        struct {
+           __IO uint32_t  rw_ble_isoevtcntloffsetl1 : 32;
+          } RW_BLE_ISOEVTCNTLOFFSETL1_b;
+        };
+        /* Address 0x168 */
+        union {
+           __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU1;
+
+        struct {
+           __IO uint32_t  rw_ble_isoevtcntloffsetu1 : 32;
+          } RW_BLE_ISOEVTCNTLOFFSETU1_b;
+        };
+        /* Address 0x16C */
+        __O  uint32_t  RESERVED16C[1];
+        /* Address 0x170 */
+        union {
+           __IO uint32_t RW_BLE_ISOCHANCNTL2;
+
+        struct {
+           __IO uint32_t  rw_ble_isochancntl2 : 32;
+          } RW_BLE_ISOCHANCNTL2_b;
+        };
+        /* Address 0x174 */
+        union {
+           __IO uint32_t RW_BLE_ISOMUTECNTL2;
+
+        struct {
+           __IO uint32_t  rw_ble_isomutecntl2 : 32;
+          } RW_BLE_ISOMUTECNTL2_b;
+        };
+        /* Address 0x178 */
+        union {
+           __IO uint32_t RW_BLE_ISOCURRENTTXPTR2;
+
+        struct {
+           __IO uint32_t  rw_ble_isocurrenttxptr2 : 32;
+          } RW_BLE_ISOCURRENTTXPTR2_b;
+        };
+        /* Address 0x17C */
+        union {
+           __IO uint32_t RW_BLE_ISOCURRENTRXPTR2;
+
+        struct {
+           __IO uint32_t  rw_ble_isocurrentrxptr2 : 32;
+          } RW_BLE_ISOCURRENTRXPTR2_b;
+        };
+        /* Address 0x180 */
+        union {
+           __IO uint32_t RW_BLE_ISOTRCNL2;
+
+        struct {
+           __IO uint32_t  rw_ble_isotrcnl2 : 32;
+          } RW_BLE_ISOTRCNL2_b;
+        };
+        /* Address 0x184 */
+        union {
+           __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL2;
+
+        struct {
+           __IO uint32_t  rw_ble_isoevtcntloffsetl2 : 32;
+          } RW_BLE_ISOEVTCNTLOFFSETL2_b;
+        };
+        /* Address 0x188 */
+        union {
+           __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU2;
+
+        struct {
+           __IO uint32_t  rw_ble_isoevtcntloffsetu2 : 32;
+          } RW_BLE_ISOEVTCNTLOFFSETU2_b;
+        };
+        /* Address 0x18C */
+        __O  uint32_t  RESERVED18C[1];
+        /* Address 0x190 */
+        union {
+           __IO uint32_t RW_BLE_BLEPRIOSCHARB;
+
+        struct {
+           __IO uint32_t  rw_ble_bleprioscharb : 32;
+          } RW_BLE_BLEPRIOSCHARB_b;
+        };
+        /* Addresses 0x194 - 0xFF0 */
+        __O  uint32_t  RESERVED194[920];
+    } BLE_LINK_IF_Type;
+
+  #define BLELNK_RW_BLE_RWBLECNTL_RW_BLE_RWBLECNTL_Pos 0
+  #define BLELNK_RW_BLE_RWBLECNTL_RW_BLE_RWBLECNTL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_VERSION_RW_BLE_VERSION_Pos 0
+  #define BLELNK_RW_BLE_VERSION_RW_BLE_VERSION_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RWBLECONF_RW_BLE_RWBLECONF_Pos 0
+  #define BLELNK_RW_BLE_RWBLECONF_RW_BLE_RWBLECONF_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_INTCNTL_RW_BLE_INTCNTL_Pos 0
+  #define BLELNK_RW_BLE_INTCNTL_RW_BLE_INTCNTL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_INTSTAT_RW_BLE_INTSTAT_Pos 0
+  #define BLELNK_RW_BLE_INTSTAT_RW_BLE_INTSTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_INTRAWSTAT_RW_BLE_INTRAWSTAT_Pos 0
+  #define BLELNK_RW_BLE_INTRAWSTAT_RW_BLE_INTRAWSTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_INTACK_RW_BLE_INTACK_Pos 0
+  #define BLELNK_RW_BLE_INTACK_RW_BLE_INTACK_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_BASETIMECNT_RW_BLE_BASETIMECNT_Pos 0
+  #define BLELNK_RW_BLE_BASETIMECNT_RW_BLE_BASETIMECNT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_FINETIMECNT_RW_BLE_FINETIMECNT_Pos 0
+  #define BLELNK_RW_BLE_FINETIMECNT_RW_BLE_FINETIMECNT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_BDADDRL_RW_BLE_BDADDRL_Pos 0
+  #define BLELNK_RW_BLE_BDADDRL_RW_BLE_BDADDRL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_BDADDRU_RW_BLE_BDADDRU_Pos 0
+  #define BLELNK_RW_BLE_BDADDRU_RW_BLE_BDADDRU_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ET_CURRENTRXDESCPTR_RW_BLE_ET_CURRENTRXDESCPTR_Pos 0
+  #define BLELNK_RW_BLE_ET_CURRENTRXDESCPTR_RW_BLE_ET_CURRENTRXDESCPTR_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_DEEPSLCNTL_RW_BLE_DEEPSLCNTL_Pos 0
+  #define BLELNK_RW_BLE_DEEPSLCNTL_RW_BLE_DEEPSLCNTL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_DEEPSLWKUP_RW_BLE_DEEPSLWKUP_Pos 0
+  #define BLELNK_RW_BLE_DEEPSLWKUP_RW_BLE_DEEPSLWKUP_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_DEEPSLSTAT_RW_BLE_DEEPSLSTAT_Pos 0
+  #define BLELNK_RW_BLE_DEEPSLSTAT_RW_BLE_DEEPSLSTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ENBPRESET_RW_BLE_ENBPRESET_Pos 0
+  #define BLELNK_RW_BLE_ENBPRESET_RW_BLE_ENBPRESET_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_FINECNTCORR_RW_BLE_FINECNTCORR_Pos 0
+  #define BLELNK_RW_BLE_FINECNTCORR_RW_BLE_FINECNTCORR_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_BASETIMECNTCORR_RW_BLE_BASETIMECNTCORR_Pos 0
+  #define BLELNK_RW_BLE_BASETIMECNTCORR_RW_BLE_BASETIMECNTCORR_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_DIAGCNTL_RW_BLE_DIAGCNTL_Pos 0
+  #define BLELNK_RW_BLE_DIAGCNTL_RW_BLE_DIAGCNTL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_DIAGSTAT_RW_BLE_DIAGSTAT_Pos 0
+  #define BLELNK_RW_BLE_DIAGSTAT_RW_BLE_DIAGSTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_DEBUGADDMAX_RW_BLE_DEBUGADDMAX_Pos 0
+  #define BLELNK_RW_BLE_DEBUGADDMAX_RW_BLE_DEBUGADDMAX_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_DEBUGADDMIN_RW_BLE_DEBUGADDMIN_Pos 0
+  #define BLELNK_RW_BLE_DEBUGADDMIN_RW_BLE_DEBUGADDMIN_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ERRORTYPESTAT_RW_BLE_ERRORTYPESTAT_Pos 0
+  #define BLELNK_RW_BLE_ERRORTYPESTAT_RW_BLE_ERRORTYPESTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_SWPROFILING_RW_BLE_SWPROFILING_Pos 0
+  #define BLELNK_RW_BLE_SWPROFILING_RW_BLE_SWPROFILING_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RADIOCNTL0_RW_BLE_RADIOCNTL0_Pos 0
+  #define BLELNK_RW_BLE_RADIOCNTL0_RW_BLE_RADIOCNTL0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RADIOCNTL1_RW_BLE_RADIOCNTL1_Pos 0
+  #define BLELNK_RW_BLE_RADIOCNTL1_RW_BLE_RADIOCNTL1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RADIOCNTL2_RW_BLE_RADIOCNTL2_Pos 0
+  #define BLELNK_RW_BLE_RADIOCNTL2_RW_BLE_RADIOCNTL2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RADIOCNTL3_RW_BLE_RADIOCNTL3_Pos 0
+  #define BLELNK_RW_BLE_RADIOCNTL3_RW_BLE_RADIOCNTL3_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RADIOPWRUPDN_RW_BLE_RADIOPWRUPDN_Pos 0
+  #define BLELNK_RW_BLE_RADIOPWRUPDN_RW_BLE_RADIOPWRUPDN_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_SPIPTRCNTL0_RW_BLE_SPIPTRCNTL0_Pos 0
+  #define BLELNK_RW_BLE_SPIPTRCNTL0_RW_BLE_SPIPTRCNTL0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_SPIPTRCNTL1_RW_BLE_SPIPTRCNTL1_Pos 0
+  #define BLELNK_RW_BLE_SPIPTRCNTL1_RW_BLE_SPIPTRCNTL1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_SPIPTRCNTL2_RW_BLE_SPIPTRCNTL2_Pos 0
+  #define BLELNK_RW_BLE_SPIPTRCNTL2_RW_BLE_SPIPTRCNTL2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ADVCHMAP_RW_BLE_ADVCHMAP_Pos 0
+  #define BLELNK_RW_BLE_ADVCHMAP_RW_BLE_ADVCHMAP_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ADVTIM_RW_BLE_ADVTIM_Pos 0
+  #define BLELNK_RW_BLE_ADVTIM_RW_BLE_ADVTIM_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ACTSCANSTAT_RW_BLE_ACTSCANSTAT_Pos 0
+  #define BLELNK_RW_BLE_ACTSCANSTAT_RW_BLE_ACTSCANSTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_WLPUBADDPTR_RW_BLE_WLPUBADDPTR_Pos 0
+  #define BLELNK_RW_BLE_WLPUBADDPTR_RW_BLE_WLPUBADDPTR_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_WLPRIVADDPTR_RW_BLE_WLPRIVADDPTR_Pos 0
+  #define BLELNK_RW_BLE_WLPRIVADDPTR_RW_BLE_WLPRIVADDPTR_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_WLNBDEV_RW_BLE_WLNBDEV_Pos 0
+  #define BLELNK_RW_BLE_WLNBDEV_RW_BLE_WLNBDEV_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_AESCNTL_RW_BLE_AESCNTL_Pos 0
+  #define BLELNK_RW_BLE_AESCNTL_RW_BLE_AESCNTL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_AESKEY31_0_RW_BLE_AESKEY31_0_Pos 0
+  #define BLELNK_RW_BLE_AESKEY31_0_RW_BLE_AESKEY31_0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_AESKEY63_32_RW_BLE_AESKEY63_32_Pos 0
+  #define BLELNK_RW_BLE_AESKEY63_32_RW_BLE_AESKEY63_32_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_AESKEY95_64_RW_BLE_AESKEY95_64_Pos 0
+  #define BLELNK_RW_BLE_AESKEY95_64_RW_BLE_AESKEY95_64_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_AESKEY127_96_RW_BLE_AESKEY127_96_Pos 0
+  #define BLELNK_RW_BLE_AESKEY127_96_RW_BLE_AESKEY127_96_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_AESPTR_RW_BLE_AESPTR_Pos 0
+  #define BLELNK_RW_BLE_AESPTR_RW_BLE_AESPTR_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_TXMICVAL_RW_BLE_TXMICVAL_Pos 0
+  #define BLELNK_RW_BLE_TXMICVAL_RW_BLE_TXMICVAL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RXMICVAL_RW_BLE_RXMICVAL_Pos 0
+  #define BLELNK_RW_BLE_RXMICVAL_RW_BLE_RXMICVAL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RFTESTCNTL_RW_BLE_RFTESTCNTL_Pos 0
+  #define BLELNK_RW_BLE_RFTESTCNTL_RW_BLE_RFTESTCNTL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RFTESTTXSTAT_RW_BLE_RFTESTTXSTAT_Pos 0
+  #define BLELNK_RW_BLE_RFTESTTXSTAT_RW_BLE_RFTESTTXSTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RFTESTRXSTAT_RW_BLE_RFTESTRXSTAT_Pos 0
+  #define BLELNK_RW_BLE_RFTESTRXSTAT_RW_BLE_RFTESTRXSTAT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_TIMGENCNTL_RW_BLE_TIMGENCNTL_Pos 0
+  #define BLELNK_RW_BLE_TIMGENCNTL_RW_BLE_TIMGENCNTL_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_GROSSTIMTGT_RW_BLE_GROSSTIMTGT_Pos 0
+  #define BLELNK_RW_BLE_GROSSTIMTGT_RW_BLE_GROSSTIMTGT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_FINETIMTGT_RW_BLE_FINETIMTGT_Pos 0
+  #define BLELNK_RW_BLE_FINETIMTGT_RW_BLE_FINETIMTGT_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_COEXIFCNTL0_RW_BLE_COEXIFCNTL0_Pos 0
+  #define BLELNK_RW_BLE_COEXIFCNTL0_RW_BLE_COEXIFCNTL0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_COEXIFCNTL1_RW_BLE_COEXIFCNTL1_Pos 0
+  #define BLELNK_RW_BLE_COEXIFCNTL1_RW_BLE_COEXIFCNTL1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_COEXIFCNTL2_RW_BLE_COEXIFCNTL2_Pos 0
+  #define BLELNK_RW_BLE_COEXIFCNTL2_RW_BLE_COEXIFCNTL2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_BLEMPRIO0_RW_BLE_BLEMPRIO0_Pos 0
+  #define BLELNK_RW_BLE_BLEMPRIO0_RW_BLE_BLEMPRIO0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_BLEMPRIO1_RW_BLE_BLEMPRIO1_Pos 0
+  #define BLELNK_RW_BLE_BLEMPRIO1_RW_BLE_BLEMPRIO1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RALPTR_RW_BLE_RALPTR_Pos 0
+  #define BLELNK_RW_BLE_RALPTR_RW_BLE_RALPTR_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RALNBDEV_RW_BLE_RALNBDEV_Pos 0
+  #define BLELNK_RW_BLE_RALNBDEV_RW_BLE_RALNBDEV_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RAL_LOCAL_RND_RW_BLE_RAL_LOCAL_RND_Pos 0
+  #define BLELNK_RW_BLE_RAL_LOCAL_RND_RW_BLE_RAL_LOCAL_RND_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_RAL_PEER_RND_RW_BLE_RAL_PEER_RND_Pos 0
+  #define BLELNK_RW_BLE_RAL_PEER_RND_RW_BLE_RAL_PEER_RND_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCHANCNTL0_RW_BLE_ISOCHANCNTL0_Pos 0
+  #define BLELNK_RW_BLE_ISOCHANCNTL0_RW_BLE_ISOCHANCNTL0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOMUTECNTL0_RW_BLE_ISOMUTECNTL0_Pos 0
+  #define BLELNK_RW_BLE_ISOMUTECNTL0_RW_BLE_ISOMUTECNTL0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCURRENTTXPTR0_RW_BLE_ISOCURRENTTXPTR0_Pos 0
+  #define BLELNK_RW_BLE_ISOCURRENTTXPTR0_RW_BLE_ISOCURRENTTXPTR0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCURRENTRXPTR0_RW_BLE_ISOCURRENTRXPTR0_Pos 0
+  #define BLELNK_RW_BLE_ISOCURRENTRXPTR0_RW_BLE_ISOCURRENTRXPTR0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOTRCNL0_RW_BLE_ISOTRCNL0_Pos 0
+  #define BLELNK_RW_BLE_ISOTRCNL0_RW_BLE_ISOTRCNL0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL0_RW_BLE_ISOEVTCNTLOFFSETL0_Pos 0
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL0_RW_BLE_ISOEVTCNTLOFFSETL0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU0_RW_BLE_ISOEVTCNTLOFFSETU0_Pos 0
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU0_RW_BLE_ISOEVTCNTLOFFSETU0_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCHANCNTL1_RW_BLE_ISOCHANCNTL1_Pos 0
+  #define BLELNK_RW_BLE_ISOCHANCNTL1_RW_BLE_ISOCHANCNTL1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOMUTECNTL1_RW_BLE_ISOMUTECNTL1_Pos 0
+  #define BLELNK_RW_BLE_ISOMUTECNTL1_RW_BLE_ISOMUTECNTL1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCURRENTTXPTR1_RW_BLE_ISOCURRENTTXPTR1_Pos 0
+  #define BLELNK_RW_BLE_ISOCURRENTTXPTR1_RW_BLE_ISOCURRENTTXPTR1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCURRENTRXPTR1_RW_BLE_ISOCURRENTRXPTR1_Pos 0
+  #define BLELNK_RW_BLE_ISOCURRENTRXPTR1_RW_BLE_ISOCURRENTRXPTR1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOTRCNL1_RW_BLE_ISOTRCNL1_Pos 0
+  #define BLELNK_RW_BLE_ISOTRCNL1_RW_BLE_ISOTRCNL1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL1_RW_BLE_ISOEVTCNTLOFFSETL1_Pos 0
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL1_RW_BLE_ISOEVTCNTLOFFSETL1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU1_RW_BLE_ISOEVTCNTLOFFSETU1_Pos 0
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU1_RW_BLE_ISOEVTCNTLOFFSETU1_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCHANCNTL2_RW_BLE_ISOCHANCNTL2_Pos 0
+  #define BLELNK_RW_BLE_ISOCHANCNTL2_RW_BLE_ISOCHANCNTL2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOMUTECNTL2_RW_BLE_ISOMUTECNTL2_Pos 0
+  #define BLELNK_RW_BLE_ISOMUTECNTL2_RW_BLE_ISOMUTECNTL2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCURRENTTXPTR2_RW_BLE_ISOCURRENTTXPTR2_Pos 0
+  #define BLELNK_RW_BLE_ISOCURRENTTXPTR2_RW_BLE_ISOCURRENTTXPTR2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOCURRENTRXPTR2_RW_BLE_ISOCURRENTRXPTR2_Pos 0
+  #define BLELNK_RW_BLE_ISOCURRENTRXPTR2_RW_BLE_ISOCURRENTRXPTR2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOTRCNL2_RW_BLE_ISOTRCNL2_Pos 0
+  #define BLELNK_RW_BLE_ISOTRCNL2_RW_BLE_ISOTRCNL2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL2_RW_BLE_ISOEVTCNTLOFFSETL2_Pos 0
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL2_RW_BLE_ISOEVTCNTLOFFSETL2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU2_RW_BLE_ISOEVTCNTLOFFSETU2_Pos 0
+  #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU2_RW_BLE_ISOEVTCNTLOFFSETU2_Msk 0x0ffffffffUL
+  #define BLELNK_RW_BLE_BLEPRIOSCHARB_RW_BLE_BLEPRIOSCHARB_Pos 0
+  #define BLELNK_RW_BLE_BLEPRIOSCHARB_RW_BLE_BLEPRIOSCHARB_Msk 0x0ffffffffUL
+
+#endif // __BLE_LINK_IF_H__

third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_mac.h

@@ -0,0 +1,930 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef __ZB_MAC_IF_H__
+#define __ZB_MAC_IF_H__
+
+  typedef  struct {
+        /* Address 0x000 */
+        union {
+           __IO uint32_t SCMR0;
+
+        struct {
+           __IO uint32_t  scmr0 : 32;
+          } SCMR0_b;
+        };
+        /* Address 0x004 */
+        union {
+           __IO uint32_t SCMR1;
+
+        struct {
+           __IO uint32_t  scmr1 : 32;
+          } SCMR1_b;
+        };
+        /* Address 0x008 */
+        union {
+           __IO uint32_t SCMR2;
+
+        struct {
+           __IO uint32_t  scmr2 : 32;
+          } SCMR2_b;
+        };
+        /* Address 0x00C */
+        union {
+           __IO uint32_t SCMR3;
+
+        struct {
+           __IO uint32_t  scmr3 : 32;
+          } SCMR3_b;
+        };
+        /* Address 0x010 */
+        union {
+           __IO uint32_t SCTR0;
+
+        struct {
+           __IO uint32_t  sctr0 : 32;
+          } SCTR0_b;
+        };
+        /* Address 0x014 */
+        union {
+           __IO uint32_t SCTR1;
+
+        struct {
+           __IO uint32_t  sctr1 : 32;
+          } SCTR1_b;
+        };
+        /* Addresses 0x018 - 0x01C */
+        __O  uint32_t  RESERVED018[2];
+        /* Address 0x020 */
+        union {
+           __IO uint32_t SCTCR;
+
+        struct {
+           __IO uint32_t  sctcr : 2;
+           __IO uint32_t  reserved2 : 30;
+          } SCTCR_b;
+        };
+        /* Address 0x024 */
+        union {
+           __IO uint32_t SCFRC;
+
+        struct {
+           __IO uint32_t  scfrc : 32;
+          } SCFRC_b;
+        };
+        /* Address 0x028 */
+        union {
+           __I  uint32_t SCSSR;
+
+        struct {
+           __I  uint32_t  scssr : 32;
+          } SCSSR_b;
+        };
+        /* Address 0x02C */
+        union {
+           __IO uint32_t SCESL;
+
+        struct {
+           __IO uint32_t  scesl : 32;
+          } SCESL_b;
+        };
+        /* Address 0x030 */
+        union {
+           __IO uint32_t RXETST;
+
+        struct {
+           __IO uint32_t  rxetst : 32;
+          } RXETST_b;
+        };
+        /* Address 0x034 */
+        union {
+           __I  uint32_t RXTSTP;
+
+        struct {
+           __I  uint32_t  rxtstp : 32;
+          } RXTSTP_b;
+        };
+        /* Address 0x038 */
+        union {
+           __IO uint32_t TXTSTP;
+
+        struct {
+           __IO uint32_t  txtstp : 32;
+          } TXTSTP_b;
+        };
+        /* Address 0x03C */
+        union {
+           __IO uint32_t IER;
+
+        struct {
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __IO uint32_t  ier : 10;
+           __IO uint32_t  reserved10 : 22;
+#else
+           __IO uint32_t  ier : 12;
+           __IO uint32_t  reserved12 : 20;
+#endif
+          } IER_b;
+        };
+        /* Address 0x040 */
+        union {
+           __IO uint32_t ISR;
+
+        struct {
+           __IO uint32_t  txint : 1;
+           __IO uint32_t  headerrxint : 1;
+           __IO uint32_t  rxint : 1;
+           __IO uint32_t  unused_3_3 : 1;
+           __IO uint32_t  match : 4;
+           __IO uint32_t  timeout : 2;
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __IO uint32_t  reserved10 : 22;
+#else
+           __IO uint32_t  rxaddnomatch : 1;
+           __IO uint32_t  rxaddmatch : 1;
+           __IO uint32_t  reserved12 : 20;
+#endif
+          } ISR_b;
+        };
+        /* Address 0x044 */
+        union {
+           __IO uint32_t SCTL;
+
+        struct {
+           __IO uint32_t  sctl : 7;
+           __IO uint32_t  reserved7 : 25;
+          } SCTL_b;
+        };
+        /* Address 0x048 */
+        union {
+           __IO uint32_t PHYTXTUNETIME;
+
+        struct {
+           __IO uint32_t  phytxtunetime : 8;
+           __IO uint32_t  phyrx2txtime : 8;
+           __IO uint32_t  reserved16 : 16;
+          } PHYTXTUNETIME_b;
+        };
+        /* Address 0x04C */
+        union {
+           __IO uint32_t PHYRXTUNETIME;
+
+        struct {
+           __IO uint32_t  phyrxtunetime : 8;
+           __IO uint32_t  reserved8 : 24;
+          } PHYRXTUNETIME_b;
+        };
+        /* Address 0x050 */
+        __O  uint32_t  RESERVED050[1];
+        /* Address 0x054 */
+        union {
+           __IO uint32_t TURNAROUNDTIME;
+
+        struct {
+           __IO uint32_t  turnaroundtime : 8;
+           __IO uint32_t  reserved8 : 24;
+          } TURNAROUNDTIME_b;
+        };
+        /* Address 0x058 */
+        union {
+           __IO uint32_t BACKOFFTIME;
+
+        struct {
+           __IO uint32_t  backofftime : 8;
+           __IO uint32_t  reserved8 : 24;
+          } BACKOFFTIME_b;
+        };
+        /* Addresses 0x05C - 0x06C */
+        __O  uint32_t  RESERVED05C[5];
+        /* Address 0x070 */
+        union {
+           __IO uint32_t PRBS_SEED;
+
+        struct {
+           __IO uint32_t  prbs_seed : 15;
+           __IO uint32_t  reserved15 : 17;
+          } PRBS_SEED_b;
+        };
+        /* Addresses 0x074 - 0x078 */
+        __O  uint32_t  RESERVED074[2];
+        /* Address 0x07C */
+        union {
+           __IO uint32_t SM_STATE;
+
+        struct {
+           __IO uint32_t  sm_state : 7;
+           __IO uint32_t  reserved7 : 25;
+          } SM_STATE_b;
+        };
+        /* Address 0x080 */
+        union {
+           __IO uint32_t LIFSTURNAROUNDTIME;
+
+        struct {
+           __IO uint32_t  lifsturnaroundtime : 8;
+           __IO uint32_t  reserved8 : 24;
+          } LIFSTURNAROUNDTIME_b;
+        };
+        /* Address 0x084 */
+        union {
+           __IO uint32_t HDR_CTRL;
+
+        struct {
+           __IO uint32_t  hdr_ctrl : 2;
+           __IO uint32_t  reserved2 : 30;
+          } HDR_CTRL_b;
+        };
+        /* Address 0x088 */
+        union {
+           __IO uint32_t MISR;
+
+        struct {
+           __IO uint32_t  misr : 10;
+           __IO uint32_t  reserved10 : 22;
+          } MISR_b;
+        };
+        /* Addresses 0x08C - 0x0F8 */
+        __O  uint32_t  RESERVED08C[28];
+        /* Address 0x0FC */
+        union {
+           __I  uint32_t IDENTIFIER;
+
+        struct {
+           __I  uint32_t  identifier : 32;
+          } IDENTIFIER_b;
+        };
+        /* Addresses 0x100 - 0x1BC */
+        __O  uint32_t  RESERVED100[48];
+        /* Address 0x1C0 */
+        union {
+           __IO uint32_t TXCTL;
+
+        struct {
+           __IO uint32_t  sch : 1;
+           __IO uint32_t  ss : 1;
+           __IO uint32_t  slotack : 1;
+           __IO uint32_t  aa : 1;
+           __IO uint32_t  mode : 2;
+           __IO uint32_t  reserved6 : 26;
+          } TXCTL_b;
+        };
+        /* Address 0x1C4 */
+        union {
+           __I  uint32_t TXSTAT;
+
+        struct {
+           __I  uint32_t  txstat : 5;
+           __I  uint32_t  txto : 1;
+           __I  uint32_t  txpcto : 1;
+           __I  uint32_t  reserved7 : 25;
+          } TXSTAT_b;
+        };
+        /* Address 0x1C8 */
+        union {
+           __IO uint32_t TXMBEBT;
+
+        struct {
+           __IO uint32_t  minbe : 4;
+           __IO uint32_t  maxbo : 3;
+           __IO uint32_t  ble : 1;
+           __IO uint32_t  maxbe : 4;
+           __IO uint32_t  frcdly : 1;
+           __IO uint32_t  hide : 4;
+           __IO uint32_t  reserved17 : 15;
+          } TXMBEBT_b;
+        };
+        /* Address 0x1CC */
+        union {
+           __IO uint32_t TXCSMAC;
+
+        struct {
+           __IO uint32_t  txcsmac : 18;
+           __IO uint32_t  reserved18 : 14;
+          } TXCSMAC_b;
+        };
+        /* Address 0x1D0 */
+        union {
+           __IO uint32_t TXTRIES;
+
+        struct {
+           __IO uint32_t  txtries : 4;
+           __IO uint32_t  reserved4 : 28;
+          } TXTRIES_b;
+        };
+        /* Address 0x1D4 */
+        union {
+           __IO uint32_t TXPEND;
+
+        struct {
+           __IO uint32_t  txpend : 1;
+           __IO uint32_t  reserved1 : 31;
+          } TXPEND_b;
+        };
+        /* Address 0x1D8 */
+        union {
+           __IO uint32_t TXASC;
+
+        struct {
+           __IO uint32_t  txasc : 1;
+           __IO uint32_t  reserved1 : 31;
+          } TXASC_b;
+        };
+        /* Address 0x1DC */
+        union {
+           __IO uint32_t TXBUFAD;
+
+        struct {
+           __IO uint32_t  txbufad : 32;
+          } TXBUFAD_b;
+        };
+        /* Address 0x1E0 */
+        union {
+           __IO uint32_t TXTO;
+
+        struct {
+           __IO uint32_t  tx_to_len : 7;
+           __IO uint32_t  tx_to_ena : 1;
+           __IO uint32_t  tx_topc_ena : 1;
+           __IO uint32_t  reserved9 : 23;
+          } TXTO_b;
+        };
+        /* Addresses 0x1E4 - 0x2BC */
+        __O  uint32_t  RESERVED1E4[55];
+        /* Address 0x2C0 */
+        union {
+           __IO uint32_t RXCTL;
+
+        struct {
+           __IO uint32_t  rxctl : 5;
+           __IO uint32_t  reserved5 : 27;
+          } RXCTL_b;
+        };
+        /* Address 0x2C4 */
+        union {
+           __I  uint32_t RXSTAT;
+
+        struct {
+           __I  uint32_t  fcs_error : 1;
+           __I  uint32_t  abort : 1;
+           __I  uint32_t  unused_2_2 : 1;
+           __I  uint32_t  unused_3_3 : 1;
+           __I  uint32_t  mod_in_packet : 1;
+           __I  uint32_t  malformed : 1;
+           __I  uint32_t  reserved6 : 26;
+          } RXSTAT_b;
+        };
+        /* Address 0x2C8 */
+        union {
+           __IO uint32_t RXMPID;
+
+        struct {
+           __IO uint32_t  rxmpid : 18;
+           __IO uint32_t  reserved18 : 14;
+          } RXMPID_b;
+        };
+        /* Address 0x2CC */
+        union {
+           __IO uint32_t RXMSAD;
+
+        struct {
+           __IO uint32_t  rxmsad : 16;
+           __IO uint32_t  reserved16 : 16;
+          } RXMSAD_b;
+        };
+        /* Address 0x2D0 */
+        union {
+           __IO uint32_t RXMEADL;
+
+        struct {
+           __IO uint32_t  rxmeadl : 32;
+          } RXMEADL_b;
+        };
+        /* Address 0x2D4 */
+        union {
+           __IO uint32_t RXMEADH;
+
+        struct {
+           __IO uint32_t  rxmeadh : 32;
+          } RXMEADH_b;
+        };
+        /* Address 0x2D8 */
+        __O  uint32_t  RESERVED2D8[1];
+        /* Address 0x2DC */
+        union {
+           __IO uint32_t RXBUFAD;
+
+        struct {
+           __IO uint32_t  rxbufad : 32;
+          } RXBUFAD_b;
+        };
+        /* Address 0x2E0 */
+        union {
+           __IO uint32_t RXPROM;
+
+        struct {
+           __IO uint32_t  rxprom : 2;
+           __IO uint32_t  reserved2 : 30;
+          } RXPROM_b;
+        };
+        /* Address 0x2E4 */
+        union {
+           __IO uint32_t RXMPID_SEC;
+
+        struct {
+           __IO uint32_t  rxmpid_sec : 19;
+           __IO uint32_t  reserved19 : 13;
+          } RXMPID_SEC_b;
+        };
+        /* Address 0x2E8 */
+        union {
+           __IO uint32_t RXMSAD_SEC;
+
+        struct {
+           __IO uint32_t  rxmsad_sec : 16;
+           __IO uint32_t  reserved16 : 16;
+          } RXMSAD_SEC_b;
+        };
+        /* Address 0x2EC */
+        union {
+           __IO uint32_t RXMEADL_SEC;
+
+        struct {
+           __IO uint32_t  rxmeadl_sec : 32;
+          } RXMEADL_SEC_b;
+        };
+        /* Address 0x2F0 */
+        union {
+           __IO uint32_t RXMEADH_SEC;
+
+        struct {
+           __IO uint32_t  rxmeadh_sec : 32;
+          } RXMEADH_SEC_b;
+        };
+        /* Addresses 0x2F4 - 0x2FC */
+        __O  uint32_t  RESERVED2F4[3];
+        /* Address 0x300 */
+        union {
+           __IO uint32_t DMA_ADDR;
+
+        struct {
+           __IO uint32_t  dma_addr : 32;
+          } DMA_ADDR_b;
+        };
+        /* Address 0x304 */
+        union {
+           __I  uint32_t DMA_RD_DATA;
+
+        struct {
+           __I  uint32_t  dma_rd_data : 32;
+          } DMA_RD_DATA_b;
+        };
+        /* Address 0x308 */
+        union {
+           __IO uint32_t DMA_WR_DATA;
+
+        struct {
+           __IO uint32_t  dma_wr_data : 32;
+          } DMA_WR_DATA_b;
+        };
+        /* Address 0x30C */
+        union {
+           __IO uint32_t DMA_ADDR_OFFSET;
+
+        struct {
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __IO uint32_t  reserved0 : 15;
+           __IO uint32_t  dma_addr_offset : 17;
+#else
+           __IO uint32_t  reserved0 : 17;
+           __IO uint32_t  dma_addr_offset : 15;
+#endif
+          } DMA_ADDR_OFFSET_b;
+        };
+        /* Addresses 0x310 - 0x3FC */
+        __O  uint32_t  RESERVED310[60];
+        /* Address 0x400 */
+        union {
+           __IO uint32_t DMA_FROM_ADC;
+
+        struct {
+           __IO uint32_t  activate : 1;
+           __IO uint32_t  mode : 4;
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __IO uint32_t  reserved5 : 27;
+#else
+           __IO uint32_t  safe : 1;
+           __IO uint32_t  reserved6 : 26;
+#endif
+          } DMA_FROM_ADC_b;
+        };
+        /* Address 0x404 */
+        union {
+           __IO uint32_t PHY_MCTRL;
+
+        struct {
+           __IO uint32_t  bbc_rmi_req : 1;
+           __IO uint32_t  reserved1 : 31;
+          } PHY_MCTRL_b;
+        };
+        /* Address 0x408 */
+        union {
+           __I  uint32_t PHY_MSTATUS;
+
+        struct {
+           __I  uint32_t  bbc_rmi_ack : 1;
+           __I  uint32_t  reserved1 : 31;
+          } PHY_MSTATUS_b;
+        };
+        /* Addresses 0x40C - 0xFF0 */
+        __O  uint32_t  RESERVED40C[762];
+        /* Address 0xFF4 */
+        union {
+           __IO uint32_t POWERDOWN;
+
+        struct {
+           __IO uint32_t  soft_reset : 1;
+           __IO uint32_t  force_softreset : 1;
+           __IO uint32_t  enable_flags_with_core_bus : 1;
+           __IO uint32_t  reserved3 : 28;
+           __IO uint32_t  powerdown : 1;
+          } POWERDOWN_b;
+        };
+        /* Address 0xFF8 */
+        __O  uint32_t  RESERVEDFF8[1];
+        /* Address 0xFFC */
+        union {
+           __I  uint32_t MODULEID;
+
+        struct {
+           __I  uint32_t  aperture : 8;
+           __I  uint32_t  minor_revision : 4;
+           __I  uint32_t  major_revision : 4;
+           __I  uint32_t  identifier : 16;
+          } MODULEID_b;
+        };
+    } ZB_MAC_IF_Type;
+
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+  #define ZBMAC_SCMR0_SCMR0_Pos 0
+  #define ZBMAC_SCMR0_SCMR0_Msk 0x0ffffffffUL
+  #define ZBMAC_SCMR1_SCMR1_Pos 0
+  #define ZBMAC_SCMR1_SCMR1_Msk 0x0ffffffffUL
+  #define ZBMAC_SCMR2_SCMR2_Pos 0
+  #define ZBMAC_SCMR2_SCMR2_Msk 0x0ffffffffUL
+  #define ZBMAC_SCMR3_SCMR3_Pos 0
+  #define ZBMAC_SCMR3_SCMR3_Msk 0x0ffffffffUL
+  #define ZBMAC_SCTR0_SCTR0_Pos 0
+  #define ZBMAC_SCTR0_SCTR0_Msk 0x0ffffffffUL
+  #define ZBMAC_SCTR1_SCTR1_Pos 0
+  #define ZBMAC_SCTR1_SCTR1_Msk 0x0ffffffffUL
+  #define ZBMAC_SCTCR_SCTCR_Pos 0
+  #define ZBMAC_SCTCR_SCTCR_Msk 0x03UL
+  #define ZBMAC_SCFRC_SCFRC_Pos 0
+  #define ZBMAC_SCFRC_SCFRC_Msk 0x0ffffffffUL
+  #define ZBMAC_SCSSR_SCSSR_Pos 0
+  #define ZBMAC_SCSSR_SCSSR_Msk 0x0ffffffffUL
+  #define ZBMAC_SCESL_SCESL_Pos 0
+  #define ZBMAC_SCESL_SCESL_Msk 0x0ffffffffUL
+  #define ZBMAC_RXETST_RXETST_Pos 0
+  #define ZBMAC_RXETST_RXETST_Msk 0x0ffffffffUL
+  #define ZBMAC_RXTSTP_RXTSTP_Pos 0
+  #define ZBMAC_RXTSTP_RXTSTP_Msk 0x0ffffffffUL
+  #define ZBMAC_TXTSTP_TXTSTP_Pos 0
+  #define ZBMAC_TXTSTP_TXTSTP_Msk 0x0ffffffffUL
+  #define ZBMAC_IER_IER_Pos 0
+  #define ZBMAC_IER_IER_Msk 0x03ffUL
+  #define ZBMAC_ISR_TXINT_Pos 0
+  #define ZBMAC_ISR_TXINT_Msk 0x01UL
+  #define ZBMAC_ISR_HEADERRXINT_Pos 1
+  #define ZBMAC_ISR_HEADERRXINT_Msk 0x02UL
+  #define ZBMAC_ISR_RXINT_Pos 2
+  #define ZBMAC_ISR_RXINT_Msk 0x04UL
+  #define ZBMAC_ISR_UNUSED_3_3_Pos 3
+  #define ZBMAC_ISR_UNUSED_3_3_Msk 0x08UL
+  #define ZBMAC_ISR_MATCH_Pos 4
+  #define ZBMAC_ISR_MATCH_Msk 0x0f0UL
+  #define ZBMAC_ISR_TIMEOUT_Pos 8
+  #define ZBMAC_ISR_TIMEOUT_Msk 0x0300UL
+  #define ZBMAC_SCTL_SCTL_Pos 0
+  #define ZBMAC_SCTL_SCTL_Msk 0x07fUL
+  #define ZBMAC_PHYTXTUNETIME_PHYTXTUNETIME_Pos 0
+  #define ZBMAC_PHYTXTUNETIME_PHYTXTUNETIME_Msk 0x0ffUL
+  #define ZBMAC_PHYTXTUNETIME_PHYRX2TXTIME_Pos 8
+  #define ZBMAC_PHYTXTUNETIME_PHYRX2TXTIME_Msk 0x0ff00UL
+  #define ZBMAC_PHYRXTUNETIME_PHYRXTUNETIME_Pos 0
+  #define ZBMAC_PHYRXTUNETIME_PHYRXTUNETIME_Msk 0x0ffUL
+  #define ZBMAC_TURNAROUNDTIME_TURNAROUNDTIME_Pos 0
+  #define ZBMAC_TURNAROUNDTIME_TURNAROUNDTIME_Msk 0x0ffUL
+  #define ZBMAC_BACKOFFTIME_BACKOFFTIME_Pos 0
+  #define ZBMAC_BACKOFFTIME_BACKOFFTIME_Msk 0x0ffUL
+  #define ZBMAC_PRBS_SEED_PRBS_SEED_Pos 0
+  #define ZBMAC_PRBS_SEED_PRBS_SEED_Msk 0x07fffUL
+  #define ZBMAC_SM_STATE_SM_STATE_Pos 0
+  #define ZBMAC_SM_STATE_SM_STATE_Msk 0x07fUL
+  #define ZBMAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Pos 0
+  #define ZBMAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Msk 0x0ffUL
+  #define ZBMAC_HDR_CTRL_HDR_CTRL_Pos 0
+  #define ZBMAC_HDR_CTRL_HDR_CTRL_Msk 0x03UL
+  #define ZBMAC_MISR_MISR_Pos 0
+  #define ZBMAC_MISR_MISR_Msk 0x03ffUL
+  #define ZBMAC_IDENTIFIER_IDENTIFIER_Pos 0
+  #define ZBMAC_IDENTIFIER_IDENTIFIER_Msk 0x0ffffffffUL
+  #define ZBMAC_TXCTL_SCH_Pos 0
+  #define ZBMAC_TXCTL_SCH_Msk 0x01UL
+  #define ZBMAC_TXCTL_SS_Pos 1
+  #define ZBMAC_TXCTL_SS_Msk 0x02UL
+  #define ZBMAC_TXCTL_SLOTACK_Pos 2
+  #define ZBMAC_TXCTL_SLOTACK_Msk 0x04UL
+  #define ZBMAC_TXCTL_AA_Pos 3
+  #define ZBMAC_TXCTL_AA_Msk 0x08UL
+  #define ZBMAC_TXCTL_MODE_Pos 4
+  #define ZBMAC_TXCTL_MODE_Msk 0x030UL
+  #define ZBMAC_TXSTAT_TXSTAT_Pos 0
+  #define ZBMAC_TXSTAT_TXSTAT_Msk 0x01fUL
+  #define ZBMAC_TXSTAT_TXTO_Pos 5
+  #define ZBMAC_TXSTAT_TXTO_Msk 0x020UL
+  #define ZBMAC_TXSTAT_TXPCTO_Pos 6
+  #define ZBMAC_TXSTAT_TXPCTO_Msk 0x040UL
+  #define ZBMAC_TXMBEBT_MINBE_Pos 0
+  #define ZBMAC_TXMBEBT_MINBE_Msk 0x0fUL
+  #define ZBMAC_TXMBEBT_MAXBO_Pos 4
+  #define ZBMAC_TXMBEBT_MAXBO_Msk 0x070UL
+  #define ZBMAC_TXMBEBT_BLE_Pos 7
+  #define ZBMAC_TXMBEBT_BLE_Msk 0x080UL
+  #define ZBMAC_TXMBEBT_MAXBE_Pos 8
+  #define ZBMAC_TXMBEBT_MAXBE_Msk 0x0f00UL
+  #define ZBMAC_TXMBEBT_FRCDLY_Pos 12
+  #define ZBMAC_TXMBEBT_FRCDLY_Msk 0x01000UL
+  #define ZBMAC_TXMBEBT_HIDE_Pos 13
+  #define ZBMAC_TXMBEBT_HIDE_Msk 0x01e000UL
+  #define ZBMAC_TXCSMAC_TXCSMAC_Pos 0
+  #define ZBMAC_TXCSMAC_TXCSMAC_Msk 0x03ffffUL
+  #define ZBMAC_TXTRIES_TXTRIES_Pos 0
+  #define ZBMAC_TXTRIES_TXTRIES_Msk 0x0fUL
+  #define ZBMAC_TXPEND_TXPEND_Pos 0
+  #define ZBMAC_TXPEND_TXPEND_Msk 0x01UL
+  #define ZBMAC_TXASC_TXASC_Pos 0
+  #define ZBMAC_TXASC_TXASC_Msk 0x01UL
+  #define ZBMAC_TXBUFAD_TXBUFAD_Pos 0
+  #define ZBMAC_TXBUFAD_TXBUFAD_Msk 0x0ffffffffUL
+  #define ZBMAC_TXTO_TX_TO_LEN_Pos 0
+  #define ZBMAC_TXTO_TX_TO_LEN_Msk 0x07fUL
+  #define ZBMAC_TXTO_TX_TO_ENA_Pos 7
+  #define ZBMAC_TXTO_TX_TO_ENA_Msk 0x080UL
+  #define ZBMAC_TXTO_TX_TOPC_ENA_Pos 8
+  #define ZBMAC_TXTO_TX_TOPC_ENA_Msk 0x0100UL
+  #define ZBMAC_RXCTL_RXCTL_Pos 0
+  #define ZBMAC_RXCTL_RXCTL_Msk 0x01fUL
+  #define ZBMAC_RXSTAT_FCS_ERROR_Pos 0
+  #define ZBMAC_RXSTAT_FCS_ERROR_Msk 0x01UL
+  #define ZBMAC_RXSTAT_ABORT_Pos 1
+  #define ZBMAC_RXSTAT_ABORT_Msk 0x02UL
+  #define ZBMAC_RXSTAT_UNUSED_2_2_Pos 2
+  #define ZBMAC_RXSTAT_UNUSED_2_2_Msk 0x04UL
+  #define ZBMAC_RXSTAT_UNUSED_3_3_Pos 3
+  #define ZBMAC_RXSTAT_UNUSED_3_3_Msk 0x08UL
+  #define ZBMAC_RXSTAT_MOD_IN_PACKET_Pos 4
+  #define ZBMAC_RXSTAT_MOD_IN_PACKET_Msk 0x010UL
+  #define ZBMAC_RXSTAT_MALFORMED_Pos 5
+  #define ZBMAC_RXSTAT_MALFORMED_Msk 0x020UL
+  #define ZBMAC_RXMPID_RXMPID_Pos 0
+  #define ZBMAC_RXMPID_RXMPID_Msk 0x03ffffUL
+  #define ZBMAC_RXMSAD_RXMSAD_Pos 0
+  #define ZBMAC_RXMSAD_RXMSAD_Msk 0x0ffffUL
+  #define ZBMAC_RXMEADL_RXMEADL_Pos 0
+  #define ZBMAC_RXMEADL_RXMEADL_Msk 0x0ffffffffUL
+  #define ZBMAC_RXMEADH_RXMEADH_Pos 0
+  #define ZBMAC_RXMEADH_RXMEADH_Msk 0x0ffffffffUL
+  #define ZBMAC_RXBUFAD_RXBUFAD_Pos 0
+  #define ZBMAC_RXBUFAD_RXBUFAD_Msk 0x0ffffffffUL
+  #define ZBMAC_RXPROM_RXPROM_Pos 0
+  #define ZBMAC_RXPROM_RXPROM_Msk 0x03UL
+  #define ZBMAC_RXMPID_SEC_RXMPID_SEC_Pos 0
+  #define ZBMAC_RXMPID_SEC_RXMPID_SEC_Msk 0x07ffffUL
+  #define ZBMAC_RXMSAD_SEC_RXMSAD_SEC_Pos 0
+  #define ZBMAC_RXMSAD_SEC_RXMSAD_SEC_Msk 0x0ffffUL
+  #define ZBMAC_RXMEADL_SEC_RXMEADL_SEC_Pos 0
+  #define ZBMAC_RXMEADL_SEC_RXMEADL_SEC_Msk 0x0ffffffffUL
+  #define ZBMAC_RXMEADH_SEC_RXMEADH_SEC_Pos 0
+  #define ZBMAC_RXMEADH_SEC_RXMEADH_SEC_Msk 0x0ffffffffUL
+  #define ZBMAC_DMA_ADDR_DMA_ADDR_Pos 0
+  #define ZBMAC_DMA_ADDR_DMA_ADDR_Msk 0x0ffffffffUL
+  #define ZBMAC_DMA_RD_DATA_DMA_RD_DATA_Pos 0
+  #define ZBMAC_DMA_RD_DATA_DMA_RD_DATA_Msk 0x0ffffffffUL
+  #define ZBMAC_DMA_WR_DATA_DMA_WR_DATA_Pos 0
+  #define ZBMAC_DMA_WR_DATA_DMA_WR_DATA_Msk 0x0ffffffffUL
+  #define ZBMAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Pos 15
+  #define ZBMAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Msk 0x0ffff8000UL
+  #define ZBMAC_DMA_FROM_ADC_ACTIVATE_Pos 0
+  #define ZBMAC_DMA_FROM_ADC_ACTIVATE_Msk 0x01UL
+  #define ZBMAC_DMA_FROM_ADC_MODE_Pos 1
+  #define ZBMAC_DMA_FROM_ADC_MODE_Msk 0x01eUL
+  #define ZBMAC_PHY_MCTRL_BBC_RMI_REQ_Pos 0
+  #define ZBMAC_PHY_MCTRL_BBC_RMI_REQ_Msk 0x01UL
+  #define ZBMAC_PHY_MSTATUS_BBC_RMI_ACK_Pos 0
+  #define ZBMAC_PHY_MSTATUS_BBC_RMI_ACK_Msk 0x01UL
+  #define ZBMAC_POWERDOWN_SOFT_RESET_Pos 0
+  #define ZBMAC_POWERDOWN_SOFT_RESET_Msk 0x01UL
+  #define ZBMAC_POWERDOWN_FORCE_SOFTRESET_Pos 1
+  #define ZBMAC_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
+  #define ZBMAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
+  #define ZBMAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
+  #define ZBMAC_POWERDOWN_POWERDOWN_Pos 31
+  #define ZBMAC_POWERDOWN_POWERDOWN_Msk 0x080000000UL
+  #define ZBMAC_MODULEID_APERTURE_Pos 0
+  #define ZBMAC_MODULEID_APERTURE_Msk 0x0ffUL
+  #define ZBMAC_MODULEID_MINOR_REVISION_Pos 8
+  #define ZBMAC_MODULEID_MINOR_REVISION_Msk 0x0f00UL
+  #define ZBMAC_MODULEID_MAJOR_REVISION_Pos 12
+  #define ZBMAC_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
+  #define ZBMAC_MODULEID_IDENTIFIER_Pos 16
+  #define ZBMAC_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
+#else
+  #define ZB_MAC_SCMR0_SCMR0_Pos 0
+  #define ZB_MAC_SCMR0_SCMR0_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCMR1_SCMR1_Pos 0
+  #define ZB_MAC_SCMR1_SCMR1_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCMR2_SCMR2_Pos 0
+  #define ZB_MAC_SCMR2_SCMR2_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCMR3_SCMR3_Pos 0
+  #define ZB_MAC_SCMR3_SCMR3_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCTR0_SCTR0_Pos 0
+  #define ZB_MAC_SCTR0_SCTR0_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCTR1_SCTR1_Pos 0
+  #define ZB_MAC_SCTR1_SCTR1_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCTCR_SCTCR_Pos 0
+  #define ZB_MAC_SCTCR_SCTCR_Msk 0x03UL
+  #define ZB_MAC_SCFRC_SCFRC_Pos 0
+  #define ZB_MAC_SCFRC_SCFRC_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCSSR_SCSSR_Pos 0
+  #define ZB_MAC_SCSSR_SCSSR_Msk 0x0ffffffffUL
+  #define ZB_MAC_SCESL_SCESL_Pos 0
+  #define ZB_MAC_SCESL_SCESL_Msk 0x0ffffffffUL
+  #define ZB_MAC_RXETST_RXETST_Pos 0
+  #define ZB_MAC_RXETST_RXETST_Msk 0x0ffffffffUL
+  #define ZB_MAC_RXTSTP_RXTSTP_Pos 0
+  #define ZB_MAC_RXTSTP_RXTSTP_Msk 0x0ffffffffUL
+  #define ZB_MAC_TXTSTP_TXTSTP_Pos 0
+  #define ZB_MAC_TXTSTP_TXTSTP_Msk 0x0ffffffffUL
+  #define ZB_MAC_IER_IER_Pos 0
+  #define ZB_MAC_IER_IER_Msk 0x0fffUL
+  #define ZB_MAC_ISR_TXINT_Pos 0
+  #define ZB_MAC_ISR_TXINT_Msk 0x01UL
+  #define ZB_MAC_ISR_HEADERRXINT_Pos 1
+  #define ZB_MAC_ISR_HEADERRXINT_Msk 0x02UL
+  #define ZB_MAC_ISR_RXINT_Pos 2
+  #define ZB_MAC_ISR_RXINT_Msk 0x04UL
+  #define ZB_MAC_ISR_UNUSED_3_3_Pos 3
+  #define ZB_MAC_ISR_UNUSED_3_3_Msk 0x08UL
+  #define ZB_MAC_ISR_MATCH_Pos 4
+  #define ZB_MAC_ISR_MATCH_Msk 0x0f0UL
+  #define ZB_MAC_ISR_TIMEOUT_Pos 8
+  #define ZB_MAC_ISR_TIMEOUT_Msk 0x0300UL
+  #define ZB_MAC_ISR_RXNOMATCH_Pos 10
+  #define ZB_MAC_ISR_RXNOMATCH_Msk 0x0400UL
+  #define ZB_MAC_ISR_RXMATCH_Pos 11
+  #define ZB_MAC_ISR_RXMATCH_Msk 0x0800UL
+  #define ZB_MAC_SCTL_SCTL_Pos 0
+  #define ZB_MAC_SCTL_SCTL_Msk 0x07fUL
+  #define ZB_MAC_PHYTXTUNETIME_PHYTXTUNETIME_Pos 0
+  #define ZB_MAC_PHYTXTUNETIME_PHYTXTUNETIME_Msk 0x0ffUL
+  #define ZB_MAC_PHYTXTUNETIME_PHYRX2TXTIME_Pos 8
+  #define ZB_MAC_PHYTXTUNETIME_PHYRX2TXTIME_Msk 0x0ff00UL
+  #define ZB_MAC_PHYRXTUNETIME_PHYRXTUNETIME_Pos 0
+  #define ZB_MAC_PHYRXTUNETIME_PHYRXTUNETIME_Msk 0x0ffUL
+  #define ZB_MAC_TURNAROUNDTIME_TURNAROUNDTIME_Pos 0
+  #define ZB_MAC_TURNAROUNDTIME_TURNAROUNDTIME_Msk 0x0ffUL
+  #define ZB_MAC_BACKOFFTIME_BACKOFFTIME_Pos 0
+  #define ZB_MAC_BACKOFFTIME_BACKOFFTIME_Msk 0x0ffUL
+  #define ZB_MAC_PRBS_SEED_PRBS_SEED_Pos 0
+  #define ZB_MAC_PRBS_SEED_PRBS_SEED_Msk 0x07fffUL
+  #define ZB_MAC_SM_STATE_SM_STATE_Pos 0
+  #define ZB_MAC_SM_STATE_SM_STATE_Msk 0x07fUL
+  #define ZB_MAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Pos 0
+  #define ZB_MAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Msk 0x0ffUL
+  #define ZB_MAC_HDR_CTRL_HDR_CTRL_Pos 0
+  #define ZB_MAC_HDR_CTRL_HDR_CTRL_Msk 0x03UL
+  #define ZB_MAC_MISR_MISR_Pos 0
+  #define ZB_MAC_MISR_MISR_Msk 0x03ffUL
+  #define ZB_MAC_IDENTIFIER_IDENTIFIER_Pos 0
+  #define ZB_MAC_IDENTIFIER_IDENTIFIER_Msk 0x0ffffffffUL
+  #define ZB_MAC_TXCTL_SCH_Pos 0
+  #define ZB_MAC_TXCTL_SCH_Msk 0x01UL
+  #define ZB_MAC_TXCTL_SS_Pos 1
+  #define ZB_MAC_TXCTL_SS_Msk 0x02UL
+  #define ZB_MAC_TXCTL_SLOTACK_Pos 2
+  #define ZB_MAC_TXCTL_SLOTACK_Msk 0x04UL
+  #define ZB_MAC_TXCTL_AA_Pos 3
+  #define ZB_MAC_TXCTL_AA_Msk 0x08UL
+  #define ZB_MAC_TXCTL_MODE_Pos 4
+  #define ZB_MAC_TXCTL_MODE_Msk 0x030UL
+  #define ZB_MAC_TXSTAT_TXSTAT_Pos 0
+  #define ZB_MAC_TXSTAT_TXSTAT_Msk 0x01fUL
+  #define ZB_MAC_TXSTAT_TXTO_Pos 5
+  #define ZB_MAC_TXSTAT_TXTO_Msk 0x020UL
+  #define ZB_MAC_TXSTAT_TXPCTO_Pos 6
+  #define ZB_MAC_TXSTAT_TXPCTO_Msk 0x040UL
+  #define ZB_MAC_TXMBEBT_MINBE_Pos 0
+  #define ZB_MAC_TXMBEBT_MINBE_Msk 0x0fUL
+  #define ZB_MAC_TXMBEBT_MAXBO_Pos 4
+  #define ZB_MAC_TXMBEBT_MAXBO_Msk 0x070UL
+  #define ZB_MAC_TXMBEBT_BLE_Pos 7
+  #define ZB_MAC_TXMBEBT_BLE_Msk 0x080UL
+  #define ZB_MAC_TXMBEBT_MAXBE_Pos 8
+  #define ZB_MAC_TXMBEBT_MAXBE_Msk 0x0f00UL
+  #define ZB_MAC_TXMBEBT_FRCDLY_Pos 12
+  #define ZB_MAC_TXMBEBT_FRCDLY_Msk 0x01000UL
+  #define ZB_MAC_TXMBEBT_HIDE_Pos 13
+  #define ZB_MAC_TXMBEBT_HIDE_Msk 0x01e000UL
+  #define ZB_MAC_TXCSMAC_TXCSMAC_Pos 0
+  #define ZB_MAC_TXCSMAC_TXCSMAC_Msk 0x03ffffUL
+  #define ZB_MAC_TXTRIES_TXTRIES_Pos 0
+  #define ZB_MAC_TXTRIES_TXTRIES_Msk 0x0fUL
+  #define ZB_MAC_TXPEND_TXPEND_Pos 0
+  #define ZB_MAC_TXPEND_TXPEND_Msk 0x01UL
+  #define ZB_MAC_TXASC_TXASC_Pos 0
+  #define ZB_MAC_TXASC_TXASC_Msk 0x01UL
+  #define ZB_MAC_TXBUFAD_TXBUFAD_Pos 0
+  #define ZB_MAC_TXBUFAD_TXBUFAD_Msk 0x0ffffffffUL
+  #define ZB_MAC_TXTO_TX_TO_LEN_Pos 0
+  #define ZB_MAC_TXTO_TX_TO_LEN_Msk 0x07fUL
+  #define ZB_MAC_TXTO_TX_TO_ENA_Pos 7
+  #define ZB_MAC_TXTO_TX_TO_ENA_Msk 0x080UL
+  #define ZB_MAC_TXTO_TX_TOPC_ENA_Pos 8
+  #define ZB_MAC_TXTO_TX_TOPC_ENA_Msk 0x0100UL
+  #define ZB_MAC_RXCTL_RXCTL_Pos 0
+  #define ZB_MAC_RXCTL_RXCTL_Msk 0x01fUL
+  #define ZB_MAC_RXSTAT_FCS_ERROR_Pos 0
+  #define ZB_MAC_RXSTAT_FCS_ERROR_Msk 0x01UL
+  #define ZB_MAC_RXSTAT_ABORT_Pos 1
+  #define ZB_MAC_RXSTAT_ABORT_Msk 0x02UL
+  #define ZB_MAC_RXSTAT_UNUSED_2_2_Pos 2
+  #define ZB_MAC_RXSTAT_UNUSED_2_2_Msk 0x04UL
+  #define ZB_MAC_RXSTAT_UNUSED_3_3_Pos 3
+  #define ZB_MAC_RXSTAT_UNUSED_3_3_Msk 0x08UL
+  #define ZB_MAC_RXSTAT_MOD_IN_PACKET_Pos 4
+  #define ZB_MAC_RXSTAT_MOD_IN_PACKET_Msk 0x010UL
+  #define ZB_MAC_RXSTAT_MALFORMED_Pos 5
+  #define ZB_MAC_RXSTAT_MALFORMED_Msk 0x020UL
+  #define ZB_MAC_RXMPID_RXMPID_Pos 0
+  #define ZB_MAC_RXMPID_RXMPID_Msk 0x03ffffUL
+  #define ZB_MAC_RXMSAD_RXMSAD_Pos 0
+  #define ZB_MAC_RXMSAD_RXMSAD_Msk 0x0ffffUL
+  #define ZB_MAC_RXMEADL_RXMEADL_Pos 0
+  #define ZB_MAC_RXMEADL_RXMEADL_Msk 0x0ffffffffUL
+  #define ZB_MAC_RXMEADH_RXMEADH_Pos 0
+  #define ZB_MAC_RXMEADH_RXMEADH_Msk 0x0ffffffffUL
+  #define ZB_MAC_RXBUFAD_RXBUFAD_Pos 0
+  #define ZB_MAC_RXBUFAD_RXBUFAD_Msk 0x0ffffffffUL
+  #define ZB_MAC_RXPROM_RXPROM_Pos 0
+  #define ZB_MAC_RXPROM_RXPROM_Msk 0x03UL
+  #define ZB_MAC_RXMPID_SEC_RXMPID_SEC_Pos 0
+  #define ZB_MAC_RXMPID_SEC_RXMPID_SEC_Msk 0x07ffffUL
+  #define ZB_MAC_RXMSAD_SEC_RXMSAD_SEC_Pos 0
+  #define ZB_MAC_RXMSAD_SEC_RXMSAD_SEC_Msk 0x0ffffUL
+  #define ZB_MAC_RXMEADL_SEC_RXMEADL_SEC_Pos 0
+  #define ZB_MAC_RXMEADL_SEC_RXMEADL_SEC_Msk 0x0ffffffffUL
+  #define ZB_MAC_RXMEADH_SEC_RXMEADH_SEC_Pos 0
+  #define ZB_MAC_RXMEADH_SEC_RXMEADH_SEC_Msk 0x0ffffffffUL
+  #define ZB_MAC_DMA_ADDR_DMA_ADDR_Pos 0
+  #define ZB_MAC_DMA_ADDR_DMA_ADDR_Msk 0x0ffffffffUL
+  #define ZB_MAC_DMA_RD_DATA_DMA_RD_DATA_Pos 0
+  #define ZB_MAC_DMA_RD_DATA_DMA_RD_DATA_Msk 0x0ffffffffUL
+  #define ZB_MAC_DMA_WR_DATA_DMA_WR_DATA_Pos 0
+  #define ZB_MAC_DMA_WR_DATA_DMA_WR_DATA_Msk 0x0ffffffffUL
+  #define ZB_MAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Pos 17
+  #define ZB_MAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Msk 0x0fffe0000UL
+  #define ZB_MAC_DMA_FROM_ADC_ACTIVATE_Pos 0
+  #define ZB_MAC_DMA_FROM_ADC_ACTIVATE_Msk 0x01UL
+  #define ZB_MAC_DMA_FROM_ADC_MODE_Pos 1
+  #define ZB_MAC_DMA_FROM_ADC_MODE_Msk 0x01eUL
+  #define ZB_MAC_DMA_FROM_ADC_SAFE_Pos 5
+  #define ZB_MAC_DMA_FROM_ADC_SAFE_Msk 0x020UL
+  #define ZB_MAC_PHY_MCTRL_BBC_RMI_REQ_Pos 0
+  #define ZB_MAC_PHY_MCTRL_BBC_RMI_REQ_Msk 0x01UL
+  #define ZB_MAC_PHY_MSTATUS_BBC_RMI_ACK_Pos 0
+  #define ZB_MAC_PHY_MSTATUS_BBC_RMI_ACK_Msk 0x01UL
+  #define ZB_MAC_POWERDOWN_SOFT_RESET_Pos 0
+  #define ZB_MAC_POWERDOWN_SOFT_RESET_Msk 0x01UL
+  #define ZB_MAC_POWERDOWN_FORCE_SOFTRESET_Pos 1
+  #define ZB_MAC_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
+  #define ZB_MAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
+  #define ZB_MAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
+  #define ZB_MAC_POWERDOWN_POWERDOWN_Pos 31
+  #define ZB_MAC_POWERDOWN_POWERDOWN_Msk 0x080000000UL
+  #define ZB_MAC_MODULEID_APERTURE_Pos 0
+  #define ZB_MAC_MODULEID_APERTURE_Msk 0x0ffUL
+  #define ZB_MAC_MODULEID_MINOR_REVISION_Pos 8
+  #define ZB_MAC_MODULEID_MINOR_REVISION_Msk 0x0f00UL
+  #define ZB_MAC_MODULEID_MAJOR_REVISION_Pos 12
+  #define ZB_MAC_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
+  #define ZB_MAC_MODULEID_IDENTIFIER_Pos 16
+  #define ZB_MAC_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
+#endif
+
+#endif // __ZB_MAC_IF_H__

third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_modem.h

@@ -0,0 +1,405 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef __ZB_MODEM_IF_H__
+#define __ZB_MODEM_IF_H__
+
+  typedef  struct {
+        /* Address 0x000 */
+        union {
+           __IO uint32_t MCCA_CTRL;
+
+        struct {
+           __IO uint32_t  rx_cca_mode : 2;
+           __IO uint32_t  rx_cca_thresh : 10;
+           __IO uint32_t  rx_cca_or : 1;
+           __IO uint32_t  reserved13 : 19;
+          } MCCA_CTRL_b;
+        };
+        /* Address 0x004 */
+        union {
+           __IO uint32_t MTX_CTRL;
+
+        struct {
+           __IO uint32_t  tx_test_en : 1;
+           __IO uint32_t  tx_test_mode : 1;
+           __IO uint32_t  tx_pol : 1;
+           __IO uint32_t  tx_inframe_sync : 1;
+           __IO uint32_t  reserved4 : 28;
+          } MTX_CTRL_b;
+        };
+        /* Address 0x008 */
+        union {
+           __IO uint32_t MTX_TST_SEQ;
+
+        struct {
+           __IO uint32_t  tx_test_seq : 32;
+          } MTX_TST_SEQ_b;
+        };
+        /* Address 0x00C */
+        union {
+           __IO uint32_t MRX_CTRL;
+
+        struct {
+           __IO uint32_t  rx_cor_lo : 6;
+           __IO uint32_t  rx_cor_hi : 6;
+           __IO uint32_t  rx_sync_mode : 2;
+           __IO uint32_t  rx_pol : 2;
+           __IO uint32_t  rx_pre_num : 3;
+           __IO uint32_t  rx_early_eop : 2;
+           __IO uint32_t  rx_agc_rst_en : 1;
+           __IO uint32_t  rx_agc_rst_thr : 7;
+           __IO uint32_t  rx_rssi_avg_en : 1;
+           __IO uint32_t  rx_rssi_pulse_mode : 1;
+           __IO uint32_t  reserved31 : 1;
+          } MRX_CTRL_b;
+        };
+        /* Address 0x010 */
+        union {
+           __I  uint32_t MSTAT;
+
+        struct {
+           __I  uint32_t  rx_pre_state : 2;
+           __I  uint32_t  rx_pre_cnt : 3;
+           __I  uint32_t  rx_ad_ant : 1;
+           __I  uint32_t  rx_rssi_avg : 10;
+           __I  uint32_t  rx_sqi : 8;
+           __I  uint32_t  rx_ccas : 1;
+           __I  uint32_t  rx_ad_switch : 1;
+           __I  uint32_t  reserved26 : 6;
+          } MSTAT_b;
+        };
+        /* Address 0x014 */
+        union {
+           __IO uint32_t RXFE_CONFIG;
+
+        struct {
+           __IO uint32_t  selfi : 4;
+           __IO uint32_t  specinv : 1;
+           __IO uint32_t  bypass_lpf : 1;
+           __IO uint32_t  bypass_adj : 1;
+           __IO uint32_t  selfe4demod : 1;
+           __IO uint32_t  selfe4agc : 1;
+           __IO uint32_t  loopback : 1;
+           __IO uint32_t  bitinv : 1;
+           __IO uint32_t  xcorr_mode : 1;
+           __IO uint32_t  reserved12 : 20;
+          } RXFE_CONFIG_b;
+        };
+        /* Address 0x018 */
+        union {
+           __IO uint32_t PHY_MCTRL;
+
+        struct {
+           __IO uint32_t  reserved0 : 1;
+           __IO uint32_t  miom : 1;
+           __IO uint32_t  mphyon : 1;
+           __IO uint32_t  mphydir : 1;
+           __IO uint32_t  mccat : 1;
+           __IO uint32_t  medt : 1;
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+    /* ES1 if explicitly configured */
+	           __IO uint32_t  reserved6 : 26;
+#else
+    /* ES2 default */
+           __IO uint32_t  aedt : 1;
+           __IO uint32_t  reserved7 : 25;
+#endif
+          } PHY_MCTRL_b;
+        };
+        /* Address 0x01C */
+        union {
+           __IO uint32_t PHY_CHAN;
+
+        struct {
+           __IO uint32_t  chan : 5;
+           __IO uint32_t  unused_6_5 : 2;
+           __IO uint32_t  man_freq_en : 1;
+           __IO uint32_t  man_freq : 8;
+           __IO uint32_t  reserved16 : 16;
+          } PHY_CHAN_b;
+        };
+        /* Address 0x020 */
+        union {
+           __IO uint32_t PHY_PWR;
+
+        struct {
+           __IO uint32_t  pwr : 8;
+           __IO uint32_t  reserved8 : 24;
+          } PHY_PWR_b;
+        };
+        /* Address 0x024 */
+        union {
+           __I  uint32_t RX_PP;
+
+        struct {
+           __I  uint32_t  rx_cpp : 10;
+           __I  uint32_t  rx_ppp : 10;
+           __I  uint32_t  rx_ipp : 10;
+           __I  uint32_t  reserved30 : 2;
+          } RX_PP_b;
+        };
+        /* Address 0x028 */
+        union {
+           __IO uint32_t ANT_DIV_P;
+
+        struct {
+           __IO uint32_t  sw_toogle : 1;
+           __IO uint32_t  reserved1 : 31;
+          } ANT_DIV_P_b;
+        };
+        /* Address 0x02C */
+        union {
+           __IO uint32_t ANT_DIV;
+
+        struct {
+           __IO uint32_t  ad_rssi_thr : 10;
+           __IO uint32_t  rx_ad_en : 1;
+           __IO uint32_t  tx_ad_en : 1;
+           __IO uint32_t  rx_ad_timer : 4;
+           __IO uint32_t  reserved16 : 16;
+          } ANT_DIV_b;
+        };
+        /* Addresses 0x030 - 0xFDC */
+        __O  uint32_t  RESERVED030[1004];
+        /* Address 0xFE0 */
+        union {
+           __I  uint32_t ZB_EVENTS_STATUS;
+
+        struct {
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __I  uint32_t  status : 13;
+           __I  uint32_t  reserved13 : 19;
+#else
+           __I  uint32_t  status : 15;
+           __I  uint32_t  reserved15 : 17;
+#endif
+          } ZB_EVENTS_STATUS_b;
+        };
+        /* Address 0xFE4 */
+        union {
+           __IO uint32_t ZB_EVENTS_ENABLE;
+
+        struct {
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __IO uint32_t  enable : 13;
+           __IO uint32_t  reserved13 : 19;
+#else
+           __IO uint32_t  enable : 15;
+           __IO uint32_t  reserved15 : 17;
+#endif
+          } ZB_EVENTS_ENABLE_b;
+        };
+        /* Address 0xFE8 */
+        union {
+           __IO uint32_t ZB_EVENTS_CLEAR;
+
+        struct {
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __IO uint32_t  clear : 13;
+           __IO uint32_t  reserved13 : 19;
+#else
+           __IO uint32_t  clear : 15;
+           __IO uint32_t  reserved15 : 17;
+#endif
+          } ZB_EVENTS_CLEAR_b;
+        };
+        /* Address 0xFEC */
+        union {
+           __IO uint32_t ZB_EVENTS_SET;
+
+        struct {
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+           __IO uint32_t  set : 13;
+           __IO uint32_t  reserved13 : 19;
+#else
+           __IO uint32_t  set : 15;
+           __IO uint32_t  reserved15 : 17;
+#endif
+          } ZB_EVENTS_SET_b;
+        };
+        /* Address 0xFF0 */
+        __O  uint32_t  RESERVEDFF0[1];
+        /* Address 0xFF4 */
+        union {
+           __IO uint32_t POWERDOWN;
+
+        struct {
+           __IO uint32_t  soft_reset : 1;
+           __IO uint32_t  force_softreset : 1;
+           __IO uint32_t  enable_flags_with_core_bus : 1;
+           __IO uint32_t  reserved3 : 28;
+           __IO uint32_t  powerdown : 1;
+          } POWERDOWN_b;
+        };
+        /* Address 0xFF8 */
+        __O  uint32_t  RESERVEDFF8[1];
+        /* Address 0xFFC */
+        union {
+           __I  uint32_t MODULEID;
+
+        struct {
+           __I  uint32_t  aperture : 8;
+           __I  uint32_t  minor_revision : 4;
+           __I  uint32_t  major_revision : 4;
+           __I  uint32_t  identifier : 16;
+          } MODULEID_b;
+        };
+    } ZB_MODEM_IF_Type;
+
+  #define ZB_MODEM_MCCA_CTRL_RX_CCA_MODE_Pos 0
+  #define ZB_MODEM_MCCA_CTRL_RX_CCA_MODE_Msk 0x03UL
+  #define ZB_MODEM_MCCA_CTRL_RX_CCA_THRESH_Pos 2
+  #define ZB_MODEM_MCCA_CTRL_RX_CCA_THRESH_Msk 0x0ffcUL
+  #define ZB_MODEM_MCCA_CTRL_RX_CCA_OR_Pos 12
+  #define ZB_MODEM_MCCA_CTRL_RX_CCA_OR_Msk 0x01000UL
+  #define ZB_MODEM_MTX_CTRL_TX_TEST_EN_Pos 0
+  #define ZB_MODEM_MTX_CTRL_TX_TEST_EN_Msk 0x01UL
+  #define ZB_MODEM_MTX_CTRL_TX_TEST_MODE_Pos 1
+  #define ZB_MODEM_MTX_CTRL_TX_TEST_MODE_Msk 0x02UL
+  #define ZB_MODEM_MTX_CTRL_TX_POL_Pos 2
+  #define ZB_MODEM_MTX_CTRL_TX_POL_Msk 0x04UL
+  #define ZB_MODEM_MTX_CTRL_TX_INFRAME_SYNC_Pos 3
+  #define ZB_MODEM_MTX_CTRL_TX_INFRAME_SYNC_Msk 0x08UL
+  #define ZB_MODEM_MTX_TST_SEQ_TX_TEST_SEQ_Pos 0
+  #define ZB_MODEM_MTX_TST_SEQ_TX_TEST_SEQ_Msk 0x0ffffffffUL
+  #define ZB_MODEM_MRX_CTRL_RX_COR_LO_Pos 0
+  #define ZB_MODEM_MRX_CTRL_RX_COR_LO_Msk 0x03fUL
+  #define ZB_MODEM_MRX_CTRL_RX_COR_HI_Pos 6
+  #define ZB_MODEM_MRX_CTRL_RX_COR_HI_Msk 0x0fc0UL
+  #define ZB_MODEM_MRX_CTRL_RX_SYNC_MODE_Pos 12
+  #define ZB_MODEM_MRX_CTRL_RX_SYNC_MODE_Msk 0x03000UL
+  #define ZB_MODEM_MRX_CTRL_RX_POL_Pos 14
+  #define ZB_MODEM_MRX_CTRL_RX_POL_Msk 0x0c000UL
+  #define ZB_MODEM_MRX_CTRL_RX_PRE_NUM_Pos 16
+  #define ZB_MODEM_MRX_CTRL_RX_PRE_NUM_Msk 0x070000UL
+  #define ZB_MODEM_MRX_CTRL_RX_EARLY_EOP_Pos 19
+  #define ZB_MODEM_MRX_CTRL_RX_EARLY_EOP_Msk 0x0180000UL
+  #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_EN_Pos 21
+  #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_EN_Msk 0x0200000UL
+  #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_THR_Pos 22
+  #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_THR_Msk 0x01fc00000UL
+  #define ZB_MODEM_MRX_CTRL_RX_RSSI_AVG_EN_Pos 29
+  #define ZB_MODEM_MRX_CTRL_RX_RSSI_AVG_EN_Msk 0x020000000UL
+  #define ZB_MODEM_MRX_CTRL_RX_RSSI_PULSE_MODE_Pos 30
+  #define ZB_MODEM_MRX_CTRL_RX_RSSI_PULSE_MODE_Msk 0x040000000UL
+  #define ZB_MODEM_MSTAT_RX_PRE_STATE_Pos 0
+  #define ZB_MODEM_MSTAT_RX_PRE_STATE_Msk 0x03UL
+  #define ZB_MODEM_MSTAT_RX_PRE_CNT_Pos 2
+  #define ZB_MODEM_MSTAT_RX_PRE_CNT_Msk 0x01cUL
+  #define ZB_MODEM_MSTAT_RX_AD_ANT_Pos 5
+  #define ZB_MODEM_MSTAT_RX_AD_ANT_Msk 0x020UL
+  #define ZB_MODEM_MSTAT_RX_RSSI_AVG_Pos 6
+  #define ZB_MODEM_MSTAT_RX_RSSI_AVG_Msk 0x0ffc0UL
+  #define ZB_MODEM_MSTAT_RX_SQI_Pos 16
+  #define ZB_MODEM_MSTAT_RX_SQI_Msk 0x0ff0000UL
+  #define ZB_MODEM_MSTAT_RX_CCAS_Pos 24
+  #define ZB_MODEM_MSTAT_RX_CCAS_Msk 0x01000000UL
+  #define ZB_MODEM_MSTAT_RX_AD_SWITCH_Pos 25
+  #define ZB_MODEM_MSTAT_RX_AD_SWITCH_Msk 0x02000000UL
+  #define ZB_MODEM_RXFE_CONFIG_SELFI_Pos 0
+  #define ZB_MODEM_RXFE_CONFIG_SELFI_Msk 0x0fUL
+  #define ZB_MODEM_RXFE_CONFIG_SPECINV_Pos 4
+  #define ZB_MODEM_RXFE_CONFIG_SPECINV_Msk 0x010UL
+  #define ZB_MODEM_RXFE_CONFIG_BYPASS_LPF_Pos 5
+  #define ZB_MODEM_RXFE_CONFIG_BYPASS_LPF_Msk 0x020UL
+  #define ZB_MODEM_RXFE_CONFIG_BYPASS_ADJ_Pos 6
+  #define ZB_MODEM_RXFE_CONFIG_BYPASS_ADJ_Msk 0x040UL
+  #define ZB_MODEM_RXFE_CONFIG_SELFE4DEMOD_Pos 7
+  #define ZB_MODEM_RXFE_CONFIG_SELFE4DEMOD_Msk 0x080UL
+  #define ZB_MODEM_RXFE_CONFIG_SELFE4AGC_Pos 8
+  #define ZB_MODEM_RXFE_CONFIG_SELFE4AGC_Msk 0x0100UL
+  #define ZB_MODEM_RXFE_CONFIG_LOOPBACK_Pos 9
+  #define ZB_MODEM_RXFE_CONFIG_LOOPBACK_Msk 0x0200UL
+  #define ZB_MODEM_RXFE_CONFIG_BITINV_Pos 10
+  #define ZB_MODEM_RXFE_CONFIG_BITINV_Msk 0x0400UL
+  #define ZB_MODEM_RXFE_CONFIG_XCORR_MODE_Pos 11
+  #define ZB_MODEM_RXFE_CONFIG_XCORR_MODE_Msk 0x0800UL
+  #define ZB_MODEM_PHY_MCTRL_MIOM_Pos 1
+  #define ZB_MODEM_PHY_MCTRL_MIOM_Msk 0x02UL
+  #define ZB_MODEM_PHY_MCTRL_MPHYON_Pos 2
+  #define ZB_MODEM_PHY_MCTRL_MPHYON_Msk 0x04UL
+  #define ZB_MODEM_PHY_MCTRL_MPHYDIR_Pos 3
+  #define ZB_MODEM_PHY_MCTRL_MPHYDIR_Msk 0x08UL
+  #define ZB_MODEM_PHY_MCTRL_MCCAT_Pos 4
+  #define ZB_MODEM_PHY_MCTRL_MCCAT_Msk 0x010UL
+  #define ZB_MODEM_PHY_MCTRL_MEDT_Pos 5
+  #define ZB_MODEM_PHY_MCTRL_MEDT_Msk 0x020UL
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+#else
+  #define ZB_MODEM_PHY_MCTRL_AEDT_Pos 6
+  #define ZB_MODEM_PHY_MCTRL_AEDT_Msk 0x040UL
+#endif
+  #define ZB_MODEM_PHY_CHAN_CHAN_Pos 0
+  #define ZB_MODEM_PHY_CHAN_CHAN_Msk 0x01fUL
+  #define ZB_MODEM_PHY_CHAN_UNUSED_6_5_Pos 5
+  #define ZB_MODEM_PHY_CHAN_UNUSED_6_5_Msk 0x060UL
+  #define ZB_MODEM_PHY_CHAN_MAN_FREQ_EN_Pos 7
+  #define ZB_MODEM_PHY_CHAN_MAN_FREQ_EN_Msk 0x080UL
+  #define ZB_MODEM_PHY_CHAN_MAN_FREQ_Pos 8
+  #define ZB_MODEM_PHY_CHAN_MAN_FREQ_Msk 0x0ff00UL
+  #define ZB_MODEM_PHY_PWR_PWR_Pos 0
+  #define ZB_MODEM_PHY_PWR_PWR_Msk 0x0ffUL
+  #define ZB_MODEM_RX_PP_RX_CPP_Pos 0
+  #define ZB_MODEM_RX_PP_RX_CPP_Msk 0x03ffUL
+  #define ZB_MODEM_RX_PP_RX_PPP_Pos 10
+  #define ZB_MODEM_RX_PP_RX_PPP_Msk 0x0ffc00UL
+  #define ZB_MODEM_RX_PP_RX_IPP_Pos 20
+  #define ZB_MODEM_RX_PP_RX_IPP_Msk 0x03ff00000UL
+  #define ZB_MODEM_ANT_DIV_P_SW_TOOGLE_Pos 0
+  #define ZB_MODEM_ANT_DIV_P_SW_TOOGLE_Msk 0x01UL
+  #define ZB_MODEM_ANT_DIV_AD_RSSI_THR_Pos 0
+  #define ZB_MODEM_ANT_DIV_AD_RSSI_THR_Msk 0x03ffUL
+  #define ZB_MODEM_ANT_DIV_RX_AD_EN_Pos 10
+  #define ZB_MODEM_ANT_DIV_RX_AD_EN_Msk 0x0400UL
+  #define ZB_MODEM_ANT_DIV_TX_AD_EN_Pos 11
+  #define ZB_MODEM_ANT_DIV_TX_AD_EN_Msk 0x0800UL
+  #define ZB_MODEM_ANT_DIV_RX_AD_TIMER_Pos 12
+  #define ZB_MODEM_ANT_DIV_RX_AD_TIMER_Msk 0x0f000UL
+  #define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Pos 0
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+  #define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Msk 0x01fffUL
+#else
+  #define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Msk 0x07fffUL
+#endif
+  #define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Pos 0
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+  #define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Msk 0x01fffUL
+#else
+  #define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Msk 0x07fffUL
+#endif
+  #define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Pos 0
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+  #define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Msk 0x01fffUL
+#else
+  #define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Msk 0x07fffUL
+#endif
+  #define ZB_MODEM_ZB_EVENTS_SET_SET_Pos 0
+#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
+  #define ZB_MODEM_ZB_EVENTS_SET_SET_Msk 0x01fffUL
+#else
+  #define ZB_MODEM_ZB_EVENTS_SET_SET_Msk 0x07fffUL
+#endif
+  #define ZB_MODEM_POWERDOWN_SOFT_RESET_Pos 0
+  #define ZB_MODEM_POWERDOWN_SOFT_RESET_Msk 0x01UL
+  #define ZB_MODEM_POWERDOWN_FORCE_SOFTRESET_Pos 1
+  #define ZB_MODEM_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
+  #define ZB_MODEM_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
+  #define ZB_MODEM_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
+  #define ZB_MODEM_POWERDOWN_POWERDOWN_Pos 31
+  #define ZB_MODEM_POWERDOWN_POWERDOWN_Msk 0x080000000UL
+  #define ZB_MODEM_MODULEID_APERTURE_Pos 0
+  #define ZB_MODEM_MODULEID_APERTURE_Msk 0x0ffUL
+  #define ZB_MODEM_MODULEID_MINOR_REVISION_Pos 8
+  #define ZB_MODEM_MODULEID_MINOR_REVISION_Msk 0x0f00UL
+  #define ZB_MODEM_MODULEID_MAJOR_REVISION_Pos 12
+  #define ZB_MODEM_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
+  #define ZB_MODEM_MODULEID_IDENTIFIER_Pos 16
+  #define ZB_MODEM_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
+
+#endif // __ZB_MODEM_IF_H__

third_party/nxp/JN5189/Radio_JN5189/Include/radio.h

@@ -0,0 +1,793 @@
+/*
+ * @brief Radio driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RADIO_H_
+#define __RADIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+/****************************************************************************/
+/***        Macro/Type Definitions                                        ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***    Radio driver version (XYYY): X major version, YYY minor version   ***/
+/****************************************************************************/
+#define RADIO_VERSION (2085)
+
+/****************************************************************************/
+/***    Radio calibration data record version                             ***/
+/****************************************************************************/
+#define RADIO_CAL_RECORD_VERSION (1001)
+
+/****************************************************************************/
+/***    Radio driver int time values									  ***/
+/***	RADIO_INIT_TIME_WITH_KMOD_INIT_US full init time with Kmod cal    ***/
+/***	This init is done only when KMOD cal results are not available    ***/
+/***	in flash for the current initialization temperature. As results   ***/
+/***	are valid in a [-40...+40C] temperature range around the cal      ***/
+/***	temperature, only 4 full calibration are needed in the whole live ***/
+/***	of the chip and this init time is quite never reached.            ***/
+/***	RADIO_INIT_TIME_WITHOUT_KMOD_INIT_US full init time without Kmod  ***/
+/***	calibration. This is the typical coldstart radio init time		  ***/
+/***	RADIO_INIT_TIME_WITH_RETENTION_US init time when using retention  ***/
+/***	In that case calibrations are not run and parameters kept in      ***/
+/***	in retention flops are used instead. This is a the typical warm   ***/
+/***	start init time.                                                  ***/
+/****************************************************************************/
+
+#define RADIO_FULL_INIT_FIRST_TIME (80300) // no record available and all cal to be done because TCur far from TCAL ATE
+#define RADIO_FULL_INIT_TIME (85500) // record available but all cal to be done because TCur far from TCAL ATE
+#define RADIO_INIT_ALL_CAL_IN_FLASH (850) // record available, no cal to be done and TCur close to TCAL ATE
+#define RADIO_INIT_NO_DCO_CAL_IN_FLASH (13500) // no record available, DCO cal only and TCur close to TCAL ATE
+#define RADIO_INIT_TIME_WITH_RETENTION_US (250) // can use retention values
+#define RADIO_RECAL_TIME_ALL_CAL_IN_FLASH_US (750) // recal with cal available in flash for TCur
+#define RADIO_RECAL_TIME_NO_CAL_IN_FLASH_US (86800) // recal with cal data not available in flash, all call to be done
+#define RADIO_RECAL_TIME_NO_DCO_CAL_IN_FLASH_US (16100) // recal with DCO cal to do
+#define RADIO_RECAL_TIME_NORECAL_US (8) // recal when not needed
+#define RADIO_GET_NEXT_RECAL_DURATION (20) // u32Radio_Get_Next_Recal_Duration max execution time
+
+/****************************************************************************/
+/***    Number of bytes of the u8AppliData buffer                         ***/
+/***    See vRadio_Save_ApplicationData_Retention                  ***/
+/***    and vRadio_Restore_Retention_ApplicationData               ***/
+/****************************************************************************/
+#define APP_DATA_RET_NB_BYTES (114)
+#define ADD_DATA_RET_NB_BITS (906)
+
+
+
+/****************************************************************************/
+/***    Local defined values        									  ***/
+/****************************************************************************/
+#define RADIO_MODE_LOPOWER          (0)
+#define RADIO_MODE_HITXPOWER        (1)
+
+#define RADIO_INIT_INITCAL			(0)
+#define RADIO_INIT_DEF_VAL			(1)
+#define RADIO_INIT_RETENTION		(2)
+#define RADIO_INIT_FORCE_CAL		(3)
+
+/****************************************************************************/
+/***	Values to be used as u32RadioMode parameter                       ***/
+/***	for vRadio_RadioInit API                                   ***/
+/*** 	RADIO_MODE_STD_USE_INITCAL default init mode to use. in this mode ***/
+/***	the radio init will be done in standard lowpower mode and the     ***/
+/***	calibrations will be launched automatically based on temperature  ***/
+/***	deviation since last calibration. Calibration will also be done   ***/
+/***	if no retention values are available or if it is the first init.  ***/
+/***	Other values are for test or special needs.                       ***/
+/***	RADIO_MODE_STD_USE_DEF_VAL will force using default values for    ***/
+/***	all parameters. No calibration is done.                           ***/
+/***	RADIO_MODE_STD_USE_RETENTION will force usage of retention values ***/
+/***	without any validity test nor temperature control                 ***/
+/***    RADIO_MODE_STD_USE_FORCE_CAL will force calibration, ignoring any ***/
+/***	retention values and even if temperature has not changed          ***/
+/***	RADIO_MODE_HTXP_... have the same meaning but configure radio in  ***/
+/***	high tx power mode.                                               ***/
+/****************************************************************************/
+#define RADIO_MODE_STD_USE_INITCAL		((RADIO_MODE_LOPOWER << 8) | RADIO_INIT_INITCAL)
+#define RADIO_MODE_STD_USE_DEF_VAL      ((RADIO_MODE_LOPOWER << 8) | RADIO_INIT_DEF_VAL)
+#define RADIO_MODE_STD_USE_RETENTION	((RADIO_MODE_LOPOWER << 8) | RADIO_INIT_RETENTION)
+#define RADIO_MODE_STD_USE_FORCE_CAL	((RADIO_MODE_LOPOWER << 8) | RADIO_INIT_FORCE_CAL)
+#define RADIO_MODE_HTXP_USE_INITCAL		((RADIO_MODE_HITXPOWER << 8) | RADIO_INIT_INITCAL)
+#define RADIO_MODE_HTXP_USE_DEF_VAL		((RADIO_MODE_HITXPOWER << 8) | RADIO_INIT_DEF_VAL)
+#define RADIO_MODE_HTXP_USE_RETENTION	((RADIO_MODE_HITXPOWER << 8) | RADIO_INIT_RETENTION)
+#define RADIO_MODE_HTXP_USE_FORCE_CAL	((RADIO_MODE_HITXPOWER << 8) | RADIO_INIT_FORCE_CAL)
+
+/****************************************************************************/
+/***    Local defined values        									  ***/
+/****************************************************************************/
+#define TX_REGULAR 0
+#define TX_PROP_1  1
+#define TX_PROP_2  2
+#define TX_BLE_1MB 3
+#define TX_BLE_2MB 4
+#define TX_UNDEFINED 0xFF
+
+#define RX_DETECTOR_ONLY 0
+#define RX_ENABLE_LUT    1
+#define RX_BLE_1MB       3
+#define RX_BLE_2MB       4
+#define RX_UNDEFINED 0xFF
+
+/****************************************************************************/
+/***	Values to be used as u32RadioStandard parameter                   ***/
+/***	for vRadio_Standard_Init API                               ***/
+/***	RADIO_STANDARD_ZIGBEE_REGULAR standard Zigbee Mode                ***/
+/***	RADIO_STANDARD_ZIGBEE_PROP_1 Zigbee mode with proprietary mode 1  ***/
+/***	Tx configuration (soft spread reduction)                          ***/
+/***	RADIO_STANDARD_ZIGBEE_PROP_2 Zigbee mode with proprietary mode 2  ***/
+/***	Tx configuration (more agressive spread reduction)                ***/
+/***	RADIO_STANDARD_ZIGBEE_REGULAR Zigbee Mode using LUT mode for AGC  ***/
+/***	control. Test only.                                               ***/
+/***	RADIO_STANDARD_ZIGBEE_PROP_1_LUT and _PROP_2_LUT LUT AGC control  ***/
+/***	and Tx mode1/2                                                    ***/
+/***	RADIO_STANDARD_BLE_1MB BLE 1 Mbps mode (for TX and RX)			  ***/
+/***	RADIO_STANDARD_BLE_2MB BLE 2 Mbps mode (for TX and RX)			  ***/
+/***	RADIO_STANDARD_BLE_RX1MB_TX2MB and RADIO_STANDARD_BLE_RX2MB_TX1MB ***/
+/***	are BLE configuration with different RX/TX bitrates               ***/
+/****************************************************************************/
+
+#define RADIO_STANDARD_ZIGBEE_REGULAR ((RX_DETECTOR_ONLY << 8) | (TX_REGULAR))
+#define RADIO_STANDARD_ZIGBEE_PROP_1  ((RX_DETECTOR_ONLY << 8) | (TX_PROP_1))
+#define RADIO_STANDARD_ZIGBEE_PROP_2  ((RX_DETECTOR_ONLY << 8) | (TX_PROP_2))
+#define RADIO_STANDARD_ZIGBEE_REGULAR_LUT ((RX_ENABLE_LUT << 8) | (TX_REGULAR))
+#define RADIO_STANDARD_ZIGBEE_PROP_1_LUT  ((RX_ENABLE_LUT << 8) | (TX_PROP_1))
+#define RADIO_STANDARD_ZIGBEE_PROP_2_LUT  ((RX_ENABLE_LUT << 8) | (TX_PROP_2))
+#define RADIO_STANDARD_BLE_1MB ((RX_BLE_1MB << 8) | (TX_BLE_1MB))
+#define RADIO_STANDARD_BLE_2MB ((RX_BLE_2MB << 8) | (TX_BLE_2MB))
+#define RADIO_STANDARD_BLE_RX1MB_TX2MB ((RX_BLE_1MB << 8) | (TX_BLE_2MB))
+#define RADIO_STANDARD_BLE_RX2MB_TX1MB ((RX_BLE_2MB << 8) | (TX_BLE_1MB))
+
+/****************************************************************************/
+
+/****************************************************************************/
+/*** radio driver types/macros/prototypes                                 ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***    Type definition for vRadio_SetChannelStandards function			  ***/
+/****************************************************************************/
+typedef enum
+{
+    E_RADIO_TX_MODE_STD    = TX_REGULAR,
+    E_RADIO_TX_MODE_PROP_1 = TX_PROP_1,
+    E_RADIO_TX_MODE_PROP_2 = TX_PROP_2,
+    E_RADIO_TX_MODE_RESET  = TX_UNDEFINED
+} teRadioTxMode;
+
+/* RSSI reported by XCV in 1/4 dBm step */
+#define RADIO_MAX_RSSI_REPORT       40
+#define RADIO_MIN_RSSI_REPORT     -400
+
+/****************************************************************************/
+/*** radio driver API prototypes                                          ***/
+/****************************************************************************/
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_RadioInit
+ *
+ * DESCRIPTION:
+ * Radio driver initialisation function.
+ *
+ * PARAMETERS:
+ * uint32_t u32RadioMode: use one of the defined values described above
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+void vRadio_RadioInit(uint32_t u32RadioMode);
+/****************************************************************************
+ *
+ * NAME:       vRadio_RadioDeInit
+ *
+ * DESCRIPTION:
+ * Radio driver de-initialisation function.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+void vRadio_RadioDeInit(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_Standard_Init
+ *
+ * DESCRIPTION:
+ * Set radio parameters for the specified standard in the corresponding
+ * parameter bank of the radio HW block. There is one bank of each radio standard.
+ *
+ * PARAMETERS:
+ * uint32_t u32RadioStandard: use one of the defined values described above
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+void vRadio_Standard_Init(uint32_t u32RadioStandard);
+
+/****************************************************************************
+ *
+ * NAME:       u8Radio_GetEDfromRSSI
+ *
+ * DESCRIPTION:
+ * Returns Energy Detect value calculated from RSSI value
+ *
+ * PARAMETERS:
+ * int16_t i16RSSIval: RSSI value expressed in fourth of dBm (2'complement signed value)
+ *
+ * RETURNS:
+ * uint8_t ED in [0..255] range
+ *
+ ****************************************************************************/
+uint8_t u8Radio_GetEDfromRSSI(int16_t i16RSSIval);
+
+/****************************************************************************
+ *
+ * NAME:       u32Radio_RadioModesAvailable
+ *
+ * DESCRIPTION:
+ * Returns returns bit combination of available radio modes (1 for LOPOWER and/or 2 for HIGHPOWER)
+ * Currently only LOPOWER is implemented so always returns 1
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * uint32_t bit combination of radio modes
+ *
+ ****************************************************************************/
+uint32_t u32Radio_RadioModesAvailable(void);
+
+/****************************************************************************
+ *
+ * NAME:       u32Radio_RadioGetVersion
+ *
+ * DESCRIPTION:
+ * Returns radio driver version. This function can be used to check the version
+ * of the radio driver embedded in the library used for the link against the value
+ * defined above as RADIO_VERSION and detected possible mismatch between this
+ * header file and the driver version itself.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * uint32_t radio version
+ *
+ ****************************************************************************/
+uint32_t u32Radio_RadioGetVersion(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_Temp_Update
+ *
+ * DESCRIPTION:
+ * Provides the radio driver with the current temperature value.
+ *
+ * PARAMETERS:
+ * int16_t s16Temp: Temperature expressed in half of degre C (2'complement 16 bit value)
+ * 					For example 40 (or 0x28) for 20 degre Celsius
+ * 					or -40 (0xFFD8) for -20 degre Celsius
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+void vRadio_Temp_Update(int16_t s16Temp);
+
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_ConfigCalFlashUsage
+ *
+ * DESCRIPTION:
+ * Configure usage of flash record for radio calibration parameter.
+ * For example, this function can be used to temporarily disable write of
+ * calibration results in flash if there is a risk that the power can be removed
+ * during next radio init (e.g. energy harvesting application).
+ *
+ * PARAMETERS:
+ * bool bWriteToFlash: Allows radio_init/recal to write calibration results from flash.
+ * 					   If set to false, after new calibration, new results will not be
+ * 					   saved in flash for future re-use.
+ * 					   Default value is true.
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+void vRadio_ConfigCalFlashUsage(bool bWriteToFlash);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_Save_ApplicationData_Retention
+ *
+ * DESCRIPTION:
+ * Save application data into radio retention registers.
+ *
+ * PARAMETERS:
+ * uint8_t *u8AppliData: Table of 8bit values to be stored in retention registers
+ * 						 It is the responsibility of the application that data
+ * 						 are compacted in the table as a bit steam of maximum
+ * 						 ADD_DATA_RET_NB_BITS bits over APP_DATA_RET_NB_BYTES bytes
+ * 						 See above for ADD_DATA_RET_NB_BITS and APP_DATA_RET_NB_BYTES
+ * 						 values.
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+void vRadio_Save_ApplicationData_Retention(uint8_t *u8AppliData);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_Restore_Retention_ApplicationData
+ *
+ * DESCRIPTION:
+ * Save application data into radio retention registers.
+ *
+ * PARAMETERS:
+ * uint8_t *u8AppliData: Table of 8bit values to restore the table saved using
+ * 						 vRadio_Save_ApplicationData_Retention API
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+void vRadio_Restore_Retention_ApplicationData( uint8_t *u8AppliData);
+
+
+
+
+
+/****************************************************************************/
+/***        Public Functions (to be called by LL or MAC layer)            ***/
+/****************************************************************************/
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_Recal
+ *
+ * DESCRIPTION:
+ * This function is to be called when it is possible (from the LL or MAC perspective)
+ * to re-calibrate the radio. This function will check the latest temperature
+ * value provided by the last vRadio_Temp_Update API, and if the difference between
+ * this temperature and the temperature used for the latest calibration is higher than
+ * 40 degre C, a new calibration is done and this new temperature is saved as the
+ * temperature of the latest calibration.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None
+ *
+ ****************************************************************************/
+bool vRadio_Recal(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_RFT1778_bad_crc
+ *
+ * DESCRIPTION:
+ * This function is to be called by the ZB MAC when a CRC error has been detected.
+ * This avoid lockup of the radio in some cases.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * int : 1 if lockup condition has been detected and unlocked, 0 otherwise.
+ *
+ ****************************************************************************/
+int vRadio_RFT1778_bad_crc(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_AD_control
+ *
+ * DESCRIPTION:
+ * When RX antenna diversity is enabled,  function is to be called by the ZB MAC
+ * when PRE_STATE_1 state is reached.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_AD_control(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_LockupCheckAndAbortRadio
+ *
+ * DESCRIPTION:
+ * This function is to be called by the BLE LL when an error has been detected.
+ * This avoid lockup of the radio in some cases.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_LockupCheckAndAbortRadio(void);
+
+/****************************************************************************
+ *
+ * The next 7 APIs are dedicated to the MAC layer for its internal needs.
+ *
+ ****************************************************************************/
+/* There are 3 sets of operating 'standards', which affects the frequency
+   response of the radio:
+     normal
+     proprietary 1
+     proprietary 2
+
+   For compliance it may be necessary to select different standards for
+   different channels, and this function allows that to be configured.
+   Note that this function has the AppApi prefix rather than the MMAC
+   prefix; we have traditionally provided customer-facing functions with
+   the AppApi prefix and this avoids a level of indirection via the shim
+   layer. */
+void vRadio_SetComplianceLimits(int8_t i8TxMaxPower,
+                                       int8_t i8TxMaxPowerCh26);
+void vRadio_SetChannelStandards(teRadioTxMode eNewTxMode,
+                                       teRadioTxMode eNewTxModeCh26);
+void vRadio_InitialiseRadioStandard(void);
+void vRadio_UpdateRadioStandard(uint8_t u8NewChannel);
+void vRadio_SetChannelAndPower(uint8_t u8Channel, int8_t i8TxPower_dBm);
+int8_t i8Radio_GetTxPowerLevel_dBm(void);
+
+int16_t i16Radio_GetRSSI(uint32_t u32DurationSymbols,bool bAverage, uint8_t *u8antenna);
+int16_t i16Radio_GetNbRSSISync(void);
+int16_t i16Radio_GetNbRSSISyncCor(uint8_t u8rate);
+int8_t i8Radio_GetLastPacketRSSI();
+int16_t i16Radio_BoundRssiValue(int16_t value);
+
+/****************************************************************************
+ *
+ * These APIs are dedicated to the BLE LL to reset BLE HW block if needed
+ * and to execute patch at end of RX process
+ *
+ ****************************************************************************/
+
+/* BLE reset APIs */
+void vRadio_BLE_ResetOn(void);
+void vRadio_BLE_ResetOff(void);
+
+void vRadio_remove_patch_ISR(void);
+void vRadio_SingleRX_AgcReadyPatch(void);
+void vRadio_MultiRX_AgcReadyPatch(void);
+void vRadio_Enable_AgcReadyPatch(void);
+void vRadio_Disable_AgcReadyPatch(void);
+
+
+
+/****************************************************************************
+ *
+ * The next 2 APIs are for temporary usage and are to be removed when XTAL init
+ * will be put out of radio driver
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_SkipXTALInit
+ *
+ * DESCRIPTION:
+ * Set an internal flag in the radio driver to skip any XTAL 32MHz handling
+ * by the radio driver. With this flag set, the radio driver does not start
+ * nor Trim the 32M XO.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_SkipXTALInit(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_EnableXTALInit
+ *
+ * DESCRIPTION:
+ * Reset the internal flag in the radio driver used to skip any XTAL 32MHz handling
+ * by the radio driver. With this flag cleared, the radio driver checks if 32M XO is
+ * running and start it if not already started. It also trim the 32M XO.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_EnableXTALInit(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_ActivateXtal32MRadioBiasing
+ *
+ * DESCRIPTION:
+ * Reset Radio HW block and switch XTAL32M to radio biasing control.
+ * ASSUMES THAT XTAL32M IS ALREADY SETUP, TRIMMED AND RUNNING UNDER PMC BIASING
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_ActivateXtal32MRadioBiasing(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_DisableZBRadio
+ *
+ * DESCRIPTION:
+ * Disable ZB radio block.
+ * This API needs to be called before vRadio_RadioInit and vRadio_ActivateXtal32MRadioBiasing.
+ * When ZB radio block is disabled, it is not reset and clocks are not enabled for this
+ * HW block.
+ * ONLY ONE OF vRadio_DisableZBRadio or vRadio_DisableBLERadio can be called.
+ * IF BOTH APIS ARE CALLED, ONLY THE FIRST ONE HAS EFFECT.
+ * IT CANNOT BE REVERSED. NEED HW RESET TO USE ZB RADIO AGAIN.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_DisableZBRadio(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_DisableBLERadio
+ *
+ * DESCRIPTION:
+ * Disable BLE radio block.
+ * This API needs to be called before vRadio_RadioInit and vRadio_ActivateXtal32MRadioBiasing.
+ * When BLEB radio block is disabled, clocks are not enabled for this HW block.
+ * ONLY ONE OF vRadio_DisableZBRadio or vRadio_DisableBLERadio can be called.
+ * IF BOTH APIS ARE CALLED, ONLY THE FIRST ONE HAS EFFECT.
+ * IT CANNOT BE REVERSED. NEED HW RESET TO USE BLE RADIO AGAIN.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_DisableBLERadio(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_EnableBLEFastTX
+ *
+ * DESCRIPTION:
+ * Enable keeping G1 and G2 on to give more time between RX and TX.
+ * On ES2MF it is also possible to keep PLL group using bKeepPll parameter.
+ *
+ * PARAMETERS:
+ * bool bKeepPll: when true, PLL group is kept active (ES2MF only, no effect
+ *                otherwise)
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_EnableBLEFastTX(bool bKeepPll);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_DisableBLEFastTX
+ *
+ * DESCRIPTION:
+ * Disable keeping G1 and G2 on to give more time between RX and TX.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_DisableBLEFastTX(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_Disable_DCO_DAC
+ *
+ * DESCRIPTION:
+ * Disable keeping DCO DAC always on. By default vRadio_ActivateXtal32MRadioBiasing
+ * and vRadio_RadioInit force DCO DAC to on state to ensure it is ready to operate
+ * at the very beginning of RX process. If no RX is foreseen before next powerdown or sleep
+ * DCO DAC can be disable to reduce power consumption.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_Disable_DCO_DAC(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_ZBtoBLE
+ *
+ * DESCRIPTION:
+ * Change some settings needed when switching from ZB to BLE.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_ZBtoBLE(void);
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_BLEtoZB
+ *
+ * DESCRIPTION:
+ * Change some settings needed when switching from BLE to ZB.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_BLEtoZB(void);
+
+/****************************************************************************
+ *
+ * NAME:       u16Radio_Get_Next_Recal_Duration
+ *
+ * DESCRIPTION:
+ * Returns estimate time duration of the next calibration. This estimate is
+ * based on the last temperature provided by the vRadio_Temp_Update,
+ * the temperature of the last calibration and the operations to do for this
+ * calibrations.
+ * If no calibration is needed or vRadio_RadioInit has not bee called before,
+ * the API returns 0. Otherwise it returns the estimated duration in us.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+uint32_t u32Radio_Get_Next_Recal_Duration(void);
+
+
+/****************************************************************************
+ *
+ * NAME:       vRadio_AntennaDiversityTxRxEnable
+ *
+ * DESCRIPTION:
+ * Enables Antenna Diversity for Tx and/or Rx.
+ *
+ * PARAMETERS:
+ * bool bRxEnabled: true to enable Rx AD, false to disable it
+ * bool bTxEnabled: true to enable Tx AD, false to disable it
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_AntennaDiversityTxRxEnable(bool bRxEnabled, bool bTxEnabled);
+/****************************************************************************
+ *
+ * NAME:       vRadio_AntennaDiversityConfigure
+ *
+ * DESCRIPTION:
+ * Configure some AD setings.
+ *
+ * PARAMETERS:
+ * uint16_t rssi_thr: RSSI threshold to switch antenna (10bit fourth dBm in two complement)
+ *                    Default value is 0x278 (-98dBm)
+ * uint8_t rx_timer: Timer before to check received power again (4us steps, 4bits)
+ *                   Default value is 0x8 (32us)
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_AntennaDiversityConfigure(uint16_t rssi_thr, uint8_t rx_timer);
+/****************************************************************************
+ *
+ * NAME:       vRadio_AntennaDiversitySwitch
+ *
+ * DESCRIPTION:
+ * Toggle antenna selection.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_AntennaDiversitySwitch(void);
+/****************************************************************************
+ *
+ * NAME:       u8Radio_AntennaDiversityStatus
+ *
+ * DESCRIPTION:
+ * Returns current selected antenna.
+ *
+ * PARAMETERS:
+ * None
+ *
+ * RETURNS:
+ * Selected antenna (0 or 1) on uint8_t .
+ *
+ ****************************************************************************/
+uint8_t u8Radio_AntennaDiversityStatus(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RADIO_H_ */

third_party/nxp/JN5189/Radio_JN5189/Include/radio_jn518x.h

@@ -0,0 +1,72 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+* SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __RADIO_JN518X_H_
+#define __RADIO_JN518X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "radio.h"
+
+/****************************************************************************/
+/***        Macro/Type Definitions                                        ***/
+/****************************************************************************/
+
+#define RADIO_JN518X_VERSION RADIO_VERSION
+#define RADIO_JN5189_MAX_RSSI_REPORT RADIO_MAX_RSSI_REPORT
+#define RADIO_JN5189_MIN_RSSI_REPORT RADIO_MIN_RSSI_REPORT
+
+#define vRadio_Jn518x_RadioInit vRadio_RadioInit
+#define vRadio_Jn518x_RadioDeInit vRadio_RadioDeInit
+#define vRadio_Jn518x_Standard_Init vRadio_Standard_Init
+#define u8Radio_Jn518x_GetEDfromRSSI u8Radio_GetEDfromRSSI
+#define u32Radio_Jn518x_RadioModesAvailable u32Radio_RadioModesAvailable
+#define u32Radio_Jn518x_RadioGetVersion u32Radio_RadioGetVersion
+#define vRadio_JN518x_Temp_Update vRadio_Temp_Update
+#define vRadio_JN518x_ConfigCalFlashUsage vRadio_ConfigCalFlashUsage
+#define vRadio_jn518x_Save_ApplicationData_Retention vRadio_Save_ApplicationData_Retention
+#define vRadio_jn518x_Restore_Retention_ApplicationData vRadio_Restore_Retention_ApplicationData
+#define vRadio_JN518xRecal vRadio_Recal
+#define vRadio_Jn518x_RFT1778_bad_crc vRadio_RFT1778_bad_crc
+#define vRadio_Jn518x_LockupCheckAndAbortRadio vRadio_LockupCheckAndAbortRadio
+#define i16Radio_Jn518x_GetRSSI i16Radio_GetRSSI
+#define i16Radio_Jn518x_GetNbRSSISync i16Radio_GetNbRSSISync
+#define i16Radio_Jn518x_GetNbRSSISyncCor i16Radio_GetNbRSSISyncCor
+#define i8Radio_Jn518x_GetLastPacketRSSI i8Radio_GetLastPacketRSSI
+#define i16Radio_Jn518x_BoundRssiValue i16Radio_BoundRssiValue
+#define vRadio_Jn518x_BLE_ResetOn vRadio_BLE_ResetOn
+#define vRadio_Jn518x_BLE_ResetOff vRadio_BLE_ResetOff
+#define vRadio_Jn518x_remove_patch_ISR vRadio_remove_patch_ISR
+#define vRadio_Jn518x_SingleRX_AgcReadyPatch vRadio_SingleRX_AgcReadyPatch
+#define vRadio_Jn518x_MultiRX_AgcReadyPatch vRadio_MultiRX_AgcReadyPatch
+#define vRadio_Jn518x_Enable_AgcReadyPatch vRadio_Enable_AgcReadyPatch;
+#define vRadio_Jn518x_Disable_AgcReadyPatch vRadio_Disable_AgcReadyPatch
+#define vRadio_Jn518x_SkipXTALInit vRadio_SkipXTALInit
+#define vRadio_Jn518x_EnableXTALInit vRadio_EnableXTALInit
+#define vRadio_jn518x_ActivateXtal32MRadioBiasing vRadio_ActivateXtal32MRadioBiasing
+#define vRadio_jn518x_DisableZBRadio vRadio_DisableZBRadio
+#define vRadio_jn518x_DisableBLERadio vRadio_DisableBLERadio
+#define vRadio_jn518x_EnableBLEFastTX vRadio_EnableBLEFastTX
+#define vRadio_jn518x_DisableBLEFastTX vRadio_DisableBLEFastTX
+#define vRadio_jn518x_ZBtoBLE vRadio_ZBtoBLE
+#define vRadio_jn518x_BLEtoZB vRadio_BLEtoZB
+#define u32Radio_JN518x_Get_Next_Recal_Duration u32Radio_Get_Next_Recal_Duration
+#define vRadio_Jn518x_AntennaDiversityTxRxEnable vRadio_AntennaDiversityTxRxEnable
+#define vRadio_Jn518x_AntennaDiversityConfigure vRadio_AntennaDiversityConfigure
+#define vRadio_Jn518x_AntennaDiversitySwitch vRadio_AntennaDiversitySwitch
+#define u8Radio_Jn518x_AntennaDiversityStatus u8Radio_AntennaDiversityStatus
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RADIO_JN518X_H_ */

third_party/nxp/JN5189/Radio_JN5189/Include/system_jn518x.h

@@ -0,0 +1,55 @@
+#ifndef SYSTEM_JN518X_H
+#define SYSTEM_JN518X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+
+/* *** JN518x *** */
+
+/** \brief  Exceptions and Interrupts vectors structure.
+ */
+
+typedef struct
+{
+   uint32_t pExceptions[16]; /*!< System exceptions vectors */
+   uint32_t pIsr[240];       /*!< User interrupt vectors    */
+} VectorTable_Type;
+
+
+extern const uint32_t  XSW_VTOR_BASE        ;
+
+#define JN518X_ISR_TABLE   ((VectorTable_Type *)     XSW_VTOR_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_JN518X_H */

third_party/nxp/JN5189/Radio_JN5189/makefile_Radio

@@ -0,0 +1,52 @@
+AR                              = arm-none-eabi-ar
+CCAS                            = arm-none-eabi-as
+CPP                             = arm-none-eabi-cpp
+CC                              = arm-none-eabi-gcc
+CXX                             = arm-none-eabi-g++
+LD                              = arm-none-eabi-ld
+STRIP                           = arm-none-eabi-strip
+NM                              = arm-none-eabi-nm
+RANLIB                          = arm-none-eabi-ranlib
+OBJCOPY                         = arm-none-eabi-objcopy
+
+ECHO                            := @echo
+RM_F                            := rm -f
+
+CFLAGS = -DCPU_JN518X \
+         -DCPU_JN518X_REV=2 \
+         -DJENNIC_CHIP_FAMILY_JN518x \
+         -DJENNIC_CHIP_FAMILY_NAME=_JN518x \
+         -DCORE_M4 \
+         -Wno-unknown-pragmas \
+         -Wno-sign-compare \
+         -Wno-unused-function \
+         -Wno-unused-parameter \
+         -Wno-empty-body \
+         -Iinclude \
+         -fdata-sections               \
+         -ffunction-sections           \
+         -Os                           \
+         -g                            \
+         -mcpu=cortex-m4 \
+         -mfloat-abi=soft \
+         -mthumb
+    
+INCLUDES = -I../drivers \
+           -I../uMac/Include \
+           -I../JennicCommon/Include \
+           -I../MicroSpecific/Include \
+           -I../MiniMac/Include \
+           -I../MiniMac/mMac/Include \
+           -I../MiniMac/mMac/Source \
+           -I../Radio_JN5189/Include \
+           -I../../CMSIS/Include \
+           -I../rom_apis \
+           -I../
+
+all:
+		$(CC) $(CFLAGS) $(INCLUDES) -c Source/radio_jn518x.c -o Source/radio_jn518x.o
+		$(AR) rcs ../libraries/libRadio_jn518x.a Source/radio_jn518x.o
+
+clean:
+	$(ECHO) "  CLEAN"
+	@$(RM_F) -r *.o *.a

third_party/nxp/JN5189/app/app_ota.h

@@ -0,0 +1,378 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2017 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef _APP_OTA_H
+#define _APP_OTA_H
+
+/*!=================================================================================================
+\file       app_ota.h
+\brief      This is the header file for the ota module
+==================================================================================================*/
+
+/*==================================================================================================
+Include Files
+==================================================================================================*/
+#include <openthread/coap.h>
+#include <openthread/thread.h>
+/*==================================================================================================
+Public macros
+==================================================================================================*/
+#define OTA_CLIENT_URI_PATH                     "otaclient"
+#define OTA_SERVER_URI_PATH                     "otaserver"
+
+#ifndef OTA_USE_NWK_DATA
+    #define OTA_USE_NWK_DATA                    FALSE
+#endif
+
+#if OTA_USE_NWK_DATA
+    #define GET_OTA_ADDRESS(otInst)             otThreadGetRloc(otInst)
+#else
+    #define GET_OTA_ADDRESS(otInst)             otThreadGetMeshLocalEid(otInst)
+#endif
+
+/* ota params */
+#define gOtaFileIdentifierNo_c                  0x0BEEF11E
+#define gOtaManufacturerCode_c                  0x04, 0x10
+#define gOtaManufacturerCodeNo_c                0x1004
+#define gOtaCurrentImageType_c                  0x00, 0x00
+#define gOtaCurrentImageTypeNo_c                0x0000
+#define gOtaCurrentFileVersion_c                0x05, 0x40, 0x03, 0x40
+#define gOtaCurrentFileVersionNo_c              0x40034005
+#define gOtaHardwareVersion_c                   0x21, 0x24
+#define gOtaHardwareVersionNo_c                 0x2421
+
+#define gOtaMaxBlockDataSize_c                  64 /* 60 bytes */
+
+#define gOtaServer_MaxSimultaneousClients_c     0x0A
+
+/*==================================================================================================
+Public type definitions
+==================================================================================================*/
+
+/* ota commands */
+typedef enum
+{
+    gOtaCmd_ImageNotify_c          =       0x00,
+    gOtaCmd_QueryImageReq_c,
+    gOtaCmd_QueryImageRsp_c,
+    gOtaCmd_BlockReq_c,
+    gOtaCmd_BlockRsp_c,
+    gOtaCmd_UpgradeEndReq_c,
+    gOtaCmd_UpgradeEndRsp_c,
+    gOtaCmd_ServerDiscovery_c,
+    gOtaCmd_Invalid_c              =       0xFF
+} gOtaCmd_t;
+
+/*! Ota status */
+typedef enum otaStatus_tag
+{
+    gOtaStatus_Success_c          = 0x00,
+    gOtaStatus_Failed_c           = 0x01,
+    gOtaStatus_InvalidInstance_c  = 0x02,
+    gOtaStatus_InvalidParam_c     = 0x03,
+    gOtaStatus_NotPermitted_c     = 0x04,
+    gOtaStatus_NotStarted_c       = 0x05,
+    gOtaStatus_NoMem_c            = 0x06,
+    gOtaStatus_UnsupportedAttr_c  = 0x07,
+    gOtaStatus_EmptyEntry_c       = 0x08,
+    gOtaStatus_InvalidValue_c     = 0x09,
+    gOtaStatus_AlreadyStarted_c   = 0x0A,
+    gOtaStatus_NoTimers_c         = 0x0B,
+    gOtaStatus_NoUdpSocket_c      = 0x0C,
+    gOtaStatus_EntryNotFound_c    = 0xFF
+} otaStatus_t;
+
+/* OTA File Status */
+typedef enum otaFileStatus_tag
+{
+    gOtaFileStatus_Success_c          = 0x00, /* Success Operation */
+    gOtaFileStatus_NotAuthorized_c    = 0x7E, /* Server is not authorized to upgrade the client. */
+    gOtaFileStatus_Abort_c            = 0x95, /* Failed case when a client or a server decides to abort the upgrade process. */
+    gOtaFileStatus_InvalidImage_c     = 0x96, /* Invalid OTA upgrade image. */
+    gOtaFileStatus_ServerBusy_c       = 0x97, /* Server is busy, retry later. */
+    gOtaFileStatus_NoImageAvailable_c = 0x98, /* No OTA upgrade image available for a particular client. */
+    gOtaFileStatus_ImageTooLarge_c    = 0x99, /* Received OTA image is larger than the available storage space. */
+    gOtaFileStatus_InvalidOperation_c = 0x9A, /* Client encountered an invalid operation error. */
+    gOtaFileStatus_InvalidParameter_c = 0x9B, /* Client encountered an invalid parameter error. */
+    gOtaFileStatus_ExtFlashError_c    = 0x9C, /* Client encountered an external flash error. */
+    gOtaFileStatus_ClientError_c      = 0x9D /* Generic client error. */
+} otaFileStatus_t;
+
+typedef enum otaTransferType_tag
+{
+    gOtaUnicast_c = 0x00,
+    gOtaMulticast_c
+} otaTransferType_t;
+
+/* ota command format */
+typedef struct otaCommand_tag
+{
+    uint8_t commandId;
+    uint8_t pPayload[1];
+} otaCommand_t;
+
+/* ota image notify command format*/
+typedef struct otaServerCmd_ImageNotify_tag
+{
+    uint8_t commandId;
+    uint8_t transferType;
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+    uint8_t imageSize[4];
+    uint8_t fileSize[4];
+    uint8_t fileVersion[4];
+    uint8_t serverDownloadPort[2];
+    uint8_t fragmentSize[2];
+} otaServerCmd_ImageNotify_t;
+
+/* ota query image req command format*/
+typedef struct otaCmd_QueryImageReq_tag
+{
+    uint8_t commandId;
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+    uint8_t fileVersion[4];
+    uint8_t hardwareVersion[2];
+} otaCmd_QueryImageReq_t;
+
+/* ota query image rsp - success */
+typedef struct otaCmd_QueryImageRspSuccess_tag
+{
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+    uint8_t fileVersion[4];
+    uint8_t fileSize[4];
+    uint8_t serverDownloadPort[2];
+} otaCmd_QueryImageRspSuccess_t;
+
+/* ota query image rsp - wait */
+typedef struct otaCmd_QueryImageRspWait_tag
+{
+    uint8_t currentTime[4];
+    uint8_t requestTime[4];
+} otaCmd_QueryImageRspWait_t;
+
+/* ota query image rsp command format*/
+typedef struct otaCmd_QueryImageRsp_tag
+{
+    uint8_t commandId;
+    uint8_t status;
+    union
+    {
+        otaCmd_QueryImageRspSuccess_t success;
+        otaCmd_QueryImageRspWait_t wait;
+    } data;
+} otaCmd_QueryImageRsp_t;
+
+/* ota block req command format*/
+typedef struct otaCmd_BlockReq_tag
+{
+    uint8_t commandId;
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+    uint8_t fileVersion[4];
+    uint8_t fileOffset[4];
+    uint8_t maxDataSize;
+} otaCmd_BlockReq_t;
+
+/* ota block rsp - success */
+typedef struct otaCmd_BlockRspSuccess_tag
+{
+    uint8_t fileVersion[4];
+    uint8_t fileOffset[4];
+    uint8_t dataSize;
+    uint8_t pData[1];
+} otaCmd_BlockRspSuccess_t;
+
+/* ota block rsp - wait for data */
+typedef struct otaCmd_BlockRspWaitForData_tag
+{
+    uint8_t currentTime[4];
+    uint8_t requestTime[4];
+} otaCmd_BlockRspWaitForData_t;
+
+/* ota block rsp command format*/
+typedef struct otaCmd_BlockRsp_tag
+{
+    uint8_t commandId;
+    uint8_t status;
+    union
+    {
+        otaCmd_BlockRspSuccess_t success;
+        otaCmd_BlockRspWaitForData_t wait;
+    } data;
+} otaCmd_BlockRsp_t;
+
+/* ota upgrade end req command format*/
+typedef struct otaCmd_UpgradeEndReq_tag
+{
+    uint8_t commandId;
+    uint8_t status;
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+    uint8_t fileVersion[4];
+} otaCmd_UpgradeEndReq_t;
+
+/* ota upgrade end rsp - success */
+typedef struct otaCmd_UpgradeEndRspSuccess_tag
+{
+    uint8_t currentTime[4];     /* milliseconds */
+    uint8_t upgradeTime[4];     /* milliseconds */
+    uint8_t fileVersion[4];
+} otaCmd_UpgradeEndRspSuccess_t;
+
+/* ota upgrade end rsp - wait for data */
+typedef struct otaCmd_UpgradeEndRspWaitForData_tag
+{
+    uint8_t currentTime[4];
+    uint8_t requestTime[4];
+} otaCmd_UpgradeEndRspWaitForData_t;
+
+/* ota upgrade end rsp command format*/
+typedef struct otaCmd_UpgradeEndRsp_tag
+{
+    uint8_t commandId;
+    uint8_t status;
+    union
+    {
+        otaCmd_UpgradeEndRspSuccess_t success;
+        otaCmd_UpgradeEndRspWaitForData_t wait;
+    } data;
+} otaCmd_UpgradeEndRsp_t;
+
+/* ota upgrade server discovery command format */
+typedef struct otaCmd_ServerDiscovery_tag
+{
+    uint8_t commandId;
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+} otaCmd_ServerDiscovery_t;
+
+/* ota file header */
+typedef struct otaFileHeader_tag
+{
+    uint8_t fileIdentifier[4];
+    uint8_t headerVersion[2];
+    uint8_t headerLength[2];
+    uint8_t fieldControl[2];
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+    uint8_t fileVersion[4];
+    uint8_t stackVersion[2];
+    uint8_t headerString[32];
+    uint8_t totalImageSize[4];
+    uint8_t minHwVersion[2];
+    uint8_t maxHwVersion[2];
+} otaFileHeader_t;
+
+typedef struct otaFileSubElement_tag
+{
+    uint8_t id[2];
+    uint8_t length[4];
+} otaFileSubElement_t;
+
+/* OTA Server Serial Protocol */
+
+/* Image notify command format */
+typedef struct otaServer_ImageNotify_tag
+{
+    uint8_t deviceId[2];
+    uint8_t manufacturerCode[2];
+    uint8_t imageType[2];
+    uint8_t imageSize[4];
+    uint8_t fileSize[4];
+    uint8_t fileVersion[4];
+} otaServer_ImageNotify_t;
+
+/* OTA unicast and multicast finished percentage information structures */
+typedef struct otaServerUnicastClientEntry_tag
+{
+    uint16_t clientId;
+    uint8_t percentage;
+} otaServerUnicastClientEntry_t;
+
+typedef struct otaServerPercentageInfo_tag
+{
+	uint8_t otaType;
+	uint8_t multicastPercentage;
+	otaServerUnicastClientEntry_t unicastEntry[gOtaServer_MaxSimultaneousClients_c];
+} otaServerPercentageInfo_t;
+
+/* ota server operation mode */
+typedef enum
+{
+    gOtaServerOpMode_Reserved_c = 0,
+    gOtaServerOpMode_Standalone_c,           /* requires an external memory or a reserved region of internal MCU flash to keep the client image */
+    gOtaServerOpMode_Dongle_c,               /* without internal/external memory capacity */
+} otaServerOpMode_t;
+
+/*==================================================================================================
+Public global variables declarations
+==================================================================================================*/
+
+extern otCoapResource gOTA_CLIENT_URI_PATH;
+extern otCoapResource gOTA_SERVER_URI_PATH;
+
+/*==================================================================================================
+Public function prototypes
+==================================================================================================*/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!*************************************************************************************************
+\public
+\fn  otaStatus_t OtaServerInit(taskMsgQueue_t *pMsgQueue)
+\brief  Initialize OTA server application
+
+\param  [in]    pMsgQueue   Pointer to task message queue
+
+\return   otaStatus_t
+ ***************************************************************************************************/
+otaStatus_t OtaServerInit(otInstance *pOtInstance);
+
+/*!*************************************************************************************************
+\public
+\fn  otaStatus_t OtaServer_StartOta()
+\brief  Start OTA process
+
+\param  [in]    otaType        Type of OTA process (unicast or multicast)
+\param  [in]    pFilePath      Path to binary
+
+\return         otaStatus_t    Status of the operation
+ ***************************************************************************************************/
+otaStatus_t OtaServer_StartOta(uint8_t otaType, const char *pFilePath);
+
+/*!*************************************************************************************************
+\fn     otaResult_t OtaServer_StopOta(void)
+\brief  Process Stop OTA command received from an external application.
+
+\return         otaStatus_t    Status of the operation
+***************************************************************************************************/
+otaStatus_t OtaServer_StopOta(void);
+
+/*!*************************************************************************************************
+\fn     void OtaServer_CheckTime(void)
+\brief  This function is used to check if a timer callback for OTA needs to be called.
+***************************************************************************************************/
+void OtaServer_CheckTime(void);
+
+/*!*************************************************************************************************
+\fn     void OtaServer_GetOtaStatus(otaServerPercentageInfo_t *pData)
+\brief  This function is used to check the status of the OTA transfer.
+
+\param  [in]    pData        Pointer to output structure
+***************************************************************************************************/
+void OtaServer_GetOtaStatus(otaServerPercentageInfo_t *pData);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*================================================================================================*/
+#endif  /*  _APP_OTA_H */

third_party/nxp/JN5189/app/network_utils.c

@@ -0,0 +1,240 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2017 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*==================================================================================================
+Include Files
+==================================================================================================*/
+
+#include <string.h>
+
+#include "network_utils.h"
+
+#include <openthread/ip6.h>
+
+/*==================================================================================================
+Private macros
+==================================================================================================*/
+
+/*==================================================================================================
+Private type definitions
+==================================================================================================*/
+
+/*==================================================================================================
+Private prototypes
+==================================================================================================*/
+
+/*==================================================================================================
+Private global variables declarations
+==================================================================================================*/
+
+/*==================================================================================================
+Public global variables declarations
+==================================================================================================*/
+
+/* RAM global addresses - updated when the device join the network */
+otIp6Address in6addr_linklocal_allthreadnodes = {0};
+otIp6Address in6addr_realmlocal_allthreadnodes = {0};
+otIp6Address in6addr_realmlocal_threadleaderanycast = {0};
+
+/*==================================================================================================
+Public functions
+==================================================================================================*/
+void NWKU_MemCpyReverseOrder(void* pDst, void* pSrc, uint32_t cBytes)
+{
+    if(cBytes)
+    {
+        pDst = (uint8_t *)pDst + (uint32_t)(cBytes - 1);
+
+        while (cBytes)
+        {
+            *((uint8_t *)pDst) = *((uint8_t *)pSrc);
+            pDst = (uint8_t *)pDst-1;
+            pSrc = (uint8_t *)pSrc+1;
+            cBytes--;
+        }
+    }
+}
+
+/*!*************************************************************************************************
+\fn     bool_t NWKU_GetBit(uint32_t bitNr, uint8_t *pArray)
+\brief  This function returns the value of a bit in an array.
+
+\param  [in]    bitNr           bit number in the whole array
+\param  [in]    pArray          pointer to the start of the array
+
+\retval         TRUE            if the bit is set
+\retval         FALSE           if the bit is not set
+***************************************************************************************************/
+bool_t NWKU_GetBit
+(
+    uint32_t bitNr,
+    uint8_t *pArray
+)
+{
+    return ((pArray[bitNr / 8] & (1 << (bitNr % 8))) ? true : false);
+}
+
+/*!*************************************************************************************************
+\fn     void NWKU_ClearBit(uint32_t bitNr, uint8_t* pArray)
+\brief  This function clears a bit in an array.
+
+\param  [in]    bitNr           bit number in the whole array
+\param  [in]    pArray          pointer to the start of the array
+***************************************************************************************************/
+void NWKU_ClearBit
+(
+    uint32_t bitNr,
+    uint8_t *pArray
+)
+{
+    pArray[bitNr / 8] &= ~(1 << (bitNr % 8));
+}
+
+/*!*************************************************************************************************
+\fn     void NWKU_SetBit(uint32_t bitNr, uint8_t* pArray)
+\brief  This function sets a bit in an array.
+
+\param  [in]    bitNr           bit number in the whole array
+\param  [in]    pArray          pointer to the start of the array
+***************************************************************************************************/
+void NWKU_SetBit
+(
+    uint32_t bitNr,
+    uint8_t *pArray
+)
+{
+    pArray[bitNr / 8] |= (1 << (bitNr % 8));
+}
+
+/*!*************************************************************************************************
+\fn     uint32_t NWKU_GetFirstBitValueInRange(uint8_t* pArray, uint32_t lowBitNr, uint32_t
+        highBitNr, bool_t bitValue)
+\brief  This function returns the first bit with value=bitValue in a range in the array.
+
+\param  [in]    pArray          pointer to the start of the array
+\param  [in]    lowBitNr        starting bit number
+\param  [in]    highBitNr       ending bit number
+\param  [in]    bitValue        bit value
+
+\return         uint32_t        bit number
+***************************************************************************************************/
+uint32_t NWKU_GetFirstBitValueInRange
+(
+    uint8_t *pArray,
+    uint32_t lowBitNr,
+    uint32_t highBitNr,
+    bool_t bitValue
+)
+{
+    for (; lowBitNr < highBitNr; lowBitNr++)
+    {
+        if (bitValue == NWKU_GetBit(lowBitNr, pArray))
+        {
+            return lowBitNr;
+        }
+    }
+
+    return ((uint32_t) - 1); // invalid
+}
+
+/*!*************************************************************************************************
+\fn     uint32_t getFirstBitValue(uint8_t* pArray, uint32_t arrayBytes, bool_t bitValue)
+\brief  This function returns the index of the first bit with value=bitValue.
+
+\param  [in]    pArray          pointer to the start of the array
+\param  [in]    arrayBytes      number of bytes in the array
+\param  [in]    bitValue        bit value
+
+\return         uint32_t        bit value
+***************************************************************************************************/
+uint32_t NWKU_GetFirstBitValue
+(
+    uint8_t *pArray,
+    uint32_t arrayBytes,
+    bool_t bitValue
+)
+{
+    return NWKU_GetFirstBitValueInRange(pArray, 0, (arrayBytes * 8), bitValue);
+}
+
+/*!*************************************************************************************************
+\fn    otIp6Address *NWKU_GetSpecificMcastAddr(otInstance *pOtInstance, thrMcastAllThrNodes_t type)
+\brief This function is used to get a specific multicast address (Mesh Local All nodes multicast or
+       link local All nodes multicast)
+
+\param [in]    pOtInstance         Pointer to the OpenThread instance
+\param [in]    type                Ip address type: gMcastLLAddrAllThrNodes_c, gMcastMLAddrAllThrNodes_c
+
+\retval        otIp6Address        Pointer to requested multicast address
+***************************************************************************************************/
+
+otIp6Address *NWKU_GetSpecificMcastAddr
+(
+    otInstance *pOtInstance,
+    thrMcastAllThrNodes_t type
+)
+{
+    otIp6Address *pAddr = NULL;
+    const otNetifMulticastAddress *pMCastAddr = otIp6GetMulticastAddresses(pOtInstance);
+
+    while(pMCastAddr != NULL)
+    {
+        if((type == gMcastLLAddrAllThrNodes_c) && (pMCastAddr->mAddress.mFields.m8[1] == 0x32))
+        {
+            pAddr = (otIp6Address *)&pMCastAddr->mAddress;
+            break;
+        }
+        else if((type == gMcastMLAddrAllThrNodes_c) && (pMCastAddr->mAddress.mFields.m8[1] == 0x33))
+        {
+            pAddr = (otIp6Address *)&pMCastAddr->mAddress;
+            break;
+        }
+
+        pMCastAddr = pMCastAddr->mNext;
+    }
+
+    return pAddr;
+}
+
+/*!*************************************************************************************************
+\fn     void APP_OtSetMulticastAddresses(otInstance *pOtInstance)
+\brief  This function is used to set the multicast addresses from the stack for application usage.
+
+\param  [in]    pOtInstance      Pointer to OpenThread instance
+
+\return         NONE
+***************************************************************************************************/
+void NWKU_OtSetMulticastAddresses
+(
+    otInstance *pOtInstance
+)
+{
+    otIp6Address *pAddr = NULL;
+
+    pAddr = NWKU_GetSpecificMcastAddr(pOtInstance, gMcastLLAddrAllThrNodes_c);
+
+    if(pAddr != NULL)
+    {
+        memcpy(&in6addr_linklocal_allthreadnodes, pAddr, sizeof(otIp6Address));
+    }
+
+    pAddr = NWKU_GetSpecificMcastAddr(pOtInstance, gMcastMLAddrAllThrNodes_c);
+
+    if(pAddr != NULL)
+    {
+    	memcpy(&in6addr_realmlocal_allthreadnodes, pAddr, sizeof(otIp6Address));
+    }
+}
+
+/*==================================================================================================
+Private functions
+==================================================================================================*/
+
+/*==================================================================================================
+Private debug functions
+==================================================================================================*/

third_party/nxp/JN5189/app/network_utils.h

@@ -0,0 +1,134 @@
+/*! *********************************************************************************
+ * \defgroup NUT  Thread Network Utilities Interface
+ * @{
+ ***********************************************************************************/
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2017 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef _NETWORK_UTILS_H
+#define _NETWORK_UTILS_H
+
+/*!
+\file       network_utils.h
+\brief      This is a header file for the Network Utils module.
+*/
+
+/*==================================================================================================
+Include Files
+==================================================================================================*/
+#include <openthread/ip6.h>
+
+typedef bool bool_t;
+
+/*! Macro for IP address copy */
+#define IP_AddrCopy(dst, src) \
+        (dst)->m32[0] = (src)->m32[0]; \
+        (dst)->m32[1] = (src)->m32[1]; \
+        (dst)->m32[2] = (src)->m32[2]; \
+        (dst)->m32[3] = (src)->m32[3];
+
+/*! Macro for IPV6 address comparison */
+#define IP_IsAddrEqual(addr1, addr2) \
+        (((addr1)->m32[0] == (addr2)->m32[0]) && \
+         ((addr1)->m32[1] == (addr2)->m32[1]) && \
+         ((addr1)->m32[2] == (addr2)->m32[2]) && \
+         ((addr1)->m32[3] == (addr2)->m32[3]))
+
+/* RAM global addresses - updated when the device join the network */
+extern otIp6Address in6addr_linklocal_allthreadnodes;
+extern otIp6Address in6addr_realmlocal_allthreadnodes;
+extern otIp6Address in6addr_realmlocal_threadleaderanycast;
+
+/*==================================================================================================
+Public type definitions
+==================================================================================================*/
+/*! Multicast all thread nodes */
+typedef enum thrMcastAllThrNodes_tag
+{
+    gMcastLLAddrAllThrNodes_c,  /*!< Multicast link local - all thread nodes */
+    gMcastMLAddrAllThrNodes_c,  /*!< Multicast mesh local - all thread nodes */
+} thrMcastAllThrNodes_t;
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!*************************************************************************************************
+\fn    otIp6Address *NWKU_GetSpecificMcastAddr(otInstance *pOtInstance, thrMcastAllThrNodes_t type)
+\brief This function is used to get a specific multicast address (Mesh Local All nodes multicast or
+       link local All nodes multicast)
+
+\param [in]    pOtInstance         Pointer to the OpenThread instance
+\param [in]    type                Ip address type: gMcastLLAddrAllThrNodes_c, gMcastMLAddrAllThrNodes_c
+
+\retval        otIp6Address        Pointer to requested multicast address
+***************************************************************************************************/
+otIp6Address *NWKU_GetSpecificMcastAddr(otInstance *pOtInstance, thrMcastAllThrNodes_t type);
+
+void NWKU_MemCpyReverseOrder(void* pDst, void* pSrc, uint32_t cBytes);
+
+/*!*************************************************************************************************
+\fn     uint32_t NWKU_GetFirstBitValueInRange(uint8_t* pArray, uint32_t lowBitNr, uint32_t
+        highBitNr, bool_t bitValue)
+\brief  This function returns the first bit with value=bitValue in a range in the array.
+
+\param  [in]    pArray          pointer to the start of the array
+\param  [in]    lowBitNr        starting bit number
+\param  [in]    highBitNr       ending bit number
+\param  [in]    bitValue        bit value
+
+\return         uint32_t        bit number
+***************************************************************************************************/
+uint32_t NWKU_GetFirstBitValueInRange(uint8_t *pArray, uint32_t lowBitNr, uint32_t highBitNr, bool_t bitValue);
+
+/*!*************************************************************************************************
+\fn     void NWKU_ClearBit(uint32_t bitNr, uint8_t* pArray)
+\brief  This function clears a bit in an array.
+
+\param  [in]    bitNr           bit number in the whole array
+\param  [in]    pArray          pointer to the start of the array
+***************************************************************************************************/
+void NWKU_ClearBit(uint32_t bitNr, uint8_t *pArray);
+
+/*!*************************************************************************************************
+\fn     void NWKU_SetBit(uint32_t bitNr, uint8_t* pArray)
+\brief  This function sets a bit in an array.
+
+\param  [in]    bitNr           bit number in the whole array
+\param  [in]    pArray          pointer to the start of the array
+***************************************************************************************************/
+void NWKU_SetBit(uint32_t bitNr, uint8_t *pArray);
+
+/*!*************************************************************************************************
+\fn     uint32_t getFirstBitValue(uint8_t* pArray, uint32_t arrayBytes, bool_t bitValue)
+\brief  This function returns the index of the first bit with value=bitValue.
+
+\param  [in]    pArray          pointer to the start of the array
+\param  [in]    arrayBytes      number of bytes in the array
+\param  [in]    bitValue        bit value
+
+\return         uint32_t        bit value
+***************************************************************************************************/
+uint32_t NWKU_GetFirstBitValue(uint8_t *pArray, uint32_t arrayBytes, bool_t bitValue);
+
+/*!*************************************************************************************************
+\fn     void APP_OtSetMulticastAddresses(otInstance *pOtInstance)
+\brief  This function is used to set the multicast addresses from the stack for application usage.
+
+\param  [in]    pOtInstance      Pointer to OpenThread instance
+
+\return         NONE
+***************************************************************************************************/
+void NWKU_OtSetMulticastAddresses(otInstance *pOtInstance);
+
+#ifdef __cplusplus
+}
+#endif
+/*================================================================================================*/
+#endif  /* _NETWORK_UTILS_H */

third_party/nxp/JN5189/crypto/aes_alt.h

@@ -0,0 +1,86 @@
+/**
+ * \file aes_alt.h
+ *
+ * \brief   This file contains alternate AES definitions and functions.
+ *
+ *          The Advanced Encryption Standard (AES) specifies a FIPS-approved
+ *          cryptographic algorithm that can be used to protect electronic
+ *          data.
+ *
+ *          The AES algorithm is a symmetric block cipher that can
+ *          encrypt and decrypt information. For more information, see
+ *          <em>FIPS Publication 197: Advanced Encryption Standard</em> and
+ *          <em>ISO/IEC 18033-2:2006: Information technology -- Security
+ *          techniques -- Encryption algorithms -- Part 2: Asymmetric
+ *          ciphers</em>.
+ *
+ *          The AES-XTS block mode is standardized by NIST SP 800-38E
+ *          <https://nvlpubs.nist.gov/nistpubs/legacy/sp/nistspecialpublication800-38e.pdf>
+ *          and described in detail by IEEE P1619
+ *          <https://ieeexplore.ieee.org/servlet/opac?punumber=4375278>.
+ */
+
+/*  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved.
+ *  SPDX-License-Identifier: Apache-2.0
+ *  Copyright 2018 NXP. Not a Contribution
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of Mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_AES_ALT_H
+#define MBEDTLS_AES_ALT_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_AES_ALT)
+
+#if defined(MBEDTLS_FREESCALE_HASHCRYPT_AES)
+/**
+ * \brief          AES context structure
+ */
+#define mbedtls_aes_context hashcrypt_handle_t
+
+#else
+// Regular implementation
+//
+
+/**
+ * \brief The AES context-type definition.
+ */
+typedef struct
+{
+    int nr;                     /*!< The number of rounds. */
+    uint32_t *rk;               /*!< AES round keys. */
+    uint32_t buf[68];           /*!< Unaligned data buffer. This buffer can
+                                     hold 32 extra Bytes, which can be used for
+                                     one of the following purposes:
+                                     <ul><li>Alignment if VIA padlock is
+                                             used.</li>
+                                     <li>Simplifying key expansion in the 256-bit
+                                         case by generating an extra round key.
+                                         </li></ul> */
+}
+mbedtls_aes_context;
+#endif /* MBEDTLS_FREESCALE_HASHCRYPT_AES */
+
+#endif /* MBEDTLS_AES_ALT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* aes_alt.h */

third_party/nxp/JN5189/crypto/ksdk_mbedtls.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef KSDK_MBEDTLS_H
+#define KSDK_MBEDTLS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int fsl_mbedtls_printf(const char *fmt_s, ...);
+void CRYPTO_InitHardware(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* KSDK_MBEDTLS_H */

third_party/nxp/JN5189/crypto/sha1_alt.h

@@ -0,0 +1,79 @@
+/**
+ * \file mbedtls_alt_sha1.h
+ *
+ * \brief SHA-1 cryptographic hash function
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *  Copyright 2017 NXP. Not a Contribution
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SHA1_ALT_H
+#define MBEDTLS_SHA1_ALT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_FREESCALE_LTC_SHA1)
+
+/**
+ * \brief          SHA-1 context structure
+ */
+#define mbedtls_sha1_context ltc_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_LPC_SHA1)
+
+/**
+ * \brief          SHA-1 context structure
+ */
+#define mbedtls_sha1_context sha_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_CAAM_SHA1)
+
+/**
+ * \brief          SHA-1 context structure
+ */
+#define mbedtls_sha1_context caam_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_CAU3_SHA1)
+
+/**
+ * \brief          SHA-1 context structure
+ */
+#define mbedtls_sha1_context cau3_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_DCP_SHA1)
+
+/**
+ * \brief          SHA-1 context structure
+ */
+#define mbedtls_sha1_context dcp_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_HASHCRYPT_SHA1)
+
+/**
+ * \brief          SHA-1 context structure
+ */
+#define mbedtls_sha1_context hashcrypt_hash_ctx_t
+
+#endif /* MBEDTLS_FREESCALE_LTC_SHA1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_SHA1_ALT_H */

third_party/nxp/JN5189/crypto/sha256_alt.h

@@ -0,0 +1,82 @@
+/**
+ * \file mbedtls_sha256.h
+ *
+ * \brief SHA-224 and SHA-256 cryptographic hash function
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *  Copyright 2017 NXP. Not a Contribution
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SHA256_ALT_H
+#define MBEDTLS_SHA256_ALT_H
+
+// Regular implementation
+//
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(MBEDTLS_FREESCALE_LTC_SHA256)
+
+/**
+ * \brief          SHA-256 context structure
+ */
+#define mbedtls_sha256_context ltc_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_LPC_SHA256)
+
+/**
+ * \brief          SHA-256 context structure
+ */
+#define mbedtls_sha256_context sha_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_CAAM_SHA256)
+
+/**
+ * \brief          SHA-256 context structure
+ */
+#define mbedtls_sha256_context caam_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_CAU3_SHA256)
+
+/**
+ * \brief          SHA-256 context structure
+ */
+#define mbedtls_sha256_context cau3_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_DCP_SHA256)
+
+/**
+ * \brief          SHA-256 context structure
+ */
+#define mbedtls_sha256_context dcp_hash_ctx_t
+
+#elif defined(MBEDTLS_FREESCALE_HASHCRYPT_SHA256)
+
+/**
+ * \brief          SHA-256 context structure
+ */
+#define mbedtls_sha256_context hashcrypt_hash_ctx_t
+
+#endif /* MBEDTLS_FREESCALE_LTC_SHA256 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* sha256_alt.h */

third_party/nxp/JN5189/dk6_jn5180/board.c

@@ -0,0 +1,71 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include "fsl_debug_console.h"
+#include "fsl_clock.h"
+#include "board.h"
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if (defined TCXO_32M_MODE_EN) && (TCXO_32M_MODE_EN != 0)
+/* Table of load capacitance versus temperature for 32MHz crystal. Values below
+   are for NDK NX2016SA 32MHz EXS00A-CS11213-6(IEC). Values are for temperatures
+   from -40 to +130 in steps of 5 */
+int32_t CLOCK_ai32MXtalIecLoadPfVsTemp_x1000[HW_32M_LOAD_VS_TEMP_SIZE] =
+    {  960,  1097,  1194,  1246,  1253,  1216,  1137,  1023, /* -40, -35, ... -5 */
+       879,   710,   523,   325,   122,   -81,  -277,  -464, /* 0, 5, ... 35 */
+      -637,  -794,  -933, -1052, -1150, -1227, -1283, -1317, /* 40, 45, ... 75 */
+     -1328, -1315, -1274, -1202, -1090,  -930,  -709,  -409, /* 80, 85, ... 115 */
+        -9,   518,  1205};                                   /* 120, 125, 130 */
+#endif
+
+#if (defined TCXO_32k_MODE_EN) && (TCXO_32k_MODE_EN != 0)
+/* Table of load capacitance versus temperature for 32kHz crystal. Values are
+   for temperatures from -20 to +100 in steps of 20. *Note* values below are
+   just for example */
+int32_t CLOCK_ai32kXtalIecLoadPfVsTemp_x1000[HW_32k_LOAD_VS_TEMP_SIZE] =
+    {  960,  /* -20 */
+      1097,  /*   0 */
+      1194,  /*  20 */
+      1246,  /*  40 */
+      1253,  /*  60 */
+      1216,  /*  80 */
+      1137}; /* 100 */
+#endif
+
+/*******************************************************************************
+* Local Prototypes
+******************************************************************************/
+
+/*****************************************************************************
+* Local functions
+****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize debug console. */
+status_t BOARD_InitDebugConsole(void)
+{
+    status_t result;
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+
+#ifndef RTL_SIMU_ON_ES2
+    CLOCK_uDelay(500);
+#endif
+
+    return result;
+}
+
+

third_party/nxp/JN5189/dk6_jn5180/board.h

@@ -0,0 +1,206 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "clock_config.h"
+#include "fsl_clock.h"
+#include "fsl_power.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DK6"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE       DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM
+#define BOARD_DEBUG_UART_BAUDRATE   115200U
+#define BOARD_DEBUG_UART_BASEADDR   (uint32_t) USART0
+#define BOARD_DEBUG_UART_CLK_FREQ   CLOCK_GetFreq(kCLOCK_Fro32M)
+#define BOARD_UART_IRQ              LPUART0_IRQn
+#define BOARD_UART_IRQ_HANDLER      LPUART0_IRQHandler
+#define BOARD_DEBUG_UART_CLK_ATTACH kOSC32M_to_USART_CLK
+
+/* There are 2 red LEDs on DK6 board: PIO0 and PIO3 */
+#define BOARD_LED_RED_GPIO        GPIO
+#define BOARD_LED_RED_GPIO_PORT   0U
+#define BOARD_LED_RED_GPIO_PIN    0U
+#define BOARD_LED_GREEN_GPIO      GPIO
+#define BOARD_LED_GREEN_GPIO_PORT 0U
+#define BOARD_LED_GREEN_GPIO_PIN  5U
+#define BOARD_LED_BLUE_GPIO       GPIO
+#define BOARD_LED_BLUE_GPIO_PORT  0U
+#define BOARD_LED_BLUE_GPIO_PIN   3U
+
+/* Board led color mapping */
+#define LOGIC_LED_ON  0U
+#define LOGIC_LED_OFF 1U
+
+#define LED_RED_INIT(output)                                                          \
+    GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */
+#define LED_RED_ON()                                                  \
+    GPIO_ClearPinsOutput(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                         1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
+#define LED_RED_OFF()                                               \
+    GPIO_SetPinsOutput(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                       1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
+#define LED_RED_TOGGLE()                                               \
+    GPIO_TogglePinsOutput(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+                          1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
+
+#define LED_GREEN_INIT(output)                                                              \
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */
+#define LED_GREEN_ON()                                                    \
+    GPIO_ClearPinsOutput(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                         1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
+#define LED_GREEN_OFF()                                                 \
+    GPIO_SetPinsOutput(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                       1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
+#define LED_GREEN_TOGGLE()                                                 \
+    GPIO_TogglePinsOutput(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+                          1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
+
+#define LED_BLUE_INIT(output)                                                            \
+    GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */
+#define LED_BLUE_ON()                                                   \
+    GPIO_ClearPinsOutput(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                         1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
+#define LED_BLUE_OFF()                                                \
+    GPIO_SetPinsOutput(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                       1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
+#define LED_BLUE_TOGGLE()                                                \
+    GPIO_TogglePinsOutput(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+                          1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
+
+/* There are 2 red LEDs on USB Dongle: PIO4 and PIO10 */
+#define BOARD_LED_USB_DONGLE_GPIO GPIO
+#define BOARD_LED_USB_DONGLE_GPIO_PORT 0U
+#define BOARD_LED_USB_DONGLE1_GPIO_PIN 4U
+#define BOARD_LED_USB_DONGLE2_GPIO_PIN 10U
+
+#define BOARD_SW1_GPIO GPIO
+#define BOARD_SW1_GPIO_PORT 0U
+#define BOARD_SW1_GPIO_PIN  1U
+#define BOARD_SW1_NAME "SW1"
+#define BOARD_SW3_IRQ PIN_INT0_IRQn
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler
+
+#define BOARD_SW2_GPIO GPIO
+#define BOARD_SW2_GPIO_PORT 0U
+#define BOARD_SW2_GPIO_PIN  5U
+#define BOARD_SW2_NAME "SW2"
+#define BOARD_SW3_IRQ PIN_INT0_IRQn
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler
+
+/* Capacitance values for 32MHz and 32kHz crystals; board-specific. Value is
+   pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 */
+#define CLOCK_32MfXtalIecLoadpF_x100    (600) /* 6.0pF */
+#define CLOCK_32MfXtalPPcbParCappF_x100 (20)  /* 0.2pF */
+#define CLOCK_32MfXtalNPcbParCappF_x100 (40)  /* 0.4pF */
+#define CLOCK_32kfXtalIecLoadpF_x100    (600) /* 6.0pF */
+#define CLOCK_32kfXtalPPcbParCappF_x100 (40)  /* 0.4pF */
+#define CLOCK_32kfXtalNPcbParCappF_x100 (40)  /* 0.4pF */
+
+/* Capacitance variation for 32MHz crystal across temperature
+   ----------------------------------------------------------
+
+   TCXO_32M_MODE_EN should be 1 to indicate that temperature-compensated 32MHz
+   XO is supported and required. If so, HW_32M_LOAD_VS_TEMP_MIN,
+   _MAX, _STEP must be defined here and CLOCK_ai32MXtalIecLoadPfVsTemp_x1000
+   must be defined in board.c.
+
+   Values are used as follows:
+   CLOCK_ai32MXtalIecLoadPfVsTemp_x1000 is an array of crystal load capacitance
+   values across temp, with each value being at a specific temp. First value is
+   for temp given by HW_32M_LOAD_VS_TEMP_MIN, next value is for
+   temp given by HW_32M_LOAD_VS_TEMP_MIN + _STEP, next value is
+   for temp given by HW_32M_LOAD_VS_TEMP_MIN + _ STEP x 2, etc.
+   Final value is for temp given by HW_32M_LOAD_VS_TEMP_MAX. It is
+   important for HW_32M_LOAD_VS_TEMP_x defines and the table to be
+   matched to one another */
+#define TCXO_32M_MODE_EN                     (1)
+
+/* Values below are for NDK NX2016SA 32MHz EXS00A-CS11213-6(IEC) */
+
+/* Temperature related to element 0 of CLOCK_ai32MXtalIecLoadPfVsTemp_x1000 */
+#define HW_32M_LOAD_VS_TEMP_MIN  (-40)
+
+/* Temperature related to final element of CLOCK_ai32MXtalIecLoadPfVsTemp_x1000 */
+#define HW_32M_LOAD_VS_TEMP_MAX  (130)
+
+/* Temperature step between elements of CLOCK_ai32MXtalIecLoadPfVsTemp_x1000 */
+#define HW_32M_LOAD_VS_TEMP_STEP (5)
+
+#define HW_32M_LOAD_VS_TEMP_SIZE ((HW_32M_LOAD_VS_TEMP_MAX \
+                                   - HW_32M_LOAD_VS_TEMP_MIN) \
+                                  / HW_32M_LOAD_VS_TEMP_STEP + 1U)
+
+/* Table of load capacitance versus temperature for 32MHz crystal. Values are
+   for temperatures from -40 to +130 in steps of 5 */
+extern int32_t CLOCK_ai32MXtalIecLoadPfVsTemp_x1000[HW_32M_LOAD_VS_TEMP_SIZE];
+
+/* Capacitance variation for 32kHz crystal across temperature
+   ----------------------------------------------------------
+
+   TCXO_32k_MODE_EN should be 1 to indicate that temperature-compensated 32kHz
+   XO is supported and required. If so, HW_32k_LOAD_VS_TEMP_MIN,
+   _MAX, _STEP must be defined here and CLOCK_ai32kXtalIecLoadPfVsTemp_x1000
+   must be defined in board.c.
+
+   Values are used as follows:
+   CLOCK_ai32kXtalIecLoadPfVsTemp_x1000 is an array of crystal load capacitance
+   values across temp, with each value being at a specific temp. First value is
+   for temp given by HW_32k_LOAD_VS_TEMP_MIN, next value is for
+   temp given by HW_32k_LOAD_VS_TEMP_MIN + _STEP, next value is
+   for temp given by HW_32k_LOAD_VS_TEMP_MIN + _ STEP x 2, etc.
+   Final value is for temp given by HW_32k_LOAD_VS_TEMP_MAX. It is
+   important for HW_32k_LOAD_VS_TEMP_x defines and the table to be
+   matched to one another */
+#define TCXO_32k_MODE_EN                     (0) /* Disabled because table is
+                                                    *not* correct: values below
+                                                    are just for example */
+
+/* Temperature related to element 0 of CLOCK_ai32kXtalIecLoadPfVsTemp_x1000 */
+#define HW_32k_LOAD_VS_TEMP_MIN  (-20)
+
+/* Temperature related to final element of CLOCK_ai32kXtalIecLoadPfVsTemp_x1000 */
+#define HW_32k_LOAD_VS_TEMP_MAX  (100)
+
+/* Temperature step between elements of CLOCK_ai32kXtalIecLoadPfVsTemp_x1000 */
+#define HW_32k_LOAD_VS_TEMP_STEP (20)
+
+#define HW_32k_LOAD_VS_TEMP_SIZE ((HW_32k_LOAD_VS_TEMP_MAX \
+                                   - HW_32k_LOAD_VS_TEMP_MIN) \
+                                  / HW_32k_LOAD_VS_TEMP_STEP + 1U)
+
+/* Table of load capacitance versus temperature for 32kHz crystal. Values are
+   for temperatures from -20 to +100 in steps of 20 */
+extern int32_t CLOCK_ai32kXtalIecLoadPfVsTemp_x1000[HW_32k_LOAD_VS_TEMP_SIZE];
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+status_t BOARD_InitDebugConsole(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

third_party/nxp/JN5189/dk6_jn5180/clock_config.c

@@ -0,0 +1,67 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include "fsl_common.h"
+#include "clock_config.h"
+#include "system_JN5189.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+}
+
+void BOARD_BootClockRUN(void)
+{
+    /* Set PMC FRO selection */
+    CLOCK_EnableClock(kCLOCK_Fro32M);
+    CLOCK_EnableClock(kCLOCK_Fro48M);
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+    CLOCK_EnableClock(kCLOCK_Rtc);
+
+    /* INMUX and IOCON are used by many apps, enable both INMUX and IOCON clock bits here. */
+    CLOCK_AttachClk(kOSC32M_to_FRG_CLK);
+    CLOCK_AttachClk(kMAIN_CLK_to_DMI_CLK);
+
+    CLOCK_EnableAPBBridge();
+    SYSCON->DMICCLKDIV=0;
+    CLOCK_SetClkDiv(kCLOCK_DivClkout, 1, false);
+
+    CLOCK_EnableClock(kCLOCK_Xtal32M);
+    CLOCK_EnableClock(kCLOCK_Xtal32k);
+    CLOCK_AttachClk(kXTAL32K_to_OSC32K_CLK);
+
+    /* Enable 48MHz CPU freq */
+    CLOCK_AttachClk(kFRO48M_to_MAIN_CLK);
+    /* Enable 32MHZ XTAL to Ctimer */
+    CLOCK_AttachClk(kXTAL32M_to_ASYNC_APB);
+
+    /* WWDT clock config (32k oscillator, no division) */
+    CLOCK_AttachClk(kOSC32K_to_WDT_CLK);
+    CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1, true);
+
+    /* enable the clocks for the cryto blocks */
+    CLOCK_EnableClock(kCLOCK_Aes);
+
+    SystemCoreClockUpdate();
+}
+
+void BOARD_BootClockHSRUN(void)
+{
+}

third_party/nxp/JN5189/dk6_jn5180/clock_config.h

@@ -0,0 +1,31 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockVLPR(void);
+void BOARD_BootClockRUN(void);
+void BOARD_BootClockHSRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */

third_party/nxp/JN5189/dk6_jn5180/pin_mux.c

@@ -0,0 +1,139 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#ifndef BOARD_USECLKINSRC
+#define BOARD_USECLKINSRC (0)
+#endif
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Local Prototypes
+ ****************************************************************************/
+/*****************************************************************************
+* Private functions
+****************************************************************************/
+static void ConfigureConsolePort(void)
+{
+    /* UART0 RX/TX pins */
+    IOCON_PinMuxSet(IOCON, 0, 8, IOCON_MODE_INACT | IOCON_FUNC2 | IOCON_DIGITAL_EN);
+    IOCON_PinMuxSet(IOCON, 0, 9, IOCON_MODE_INACT | IOCON_FUNC2 | IOCON_DIGITAL_EN);
+}
+
+static void ConfigureDebugPort(void)
+{
+    /* SWD SWCLK/SWDIO pins */
+    IOCON_PinMuxSet(IOCON, 0, 12, IOCON_FUNC2 | IOCON_MODE_INACT | IOCON_DIGITAL_EN);
+    IOCON_PinMuxSet(IOCON, 0, 13, IOCON_FUNC2 | IOCON_MODE_INACT | IOCON_DIGITAL_EN);
+#ifdef ENABLE_DEBUG_PORT_SWO
+    /* SWD SWO pin (optional) */
+    IOCON_PinMuxSet(IOCON, 0, 14, IOCON_FUNC5 | IOCON_MODE_INACT | IOCON_DIGITAL_EN);
+    SYSCON->TRACECLKDIV = 0; /* Clear HALT bit */
+#endif
+}
+
+static void ConfigureDongleLEDs(void)
+{
+    const uint32_t port0_pin4_config = (/* Pin is configured as PIO0_4 */
+                                        IOCON_PIO_FUNC0 |
+                                        /* Selects pull-up function */
+                                        IOCON_PIO_MODE_PULLUP |
+                                        /* Standard mode, output slew rate control is disabled */
+                                        IOCON_PIO_SLEW0_STANDARD |
+                                        /* Input function is not inverted */
+                                        IOCON_PIO_INV_DI |
+                                        /* Enables digital function */
+                                        IOCON_PIO_DIGITAL_EN |
+                                        /* Input filter disabled */
+                                        IOCON_PIO_INPFILT_OFF |
+                                        /* Standard mode, output slew rate control is disabled */
+                                        IOCON_PIO_SLEW1_STANDARD |
+                                        /* Open drain is disabled */
+                                        IOCON_PIO_OPENDRAIN_DI |
+                                        /* SSEL is disabled */
+                                        IOCON_PIO_SSEL_DI);
+    /* PORT0 PIN4 (coords: 7) is configured as PIO0_4 */
+    IOCON_PinMuxSet(IOCON, 0U, 4U, port0_pin4_config);
+
+    const uint32_t port0_pin10_config = (/* Pin is configured as PIO0_10 */
+                                         IOCON_PIO_FUNC0 |
+                                         /* GPIO mode */
+                                         IOCON_PIO_EGP_GPIO |
+                                         /* IO is an open drain cell */
+                                         IOCON_PIO_ECS_DI |
+                                         /* High speed IO for GPIO mode, IIC not */
+                                         IOCON_PIO_EHS_DI |
+                                         /* Input function is not inverted */
+                                         IOCON_PIO_INV_DI |
+                                         /* Enables digital function */
+                                         IOCON_PIO_DIGITAL_EN |
+                                         /* Input filter disabled */
+                                         IOCON_PIO_INPFILT_OFF |
+                                         /* IIC mode:Noise pulses below approximately 50ns are filtered out. GPIO mode:a 3ns filter */
+                                         IOCON_PIO_FSEL_DI |
+                                         /* Open drain is disabled */
+                                         IOCON_PIO_OPENDRAIN_DI |
+                                         /* IO_CLAMP disabled */
+                                         IOCON_PIO_IO_CLAMP_DI);
+    /* PORT0 PIN10 (coords: 13) is configured as PIO0_10 */
+    IOCON_PinMuxSet(IOCON, 0U, 10U, port0_pin10_config);
+}
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_InitPins(void)
+{
+    /* Define the init structure for the output LED pin*/
+    gpio_pin_config_t led_config = {
+        kGPIO_DigitalOutput,
+        0,
+    };
+
+    /* Enable IOCON clock */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+    CLOCK_EnableClock(kCLOCK_InputMux);
+
+    /* Console signals */
+    ConfigureConsolePort();
+
+    /* Debugger signals */
+    ConfigureDebugPort();
+
+    ConfigureDongleLEDs();
+
+    /* IOCON clock left on, this is needed if CLKIN is used. */
+    /* Initialize GPIO */
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+    RESET_PeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+
+    /* Init output LED GPIO. */
+    GPIO_PortInit(BOARD_LED_USB_DONGLE_GPIO, BOARD_LED_USB_DONGLE_GPIO_PORT);
+    GPIO_PinInit(BOARD_LED_USB_DONGLE_GPIO, BOARD_LED_USB_DONGLE_GPIO_PORT, BOARD_LED_USB_DONGLE1_GPIO_PIN, &led_config);
+    GPIO_PinInit(BOARD_LED_USB_DONGLE_GPIO, BOARD_LED_USB_DONGLE_GPIO_PORT, BOARD_LED_USB_DONGLE2_GPIO_PIN, &led_config);
+
+    GPIO_PortToggle(BOARD_LED_USB_DONGLE_GPIO, BOARD_LED_USB_DONGLE_GPIO_PORT, 1u << BOARD_LED_USB_DONGLE1_GPIO_PIN);
+}
+
+
+void BOARD_LedDongleToggle(void)
+{
+    GPIO_PortToggle(BOARD_LED_USB_DONGLE_GPIO, BOARD_LED_USB_DONGLE_GPIO_PORT, 1u << BOARD_LED_USB_DONGLE1_GPIO_PIN);
+    GPIO_PortToggle(BOARD_LED_USB_DONGLE_GPIO, BOARD_LED_USB_DONGLE_GPIO_PORT, 1u << BOARD_LED_USB_DONGLE2_GPIO_PIN);
+}

third_party/nxp/JN5189/dk6_jn5180/pin_mux.h

@@ -0,0 +1,45 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+#include "fsl_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+       /*!
+        * @brief configure all pins for this demo/example
+        *
+        */
+
+#define IOCON_PIO_DIGITAL_EN 0x80u     /*!<@brief Enables digital function */
+#define IOCON_PIO_ECS_DI 0x00u         /*!<@brief IO is an open drain cell */
+#define IOCON_PIO_EGP_GPIO 0x08u       /*!<@brief GPIO mode */
+#define IOCON_PIO_EHS_DI 0x00u         /*!<@brief High speed IO for GPIO mode, IIC not */
+#define IOCON_PIO_FSEL_DI 0x00u        /*!<@brief IIC mode:Noise pulses below approximately 50ns are filtered out. GPIO mode:a 3ns filter */
+#define IOCON_PIO_FUNC0 0x00u          /*!<@brief Selects pin function 2 */
+#define IOCON_PIO_FUNC2 0x02u          /*!<@brief Selects pin function 2 */
+#define IOCON_PIO_INPFILT_OFF 0x0100u  /*!<@brief Input filter disabled */
+#define IOCON_PIO_INV_DI 0x00u         /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_PULLUP 0x00u    /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u   /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW0_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is disabled */
+#define IOCON_PIO_SLEW1_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is disabled */
+#define IOCON_PIO_SSEL_DI 0x00u        /*!<@brief SSEL is disabled */
+#define IOCON_PIO_IO_CLAMP_DI 0x00u    /*!<@brief IO_CLAMP disabled */
+
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _PIN_MUX_H_  */

third_party/nxp/JN5189/drivers/aes/fsl_aes.h

@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_AES_H_
+#define _FSL_AES_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup aes
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines LPC AES driver version 2.0.1.
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ * - Version 2.0.1
+ *   - GCM constant time tag comparison
+ */
+#define FSL_AES_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name AES Functional Operation
+ * @{
+ */
+
+/*! AES block size in bytes */
+#define AES_BLOCK_SIZE 16
+/*! AES Input Vector size in bytes */
+#define AES_IV_SIZE 16
+
+/*!
+ * @brief Sets AES key.
+ *
+ * Sets AES key.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @return Status from Set Key operation
+ */
+status_t AES_SetKey(AES_Type *base, const uint8_t *key, size_t keySize);
+
+/*!
+ * @brief Encrypts AES using the ECB block mode.
+ *
+ * Encrypts AES using the ECB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptEcb(AES_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, size_t size);
+
+/*!
+ * @brief Decrypts AES using the ECB block mode.
+ *
+ * Decrypts AES using the ECB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptEcb(AES_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, size_t size);
+
+/*!
+ * @brief Encrypts AES using CBC block mode.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptCbc(
+    AES_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[AES_IV_SIZE]);
+
+/*!
+ * @brief Decrypts AES using CBC block mode.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptCbc(
+    AES_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[AES_IV_SIZE]);
+
+/*!
+ * @brief Encrypts AES using CFB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input Initial vector to be used as the first input block.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptCfb(
+    AES_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[AES_IV_SIZE]);
+
+/*!
+ * @brief Decrypts AES using CFB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input Initial vector to be used as the first input block.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptCfb(
+    AES_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[AES_IV_SIZE]);
+
+/*!
+ * @brief Encrypts AES using OFB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes.
+ * @param iv Input Initial vector to be used as the first input block.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptOfb(
+    AES_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, size_t size, const uint8_t iv[AES_IV_SIZE]);
+
+/*!
+ * @brief Decrypts AES using OFB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes.
+ * @param iv Input Initial vector to be used as the first input block.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptOfb(
+    AES_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, size_t size, const uint8_t iv[AES_IV_SIZE]);
+
+/*!
+ * @brief Encrypts or decrypts AES using CTR block mode.
+ *
+ * Encrypts or decrypts AES using CTR block mode.
+ * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * @param base AES peripheral base address
+ * @param input Input data for CTR block mode
+ * @param[out] output Output data for CTR block mode
+ * @param size Size of input and output data in bytes
+ * @param[in,out] counter Input counter (updates on return)
+ * @param[out] counterlast Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are
+ * not used.
+ * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls
+ * are not used.
+ * @return Status from crypt operation
+ */
+status_t AES_CryptCtr(AES_Type *base,
+                      const uint8_t *input,
+                      uint8_t *output,
+                      size_t size,
+                      uint8_t counter[AES_BLOCK_SIZE],
+                      uint8_t counterlast[AES_BLOCK_SIZE],
+                      size_t *szLeft);
+
+/*!
+ * @brief Encrypts AES and tags using GCM block mode.
+ *
+ * Encrypts AES and optionally tags using GCM block mode. If plaintext is NULL, only the GHASH is calculated and output
+ * in the 'tag' field.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the IV
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of AAD
+ * @param[out] tag Output hash tag. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag to generate, in bytes. Must be 4,8,12,13,14,15 or 16.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptTagGcm(AES_Type *base,
+                           const uint8_t *plaintext,
+                           uint8_t *ciphertext,
+                           size_t size,
+                           const uint8_t *iv,
+                           size_t ivSize,
+                           const uint8_t *aad,
+                           size_t aadSize,
+                           uint8_t *tag,
+                           size_t tagSize);
+
+/*!
+ * @brief Decrypts AES and authenticates using GCM block mode.
+ *
+ * Decrypts AES and optionally authenticates using GCM block mode. If ciphertext is NULL, only the GHASH is calculated
+ * and compared with the received GHASH in 'tag' field.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the IV
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of AAD
+ * @param tag Input hash tag to compare. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag, in bytes. Must be 4, 8, 12, 13, 14, 15, or 16.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptTagGcm(AES_Type *base,
+                           const uint8_t *ciphertext,
+                           uint8_t *plaintext,
+                           size_t size,
+                           const uint8_t *iv,
+                           size_t ivSize,
+                           const uint8_t *aad,
+                           size_t aadSize,
+                           const uint8_t *tag,
+                           size_t tagSize);
+
+void AES_Init(AES_Type *base);
+
+void AES_Deinit(AES_Type *base);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+/*! @}*/ /* end of group aes */
+
+#endif /* _FSL_AES_H_ */

third_party/nxp/JN5189/drivers/fsl_assert.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif (defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+#endif /* NDEBUG */

third_party/nxp/JN5189/drivers/fsl_clock.h

@@ -0,0 +1,591 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include <stddef.h>
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+#ifdef FPGA_50MHZ
+#define SYSCON_BASE_CLOCK_DIV (6)
+#define SYSCON_BASE_CLOCK_MUL (5)
+
+#define SYS_FREQ(A) ((A * SYSCON_BASE_CLOCK_MUL) / SYSCON_BASE_CLOCK_DIV)
+#else
+#define SYS_FREQ(A) (A)
+#endif
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (48000000UL)
+#endif
+
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS                                                                               \
+    {                                                                                                 \
+        kCLOCK_Usart0, kCLOCK_Usart1, kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_I2c2 \
+    }
+/*! @brief Clock ip name array for CTIMER. */
+#define CTIMER_CLOCKS                \
+    {                                \
+        kCLOCK_Timer0, kCLOCK_Timer1 \
+    }
+/*! @brief Clock ip name array for GINT. */
+#define GINT_CLOCKS \
+    {               \
+        kCLOCK_Gint \
+    }
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS   \
+    {                 \
+        kCLOCK_WdtOsc \
+    }
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS \
+    {               \
+        kCLOCK_DMic \
+    }
+/*! @brief Clock ip name array for ADC. */
+#define ADC_CLOCKS  \
+    {               \
+        kCLOCK_Adc0 \
+    }
+/*! @brief Clock ip name array for SPIFI. */
+#define SPIFI_CLOCKS \
+    {                \
+        kCLOCK_Spifi \
+    }
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS  \
+    {                \
+        kCLOCK_Gpio0 \
+    }
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS \
+    {              \
+        kCLOCK_Dma \
+    }
+
+/* Test line to verify RCS */
+/* Another test line to verify source control */
+/* Test lines added by Robert Gee */
+
+/**
+ * @brief Clock sources for main system clock.
+ */
+typedef enum
+{
+    SYSCON_MAINCLKSRC_FRO12M,  /*!< FRO 12MHz */
+    SYSCON_MAINCLKSRC_OSC32K,  /*!< OSC 32kHz */
+    SYSCON_MAINCLKSRC_XTAL32M, /*!< XTAL 32MHz */
+    SYSCON_MAINCLKSRC_FRO32M,  /*!< FRO 32MHz */
+    SYSCON_MAINCLKSRC_FRO48M,  /*!< FRO 48MHz */
+    SYSCON_MAINCLKSRC_EXT,     /*!< External clock */
+    SYSCON_MAINCLKSRC_FRO1M,   /*!< FRO 1MHz */
+} CHIP_SYSCON_MAINCLKSRC_T;
+
+/**
+ * @brief	Fractional Divider clock sources
+ */
+typedef enum
+{
+    SYSCON_FRGCLKSRC_MAINCLK,  /*!< Main Clock */
+    SYSCON_FRGCLKSRC_OSC32M,   /*!< 32MHz Clock (XTAL or FRO) */
+    SYSCON_FRGCLKSRC_FRO48MHZ, /*!< FRO 48-MHz */
+    SYSCON_FRGCLKSRC_NONE,     /*!< FRO 48-MHz */
+} CHIP_SYSCON_FRGCLKSRC_T;
+
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
+    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define AHB_CLK_CTRL0 0
+#define AHB_CLK_CTRL1 1
+#define ASYNC_CLK_CTRL0 2
+
+/**
+ * @brief   Clock name definition
+ */
+typedef enum _clock_name
+{
+    kCLOCK_Rom      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ROM_SHIFT),        /*!< ROM clock */
+    kCLOCK_Sram0    = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL0_SHIFT), /*!< SRAM0 clock */
+    kCLOCK_Sram1    = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT), /*!< SRAM1 clock */
+    kCLOCK_Flash    = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_FLASH_SHIFT),      /*!< Flash clock */
+    kCLOCK_Spifi    = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SPIFI_SHIFT),      /*!< SPIFI clock */
+    kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_MUX_SHIFT),        /*!< InputMux clock */
+    kCLOCK_Iocon    = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_IOCON_SHIFT),      /*!< IOCON clock */
+    kCLOCK_Gpio0    = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_GPIO_SHIFT),       /*!< GPIO0 clock */
+    kCLOCK_Pint     = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_PINT_SHIFT),       /*!< PINT clock */
+    kCLOCK_Gint     = CLK_GATE_DEFINE(
+        AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_GINT_SHIFT), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot  */
+    kCLOCK_Dma     = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_DMA_SHIFT),     /*!< DMA clock */
+    kCLOCK_Iso7816 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ISO7816_SHIFT), /*!< ISO7816 clock */
+    kCLOCK_WdtOsc  = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_WWDT_SHIFT),    /*!< WDTOSC clock */
+    kCLOCK_Rtc     = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_RTC_SHIFT),     /*!< RTC clock */
+    kCLOCK_AnaInt  = CLK_GATE_DEFINE(
+        AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ANA_INT_CTRL_SHIFT), /*!<  Analog Interrupt Control module clock */
+    kCLOCK_WakeTmr =
+        CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_WAKE_UP_TIMERS_SHIFT),        /*!<  Wake up Timers clock */
+    kCLOCK_Adc0      = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ADC_SHIFT),    /*!< ADC0 clock */
+    kCLOCK_Efuse     = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_EFUSE_SHIFT),  /*!< EFuse clock */
+    kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART0_SHIFT), /*!< FlexComm0 clock */
+    kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART1_SHIFT), /*!< FlexComm1 clock */
+    kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C0_SHIFT),   /*!< FlexComm2 clock */
+    kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C1_SHIFT),   /*!< FlexComm3 clock */
+    kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI0_SHIFT),   /*!< FlexComm4 clock */
+    kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI1_SHIFT),   /*!< FlexComm5 clock */
+    kCLOCK_Ir        = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_IR_SHIFT),     /*!< Infra Red clock */
+    kCLOCK_Pwm       = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_PWM_SHIFT),    /*!< PWM clock */
+    kCLOCK_Rng       = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_RNG_SHIFT),    /*!< RNG clock */
+    kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C2_SHIFT),   /*!< FlexComm6 clock */
+    kCLOCK_Usart0    = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART0_SHIFT), /*!< USART0 clock */
+    kCLOCK_Usart1    = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART1_SHIFT), /*!< USART1 clock */
+    kCLOCK_I2c0      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C0_SHIFT),   /*!< I2C0 clock */
+    kCLOCK_I2c1      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C1_SHIFT),   /*!< I2C1 clock */
+    kCLOCK_Spi0      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI0_SHIFT),   /*!< SPI0 clock */
+    kCLOCK_Spi1      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI1_SHIFT),   /*!< SPI1 clock */
+    kCLOCK_I2c2      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C2_SHIFT),   /*!< I2C2 clock */
+    kCLOCK_Modem     = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_MODEM_MASTER_SHIFT), /*!< MODEM clock */
+    kCLOCK_Aes       = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_AES_SHIFT),          /*!< AES clock */
+    kCLOCK_Rfp       = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_RFP_SHIFT),          /*!< RFP clock */
+    kCLOCK_DMic      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_DMIC_SHIFT),         /*!< DMIC clock */
+    kCLOCK_Sha0      = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_HASH_SHIFT),         /*!< SHA0 clock */
+    kCLOCK_Timer0    = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 1),                                   /*!< Timer0 clock */
+    kCLOCK_Timer1    = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 2),                                   /*!< Timer1 clock */
+    kCLOCK_MainClk   = (1 << 16),                                                             /*!< MAIN_CLK */
+    kCLOCK_CoreSysClk,                                                                        /*!< Core/system clock */
+    kCLOCK_BusClk,                                                                            /*!< AHB bus clock */
+    kCLOCK_Xtal32k,                                                             /*!< 32kHz crystal oscillator */
+    kCLOCK_Xtal32M,                                                             /*!< 32MHz crystal oscillator */
+    kCLOCK_Fro32k,                                                              /*!< 32kHz free running oscillator */
+    kCLOCK_Fro1M,                                                               /*!< 1MHz Free Running Oscillator */
+    kCLOCK_Fro12M,                                                              /*!< 12MHz Free Running Oscillator */
+    kCLOCK_Fro32M,                                                              /*!< 32MHz Free Running Oscillator */
+    kCLOCK_Fro48M,                                                              /*!< 48MHz Free Running Oscillator */
+    kCLOCK_Fro64M,                                                              /*!< 64Mhz Free Running Oscillator */
+    kCLOCK_ExtClk,                                                              /*!< External clock */
+    kCLOCK_WdtClk,                                                              /*!< Watchdog clock */
+    kCLOCK_Frg,                                                                 /*!< Fractional divider */
+    kCLOCK_ClkOut,                                                              /*!< Clock out */
+    kCLOCK_Fmeas,                                                               /*!< FMEAS clock */
+    kCLOCK_Sha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_HASH_SHIFT), /*!< Hash clock */
+} clock_name_t;
+
+typedef clock_name_t clock_ip_name_t;
+
+#define REG_OFST(block, member) (offsetof(block##_Type, member) / sizeof(uint32_t))
+
+#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 12))
+
+/*! @brief Clock source selector definition */
+typedef enum
+{
+    CM_MAINCLKSEL   = REG_OFST(SYSCON, MAINCLKSEL),  /*!< Clock source selector of Main clock source */
+    CM_OSC32CLKSEL  = REG_OFST(SYSCON, OSC32CLKSEL), /*!< Clock source selector of OSC32KCLK and OSC32MCLK */
+    CM_CLKOUTCLKSEL = REG_OFST(SYSCON, CLKOUTSEL),   /*!< Clock source selector of CLKOUT */
+    CM_SPIFICLKSEL  = REG_OFST(SYSCON, SPIFICLKSEL), /*!< Clock source selector of SPIFI */
+    CM_ADCCLKSEL    = REG_OFST(SYSCON, ADCCLKSEL),   /*!< Clock source selector of ADC */
+    CM_USARTCLKSEL  = REG_OFST(SYSCON, USARTCLKSEL), /*!< Clock source selector of USART0 & 1 */
+    CM_I2CCLKSEL    = REG_OFST(SYSCON, I2CCLKSEL),   /*!< Clock source selector of I2C0, 1 and 2 */
+    CM_SPICLKSEL    = REG_OFST(SYSCON, SPICLKSEL),   /*!< Clock source selector of SPI0 & 1 */
+    CM_IRCLKSEL     = REG_OFST(SYSCON, IRCLKSEL),    /*!< Clock source selector of Infra Red */
+    CM_PWMCLKSEL    = REG_OFST(SYSCON, PWMCLKSEL),   /*!< Clock source selector of PWM */
+    CM_WDTCLKSEL    = REG_OFST(SYSCON, WDTCLKSEL),   /*!< Clock source selector of Watchdog Timer */
+    CM_MODEMCLKSEL  = REG_OFST(SYSCON, MODEMCLKSEL), /*!< Clock source selector of Modem */
+    CM_FRGCLKSEL    = REG_OFST(SYSCON, FRGCLKSEL),   /*!< Clock source selector of Fractional Rate Generator (FRG) */
+    CM_DMICLKSEL    = REG_OFST(SYSCON, DMICCLKSEL),  /*!< Clock source selector of Digital microphone (DMIC) */
+    CM_WKTCLKSEL    = REG_OFST(SYSCON, WKTCLKSEL),   /*!< Clock source selector of Wake-up Timer */
+    CM_ASYNCAPB
+} clock_sel_ofst_t;
+
+/*! @brief Clock attach definition */
+typedef enum _clock_attach_id
+{
+    kFRO12M_to_MAIN_CLK  = MUX_A(CM_MAINCLKSEL, 0), /*!< Select FRO 12M for main clock */
+    kOSC32K_to_MAIN_CLK  = MUX_A(CM_MAINCLKSEL, 1), /*!< Select OSC 32K for main clock */
+    kXTAL32M_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 2), /*!< Select XTAL 32M for main clock */
+    kFRO32M_to_MAIN_CLK  = MUX_A(CM_MAINCLKSEL, 3), /*!< Select FRO 32M for main clock */
+    kFRO48M_to_MAIN_CLK  = MUX_A(CM_MAINCLKSEL, 4), /*!< Select FRO 48M for main clock */
+    kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 5), /*!< Select external clock for main clock */
+    kFROM1M_to_MAIN_CLK  = MUX_A(CM_MAINCLKSEL, 6), /*!< Select FRO 1M for main clock */
+
+    kFRO32M_to_OSC32M_CLK  = MUX_A(CM_OSC32CLKSEL, 0), /*!< Select FRO 32M for OSC32KCLK and OSC32MCLK */
+    kXTAL32M_to_OSC32M_CLK = MUX_A(CM_OSC32CLKSEL, 1), /*!< Select XTAL 32M for OSC32KCLK and OSC32MCLK */
+    kFRO32K_to_OSC32K_CLK  = MUX_A(CM_OSC32CLKSEL, 2), /*!< Select FRO 32K for OSC32KCLK and OSC32MCLK */
+    kXTAL32K_to_OSC32K_CLK = MUX_A(CM_OSC32CLKSEL, 3), /*!< Select XTAL 32K for OSC32KCLK and OSC32MCLK */
+
+    kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Select main clock for CLKOUT */
+    kXTAL32K_to_CLKOUT  = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Select XTAL 32K for CLKOUT */
+    kFRO32K_to_CLKOUT   = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Select FRO 32K for CLKOUT */
+    kXTAL32M_to_CLKOUT  = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Select XTAL 32M for CLKOUT */
+    kDCDC_to_CLKOUT     = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Select DCDC for CLKOUT */
+    kFROM48M_to_CLKOUT  = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Select FRO 48M for CLKOUT */
+    kFRO1M_to_CLKOUT    = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Select FRO 1M for CLKOUT */
+    kNONE_to_CLKOUT     = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< No clock for CLKOUT */
+
+    kMAIN_CLK_to_SPIFI = MUX_A(CM_SPIFICLKSEL, 0), /*!< Select main clock for SPIFI */
+    kXTAL32M_to_SPIFI  = MUX_A(CM_SPIFICLKSEL, 1), /*!< Select XTAL 32M for SPIFI */
+    kFRO64M_to_SPIFI   = MUX_A(CM_SPIFICLKSEL, 2), /*!< Select FRO 64M for SPIFI */
+    kFRO48M_to_SPIFI   = MUX_A(CM_SPIFICLKSEL, 3), /*!< Select FRO 48M for SPIFI */
+
+    kXTAL32M_to_ADC_CLK = MUX_A(CM_ADCCLKSEL, 0), /*!< Select XTAL 32M for ADC */
+    kFRO12M_to_ADC_CLK  = MUX_A(CM_ADCCLKSEL, 1), /*!< Select FRO 12M for ADC */
+    kNONE_to_ADC_CLK    = MUX_A(CM_ADCCLKSEL, 2), /*!< No clock for ADC */
+
+    kOSC32M_to_USART_CLK  = MUX_A(CM_USARTCLKSEL, 0), /*!< Select OSC 32M for USART0 & 1 */
+    kFRO48M_to_USART_CLK  = MUX_A(CM_USARTCLKSEL, 1), /*!< Select FRO 48M for USART0 & 1 */
+    kFRG_CLK_to_USART_CLK = MUX_A(CM_USARTCLKSEL, 2), /*!< Select FRG clock for USART0 & 1 */
+    kNONE_to_USART_CLK    = MUX_A(CM_USARTCLKSEL, 3), /*!< No clock for USART0 & 1 */
+
+    kOSC32M_to_I2C_CLK = MUX_A(CM_I2CCLKSEL, 0), /*!< Select OSC 32M for I2C0, 1 and 2 */
+    kFRO48M_to_I2C_CLK = MUX_A(CM_I2CCLKSEL, 1), /*!< Select FRO 48M for I2C0, 1 and 2 */
+    kNONE_to_I2C_CLK   = MUX_A(CM_I2CCLKSEL, 2), /*!< No clock for I2C0, 1 and 2 */
+
+    kOSC32M_to_SPI_CLK = MUX_A(CM_SPICLKSEL, 0), /*!< Select OSC 32M for SPI0 & 1 */
+    kFRO48M_to_SPI_CLK = MUX_A(CM_SPICLKSEL, 1), /*!< Select FRO 48M for SPI0 & 1 */
+    kNONE_to_SPI_CLK   = MUX_A(CM_SPICLKSEL, 2), /*!< No clock for SPI0 & 1 */
+
+    kOSC32M_to_IR_CLK = MUX_A(CM_IRCLKSEL, 0), /*!< Select OSC 32M for Infra Red */
+    kFRO48M_to_IR_CLK = MUX_A(CM_IRCLKSEL, 1), /*!< Select FRO 48M for Infra Red */
+    kNONE_to_IR_CLK   = MUX_A(CM_IRCLKSEL, 2), /*!< No clock for Infra Red */
+
+    kOSC32M_to_PWM_CLK = MUX_A(CM_PWMCLKSEL, 0), /*!< Select OSC 32M for PWM */
+    kFRO48M_to_PWM_CLK = MUX_A(CM_PWMCLKSEL, 1), /*!< Select FRO 48M for PWM */
+    kNONE_to_PWM_CLK   = MUX_A(CM_PWMCLKSEL, 2), /*!< No clock for PWM */
+
+    kOSC32M_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 0), /*!< Select OSC 32M for Watchdog Timer */
+    kOSC32K_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 1), /*!< Select FRO 32K for Watchdog Timer */
+    kFRO1M_to_WDT_CLK  = MUX_A(CM_WDTCLKSEL, 2), /*!< Select FRO 1M for Watchdog Timer */
+
+    kMAIN_CLK_to_FRG_CLK = MUX_A(CM_FRGCLKSEL, 0), /*!< Select main clock for FRG */
+    kOSC32M_to_FRG_CLK   = MUX_A(CM_FRGCLKSEL, 1), /*!< Select OSC 32M for FRG */
+    kFRO48M_to_FRG_CLK   = MUX_A(CM_FRGCLKSEL, 2), /*!< Select FRO 48M for FRG */
+    kNONE_to_FRG_CLK     = MUX_A(CM_FRGCLKSEL, 3), /*!< No clock for FRG */
+
+    kMAIN_CLK_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 0), /*!< Select main clock for DMIC */
+    kOSC32K_to_DMI_CLK   = MUX_A(CM_DMICLKSEL, 1), /*!< Select OSC 32K for DMIC */
+    kFRO48M_to_DMI_CLK   = MUX_A(CM_DMICLKSEL, 2), /*!< Select FRO 48M for DMIC */
+    kMCLK_to_DMI_CLK     = MUX_A(CM_DMICLKSEL, 3), /*!< Select external clock for DMIC */
+    kFRO1M_to_DMI_CLK    = MUX_A(CM_DMICLKSEL, 4), /*!< Select FRO 1M for DMIC */
+    kFRO12M_to_DMI_CLK   = MUX_A(CM_DMICLKSEL, 5), /*!< Select FRO 12M for DMIC */
+    kNONE_to_DMI_CLK     = MUX_A(CM_DMICLKSEL, 6), /*!< No clock for DMIC */
+
+    kOSC32K_to_WKT_CLK  = MUX_A(CM_WKTCLKSEL, 0),
+    kFRO1M_to_WKT_CLK   = MUX_A(CM_WKTCLKSEL, 1),
+    kNONE_to_WKT_CLK    = MUX_A(CM_WKTCLKSEL, 2),
+    kTESTCLK_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 3),
+
+    kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), /*!< Select main clock for Asynchronous APB */
+    kXTAL32M_to_ASYNC_APB  = MUX_A(CM_ASYNCAPB, 1), /*!< Select XTAL 32M for Asynchronous APB */
+    kFRO32M_to_ASYNC_APB   = MUX_A(CM_ASYNCAPB, 2), /*!< Select FRO 32M for Asynchronous APB */
+    kFRO48M_to_ASYNC_APB   = MUX_A(CM_ASYNCAPB, 3), /*!< Select FRO 48M for Asynchronous APB */
+    kNONE_to_NONE          = 0x80000000U,
+} clock_attach_id_t;
+
+/*  Clock dividers */
+#define FIRST_DIV_MEMBER SYSTICKCLKDIV
+#define CLOCK_DIV_OFST(member) offsetof(SYSCON_Type, member)
+
+/*! @brief Clock divider definition */
+typedef enum _clock_div_name
+{
+    kCLOCK_DivNone       = 0,
+    kCLOCK_DivSystickClk = (offsetof(SYSCON_Type, SYSTICKCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivWdtClk     = (offsetof(SYSCON_Type, WDTCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivIrClk      = (offsetof(SYSCON_Type, IRCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivAhbClk     = (offsetof(SYSCON_Type, AHBCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivClkout     = (offsetof(SYSCON_Type, CLKOUTDIV) / sizeof(uint32_t)),
+    kCLOCK_DivSpifiClk   = (offsetof(SYSCON_Type, SPIFICLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivAdcClk     = (offsetof(SYSCON_Type, ADCCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivRtcClk     = (offsetof(SYSCON_Type, RTCCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivDmicClk    = (offsetof(SYSCON_Type, DMICCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivRtc1HzClk  = (offsetof(SYSCON_Type, RTC1HZCLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivTraceClk   = (offsetof(SYSCON_Type, TRACECLKDIV) / sizeof(uint32_t)),
+    kCLOCK_DivFrg        = (offsetof(SYSCON_Type, FRGCTRL) / sizeof(uint32_t))
+} clock_div_name_t;
+
+/*! @brief Clock source selections for the Main Clock */
+typedef enum _main_clock_src
+{
+    kCLOCK_MainFro12M  = 0, /*!< FRO 12M for main clock */
+    kCLOCK_MainOsc32k  = 1, /*!< OSC 32K for main clock */
+    kCLOCK_MainXtal32M = 2, /*!< XTAL 32M for main clock */
+    kCLOCK_MainFro32M  = 3, /*!< FRO 32M for main clock */
+    kCLOCK_MainFro48M  = 4, /*!< FRO 48M for main clock */
+    kCLOCK_MainExtClk  = 5, /*!< External clock for main clock */
+    kCLOCK_MainFro1M   = 6, /*!< FRO 1M for main clock */
+} main_clock_src_t;
+
+/*! @brief Clock source selections for CLKOUT */
+typedef enum _clkout_clock_src
+{
+    kCLOCK_ClkoutMainClk  = 0, /*!< CPU & System Bus clock for CLKOUT */
+    kCLOCK_ClkoutXtal32k  = 1, /*!< XTAL 32K for CLKOUT */
+    kCLOCK_ClkoutFro32k   = 2, /*!< FRO 32K for CLKOUT */
+    kCLOCK_ClkoutXtal32M  = 3, /*!< XTAL 32M for CLKOUT */
+    kCLOCK_ClkoutDcDcTest = 4, /*!< DCDC Test for CLKOUT */
+    kCLOCK_ClkoutFro48M   = 5, /*!< FRO 48M for CLKOUT */
+    kCLOCK_ClkoutFro1M    = 6, /*!< FRO 1M for CLKOUT */
+    kCLOCK_ClkoutNoClock  = 7  /*!< No clock for CLKOUT */
+} clkout_clock_src_t;
+
+/*! @brief Clock source definition for Watchdog timer */
+typedef enum _wdt_clock_src
+{
+    kCLOCK_WdtOsc32MClk = 0, /*!< OSC 32M for WDT */
+    kCLOCK_WdtOsc32kClk = 1, /*!< OSC 32K for WDT */
+    kCLOCK_WdtFro1M     = 2, /*!< FRO 1M for WDT */
+    kCLOCK_WdtNoClock   = 3  /*!< No clock for WDT */
+} wdt_clock_src_t;
+
+/*! @brief Clock source definition for fractional divider */
+typedef enum _frg_clock_src
+{
+    kCLOCK_FrgMainClk   = 0, /*!< CPU & System Bus clock for FRG */
+    kCLOCK_FrgOsc32MClk = 1, /*!< OSC 32M clock for FRG */
+    kCLOCK_FrgFro48M    = 2, /*!< FRO 48M for FRG */
+    kCLOCK_FrgNoClock   = 3  /*!< No clock for FRG */
+} frg_clock_src_t;
+
+/*! @brief Clock source definition for the APB */
+typedef enum _apb_clock_src
+{
+    kCLOCK_ApbMainClk = 0, /*!< CPU & System Bus clock for APB bridge */
+    kCLOCK_ApbXtal32M = 1, /*!< XTAL 32M for APB bridge */
+    kCLOCK_ApbFro32M  = 2, /*!< FRO 32M for APB bridge */
+    kCLOCK_ApbFro48M  = 3  /*!< FRO 48M for APB bridge */
+} apb_clock_src_t;
+
+/*! @brief Clock source definition for frequency measure  */
+typedef enum _fmeas_clock_src
+{
+    kCLOCK_fmeasClkIn     = 0, /*!< Clock in for FMEAS */
+    kCLOCK_fmeasXtal32Mhz = 1, /*!< XTAL 32M for FMEAS */
+    kCLOCK_fmeasFRO1Mhz   = 2, /*!< FRO 1M for FMEAS */
+    kCLOCK_fmeasXtal32kHz = 3, /*!< XTAL 32K for FMEAS */
+    kCLOCK_fmeasMainClock = 4, /*!< CPU & System Bus clock for FMEAS */
+    kCLOCK_fmeasGPIO_0_4  = 5, /*!< GPIO0_4 input for FMEAS */
+    kCLOCK_fmeasGPIO_0_20 = 6, /*!< GPIO0_20 input for FMEAS */
+    kCLOCK_fmeasGPIO_0_16 = 7, /*!< GPIO0_16 input for FMEAS */
+    kCLOCK_fmeasGPIO_0_15 = 8, /*!< GPIO0_15 input for FMEAS */
+} fmeas_clock_src_t;
+
+/*! @brief Clock source selection for SPIFI */
+typedef enum _spifi_clock_src
+{
+    kCLOCK_SpifiMainClk = 0, /*!< CPU & System Bus clock for SPIFI */
+    kCLOCK_SpifiXtal32M = 1, /*!< XTAL 32M for SPIFI */
+    kCLOCK_SpifiFro64M  = 2, /*!< FRO 64M for SPIFI */
+    kCLOCK_SpifiFro48M  = 3, /*!< FRO 48M for SPIFI */
+    kCLOCK_SpifiNoClock = 4  /*!< No clock for SPIFI */
+} spifi_clock_src_t;
+
+/*! @brief Clock definition for ADC */
+typedef enum _adc_clock_src
+{
+    kCLOCK_AdcXtal32M = 0, /*!< XTAL 32MHz for ADC */
+    kCLOCK_AdcFro12M  = 1, /*!< FRO 12MHz for ADC */
+    kCLOCK_AdcNoClock = 2  /*!< No clock for ADC */
+} adc_clock_src_t;
+
+/*! @brief PWM Clock source selection values */
+typedef enum _pwm_clock_source
+{
+    kCLOCK_PWMOsc32Mclk = 0x0, /*!< 32MHz FRO or XTAL clock */
+    kCLOCK_PWMFro48Mclk = 0x1, /*!< FRO 48MHz clock */
+    kCLOCK_PWMNoClkSel  = 0x2, /*!< No clock selected - Shutdown functional
+                            PWM clock for power saving */
+    kCLOCK_PWMTestClk = 0x3,   /*!< Test clock input - Shutdown functional
+                              PWM clock for power saving */
+} pwm_clock_source_t;
+
+/*! @brief FRO clock selection values */
+typedef enum
+{
+    FRO12M_ENA = (1 << 0), /*!< FRO12M */
+    FRO32M_ENA = (1 << 1), /*!< FRO32M */
+    FRO48M_ENA = (1 << 2), /*!< FRO48M */
+    FRO64M_ENA = (1 << 3), /*!< FRO64M */
+    FRO96M_ENA = (1 << 4)  /*!< FRO96M */
+} Fro_ClkSel_t;
+
+/*! @brief Board specific constant capacitance characteristics
+ * Should be supplied by board manufacturer for best performance.
+ * Capacitances are expressed in hundreds of pF
+ */
+typedef struct
+{
+    uint32_t clk_XtalIecLoadpF_x100;    /*< XTAL Load capacitance */
+    uint32_t clk_XtalPPcbParCappF_x100; /*< XTAL PCB +ve parasitic capacitance */
+    uint32_t clk_XtalNPcbParCappF_x100; /*< XTAL PCB -ve parasitic capacitance */
+} ClockCapacitanceCompensation_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief	Obtains frequency of specified clock
+ * @param   clock_name_t  specify clock to be read
+ * @return	uint32_t      frequency
+ * @note
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clock);
+
+/**
+ * @brief	Selects clock source using <name>SEL register in syscon
+ * @param   clock_attach_id_t  specify clock mapping
+ * @return	none
+ * @note
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+
+/**
+ * @brief	Selects clock divider using <name>DIV register in syscon
+ * @param   clock_div_name_t  	specifies which DIV register we are accessing
+ * @param   uint32_t			specifies divisor
+ * @param	bool				true if a syscon clock reset should also be carried out
+ * @return	none
+ * @note
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
+
+/**
+ * @brief	Enables specific AHB clock channel
+ * @param   clock_ip_name_t  	specifies which peripheral clock we are controlling
+ * @return	none
+ * @note	clock_ip_name_t is a typedef clone of clock_name_t
+ */
+void CLOCK_EnableClock(clock_ip_name_t clk);
+
+/**
+ * @brief	Disables specific AHB clock channel
+ * @param   clock_ip_name_t  	specifies which peripheral clock we are controlling
+ * @return	none
+ * @note	clock_ip_name_t is a typedef clone of clock_name_t
+ */
+void CLOCK_DisableClock(clock_ip_name_t clk);
+
+/**
+ * @brief	Check if clock is enabled
+ * @param   clock_ip_name_t  	specifies which peripheral clock we are controlling
+ * @return  bool
+ * @note	clock_ip_name_t is a typedef clone of clock_name_t
+ */
+bool CLOCK_IsClockEnable(clock_ip_name_t clk);
+
+/**
+ * @brief	Obtains frequency of APB Bus clock
+ * @param   none
+ * @return	uint32_t      frequency
+ * @note
+ */
+uint32_t CLOCK_GetApbCLkFreq(void);
+
+void CLOCK_EnableAPBBridge(void);
+
+void CLOCK_DisableAPBBridge(void);
+
+/*! @brief      Return Frequency of Spifi Clock
+ *  @return     Frequency of Spifi.
+ */
+uint32_t CLOCK_GetSpifiClkFreq(void);
+
+/*! @brief   Delay execution by busy waiting
+ *  @param   delayUs delay duration in micro seconds
+ *  @return  none
+ */
+void CLOCK_uDelay(uint32_t delayUs);
+
+/**
+ * @brief	Sets default trim values for 32MHz XTAL
+ * @param   none
+ * @return	none
+ * @note    Has no effect if CLOCK_Xtal32M_Trim has been called
+ */
+void CLOCK_XtalBasicTrim(void);
+
+/**
+ * @brief   Sets board-specific trim values for 32MHz XTAL
+ * @param   XO_32M_OSC_CAP_Delta_x1000 capacitance correction in fF (femtoFarad)
+ * @param   capa_charac board 32M capacitance characteristics pointer
+ * @return  none
+ * @note    capa_charac must point to a struct set in board.c using
+ *          CLOCK_32MfXtalIecLoadpF    Load capacitance, pF
+ *          CLOCK_32MfXtalPPcbParCappF PCB +ve parasitic capacitance, pF
+ *          CLOCK_32MfXtalNPcbParCappF PCB -ve parasitic capacitance, pF
+ */
+void CLOCK_Xtal32M_Trim(int32_t XO_32M_OSC_CAP_Delta_x1000, const ClockCapacitanceCompensation_t *capa_charac);
+
+/**
+ * @brief   Sets board-specific trim values for 32kHz XTAL
+ * @param   XO_32k_OSC_CAP_Delta_x1000 capacitance correction in fF
+ * @param   capa_charac board 32k capacitance characteristics pointer
+ * @return  none
+ * @note    capa_charac must point to a struct set in board.c using
+ *          CLOCK_32kfXtalIecLoadpF    Load capacitance, pF
+ *          CLOCK_32kfXtalPPcbParCappF PCB +ve parasitic capacitance, pF
+ *          CLOCK_32kfXtalNPcbParCappF PCB -ve parasitic capacitance, pF
+ */
+void CLOCK_Xtal32k_Trim(int32_t XO_32k_OSC_CAP_Delta_x1000, const ClockCapacitanceCompensation_t *capa_charac);
+
+/**
+ * @brief	Enables and sets LDO for 32MHz XTAL
+ * @param   none
+ * @return	none
+ */
+void CLOCK_SetXtal32M_LDO(void);
+
+/**
+ * @brief	Waits for 32MHz XTAL to stabilise
+ * @param   u32AdditionalWait_us Additional wait after hardware indicates that
+ *                               stability has been reached
+ * @return	none
+ * @note    Operates as a tight loop. Worst case would be ~600ms
+ */
+void CLOCK_Xtal32M_WaitUntilStable(uint32_t u32AdditionalWait_us);
+
+/*!
+ * @brief Use DWT to delay at least for some time.
+ *  Please note that, this API will calculate the microsecond period with the maximum devices
+ *  supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
+ *  delay count was needed, please implement a new timer count to achieve this function.
+ *
+ * @param delay_us  Delay time in unit of microsecond.
+ */
+void SDK_DelayAtLeastUs(uint32_t delay_us);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */

third_party/nxp/JN5189/drivers/fsl_common.h

@@ -0,0 +1,620 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version 2.1.3. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE          0U      /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART          1U      /*!< Debug console based on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART        2U      /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI         3U      /*!< Debug console based on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC        4U      /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM      5U      /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART         6U      /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART        7U      /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART    8U      /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO           9U      /*!< Debug console based on SWO. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI = 29,                    /*!< Group number for CSI status codes */
+    kStatusGroup_MIPI_DSI = 30,               /*!< Group number for MIPI DSI status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C = 66,                /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_DCP = 67,                    /*!< Group number for DCP status codes.*/
+    kStatusGroup_MSCAN = 68,                  /*!< Group number for MSCAN status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */
+    kStatusGroup_PDM = 72,                    /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
+    kStatusGroup_SPDIF = 75,                  /*!< Group number for SPDIF status codes. */
+    kStatusGroup_LPC_MINISPI = 76,            /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT = 77,              /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP = 78,            /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_I3C = 79,                    /*!< Group number for I3C status codes */
+    kStatusGroup_LPC_I2C_1 = 97,              /*!< Group number for LPC_I2C_1 status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_SEMC = 100,                  /*!< Group number for SEMC status codes. */
+    kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+    kStatusGroup_IAP = 102,                   /*!< Group number for IAP status codes */
+
+    kStatusGroup_HAL_GPIO = 121,              /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART = 122,              /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER = 123,             /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI = 124,               /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C = 125,               /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH = 126,             /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM = 127,               /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG = 128,               /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_TIMERMANAGER = 135,          /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER = 136,         /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED = 137,                   /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON = 138,                /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM = 139,         /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL = 140,                 /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER = 141,           /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST = 142,                  /*!< Group number for List status codes. */
+    kStatusGroup_OSA = 143,                   /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK = 144,           /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG = 145,                   /*!< Group number for messaging status codes. */
+    kStatusGroup_SDK_OCOTP = 146,             /*!< Group number for OCOTP status codes. */
+    kStatusGroup_SDK_FLEXSPINOR = 147,        /*!< Group number for FLEXSPINOR status codes.*/
+    kStatusGroup_CODEC = 148,                 /*!< Group number for codec status codes. */
+};
+
+/*! @brief Generic status return codes. */
+enum
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * Macro guard for whether to use default weak IRQ implementation in drivers
+ */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http://supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+    _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
+#endif
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
+#endif
+#else
+#error Toolchain not supported
+#define SDK_ALIGN(var, alignbytes) var
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var
+#endif
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var
+#endif
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
+ * will be initialized to zero in system startup.
+ */
+/* @{ */
+#if (defined(__ICCARM__))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#endif
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#endif
+#elif(defined(__XCC__))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#endif
+#else
+#error Toolchain not supported.
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
+#endif
+/* @} */
+
+/*! @name Time sensitive region */
+/* @{ */
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+#else
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#else
+#error Toolchain not supported.
+#endif
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif(defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
+
+/*! @name Suppress fallthrough warning macro */
+/* For switch case code block, if case section ends without "break;" statement, there wil be
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ case section which misses "break;"statement.
+ */
+/* @{ */
+#if (defined(__GNUC__))
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough))
+#else
+#define SUPPRESS_FALL_THROUGH_WARNING()
+#endif /* defined(__GNUC__) */
+/* @} */
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+        extern "C"
+{
+#endif
+
+    /*!
+     * @brief Enable specific interrupt.
+     *
+     * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+     * levels. For example, there are NVIC and intmux. Here the interrupts connected
+     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+     * to NVIC first then routed to core.
+     *
+     * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+     *
+     * @param interrupt The IRQ number.
+     * @retval kStatus_Success Interrupt enabled successfully
+     * @retval kStatus_Fail Failed to enable the interrupt
+     */
+    static inline status_t EnableIRQ(IRQn_Type interrupt)
+    {
+        if (NotAvail_IRQn == interrupt)
+        {
+            return kStatus_Fail;
+        }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+        {
+            return kStatus_Fail;
+        }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_EnableIRQ(interrupt);
+#endif
+        return kStatus_Success;
+    }
+
+    /*!
+     * @brief Disable specific interrupt.
+     *
+     * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+     * levels. For example, there are NVIC and intmux. Here the interrupts connected
+     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+     * to NVIC first then routed to core.
+     *
+     * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+     *
+     * @param interrupt The IRQ number.
+     * @retval kStatus_Success Interrupt disabled successfully
+     * @retval kStatus_Fail Failed to disable the interrupt
+     */
+    static inline status_t DisableIRQ(IRQn_Type interrupt)
+    {
+        if (NotAvail_IRQn == interrupt)
+        {
+            return kStatus_Fail;
+        }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+        {
+            return kStatus_Fail;
+        }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
+    NVIC_DisableIRQ(interrupt);
+#endif
+        return kStatus_Success;
+    }
+
+    /*!
+     * @brief Disable the global IRQ
+     *
+     * Disable the global interrupt and return the current primask register. User is required to provided the primask
+     * register for the EnableGlobalIRQ().
+     *
+     * @return Current primask value.
+     */
+    static inline uint32_t DisableGlobalIRQ(void)
+    {
+#if defined (__XCC__)
+        return 0;
+#else
+#if defined(CPSR_I_Msk)
+        uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+        __disable_irq();
+
+        return cpsr;
+#else
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+#endif
+#endif
+    }
+
+    /*!
+     * @brief Enable the global IRQ
+     *
+     * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+     * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+     * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+     *
+     * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+     * DisableGlobalIRQ().
+     */
+    static inline void EnableGlobalIRQ(uint32_t primask)
+    {
+#if defined (__XCC__)
+#else
+#if defined(CPSR_I_Msk)
+        __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+    __set_PRIMASK(primask);
+#endif
+#endif
+    }
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+    /*!
+     * @brief install IRQ handler
+     *
+     * @param irq IRQ number
+     * @param irqHandler IRQ handler address
+     * @return The old IRQ handler address
+     */
+    uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+    /*!
+     * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+     *
+     * Enable the interrupt for wake-up from deep sleep mode.
+     * Some interrupts are typically used in sleep mode only and will not occur during
+     * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+     * those clocks (significantly increasing power consumption in the reduced power mode),
+     * making these wake-ups possible.
+     *
+     * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+     *
+     * @param interrupt The IRQ number.
+     */
+    void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+    /*!
+     * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+     *
+     * Disable the interrupt for wake-up from deep sleep mode.
+     * Some interrupts are typically used in sleep mode only and will not occur during
+     * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+     * those clocks (significantly increasing power consumption in the reduced power mode),
+     * making these wake-ups possible.
+     *
+     * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+     *
+     * @param interrupt The IRQ number.
+     */
+    void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+    /*!
+     * @brief Allocate memory with given alignment and aligned size.
+     *
+     * This is provided to support the dynamically allocated memory
+     * used in cache-able region.
+     * @param size The length required to malloc.
+     * @param alignbytes The alignment size.
+     * @retval The allocated memory.
+     */
+    void *SDK_Malloc(size_t size, size_t alignbytes);
+
+    /*!
+     * @brief Free memory.
+     *
+     * @param ptr The memory to be release.
+     */
+    void SDK_Free(void *ptr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */

third_party/nxp/JN5189/drivers/fsl_ctimer.c

@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_ctimer.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.ctimer"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The Timer instance
+ */
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to Timer bases for each instance. */
+static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to Timer clocks for each instance. */
+static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET))
+#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET
+/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */
+static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N;
+#else
+/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */
+static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
+#endif
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
+
+/*! @brief Pointers real ISRs installed by drivers for each instance. */
+static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
+
+/*! @brief Callback type installed by drivers for each instance. */
+static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
+
+/*! @brief Array to map timer instance to IRQ number. */
+static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
+{
+    uint32_t instance;
+    uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ctimerArrayCount; instance++)
+    {
+        if (s_ctimerBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ctimerArrayCount);
+
+    return instance;
+}
+
+/*!
+ * brief Ungates the clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application before using the driver.
+ *
+ * param base   Ctimer peripheral base address
+ * param config Pointer to the user configuration structure.
+ */
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the timer clock*/
+    CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+/* Reset the module. */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET))
+    RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
+
+/* Setup the cimer mode and count select */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
+    base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
+#endif
+    /* Setup the timer prescale value */
+    base->PR = CTIMER_PR_PRVAL(config->prescale);
+}
+
+/*!
+ * brief Gates the timer clock.
+ *
+ * param base Ctimer peripheral base address
+ */
+void CTIMER_Deinit(CTIMER_Type *base)
+{
+    uint32_t index = CTIMER_GetInstance(base);
+    /* Stop the timer */
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the timer clock*/
+    CLOCK_DisableClock(s_ctimerClocks[index]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable IRQ at NVIC Level */
+    DisableIRQ(s_ctimerIRQ[index]);
+}
+
+/*!
+ * brief  Fills in the timers configuration structure with the default settings.
+ *
+ * The default values are:
+ * code
+ *   config->mode = kCTIMER_TimerMode;
+ *   config->input = kCTIMER_Capture_0;
+ *   config->prescale = 0;
+ * endcode
+ * param config Pointer to the user configuration structure.
+ */
+void CTIMER_GetDefaultConfig(ctimer_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    /* Run as a timer */
+    config->mode = kCTIMER_TimerMode;
+    /* This field is ignored when mode is timer */
+    config->input = kCTIMER_Capture_0;
+    /* Timer counter is incremented on every APB bus clock */
+    config->prescale = 0;
+}
+
+/*!
+ * brief Configures the PWM signal parameters.
+ *
+ * Enables PWM mode on the match channel passed in and will then setup the match value
+ * and other match parameters to generate a PWM signal.
+ * This function will assign match channel 3 to set the PWM cycle.
+ *
+ * note When setting PWM output from multiple output pins, all should use the same PWM
+ * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
+ *
+ * param base             Ctimer peripheral base address
+ * param matchChannel     Match pin to be used to output the PWM signal
+ * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
+ * param pwmFreq_Hz       PWM signal frequency in Hz
+ * param srcClock_Hz      Timer counter clock in Hz
+ * param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
+ *                         if it is 0 then no interrupt is generated
+ *
+ * return kStatus_Success on success
+ *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ */
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt)
+{
+    assert(pwmFreq_Hz > 0);
+
+    uint32_t reg;
+    uint32_t period, pulsePeriod = 0;
+    uint32_t timerClock = srcClock_Hz / (base->PR + 1);
+    uint32_t index      = CTIMER_GetInstance(base);
+
+    if (matchChannel == kCTIMER_Match_3)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Enable PWM mode on the channel */
+    base->PWMC |= (1U << matchChannel);
+
+    /* Clear the stop, reset and interrupt bits for this channel */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+
+    /* If call back function is valid then enable match interrupt for the channel */
+    if (enableInt)
+    {
+        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    }
+
+    /* Reset the counter when match on channel 3 */
+    reg |= CTIMER_MCR_MR3R_MASK;
+
+    base->MCR = reg;
+
+    /* Calculate PWM period match value */
+    period = (timerClock / pwmFreq_Hz) - 1;
+
+    /* Calculate pulse width match value */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Match on channel 3 will define the PWM period */
+    base->MR[kCTIMER_Match_3] = period;
+
+    /* This will define the PWM pulse period */
+    base->MR[matchChannel] = pulsePeriod;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If call back function is valid then enable interrupt and update the call back function */
+    if (enableInt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures the PWM signal parameters.
+ *
+ * Enables PWM mode on the match channel passed in and will then setup the match value
+ * and other match parameters to generate a PWM signal.
+ * This function will assign match channel 3 to set the PWM cycle.
+ *
+ * note When setting PWM output from multiple output pins, all should use the same PWM
+ * period
+ *
+ * param base             Ctimer peripheral base address
+ * param matchChannel     Match pin to be used to output the PWM signal
+ * param pwmPeriod        PWM period match value
+ * param pulsePeriod      Pulse width match value
+ * param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
+ *                         if it is 0 then no interrupt is generated
+ *
+ * return kStatus_Success on success
+ *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period
+ */
+status_t CTIMER_SetupPwmPeriod(
+    CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt)
+{
+/* Some CTimers only have 16bits , so the value is limited*/
+#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B
+    assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU)));
+#endif
+
+    uint32_t reg;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    if (matchChannel == kCTIMER_Match_3)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Enable PWM mode on the channel */
+    base->PWMC |= (1U << matchChannel);
+
+    /* Clear the stop, reset and interrupt bits for this channel */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+
+    /* If call back function is valid then enable match interrupt for the channel */
+    if (enableInt)
+    {
+        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    }
+
+    /* Reset the counter when match on channel 3 */
+    reg |= CTIMER_MCR_MR3R_MASK;
+
+    base->MCR = reg;
+
+    /* Match on channel 3 will define the PWM period */
+    base->MR[kCTIMER_Match_3] = pwmPeriod;
+
+    /* This will define the PWM pulse period */
+    base->MR[matchChannel] = pulsePeriod;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If call back function is valid then enable interrupt and update the call back function */
+    if (enableInt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Updates the duty cycle of an active PWM signal.
+ *
+ * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution.
+ *
+ * param base             Ctimer peripheral base address
+ * param matchChannel     Match pin to be used to output the PWM signal
+ * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
+ */
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
+{
+    uint32_t pulsePeriod = 0, period;
+
+    /* Match channel 3 defines the PWM period */
+    period = base->MR[kCTIMER_Match_3];
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * dutyCyclePercent) / 100;
+
+    /* For 0% dutycyle, make pulse period greater than period so the event will never occur */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Update dutycycle */
+    base->MR[matchChannel] = pulsePeriod;
+}
+
+/*!
+ * brief Setup the match register.
+ *
+ * User configuration is used to setup the match value and action to be taken when a match occurs.
+ *
+ * param base         Ctimer peripheral base address
+ * param matchChannel Match register to configure
+ * param config       Pointer to the match configuration structure
+ */
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
+{
+/* Some CTimers only have 16bits , so the value is limited*/
+#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B
+    assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU));
+#endif
+    uint32_t reg;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the counter operation when a match on this channel occurs */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    base->MCR = reg;
+
+    reg = base->EMR;
+    /* Set the match output operation when a match on this channel occurs */
+    reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
+    reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
+
+    /* Set the initial state of the EM bit/output */
+    reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
+    reg |= (uint32_t)config->outPinInitState << matchChannel;
+    base->EMR = reg;
+
+    /* Set the match value */
+    base->MR[matchChannel] = config->matchValue;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If interrupt is enabled then enable interrupt and update the call back function */
+    if (config->enableInterrupt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+}
+
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
+/*!
+ * brief Setup the capture.
+ *
+ * param base      Ctimer peripheral base address
+ * param capture   Capture channel to configure
+ * param edge      Edge on the channel that will trigger a capture
+ * param enableInt Flag to enable channel interrupts, if enabled then the registered call back
+ *                  is called upon capture
+ */
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt)
+{
+    uint32_t reg   = base->CCR;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the capture edge */
+    reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
+    reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
+    /* If call back function is valid then enable capture interrupt for the channel and update the call back function */
+    if (enableInt)
+    {
+        reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+    base->CCR = reg;
+}
+#endif
+
+/*!
+ * brief Register callback.
+ *
+ * param base      Ctimer peripheral base address
+ * param cb_func   callback function
+ * param cb_type   callback function type, singular or multiple
+ */
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
+{
+    uint32_t index            = CTIMER_GetInstance(base);
+    s_ctimerCallback[index]   = cb_func;
+    ctimerCallbackType[index] = cb_type;
+}
+
+void CTIMER_GenericIRQHandler(uint32_t index)
+{
+    uint32_t int_stat, i, mask;
+    /* Get Interrupt status flags */
+    int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
+    /* Clear the status flags that were set */
+    CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
+    if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
+    {
+        if (s_ctimerCallback[index][0])
+        {
+            s_ctimerCallback[index][0](int_stat);
+        }
+    }
+    else
+    {
+#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE
+        for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++)
+#else
+#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
+        for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
+#else
+        for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++)
+#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
+#endif
+        {
+            mask = 0x01 << i;
+            /* For each status flag bit that was set call the callback function if it is valid */
+            if ((int_stat & mask) && (s_ctimerCallback[index][i]))
+            {
+                s_ctimerCallback[index][i](int_stat);
+            }
+        }
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(CTIMER0)
+void CTIMER0_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(0);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(CTIMER1)
+void CTIMER1_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(1);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(CTIMER2)
+void CTIMER2_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(2);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(CTIMER3)
+void CTIMER3_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(3);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(CTIMER4)
+void CTIMER4_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(4);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif

third_party/nxp/JN5189/drivers/fsl_ctimer.h

@@ -0,0 +1,488 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_CTIMER_H_
+#define _FSL_CTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup ctimer
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
+/*@}*/
+
+/*! @brief List of Timer capture channels */
+typedef enum _ctimer_capture_channel
+{
+    kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
+    kCTIMER_Capture_1,      /*!< Timer capture channel 1 */
+    kCTIMER_Capture_2,      /*!< Timer capture channel 2 */
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+    kCTIMER_Capture_3 /*!< Timer capture channel 3 */
+#endif                /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
+} ctimer_capture_channel_t;
+
+/*! @brief List of capture edge options */
+typedef enum _ctimer_capture_edge
+{
+    kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
+    kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
+    kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
+} ctimer_capture_edge_t;
+
+/*! @brief List of Timer match registers */
+typedef enum _ctimer_match
+{
+    kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
+    kCTIMER_Match_1,      /*!< Timer match register 1 */
+    kCTIMER_Match_2,      /*!< Timer match register 2 */
+    kCTIMER_Match_3       /*!< Timer match register 3 */
+} ctimer_match_t;
+
+/*! @brief List of output control options */
+typedef enum _ctimer_match_output_control
+{
+    kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
+    kCTIMER_Output_Clear,         /*!< Clear the EM bit/output to 0 */
+    kCTIMER_Output_Set,           /*!< Set the EM bit/output to 1 */
+    kCTIMER_Output_Toggle         /*!< Toggle the EM bit/output */
+} ctimer_match_output_control_t;
+
+/*! @brief List of Timer modes */
+typedef enum _ctimer_timer_mode
+{
+    kCTIMER_TimerMode = 0U,     /* TC is incremented every rising APB bus clock edge */
+    kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
+    kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
+    kCTIMER_IncreaseOnBothEdge  /* TC is incremented on both edges of input signal */
+} ctimer_timer_mode_t;
+
+/*! @brief List of Timer interrupts */
+typedef enum _ctimer_interrupt_enable
+{
+    kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */
+    kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */
+    kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */
+    kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
+    kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
+    kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
+    kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+    kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
+#endif                                                       /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
+#endif
+} ctimer_interrupt_enable_t;
+
+/*! @brief List of Timer flags */
+typedef enum _ctimer_status_flags
+{
+    kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */
+    kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */
+    kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */
+    kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
+    kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
+    kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
+    kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
+#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
+    kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
+#endif                                            /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
+#endif
+} ctimer_status_flags_t;
+
+typedef void (*ctimer_callback_t)(uint32_t flags);
+
+/*! @brief Callback type when registering for a callback. When registering a callback
+ *         an array of function pointers is passed the size could be 1 or 8, the callback
+ *         type will tell that.
+ */
+typedef enum
+{
+    kCTIMER_SingleCallback,  /*!< Single Callback type where there is only one callback for the timer.
+                                 based on the status flags different channels needs to be handled differently */
+    kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel.
+                                 for both match/capture */
+} ctimer_callback_type_t;
+
+/*!
+ * @brief Match configuration
+ *
+ * This structure holds the configuration settings for each match register.
+ */
+typedef struct _ctimer_match_config
+{
+    uint32_t matchValue;                      /*!< This is stored in the match register */
+    bool enableCounterReset;                  /*!< true: Match will reset the counter
+                                                   false: Match will not reser the counter */
+    bool enableCounterStop;                   /*!< true: Match will stop the counter
+                                                   false: Match will not stop the counter */
+    ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
+    bool outPinInitState;                     /*!< Initial value of the EM bit/output */
+    bool enableInterrupt;                     /*!< true: Generate interrupt upon match
+                                                   false: Do not generate interrupt on match */
+
+} ctimer_match_config_t;
+
+/*!
+ * @brief Timer configuration structure
+ *
+ * This structure holds the configuration settings for the Timer peripheral. To initialize this
+ * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _ctimer_config
+{
+    ctimer_timer_mode_t mode;       /*!< Timer mode */
+    ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
+                                        modes that rely on this input signal to increment TC */
+    uint32_t prescale;              /*!< Prescale value */
+} ctimer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application before using the driver.
+ *
+ * @param base   Ctimer peripheral base address
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
+
+/*!
+ * @brief Gates the timer clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+void CTIMER_Deinit(CTIMER_Type *base);
+
+/*!
+ * @brief  Fills in the timers configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ *   config->mode = kCTIMER_TimerMode;
+ *   config->input = kCTIMER_Capture_0;
+ *   config->prescale = 0;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_GetDefaultConfig(ctimer_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name PWM setup operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Enables PWM mode on the match channel passed in and will then setup the match value
+ * and other match parameters to generate a PWM signal.
+ * This function will assign match channel 3 to set the PWM cycle.
+ *
+ * @note When setting PWM output from multiple output pins, all should use the same PWM
+ * period
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param pwmPeriod        PWM period match value
+ * @param pulsePeriod      Pulse width match value
+ * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
+ *                         if it is 0 then no interrupt is generated
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period
+ */
+status_t CTIMER_SetupPwmPeriod(
+    CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt);
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Enables PWM mode on the match channel passed in and will then setup the match value
+ * and other match parameters to generate a PWM signal.
+ * This function will assign match channel 3 to set the PWM cycle.
+ *
+ * @note When setting PWM output from multiple output pins, all should use the same PWM
+ * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
+ * @param pwmFreq_Hz       PWM signal frequency in Hz
+ * @param srcClock_Hz      Timer counter clock in Hz
+ * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
+ *                         if it is 0 then no interrupt is generated
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ */
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt);
+
+/*!
+ * @brief Updates the pulse period of an active PWM signal.
+ *
+ * @param base         Ctimer peripheral base address
+ * @param matchChannel Match pin to be used to output the PWM signal
+ * @param pulsePeriod  New PWM pulse width match value
+ */
+static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod)
+{
+    /* Update PWM pulse period match value */
+    base->MR[matchChannel] = pulsePeriod;
+}
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution.
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
+ */
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
+
+/*! @}*/
+
+/*!
+ * @brief Setup the match register.
+ *
+ * User configuration is used to setup the match value and action to be taken when a match occurs.
+ *
+ * @param base         Ctimer peripheral base address
+ * @param matchChannel Match register to configure
+ * @param config       Pointer to the match configuration structure
+ */
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
+
+/*!
+ * @brief Setup the capture.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param capture   Capture channel to configure
+ * @param edge      Edge on the channel that will trigger a capture
+ * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
+ *                  is called upon capture
+ */
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt);
+
+/*!
+ * @brief Get the timer count value from TC register.
+ *
+ * @param  base  Ctimer peripheral base address.
+ * @return       return the timer count value.
+ */
+static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base)
+{
+    return (base->TC);
+}
+
+/*!
+ * @brief Register callback.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param cb_func   callback function
+ * @param cb_type   callback function type, singular or multiple
+ */
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Enable match interrupts */
+    base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
+
+/* Enable capture interrupts */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
+    base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+                         | CTIMER_CCR_CAP3I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
+                        );
+#endif
+}
+
+/*!
+ * @brief Disables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Disable match interrupts */
+    base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK));
+
+/* Disable capture interrupts */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
+    base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+                           | CTIMER_CCR_CAP3I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
+                           ));
+#endif
+}
+
+/*!
+ * @brief Gets the enabled Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::ctimer_interrupt_enable_t
+ */
+static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
+{
+    uint32_t enabledIntrs = 0;
+
+    /* Get all the match interrupts enabled */
+    enabledIntrs =
+        base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
+
+/* Get all the capture interrupts enabled */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
+    enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+                                 | CTIMER_CCR_CAP3I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
+                                );
+#endif
+
+    return enabledIntrs;
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::ctimer_status_flags_t
+ */
+static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
+{
+    return base->IR;
+}
+
+/*!
+ * @brief Clears the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::ctimer_status_flags_t
+ */
+static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
+{
+    base->IR = mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Counter Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StartTimer(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CEN_MASK;
+}
+
+/*!
+ * @brief Stops the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StopTimer(CTIMER_Type *base)
+{
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Reset the counter.
+ *
+ * The timer counter and prescale counter are reset on the next positive edge of the APB clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_Reset(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CRST_MASK;
+    base->TCR &= ~CTIMER_TCR_CRST_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CTIMER_H_ */

third_party/nxp/JN5189/drivers/fsl_debug_console.h

@@ -0,0 +1,173 @@
+/*
+* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+* Copyright 2016-2019 NXP
+* All rights reserved.
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/*
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ *   - [flags] :'-', '+', '#', ' ', '0'
+ *   - [width]:  number (0,1...)
+ *   - [.precision]: number (0,1...)
+ *   - [length]: do not support
+ *   - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ *   - [*]: is supported.
+ *   - [width]: number (0,1...)
+ *   - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ *   - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+
+/*
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE 1U
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#endif
+
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#else /* Select printf, scanf, putchar, getchar of toolchain. */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+/*!
+ * @brief Initializes the the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral,
+ * frequency of peripheral source clock, and base address at the specified baud rate.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param baseAddr      Indicates the address of the peripheral used to send debug messages.
+ * @param baudRate      The desired baud rate in bits per second.
+ * @param device        Low level device type for the debug console, can be one of the following.
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_UART,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC.
+ * @param clkSrcFreq    Frequency of peripheral source clock.
+ *
+ * @return              Indicates whether initialization was successful or not.
+ * @retval kStatus_Success          Execution successfully
+ * @retval kStatus_Fail             Execution failure
+ * @retval kStatus_InvalidArgument  Invalid argument existed
+ */
+status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * base address and at the specified baud rate.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param   fmt_s Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *fmt_s, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param   ch Character to be written.
+ * @return  Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @param   fmt_ptr Format control string.
+ * @return  Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *fmt_ptr, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */

third_party/nxp/JN5189/drivers/fsl_flash.c

@@ -0,0 +1,526 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flash.h"
+#include "rom_api.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.jn_flash"
+#endif
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define MAX_ERASE_LENGTH (FLASH_PAGE_SIZE * 100)
+
+/*
+ * Macros below participate to the Flash checksum calculation.
+ * FLASH_CheckSum implements CMD_CHECKSUM function of the flash controller for whole pages strictly.
+ * SW is required when needing to program a checksums or check over areas smaller than a whole flash page.
+ */
+#define RSHIFT_128BIT(_WORD_, _SHIFT_)     \
+    _WORD_[0] >>= (uint32_t)_SHIFT_;\
+    _WORD_[0] |= (uint32_t)((_WORD_[1] & (uint32_t)((1<<_SHIFT_)-1)) << (uint32_t)(32-_SHIFT_));\
+    _WORD_[1] >>=(uint32_t)_SHIFT_;\
+    _WORD_[1] |= (uint32_t)((_WORD_[2] & (uint32_t)((1<<_SHIFT_)-1)) << (uint32_t)(32-_SHIFT_));\
+    _WORD_[2] >>=(uint32_t)_SHIFT_;\
+    _WORD_[2] |= (uint32_t)((_WORD_[3] & (uint32_t)((1<<_SHIFT_)-1)) << (uint32_t)(32-_SHIFT_));\
+    _WORD_[3] >>=(uint32_t)_SHIFT_;
+
+#define PARITY(_WORD_) \
+          (uint32_t)((_WORD_ & (uint32_t)(1<<0UL))>>0UL) \
+        ^ (uint32_t)((_WORD_ & (uint32_t)(1<<2UL))>>2UL) \
+        ^ (uint32_t)((_WORD_ & (uint32_t)(1<<27UL))>>27UL)\
+        ^ (uint32_t)((_WORD_ & (uint32_t)(1<<29UL))>>29UL)
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+flash_config_t gFlashConfig;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/**
+ * @brief      Enable the FLASH
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ *
+ * @return     Nothing
+ */
+void FLASH_Init(FLASH_Type *pFLASH)
+{
+    int status;
+    /* From Flash Adapter */
+    gFlashConfig.PFlashSectorSize = FLASH_PAGE_SIZE;
+    ROM_GetFlash(&gFlashConfig.PFlashBlockBase, &gFlashConfig.PFlashTotalSize);
+
+    pFLASH->CMD = FLASH_CMD_INIT;
+
+    status = FLASH_Wait(pFLASH);
+    /* Loop if the flash controller detects an unrecoverable error */
+    /* That should have been caught by the ROM code but might not !*/
+    if (status & FLASH_FAIL)
+    {
+        while (1);
+    }
+}
+
+/**
+ * @brief      Power down the FLASH
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ *
+ * @return     Nothing
+ */
+void FLASH_Powerdown(FLASH_Type *pFLASH)
+{
+    pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+    pFLASH->CMD = FLASH_CMD_POWERDOWN;
+
+    FLASH_Wait(pFLASH);
+}
+
+/**
+ * @brief      Wait for FLASH command to complete
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Wait(FLASH_Type *pFLASH)
+{
+    while (!(pFLASH->INT_STATUS & FLASH_DONE));
+    /* mask out ECC_ERR bit that may raise independantly from flash commands */
+    return (pFLASH->INT_STATUS & ~FLASH_ECC_ERR);
+}
+
+/**
+ * @brief      Return unfiltered FLASH INT_STATUS.
+ * In normal operation FLASH_DONE rises systematically but other status bits
+ * may rise at the same time or have risen before to notify of an error.
+ * Usually testing the value returned by FLASH_Wait is sufficionet but in some special
+ * cases the raw value may be needed.
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral.
+ *
+ * @return     INT_STATUS raw value.
+ * @see flash_status_t
+ */
+int FLASH_GetStatus(FLASH_Type *pFLASH)
+{
+    return pFLASH->INT_STATUS;
+}
+
+/**
+ * @brief      Erase page
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Start address with page to inspect
+ * @param[in]  pu8End End address (included in check)
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Erase(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End)
+{
+    int status = 0;
+
+    uint32_t erase_length = pu8End - pu8Start;
+
+    while (erase_length > 0)
+    {
+        pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+        if (erase_length > MAX_ERASE_LENGTH)
+        {
+            pu8End = pu8Start + MAX_ERASE_LENGTH - 1;
+            erase_length -= MAX_ERASE_LENGTH;
+        }
+        else
+        {
+            pu8End       = pu8Start + erase_length;
+            erase_length = 0;
+        }
+
+        /* Set end address */
+        *pu8End = 0xAA;
+
+        /* Set start address */
+        *pu8Start = 0xBB;
+
+        pu8Start = pu8End + 1;
+
+        pFLASH->CMD = FLASH_CMD_ERASE_RANGE;
+
+        status = FLASH_Wait(pFLASH);
+    }
+
+    return status;
+}
+
+/**
+ * @brief      Erase multiple pages
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  u32StartPage Index of page to start erasing from
+ * @param[in]  u32PageCount Number of pages to erase
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_ErasePages(FLASH_Type *pFLASH, uint32_t u32StartPage, uint32_t u32PageCount)
+{
+    uint8_t *pu8Start = (uint8_t *)(FLASH_PAGE_SIZE * u32StartPage);
+    uint8_t *pu8End   = (pu8Start + FLASH_PAGE_SIZE * u32PageCount) - 1;
+
+    return FLASH_Erase(pFLASH, pu8Start, pu8End);
+}
+
+/**
+ * @brief      Page Blank check
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Start address with page to inspect
+ * @param[in]  pu8End End address (included in check)
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_BlankCheck(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End)
+{
+    pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+    /* Set end address */
+    *pu8End = 0xAA;
+
+    /* Set start address */
+    *pu8Start = 0xBB;
+
+    pFLASH->CMD = FLASH_CMD_BLANK_CHECK;
+
+    return FLASH_Wait(pFLASH);
+}
+
+/**
+ * @brief      Margin Check
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Start address with page to inspect
+ * @param[in]  pu8End End address (included in check)
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_MarginCheck(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End)
+{
+    pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+    /* Set end address */
+    *pu8End = 0xAA;
+
+    /* Set start address */
+    *pu8Start = 0xBB;
+
+    pFLASH->CMD = FLASH_CMD_MARGIN_CHECK;
+
+    return FLASH_Wait(pFLASH);
+}
+
+/**
+ * @brief      Program page
+ *
+ * @param[in]  pFLASH Pointer to selected FLASH peripheral
+ * @param[out] pu32Start Pointer location that must be programmed in flash
+ * @param[in]  pu32Data Pointer to source buffer being written to flash
+ * @param[in]  u32Length Number of bytes to be programmed
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Program(FLASH_Type *pFLASH, uint32_t *pu32Start, uint32_t *pu32Data, uint32_t u32Length)
+{
+    int status = 0;
+
+    uint32_t end  = (uint32_t)pu32Start + u32Length;
+
+    uint32_t padding  = (FLASH_PAGE_SIZE - (end & (FLASH_PAGE_SIZE-1))) & (FLASH_PAGE_SIZE-1);
+
+    pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+    pFLASH->AUTOPROG = FLASH_AUTO_PAGE;
+
+    memcpy(pu32Start, pu32Data, u32Length);
+
+    while (padding-- > 0)
+    {
+        *(uint8_t*)end ++ = 0;
+    }
+
+    status = FLASH_Wait(pFLASH);
+
+    pFLASH->AUTOPROG = FLASH_AUTO_OFF;
+
+    return status;
+}
+
+/**
+ * @brief      Page Checksum
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Pointer to data within starting page  page checksum must be computed
+ * @param[in]  pu8End Pointer to data whose page is the last of the checksum calculation
+ * @param[out] au32Checksum Four 32bit word array to store checksum calculation result
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Checksum(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End, uint32_t au32Checksum[4])
+{
+    int status;
+    pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+    /* Set end address */
+    *pu8End = 0xAA;
+
+    /* Set start address */
+    *pu8Start = 0xBB;
+
+    pFLASH->CMD = FLASH_CMD_CHECKSUM;
+
+    status = FLASH_Wait(pFLASH);
+
+    au32Checksum[0] = pFLASH->DATAW[0];
+    au32Checksum[1] = pFLASH->DATAW[1];
+    au32Checksum[2] = pFLASH->DATAW[2];
+    au32Checksum[3] = pFLASH->DATAW[3];
+
+    return status;
+}
+
+/**
+ * @brief      Read flash word (16 byte worth of data)
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Pointer to data to be read
+ * @param[in]  u32ReadMode Read mode see also flash_read_mode_t
+ * @param[out] au32Data Four 32bit word array to store read result
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Read(FLASH_Type *pFLASH, uint8_t *pu8Start, uint32_t u32ReadMode, uint32_t au32Data[4])
+{
+    int status;
+    pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+    /* Set start address */
+    *pu8Start = 0xBB;
+
+    /* Set read mode */
+    pFLASH->DATAW[0] = u32ReadMode;
+
+    pFLASH->CMD = FLASH_CMD_READ_SINGLE_WORD;
+
+    status = FLASH_Wait(pFLASH);
+
+    au32Data[0] = pFLASH->DATAW[0];
+    au32Data[1] = pFLASH->DATAW[1];
+    au32Data[2] = pFLASH->DATAW[2];
+    au32Data[3] = pFLASH->DATAW[3];
+
+    return status;
+}
+
+/*
+* Details on the fields that can be updated through the FLASH_CMD_SET_READ_MODE cmd.
+* bit 31   : prefetch enable
+* bit 30   : ignore hprot[0] and assume that all accesses are code accesses
+* bit 29-28: 00: hprot[3] specifies whether an access is cacheable
+*            01: reserved
+*            10: hprot[3] ignored, all accesses are not cacheable
+*            11: hprot[3] ignored, all accesses are cacheable
+* bit 27-8 : reserved
+* bit 7    : ewle read mode active. Default value after reset is: 0
+* bit 6-4  : number of extra precharge states.
+* bit 3-0  : number of extra evaluation states.
+*
+* After reset, the only value field set is the "number of extra evaluation states" field. In other words, if you want to
+* return to the default values, you shall write DEFAULT_READ_MODE to DATAW[0]
+*/
+#define DEFAULT_READ_MODE_VAL          0x00000000
+#define EWLE_MODE_MASK                 0x80
+
+/**
+ * @brief      Configure the flash wait state depending of the elwe mode and CPU frequency.
+ * When the CPU clock frequency is decreased, the Set Read command shall be called after the frequency change.
+ * When the CPU clock frequency is increased, the Set Read command shall be called before the frequency change.
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ * @param      freq_48M_not_32M CPU clock frequency @48MHz - lower or equal to 32Mhz if 0
+ *
+ * @return     Nothing
+ */
+void FLASH_SetReadMode(FLASH_Type *pFLASH, bool cpu_freq_48M_not_32M)
+{
+   int flash_ws = DEFAULT_READ_MODE_VAL;
+
+   pFLASH->INT_CLR_STATUS = FLASH_STAT_ALL;
+
+   flash_ws += cpu_freq_48M_not_32M ? 1 : 0;
+
+   pFLASH->DATAW[0] = (EWLE_MODE_MASK | flash_ws);
+
+   pFLASH->CMD = FLASH_CMD_SET_READ_MODE;
+
+   /* no need to wait until command is completed: further accesses are stalled
+    * until the command is completed. */
+   //status = FLASH_Wait(pFLASH);
+}
+
+/**
+ * @brief      Calculate checksum using the same checksum algorithm as the CMD_CHECKSUM implementation of the
+ * Flash controller. When executed over a 512 byte page (page size) must return the same value as FLASH_Checksum.
+ *
+ * @param[in]  input Pointer to data over which checksum calculation must be executed.
+ * @param[in]  nb_128b_words Number of 16 byte words on flash.
+ * @param[out] misr Pointer on a four 32bit word array to store calculated checksum.
+ * @param[in]  init Set to true to clear the misr buffer.
+ *
+ * @return     Nothing
+ */
+void FLASH_CalculateChecksum(const uint32_t *input,
+                            size_t nb_128b_words,
+                            uint32_t* misr,
+                            int init)
+{
+    int i;
+
+    if (init)
+    {
+        for (i = 0; i < 4; i++)
+        {
+            misr[i] = 0;
+        }
+    }
+
+    for (i = 0; i < nb_128b_words*4; )
+    {
+        int cy;
+
+        /* Compute carry */
+        cy = PARITY(misr[0]);
+        /* Shift right the 128 bits */
+        RSHIFT_128BIT(misr, 1UL);
+        /* Let Carry become the MISR[127] bit */
+        misr[3] ^= (uint32_t)((cy&1UL) << 31);
+
+        /* Xor with 128 bit word */
+        misr[0] ^= input[i++];
+        misr[1] ^= input[i++];
+        misr[2] ^= input[i++];
+        misr[3] ^= input[i++];
+    }
+
+}
+
+/*
+ * Expected values for Config page checksum and GPO checksum.
+ */
+const uint32_t CONFIG_PAGE_CHSUM[4] = {0x11112222U, 0x33334444U, 0x55556666U, 0x77778888U};
+const uint32_t GPO_CHKSUM[4] =         {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U};
+
+/**
+ * @brief      Calculate checksum over page (N-2) aka CONFIG page and check it matches the expected value.
+ *
+ * @param[in]  page_buffer Pointer to data over which checksum calculation must be executed.
+ * @param[out] misr Pointer on a four 32bit word array to store calculated checksum.
+ *             Note: this buffer is only useful for debugging purposes.
+ *
+ * @return Result of the page checksum verification:
+ *         -  0: Verification successfully.
+ *         - -1: Verification failed.
+ */
+int FLASH_ConfigPageVerifyPageChecksum(const uint32_t *page_buffer,
+                                      uint32_t *misr)
+{
+    int res = 0;
+    FLASH_CalculateChecksum(page_buffer, 32, &misr[0], 1);
+    for (int i = 0; i < 4; i++)
+    {
+        if (misr[i] != CONFIG_PAGE_CHSUM[i])
+        {
+            res = -1;
+            break;
+        }
+    }
+    return res;
+}
+
+/**
+ * @brief      Calculate checksum over GPO array of CONFIG page and check it matches the expected value
+ *
+ * @param[in]  page_buffer Pointer to data over which checksum calculation must be executed.
+ * @param[out] misr Pointer on a 4 32bit word array to store calculated checksum.
+ *             Note: this buffer is only useful for debugging purposes.
+ *
+ * @return Result of the GPO array checksum verification:
+ *         -  0: Verification successfully.
+ *         - -1: Verification failed.
+ */
+int FLASH_ConfigPageVerifyGpoChecksum(const uint32_t *page_buffer,
+                                     uint32_t *misr)
+{
+    int res = 0;
+    FLASH_CalculateChecksum(page_buffer, 5, misr, 1);
+    for (int i = 0; i < 4; i++)
+    {
+        if (misr[i] != GPO_CHKSUM[i])
+        {
+            res = -1;
+            break;
+        }
+    }
+    return res;
+}
+
+/**
+ * @brief      Configure the flash wait state depending of the elwe mode and CPU frequency.
+ * When the CPU clock frequency is decreased, the Set Read command shall be called after the frequency change.
+ * When the CPU clock frequency is increased, the Set Read command shall be called before the frequency change.
+ *
+ * @param      page_ram_buffer Pointer to RAM page buffer in which the read-modify-write of page (N-2) is performed
+ * @param      gpo_chksum Pointer on a four 32bit word array to store calculated checksum.
+ * @param      page_chksum Pointer on a four 32bit word array to store calculated checksum.
+ *
+ * @return     Nothing
+ */
+void FLASH_ConfigPageUpdate(uint32_t *page_ram_buffer,
+                          uint32_t *gpo_chksum,
+                          uint32_t *page_chksum )
+{
+
+    FLASH_CalculateChecksum(page_ram_buffer, 4, gpo_chksum, 1);
+    FLASH_CalculateChecksum(GPO_CHKSUM, 1, gpo_chksum, 0);
+    for (int i = 0; i < 4; i++)
+    {
+        page_ram_buffer[16+i] = gpo_chksum[i];
+    }
+    FLASH_CalculateChecksum(&page_ram_buffer[0], 31, page_chksum, 1);
+    FLASH_CalculateChecksum(CONFIG_PAGE_CHSUM, 1, page_chksum, 0);
+    for (int i = 0; i < 4; i++)
+    {
+        page_ram_buffer[124+i] = page_chksum[i];
+    }
+}

third_party/nxp/JN5189/drivers/fsl_flash.h

@@ -0,0 +1,332 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_FLASH_H_
+#define __FSL_FLASH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup jn_flash
+ * @{
+ */
+
+/*! @file */
+
+/*******************
+ * EXPORTED MACROS  *
+ ********************/
+
+/* FLASH Commands */
+#define FLASH_CMD_INIT 0
+#define FLASH_CMD_POWERDOWN 1
+#define FLASH_CMD_SET_READ_MODE 2
+#define FLASH_CMD_READ_SINGLE_WORD 3
+#define FLASH_CMD_ERASE_RANGE 4
+#define FLASH_CMD_BLANK_CHECK 5
+#define FLASH_CMD_MARGIN_CHECK 6
+#define FLASH_CMD_CHECKSUM 7
+#define FLASH_CMD_WRITE 8
+#define FLASH_CMD_WRITE_PROG 10
+#define FLASH_CMD_PROGRAM 12
+#define FLASH_CMD_REPORT_ECC 13
+
+/* FLASH Autoprogram modes */
+#define FLASH_AUTO_OFF 0
+#define FLASH_AUTO_WORD 1
+#define FLASH_AUTO_PAGE 2
+
+#define FLASH_BASE_ADDRESS 0
+#define FLASH_PAGE_SIZE 512
+#define FLASH_PAGE_SIZE_LOG 9
+
+#define FLASH_CONFIG_PAGE_ADDR 0x9fc00
+#define FLASH_TRIMMING_DATA_ADDR 0x9fe00
+
+/**
+ * @brief FLASH INT_STATUS register definitions
+ */
+#define FLASH_FAIL (1 << 0)    /*!< Command failed */
+#define FLASH_ERR (1 << 1)     /*!< Illegal command */
+#define FLASH_DONE (1 << 2)    /*!< Command complete */
+#define FLASH_ECC_ERR (1 << 3) /*!< ECC error detected */
+
+/**
+ * @brief FLASH INT_ENABLE register definitions
+ */
+#define FLASH_FAIL (1 << 0)    /*!< Command failed */
+#define FLASH_ERR (1 << 1)     /*!< Illegal command */
+#define FLASH_DONE (1 << 2)    /*!< Command complete */
+#define FLASH_ECC_ERR (1 << 3) /*!< ECC error detected */
+
+#define FLASH_STAT_ALL (0xF)
+
+/* FLASH Events */
+#define FLASH_EVENT_RESET (1 << 0)
+//#define FLASH_EVENT_WAKEUP         (1 << 1)
+//#define FLASH_EVENT_ABORT          (1 << 2)
+
+/******************************
+ * EXPORTED TYPE DEFINITIONS  *
+ ******************************/
+typedef enum _flash_status
+{
+    kStatus_FLASH_Success         = FLASH_DONE,                             /*!< flash operation is successful*/
+    kStatus_FLASH_Fail            = FLASH_DONE | FLASH_FAIL,                /*!< flash operation is not successful*/
+    kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),   /*!< Invalid argument */
+    kStatus_FLASH_AlignmentError  = MAKE_STATUS(kStatusGroup_FLASH, 6),     /*!< Alignment Error */
+    kStatus_FLASH_EccError        = FLASH_DONE | FLASH_ECC_ERR,             /*!< ECC error detected */
+    kStatus_FLASH_Error           = FLASH_DONE | FLASH_ERR,                 /*!< Illegal command */
+} flash_status_t;
+
+
+/* Read Mode related definitions */
+#define FLASH_READ_MODE_RD_DMACC_SHIFT    15
+#define FLASH_READ_MODE_SHIFT             10
+#define FLASH_READ_MODE_NORMAL             0
+#define FLASH_READ_MODE_MARGIN_VS_PROGRAM  1
+#define FLASH_READ_MODE_MARGIN_VS_ERASE    2
+#define FLASH_READ_MODE_ILLEGAL            3
+#define FLASH_READ_MODE_MASK (FLASH_READ_MODE_ILLEGAL << FLASH_READ_MODE_SHIFT)
+#define FLASH_READ_MODE_ECC_OFF_SHIFT      2
+
+typedef enum _flash_read_modes
+{
+    FLASH_ReadModeNormal         = (FLASH_READ_MODE_NORMAL << FLASH_READ_MODE_SHIFT),
+    FLASH_ReadModeNormalEccOff   = (FLASH_READ_MODE_NORMAL << FLASH_READ_MODE_SHIFT)|(1<<FLASH_READ_MODE_ECC_OFF_SHIFT),                /*!< flash operation is not successful*/
+    FLASH_ReadModeDMACC          = (1<<FLASH_READ_MODE_RD_DMACC_SHIFT),
+    FLASH_ReadModeMarginProgram  = (FLASH_READ_MODE_MARGIN_VS_PROGRAM << FLASH_READ_MODE_SHIFT),
+    FLASH_ReadModeMarginErase    = (FLASH_READ_MODE_MARGIN_VS_ERASE << FLASH_READ_MODE_SHIFT),
+} flash_read_mode_t;
+
+/*! @brief Flash configuration information.
+ *
+ * An instance of this structure is allocated by the user of the flash driver and
+ * at initialization.
+ */
+typedef struct _flash_config
+{
+    uint32_t PFlashBlockBase;  /*!< A base address of the first PFlash block */
+    uint32_t PFlashTotalSize;  /*!< The size of the combined PFlash block. */
+    uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */
+} flash_config_t;
+
+extern flash_config_t gFlashConfig;
+
+/**
+ * @brief      Enable the FLASH
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ *
+ * @return     Nothing
+ */
+void FLASH_Init(FLASH_Type *pFLASH);
+
+/**
+ * @brief      Power down the FLASH
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ *
+ * @return     Nothing
+ */
+void FLASH_Powerdown(FLASH_Type *pFLASH);
+
+/**
+ * @brief      Wait for FLASH command to complete
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ */
+int FLASH_Wait(FLASH_Type *pFLASH);
+
+/**
+ * @brief      Erase page
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Start address with page to inspect
+ * @param[in]  pu8End End address (included in check)
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Erase(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End);
+
+/**
+ * @brief      Erase multiple pages
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  u32StartPage Index of page to start erasing from
+ * @param[in]  u32PageCount Number of pages to erase
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_ErasePages(FLASH_Type *pFLASH, uint32_t u32StartPage, uint32_t u32PageCount);
+
+/**
+ * @brief      Page Blank check
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Start address with page to inspect
+ * @param[in]  pu8End End address (included in check)
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_BlankCheck(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End);
+
+/**
+ * @brief      Margin Check
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Start address with page to inspect
+ * @param[in]  pu8End End address (included in check)
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_MarginCheck(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End);
+
+/**
+ * @brief      Program page
+ *
+ * @param[in]  pFLASH Pointer to selected FLASH peripheral
+ * @param[out] pu32Start Pointer location that must be programmed in flash
+ * @param[in]  pu32Data Pointer to source buffer being written to flash
+ * @param[in]  u32Length Number of bytes to be programmed
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Program(FLASH_Type *pFLASH, uint32_t *pu32Start, uint32_t *pu32Data, uint32_t u32Length);
+
+/**
+ * @brief      Page Checksum
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Pointer to data within starting page  page checksum must be computed
+ * @param[in]  pu8End Pointer to data whose page is the last of the checksum calculation
+ * @param[out] au32Checksum Four 32bit word array to store checksum calculation result
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Checksum(FLASH_Type *pFLASH, uint8_t *pu8Start, uint8_t *pu8End, uint32_t au32Checksum[4]);
+
+/**
+ * @brief      Read flash word (16 byte worth of data)
+ *
+ * @param      pFLASH Pointer to selected FLASH peripheral
+ * @param[in]  pu8Start Pointer to data to be read
+ * @param[in]  u32ReadMode Read mode see also flash_read_mode_t
+ * @param[out] au32Data Four 32bit word array to store read result
+ *
+ * @return     INT_STATUS with ECC_ERR bit masked out
+ * @see flash_status_t
+ */
+int FLASH_Read(FLASH_Type *pFLASH, uint8_t *pu8Start, uint32_t u32ReadMode, uint32_t au32Data[4]);
+
+/**
+ * @brief      Configure the flash wait state depending of the elwe mode and CPU frequency.
+ * When the CPU clock frequency is decreased, the Set Read command shall be called after the frequency change.
+ * When the CPU clock frequency is increased, the Set Read command shall be called before the frequency change.
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral
+ * @param      freq_48M_not_32M CPU clock frequency @48MHz - lower or equal to 32Mhz if 0
+ *
+ * @return     Nothing
+ */
+void FLASH_SetReadMode(FLASH_Type *pFLASH, bool freq_48M_not_32M);
+
+/**
+ * @brief      Calculate checksum using the same checksum algorithm as the CMD_CHECKSUM implementation of the
+ * Flash controller. When executed over a 512 byte page (page size) must return the same value as FLASH_Checksum.
+ *
+ * @param[in]  input Pointer to data over which checksum calculation must be executed.
+ * @param[in]  nb_128b_words Number of 16 byte words on flash.
+ * @param[out] misr Pointer on a four 32bit word array to store calculated checksum.
+ * @param[in]  init Set to true to clear the misr buffer.
+ *
+ * @return     Nothing
+ */
+void FLASH_CalculateChecksum(const uint32_t *input,
+                            size_t nb_128b_words,
+                            uint32_t* misr,
+                            int init);
+
+/**
+ * @brief      Calculate checksum over page (N-2) aka CONFIG page and check it matches the expected value.
+ *
+ * @param[in]  page_buffer Pointer to data over which checksum calculation must be executed.
+ * @param[out] misr Pointer on a four 32bit word array to store calculated checksum.
+ *             Note: this buffer is only useful for debugging purposes.
+ *
+ * @return Result of the page checksum verification:
+ *         -  0: Verify successfully.
+ *         - -1: Verification failed.
+ */
+int FLASH_ConfigPageVerifyPageChecksum(const uint32_t *page_buffer,
+                                      uint32_t *misr);
+
+/**
+ * @brief      Calculate checksum over GPO array of CONFIG page and check it matches the expected value
+ *
+ * @param[in]  page_buffer Pointer to data over which checksum calculation must be executed.
+ * @param[out] misr Pointer on a 4 32bit word array to store calculated checksum.
+ *             Note: this buffer is only useful for debugging purposes.
+ *
+ * @return Result of the GPO array checksum verification:
+ *         -  0: Verify successfully.
+ *         - -1: Verification failed.
+ */
+int FLASH_ConfigPageVerifyGpoChecksum(const uint32_t *page_buffer,
+                                     uint32_t *misr);
+
+/**
+ * @brief      Configure the flash wait state depending of the elwe mode and CPU frequency.
+ * When the CPU clock frequency is decreased, the Set Read command shall be called after the frequency change.
+ * When the CPU clock frequency is increased, the Set Read command shall be called before the frequency change.
+ *
+ * @param      page_ram_buffer Pointer to RAM page buffer in which the read-modify-write of page (N-2) is performed
+ * @param      gpo_chksum Pointer on a four 32bit word array to store calculated checksum.
+ * @param      page_chksum Pointer on a four 32bit word array to store calculated checksum.
+ *
+ * @return     Nothing
+ */
+void FLASH_ConfigPageUpdate(uint32_t *page_ram_buffer,
+                          uint32_t *gpo_chksum,
+                          uint32_t *page_chksum);
+
+/**
+ * @brief      Return unfiltered FLASH INT_STATUS.
+ * In normal operation FLASH_DONE rises systematically but other status bits
+ * may rise at the same time or have risen before to notify of an error.
+ * Usually testing the value returned by FLASH_Wait is sufficionet but in some special
+ * cases the raw value may be needed.
+ *
+ * @param      pFLASH Pointer to selected FLASHx peripheral.
+ *
+ * @return     INT_STATUS raw value.
+ * @see flash_status_t
+ */
+int FLASH_GetStatus(FLASH_Type *pFLASH);
+
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FSL_FLASH_H_ */

third_party/nxp/JN5189/drivers/fsl_flexcomm.c

@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*! @brief Set the FLEXCOMM mode . */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);
+
+/*! @brief check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+/*! @brief Pointers to FLEXCOMM resets for each instance. */
+static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+    if (periph == FLEXCOMM_PERIPH_NONE)
+    {
+        return true;
+    }
+    else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
+    {
+        return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false;
+    }
+    else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+    {
+        return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+/*! brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+    {
+        if ((uint32_t)base == s_flexcommBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+/* Changes FLEXCOMM mode */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+    /* Check whether peripheral type is present */
+    if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Flexcomm is locked to different peripheral type than expected  */
+    if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check if we are asked to lock */
+    if (lock)
+    {
+        base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+    }
+    else
+    {
+        base->PSELID = (uint32_t)periph;
+    }
+
+    return kStatus_Success;
+}
+
+/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+    int idx = FLEXCOMM_GetInstance(base);
+
+    if (idx < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_flexcommClocks[idx]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+    /* Reset the FLEXCOMM module */
+    RESET_PeripheralReset(s_flexcommResets[idx]);
+#endif
+
+    /* Set the FLEXCOMM to given peripheral */
+    return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(base);
+
+    /* Clear handler first to avoid execution of the handler with wrong handle */
+    s_flexcommIrqHandler[instance] = NULL;
+    s_flexcommHandle[instance]     = handle;
+    s_flexcommIrqHandler[instance] = handler;
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[0]);
+    s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[1]);
+    s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[2]);
+    s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[3]);
+    s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[4]);
+    s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+#endif
+
+#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[5]);
+    s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[6]);
+    s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[7]);
+    s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[8]);
+    s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[9]);
+    s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM10)
+void FLEXCOMM10_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[10]);
+    s_flexcommIrqHandler[10]((void *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM11)
+void FLEXCOMM11_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[11]);
+    s_flexcommIrqHandler[11]((void *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM12)
+void FLEXCOMM12_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[12]);
+    s_flexcommIrqHandler[12]((void *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM13)
+void FLEXCOMM13_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[13]);
+    s_flexcommIrqHandler[13]((void *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM14)
+void FLEXCOMM14_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM14);
+    assert(s_flexcommIrqHandler[instance]);
+    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM15)
+void FLEXCOMM15_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM15);
+    assert(s_flexcommIrqHandler[instance]);
+    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM16)
+void FLEXCOMM16_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM16);
+    assert(s_flexcommIrqHandler[instance]);
+    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif

third_party/nxp/JN5189/drivers/fsl_flexcomm.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/

third_party/nxp/JN5189/drivers/fsl_gpio.c

@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+/*! @brief Pointers to GPIO resets for each instance. */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
+#endif
+/*******************************************************************************
+ * Prototypes
+ ************ ******************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * param base   GPIO peripheral base pointer.
+ * param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    assert(port < ARRAY_SIZE(s_gpioClockName));
+
+    /* Upgate the GPIO clock */
+    CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+    /* Reset the GPIO module */
+    RESET_PeripheralReset(s_gpioResets[port]);
+#endif
+}
+
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   GPIO peripheral base pointer(Typically GPIO)
+ * param port   GPIO port number
+ * param pin    GPIO pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRCLR[port] = 1U << pin;
+#else
+        base->DIR[port] &= ~(1U << pin);
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+    }
+    else
+    {
+        /* Set default output value */
+        if (config->outputLogic == 0U)
+        {
+            base->CLR[port] = (1U << pin);
+        }
+        else
+        {
+            base->SET[port] = (1U << pin);
+        }
+/* Set pin direction */
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRSET[port] = 1U << pin;
+#else
+        base->DIR[port] |= 1U << pin;
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+    }
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
+{
+    base->INTEDG[port] = base->INTEDG[port] | (config->mode << pin);
+
+    base->INTPOL[port] = base->INTPOL[port] | (config->polarity << pin);
+}
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if (kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] | mask;
+    }
+    else if (kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] | mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if (kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] & ~mask;
+    }
+    else if (kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] & ~mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Clears multiple pins interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if (kGPIO_InterruptA == index)
+    {
+        base->INTSTATA[port] = mask;
+    }
+    else if (kGPIO_InterruptB == index)
+    {
+        base->INTSTATB[port] = mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index)
+{
+    uint32_t status = 0U;
+
+    if (kGPIO_InterruptA == index)
+    {
+        status = base->INTSTATA[port];
+    }
+    else if (kGPIO_InterruptB == index)
+    {
+        status = base->INTSTATB[port];
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+    return status;
+
+}
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if (kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] | (1U << pin);
+    }
+    else if (kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] | (1U << pin);
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if (kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] & ~(1U << pin);
+    }
+    else if (kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] & ~(1U << pin);
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if (kGPIO_InterruptA == index)
+    {
+        base->INTSTATA[port] = 1U << pin;
+    }
+    else if (kGPIO_InterruptB == index)
+    {
+        base->INTSTATB[port] = 1U << pin;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */

third_party/nxp/JN5189/drivers/fsl_gpio.h

@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPC GPIO driver version 2.1.3. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*@}*/
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
+#define GPIO_PIN_INT_LEVEL 0x00U
+#define GPIO_PIN_INT_EDGE 0x01U
+
+#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
+
+/*! @brief GPIO Pin Interrupt enable mode */
+typedef enum _gpio_pin_enable_mode
+{
+    kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
+    kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE    /*!< Generate Pin Interrupt on edge mode */
+} gpio_pin_enable_mode_t;
+
+/*! @brief GPIO Pin Interrupt enable polarity */
+typedef enum _gpio_pin_enable_polarity
+{
+    kGPIO_PinIntEnableHighOrRise =
+        PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */
+    kGPIO_PinIntEnableLowOrFall =
+        PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */
+} gpio_pin_enable_polarity_t;
+
+/*! @brief LPC GPIO interrupt index definition */
+typedef enum _gpio_interrupt_index
+{
+    kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/
+    kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/
+} gpio_interrupt_index_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef struct _gpio_interrupt_config
+{
+    uint8_t mode;         /* The trigger mode of GPIO interrupts */
+    uint8_t polarity;     /* The polarity of GPIO interrupts */
+} gpio_interrupt_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * @param base   GPIO peripheral base pointer.
+ * @param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+    base->B[port][pin] = output;
+}
+
+/*@}*/
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+    return (uint32_t)base->B[port][pin];
+}
+
+/*@}*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->NOT[port] = mask;
+}
+
+/*@}*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->PIN[port];
+}
+
+/*@}*/
+/*! @name GPIO Mask Operations */
+/*@{*/
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param output  GPIO port output value.
+ */
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+    base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @retval       masked GPIO port value
+ */
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->MPIN[port];
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config);
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Clears pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index);
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/

third_party/nxp/JN5189/drivers/fsl_iocon.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOCON_H_
+#define _FSL_IOCON_H_
+
+#include "fsl_common.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.jn_iocon"
+#endif
+
+/*!
+ * @addtogroup jn_iocon
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOCON driver version 2.0.0. */
+#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/**
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
+ */
+typedef struct _iocon_group
+{
+    uint32_t port : 8;      /* Pin port */
+    uint32_t pin : 8;       /* Pin number */
+    uint32_t modefunc : 16; /* Function and mode */
+} iocon_group_t;
+
+/**
+ * @brief IOCON function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+#define IOCON_FUNC0 IOCON_PIO_FUNC(0) /*!< Selects pin function 0 */
+#define IOCON_FUNC1 IOCON_PIO_FUNC(1) /*!< Selects pin function 1 */
+#define IOCON_FUNC2 IOCON_PIO_FUNC(2) /*!< Selects pin function 2 */
+#define IOCON_FUNC3 IOCON_PIO_FUNC(3) /*!< Selects pin function 3 */
+#define IOCON_FUNC4 IOCON_PIO_FUNC(4) /*!< Selects pin function 4 */
+#define IOCON_FUNC5 IOCON_PIO_FUNC(5) /*!< Selects pin function 5 */
+#define IOCON_FUNC6 IOCON_PIO_FUNC(6) /*!< Selects pin function 6 */
+#define IOCON_FUNC7 IOCON_PIO_FUNC(7) /*!< Selects pin function 7 */
+
+#define IOCON_MODE_PULLUP IOCON_PIO_MODE(0)   /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER IOCON_PIO_MODE(1) /*!< Selects pin repeater function */
+#define IOCON_MODE_INACT IOCON_PIO_MODE(2)    /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN IOCON_PIO_MODE(3) /*!< Selects pull-down function */
+
+#define IOCON_HYS_EN (0x1 << 5)            /*!< Enables hysteresis ??*/
+#define IOCON_GPIO_MODE IOCON_PIO_SLEW0(1) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW IOCON_PIO_SLEW0(1)  /*!< I2C Slew Rate Control */
+
+#define IOCON_INV_EN IOCON_PIO_INVERT(1) /*!< Enables invert function on input */
+
+#define IOCON_ANALOG_EN IOCON_PIO_DIGIMODE(0)  /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN IOCON_PIO_DIGIMODE(1) /*!< Enables digital function by setting 1 to bit 7(default) */
+
+#define IOCON_STDI2C_EN IOCON_PIO_FILTEROFF(1) /*!< I2C standard mode/fast-mode */
+
+#define IOCON_INPFILT_OFF IOCON_PIO_FILTEROFF(1) /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON IOCON_PIO_FILTEROFF(0)  /*!< Input filter On for GPIO pins */
+
+#define IOCON_SLEW1_OFF IOCON_PIO_SLEW1(0) /*!< Driver Slew Rate Control */
+#define IOCON_SLEW1_ON IOCON_PIO_SLEW1(1)  /*!< Driver Slew Rate Control */
+
+#define IOCON_FASTI2C_EN (IOCON_INPFILT_ON | IOCON_SLEW1_ON) /*!< I2C Fast-mode Plus and high-speed slave */
+
+#define IOCON_OPENDRAIN_EN IOCON_PIO_OD(1) /*!< Enables open-drain function */
+
+#define IOCON_S_MODE_0CLK IOCON_PIO_SSEL(0) /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK IOCON_PIO_SSEL(1) /*!< Input pulses shorter than 1 filter clock are rejected */
+#define IOCON_S_MODE_2CLK IOCON_PIO_SSEL(2) /*!< Input pulses shorter than 2 filter clock2 are rejected */
+#define IOCON_S_MODE_3CLK IOCON_PIO_SSEL(3) /*!< Input pulses shorter than 3 filter clock2 are rejected */
+
+/* Set IO clamping to the DIO : freeze the IO state.
+ * Requires SYSCON->RETENTIONCTRL.IOCLAMPING=1 . Automatically set in powerdown */
+#define IOCON_IO_CLAMPING_NORMAL_MFIO (1 << 11)
+#define IOCON_IO_CLAMPING_COMBO_MFIO_I2C (1 << 12) /* Use this flag for PIO11 and PIO12 only */
+
+#define IOCON_CFG(dbg_func) (IOCON_PIO_FUNC(0) | IOCON_MODE_PULLDOWN |\
+                             IOCON_DIGITAL_EN | IOCON_INPFILT_OFF | \
+                             IOCON_PIO_DBG_FUNC(dbg_func) | IOCON_PIO_DBG_MODE(1))
+
+#define IOCON_PIO_I2C_EGP_SHIFT        (3U)
+#define IOCON_PIO_I2C_EGP_MASK         (1 << IOCON_PIO_I2C_EGP_SHIFT)
+#define IOCON_PIO_I2C_ECS_SHIFT        (4U)
+#define IOCON_PIO_I2C_ECS_MASK         (1 << IOCON_PIO_I2C_ECS_SHIFT)
+#define IOCON_PIO_I2C_EHS_SHIFT        (5U)
+#define IOCON_PIO_I2C_EHS_MASK         (1 << IOCON_PIO_I2C_EHS_SHIFT)
+#define IOCON_PIO_I2C_FSEL_SHIFT       (9U)
+#define IOCON_PIO_I2C_FSEL_MASK        (1 << IOCON_PIO_I2C_FSEL_SHIFT)
+#define IOCON_PIO_I2C_CLAMP_SHIFT      (12U)
+#define IOCON_PIO_I2C_CLAMP_MASK       (1 << IOCON_PIO_I2C_CLAMP_SHIFT)
+#define IOCON_PIO_I2C_DBG_FUNC_SHIFT   (13U)
+#define IOCON_PIO_I2C_DBG_FUNC_MASK    (0xf << IOCON_PIO_I2C_DBG_FUNC_SHIFT)
+#define IOCON_PIO_I2C_DBG_FUNC(x)      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2C_DBG_FUNC_SHIFT)) & IOCON_PIO_I2C_DBG_FUNC_MASK)
+#define IOCON_PIO_I2C_DBG_MODE_SHIFT   (17U)
+#define IOCON_PIO_I2C_DBG_MODE_MASK    (1 << IOCON_PIO_I2C_DBG_MODE_SHIFT)
+#define IOCON_PIO_I2C_DBG_MODE(x)      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2C_DBG_MODE_SHIFT)) & IOCON_PIO_I2C_DBG_MODE_MASK)
+
+
+#define IOCON_I2C_CFG(dbg_func) (IOCON_PIO_FUNC(0) |\
+                                 IOCON_PIO_I2C_EGP_MASK |\
+                                 IOCON_PIO_I2C_ECS_MASK |\
+                                 IOCON_DIGITAL_EN |\
+                                 IOCON_INPFILT_OFF |\
+                                 IOCON_PIO_I2C_DBG_FUNC(dbg_func)|\
+                                 IOCON_PIO_I2C_DBG_MODE(1))
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief   Sets I/O Control pin mux
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   port        : GPIO port to mux
+ * @param   pin         : GPIO pin to mux
+ * @param   modefunc    : OR'ed values of type IOCON_*
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+    base->PIO[port][pin] = modefunc;
+}
+
+/**
+ * @brief   Set all I/O Control pin muxing
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   pinArray    : Pointer to array of pin mux selections
+ * @param   arrayLength : Number of entries in pinArray
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
+{
+    uint32_t i;
+
+    for (i = 0; i < arrayLength; i++)
+    {
+        IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
+    }
+}
+
+/**
+ * @brief   Sets I/O Control pin mux pull select
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   port        : GPIO port to mux
+ * @param   pin         : GPIO pin to mux
+ * @param   pull_select : OR'ed values of type IOCON_*
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_PullSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint8_t pull_select)
+{
+    uint32_t reg = base->PIO[port][pin];
+    reg &= ~IOCON_PIO_MODE_MASK;
+    reg |= IOCON_PIO_MODE(pull_select);
+    base->PIO[port][pin] = reg;
+}
+
+/**
+ * @brief   Sets I/O Control pin mux pull select
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   port        : GPIO port to mux
+ * @param   pin         : GPIO pin to mux
+ * @param   func        : Pinmux function
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_FuncSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint8_t func)
+{
+    uint32_t reg = base->PIO[port][pin];
+    reg &= ~IOCON_PIO_FUNC_MASK;
+    reg |= IOCON_PIO_FUNC(func);
+    base->PIO[port][pin] = reg;
+}
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_IOCON_H_ */

third_party/nxp/JN5189/drivers/fsl_power.c

@@ -0,0 +1,929 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+#include "fsl_debug_console.h"
+#include "fsl_iocon.h"
+
+#include "rom_mpu.h"
+#include "rom_pmc.h"
+#include "rom_api.h"
+#include "rom_lowpower.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power_no_lib"
+#endif
+
+#define POWER_LIB_VERSION 6042018
+
+/* Do not disable the DC bus when going to power modes */
+//#define POWER_DCBUS_NOT_DISABLED
+
+//#define DUMP_CONFIG
+//#define TRACE_ERR
+//#define TRACE_VRB
+//#define DISPLAY_ACTIVE_VOLTAGE
+
+/* Force BODMEM enable in power down mode for test : 1uA power consumption increase */
+//#define POWER_FORCE_BODMEM_IN_PD
+
+/* On ES2, use directly the safe voltage in deep sleep provided by Patrick */
+/* on ES2 powerdown1/2/3/4 , only BANK7 is maintained in retention */
+#define POWER_DOWN_WARM_4K
+
+#if defined(DUMP_CONFIG) || defined(TRACE_ERR) || defined(TRACE_VRB)
+#define POWER_CONSOLE_DEINIT
+#endif
+
+/*******************************************************************************
+ * Macros/Constants
+ *******************************************************************************/
+
+#if 1                         /* Cope with LDO CORE @ 1.0v in Active and LDO MEM @ 0.9 in power down */
+#define POWER_BODMEM_TRIG 0x4 /* 0.80V  Considering LDOMEM = 0.9v */
+#define POWER_BODMEM_HYST 0x1 /* 0.050V */
+
+#define POWER_BODCORE_TRIG 0x6 /* 0.90V   Considering LDOCORE = 1.0v */
+#define POWER_BODCORE_HYST 0x1 /* 0.050V */
+#else                          // safest setting for LDO CORE @ 1.1v and LDO MEM @ 1.0v
+#define POWER_BODMEM_TRIG 0x6  /* 0.90V - 0.925V +/- 3%   Considering LDOMEM = 1.9v */
+#define POWER_BODMEM_HYST 0x0  /* 0.025V */
+
+#define POWER_BODCORE_TRIG 0x7 /* 0.95V - 0.975V +/- 3%   Considering LDOCORE = 1.1v */
+#define POWER_BODCORE_HYST 0x0 /* 0.025V */
+#endif
+
+#define BODVBAT_LVL_DEFAULT POWER_BOD_LVL_1_75V
+#define BODVBAT_HYST_DEFAULT POWER_BOD_HYST_100MV
+
+#define POWER_LDO_TRIM_UNDEFINED 0x7F
+
+/* **********************   END OF POWER MODE DEFINITIONS   **************************************************/
+
+#define VOLTAGE(Vpmu, Vpmuboost, Vmem, Vmemboost, Vcore, Vpmuboostenable, Vflashcore)                                  \
+    (((Vpmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) & LOWPOWER_VOLTAGE_LDO_PMU_MASK) |                                      \
+     ((Vpmuboost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) & LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK) |                     \
+     ((Vpmuboostenable << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_ENABLE_INDEX) & LOWPOWER_VOLTAGE_LDO_PMU_BOOST_ENABLE_MASK) | \
+     ((Vmem << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) & LOWPOWER_VOLTAGE_LDO_MEM_MASK) |                                      \
+     ((Vmemboost << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) & LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK) |                     \
+     ((Vcore << LOWPOWER_VOLTAGE_LDO_CORE_INDEX) & LOWPOWER_VOLTAGE_LDO_CORE_MASK) |                                   \
+     ((Vflashcore << LOWPOWER_VOLTAGE_LDO_FLASH_CORE_INDEX) & LOWPOWER_VOLTAGE_LDO_FLASH_CORE_MASK))
+
+/*
+ * Recommended Voltage settings from
+ * https://www.collabnet.nxp.com/svn/lprfprojects/JN5189/Documents/17_Architecture/17_n_Digital/Block_Specification/jn5189_settings.xlsx
+ */
+#define VOLTAGE_PMU_DOWN 0x5      /* 0.8V  */
+#define VOLTAGE_PMUBOOST_DOWN 0x3 /* 0.75V */
+
+#define VOLTAGE_MEM_DOWN_0_9V 0x9       /* 0.9V  */
+#define VOLTAGE_MEM_DOWN_1_0V 0xE       /* 1V    */
+#define VOLTAGE_MEMBOOST_DOWN_0_85V 0x7 /* 0.85V */
+#define VOLTAGE_MEMBOOST_DOWN_0_96V 0xA /* 0.96V */
+
+#define VOLTAGE_PMU_DEEP_SLEEP 0xA       /* 0.96V */
+#define VOLTAGE_PMUBOOST_DEEP_SLEEP 0x9  /* 0.9V  */
+#define VOLTAGE_MEM_DEEP_SLEEP 0x18      /* 1.1V  */
+#define VOLTAGE_MEMBOOST_DEEP_SLEEP 0x13 /* 1.05V */
+#define VOLTAGE_CORE_DEEP_SLEEP 0x2      /* 0.95V */
+#define VOLTAGE_FLASH_CORE_DEEP_SLEEP 2  /* 0.95V */
+
+#define VOLTAGE_PMU_DEEP_DOWN 0x5      /* 0.8V  */
+#define VOLTAGE_PMUBOOST_DEEP_DOWN 0x3 /* 0.75V */
+
+#define VOLTAGE_LDO_PMU_BOOST 0
+
+#define POWER_ULPGB_TRIM_FLASH_ADDR (uint32_t *)0x9FCD4
+
+#define POWER_GET_ACTIVE_TRIM_VALUE(__reg) ((int8_t)((__reg & (1 << 4)) ? -(__reg & 0xF) : (__reg & 0xF)))
+#define POWER_GET_PWD_TRIM_VALUE(__reg) \
+    ((int8_t)(((__reg >> 5) & (1 << 4)) ? -((__reg >> 5) & 0xF) : ((__reg >> 5) & 0xF)))
+
+#define POWER_APPLY_ACTIVE_TRIM(__voltage)                                                                          \
+    ((active_trim_val != POWER_LDO_TRIM_UNDEFINED) ? (MIN(0x1E, MAX(((int8_t)__voltage + active_trim_val), 0xA))) : \
+                                                     (__voltage))
+#define POWER_APPLY_PWD_TRIM(__voltage)                                                                         \
+    ((active_trim_val != POWER_LDO_TRIM_UNDEFINED) ? (MIN(0x9, MAX(((int8_t)__voltage + pwd_trim_val), 0x1))) : \
+                                                     (__voltage))
+
+#define POWER_APPLY_TRIM(__voltage) \
+    ((__voltage < 0xA) ? POWER_APPLY_PWD_TRIM(__voltage) : POWER_APPLY_ACTIVE_TRIM(__voltage))
+
+/*******************************************************************************
+ * Types
+ ******************************************************************************/
+static const LPC_LOWPOWER_LDOVOLTAGE_T lowpower_ldovoltage_reset = {
+    .LDOPMU             = 0x18, // 1.1V
+    .LDOPMUBOOST        = 0x13, // 1.05V
+    .LDOMEM             = 0x18, // 1.1V
+    .LDOMEMBOOST        = 0x13, // 1.05V
+    .LDOCORE            = 0x5,  // 1.1V
+    .LDOFLASHNV         = 0x5,  // 1.9V
+    .LDOFLASHCORE       = 0x6,  // 1.15V
+    .LDOADC             = 0x5,  // 1.1V
+    .LDOPMUBOOST_ENABLE = 1,    // Force Boost activation on LDOPMU
+};
+
+static const LPC_LOWPOWER_LDOVOLTAGE_T lowpower_ldovoltage_min = {
+    .LDOPMU             = 0xE, // 1V
+    .LDOPMUBOOST        = 0xA, // 0.96V
+    .LDOMEM             = 0xE, // 1V
+    .LDOMEMBOOST        = 0xA, // 0.96V
+    .LDOCORE            = 0x3, // 1V
+    .LDOFLASHNV         = 0x5, // 1.9V
+    .LDOFLASHCORE       = 0x6, // 1.15V
+    .LDOADC             = 0x5, // 1.1V
+    .LDOPMUBOOST_ENABLE = 1,   // Force Boost activation on LDOPMU
+};
+
+/* trimming value to apply to active/pwd voltage - Initialized from flash in POWER_Init() */
+static int8_t active_trim_val = POWER_LDO_TRIM_UNDEFINED;
+static int8_t pwd_trim_val    = POWER_LDO_TRIM_UNDEFINED;
+
+/*******************************************************************************
+ * Local prototypes
+ ******************************************************************************/
+
+#ifdef DUMP_CONFIG
+static void LF_DumpConfig(LPC_LOWPOWER_T *LV_LowPowerMode);
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void POWER_FlexcomClocksDisable(void)
+{
+    CLOCK_AttachClk(kNONE_to_USART_CLK);
+    CLOCK_AttachClk(kNONE_to_FRG_CLK);
+    CLOCK_AttachClk(kNONE_to_I2C_CLK);
+    CLOCK_AttachClk(kNONE_to_SPI_CLK);
+
+    CLOCK_DisableClock(kCLOCK_Usart0);
+    CLOCK_DisableClock(kCLOCK_I2c0);
+    CLOCK_DisableClock(kCLOCK_Spi0);
+}
+
+#ifdef FOR_BOD_DEBUG
+/******   BODMEM ********/
+static void POWER_BodMemDisable(void)
+{
+    PMC->PDRUNCFG &= ~PMC_PDRUNCFG_ENA_BOD_MEM_MASK;
+    PMC->BODMEM &= ~PMC_BODMEM_RESETENABLE_MASK;
+}
+
+static void POWER_BodMemSetup(void)
+{
+    // TODO : really needed?
+    POWER_BodMemDisable();
+
+    /* Configure BODMEM so it can be enabled before going to power down */
+    PMC->BODMEM = (PMC->BODMEM & ~(PMC_BODMEM_TRIGLVL_MASK | PMC_BODMEM_HYST_MASK)) |
+                  (PMC_BODMEM_TRIGLVL(POWER_BODMEM_TRIG) | PMC_BODMEM_HYST(POWER_BODMEM_HYST));
+
+    /* Clear BODMEM interrupt */
+    SYSCON->ANACTRL_INTENCLR = SYSCON_ANACTRL_INTENSET_BODMEM_MASK;
+
+    /* Enable the BODMEM */
+    PMC->PDRUNCFG |= PMC_PDRUNCFG_ENA_BOD_MEM_MASK;
+}
+
+static void POWER_BodMemEnableInt(void)
+{
+    /* Warning, we should wait for the LDO to set up (27us) before clearing the status and enabling the interrupts
+     * (RFT1852) However, we expect this function to be called more than 27us after POWER_BodCoreConfigure() so we can
+     * discard the 27us delay here */
+    // CLOCK_uDelay(27);
+
+    /* clear initial status  (RFT1891) and enable interrupt */
+    SYSCON->ANACTRL_STAT     = SYSCON_ANACTRL_STAT_BODMEM_MASK;
+    SYSCON->ANACTRL_INTENSET = SYSCON_ANACTRL_INTENSET_BODMEM_MASK;
+
+    /* BODMEM Reset enable */
+    PMC->BODMEM |= PMC_BODMEM_RESETENABLE_MASK;
+}
+
+/******   BODCORE ********/
+static void POWER_BodCoreDisable(void)
+{
+    PMC->PDRUNCFG &= ~PMC_PDRUNCFG_ENA_BOD_CORE_MASK;
+    PMC->BODCORE &= ~PMC_BODCORE_RESETENABLE_MASK;
+}
+
+static void POWER_BodCoreSetup(void)
+{
+    /* TODO : shall we disable it first? */
+    POWER_BodCoreDisable();
+
+    /* Configure BODMEM so it can be enabled before going to power down */
+    PMC->BODCORE = (PMC->BODCORE & ~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK)) |
+                   (PMC_BODCORE_TRIGLVL(POWER_BODCORE_TRIG) | PMC_BODCORE_HYST(POWER_BODCORE_TRIG));
+
+    /* Clear BODCORE interrupt */
+    SYSCON->ANACTRL_INTENCLR = SYSCON_ANACTRL_INTENSET_BODCORE_MASK;
+
+    /* Enable the BODCORE */
+    PMC->PDRUNCFG |= PMC_PDRUNCFG_ENA_BOD_CORE_MASK;
+}
+
+static void POWER_BodCoreEnableInt(void)
+{
+    /* Warning, we should wait for the LDO to set up (27us) before clearing the status and enabling the interrupts
+     * (RFT1852) However, we expect this function to be called more than 27us after POWER_BodCoreConfigure() so we can
+     * discard the 27us delay here */
+    // CLOCK_uDelay(27);
+
+    /* clear initial status  (RFT1891) and enable interrupt */
+    SYSCON->ANACTRL_STAT     = SYSCON_ANACTRL_STAT_BODCORE_MASK;
+    SYSCON->ANACTRL_INTENSET = SYSCON_ANACTRL_INTENSET_BODCORE_MASK;
+
+    /* BOD IC Reset enable */
+    PMC->BODCORE |= PMC_BODCORE_RESETENABLE_MASK;
+}
+#endif
+
+static void POWER_UpdateTrimmingVoltageValue(void)
+{
+    uint32_t ulpbg_trim_flash_val;
+    /* Save a bit of time is the trimming values are already retrieved */
+
+    if ((active_trim_val == POWER_LDO_TRIM_UNDEFINED) || (pwd_trim_val == POWER_LDO_TRIM_UNDEFINED))
+    {
+        /* set the trimming values for active and pwd from N-2 page Flash */
+        ulpbg_trim_flash_val = *POWER_ULPGB_TRIM_FLASH_ADDR;
+        active_trim_val      = POWER_GET_ACTIVE_TRIM_VALUE(ulpbg_trim_flash_val);
+        pwd_trim_val         = POWER_GET_PWD_TRIM_VALUE(ulpbg_trim_flash_val);
+    }
+#ifdef DUMP_CONFIG
+    PRINTF("reg=0x%x active_trim=0x%X pwd_trim=0x%X\r\n", ulpbg_trim_flash_val, active_trim_val, pwd_trim_val);
+#endif
+}
+
+static uint32_t POWER_GetIoClampConfig(void)
+{
+    uint32_t io_clamp = 0;
+
+    for (int i = 0; i < 22; i++)
+    {
+        if ((i == 10) | (i == 11))
+        {
+            io_clamp |= (((IOCON->PIO[0][i] & IOCON_IO_CLAMPING_COMBO_MFIO_I2C) >> 12) << i);
+        }
+        else
+        {
+            io_clamp |= (((IOCON->PIO[0][i] & IOCON_IO_CLAMPING_NORMAL_MFIO) >> 11) << i);
+        }
+    }
+    return io_clamp;
+}
+
+/*!
+ * brief Power Library API to return the library version.
+ *
+ * param none
+ * return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void)
+{
+    return POWER_LIB_VERSION;
+}
+
+/*!
+ * brief determine cause of reset
+ * return reset_cause
+ */
+reset_cause_t POWER_GetResetCause(void)
+{
+    reset_cause_t reset_cause = RESET_UNDEFINED;
+    uint32_t pmc_reset        = pmc_reset_get_cause();
+
+    if (pmc_reset & PMC_RESETCAUSE_POR_MASK)
+    {
+        reset_cause |= RESET_POR;
+    }
+
+    if (pmc_reset & PMC_RESETCAUSE_PADRESET_MASK)
+    {
+        reset_cause |= RESET_EXT_PIN;
+    }
+
+    if (pmc_reset & PMC_RESETCAUSE_BODRESET_MASK)
+    {
+        reset_cause |= RESET_BOR;
+    }
+
+    if (pmc_reset & PMC_RESETCAUSE_SYSTEMRESET_MASK)
+    {
+        reset_cause |= RESET_SYS_REQ;
+    }
+
+    if (pmc_reset & PMC_RESETCAUSE_WDTRESET_MASK)
+    {
+        reset_cause |= RESET_WDT;
+    }
+
+    if (pmc_reset & PMC_RESETCAUSE_WAKEUPIORESET_MASK)
+    {
+        reset_cause |= RESET_WAKE_DEEP_PD;
+    }
+
+    if (pmc_reset & PMC_RESETCAUSE_WAKEUPPWDNRESET_MASK)
+    {
+        reset_cause |= RESET_WAKE_PD;
+    }
+
+    if (pmc_reset & PMC_RESETCAUSE_SWRRESET_MASK)
+    {
+        reset_cause |= RESET_SW_REQ;
+    }
+
+    return reset_cause;
+}
+
+/*!
+ * brief Clear cause of reset
+ */
+void POWER_ClearResetCause(void)
+{
+    pmc_reset_clear_cause(0xFFFFFFFF);
+}
+
+void POWER_DisplayActiveVoltage(void)
+{
+    LPC_LOWPOWER_LDOVOLTAGE_T ldo_voltage;
+
+    Chip_LOWPOWER_GetSystemVoltages(&ldo_voltage);
+
+    PRINTF("LDOPMU       : %d\n", (int)(ldo_voltage.LDOPMU & 0x1fUL));
+    PRINTF("LDOPMUBOOST  : %d\n", (int)(ldo_voltage.LDOPMUBOOST & 0x1fUL));
+    PRINTF("LDOMEM       : %d\n", (int)(ldo_voltage.LDOMEM & 0x1fUL));
+    PRINTF("LDOMEMBOOST  : %d\n", (int)(ldo_voltage.LDOMEMBOOST & 0x1fUL));
+    PRINTF("LDOCORE      : %d\n", (int)(ldo_voltage.LDOCORE & 0x07UL));
+    PRINTF("LDOFLASHCORE : %d\n", (int)(ldo_voltage.LDOFLASHCORE & 0x07UL));
+    PRINTF("LDOFLASHNV   : %d\n", (int)(ldo_voltage.LDOFLASHNV & 0x07UL));
+    PRINTF("LDOADC       : %d\n", (int)(ldo_voltage.LDOADC & 0x07UL));
+
+    PRINTF("LDOPMUBOOST_ENABLE : %d\n", ldo_voltage.LDOPMUBOOST_ENABLE);
+
+    PRINTF("\n");
+}
+
+void POWER_ApplyActiveVoltage(const LPC_LOWPOWER_LDOVOLTAGE_T *ldo_voltage)
+{
+    LPC_LOWPOWER_LDOVOLTAGE_T ldo_voltage_l;
+
+    memcpy(&ldo_voltage_l, ldo_voltage, sizeof(LPC_LOWPOWER_LDOVOLTAGE_T));
+
+    /* Apply some trimming on LDOPMU and LDOMEM to avoid extra consumption */
+    ldo_voltage_l.LDOPMU      = POWER_APPLY_TRIM(ldo_voltage->LDOPMU);
+    ldo_voltage_l.LDOPMUBOOST = POWER_APPLY_TRIM(ldo_voltage->LDOPMUBOOST);
+
+    ldo_voltage_l.LDOMEM      = POWER_APPLY_TRIM(ldo_voltage->LDOMEM);
+    ldo_voltage_l.LDOMEMBOOST = POWER_APPLY_TRIM(ldo_voltage->LDOMEMBOOST);
+
+    Chip_LOWPOWER_SetSystemVoltages(&ldo_voltage_l);
+}
+
+void POWER_ApplyLdoActiveVoltage(pm_ldo_volt_t ldoVolt)
+{
+    switch (ldoVolt)
+    {
+        case PM_LDO_VOLT_1_0V:
+            POWER_ApplyActiveVoltage(&lowpower_ldovoltage_min);
+            break;
+
+        case PM_LDO_VOLT_1_1V_DEFAULT:
+        default:
+            POWER_ApplyActiveVoltage(&lowpower_ldovoltage_reset);
+    }
+}
+
+/*!
+ * brief Initialize the sdk power drivers
+ *
+ * Optimize the LDO voltage for power saving
+ * Initialize the power domains
+ * Activate the BOD
+ *
+ * return none
+ */
+void POWER_Init(void)
+{
+    static bool warm_start = false;
+#ifdef FOR_BOD_DEBUG
+    /* Enable the clock for the analog interrupt control module - required for the BOD
+     * and set up BOD core and mem*/
+    POWER_BodSetUp();
+#endif
+    if (warm_start == false)
+    {
+        POWER_SetTrimDefaultActiveVoltage();
+
+        warm_start = true;
+    }
+
+#ifdef DISPLAY_ACTIVE_VOLTAGE
+    POWER_DisplayActiveVoltage();
+#endif
+
+    /* This time, need to wait for LDO to be set up (27us) */
+    CLOCK_uDelay(27);
+#ifdef FOR_BOD_DEBUG
+    /* enable interrupt and SW reset for the BODCORE */
+    POWER_BodActivate();
+#endif
+}
+
+void POWER_SetTrimDefaultActiveVoltage(void)
+{
+    POWER_UpdateTrimmingVoltageValue();
+
+    /* Always startup at 1.1V to cope with higher current load when enabling clocks */
+    POWER_ApplyLdoActiveVoltage(PM_LDO_VOLT_1_1V_DEFAULT);
+
+#ifdef DISPLAY_ACTIVE_VOLTAGE
+    POWER_DisplayActiveVoltage();
+#endif
+}
+
+#ifdef FOR_BOD_DEBUG
+void POWER_BodSetUp(void)
+{
+    /* Enable the clock for the analog interrupt control module - required for the BOD */
+    CLOCK_EnableClock(kCLOCK_AnaInt);
+
+    POWER_BodCoreSetup();
+    POWER_BodMemSetup();
+}
+
+void POWER_BodActivate(void)
+{
+    /* enable interrupt and SW reset for the BODCORE */
+    POWER_BodCoreEnableInt();
+
+    CLOCK_DisableClock(kCLOCK_AnaInt);
+}
+#endif
+
+/*!
+ * brief Get default Vbat BOD config parameters, level 1.75V, Hysteresis  100mV
+ *
+ * param bod_cfg_p
+ * return none
+ */
+void POWER_BodVbatGetDefaultConfig(pm_bod_cfg_t *bod_cfg_p)
+{
+    bod_cfg_p->bod_level = BODVBAT_LVL_DEFAULT;
+    bod_cfg_p->bod_hyst  = BODVBAT_HYST_DEFAULT;
+    bod_cfg_p->bod_cfg   = POWER_BOD_ENABLE | POWER_BOD_INT_ENABLE;
+}
+
+/*!
+ * brief Configure the VBAT BOD
+ *
+ * param bod_cfg_p
+ * return false if configuration parameters are incorrect
+ */
+bool POWER_BodVbatConfig(pm_bod_cfg_t *bod_cfg_p)
+{
+    uint32_t comparator_interrupt;
+
+    if (bod_cfg_p->bod_cfg & POWER_BOD_ENABLE)
+    {
+        if ((bod_cfg_p->bod_level >= POWER_BOD_LVL_1_75V) && (bod_cfg_p->bod_level <= POWER_BOD_LVL_3_3V) &&
+            (bod_cfg_p->bod_hyst <= POWER_BOD_HYST_100MV))
+        {
+            uint32_t bodvbat = PMC->BODVBAT;
+            bodvbat &= ~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK);
+            bodvbat |= PMC_BODVBAT_TRIGLVL(bod_cfg_p->bod_level);
+            bodvbat |= PMC_BODVBAT_HYST(bod_cfg_p->bod_hyst);
+            PMC->BODVBAT = bodvbat;
+        }
+        else
+        {
+            return false;
+        }
+    }
+
+    /* enable the clock for the analog interrupt control module */
+    CLOCK_EnableClock(kCLOCK_AnaInt);
+
+    if (bod_cfg_p->bod_cfg & POWER_BOD_HIGH)
+    {
+        /* Disable Interrupt on BODVBAT High */
+        SYSCON->ANACTRL_INTENCLR = SYSCON_ANACTRL_INTENCLR_BODVBATHIGH_MASK;
+
+        /* clear initial status of interrupt */
+        SYSCON->ANACTRL_STAT = SYSCON_ANACTRL_STAT_BODVBATHIGH_MASK;
+
+        /* enable comparator interrupt       */
+        comparator_interrupt = SYSCON_ANACTRL_INTENSET_BODVBATHIGH_MASK;
+    }
+    else
+    {
+        /*  BOD IC Interrupt enable */
+        SYSCON->ANACTRL_INTENCLR = SYSCON_ANACTRL_INTENCLR_BODVBAT_MASK;
+
+        /* clear initial status of interrupt */
+        SYSCON->ANACTRL_STAT = SYSCON_ANACTRL_STAT_BODVBAT_MASK;
+
+        /* enable comparator interrupt      */
+        comparator_interrupt = SYSCON_ANACTRL_INTENSET_BODVBAT_MASK;
+    }
+
+    if (bod_cfg_p->bod_cfg & POWER_BOD_ENABLE)
+    {
+        if (bod_cfg_p->bod_cfg & POWER_BOD_INT_ENABLE)
+        {
+            SYSCON->ANACTRL_INTENSET = comparator_interrupt;
+            NVIC_EnableIRQ(WDT_BOD_IRQn);
+        }
+        else
+        {
+            NVIC_DisableIRQ(WDT_BOD_IRQn);
+        }
+#ifdef FOR_BOD_DEBUG
+        if (bod_cfg_p->bod_cfg & POWER_BOD_RST_ENABLE)
+        {
+            PMC->BODVBAT |= PMC_BODVBAT_RESETENABLE_MASK;
+        }
+        else
+        {
+            PMC->BODVBAT &= ~PMC_BODVBAT_RESETENABLE_MASK;
+        }
+#endif
+    }
+
+    CLOCK_DisableClock(kCLOCK_AnaInt);
+    // PRINTF( "BODVBAT=0x%X ANACTRL_CTRL=0x%X _STAT=0x%X _VAL=0x%X _INTENSET=0x%X\n", PMC->BODVBAT,
+    // SYSCON->ANACTRL_CTRL, SYSCON->ANACTRL_STAT, SYSCON->ANACTRL_VAL, SYSCON->ANACTRL_INTENSET);
+
+    return true;
+}
+
+bool POWER_EnterDeepSleepMode(pm_power_config_t *pm_power_config)
+{
+    /* [RFT1911] Disable the DC bus to prevent extra consumption */
+#ifndef POWER_DCBUS_NOT_DISABLED
+    ASYNC_SYSCON->DCBUSCTRL =
+        (ASYNC_SYSCON->DCBUSCTRL & ~ASYNC_SYSCON_DCBUSCTRL_ADDR_MASK) | (1 << ASYNC_SYSCON_DCBUSCTRL_ADDR_SHIFT);
+#endif
+
+    /* [artf555998] Enable new ES2 feature for fast wakeup */
+    PMC->CTRLNORST = PMC_CTRLNORST_FASTLDOENABLE_MASK;
+
+    return false;
+}
+
+bool POWER_EnterPowerDownMode(pm_power_config_t *pm_power_config)
+{
+    int radio_retention;
+    int autostart_32mhz_xtal;
+    int keep_ao_voltage;
+    int sram_cfg;
+    int wakeup_src0;
+    int wakeup_src1;
+    uint8_t voltage_mem_down;
+    uint8_t voltage_membootst_down;
+    LPC_LOWPOWER_T lp_config;
+    memset(&lp_config, 0, sizeof(lp_config));
+
+    sram_cfg             = pm_power_config->pm_config & PM_CFG_SRAM_ALL_RETENTION;
+    radio_retention      = pm_power_config->pm_config & PM_CFG_RADIO_RET;
+    autostart_32mhz_xtal = pm_power_config->pm_config & PM_CFG_XTAL32M_AUTOSTART;
+    keep_ao_voltage      = pm_power_config->pm_config & PM_CFG_KEEP_AO_VOLTAGE;
+
+    wakeup_src0 = (int)pm_power_config->pm_wakeup_src & 0xFFFFFFFF;
+    wakeup_src1 = (int)(pm_power_config->pm_wakeup_src >> 32) & 0xFFFFFFFF;
+#ifdef TRACE_VRB
+    PRINTF("POWER_EnterPowerDownMode:\n");
+    PRINTF("  wakeup_src0      : 0x%x\n", wakeup_src0);
+    PRINTF("  wakeup_src1      : 0x%x\n", wakeup_src1);
+    PRINTF("  wakeup_io        : 0x%x\n", pm_power_config->pm_wakeup_io);
+    PRINTF("  pm_config        : 0x%x\n", pm_power_config->pm_config);
+#endif
+
+    lp_config.CFG = LOWPOWER_CFG_MODE_POWERDOWN;
+
+    /* PDRUNCFG : on ES2, flag discard to keep the same configuration than active */
+    lp_config.CFG |= LOWPOWER_CFG_PDRUNCFG_DISCARD_MASK;
+
+    /* PDSLEEPCFG (note: LDOMEM will be enabled by lowpower API if one memory bank in retention*/
+    lp_config.PMUPWDN |= LOWPOWER_PMUPWDN_DCDC | LOWPOWER_PMUPWDN_BIAS | LOWPOWER_PMUPWDN_BODVBAT;
+
+    /* Disable All banks except those given in sram_cfg */
+    lp_config.DIGPWDN |= ((LOWPOWER_DIGPWDN_SRAM_ALL_MASK) & ~(sram_cfg << LOWPOWER_DIGPWDN_SRAM0_INDEX));
+
+    // TODO : if COMM0 is disabled, need to switch off the clocks also for safe wake up
+    lp_config.DIGPWDN |= LOWPOWER_DIGPWDN_COMM0; // PDSLEEP DISABLE COM0
+
+    lp_config.DIGPWDN |=
+        LOWPOWER_DIGPWDN_MCU_RET; // PDSLEEP DISABLE retention  : on ES1, CPU retention, on ES2 Zigbee retention
+
+    // lp_config.DIGPWDN |= LOWPOWER_DIGPWDN_NTAG_FD;         // DPDWKSRC DISABLE NTAG  - not used in lowpower API in
+    // power down
+
+    lp_config.SLEEPPOSTPONE = 0;
+    lp_config.GPIOLATCH     = 0;
+
+#if gPWR_LDOMEM_0_9V_PD /* Warning : do not apply this flag , for experimental use only */
+    voltage_mem_down       = VOLTAGE_MEM_DOWN_0_9V;
+    voltage_membootst_down = VOLTAGE_MEMBOOST_DOWN_0_85V;
+#else
+    /* A bit in the flash is now set (bit 31 at address 0x9FCD4).
+     * If this bit is set, RAM retention in sleep should use voltage of 0.9v.
+     * If it is not set, RAM retention in sleep should use voltage of 1.0v. */
+    uint32_t *ate_setting = (uint32_t *)0x9FCD4;
+
+    if ((*ate_setting & 0x80000000) == 0x80000000)
+    {
+        voltage_mem_down       = VOLTAGE_MEM_DOWN_0_9V;
+        voltage_membootst_down = VOLTAGE_MEMBOOST_DOWN_0_85V;
+    }
+    else
+    {
+        voltage_mem_down       = VOLTAGE_MEM_DOWN_1_0V;
+        voltage_membootst_down = VOLTAGE_MEMBOOST_DOWN_0_96V;
+    }
+#endif
+
+    if (keep_ao_voltage)
+    {
+        LPC_LOWPOWER_LDOVOLTAGE_T ldo_voltage;
+
+        Chip_LOWPOWER_GetSystemVoltages(&ldo_voltage);
+
+        /* keep the same voltage than in active for the Always ON powerdomain */
+        lp_config.VOLTAGE = VOLTAGE(POWER_APPLY_TRIM(ldo_voltage.LDOPMU), POWER_APPLY_TRIM(ldo_voltage.LDOPMUBOOST),
+                                    POWER_APPLY_TRIM(voltage_mem_down), POWER_APPLY_TRIM(voltage_membootst_down), 0,
+                                    VOLTAGE_LDO_PMU_BOOST, 0);
+    }
+    else
+    {
+        lp_config.VOLTAGE = VOLTAGE(POWER_APPLY_TRIM(VOLTAGE_PMU_DOWN), POWER_APPLY_TRIM(VOLTAGE_PMUBOOST_DOWN),
+                                    POWER_APPLY_TRIM(voltage_mem_down), POWER_APPLY_TRIM(voltage_membootst_down), 0,
+                                    VOLTAGE_LDO_PMU_BOOST, 0);
+    }
+
+    lp_config.WAKEUPSRCINT0 = wakeup_src0;
+    lp_config.WAKEUPSRCINT1 = wakeup_src1;
+
+    /* Variation from reference */
+    if (radio_retention)
+    {
+        /* Enable Zigbee retention */
+        lp_config.DIGPWDN &= ~LOWPOWER_DIGPWDN_MCU_RET;
+    }
+
+    /* Configure IO wakeup source */
+    if (lp_config.WAKEUPSRCINT1 & LOWPOWER_WAKEUPSRCINT1_IO_IRQ)
+    {
+        lp_config.WAKEUPIOSRC = pm_power_config->pm_wakeup_io;
+    }
+
+    if (lp_config.WAKEUPSRCINT0 & LOWPOWER_WAKEUPSRCINT0_SYSTEM_IRQ)
+    {
+        /* Need to enable the BIAS for VBAT BOD */
+        lp_config.PMUPWDN &= ~(LOWPOWER_PMUPWDN_BIAS | LOWPOWER_PMUPWDN_BODVBAT);
+    }
+
+    if (lp_config.WAKEUPSRCINT0 &
+        (LOWPOWER_WAKEUPSRCINT0_USART0_IRQ | LOWPOWER_WAKEUPSRCINT0_I2C0_IRQ | LOWPOWER_WAKEUPSRCINT0_SPI0_IRQ))
+    {
+        /* Keep Flexcom0 in power down mode */
+        lp_config.DIGPWDN &= ~LOWPOWER_DIGPWDN_COMM0;
+    }
+
+    /* On ES2 , Analog comparator is already enabled in PDRUNCFG + RFT1877 : No need to keep the bias */
+    if (sram_cfg)
+    {
+        /* Configure the SRAM to SMB1 (low leakage biasing) */
+        SYSCON->SRAMCTRL =
+            (SYSCON->SRAMCTRL & (~SYSCON_SRAMCTRL_SMB_MASK)) | (SYSCON_SRAMCTRL_SMB(1) << SYSCON_SRAMCTRL_SMB_SHIFT);
+
+        /*
+         * BODMEM requires the bandgap enable in power down, this induces a power consumption increase of 1uA
+         * so Enable BODMEM only if bandgap is already enabled for BODVBAT (see code above)
+         */
+#ifndef POWER_FORCE_BODMEM_IN_PD
+        if ((lp_config.PMUPWDN & LOWPOWER_PMUPWDN_BIAS) == 0)
+#endif
+        {
+#ifdef FOR_BOD_DEBUG
+            CLOCK_EnableClock(kCLOCK_AnaInt);
+
+            /* Note: BODMEM should be already enabled in the POWER_Init() function but do it again if not */
+            if (!(PMC->PDRUNCFG & PMC_PDRUNCFG_ENA_BOD_MEM_MASK))
+            {
+                POWER_BodMemSetup();
+                /* This time, need to wait for LDO to be set up (27us) */
+                CLOCK_uDelay(27);
+            }
+            POWER_BodMemEnableInt();
+#endif
+        }
+#ifndef POWER_FORCE_BODMEM_IN_PD
+        else
+        {
+#ifdef FOR_BOD_DEBUG
+            /* Disable the BODMEM otherwise */
+            POWER_BodMemDisable();
+#endif
+        }
+#endif
+    }
+    else
+    {
+#ifdef FOR_BOD_DEBUG
+        /* Disable the BODMEM otherwise */
+        POWER_BodMemDisable();
+#endif
+    }
+#ifdef FOR_BOD_DEBUG
+    /* Disable BodCore , no longer used in power down */
+    POWER_BodCoreDisable();
+#endif
+    if (wakeup_src0 & LOWPOWER_WAKEUPSRCINT0_NFCTAG_IRQ)
+    {
+        lp_config.WAKEUPSRCINT1 |= LOWPOWER_WAKEUPSRCINT1_IO_IRQ;
+        lp_config.WAKEUPIOSRC |= LOWPOWER_WAKEUPIOSRC_NTAG_FD;
+    }
+
+    /* On Power down, NTAG field detect is enabled by IO so don t need to set the LOWPOWER_DIGPWDN_NTAG_FD */
+    // lp_config.DIGPWDN &= ~LOWPOWER_DIGPWDN_NTAG_FD;      // used for deep down only
+
+    if (autostart_32mhz_xtal)
+    {
+        lp_config.CFG |= LOWPOWER_CFG_XTAL32MSTARTENA_MASK;
+    }
+
+    /* get IO clamping state already set by the application and give it to lowpower API
+     * Lowpower API overrides the IO configuration with GPIOLATCH setting
+     */
+    lp_config.GPIOLATCH = POWER_GetIoClampConfig();
+
+    /* [RFT1911] Disable the DC bus to prevent extra consumption */
+#ifndef POWER_DCBUS_NOT_DISABLED
+    ASYNC_SYSCON->DCBUSCTRL =
+        (ASYNC_SYSCON->DCBUSCTRL & ~ASYNC_SYSCON_DCBUSCTRL_ADDR_MASK) | (1 << ASYNC_SYSCON_DCBUSCTRL_ADDR_SHIFT);
+#endif
+
+    /* [artf555998] Enable new ES2 feature for fast wakeup */
+    PMC->CTRLNORST = PMC_CTRLNORST_FASTLDOENABLE_MASK;
+
+#ifdef DUMP_CONFIG
+    LF_DumpConfig(&lp_config);
+#endif
+
+    /* If flexcom is maintained, do not disable the console and the clocks - let the application do it if needed */
+    if (lp_config.DIGPWDN & LOWPOWER_DIGPWDN_COMM0)
+    {
+        /* remove console if not done */
+        DbgConsole_Deinit();
+
+        /* Disable clocks to FLEXCOM power domain. This power domain is not reseted on wakeup by HW */
+        POWER_FlexcomClocksDisable();
+    }
+    /* Apply default LDO voltage */
+    POWER_ApplyLdoActiveVoltage(PM_LDO_VOLT_1_1V_DEFAULT);
+
+    Chip_LOWPOWER_SetLowPowerMode(&lp_config);
+
+    /* If we go here, the power mode has been aborted - this can happen only if WFI is executed in lowpower API*/
+    return false;
+}
+
+bool POWER_EnterDeepDownMode(pm_power_config_t *pm_power_config)
+{
+    int autostart_32mhz_xtal;
+    int wakeup_src0;
+    int wakeup_src1;
+    LPC_LOWPOWER_T lp_config;
+
+    memset(&lp_config, 0, sizeof(lp_config));
+
+    autostart_32mhz_xtal = pm_power_config->pm_config & PM_CFG_XTAL32M_AUTOSTART;
+
+    wakeup_src0 = (int)pm_power_config->pm_wakeup_src & 0xFFFFFFFF;
+    wakeup_src1 = (int)(pm_power_config->pm_wakeup_src >> 32) & 0xFFFFFFFF;
+
+#ifdef TRACE_VRB
+    PRINTF("POWER_EnterDeepDownMode:\n");
+    PRINTF("  wakeup_src0      : 0x%x\n", wakeup_src0);
+    PRINTF("  wakeup_src1      : 0x%x\n", wakeup_src1);
+#else
+    (void)wakeup_src0;
+#endif
+
+    lp_config.CFG = LOWPOWER_CFG_MODE_DEEPPOWERDOWN;
+
+    lp_config.PMUPWDN = LOWPOWER_PMUPWDN_DCDC | LOWPOWER_PMUPWDN_BIAS | LOWPOWER_PMUPWDN_BODVBAT |
+                        LOWPOWER_PMUPWDN_FRO192M | LOWPOWER_PMUPWDN_FRO1M;
+
+    lp_config.DIGPWDN = LOWPOWER_DIGPWDN_IO;
+
+    if (wakeup_src1 & LOWPOWER_WAKEUPSRCINT1_IO_IRQ)
+    {
+        lp_config.DIGPWDN &= ~LOWPOWER_DIGPWDN_IO;
+        lp_config.WAKEUPIOSRC = pm_power_config->pm_wakeup_io;
+    }
+
+    if (wakeup_src0 & LOWPOWER_WAKEUPSRCINT0_NFCTAG_IRQ)
+    {
+        lp_config.DIGPWDN &= ~LOWPOWER_DIGPWDN_NTAG_FD;
+    }
+    else
+    {
+        lp_config.DIGPWDN |= LOWPOWER_DIGPWDN_NTAG_FD;
+    }
+
+    lp_config.VOLTAGE = VOLTAGE(POWER_APPLY_TRIM(VOLTAGE_PMU_DEEP_DOWN), POWER_APPLY_TRIM(VOLTAGE_PMUBOOST_DEEP_DOWN),
+                                0, 0, 0, VOLTAGE_LDO_PMU_BOOST, 0);
+
+    if (autostart_32mhz_xtal)
+    {
+        lp_config.CFG |= LOWPOWER_CFG_XTAL32MSTARTENA_MASK;
+    }
+
+    /* [RFT1911] Disable the DC bus to prevent extra consumption */
+#ifndef POWER_DCBUS_NOT_DISABLED
+    ASYNC_SYSCON->DCBUSCTRL =
+        (ASYNC_SYSCON->DCBUSCTRL & ~ASYNC_SYSCON_DCBUSCTRL_ADDR_MASK) | (1 << ASYNC_SYSCON_DCBUSCTRL_ADDR_SHIFT);
+#endif
+
+    /* [artf555998] Enable new ES2 feature for fast wakeup */
+    PMC->CTRLNORST = PMC_CTRLNORST_FASTLDOENABLE_MASK;
+
+#ifdef DUMP_CONFIG
+    LF_DumpConfig(&lp_config);
+#endif
+
+    /* remove console if not done */
+    DbgConsole_Deinit();
+
+    /* Disable clocks to FLEXCOM power domain. This power domain is not reseted on wakeup by HW */
+    POWER_FlexcomClocksDisable();
+
+    Chip_LOWPOWER_SetLowPowerMode(&lp_config);
+
+    /* If we go here, the power mode has been aborted - this can happen only if WFI is executed in lowpower API*/
+    return false;
+}
+
+/*!
+ * brief Power Library API to enter different power mode.
+ *
+ * If requested mode is PM_POWER_DOWN, the API will perform the clamping of the DIOs
+ * if the PIO register has the bit IO_CLAMPING set: SYSCON->RETENTIONCTRL.IOCLAMP
+ * will be set
+ *
+ * return false if chip could not go to sleep. Configuration structure is incorrect
+ */
+bool POWER_EnterPowerMode(pm_power_mode_t pm_power_mode, pm_power_config_t *pm_power_config)
+{
+    bool ret;
+    switch (pm_power_mode)
+    {
+            /*  case PM_DEEP_SLEEP:
+                    ret = POWER_EnterDeepSleepMode(pm_power_config);
+                    break; */
+        case PM_POWER_DOWN:
+            ret = POWER_EnterPowerDownMode(pm_power_config);
+            break;
+        case PM_DEEP_DOWN:
+            ret = POWER_EnterDeepDownMode(pm_power_config);
+            break;
+        default:
+            ret = false;
+    }
+
+    return ret;
+}
+
+#ifdef DUMP_CONFIG
+static void LF_DumpConfig(LPC_LOWPOWER_T *LV_LowPowerMode)
+{
+    PRINTF("Powerdown configuration\n");
+    PRINTF("CFG:             0x%x\n", LV_LowPowerMode->CFG);
+    PRINTF("PMUPWDN:         0x%x\n", LV_LowPowerMode->PMUPWDN);
+    PRINTF("DIGPWDN:         0x%x\n", LV_LowPowerMode->DIGPWDN);
+    PRINTF("VOLTAGE:         0x%x\n", LV_LowPowerMode->VOLTAGE);
+    PRINTF("WAKEUPSRCINT0:   0x%x\n", LV_LowPowerMode->WAKEUPSRCINT0);
+    PRINTF("WAKEUPSRCINT1:   0x%x\n", LV_LowPowerMode->WAKEUPSRCINT1);
+    PRINTF("SLEEPPOSTPONE:   0x%x\n", LV_LowPowerMode->SLEEPPOSTPONE);
+    PRINTF("WAKEUPIOSRC      0x%x\n", LV_LowPowerMode->WAKEUPIOSRC);
+    PRINTF("GPIOLATCH        0x%x\n", LV_LowPowerMode->GPIOLATCH);
+    PRINTF("TIMERCFG         0x%x\n", LV_LowPowerMode->TIMERCFG);
+    PRINTF("TIMERBLECFG      0x%x\n", LV_LowPowerMode->TIMERBLECFG);
+    PRINTF("TIMERCOUNTLSB    0x%x\n", LV_LowPowerMode->TIMERCOUNTLSB);
+    PRINTF("TIMERCOUNTMSB    0x%x\n", LV_LowPowerMode->TIMERCOUNTMSB);
+    PRINTF("TIMER2NDCOUNTLSB 0x%x\n", LV_LowPowerMode->TIMER2NDCOUNTLSB);
+    PRINTF("TIMER2NDCOUNTMSB 0x%x\n", LV_LowPowerMode->TIMER2NDCOUNTMSB);
+}
+
+#endif

third_party/nxp/JN5189/drivers/fsl_power.h

@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "rom_lowpower.h"
+#include "fsl_common.h"
+
+/*! @addtogroup power */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief BODVBAT configuration flag */
+#define POWER_BOD_ENABLE           ( 1 << 0 )
+#define POWER_BOD_DISABLE          ( 0 << 0 )
+#define POWER_BOD_INT_ENABLE       ( 1 << 1 )
+#define POWER_BOD_RST_ENABLE       ( 1 << 2 )
+#define POWER_BOD_HIGH             ( 1 << 3 ) /*!< ES2 BOD VBAT only */
+#define POWER_BOD_LOW              ( 0 << 3 )
+
+/*! @brief BOD trigger level setting */
+#define POWER_BOD_LVL_1_75V        9        /*!< Default at Reset , 1.7V on ES1 */
+#define POWER_BOD_LVL_1_8V         10       /*!< BOD trigger level 1.8V */
+#define POWER_BOD_LVL_1_9V         11       /*!< BOD trigger level 1.9V */
+#define POWER_BOD_LVL_2_0V         12       /*!< BOD trigger level 2.0V */
+#define POWER_BOD_LVL_2_1V         13       /*!< BOD trigger level 2.1V */
+#define POWER_BOD_LVL_2_2V         14       /*!< BOD trigger level 2.2V */
+#define POWER_BOD_LVL_2_3V         15       /*!< BOD trigger level 2.3V */
+#define POWER_BOD_LVL_2_4V         16       /*!< BOD trigger level 2.4V */
+#define POWER_BOD_LVL_2_5V         17       /*!< BOD trigger level 2.5V */
+#define POWER_BOD_LVL_2_6V         18       /*!< BOD trigger level 2.6V */
+#define POWER_BOD_LVL_2_7V         19       /*!< BOD trigger level 2.7V */
+#define POWER_BOD_LVL_2_8V         20       /*!< BOD trigger level 2.8V */
+#define POWER_BOD_LVL_2_9V         21       /*!< BOD trigger level 2.9V */
+#define POWER_BOD_LVL_3_0V         22       /*!< BOD trigger level 3.0V */
+#define POWER_BOD_LVL_3_1V         23       /*!< BOD trigger level 3.1V */
+#define POWER_BOD_LVL_3_2V         24       /*!< BOD trigger level 3.2V */
+#define POWER_BOD_LVL_3_3V         25       /*!< BOD trigger level 3.3V */
+
+/*! @brief BOD Hysteresis control setting */
+#define POWER_BOD_HYST_25MV        0        /*!< BOD Hysteresis control 25mV */
+#define POWER_BOD_HYST_50MV        1        /*!< BOD Hysteresis control 50mV */
+#define POWER_BOD_HYST_75MV        2        /*!< BOD Hysteresis control 75mV */
+#define POWER_BOD_HYST_100MV       3        /*!< BOD Hysteresis control 100mV, default at Reset */
+
+/**
+ * @brief  SRAM banks definition list for retention in power down modes !
+ */
+#define        PM_CFG_SRAM_BANK_BIT_BASE   0
+#define        PM_CFG_SRAM_BANK0_RET       (1<<0)   /*!< On ES1, this bank shall be kept in retention for Warmstart from power down */
+#define        PM_CFG_SRAM_BANK1_RET       (1<<1)   /*!< Bank 1 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK2_RET       (1<<2)   /*!< Bank 2 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK3_RET       (1<<3)   /*!< Bank 3 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK4_RET       (1<<4)   /*!< Bank 4 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK5_RET       (1<<5)   /*!< Bank 5 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK6_RET       (1<<6)   /*!< Bank 6 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK7_RET       (1<<7)   /*!< On ES2, this bank shall be kept in retention for Warmstart */
+#define        PM_CFG_SRAM_BANK8_RET       (1<<8)   /*!< Bank 8 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK9_RET       (1<<9)   /*!< Bank 9 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK10_RET      (1<<10)  /*!< Bank 10 shall be kept in retention */
+#define        PM_CFG_SRAM_BANK11_RET      (1<<11)  /*!< Bank 11 shall be kept in retention */
+
+#define        PM_CFG_SRAM_ALL_RETENTION   0xFFF    /*!< All banks shall be kept in retention */
+
+#define        PM_CFG_RADIO_RET            (1<<13)
+#define        PM_CFG_XTAL32M_AUTOSTART    (1<<14)
+#define        PM_CFG_KEEP_AO_VOLTAGE      (1<<15)  /*!< keep the same voltage on the Always-on power domain - typical used with FRO32K to avoid timebase drift */
+
+#define POWER_WAKEUPSRC_SYSTEM         LOWPOWER_WAKEUPSRCINT0_SYSTEM_IRQ         /*!< BOD, Watchdog Timer, Flash controller, [DEEP SLEEP] BODVBAT [POWER_DOWN]*/
+#define POWER_WAKEUPSRC_DMA            LOWPOWER_WAKEUPSRCINT0_DMA_IRQ            /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_GINT           LOWPOWER_WAKEUPSRCINT0_GINT_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_IRBLASTER      LOWPOWER_WAKEUPSRCINT0_IRBLASTER_IRQ      /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PINT0          LOWPOWER_WAKEUPSRCINT0_PINT0_IRQ          /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PINT1          LOWPOWER_WAKEUPSRCINT0_PINT1_IRQ          /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PINT2          LOWPOWER_WAKEUPSRCINT0_PINT2_IRQ          /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PINT3          LOWPOWER_WAKEUPSRCINT0_PINT3_IRQ          /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_SPIFI          LOWPOWER_WAKEUPSRCINT0_SPIFI_IRQ          /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_TIMER0         LOWPOWER_WAKEUPSRCINT0_TIMER0_IRQ         /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_TIMER1         LOWPOWER_WAKEUPSRCINT0_TIMER1_IRQ         /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_USART0         LOWPOWER_WAKEUPSRCINT0_USART0_IRQ         /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_USART1         LOWPOWER_WAKEUPSRCINT0_USART1_IRQ         /*!< [DEEP SLEEP]  */
+#define POWER_WAKEUPSRC_I2C0           LOWPOWER_WAKEUPSRCINT0_I2C0_IRQ           /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_I2C1           LOWPOWER_WAKEUPSRCINT0_I2C1_IRQ           /*!< [DEEP SLEEP]  */
+#define POWER_WAKEUPSRC_SPI0           LOWPOWER_WAKEUPSRCINT0_SPI0_IRQ           /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_SPI1           LOWPOWER_WAKEUPSRCINT0_SPI1_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM0           LOWPOWER_WAKEUPSRCINT0_PWM0_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM1           LOWPOWER_WAKEUPSRCINT0_PWM1_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM2           LOWPOWER_WAKEUPSRCINT0_PWM2_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM3           LOWPOWER_WAKEUPSRCINT0_PWM3_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM4           LOWPOWER_WAKEUPSRCINT0_PWM4_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM5           LOWPOWER_WAKEUPSRCINT0_PWM5_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM6           LOWPOWER_WAKEUPSRCINT0_PWM6_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM7           LOWPOWER_WAKEUPSRCINT0_PWM7_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM8           LOWPOWER_WAKEUPSRCINT0_PWM8_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM9           LOWPOWER_WAKEUPSRCINT0_PWM9_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_PWM10          LOWPOWER_WAKEUPSRCINT0_PWM10_IR           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_I2C2           LOWPOWER_WAKEUPSRCINT0_I2C2_IRQ           /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_RTC            LOWPOWER_WAKEUPSRCINT0_RTC_IRQ            /*!< [DEEP SLEEP, POWER DOWN]  */
+#define POWER_WAKEUPSRC_NFCTAG         LOWPOWER_WAKEUPSRCINT0_NFCTAG_IRQ         /*!< [DEEP SLEEP, POWER DOWN (ES2 Only), DEEP DOWN (ES2 only)]  */
+#define POWER_WAKEUPSRC_MAILBOX        LOWPOWER_WAKEUPSRCINT0_MAILBOX_IRQ        /*!< Mailbox, Wake-up from DEEP SLEEP and POWER DOWN low power mode [DEEP SLEEP, POWER DOWN] */
+
+#define POWER_WAKEUPSRC_ADC_SEQA       ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_SEQA_IRQ       << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_ADC_SEQB       ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_SEQB_IRQ       << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_ADC_THCMP_OVR  ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_THCMP_OVR_IRQ  << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_DMIC           ((uint64_t)LOWPOWER_WAKEUPSRCINT1_DMIC_IRQ           << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_HWVAD          ((uint64_t)LOWPOWER_WAKEUPSRCINT1_HWVAD_IRQ          << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_BLE_DP         ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP_IRQ         << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_BLE_DP0        ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP0_IRQ        << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_BLE_DP1        ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP1_IRQ        << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_BLE_DP2        ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP2_IRQ        << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_BLE_LL_ALL     ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_LL_ALL_IRQ     << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_ZIGBEE_MAC     ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MAC_IRQ     << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_ZIGBEE_MODEM   ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MODEM_IRQ   << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_RFP_TMU        ((uint64_t)LOWPOWER_WAKEUPSRCINT1_RFP_TMU_IRQ        << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_RFP_AGC        ((uint64_t)LOWPOWER_WAKEUPSRCINT1_RFP_AGC_IRQ        << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_ISO7816        ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ISO7816_IRQ        << 32)  /*!< [DEEP SLEEP] */
+#define POWER_WAKEUPSRC_ANA_COMP       ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ANA_COMP_IRQ       << 32)  /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_WAKE_UP_TIMER0 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER0_IRQ << 32)  /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_WAKE_UP_TIMER1 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER1_IRQ << 32)  /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_BLE_WAKE_TIMER ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_WAKE_TIMER_IRQ << 32)  /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_BLE_OSC_EN     ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_OSC_EN_IRQ     << 32)  /*!< [DEEP SLEEP, POWER DOWN] */
+#define POWER_WAKEUPSRC_IO             ((uint64_t)LOWPOWER_WAKEUPSRCINT1_IO_IRQ             << 32)  /*!< [POWER DOWN, DEEP DOWN]  */
+
+/**
+ * @brief  BOD config
+ */
+typedef struct {
+    uint8_t bod_level;  /*!< BOD trigger level */
+    uint8_t bod_hyst;   /*!< BOD Hysteresis control */
+    uint8_t bod_cfg;    /*!< BOD config setting */
+} pm_bod_cfg_t;
+
+typedef uint64_t       pm_wake_source_t;
+
+/**
+ * @brief  PDRUNCFG bits offset
+ */
+typedef enum pd_bits
+{
+    kPDRUNCFG_PD_LDO_ADC_EN = 22,           /*!< Offset is 22, LDO ADC enabled */
+    kPDRUNCFG_PD_BOD_MEM_EN = 23,           /*!< Offset is 23, BOD MEM enabled */
+    kPDRUNCFG_PD_BOD_CORE_EN = 24,          /*!< Offset is 24, BOD CORE enabled */
+    kPDRUNCFG_PD_FRO32K_EN       = 25,      /*!< Offset is 25, FRO32K enabled */
+    kPDRUNCFG_PD_XTAL32K_EN      = 26,      /*!< Offset is 26, XTAL32K enabled */
+    kPDRUNCFG_PD_BOD_ANA_COMP_EN = 27,      /*!< Offset is 27, Analog Comparator enabled */
+
+    kPDRUNCFG_ForceUnsigned = 0x80000000U
+} pd_bit_t;
+
+/**
+ * @brief  Power modes
+ */
+typedef enum {
+    /* PM_DEEP_SLEEP, */
+    PM_POWER_DOWN,  /*!< Power down mode */
+    PM_DEEP_DOWN,   /*!< Deep power down mode */
+} pm_power_mode_t ;
+
+/**
+ * @brief  Power config
+ */
+typedef struct {
+    pm_wake_source_t pm_wakeup_src; /*!< Wakeup source select */
+    uint32_t         pm_wakeup_io;  /*!< Wakeup IO */
+    uint32_t         pm_config;     /*!< Power mode config */
+} pm_power_config_t;
+
+/**
+ * @brief  Reset Cause definition
+ */
+typedef enum reset_cause
+{
+    RESET_UNDEFINED     = 0,
+    RESET_POR           = (1 << 0), /*!< The last chip reset was caused by a Power On Reset. */
+    RESET_EXT_PIN       = (1 << 1), /*!< The last chip reset was caused by a Pad Reset. */
+    RESET_BOR           = (1 << 2), /*!< The last chip reset was caused by a Brown Out Detector. */
+    RESET_SYS_REQ       = (1 << 3), /*!< The last chip reset was caused by a System Reset requested by the ARM CPU. */
+    RESET_WDT           = (1 << 4), /*!< The last chip reset was caused by the Watchdog Timer. */
+    RESET_WAKE_DEEP_PD  = (1 << 5), /*!< The last chip reset was caused by a Wake-up I/O (GPIO or internal NTAG FD INT). */
+    RESET_WAKE_PD       = (1 << 6), /*!< The last CPU reset was caused by a Wake-up from Power down (many sources possible: timer, IO, ...). */
+    RESET_SW_REQ        = (1 << 7)  /*!< The last chip reset was caused by a Software. ES2 Only */
+} reset_cause_t;
+
+/**
+ * @brief  LDO voltage setting
+ */
+typedef enum {
+    PM_LDO_VOLT_1_1V_DEFAULT,   /*!< LDO voltage 1.1V */
+    PM_LDO_VOLT_1_0V,  /*!< not safe at system start/wakeup and CPU clock switch to higher frequency */
+} pm_ldo_volt_t ;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @name Power Configuration
+* @{
+*/
+
+/*!
+ * @brief Initialize the sdk power drivers
+ *
+ * Optimize the LDO voltage for power saving
+ * Initialize the power domains
+ *
+ * @return none
+ */
+void POWER_Init(void);
+
+/*!
+ * @brief  Optimize the LDO voltage for power saving
+ * Initialize the power domains
+ *
+ * @return none
+ */
+void POWER_SetTrimDefaultActiveVoltage(void);
+
+/*!
+ * @brief BODMEM and BODCORE setup
+ *
+ * Enable the BOD core and BOD mem
+ * Disable the analog comnparator clock
+ *
+ * @return none
+ */
+void POWER_BodSetUp(void);
+
+/*!
+ * @brief enable SW reset for the BODCORE
+ *
+ * @return none
+ */
+void POWER_BodActivate(void);
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
+ *
+ * @param en    peripheral for which to enable the PDRUNCFG bit
+ *
+ * @return none
+ */
+static inline void POWER_EnablePD(pd_bit_t en)
+{
+    /* PDRUNCFGSET */
+    PMC->PDRUNCFG |= (1UL << (en & 0xffU));
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
+ *
+ * @param en    peripheral for which to disable the PDRUNCFG bit
+ *
+ * @return none
+ */
+static inline void POWER_DisablePD(pd_bit_t en)
+{
+    /* PDRUNCFGCLR */
+    PMC->PDRUNCFG &= ~(1UL << (en & 0xffU));
+}
+
+/*!
+ *  @brief Get IO and Ntag Field detect Wake-up sources from Power Down and Deep Power Down modes.
+ *  Allow to identify the wake-up source when waking up from Power-Down modes or Deep Power Down modes.
+ *  Status is reset by POR, RSTN, WDT.
+ *  bit in range from 0 to 21 are for DIO0 to DIO21
+ *  bit 22 is NTAG field detect wakeup source
+ *
+ *  @return IO and Field detect Wake-up source
+ */
+static inline uint32_t POWER_GetIoWakeStatus(void)
+{
+    return PMC->WAKEIOCAUSE;
+}
+
+/*!
+ * @brief Power API to enter sleep mode (Doze mode)
+ *
+ * @note: The static inline function has not the expecetd effect in -O0. If order to force inline this macro is added
+ *
+ * @return none
+ */
+#define POWER_ENTER_SLEEP()  __DSB(); __WFI(); __ISB();
+
+/*!
+ * @brief Power API to enter sleep mode (Doze mode)
+ *
+ * @note: If the user desires to program a wakeup timer before going to sleep, it needs to use
+ * either the fsl_wtimer.h API or use the POWER_SetLowPower() API instead
+ * see POWER_ENTER_SLEEP
+ *
+ * @return none
+ */
+static inline void POWER_EnterSleep(void)
+{
+    POWER_ENTER_SLEEP();
+}
+
+/*!
+ * @brief Power Library API to enter different power mode.
+ * If requested mode is PM_POWER_DOWN, the API will perform the clamping of the DIOs
+ * if the PIO register has the bit IO_CLAMPING set: SYSCON->RETENTIONCTRL.IOCLAMP
+ * will be set
+ *
+ * @param pm_power_mode  Power modes
+ * @see pm_power_mode_t
+ * @param pm_power_config Power config
+ * @see pm_power_config_t
+ *
+ * @return false if chip could not go to sleep. Configuration structure is incorrect
+ */
+bool POWER_EnterPowerMode(pm_power_mode_t pm_power_mode, pm_power_config_t* pm_power_config);
+
+/*!
+ * @brief determine cause of reset
+ *
+ * @return reset_cause
+ */
+reset_cause_t POWER_GetResetCause(void);
+
+/*!
+ * @brief Clear cause of reset
+ */
+void POWER_ClearResetCause(void);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @param none
+ *
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+/*!
+ * @brief Get default Vbat BOD config parameters, level @1.75V, Hysteresis @ 100mV
+ *
+ * @param bod_cfg_p BOD config
+ * @see pm_bod_cfg_t
+ *
+ * @return none
+ */
+void POWER_BodVbatGetDefaultConfig(pm_bod_cfg_t * bod_cfg_p);
+
+/*!
+ * @brief Configure the VBAT BOD
+ *
+ * @param bod_cfg_p BOD config
+ * @see pm_bod_cfg_t
+ *
+ * @return false if configuration parameters are incorrect
+ */
+bool POWER_BodVbatConfig(pm_bod_cfg_t * bod_cfg_p);
+
+/*!
+ * @brief Configure the LDO voltage
+ *
+ * @param ldoVolt LDO voltage setting
+ * @see pm_ldo_volt_t
+ *
+ * @return none
+ */
+void POWER_ApplyLdoActiveVoltage(pm_ldo_volt_t ldoVolt);
+
+/* @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_POWER_H_ */

third_party/nxp/JN5189/drivers/fsl_reset.c

@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+#include "rom_lowpower.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* RG TODO This should be defined in jn518x.h */
+#define SYSCON_PRESETCTRL_COUNT 	2
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* set bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* set bit */
+        SYSCON->PRESETCTRLSETS[regIndex] = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (SYSCON->PRESETCTRLS[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset > SYSCON_PRESETCTRL_COUNT */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* clear bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* clear bit */
+        SYSCON->PRESETCTRLCLRS[regIndex] = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (SYSCON->PRESETCTRLS[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
+
+
+/*!
+ * brief Reset the chip.
+ *
+ * Full software reset of the chip.
+ * On reboot, function POWER_GetResetCause() from fsl_power.h will return RESET_SYS_REQ
+ */
+void RESET_SystemReset(void)
+{
+    /* Disable all interrupts */
+    __disable_irq();
+    /* On ES2, software reset is directly implemented in ROM code so the Flash
+     * controller can be correctly powered OFF before the reset */
+    Chip_LOWPOWER_ChipSoftwareReset();
+}

third_party/nxp/JN5189/drivers/fsl_reset.h

@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+    kFLASH_RST_SHIFT_RSTn   = (0 | SYSCON_PRESETCTRL0_FLASH_RST_SHIFT), /**< Flash controller reset control */
+    kSPIFI_RST_SHIFT_RSTn   = (0 | SYSCON_PRESETCTRL0_SPIFI_RST_SHIFT), /**< SpiFi reset control   */
+    kMUX_RST_SHIFT_RSTn     = (0 | SYSCON_PRESETCTRL0_MUX_RST_SHIFT),   /**< Input mux reset control */
+    kIOCON_RST_SHIFT_RSTn   = (0 | SYSCON_PRESETCTRL0_IOCON_RST_SHIFT), /**< IOCON reset control */
+    kGPIO0_RST_SHIFT_RSTn   = (0 | SYSCON_PRESETCTRL0_GPIO_RST_SHIFT),  /**< GPIO0 reset control */
+    kPINT_RST_SHIFT_RSTn    = (0 | SYSCON_PRESETCTRL0_PINT_RST_SHIFT),  /**< Pin interrupt (PINT) reset control */
+    kGINT_RST_SHIFT_RSTn    = (0 | SYSCON_PRESETCTRL0_GINT_RST_SHIFT),  /**< Grouped interrupt (PINT) reset control. */
+    kDMA_RST_SHIFT_RSTn     = (0 | SYSCON_PRESETCTRL0_DMA_RST_SHIFT),   /**< DMA reset control */
+    kWWDT_RST_SHIFT_RSTn    = (0 | SYSCON_PRESETCTRL0_WWDT_RST_SHIFT),  /**< Watchdog timer reset control */
+    kRTC_RST_SHIFT_RSTn     = (0 | SYSCON_PRESETCTRL0_RTC_RST_SHIFT),   /**< RTC reset control */
+    kANA_INT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_ANA_INT_CTRL_RST_SHIFT), /**< Analog interrupt controller reset */
+    kWKT_RST_SHIFT_RSTn     = (0 | SYSCON_PRESETCTRL0_WAKE_UP_TIMERS_RST_SHIFT), /**< Wakeup timer reset */
+    kADC0_RST_SHIFT_RSTn    = (0 | SYSCON_PRESETCTRL0_ADC_RST_SHIFT),            /**< ADC0 reset control */
+    kEFUSE_RST_SHIFT_RSTn   = (0 | SYSCON_PRESETCTRL0_EFUSE_RST_SHIFT),          /**< EFUSE reset control */
+    kFC0_RST_SHIFT_RSTn =
+        ((1UL << 16) | SYSCON_PRESETCTRL1_USART0_RST_SHIFT), /**< Flexcomm Interface 0 reset control */
+    kFC1_RST_SHIFT_RSTn =
+        ((1UL << 16) | SYSCON_PRESETCTRL1_USART1_RST_SHIFT),                 /**< Flexcomm Interface 1 reset control */
+    kFC2_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_I2C0_RST_SHIFT), /**< Flexcomm Interface 2 reset control */
+    kFC3_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_I2C1_RST_SHIFT), /**< Flexcomm Interface 3 reset control */
+    kFC4_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_SPI0_RST_SHIFT), /**< Flexcomm Interface 4 reset control */
+    kFC5_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_SPI1_RST_SHIFT), /**< Flexcomm Interface 5 reset control */
+    kIRB_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_IR_RST_SHIFT),   /**< IR Blaster reset control */
+    kPWM_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_PWM_RST_SHIFT),  /**< PWM reset control */
+    kRNG_RST_SHIFT_RSTn =
+        ((1UL << 16) | SYSCON_PRESETCTRL1_RNG_RST_SHIFT), /**< Random number generator reset control */
+    kFC6_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_I2C2_RST_SHIFT), /**< Flexcomm Interface 6 reset control */
+    kUSART0_RST_SHIFT_RSTn = kFC0_RST_SHIFT_RSTn,                            /**< USART0 reset control == Flexcomm0 */
+    kUSART1_RST_SHIFT_RSTn = kFC1_RST_SHIFT_RSTn,                            /**< USART0 reset control == Flexcomm1 */
+    kI2C0_RST_SHIFT_RSTn   = kFC2_RST_SHIFT_RSTn,                            /**< I2C0 reset control == Flexcomm 2  */
+    kI2C1_RST_SHIFT_RSTn   = kFC3_RST_SHIFT_RSTn,                            /**< I2C1 reset control == Flexcomm 3  */
+    kSPI0_RST_SHIFT_RSTn   = kFC4_RST_SHIFT_RSTn,                            /**< SPI0 reset control == Flexcomm 4  */
+    kSPI1_RST_SHIFT_RSTn   = kFC5_RST_SHIFT_RSTn,                            /**< SPI1 reset control == Flexcomm 5  */
+    kI2C2_RST_SHIFT_RSTn   = kFC6_RST_SHIFT_RSTn,                            /**< I2C2 reset control == Flexcomm 6  */
+    kMODEM_MASTER_SHIFT_RSTn =
+        ((1UL << 16) | SYSCON_PRESETCTRL1_MODEM_MASTER_RST_SHIFT),          /**< AHB Modem master interface reset */
+    kAES_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_AES_RST_SHIFT), /**< Encryption module reset control */
+    kRFP_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_RFP_RST_SHIFT), /**< Radio front end controller reset */
+    kDMIC_RST_SHIFT_RSTn =
+        ((1UL << 16) | SYSCON_PRESETCTRL1_DMIC_RST_SHIFT), /**< Digital microphone interface reset control */
+    kHASH_RST_SHIFT_RSTn    = ((1UL << 16) | SYSCON_PRESETCTRL1_HASH_RST_SHIFT),         /**< Hash SHA reset */
+    kCTIMER0_RST_SHIFT_RSTn = ((2UL << 16) | ASYNC_SYSCON_ASYNCPRESETCTRL_CT32B0_SHIFT), /**< CT32B0 reset control */
+    kCTIMER1_RST_SHIFT_RSTn = ((2UL << 16) | ASYNC_SYSCON_ASYNCPRESETCTRL_CT32B1_SHIFT), /**< CT32B1 reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS             \
+    {                        \
+        kADC0_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define AES_RSTS             \
+    {                        \
+        kAES_RST_SHIFT_RSTbn \
+    } /* Reset bits for Encryption peripheral */
+#define ANA_INT_RSTS            \
+    {                           \
+        kANA_INT_RST_SHIFT_RSTn \
+    } /* Reset bits for Analog interrupts controller */
+#define BLE_RSTS            \
+    {                       \
+        kBLE_RST_SHIFT_RSTn \
+    } /* Reset bits for Bluetooth LE peripheral */
+#define BLE_TG_RSTS            \
+    {                          \
+        kBLE_TG_RST_SHIFT_RSTn \
+    } /* Bluetooth LE power module reset */
+#define CRC_RSTS            \
+    {                       \
+        kCRC_RST_SHIFT_RSTn \
+    } /* Reset bits for CRC peripheral */
+#define CTIMER_RSTS                                      \
+    {                                                    \
+        kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn \
+    } /* Reset bits for TIMER peripheral */
+#define DMA_RSTS_N          \
+    {                       \
+        kDMA_RST_SHIFT_RSTn \
+    } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS            \
+    {                        \
+        kDMIC_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define EFUSE_RSTS            \
+    {                         \
+        kEFUSE_RST_SHIFT_RSTn \
+    } /* Reset bits for EFuse peripheral */
+#define FLASH_RSTS            \
+    {                         \
+        kFLASH_RST_SHIFT_RSTn \
+    } /* Reset bits for flash controller */
+#define FLEXCOMM_RSTS                                                                                            \
+    {                                                                                                            \
+        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn                                                             \
+    } /* Reset bits for FLEXCOMM peripheral */
+#define GINT_RSTS            \
+    {                        \
+        kGINT_RST_SHIFT_RSTn \
+    } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
+#define GPIO_RSTS_N           \
+    {                         \
+        kGPIO0_RST_SHIFT_RSTn \
+    } /* Reset bits for GPIO peripheral */
+#define INPUTMUX_RSTS       \
+    {                       \
+        kMUX_RST_SHIFT_RSTn \
+    } /* Reset bits for INPUTMUX peripheral */
+#define IOCON_RSTS            \
+    {                         \
+        kIOCON_RST_SHIFT_RSTn \
+    } /* Reset bits for IOCON peripheral */
+#define ZIGBEE_RSTS            \
+    {                          \
+        kZIGBEE_RST_SHIFT_RSTn \
+    } /* Reset bits for RF/Zigbee peripheral */
+#define MAILBOX_RSTS            \
+    {                           \
+        kMAILBOX_RST_SHIFT_RSTn \
+    } /* Reset bits for inter-CPU mailbox peripheral */
+#define MODEM_RSTS               \
+    {                            \
+        kMODEM_MASTER_SHIFT_RSTn \
+    } /* Reset bits for AHB Modem master interface peripheral */
+#define MRT_RSTS            \
+    {                       \
+        kMRT_RST_SHIFT_RSTn \
+    } /* Reset bits for MRT peripheral */
+#define PINT_RSTS            \
+    {                        \
+        kPINT_RST_SHIFT_RSTn \
+    } /* Reset bits for PINT peripheral */
+#define PVT_RSTS            \
+    {                       \
+        kPVT_RST_SHIFT_RSTn \
+    } /* Reset bits for PVT peripheral */
+#define RTC_RSTS            \
+    {                       \
+        kRTC_RST_SHIFT_RSTn \
+    } /* Reset bits for RTC peripheral */
+#define SPIFI_RSTS            \
+    {                         \
+        kSPIFI_RST_SHIFT_RSTn \
+    } /* Reset bits for SPIFI peripheral */
+#define TPR_RSTS            \
+    {                       \
+        kTPR_RST_SHIFT_RSTn \
+    } /* Reset bits for test pointer register peripheral */
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for windowed watchdog timer */
+
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for WWDT peripheral */
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset the chip.
+ *
+ * Full software reset of the chip.
+ * On reboot, function POWER_GetResetCause() from fsl_power.h will return RESET_SYS_REQ
+ */
+void RESET_SystemReset(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */

third_party/nxp/JN5189/drivers/fsl_rng.c

@@ -0,0 +1,130 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_rng.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.jn_rng"
+#endif
+
+#define TRNG_MODE_SEL_BIT_NUM (0)
+#define TRNG_MODE_SEL_BIT_MASK (0x3 << TRNG_MODE_SEL_BIT_NUM)
+#define TRNG_CLOCK_SEL_BIT_NUM (2)
+#define TRNG_CLOCK_SEL_BIT_MASK (0x7 << TRNG_CLOCK_SEL_BIT_NUM)
+#define TRNG_SHIFT4X_BIT_NUM (5)
+#define TRNG_SHIFT4X_BIT_MASK (0x7 << TRNG_SHIFT4X_BIT_NUM)
+
+/*******************************************************************************
+ * Public APIs
+ ******************************************************************************/
+
+status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
+{
+    /* Check if valid parameters */
+    if (userConfig == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialise configuration structure */
+    userConfig->shift4x   = 0;
+    userConfig->clock_sel = 0;
+    userConfig->mode      = trng_FreeRunning;
+    return kStatus_Success;
+}
+
+status_t TRNG_Init(RNG_Type *base, const trng_config_t *userConfig)
+{
+    /* Check if valid parameters are passed */
+    if ((base == NULL) || (userConfig == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check if valid parameters are passed */
+    if ((userConfig->mode != trng_UpdateOnce) && (userConfig->mode != trng_FreeRunning))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Enable RNG peripheral clock for register access */
+    /* Make sure that the XTAL 32MHz clock is enabled before this */
+    if (!(ASYNC_SYSCON->XTAL32MCTRL & ASYNC_SYSCON_XTAL32MCTRL_XO_ENABLE_MASK))
+    {
+        return kStatus_Fail;
+    }
+    SYSCON->PRESETCTRLSET[1] = SYSCON_PRESETCTRLSET1_RNG_RST_SET_MASK;
+    //CLOCK_EnableClock(kCLOCK_Xtal32M);
+    CLOCK_EnableClock(kCLOCK_Rng);
+    SYSCON->PRESETCTRLCLR[1] = SYSCON_PRESETCTRLCLR1_RNG_RST_CLR_MASK;
+
+    /* Enable Analog clocks for RNG module */
+    SYSCON->RNGCLKCTRL = 1;
+
+    /* Configure TRNG module */
+    base->COUNTER_CFG &= ~(TRNG_CLOCK_SEL_BIT_MASK | TRNG_SHIFT4X_BIT_MASK | TRNG_MODE_SEL_BIT_MASK);
+    base->COUNTER_CFG |=
+        ((userConfig->clock_sel << TRNG_CLOCK_SEL_BIT_NUM) | (userConfig->shift4x << TRNG_SHIFT4X_BIT_NUM));
+
+    /* Set mode */
+    base->COUNTER_CFG |= userConfig->mode;
+
+    return kStatus_Success;
+}
+
+void TRNG_Deinit(RNG_Type *base)
+{
+    /* Disable Analog clocks for RNG module */
+    SYSCON->RNGCLKCTRL = 0;
+
+    /* Disable RNG clock */
+    CLOCK_DisableClock(kCLOCK_Rng);
+    return;
+}
+
+status_t TRNG_GetRandomData(RNG_Type *base, void *data, size_t data_size)
+{
+    uint32_t random_32;
+    uint8_t *random_p;
+    uint32_t random_size;
+    uint8_t *data_p = (uint8_t *)data;
+    uint32_t i;
+
+    /* Check if valid parameters */
+    if ((base == NULL) || (data == NULL) || (data_size == 0))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Read random data as per user request */
+    do
+    {
+        /* Read random data from register Entropy.*/
+        random_32 = base->RANDOM_NUMBER;
+
+        /* Extract required bytes */
+        random_p = (uint8_t *)&random_32;
+
+        if (data_size < sizeof(random_32))
+        {
+            random_size = data_size;
+        }
+        else
+        {
+            random_size = sizeof(random_32);
+        }
+
+        for (i = 0U; i < random_size; i++)
+        {
+            *data_p++ = *random_p++;
+        }
+
+        data_size -= random_size;
+    } while (data_size > 0);
+
+    return kStatus_Success;
+}

third_party/nxp/JN5189/drivers/fsl_rng.h

@@ -0,0 +1,95 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_RNG_H_
+#define __FSL_RNG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup jn_rng
+ * @{
+ */
+
+/*! @file */
+
+/**
+ * RNG return status types
+ */
+
+/**
+ * RNG operating modes
+ */
+typedef enum _trng_mode
+{
+    trng_UpdateOnce  = 0x1, /*!< TRNG update once & disable */
+    trng_FreeRunning = 0x2, /*!< TRNG updates continuously */
+} trng_mode_t;
+
+typedef struct _trng_config
+{
+    uint8_t shift4x;   /*!< Used to add precision to clock ratio & entropy refill - range from 0 to 4 */
+    uint8_t clock_sel; /*!< Internal clock on which to compute statistics */
+                       /*!< 0 - XOR results from all clocks */
+                       /*!< 1 - First clock */
+                       /*!< 2 - Second clock */
+    trng_mode_t mode;  /*!< TRNG mode select */
+} trng_config_t;
+
+/*!
+ * @brief Gets Default config of TRNG.
+ *
+ * This function initializes the TRNG configuration structure.
+ *
+ * @param userConfig Pointer to TRNG configuration structure
+ */
+status_t TRNG_GetDefaultConfig(trng_config_t *userConfig);
+
+/*!
+ * @brief Initializes the TRNG.
+ *
+ * This function initializes the TRNG.
+ *
+ * @param base TRNG base address
+ * @param userConfig The configuration of TRNG
+ * @return  kStatus_Success - Success
+ *          kStatus_InvalidArgument - Invalid parameter
+ */
+status_t TRNG_Init(RNG_Type *base, const trng_config_t *userConfig);
+
+/*!
+ * @brief Shuts down the TRNG.
+ *
+ * This function shuts down the TRNG.
+ *
+ * @param base TRNG base address
+ */
+void TRNG_Deinit(RNG_Type *base);
+
+/*!
+ * @brief Gets random data.
+ *
+ * This function gets random data from the TRNG.
+ *
+ * @param base TRNG base address
+ * @param data pointer to user buffer to be filled by random data
+ * @param data_size size of data in bytes
+ * @return TRNG status
+ */
+status_t TRNG_GetRandomData(RNG_Type *base, void *data, size_t data_size);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __RNG_JN518X_H_*/

third_party/nxp/JN5189/drivers/fsl_usart.c

@@ -0,0 +1,939 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"
+#endif
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+/*! brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++)
+    {
+        if ((uint32_t)base == s_usartBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle USART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+    size_t size;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    {
+        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+    }
+    else
+    {
+        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+    }
+    return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+    bool full;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer     = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+    /* ring buffer is ready we can start receiving data */
+    base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+
+    if (handle->rxState == kUSART_RxIdle)
+    {
+        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+    }
+    handle->rxRingBuffer     = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param config Pointer to user-defined configuration structure.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_InvalidArgument USART base address is not valid
+ * retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+    int result;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to USART mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (config->enableTx)
+    {
+        /* empty and enable txFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+    }
+
+    /* empty and enable rxFIFO */
+    if (config->enableRx)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+    }
+    /* setup configuration and enable USART */
+    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |
+                USART_CFG_SYNCEN(config->syncMode >> 1) | USART_CFG_SYNCMST(config->syncMode) |
+                USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK;
+
+    /* Setup baudrate */
+    result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+    /* Setting continuous Clock configuration. used for synchronous mode. */
+    USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+                         USART_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+    /* Check arguments */
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    /* Set always all members ! */
+    config->baudRate_Bps         = 115200U;
+    config->parityMode           = kUSART_ParityDisabled;
+    config->stopBitCount         = kUSART_OneStopBit;
+    config->bitCountPerChar      = kUSART_8BitsPerChar;
+    config->loopback             = false;
+    config->enableRx             = false;
+    config->enableTx             = false;
+    config->txWatermark          = kUSART_TxFifo0;
+    config->rxWatermark          = kUSART_RxFifo1;
+    config->syncMode             = kUSART_SyncModeDisabled;
+    config->enableContinuousSCLK = false;
+    config->clockPolarity        = kUSART_RxSampleOnFallingEdge;
+}
+
+/*!
+ * brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param baudrate_Bps USART baudrate to be set.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+    uint32_t osrval, brgval, diff, baudrate;
+
+    /* check arguments */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If synchronous master mode is enabled, only configure the BRG value. */
+    if (base->CFG & USART_CFG_SYNCEN_MASK)
+    {
+        if (base->CFG & USART_CFG_SYNCMST_MASK)
+        {
+            brgval    = srcClock_Hz / baudrate_Bps;
+            base->BRG = brgval - 1;
+        }
+    }
+    else
+    {
+        /*
+         * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+         * potentially cause more noise errors or incorrect data.
+         */
+        for (osrval = best_osrval; osrval >= 8; osrval--)
+        {
+            brgval = (((srcClock_Hz * 10) / ((osrval + 1) * baudrate_Bps)) - 5) / 10;
+            if (brgval > 0xFFFF)
+            {
+                continue;
+            }
+            baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1));
+            diff     = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
+            if (diff < best_diff)
+            {
+                best_diff   = diff;
+                best_osrval = osrval;
+                best_brgval = brgval;
+            }
+        }
+
+        /* value over range */
+        if (best_brgval > 0xFFFF)
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+
+        base->OSR = best_osrval;
+        base->BRG = best_brgval;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return;
+    }
+    /* Check whether txFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+    {
+        return;
+    }
+    for (; length > 0; length--)
+    {
+        /* Loop until txFIFO get some space for new data */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+        }
+        base->FIFOWR = *data;
+        data++;
+    }
+    /* Wait to finish transfer */
+    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+    uint32_t status;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check whether rxFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK))
+    {
+        return kStatus_Fail;
+    }
+    for (; length > 0; length--)
+    {
+        /* loop until rxFIFO have some data to read */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+        }
+        /* check receive status */
+        status = base->STAT;
+        if (status & USART_STAT_FRAMERRINT_MASK)
+        {
+            base->STAT |= USART_STAT_FRAMERRINT_MASK;
+            return kStatus_USART_FramingError;
+        }
+        if (status & USART_STAT_PARITYERRINT_MASK)
+        {
+            base->STAT |= USART_STAT_PARITYERRINT_MASK;
+            return kStatus_USART_ParityError;
+        }
+        if (status & USART_STAT_RXNOISEINT_MASK)
+        {
+            base->STAT |= USART_STAT_RXNOISEINT_MASK;
+            return kStatus_USART_NoiseError;
+        }
+        /* check rxFIFO status */
+        if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+        {
+            base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+            base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+            return kStatus_USART_RxError;
+        }
+
+        *data = base->FIFORD;
+        data++;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData)
+{
+    int32_t instance = 0;
+
+    /* Check 'base' */
+    assert(!((NULL == base) || (NULL == handle)));
+    if ((NULL == base) || (NULL == handle))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* Set the TX/RX state. */
+    handle->rxState = kUSART_RxIdle;
+    handle->txState = kUSART_TxIdle;
+    /* Set the callback and user data. */
+    handle->callback    = callback;
+    handle->userData    = userData;
+    handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base);
+    handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle);
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(s_usartIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.
+ *
+ * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure. See  #usart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if (kUSART_TxBusy == handle->txState)
+    {
+        return kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txData        = xfer->data;
+        handle->txDataSize    = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState       = kUSART_TxBusy;
+        /* Enable transmiter interrupt. */
+        base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupts */
+    USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable);
+    /* Empty txFIFO */
+    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+    handle->txDataSize = 0;
+    handle->txState    = kUSART_TxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure, see #usart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes)
+{
+    uint32_t i;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t regPrimask = 0U;
+
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+    if (kUSART_RxBusy == handle->rxState)
+    {
+        return kStatus_USART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive       = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            regPrimask = DisableGlobalIRQ();
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+            if (bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+                bytesToReceive -= bytesToCopy;
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData        = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
+                handle->rxDataSizeAll = bytesToReceive;
+                handle->rxState       = kUSART_RxBusy;
+            }
+            /* Enable IRQ if previously enabled. */
+            EnableGlobalIRQ(regPrimask);
+            /* Call user callback since all data are received. */
+            if (0 == bytesToReceive)
+            {
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData        = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState       = kUSART_RxBusy;
+
+            /* Enable RX interrupt. */
+            base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
+        }
+        /* Return the how many bytes have read. */
+        if (receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (!handle->rxRingBuffer)
+    {
+        /* Disable interrupts */
+        USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable);
+        /* Empty rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState    = kUSART_RxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert((NULL != base) && (NULL != handle));
+
+    bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer);
+    bool sendEnabled    = handle->txDataSize;
+
+    /* If RX overrun. */
+    if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+    {
+        /* Clear rx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+        }
+    }
+    while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||
+           (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))
+    {
+        /* Receive data */
+        if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+            /* Receive to app bufffer if app buffer is present */
+            if (handle->rxDataSize)
+            {
+                *handle->rxData = base->FIFORD;
+                handle->rxDataSize--;
+                handle->rxData++;
+                receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer));
+                if (!handle->rxDataSize)
+                {
+                    if (!handle->rxRingBuffer)
+                    {
+                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+                    }
+                    handle->rxState = kUSART_RxIdle;
+                    if (handle->callback)
+                    {
+                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                    }
+                }
+            }
+            /* Otherwise receive to ring buffer if ring buffer is present */
+            else
+            {
+                if (handle->rxRingBuffer)
+                {
+                    /* If RX ring buffer is full, trigger callback to notify over run. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        if (handle->callback)
+                        {
+                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+                        }
+                    }
+                    /* If ring buffer is still full after callback function, the oldest data is overridden. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        /* Increase handle->rxRingBufferTail to make room for new data. */
+                        if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                        {
+                            handle->rxRingBufferTail = 0U;
+                        }
+                        else
+                        {
+                            handle->rxRingBufferTail++;
+                        }
+                    }
+                    /* Read data. */
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD;
+                    /* Increase handle->rxRingBufferHead. */
+                    if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferHead = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferHead++;
+                    }
+                }
+            }
+        }
+        /* Send data */
+        if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+            base->FIFOWR = *handle->txData;
+            handle->txDataSize--;
+            handle->txData++;
+            sendEnabled = handle->txDataSize != 0;
+            if (!sendEnabled)
+            {
+                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+                handle->txState    = kUSART_TxIdle;
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+
+    /* ring buffer is not used */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* restore if rx transfer ends and rxLevel is different from default value */
+        if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+        }
+        /* decrease level if rx transfer is bellow */
+        if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1)))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1));
+        }
+    }
+}

third_party/nxp/JN5189/drivers/fsl_usart.h

@@ -0,0 +1,718 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_USART_H_
+#define _FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.1.0. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Error codes for the USART driver. */
+enum _usart_status
+{
+    kStatus_USART_TxBusy              = MAKE_STATUS(kStatusGroup_LPC_USART, 0),  /*!< Transmitter is busy. */
+    kStatus_USART_RxBusy              = MAKE_STATUS(kStatusGroup_LPC_USART, 1),  /*!< Receiver is busy. */
+    kStatus_USART_TxIdle              = MAKE_STATUS(kStatusGroup_LPC_USART, 2),  /*!< USART transmitter is idle. */
+    kStatus_USART_RxIdle              = MAKE_STATUS(kStatusGroup_LPC_USART, 3),  /*!< USART receiver is idle. */
+    kStatus_USART_TxError             = MAKE_STATUS(kStatusGroup_LPC_USART, 7),  /*!< Error happens on txFIFO. */
+    kStatus_USART_RxError             = MAKE_STATUS(kStatusGroup_LPC_USART, 9),  /*!< Error happens on rxFIFO. */
+    kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8),  /*!< Error happens on rx ring buffer */
+    kStatus_USART_NoiseError          = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */
+    kStatus_USART_FramingError        = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */
+    kStatus_USART_ParityError         = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */
+    kStatus_USART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief USART synchronous mode. */
+typedef enum _usart_sync_mode
+{
+    kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode.       */
+    kUSART_SyncModeSlave    = 0x2U, /*!< Synchronous slave mode.  */
+    kUSART_SyncModeMaster   = 0x3U, /*!< Synchronous master mode. */
+} usart_sync_mode_t;
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode
+{
+    kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kUSART_ParityEven     = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kUSART_ParityOdd      = 0x3U, /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count
+{
+    kUSART_OneStopBit = 0U, /*!< One stop bit */
+    kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len
+{
+    kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+    kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief USART clock polarity configuration, used in sync mode.*/
+typedef enum _usart_clock_polarity
+{
+    kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */
+    kUSART_RxSampleOnRisingEdge  = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */
+} usart_clock_polarity_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark
+{
+    kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+    kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+    kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+    kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+    kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+    kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+    kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+    kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark
+{
+    kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+    kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+    kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+    kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+    kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+    kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+    kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+    kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+    kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+    kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+    kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+    kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+    kUSART_TxError            = (USART_FIFOSTAT_TXERR_MASK),      /*!< TEERR bit, sets if TX buffer is error */
+    kUSART_RxError            = (USART_FIFOSTAT_RXERR_MASK),      /*!< RXERR bit, sets if RX buffer is error */
+    kUSART_TxFifoEmptyFlag    = (USART_FIFOSTAT_TXEMPTY_MASK),    /*!< TXEMPTY bit, sets if TX buffer is empty */
+    kUSART_TxFifoNotFullFlag  = (USART_FIFOSTAT_TXNOTFULL_MASK),  /*!< TXNOTFULL bit, sets if TX buffer is not full */
+    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
+    kUSART_RxFifoFullFlag     = (USART_FIFOSTAT_RXFULL_MASK),     /*!< RXFULL bit, sets if RX buffer is full */
+};
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+    uint32_t baudRate_Bps;                /*!< USART baud rate  */
+    usart_parity_mode_t parityMode;       /*!< Parity mode, disabled (default), even, odd */
+    usart_stop_bit_count_t stopBitCount;  /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    usart_data_len_t bitCountPerChar;     /*!< Data length - 7 bit, 8 bit  */
+    bool loopback;                        /*!< Enable peripheral loopback */
+    bool enableRx;                        /*!< Enable RX */
+    bool enableTx;                        /*!< Enable TX */
+    bool enableContinuousSCLK;            /*!< USART continuous Clock generation enable in synchronous master mode. */
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+    usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */
+    usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    usart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                     /*!< USART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*! @brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+    return base->FIFOSTAT;
+}
+
+/*!
+ * @brief Clear USART status flags.
+ *
+ * This function clear supported USART status flags
+ * Flags that can be cleared or set are:
+ *      kUSART_TxError
+ *      kUSART_RxError
+ * For example:
+ * @code
+ *     USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask status flags to be cleared.
+ */
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
+{
+    /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
+    base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = mask & 0xF;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENCLR = mask & 0xF;
+}
+
+/*!
+ * @brief Returns enabled USART interrupts.
+ *
+ * This function returns the enabled USART interrupts.
+ *
+ * @param base USART peripheral base address.
+ */
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)
+{
+    return base->FIFOINTENSET;
+}
+
+/*!
+ * @brief Enable DMA for Tx
+ */
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+    }
+}
+
+/*!
+ * @brief Enable DMA for Rx
+ */
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+    }
+}
+
+/*!
+ * @brief Enable CTS.
+ * This function will determine whether CTS is used for flow control.
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable CTS or not, true for enable and false for disable.
+ */
+static inline void USART_EnableCTS(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= USART_CFG_CTSEN_MASK;
+    }
+    else
+    {
+        base->CFG &= ~USART_CFG_CTSEN_MASK;
+    }
+}
+
+/*!
+ * @brief Continuous Clock generation.
+ * By default, SCLK is only output while data is being transmitted in synchronous mode.
+ * Enable this funciton, SCLK will run continuously in synchronous mode, allowing
+ * characters to be received on Un_RxD independently from transmission on Un_TXD).
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable Continuous Clock generation mode or not, true for enable and false for disable.
+ */
+static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= USART_CTL_CC_MASK;
+    }
+    else
+    {
+        base->CTL &= ~USART_CTL_CC_MASK;
+    }
+}
+
+/*!
+ * @brief Enable Continuous Clock generation bit auto clear.
+ * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete
+ * character has been received. This bit is cleared at the same time.
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable auto clear or not, true for enable and false for disable.
+ */
+static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= USART_CTL_CLRCCONRX_MASK;
+    }
+    else
+    {
+        base->CTL &= ~USART_CTL_CLRCCONRX_MASK;
+    }
+}
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+    base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+    return base->FIFORD;
+}
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See  #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+                                   usart_handle_t *handle,
+                                   uint8_t *ringBuffer,
+                                   size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle USART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_H_ */

third_party/nxp/JN5189/drivers/fsl_wtimer.c

@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************************/
+/***        Include files                                                 ***/
+/****************************************************************************/
+
+#include "fsl_wtimer.h"
+#include "fsl_clock.h"
+#include "fsl_device_registers.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.wtimer"
+#endif
+
+/****************************************************************************/
+/***        Macro Definitions                                             ***/
+/****************************************************************************/
+
+//#define WTIMER_TRACE
+
+#ifndef WTIMER_TRACE
+#define PRINTF(...)
+#else
+#include "fsl_debug_console.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.wtimer"
+#endif
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+typedef struct
+{
+    uint32_t wkt_stat_timeout_mask;
+    uint32_t wkt_stat_running_mask;
+    uint32_t wkt_ctrl_clk_ena_mask;
+    uint32_t wkt_ctrl_ena_mask;
+    uint32_t wkt_intenclr_timeout_mask;
+    volatile uint32_t *wkt_load_lsb_reg;
+    volatile uint32_t *wkt_load_msb_reg;
+    const volatile uint32_t *wkt_val_lsb_reg;
+    const volatile uint32_t *wkt_val_msb_reg;
+    uint8_t wkt_irq_id;
+} timer_param_t;
+
+static const timer_param_t timer_param[2] = {
+    {
+        .wkt_stat_timeout_mask     = SYSCON_WKT_STAT_WKT0_TIMEOUT_MASK,
+        .wkt_stat_running_mask     = SYSCON_WKT_STAT_WKT0_RUNNING_MASK,
+        .wkt_ctrl_clk_ena_mask     = SYSCON_WKT_CTRL_WKT0_CLK_ENA_MASK,
+        .wkt_ctrl_ena_mask         = SYSCON_WKT_CTRL_WKT0_ENA_MASK,
+        .wkt_intenclr_timeout_mask = SYSCON_WKT_INTENSET_WKT0_TIMEOUT_MASK,
+        .wkt_load_lsb_reg          = &SYSCON->WKT_LOAD_WKT0_LSB,
+        .wkt_load_msb_reg          = &SYSCON->WKT_LOAD_WKT0_MSB,
+        .wkt_val_lsb_reg           = &SYSCON->WKT_VAL_WKT0_LSB,
+        .wkt_val_msb_reg           = NULL,
+        .wkt_irq_id                = WAKE_UP_TIMER0_IRQn,
+    },
+    {
+        .wkt_stat_timeout_mask     = SYSCON_WKT_STAT_WKT1_TIMEOUT_MASK,
+        .wkt_stat_running_mask     = SYSCON_WKT_STAT_WKT1_RUNNING_MASK,
+        .wkt_ctrl_clk_ena_mask     = SYSCON_WKT_CTRL_WKT1_CLK_ENA_MASK,
+        .wkt_ctrl_ena_mask         = SYSCON_WKT_CTRL_WKT1_ENA_MASK,
+        .wkt_intenclr_timeout_mask = SYSCON_WKT_INTENSET_WKT1_TIMEOUT_MASK,
+        .wkt_load_lsb_reg          = &SYSCON->WKT_LOAD_WKT1,
+        .wkt_load_msb_reg          = NULL,
+        .wkt_val_lsb_reg           = &SYSCON->WKT_VAL_WKT1,
+        .wkt_val_msb_reg           = NULL,
+        .wkt_irq_id                = WAKE_UP_TIMER1_IRQn,
+    },
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Enable the clocks to the peripheral (functional clock and AHB clock)
+ *
+ * note This function does not reset the wake timer peripheral. Wake timer reset is done in PWRM_vColdStart() from the
+ * PWRM framework module if integrated
+ * If PWRM framework module is integrated, WTIMER_Init() is called in PWRM_vInit() for power modes with Oscillator ON.
+ *
+ */
+void WTIMER_Init(void)
+{
+    /* set clock and divider */
+    SYSCON->AHBCLKCTRLS[0] |= SYSCON_AHBCLKCTRLSET0_WAKE_UP_TIMERS_CLK_SET_MASK;
+    SYSCON->WKTCLKSEL = SYSCON_WKTCLKSEL_SEL(0); // & ~SYSCON_WKTCLKSEL_SEL_MASK ;
+}
+
+/*!
+ * brief Disable the clocks to the peripheral (functional clock and AHB clock)
+ *
+ * note This function does not reset the wake timer peripheral.
+ *
+ */
+void WTIMER_DeInit(void)
+{
+    /* set clock and divider */
+    SYSCON->AHBCLKCTRLS[0] &= ~SYSCON_AHBCLKCTRLSET0_WAKE_UP_TIMERS_CLK_SET_MASK;
+    SYSCON->WKTCLKSEL = SYSCON_WKTCLKSEL_SEL(2); // No Clock ;
+}
+
+/*!
+ * brief Gets the Timer status flags.
+ *
+ * param timer_id   Wtimer Id
+ *
+ * return The status flags.
+ */
+WTIMER_status_t WTIMER_GetStatusFlags(WTIMER_timer_id_t timer_id)
+{
+    const timer_param_t *timer_param_l = &timer_param[timer_id];
+    WTIMER_status_t status             = WTIMER_STATUS_NOT_RUNNING;
+    uint32_t stat                      = SYSCON->WKT_STAT;
+
+    if (stat & timer_param_l->wkt_stat_timeout_mask)
+    {
+        status = WTIMER_STATUS_EXPIRED;
+        PRINTF("WakeTimerFiredStatus[%d] expired\n", timer_id);
+    }
+    else if (stat & timer_param_l->wkt_stat_running_mask)
+    {
+        status = WTIMER_STATUS_RUNNING;
+        PRINTF("WakeTimerFiredStatus[%d] running\n", timer_id);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enable the selected Timer interrupts.
+ * The application shall implement the Wake timer ISR
+ *
+ * param timer_id   Wtimer Id
+ */
+void WTIMER_EnableInterrupts(WTIMER_timer_id_t timer_id)
+{
+    const timer_param_t *timer_param_l = &timer_param[timer_id];
+
+    EnableIRQ((IRQn_Type)timer_param_l->wkt_irq_id);
+    SYSCON->WKT_INTENSET = timer_param_l->wkt_intenclr_timeout_mask;
+}
+
+/*!
+ * brief Starts the Timer counter.
+ * The function performs:
+ * -stop the timer if running, clear the status and interrupt flag if set (WTIMER_ClearStatusFlags())
+ * -set the counter value
+ * -start the timer
+ *
+ * param timer_id   Wtimer Id
+ * param count      number of 32KHz clock periods before expiration
+ */
+void WTIMER_StartTimer(WTIMER_timer_id_t timer_id, uint32_t count)
+{
+    const timer_param_t *timer_param_l = &timer_param[timer_id];
+
+    PRINTF("-->> vAHI_WakeTimerStart[%d] : STAT=%x count=%d WKT_INTSTAT=%x count=%d\n", timer_id, SYSCON->WKT_STAT,
+           count, SYSCON->WKT_INTSTAT, count);
+
+    /* enable the clock */
+    SYSCON->WKT_CTRL |= timer_param_l->wkt_ctrl_clk_ena_mask;
+
+    /* clear timeout flag if set */
+    SYSCON->WKT_STAT = timer_param_l->wkt_stat_timeout_mask;
+
+    /* stop timer if running */
+    SYSCON->WKT_CTRL &= ~(timer_param_l->wkt_ctrl_ena_mask);
+
+    /* make sure the timer is really stopped */
+    while ((SYSCON->WKT_STAT & (timer_param_l->wkt_stat_running_mask)) == timer_param_l->wkt_stat_running_mask)
+    {
+        __asm volatile("nop");
+    }
+
+    *(timer_param_l->wkt_load_lsb_reg) = count;
+    if (timer_id == WTIMER_TIMER0_ID)
+    {
+        *(timer_param_l->wkt_load_msb_reg) = 0;
+    }
+
+    /* enable the timer */
+    SYSCON->WKT_CTRL |= timer_param_l->wkt_ctrl_ena_mask;
+
+    while ((SYSCON->WKT_STAT & (timer_param_l->wkt_stat_running_mask)) == 0)
+    {
+        __asm volatile("nop");
+    }
+
+    PRINTF("<<-- vAHI_WakeTimerStart[%d] : STAT=%x WKT_INTSTAT=%x\n", timer_id, SYSCON->WKT_STAT, SYSCON->WKT_INTSTAT);
+}
+
+/*!
+ * brief Read the LSB counter of the wake timer
+ * API checks the next counter update (next 32KHz clock edge) so the value is uptodate
+ * Important note : The counter shall be running otherwise, the API gets locked and never return
+ *
+ * param timer_id   Wtimer Id
+ * return  32KHz clock frequency (number of 32KHz clock in one sec) - expect to have 32768
+ */
+uint32_t WTIMER_ReadTimerSafe(WTIMER_timer_id_t timer_id)
+{
+    const timer_param_t *timer_param_l    = &timer_param[timer_id];
+    volatile uint32_t u32CurrentCount_ini = *timer_param_l->wkt_val_lsb_reg;
+    volatile uint32_t u32CurrentCount     = *timer_param_l->wkt_val_lsb_reg;
+
+    while (u32CurrentCount == u32CurrentCount_ini)
+        u32CurrentCount = *timer_param_l->wkt_val_lsb_reg;
+
+    return u32CurrentCount;
+}
+
+/*!
+ * brief Read the LSB counter of the wake timer
+ * This API is unsafe. If the counter has just been started, the counter value may not be
+ * up to date until the next 32KHz clock edge.
+ * Use WTIMER_ReadTimerSafe() instead
+ *
+ * param timer_id   Wtimer Id
+ * return  counter value - number of ticks before expiration if running
+ */
+uint32_t WTIMER_ReadTimer(WTIMER_timer_id_t timer_id)
+{
+    const timer_param_t *timer_param_l = &timer_param[timer_id];
+    volatile uint32_t u32CurrentCount  = *timer_param_l->wkt_val_lsb_reg;
+
+    return u32CurrentCount;
+}
+
+/*!
+ * brief Clears the Timer status flags if expired and clear the pendng interrupt if active
+ * it needs to be called in ISR
+ *
+ * param timer_id   Wtimer Id
+ */
+void WTIMER_ClearStatusFlags(WTIMER_timer_id_t timer_id)
+{
+    const timer_param_t *timer_param_l = &timer_param[timer_id];
+
+    /* clear expiration flag */
+    SYSCON->WKT_STAT = timer_param_l->wkt_stat_timeout_mask;
+
+    /* clear interrupt if pending */
+    NVIC_ClearPendingIRQ((IRQn_Type)timer_param_l->wkt_irq_id);
+}
+
+/*!
+ * brief Stops the Timer counter.
+ *
+ * param timer_id   Wtimer Id
+ */
+void WTIMER_StopTimer(WTIMER_timer_id_t timer_id)
+{
+    const timer_param_t *timer_param_l = &timer_param[timer_id];
+
+    /* Stop timer */
+    SYSCON->WKT_CTRL &= ~(timer_param_l->wkt_ctrl_ena_mask);
+
+    /* make sure the timer is really stopped */
+    while ((SYSCON->WKT_STAT & (timer_param_l->wkt_stat_running_mask)) == timer_param_l->wkt_stat_running_mask)
+    {
+        __asm volatile("nop");
+    }
+
+    WTIMER_ClearStatusFlags(timer_id);
+}

third_party/nxp/JN5189/drivers/fsl_wtimer.h

@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_WTIMER_H_
+#define _FSL_WTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup wtimer
+ * @{
+ */
+
+/*! @file */
+
+/**
+ * Wake timers provide wakeup capabilities in sleep modes where 32KHz clock is kept active.
+ * Wake timer 0 is a 48bit based counter while wake timer 1 is 32bit based counter.
+ * A special API functions WTIMER_StartTimerLarge(0 and WTIMER_StartTimerLarge() are provided to access the 48bit
+ * counter. The Wake timer 1 is to be used bu the PWRM framework. It shall not be used by the Application directly. API
+ * provides the capability to enable and disable interrupts. The application shall implement the Wake timer ISR on its
+ * side. The wake timer ISR prototypes are : void WAKE_UP_TIMER0_IRQHandler(void); and void
+ * WAKE_UP_TIMER1_IRQHandler(void); The Application shall correctly the 32KHz source amoung the FRO32 or Crystal 32KHz
+ * using CLOCK_EnableClock() API in fsl_clock.h The APi provides the capability to calibrate the 32KHz clock versus a
+ * high reference clock (32MHz crystal).
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_WTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+typedef enum
+{
+    WTIMER_TIMER0_ID = 0,
+    WTIMER_TIMER1_ID = 1,
+} WTIMER_timer_id_t;
+
+typedef enum
+{
+    WTIMER_STATUS_NOT_RUNNING = 0,
+    WTIMER_STATUS_RUNNING     = 1,
+    WTIMER_STATUS_EXPIRED     = 2,
+} WTIMER_status_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Enable the clocks to the peripheral (functional clock and AHB clock)
+ *
+ * @note This function does not reset the wake timer peripheral. Wake timer reset is done in PWRM_vColdStart() from the
+ * PWRM framework module if integrated If PWRM framework module is integrated, WTIMER_Init() is called in PWRM_vInit()
+ * for power modes with Oscillator ON.
+ *
+ */
+void WTIMER_Init(void);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Disable the clocks to the peripheral (functional clock and AHB clock)
+ *
+ * @note This function does not reset the wake timer peripheral.
+ *
+ */
+void WTIMER_DeInit(void);
+
+/*!
+ * @brief Enable the selected Timer interrupts.
+ * The application shall implement the Wake timer ISR
+ *
+ * @param timer_id   Wtimer Id
+ */
+void WTIMER_EnableInterrupts(WTIMER_timer_id_t timer_id);
+
+#ifdef NOT_IMPLEMENTED_YET
+/*!
+ * @brief Disable the selected Timer interrupts.
+ * Interrupts are disabled by default. The API shall be called if the interrupt was enabled before.
+ *
+ * @param timer_id   Wtimer Id
+ */
+void WTIMER_DisableInterrupts(WTIMER_timer_id_t timer_id);
+#endif
+
+/*!
+ * @brief Gets the Timer status flags.
+ *
+ * @param timer_id   Wtimer Id
+ *
+ * @return The status flags.
+ */
+WTIMER_status_t WTIMER_GetStatusFlags(WTIMER_timer_id_t timer_id);
+
+/*!
+ * @brief Clears the Timer status flags if expired and clear the pendng interrupt if active
+ * it needs to be called in ISR
+ *
+ * @param timer_id   Wtimer Id
+ */
+void WTIMER_ClearStatusFlags(WTIMER_timer_id_t timer_id);
+
+/*!
+ * @brief Starts the Timer counter.
+ * The function performs:
+ * -stop the timer if running, clear the status and interrupt flag if set (WTIMER_ClearStatusFlags())
+ * -set the counter value
+ * -start the timer
+ *
+ * @param timer_id   Wtimer Id
+ * @param count      number of 32KHz clock periods before expiration
+ */
+void WTIMER_StartTimer(WTIMER_timer_id_t timer_id, uint32_t count);
+
+/*!
+ * @brief Stops the Timer counter.
+ *
+ * @param timer_id   Wtimer Id
+ */
+void WTIMER_StopTimer(WTIMER_timer_id_t timer_id);
+
+/*!
+ * @brief Calibrate the 32KHz clock to be used by the wake timer versus the 32MHz crystal clock source
+ * The Applicaton shall switches OFF the 32MHz clock if no longer used by the chip using CLOCK_DisableClock() in
+ * fsl_clock.h
+ *
+ * @return  32KHz clock frequency (number of 32KHz clock in one sec) - expect to have 32768
+ */
+uint32_t WTIMER_CalibrateTimer(void);
+
+/*!
+ * @brief Read the LSB counter of the wake timer
+ * This API is unsafe. If the counter has just been started, the counter value may not be
+ * up to date until the next 32KHz clock edge.
+ * Use WTIMER_ReadTimerSafe() instead
+ *
+ * @param timer_id   Wtimer Id
+ * @return  counter value - number of ticks before expiration if running
+ */
+uint32_t WTIMER_ReadTimer(WTIMER_timer_id_t timer_id);
+
+/*!
+ * @brief Read the LSB counter of the wake timer
+ * API checks the next counter update (next 32KHz clock edge) so the value is uptodate
+ * Important note : The counter shall be running otherwise, the API gets locked and never return
+ *
+ * @param timer_id   Wtimer Id
+ * @return  32KHz clock frequency (number of 32KHz clock in one sec) - expect to have 32768
+ */
+uint32_t WTIMER_ReadTimerSafe(WTIMER_timer_id_t timer_id);
+
+#ifdef NOT_IMPLEMENTED_YET
+/*!
+ * @brief Starts the Timer counter.
+ *
+ * @param timer_id   Wtimer Id
+ * @param count      number of 32KHz clock periods before expiration
+ */
+void WTIMER_StartTimerLarge(WTIMER_timer_id_t timer_id, uint64_t count);
+
+/*!
+ * @brief Read the LSB + MSB counter of the 48bit wake timer, Read the LSB counter for 32bit wale timer
+ *
+ *
+ * @param timer_id   Wtimer Id
+ * @return wake timer counter
+ */
+uint64_t WTIMER_ReadTimerLarge(WTIMER_timer_id_t timer_id);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_WTIMER_H_ */

third_party/nxp/JN5189/drivers/sha/fsl_sha.c

@@ -0,0 +1,538 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_sha.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.sha"
+#endif
+
+/*!< SHA-1 and SHA-256 block size  */
+#define SHA_BLOCK_SIZE 64
+
+/*!< Use standard C library memcpy  */
+#define sha_memcpy memcpy
+
+/*! Internal states of the HASH creation process */
+typedef enum _sha_algo_state
+{
+    kSHA_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */
+    kSHA_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has been
+                        written. */
+} sha_algo_state_t;
+
+/*! 64-byte block represented as byte array of 16 32-bit words */
+typedef union _sha_hash_block
+{
+    uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */
+    uint8_t b[SHA_BLOCK_SIZE];      /*!< byte array */
+} sha_block_t;
+
+/*! internal sha context structure */
+typedef struct _sha_ctx_internal
+{
+    sha_block_t blk;        /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */
+    size_t blksz;           /*!< number of valid bytes in memory buffer */
+    sha_algo_t algo;        /*!< selected algorithm from the set of supported algorithms */
+    sha_algo_state_t state; /*!< finite machine state of the hash software process */
+    size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */
+} sha_ctx_internal_t;
+
+/*!< SHA-1 and SHA-256 digest length in bytes  */
+enum _sha_digest_len
+{
+    kSHA_OutLenSha1   = 20u,
+    kSHA_OutLenSha256 = 32u,
+};
+
+/*!< macro for checking build time condition. It is used to assure the sha_ctx_internal_t can fit into sha_ctx_t */
+#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief LDM to SHA engine INDATA and ALIAS registers.
+ *
+ * This function writes 16 words starting from the src address (must be word aligned)
+ * to the dst address. Dst address does not increment (destination is peripheral module register INDATA).
+ * Src address increments to load 16 consecutive words.
+ *
+ * @param dst peripheral register address (word aligned)
+ * @param src address of the input 512-bit block (16 words) (word aligned)
+ *
+ */
+#if defined(SHA_ALIAS_DATA_MASK)
+__STATIC_INLINE void sha_ldm_stm_16_words(SHA_Type *base, const uint32_t *src)
+{
+    base->INDATA = src[0];
+    for (int i = 0; i < 7; i++)
+    {
+        base->ALIAS[i] = src[i + 1];
+    }
+    src += 8u;
+    base->INDATA = src[0];
+    for (int i = 0; i < 7; i++)
+    {
+        base->ALIAS[i] = src[i + 1];
+    }
+}
+#else
+__STATIC_INLINE void sha_ldm_stm_16_words(volatile uint32_t *dst, const uint32_t *src)
+{
+    for (int i = 0; i < 8; i++)
+    {
+        dst[i] = src[i];
+    }
+    src += 8u;
+    for (int i = 0; i < 8; i++)
+    {
+        dst[i] = src[i];
+    }
+}
+#endif
+/*!
+ * @brief Swap bytes withing 32-bit word.
+ *
+ * This function changes endianess of a 32-bit word.
+ *
+ * @param in 32-bit unsigned integer
+ * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa).
+ */
+static uint32_t swap_bytes(uint32_t in)
+{
+    return (((in & 0x000000ffu) << 24) | ((in & 0x0000ff00u) << 8) | ((in & 0x00ff0000u) >> 8) |
+            ((in & 0xff000000u) >> 24));
+}
+
+/*!
+ * @brief Check validity of algoritm.
+ *
+ * This function checks the validity of input argument.
+ *
+ * @param algo Tested algorithm value.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t sha_check_input_alg(sha_algo_t algo)
+{
+    if ((algo != kSHA_Sha1) && (algo != kSHA_Sha256))
+    {
+        return kStatus_InvalidArgument;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Check validity of input arguments.
+ *
+ * This function checks the validity of input arguments.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context.
+ * @param algo Tested algorithm value.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t sha_check_input_args(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo)
+{
+    /* Check validity of input algorithm */
+    if (kStatus_Success != sha_check_input_alg(algo))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if ((NULL == ctx) || (NULL == base))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Check validity of internal software context.
+ *
+ * This function checks if the internal context structure looks correct.
+ *
+ * @param ctxInternal Internal context.
+ * @param message Input message address.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t sha_check_context(sha_ctx_internal_t *ctxInternal, const uint8_t *message)
+{
+    if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != sha_check_input_alg(ctxInternal->algo)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Initialize the SHA engine for new hash.
+ *
+ * This function sets NEW and MODE fields in SHA Control register to start new hash.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ */
+static void sha_engine_init(SHA_Type *base, sha_ctx_internal_t *ctxInternal)
+{
+    uint32_t shaCtrl;
+
+    if (kSHA_Sha1 == ctxInternal->algo)
+    {
+        shaCtrl = SHA_CTRL_MODE(1) | SHA_CTRL_NEW(1);
+    }
+    else
+    {
+        shaCtrl = SHA_CTRL_MODE(2) | SHA_CTRL_NEW(1);
+    }
+    base->CTRL = shaCtrl;
+}
+
+/*!
+ * @brief Load 512-bit block (16 words) into SHA engine.
+ *
+ * This function aligns the input block and moves it into SHA engine INDATA.
+ * CPU polls the WAITING bit and then moves data by using LDM and STM instructions.
+ *
+ * @param base SHA peripheral base address.
+ * @param blk 512-bit block
+ */
+static void sha_one_block(SHA_Type *base, const uint8_t *blk)
+{
+    uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)];
+    const uint32_t *actBlk;
+
+    /* make sure the 512-bit block is word aligned */
+    if ((uintptr_t)blk & 0x3u)
+    {
+        sha_memcpy(temp, blk, SHA_BLOCK_SIZE);
+        actBlk = (const uint32_t *)(uintptr_t)temp;
+    }
+    else
+    {
+        actBlk = (const uint32_t *)(uintptr_t)blk;
+    }
+
+    /* poll waiting. */
+    while (0 == (base->STATUS & SHA_STATUS_WAITING_MASK))
+    {
+    }
+/* feed INDATA (and ALIASes). use STM instruction. */
+#if defined(SHA_ALIAS_DATA_MASK)
+    sha_ldm_stm_16_words(base, actBlk);
+#else
+    sha_ldm_stm_16_words(&base->INDATA[0], actBlk);
+#endif
+}
+
+/*!
+ * @brief Adds message to current hash.
+ *
+ * This function merges the message to fill the internal buffer, empties the internal buffer if
+ * it becomes full, then process all remaining message data.
+ *
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ * @param message Input message.
+ * @param messageSize Size of input message in bytes.
+ * @return kStatus_Success.
+ */
+static status_t sha_process_message_data(SHA_Type *base,
+                                         sha_ctx_internal_t *ctxInternal,
+                                         const uint8_t *message,
+                                         size_t messageSize)
+{
+    /* first fill the internal buffer to full block */
+    size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz;
+    sha_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy);
+    message += toCopy;
+    messageSize -= toCopy;
+
+    /* process full internal block */
+    sha_one_block(base, &ctxInternal->blk.b[0]);
+
+    /* process all full blocks in message[] */
+    while (messageSize >= SHA_BLOCK_SIZE)
+    {
+        sha_one_block(base, message);
+        message += SHA_BLOCK_SIZE;
+        messageSize -= SHA_BLOCK_SIZE;
+    }
+
+    /* copy last incomplete message bytes into internal block */
+    sha_memcpy(&ctxInternal->blk.b[0], message, messageSize);
+    ctxInternal->blksz = messageSize;
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Finalize the running hash to make digest.
+ *
+ * This function empties the internal buffer, adds padding bits, and generates final digest.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ * @return kStatus_Success.
+ */
+static status_t sha_finalize(SHA_Type *base, sha_ctx_internal_t *ctxInternal)
+{
+    sha_block_t lastBlock;
+
+    memset(&lastBlock, 0, sizeof(sha_block_t));
+
+    /* this is last call, so need to flush buffered message bytes along with padding */
+    if (ctxInternal->blksz <= 55u)
+    {
+        /* last data is 440 bits or less. */
+        sha_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz);
+        lastBlock.b[ctxInternal->blksz]     = (uint8_t)0x80U;
+        lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize);
+        sha_one_block(base, &lastBlock.b[0]);
+    }
+    else
+    {
+        if (ctxInternal->blksz < SHA_BLOCK_SIZE)
+        {
+            ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U;
+            for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++)
+            {
+                ctxInternal->blk.b[i] = 0;
+            }
+        }
+        else
+        {
+            lastBlock.b[0] = (uint8_t)0x80U;
+        }
+
+        sha_one_block(base, &ctxInternal->blk.b[0]);
+        lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize);
+        sha_one_block(base, &lastBlock.b[0]);
+    }
+    /* poll wait for final digest */
+    while (0 == (base->STATUS & SHA_STATUS_DIGEST_MASK))
+    {
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Read DIGEST registers.
+ *
+ * This function copies DIGEST to output buffer.
+ *
+ * @param base SHA peripheral base address.
+ * @param[out] output Output buffer.
+ * @param Number of bytes to copy.
+ * @return kStatus_Success.
+ */
+static void sha_get_digest(SHA_Type *base, uint8_t *output, size_t outputSize)
+{
+    uint32_t digest[8];
+
+    for (int i = 0; i < 8; i++)
+    {
+        digest[i] = swap_bytes(base->DIGEST[i]);
+    }
+
+    if (outputSize > sizeof(digest))
+    {
+        outputSize = sizeof(digest);
+    }
+    sha_memcpy(output, digest, outputSize);
+}
+
+/*!
+ * brief Initialize HASH context
+ *
+ * This function initializes new hash context.
+ *
+ * param base SHA peripheral base address
+ * param[out] ctx Output hash context
+ * param algo Underlaying algorithm to use for hash computation. Either SHA-1 or SHA-256.
+ * return Status of initialization
+ */
+status_t SHA_Init(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo)
+{
+    status_t status;
+
+    sha_ctx_internal_t *ctxInternal;
+    /* compile time check for the correct structure size */
+    BUILD_ASSERT(sizeof(sha_ctx_t) >= sizeof(sha_ctx_internal_t), sha_ctx_t_size);
+    uint32_t i;
+
+    status = sha_check_input_args(base, ctx, algo);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* set algorithm in context struct for later use */
+    ctxInternal        = (sha_ctx_internal_t *)ctx;
+    ctxInternal->algo  = algo;
+    ctxInternal->blksz = 0u;
+    for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++)
+    {
+        ctxInternal->blk.w[0] = 0u;
+    }
+    ctxInternal->state           = kSHA_HashInit;
+    ctxInternal->fullMessageSize = 0;
+    return status;
+}
+
+/*!
+ * brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed.
+ *
+ * param base SHA peripheral base address
+ * param[in,out] ctx HASH context
+ * param message Input message
+ * param messageSize Size of input message in bytes
+ * return Status of the hash update operation
+ */
+status_t SHA_Update(SHA_Type *base, sha_ctx_t *ctx, const uint8_t *message, size_t messageSize)
+{
+    bool isUpdateState;
+    status_t status;
+    sha_ctx_internal_t *ctxInternal;
+    size_t blockSize;
+
+    if (messageSize == 0)
+    {
+        return kStatus_Success;
+    }
+
+    ctxInternal = (sha_ctx_internal_t *)ctx;
+    status      = sha_check_context(ctxInternal, message);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    ctxInternal->fullMessageSize += messageSize;
+    blockSize = SHA_BLOCK_SIZE;
+    /* if we are still less than 64 bytes, keep only in context */
+    if ((ctxInternal->blksz + messageSize) <= blockSize)
+    {
+        sha_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, message, messageSize);
+        ctxInternal->blksz += messageSize;
+        return status;
+    }
+    else
+    {
+        isUpdateState = ctxInternal->state == kSHA_HashUpdate;
+        if (!isUpdateState)
+        {
+            /* start NEW hash */
+            sha_engine_init(base, ctxInternal);
+            ctxInternal->state = kSHA_HashUpdate;
+        }
+    }
+
+    /* process message data */
+    status = sha_process_message_data(base, ctxInternal, message, messageSize);
+    return status;
+}
+
+/*!
+ * brief Finalize hashing
+ *
+ * Outputs the final hash and erases the context. SHA-1 or SHA-256 padding bits are automatically added by this
+ * function.
+ *
+ * param base SHA peripheral base address
+ * param[in,out] ctx HASH context
+ * param[out] output Output hash data
+ * param[in,out] outputSize On input, determines the size of bytes of the output array. On output, tells how many bytes
+ * have been written to output.
+ * return Status of the hash finish operation
+ */
+status_t SHA_Finish(SHA_Type *base, sha_ctx_t *ctx, uint8_t *output, size_t *outputSize)
+{
+    size_t algOutSize = 0;
+    status_t status;
+    sha_ctx_internal_t *ctxInternal;
+    uint32_t *ctxW;
+    uint32_t i;
+
+    ctxInternal = (sha_ctx_internal_t *)ctx;
+    status      = sha_check_context(ctxInternal, output);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    if (ctxInternal->state == kSHA_HashInit)
+    {
+        sha_engine_init(base, ctxInternal);
+    }
+
+    size_t outSize = 0u;
+
+    /* compute algorithm output length */
+    switch (ctxInternal->algo)
+    {
+        case kSHA_Sha1:
+            outSize = kSHA_OutLenSha1;
+            break;
+        case kSHA_Sha256:
+            outSize = kSHA_OutLenSha256;
+            break;
+        default:
+            break;
+    }
+    algOutSize = outSize;
+
+    /* flush message last incomplete block, if there is any, and add padding bits */
+    status = sha_finalize(base, ctxInternal);
+
+    if (outputSize)
+    {
+        if (algOutSize < *outputSize)
+        {
+            *outputSize = algOutSize;
+        }
+        else
+        {
+            algOutSize = *outputSize;
+        }
+    }
+
+    sha_get_digest(base, &output[0], algOutSize);
+
+    ctxW = (uint32_t *)ctx;
+    for (i = 0; i < SHA_CTX_SIZE; i++)
+    {
+        ctxW[i] = 0u;
+    }
+    return status;
+}
+
+void SHA_ClkInit(SHA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* ungate clock */
+    CLOCK_EnableClock(kCLOCK_Sha0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void SHA_ClkDeinit(SHA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* gate clock */
+    CLOCK_DisableClock(kCLOCK_Sha0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

third_party/nxp/JN5189/drivers/sha/fsl_sha.h

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_SHA_H_
+#define _FSL_SHA_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup sha
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines LPC SHA driver version 2.1.0. */
+#define FSL_SHA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*! Supported cryptographic block cipher functions for HASH creation */
+typedef enum _sha_algo_t
+{
+    kSHA_Sha1,   /*!< SHA_1 */
+    kSHA_Sha256, /*!< SHA_256  */
+} sha_algo_t;
+
+/*! @brief SHA Context size. */
+#define SHA_CTX_SIZE 20
+
+/*! @brief Storage type used to save hash context. */
+typedef struct _sha_ctx_t
+{
+    uint32_t x[SHA_CTX_SIZE];
+} sha_ctx_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name SHA Functional Operation
+ * @{
+ */
+
+/*!
+ * @addtogroup sha_algorithm_level_api
+ * @{
+ */
+/*!
+ * @brief Initialize HASH context
+ *
+ * This function initializes new hash context.
+ *
+ * @param base SHA peripheral base address
+ * @param[out] ctx Output hash context
+ * @param algo Underlaying algorithm to use for hash computation. Either SHA-1 or SHA-256.
+ * @return Status of initialization
+ */
+status_t SHA_Init(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo);
+
+/*!
+ * @brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed.
+ *
+ * @param base SHA peripheral base address
+ * @param[in,out] ctx HASH context
+ * @param message Input message
+ * @param messageSize Size of input message in bytes
+ * @return Status of the hash update operation
+ */
+status_t SHA_Update(SHA_Type *base, sha_ctx_t *ctx, const uint8_t *message, size_t messageSize);
+
+/*!
+ * @brief Finalize hashing
+ *
+ * Outputs the final hash and erases the context. SHA-1 or SHA-256 padding bits are automatically added by this
+ * function.
+ *
+ * @param base SHA peripheral base address
+ * @param[in,out] ctx HASH context
+ * @param[out] output Output hash data
+ * @param[in,out] outputSize On input, determines the size of bytes of the output array. On output, tells how many bytes
+ * have been written to output.
+ * @return Status of the hash finish operation
+ */
+status_t SHA_Finish(SHA_Type *base, sha_ctx_t *ctx, uint8_t *output, size_t *outputSize);
+/*!
+ * @brief Start SHA clock
+ *
+ * Start SHA clock
+ *
+ * @param base SHA peripheral base address
+ *
+ */
+void SHA_ClkInit(SHA_Type *base);
+
+/*!
+ * @brief Stop SHA clock
+ *
+ * Stop SHA clock
+ *
+ * @param base SHA peripheral base address
+ *
+ */
+void SHA_ClkDeinit(SHA_Type *base);
+
+/*!
+ *@}
+ */ /* sha_algorithm_level_api */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+/*! @}*/ /* end of group sha */
+
+#endif /* _FSL_SHA_H_ */

third_party/nxp/JN5189/fsl_device_registers.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_JN518X) || defined(CPU_JN5189HN) || defined(CPU_JN5189THN))
+
+#define JN518X_SERIES
+
+#define JN5189_SERIES
+
+/* CMSIS-style register definitions */
+#include "JN5189.h"
+/* CPU specific feature definitions */
+#include "JN5189_features.h"
+
+#else
+#error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

third_party/nxp/JN5189/rom_apis/flash_header.h

@@ -0,0 +1,94 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FLASH_HEADER_H_
+#define FLASH_HEADER_H_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/***        Include Files                                                 ***/
+/****************************************************************************/
+
+#include <stdint.h>
+
+/*!
+ * @addtogroup jn_flash
+ * @{
+ */
+
+/*! @file */
+
+/****************************************************************************/
+/***        Macro Definitions                                             ***/
+/****************************************************************************/
+
+#define NUMBER_CCSUM_VECTORS (7)
+
+#define IMAGE_SIGNATURE (0x98447902)
+#define IMAGE_HEADER_SIGNATURE_V3_ZB (IMAGE_SIGNATURE + 1)
+#define IMAGE_HEADER_SIGNATURE_V3_BLE (IMAGE_SIGNATURE + 2)
+#define BOOT_BLOCK_HDR_MARKER 0xbb0110bb
+
+/****************************************************************************/
+/***        Type Definitions                                              ***/
+/****************************************************************************/
+
+/*!
+ * @brief Image header.
+ *
+ * Be very cautious when modifying the IMG_HEADER_T and the BOOT_BLOCK_T structures (alignment) as
+ * these structures are used in the image_tool.py (which does not take care of alignment).
+ */
+typedef struct
+{
+    uint32_t vectors[NUMBER_CCSUM_VECTORS]; /*!< critical vectors protected by csum */
+    uint32_t vectorCsum;                    /*!< csum of vectors 0-7 */
+    uint32_t imageSignature;                /*!< image signature */
+    uint32_t bootBlockOffset;               /*!< offset of boot block structure */
+    uint32_t header_crc;                    /*!< the CRC of header */
+} IMG_HEADER_T;
+
+/*!
+ * @brief Boot block.
+ *
+ * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
+ * are the different channels that share the same channel number.
+ */
+typedef struct
+{
+    uint32_t header_marker;        /*!< Image header marker should always be set to 0xbb0110bb+/-2 */
+    uint32_t img_type;             /*!< Image check type, with or without optional CRC */
+    uint32_t target_addr;          /*!< Target address */
+    uint32_t img_len;              /*!< Image length or the length of image CRC check should be done.
+                           For faster boot application could set a smaller length than actual image.
+                           For Secure boot images, this MUST be the entire image length */
+    uint32_t stated_size;          /*!< max size of any subsequent image : AppSize0 = 2 x stated_size */
+    uint32_t certificate_offset;   /*!< Offset of the certificate list */
+    uint32_t compatibility_offset; /*!< Offset of the compatibility list */
+    uint32_t version;              /*!< Image version for multi-image support */
+} BOOT_BLOCK_T;
+
+/****************************************************************************/
+/***        Exported Functions                                            ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Exported Variables                                            ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* FLASH_HEADER_H_ */
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/rom_apis/rom_aes.h

@@ -0,0 +1,337 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _ROM_AES_H
+#define _ROM_AES_H
+
+/*******************
+ * INCLUDE FILES    *
+ ********************/
+#include <stdint.h>
+#include "rom_common.h"
+
+/*!
+ * @addtogroup ROM_API
+ * @{
+ */
+
+/*! @file */
+
+typedef uint32_t ErrorCode_t;  /*!< enum defined in error.h */
+
+/*******************
+ * EXPORTED MACROS  *
+ ********************/
+
+#define AES_ENCDEC_MODE (1 << 0)
+#define AES_GF128HASH_MODE (2 << 0)
+#define AES_ENDEC_GF128HASH_MODE (3 << 0)
+#define AES_GF128_SEL (1 << 2)
+#define AES_INT_BSWAP (1 << 4)
+#define AES_INT_WSWAP (1 << 5)
+#define AES_OUTT_BSWAP (1 << 6)
+#define AES_OUTT_WSWAP (1 << 7)
+#define AES_KEYSIZE_128 (0 << 8)
+#define AES_KEYSIZE_192 (1 << 8)
+#define AES_KEYSIZE_256 (2 << 8)
+#define AES_INB_FSEL(n) ((n) << 16) /*!< n->1=Input Text, n->2=Holding, n->3=Input Text XOR Holding */
+#define AES_HOLD_FSEL(n) \
+    ((n) << 20) /*!< n->0=Counter, n->1=Input Text, n->2=Output Block, n->3=Input Text XOR Output Block */
+#define AES_OUTT_FSEL(n) ((n) << 24) /*!< n->0=OUTT, n->1=Output Block XOR Input Text, n->2=Output Block XOR Holding */
+
+/*********************
+ * EXPORTED TYPEDEFS  *
+ **********************/
+
+/*! @brief AES setup modes */
+typedef enum
+{
+    AES_MODE_ECB_ENCRYPT = 0,
+    AES_MODE_ECB_DECRYPT,
+    AES_MODE_CBC_ENCRYPT,
+    AES_MODE_CBC_DECRYPT,
+    AES_MODE_CFB_ENCRYPT,
+    AES_MODE_CFB_DECRYPT,
+    AES_MODE_OFB,
+    AES_MODE_CTR,
+    AES_MODE_GCM_TAG,
+    AES_MODE_UNUSED = 0x7FFFFFFF /*!< Not used, but forces enum to 32-bit size */
+} AES_MODE_T;
+
+/*! @brief Size of the AES key */
+typedef enum
+{
+    AES_KEY_128BITS = 0, /*!< KEY size 128 bits */
+    AES_KEY_192BITS, /*!< KEY size 192 bits */
+    AES_KEY_256BITS, /*!< KEY size 256 bits */
+    AES_FVAL = 0x7FFFFFFF /*!< Not used, but forces enum to 32-bit size and unsigned */
+} AES_KEY_SIZE_T;
+
+/*******************
+ * EXPORTED DATA    *
+ ********************/
+
+/********************************
+ * EXPORTED FUNCTIONS PROTOTYPES *
+ *********************************/
+
+/**
+ * @brief	Initialize the AES
+ *
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ * @note	Driver does not enable AES clock, power, or perform reset peripheral (if needed).
+ */
+static inline ErrorCode_t aesInit(void)
+{
+    ErrorCode_t (*p_aesInit)(void);
+    p_aesInit = (ErrorCode_t (*)(void))0x03001161U;
+
+    return p_aesInit();
+}
+
+/**
+ * @brief	AES control function, byte write (useful for writing configuration register)
+ * @brief	offset	: Register offset in AES, 32-bit aligned value
+ * @brief	val8	: 8-bit value to write
+ * @return	Nothing
+ * @note	This is an obfuscated function available from the ROM API as a 2nd level API
+ *			call. An application can used it perform byte level write access to a register.
+ *			This function is not meant to be public.
+ */
+static inline void aesWriteByte(uint32_t offset, uint8_t val8)
+{
+    void (*p_aesWriteByte)(uint32_t offset, uint8_t val8);
+    p_aesWriteByte = (void (*)(uint32_t offset, uint8_t val8))0x03001175U;
+
+    p_aesWriteByte(offset, val8);
+}
+
+/**
+ * @brief	AES control function, word write
+ * @brief	offset	: Register offset in AES, 32-bit aligned value
+ * @brief	val32	: 32-bit value to write
+ * @return	Nothing
+ * @note	This is an obfuscated function available from the ROM API as a 2nd level API
+ *			call. An application can used it for write access to a register. This function
+ *			is not meant to be public.
+ */
+static inline void aesWrite(uint32_t offset, uint32_t val32)
+{
+    void (*p_aesWrite)(uint32_t offset, uint32_t val32);
+    p_aesWrite = (void (*)(uint32_t offset, uint32_t val32))0x0300118dU;
+
+    p_aesWrite(offset, val32);
+}
+
+/**
+ * @brief	AES control function, word read
+ * @brief	offset	: Register offset in AES, 32-bit aligned value
+ * @brief	pVal32	: Pointer to 32-bit area to read into
+ * @return	Nothing
+ * @note	This is an obfuscated function available from the ROM API as a 2nd level API
+ *			call. An application can used it for read access to a register. This function
+ *			is not meant to be public.
+ */
+static inline void aesRead(uint32_t offset, uint32_t *pVal32)
+{
+    void (*p_aesRead)(uint32_t offset, uint32_t *pVal32);
+    p_aesRead = (void (*)(uint32_t offset, uint32_t *pVal32))0x030011a5U;
+
+    p_aesRead(offset, pVal32);
+}
+
+/**
+ * @brief	AES control function, block write (used for multi-register block writes)
+ * @brief	offset		: Register offset in AES, 32-bit aligned value
+ * @brief	pVal32		: Pointer to 32-bit array to write
+ * @brief	numBytes	: Number of bytes to write, must be 32-bit aligned
+ * @return	Nothing
+ * @note	This is an obfuscated function available from the ROM API as a 2nd level API
+ *			call. An application can used it for write access to a register. This function
+ *			is not meant to be public. Writes occur in 32-bit chunks.
+ */
+static inline void aesWriteBlock(uint32_t offset, uint32_t *pVal32, uint32_t numBytes)
+{
+    void (*p_aesWriteBlock)(uint32_t offset, uint32_t *pVal32, uint32_t numBytes);
+    p_aesWriteBlock = (void (*)(uint32_t offset, uint32_t *pVal32, uint32_t numBytes))0x030011c1U;
+
+    p_aesWriteBlock(offset, pVal32, numBytes);
+}
+
+/**
+ * @brief	AES control function, block read (used for multi-register block read)
+ * @brief	offset		: Register offset in AES, 32-bit aligned value
+ * @brief	pVal32		: Pointer to 32-bit array to read into
+ * @brief	numBytes	: Number of bytes to read, must be 32-bit aligned
+ * @return	Nothing
+ * @note	This is an obfuscated function available from the ROM API as a 2nd level API
+ *			call. An application can used it for read access to a register. This function
+ *			is not meant to be public. Reads occur in 32-bit chunks. Read data if undefined
+ *			if AES not present.
+ */
+static inline void aesReadBlock(uint32_t offset, uint32_t *pVal32, uint32_t numBytes)
+{
+    void (*p_aesReadBlock)(uint32_t offset, uint32_t *pVal32, uint32_t numBytes);
+    p_aesReadBlock = (void (*)(uint32_t offset, uint32_t *pVal32, uint32_t numBytes))0x030011e9U;
+
+    p_aesReadBlock(offset, pVal32, numBytes);
+}
+
+/**
+ * @brief	Sets up the AES mode
+ * @param	wipe	: use true to invalidate AES key and disable cipher
+ * @param	flags	: Applies extra flags (Or'ed in config), normally should be 0, useful for swap bits only
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ */
+static inline ErrorCode_t aesMode(AES_MODE_T modeVal, uint32_t flags)
+{
+    ErrorCode_t (*p_aesMode)(AES_MODE_T modeVal, uint32_t flags);
+    p_aesMode = (ErrorCode_t (*)(AES_MODE_T modeVal, uint32_t flags))0x03001211U;
+
+    return p_aesMode(modeVal, flags);
+}
+
+/**
+ * @brief	Aborts optional AES operation and wipes AES engine
+ * @param	wipe	: use true to invalidate AES key and disable cipher
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ */
+static inline ErrorCode_t aesAbort(int wipe)
+{
+    ErrorCode_t (*p_aesAbort)(int wipe);
+    p_aesAbort = (ErrorCode_t (*)(int wipe))0x03001269U;
+
+    return p_aesAbort(wipe);
+}
+
+/**
+ * @brief	Loads the increment that is used when in counter modes in the AES block
+ * @param	counter	: 32-bit initial increment counter value
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ */
+static inline ErrorCode_t aesLoadCounter(uint32_t counter)
+{
+    ErrorCode_t (*p_aesLoadCounter)(uint32_t counter);
+    p_aesLoadCounter = (ErrorCode_t (*)(uint32_t counter))0x03001291U;
+
+    return p_aesLoadCounter(counter);
+}
+
+/**
+ * @brief	Loads the passed (software) key into the AES block
+ * @param	keySize	: 0 = 128-bits, 1 = 192-bits, 2 = 256-bits, all other values are invalid (AES_KEY_SIZE_T)
+ * @param	key		: Pointer to up to a 256-bit key array
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ */
+static inline ErrorCode_t aesLoadKeyFromSW(AES_KEY_SIZE_T keySize, uint32_t *key)
+{
+    ErrorCode_t (*p_aesLoadKeyFromSW)(AES_KEY_SIZE_T keySize, uint32_t *key);
+    p_aesLoadKeyFromSW = (ErrorCode_t (*)(AES_KEY_SIZE_T keySize, uint32_t *key))0x030012a9U;
+
+    return p_aesLoadKeyFromSW(keySize, key);
+}
+
+/**
+ * @brief	Loads the Initialization Vector (IV) into the AES block
+ * @param	iv	: 32-bit initialization vector
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ */
+static inline ErrorCode_t aesLoadIV(uint32_t *pIv)
+{
+    ErrorCode_t (*p_aesLoadIV)(uint32_t *pIv);
+    p_aesLoadIV = (ErrorCode_t (*)(uint32_t *pIv))0x030012fdU;
+
+    return p_aesLoadIV(pIv);
+}
+
+/**
+ * @brief	Process AES blocks (descrypt or encrypt)
+ * @param	pBlockIn	: 32-bit aligned pointer to input block of data
+ * @param	pBlockOut	: 32-bit aligned pointer to output block of data
+ * @param	numBlocks	: Number of blocks to process, block size = 128 bits
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ * @note	The AES mode and key must be setup prior to calling this function.
+ *			For encryption. the plain text is used as the input and encrypted
+ *			text is output. For descryption, plain text is output while
+ *			encrypted text is input.
+ */
+static inline ErrorCode_t aesProcess(uint32_t *pBlockIn, uint32_t *pBlockOut, uint32_t numBlocks)
+{
+    ErrorCode_t (*p_aesProcess)(uint32_t *pBlockIn, uint32_t *pBlockOut, uint32_t numBlocks);
+    p_aesProcess = (ErrorCode_t (*)(uint32_t *pBlockIn, uint32_t *pBlockOut, uint32_t numBlocks))0x030013d1U;
+
+    return p_aesProcess(pBlockIn, pBlockOut, numBlocks);
+}
+
+/**
+ * @brief	Sets the Y input of the GF128 hash used in GCM mode
+ * @param	pYGf128	: Y input of GF128 hash (4x32-bit words)
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ * @note	Calling this function will reset the hash logic.
+ */
+static inline ErrorCode_t aesWriteYInputGf128(uint32_t *pYGf128)
+{
+    ErrorCode_t (*p_aesWriteYInputGf128)(uint32_t *pYGf128);
+    p_aesWriteYInputGf128 = (ErrorCode_t (*)(uint32_t *pYGf128))0x0300132dU;
+
+    return p_aesWriteYInputGf128(pYGf128);
+}
+
+/**
+ * @brief	Reads the results of the GF128(Z) hash used in GCM mode
+ * @param	pGf128Hash	: Array of 4x32-bit words to read hash into
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ * @note	Value is undefined if AES is not present.
+ */
+static inline ErrorCode_t aesReadGf128Hash(uint32_t *pGf128Hash)
+{
+    ErrorCode_t (*p_aesReadGf128Hash)(uint32_t *pGf128Hash);
+    p_aesReadGf128Hash = (ErrorCode_t (*)(uint32_t *pGf128Hash))0x0300135dU;
+
+    return p_aesReadGf128Hash(pGf128Hash);
+}
+
+/**
+ * @brief	Reads the GCM tag
+ * @param	pGcmTag	: Array of 4x32-bit words to read GCM tage into
+ * @return	LPC_OK on success, or an error code (ERRORCODE_T) on failure
+ * @note	The GCM tage is an XOR value of the Output Text and GF128(Z) hash value.
+ *			Value is undefined if AES is not present.
+ */
+static inline ErrorCode_t aesReadGcmTag(uint32_t *pGcmTag)
+{
+    ErrorCode_t (*p_aesReadGcmTag)(uint32_t *pGcmTag);
+    p_aesReadGcmTag = (ErrorCode_t (*)(uint32_t *pGcmTag))0x0300138dU;
+
+    return p_aesReadGcmTag(pGcmTag);
+}
+
+/**
+ * @brief	Returns the version of the AES driver in ROM
+ * @return	Driver version, example 0x00000100 = v1.0
+ */
+static inline uint32_t aesGetDriverVersion(void)
+{
+    uint32_t (*p_aesGetDriverVersion)(void);
+    p_aesGetDriverVersion = (uint32_t (*)(void))0x030013bdU;
+
+    return p_aesGetDriverVersion();
+}
+
+/**
+ * @brief	Returns status of AES IP block (supported or not)
+ * @return	LPC_OK if enabled, ERR_SEC_AES_NOT_SUPPORTED if not supported
+ */
+static inline ErrorCode_t aesIsSupported(void)
+{
+    ErrorCode_t (*p_aesIsSupported)(void);
+    p_aesIsSupported = (ErrorCode_t (*)(void))0x0300115dU;
+
+    return p_aesIsSupported();
+}
+
+#endif /* _ROM_AES_H      Do not add any thing below this line */

third_party/nxp/JN5189/rom_apis/rom_api.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROM_API_H_
+#define ROM_API_H_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup ROM_API
+ * @{
+ */
+
+/*! @file */
+
+/****************************************************************************/
+/***        Include Files                                                 ***/
+/****************************************************************************/
+
+#include <stdint.h>
+#include "rom_common.h"
+#include "rom_psector.h"
+#include "flash_header.h"
+#include "rom_aes.h"
+
+/****************************************************************************/
+/***        Macro Definitions                                             ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Type Definitions                                              ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Exported Functions                                            ***/
+/****************************************************************************/
+
+/*!
+ * @brief Convert logical address into physical address, based on SYSCOM MEMORYREMAP register
+ *
+ * The chip has a remapping capability that allows to remap internal flash areas.
+ * This feature is part of the firmware update mechanism (OTA).
+ *
+ * @param  address logical address to convert
+ *
+ * @return  physical address
+ *
+ */
+static inline uint32_t BOOT_RemapAddress(uint32_t address)
+{
+    uint32_t (*p_BOOT_RemapAddress)(uint32_t address);
+    p_BOOT_RemapAddress = (uint32_t(*)(uint32_t address))0x03000dc9U;
+
+    return p_BOOT_RemapAddress(address);
+}
+
+/*! @brief IMAGE_DATA_T image node : element of single link chained list of images found in flash */
+typedef struct _image_data_t
+{
+    uint32_t version;           /*!< version number found in image  */
+    uint32_t address;           /*!< start address of image */
+    struct _image_data_t *next; /*!< pointer on next IMAGE_DATA_T in list */
+} IMAGE_DATA_T;
+
+/*! @brief IMAGE_VERIFY_T function pointer : verification function  e.g. boot_Verify_eScoreImageList */
+typedef uint32_t (*IMAGE_VERIFY_T)(IMAGE_DATA_T *list_head);
+
+/*!
+ * @brief Parse the image chained list and select the first valid entry.
+ *
+ * The image list is already sorted by version number. Compare image version against
+ * Min version read from PSECT. If it is greater than or equal to Min version, perform the
+ * RSA authentication over the image using the ket found in PFLASH if any.
+ * see IMAGE_VERIFY_T
+ * @param  list_head sorted list of images
+ *
+ * @return  selected image start address
+ *
+ */
+static inline uint32_t boot_Verify_eScoreImageList(IMAGE_DATA_T *list_head)
+{
+    uint32_t (*p_boot_Verify_eScoreImageList)(IMAGE_DATA_T * list_head);
+    p_boot_Verify_eScoreImageList = (uint32_t(*)(IMAGE_DATA_T * list_head))0x030003e5U;
+
+    return p_boot_Verify_eScoreImageList(list_head);
+}
+
+/*!
+ * @brief Search for a valid executable image between boundaries in internal flash.
+ *
+ * This function is involved in the search of a bootable image.
+ * It is called by the boot ROM on Cold boot but can be called by the Selective OTA.
+ *
+ * The application granularity parameter is read from the PSECT, this is used as the
+ * increment used to hop to next position in case of failure.
+ * The function builds up a chained list of image descriptors that it sorts by version number.
+ * The intent is that the most recent version is at the head of the list.
+ *
+ * @param  start_addr address from which to start search
+ *
+ * @param  end_addr  address from which to start search
+ *
+ * @param  signature  magic identifier : constant 0x98447902
+ *
+ * @param  IMAGE_VERIFY_T verification function pointer (see @boot_Verify_eScoreImageList)
+ *         This parameter cannot be NULL.
+ *         The implementer may opt for a version that simply returns the head of the chained list.
+ *
+ * @return  image address if valid, IMAGE_INVALID_ADDR (0xffffffff) otherwise
+ *
+ */
+static inline uint32_t BOOT_FindImage(uint32_t start_addr, uint32_t end_addr, uint32_t signature, IMAGE_VERIFY_T verify)
+{
+    uint32_t (*p_BOOT_FindImage)(uint32_t start_addr, uint32_t end_addr, uint32_t signature, IMAGE_VERIFY_T verify);
+    p_BOOT_FindImage =
+        (uint32_t(*)(uint32_t start_addr, uint32_t end_addr, uint32_t signature, IMAGE_VERIFY_T verify))0x03000519U;
+
+    return p_BOOT_FindImage(start_addr, end_addr, signature, verify);
+}
+
+/*!
+ * @brief Retrieve LPMode value that has been saved previously in retained RAM bank.
+ *
+ * This is mostly used to determine in which power mode the PMC was before reset,
+ * i.e. whether is is a cold or warm reset. This is to be invoked from ResetISR2
+ *
+ * @param  none
+ *
+ * @return  LPMode
+ *
+ */
+static inline uint32_t BOOT_GetStartPowerMode(void)
+{
+    uint32_t (*p_BOOT_GetStartPowerMode)(void);
+    p_BOOT_GetStartPowerMode = (uint32_t(*)(void))0x03000e9dU;
+
+    return p_BOOT_GetStartPowerMode();
+}
+
+/*!
+ * @brief Sets the value of stack pointer to be restored on warm boot.
+ *
+ * @param  stack_pointer address to be written in retained RAM bank so that
+ * boot ROM restores value on warm start
+ *
+ * @return  none
+ *
+ */
+static inline void BOOT_SetResumeStackPointer(uint32_t stack_pointer)
+{
+    void (*p_BOOT_SetResumeStackPointer)(uint32_t stack_pointer);
+    p_BOOT_SetResumeStackPointer = (void (*)(uint32_t stack_pointer))0x03000ea9U;
+
+    p_BOOT_SetResumeStackPointer(stack_pointer);
+}
+
+/*!
+ * @brief Retrieve Internal flash address and size
+ *
+ * The internal flash start address is necessarily 0.
+ * Its size may vary depending on chip options.
+ * The size returned is the number of bytes usable for program and data.
+ * The maximum possible value is 0x9dc00.
+ *
+ * @param address pointer on location to store returned address
+ *
+ * @param size pointer on location to store returned size
+ *
+ * @return  *address is 0x00000000UL and *size is up to 0x9dc00
+ *
+ */
+static inline void ROM_GetFlash(uint32_t *address, uint32_t *size)
+{
+    void (*p_ROM_GetFlash)(uint32_t * address, uint32_t * size);
+    p_ROM_GetFlash = (void (*)(uint32_t * address, uint32_t * size))0x03000e0dU;
+
+    p_ROM_GetFlash(address, size);
+}
+
+/*!
+ * @brief Retrieve SRAM0 address and size
+ *
+ * @param address pointer on location to store returned address
+ *
+ * @param size pointer on location to store returned size
+ *
+ * @return  *address is 0x04000000UL and *size is 88k (0x16000)
+ *
+ */
+static inline void ROM_GetSRAM0(uint32_t *address, uint32_t *size)
+{
+    void (*p_ROM_GetSRAM0)(uint32_t * address, uint32_t * size);
+    p_ROM_GetSRAM0 = (void (*)(uint32_t * address, uint32_t * size))0x03000e21U;
+
+    p_ROM_GetSRAM0(address, size);
+}
+
+/*!
+ * @brief Retrieve SRAM1 address and size.
+ *        SRAM1 presence is optional depending on chip variant
+ *
+ * @param address pointer on location to store returned address
+ *
+ * @param size pointer on location to store returned size
+ *
+ * @return  if SRAM1 not present *address is 0 and *size is 0,
+ *          otherwise *address is  0x04020000UL and *size is up to 64k (0x10000)
+ */
+static inline void ROM_GetSRAM1(uint32_t *address, uint32_t *size)
+{
+    void (*p_ROM_GetSRAM1)(uint32_t * address, uint32_t * size);
+    p_ROM_GetSRAM1 = (void (*)(uint32_t * address, uint32_t * size))0x03000e35U;
+
+    p_ROM_GetSRAM1(address, size);
+}
+
+/****************************************************************************/
+/***        Exported Variables                                            ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* ROM_API_H_ */
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/rom_apis/rom_common.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROM_COMMON_H_
+#define ROM_COMMON_H_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/***        Include Files                                                 ***/
+/****************************************************************************/
+
+#include <stdbool.h>
+
+/****************************************************************************/
+/***        Macro Definitions                                             ***/
+/****************************************************************************/
+
+/* Define ROM compilation for ES2 - required for lowpower API as it supports ES1/ES2 compilation */
+//#define CPU_JN518X_REV 2
+
+#ifdef ROM_BUILD
+#define ROM_API __attribute__((section(".text.api")))
+#else
+#ifdef __MINGW32__
+#define ROM_API
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+#define ROM_API
+#else
+#define ROM_API __attribute__((long_call))
+#endif
+#endif
+
+#ifndef WEAK
+#define WEAK __attribute__((weak))
+#endif
+
+#ifdef __CDT_PARSER__
+#define STATIC_ASSERT(value, message)
+#else
+#define STATIC_ASSERT _Static_assert
+#endif
+
+/****************************************************************************/
+/***        Type Definitions                                              ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Exported Functions                                            ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/***        Exported Variables                                            ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* ROM_COMMON_H_ */
+
+/****************************************************************************/
+/***        END OF FILE                                                   ***/
+/****************************************************************************/

third_party/nxp/JN5189/rom_apis/rom_lowpower.h

@@ -0,0 +1,506 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ROM_LOWPOWER_H_
+#define __ROM_LOWPOWER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rom_common.h>
+#include <rom_pmc.h>
+
+/** @defgroup LOWPOWER_JN518X CHIP: JN518X LOWPOWER Driver
+ * @ingroup CHIP_JN518X_DRIVERS
+ * @{
+ */
+
+/*******************
+ * EXPORTED MACROS  *
+ ********************/
+
+/* Low Power modes  */
+#define LOWPOWER_CFG_MODE_INDEX 0
+#define LOWPOWER_CFG_MODE_MASK (0x3UL << LOWPOWER_CFG_MODE_INDEX)
+
+#define LOWPOWER_CFG_XTAL32MSTARTENA_INDEX 2
+#define LOWPOWER_CFG_XTAL32MSTARTENA_MASK (0x1UL << LOWPOWER_CFG_XTAL32MSTARTENA_INDEX)
+
+#define LOWPOWER_CFG_FLASHPWDNMODE_INDEX 4
+#define LOWPOWER_CFG_FLASHPWDNMODE_MASK (0x1UL << LOWPOWER_CFG_FLASHPWDNMODE_INDEX)
+
+#define LOWPOWER_CFG_SRAMPWDNMODE_INDEX 6
+#define LOWPOWER_CFG_SRAMPWDNMODE_MASK (0x1UL << LOWPOWER_CFG_SRAMPWDNMODE_INDEX)
+
+#define LOWPOWER_CFG_PDRUNCFG_DISCARD_INDEX 7
+#define LOWPOWER_CFG_PDRUNCFG_DISCARD_MASK (0x1UL << LOWPOWER_CFG_PDRUNCFG_DISCARD_INDEX)
+
+#define LOWPOWER_CFG_WFI_NOT_WFE_INDEX 8
+#define LOWPOWER_CFG_WFI_NOT_WFE_MASK (0x1UL << LOWPOWER_CFG_WFI_NOT_WFE_INDEX)
+
+#define LOWPOWER_CFG_LDOMEM_FORCE_ENABLE_INDEX 9
+#define LOWPOWER_CFG_LDOMEM_FORCE_ENABLE_MASK (0x1UL << LOWPOWER_CFG_LDOMEM_FORCE_ENABLE_INDEX)
+
+#define LOWPOWER_CFG_LDOFLASHCORE_UPDATE_INDEX 10
+#define LOWPOWER_CFG_LDOFLASHCORE_UPDATE_MASK (0x1UL << LOWPOWER_CFG_LDOFLASHCORE_UPDATE_INDEX)
+
+/* Delay to wakeup the flash after the LDO Flash Core has been set up to active voltage : 0: 19us, then increment by
+ * 4.75us steps */
+#define LOWPOWER_CFG_LDOFLASHCORE_DELAY_INDEX 11
+#define LOWPOWER_CFG_LDOFLASHCORE_DELAY_MASK (0x7UL << LOWPOWER_CFG_LDOFLASHCORE_DELAY_INDEX)
+
+#define LOWPOWER_CFG_MODE_ACTIVE 0        /*!< ACTIVE mode */
+#define LOWPOWER_CFG_MODE_DEEPSLEEP 1     /*!< DEEP SLEEP mode */
+#define LOWPOWER_CFG_MODE_POWERDOWN 2     /*!< POWER DOWN mode */
+#define LOWPOWER_CFG_MODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */
+
+#define LOWPOWER_CFG_XTAL32MSTART_DISABLE \
+    0 /*!< Disable Crystal 32 MHz automatic start when waking up from POWER DOWN and DEEP POWER DOWN modes */
+#define LOWPOWER_CFG_XTAL32MSTART_ENABLE \
+    1 /*!< Enable Crystal 32 MHz automatic start when waking up from POWER DOWN and DEEP POWER DOWN modes */
+
+#define LOWPOWER_CFG_FLASHPWDNMODE_FLASHPWND \
+    0 /*!< Power down the Flash only (send CMD_POWERDOWN to Flash controller). Only valid in DEEP SLEEP mode */
+#define LOWPOWER_CFG_FLASHPWDNMODE_LDOSHUTOFF                                                                         \
+    1 /*!< Power down the Flash ((send CMD_POWERDOWN to Flash controller) and shutoff both Flash LDOs (Core and NV) \ \
+         (only valid in DEEP SLEEP mode) */
+
+/**
+ * @brief Analog Power Domains (analog components in Power Management Unit) Low Power Modes control
+ */
+#define LOWPOWER_PMUPWDN_DCDC (1UL << 0)     /*!< Power Down DCDC Converter  */
+#define LOWPOWER_PMUPWDN_BIAS (1UL << 1)     /*!< Power Down all Bias and references */
+#define LOWPOWER_PMUPWDN_LDOMEM (1UL << 2)   /*!< Power Down Memories LDO  */
+#define LOWPOWER_PMUPWDN_BODVBAT (1UL << 3)  /*!< Power Down VBAT Brown Out Detector */
+#define LOWPOWER_PMUPWDN_FRO192M (1UL << 4)  /*!< Power Down FRO 192 MHz  */
+#define LOWPOWER_PMUPWDN_FRO1M (1UL << 5)    /*!< Power Down FRO 1 MHz  */
+#define LOWPOWER_PMUPWDN_GPADC (1UL << 22)   /*!< Power Down General Purpose ADC */
+#define LOWPOWER_PMUPWDN_BODMEM (1UL << 23)  /*!< Power Down Memories Brown Out Detector */
+#define LOWPOWER_PMUPWDN_BODCORE (1UL << 24) /*!< Power Down Core Logic Brown Out Detector */
+#define LOWPOWER_PMUPWDN_FRO32K (1UL << 25)  /*!< Power Down FRO 32 KHz */
+#define LOWPOWER_PMUPWDN_XTAL32K (1UL << 26) /*!< Power Down Crystal 32 KHz */
+#define LOWPOWER_PMUPWDN_ANACOMP (1UL << 27) /*!< Power Down Analog Comparator */
+
+#define LOWPOWER_PMUPWDN_XTAL32M (1UL << 28)    /*!< Power Down Crystal 32 MHz */
+#define LOWPOWER_PMUPWDN_TEMPSENSOR (1UL << 29) /*!< Power Down Temperature Sensor   */
+
+/**
+ * @brief Digital Power Domains Low Power Modes control
+ */
+#define LOWPOWER_DIGPWDN_FLASH                                                                                     \
+    (1UL << 6) /*!< Power Down Flash Power Domain (Flash Macro, Flash Controller and/or FLash LDOs, depending on \ \
+                   LOWPOWER_CFG_FLASHPWDNMODE parameter) */
+#define LOWPOWER_DIGPWDN_COMM0 (1UL << 7) /*!< Power Down Digital COMM0 power domain (USART0, I2C0 and SPI0) */
+#define LOWPOWER_DIGPWDN_MCU_RET                                                                                    \
+    (1UL << 8) /*!< Power Down MCU Retention Power Domain (Disable Zigbee IP retention, ES1:Disable CPU retention \ \
+                   flip-flops) */
+#define LOWPOWER_DIGPWDN_ZIGBLE_RET \
+    (1UL << 9) /*!< Power Down ZIGBEE/BLE retention Power Domain (Disable ZIGBEE/BLE retention flip-flops) */
+
+#define LOWPOWER_DIGPWDN_SRAM0_INDEX 10
+#define LOWPOWER_DIGPWDN_SRAM0 \
+    (1UL << LOWPOWER_DIGPWDN_SRAM0_INDEX)   /*!< Power Down SRAM 0  instance [Bank 0, 16 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM1 (1UL << 11)  /*!< Power Down SRAM 1  instance [Bank 0, 16 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM2 (1UL << 12)  /*!< Power Down SRAM 2  instance [Bank 0, 16 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM3 (1UL << 13)  /*!< Power Down SRAM 3  instance [Bank 0, 16 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM4 (1UL << 14)  /*!< Power Down SRAM 4  instance [Bank 0,  8 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM5 (1UL << 15)  /*!< Power Down SRAM 5  instance [Bank 0,  8 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM6 (1UL << 16)  /*!< Power Down SRAM 6  instance [Bank 0,  4 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM7 (1UL << 17)  /*!< Power Down SRAM 7  instance [Bank 0,  4 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM8 (1UL << 18)  /*!< Power Down SRAM 8  instance [Bank 1, 16 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM9 (1UL << 19)  /*!< Power Down SRAM 9  instance [Bank 1, 16 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM10 (1UL << 20) /*!< Power Down SRAM 10 instance [Bank 1, 16 KB], (no retention) */
+#define LOWPOWER_DIGPWDN_SRAM11 (1UL << 21) /*!< Power Down SRAM 11 instance [Bank 1, 16 KB], (no retention) */
+
+#define LOWPOWER_DIGPWDN_SRAM_ALL_MASK                                                                   \
+    (LOWPOWER_DIGPWDN_SRAM0 | LOWPOWER_DIGPWDN_SRAM1 | LOWPOWER_DIGPWDN_SRAM2 | LOWPOWER_DIGPWDN_SRAM3 | \
+     LOWPOWER_DIGPWDN_SRAM4 | LOWPOWER_DIGPWDN_SRAM5 | LOWPOWER_DIGPWDN_SRAM6 | LOWPOWER_DIGPWDN_SRAM7 | \
+     LOWPOWER_DIGPWDN_SRAM8 | LOWPOWER_DIGPWDN_SRAM9 | LOWPOWER_DIGPWDN_SRAM10 | LOWPOWER_DIGPWDN_SRAM11)
+
+#define LOWPOWER_DIGPWDN_IO_INDEX 30
+#define LOWPOWER_DIGPWDN_IO (1UL << LOWPOWER_DIGPWDN_IO_INDEX) /*!< Power Down   */
+
+#define LOWPOWER_DIGPWDN_NTAG_FD_INDEX 31
+#define LOWPOWER_DIGPWDN_NTAG_FD \
+    (1UL << LOWPOWER_DIGPWDN_NTAG_FD_INDEX) /*!< NTAG FD field detect Disable - need the IO source to be set too */
+
+/**
+ * @brief LDO Voltage control in Low Power Modes
+ */
+
+#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL)
+#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL)    /*!<  */
+#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL)     /*!<  */
+#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!<  */
+#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL)  /*!<  */
+#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL)   /*!<  */
+
+/**
+ * @brief LDO Voltage control in Low Power Modes
+ */
+#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0
+#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FUL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX)
+#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5
+#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FUL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX)
+#define LOWPOWER_VOLTAGE_LDO_CORE_INDEX 10
+#define LOWPOWER_VOLTAGE_LDO_CORE_MASK (0x7UL << LOWPOWER_VOLTAGE_LDO_CORE_INDEX)
+#define LOWPOWER_VOLTAGE_LDO_FLASH_CORE_INDEX 13
+#define LOWPOWER_VOLTAGE_LDO_FLASH_CORE_MASK (0x7UL << LOWPOWER_VOLTAGE_LDO_FLASH_CORE_INDEX)
+#define LOWPOWER_VOLTAGE_LDO_FLASH_NV_INDEX 16
+#define LOWPOWER_VOLTAGE_LDO_FLASH_NV_MASK (0x7UL << LOWPOWER_VOLTAGE_LDO_FLASH_NV_INDEX)
+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19
+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FUL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX)
+#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24
+#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FUL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX)
+/* Only for ES2 but defined it for ES1 for easier power driver writing (has no effect on ES1) */
+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_ENABLE_INDEX 29
+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_ENABLE_MASK (0x1UL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_ENABLE_INDEX)
+
+/**
+ * @brief Low Power Modes Wake up Interrupt sources
+ */
+#define LOWPOWER_WAKEUPSRCINT0_SYSTEM_IRQ \
+    (1UL << 0) /*!< BOD, Watchdog Timer, Flash controller, Firewall [DEEP SLEEP] BOD [POWER_DOWN]*/
+#define LOWPOWER_WAKEUPSRCINT0_DMA_IRQ (1UL << 1)       /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_GINT_IRQ (1UL << 2)      /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_IRBLASTER_IRQ (1UL << 3) /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PINT0_IRQ (1UL << 4)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PINT1_IRQ (1UL << 5)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PINT2_IRQ (1UL << 6)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PINT3_IRQ (1UL << 7)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_SPIFI_IRQ (1UL << 8)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_TIMER0_IRQ (1UL << 9)    /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_TIMER1_IRQ (1UL << 10)   /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_USART0_IRQ (1UL << 11)   /*!< [DEEP SLEEP, POWER DOWN] */
+#define LOWPOWER_WAKEUPSRCINT0_USART1_IRQ (1UL << 12)   /*!< [DEEP SLEEP]  */
+#define LOWPOWER_WAKEUPSRCINT0_I2C0_IRQ (1UL << 13)     /*!< [DEEP SLEEP, POWER DOWN] */
+#define LOWPOWER_WAKEUPSRCINT0_I2C1_IRQ (1UL << 14)     /*!< [DEEP SLEEP]  */
+#define LOWPOWER_WAKEUPSRCINT0_SPI0_IRQ (1UL << 15)     /*!< [DEEP SLEEP, POWER DOWN] */
+#define LOWPOWER_WAKEUPSRCINT0_SPI1_IRQ (1UL << 16)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM0_IRQ (1UL << 17)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM1_IRQ (1UL << 18)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM2_IRQ (1UL << 19)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM3_IRQ (1UL << 20)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM4_IRQ (1UL << 21)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM5_IRQ (1UL << 22)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM6_IRQ (1UL << 23)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM7_IRQ (1UL << 24)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM8_IRQ (1UL << 25)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM9_IRQ (1UL << 26)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_PWM10_IRQ (1UL << 27)    /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_I2C2_IRQ (1UL << 28)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT0_RTC_IRQ (1UL << 29)      /*!< [DEEP SLEEP, POWER DOWN]  */
+#define LOWPOWER_WAKEUPSRCINT0_NFCTAG_IRQ (1UL << 30)   /*!< [DEEP SLEEP]  */
+#define LOWPOWER_WAKEUPSRCINT0_MAILBOX_IRQ \
+    (1UL << 31) /*!< Mailbox, Wake-up from DEEP SLEEP and POWER DOWN low power mode [DEEP SLEEP, POWER DOWN] */
+
+#define LOWPOWER_WAKEUPSRCINT1_ADC_SEQA_IRQ (1UL << 0)        /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_ADC_SEQB_IRQ (1UL << 1)        /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_ADC_THCMP_OVR_IRQ (1UL << 2)   /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_DMIC_IRQ (1UL << 3)            /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_HWVAD_IRQ (1UL << 4)           /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_BLE_DP_IRQ (1UL << 5)          /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_BLE_DP0_IRQ (1UL << 6)         /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_BLE_DP1_IRQ (1UL << 7)         /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_BLE_DP2_IRQ (1UL << 8)         /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_BLE_LL_ALL_IRQ (1UL << 9)      /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MAC_IRQ (1UL << 10)     /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MODEM_IRQ (1UL << 11)   /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_RFP_TMU_IRQ (1UL << 12)        /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_RFP_AGC_IRQ (1UL << 13)        /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_ISO7816_IRQ (1UL << 14)        /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_ANA_COMP_IRQ (1UL << 15)       /*!< [DEEP SLEEP] */
+#define LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER0_IRQ (1UL << 16) /*!< [DEEP SLEEP, POWER DOWN] */
+#define LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER1_IRQ (1UL << 17) /*!< [DEEP SLEEP, POWER DOWN] */
+#define LOWPOWER_WAKEUPSRCINT1_BLE_WAKE_TIMER_IRQ (1UL << 22) /*!< [DEEP SLEEP, POWER DOWN] */
+#define LOWPOWER_WAKEUPSRCINT1_BLE_OSC_EN_IRQ (1UL << 23)     /*!< [DEEP SLEEP, POWER DOWN] */
+#define LOWPOWER_WAKEUPSRCINT1_IO_IRQ (1UL << 31)             /*!< [POWER DOWN, DEEP DOWN]  */
+
+/**
+ * @brief Sleep Postpone
+ */
+#define LOWPOWER_SLEEPPOSTPONE_FORCED \
+    (1UL << 0) /*!< Forces postpone of power down modes in case the processor request low power mode*/
+#define LOWPOWER_SLEEPPOSTPONE_PERIPHERALS                                                                             \
+    (1UL << 1) /*!< USART0, USART1, SPI0, SPI1, I2C0, I2C1, I2C2 interrupts can postpone power down modes in case an \ \
+                   interrupt is pending when the processor request low power mode */
+#define LOWPOWER_SLEEPPOSTPONE_DMIC                                                                                   \
+    (1UL << 0) /*!< DMIC interrupt can postpone power down modes in case an interrupt is pending when the processor \ \
+                   request low power mode */
+#define LOWPOWER_SLEEPPOSTPONE_SDMA                                                                               \
+    (1UL << 1) /*!< System DMA interrupt can postpone power down modes in case an interrupt is pending when the \ \
+                   processor request low power mode */
+#define LOWPOWER_SLEEPPOSTPONE_NFCTAG                                                                          \
+    (1UL << 0) /*!< NFC Tag interrupt can postpone power down modes in case an interrupt is pending when the \ \
+                   processor request low power mode */
+#define LOWPOWER_SLEEPPOSTPONE_BLEOSC                                                                             \
+    (1UL << 1) /*!< BLE_OSC_EN interrupt can postpone power down modes in case an interrupt is pending when the \ \
+                   processor request low power mode */
+
+/**
+ * @brief Wake up I/O sources
+ */
+#define LOWPOWER_WAKEUPIOSRC_PIO0 (1UL << 0)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO1 (1UL << 1)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO2 (1UL << 2)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO3 (1UL << 3)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO4 (1UL << 4)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO5 (1UL << 5)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO6 (1UL << 6)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO7 (1UL << 7)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO8 (1UL << 8)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO9 (1UL << 9)   /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO10 (1UL << 10) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO11 (1UL << 11) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO12 (1UL << 12) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO13 (1UL << 13) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO14 (1UL << 14) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO15 (1UL << 15) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO16 (1UL << 16) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO17 (1UL << 17) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO18 (1UL << 18) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO19 (1UL << 19) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO20 (1UL << 20) /*!<    */
+#define LOWPOWER_WAKEUPIOSRC_PIO21 (1UL << 21) /*!<    */
+
+#ifndef LOWPOWER_API_ES1_ONLY
+/* For NTAG FD wakeup source, SW shall enable virtual IO 22 in */
+#define LOWPOWER_WAKEUPIOSRC_NTAG_FD (1UL << 22) /*!<    */
+#endif
+
+/**
+ * @brief I/O whose state must be kept in Power Down mode
+ */
+#define LOWPOWER_GPIOLATCH_PIO0 (1UL << 0)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO1 (1UL << 1)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO2 (1UL << 2)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO3 (1UL << 3)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO4 (1UL << 4)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO5 (1UL << 5)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO6 (1UL << 6)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO7 (1UL << 7)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO8 (1UL << 8)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO9 (1UL << 9)   /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO10 (1UL << 10) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO11 (1UL << 11) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO12 (1UL << 12) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO13 (1UL << 13) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO14 (1UL << 14) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO15 (1UL << 15) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO16 (1UL << 16) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO17 (1UL << 17) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO18 (1UL << 18) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO19 (1UL << 19) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO20 (1UL << 20) /*!<    */
+#define LOWPOWER_GPIOLATCH_PIO21 (1UL << 21) /*!<    */
+
+/**
+ * @brief Wake up timers configuration in Low Power Modes
+ */
+#define LOWPOWER_TIMERCFG_ENABLE_INDEX 0
+#define LOWPOWER_TIMERCFG_ENABLE_MASK (0x1UL << LOWPOWER_TIMERCFG_ENABLE_INDEX)
+#define LOWPOWER_TIMERCFG_TIMER_INDEX 1
+#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX)
+#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4
+#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX)
+#define LOWPOWER_TIMERCFG_2ND_ENABLE_INDEX 5
+#define LOWPOWER_TIMERCFG_2ND_ENABLE_MASK (0x1UL << LOWPOWER_TIMERCFG_2ND_ENABLE_INDEX)
+#define LOWPOWER_TIMERCFG_2ND_TIMER_INDEX 6
+#define LOWPOWER_TIMERCFG_2ND_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_2ND_TIMER_INDEX)
+
+#define LOWPOWER_TIMERCFG_TIMER_ENABLE 1 /*!< Wake Timer Enable */
+
+/**
+ * @brief Primary Wake up timers configuration in Low Power Modes
+ */
+#define LOWPOWER_TIMERCFG_TIMER_WAKEUPTIMER0 0   /*!< Zigbee Wake up Counter 0 used as wake up source */
+#define LOWPOWER_TIMERCFG_TIMER_WAKEUPTIMER1 1   /*!< Zigbee Wake up Counter 1 used as wake up source */
+#define LOWPOWER_TIMERCFG_TIMER_BLEWAKEUPTIMER 2 /*!< BLE Wake up Counter used as wake up source */
+#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 3        /*!< 1 KHz Real Time Counter (RTC) used as wake up source */
+#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 4         /*!< 1 Hz Real Time Counter (RTC) used as wake up source */
+
+/**
+ * @brief Secondary Wake up timers configuration in Low Power Modes
+ */
+#define LOWPOWER_TIMERCFG_2ND_TIMER_WAKEUPTIMER0 0   /*!< Zigbee Wake up Counter 0 used as secondary wake up source */
+#define LOWPOWER_TIMERCFG_2ND_TIMER_WAKEUPTIMER1 1   /*!< Zigbee Wake up Counter 1 used as secondary wake up source */
+#define LOWPOWER_TIMERCFG_2ND_TIMER_BLEWAKEUPTIMER 2 /*!< BLE Wake up Counter used as secondary wake up source */
+#define LOWPOWER_TIMERCFG_2ND_TIMER_RTC1KHZ 3 /*!< 1 KHz Real Time Counter (RTC) used as secondary wake up source */
+#define LOWPOWER_TIMERCFG_2ND_TIMER_RTC1HZ 4  /*!< 1 Hz Real Time Counter (RTC) used as secondary wake up source */
+
+#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0  /*!< Wake up Timers uses FRO 32 KHz as clock source */
+#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */
+
+/**
+ * @brief BLE Wake up timers configuration in Low Power Modes
+ */
+#define LOWPOWER_TIMERBLECFG_RADIOEN_INDEX 0
+#define LOWPOWER_TIMERBLECFG_RADIOEN_MASK (0x3FFUL << LOWPOWER_TIMERBLECFG_RADIOEN_INDEX)
+#define LOWPOWER_TIMERBLECFG_OSCEN_INDEX 10
+#define LOWPOWER_TIMERBLECFG_OSCEN_MASK (0x7FFUL << LOWPOWER_TIMERBLECFG_OSCEN_INDEX)
+
+/** @brief	Low Power Main Structure */
+typedef struct
+{                           /*     */
+    uint32_t CFG;           /*!< Low Power Mode Configuration, and miscallenous options  */
+    uint32_t PMUPWDN;       /*!< Analog Power Domains (analog components in Power Management Unit) Low Power Modes  */
+    uint32_t DIGPWDN;       /*!< Digital Power Domains Low Power Modes */
+    uint32_t VOLTAGE;       /*!< LDO Voltage control in Low Power Modes */
+    uint32_t WAKEUPSRCINT0; /*!< Wake up sources Interrupt control */
+    uint32_t WAKEUPSRCINT1; /*!< Wake up sources Interrupt control */
+    uint32_t SLEEPPOSTPONE; /*!< Interrupt that can postpone power down modes in case an interrupt is pending when the
+                               processor request deepsleep */
+    uint32_t WAKEUPIOSRC;   /*!< Wake up I/O sources */
+    uint32_t GPIOLATCH;     /*!< I/Os which outputs level must be kept (in Power Down  mode)*/
+    uint32_t TIMERCFG;      /*!< Wake up timers configuration */
+    uint32_t TIMERBLECFG;   /*!< BLE wake up timer configuration (OSC_EN and RADIO_EN) */
+    uint32_t TIMERCOUNTLSB; /*!< Wake up Timer LSB*/
+    uint32_t TIMERCOUNTMSB; /*!< Wake up Timer MSB*/
+    uint32_t TIMER2NDCOUNTLSB; /*!< Second Wake up Timer LSB*/
+    uint32_t TIMER2NDCOUNTMSB; /*!< Second Wake up Timer MSB*/
+
+} LPC_LOWPOWER_T;
+
+/** @brief	Low Power Main Structure */
+typedef struct
+{                         /*   */
+    uint8_t LDOPMU;       /*!< Always-ON domain LDO voltage configuration */
+    uint8_t LDOPMUBOOST;  /*!< Always-ON domain LDO Boost voltage configuration */
+    uint8_t LDOMEM;       /*!< Memories LDO voltage configuration */
+    uint8_t LDOMEMBOOST;  /*!< Memories LDO Boost voltage configuration */
+    uint8_t LDOCORE;      /*!< Core Logic domain LDO voltage configuration */
+    uint8_t LDOFLASHNV;   /*!< Flash NV domain LDO voltage configuration */
+    uint8_t LDOFLASHCORE; /*!< Flash Core domain LDO voltage configuration */
+    uint8_t LDOADC;       /*!< General Purpose ADC LDO voltage configuration */
+#ifndef LOWPOWER_API_ES1_ONLY
+    uint8_t LDOPMUBOOST_ENABLE; /*!< Force Boost activation on LDOPMU */
+#endif
+} LPC_LOWPOWER_LDOVOLTAGE_T;
+
+/**
+ * @brief	Configure Wake or RTC timers. used for testing only
+ * @param	p_lowpower_cfg: pointer to a structure that contains all low power mode parameters
+ * @return	Nothing
+ */
+static inline void Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer(LPC_LOWPOWER_T *p_lowpower_cfg)
+{
+    void (*p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer)(LPC_LOWPOWER_T *p_lowpower_cfg);
+    p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer = (void (*)(LPC_LOWPOWER_T *p_lowpower_cfg))0x030038d1U;
+
+    p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer(p_lowpower_cfg);
+}
+/**
+ * @brief	Configure CPU and System Bus clock frequency
+ * @param	Frequency	:
+ * @return	Nothing
+ */
+static inline int Chip_LOWPOWER_SetSystemFrequency(uint32_t frequency)
+{
+    int (*p_Chip_LOWPOWER_SetSystemFrequency)(uint32_t frequency);
+    p_Chip_LOWPOWER_SetSystemFrequency = (int (*)(uint32_t frequency))0x03003d55U;
+
+    return p_Chip_LOWPOWER_SetSystemFrequency(frequency);
+}
+
+/**
+ * @brief	Configure Memory instances Low Power Mode
+ * @param	p_sram_instance: SRAM instance number, between 0 and 11.
+ * @param	p_sram_lp_mode : Low power mode : LOWPOWER_SRAM_LPMODE_ACTIVE, LOWPOWER_SRAM_LPMODE_SLEEP,
+ * LOWPOWER_SRAM_LPMODE_DEEPSLEEP, LOWPOWER_SRAM_LPMODE_SHUTDOWN
+ * @return	Status code
+ */
+static inline int Chip_LOWPOWER_SetMemoryLowPowerMode(uint32_t p_sram_instance, uint32_t p_sram_lp_mode)
+{
+    int (*p_Chip_LOWPOWER_SetMemoryLowPowerMode)(uint32_t p_sram_instance, uint32_t p_sram_lp_mode);
+    p_Chip_LOWPOWER_SetMemoryLowPowerMode = (int (*)(uint32_t p_sram_instance, uint32_t p_sram_lp_mode))0x03003d89U;
+
+    return p_Chip_LOWPOWER_SetMemoryLowPowerMode(p_sram_instance, p_sram_lp_mode);
+}
+
+/**
+ * @brief	Get System Voltages
+ * @param	p_ldo_voltage: pointer to a structure to fill with current voltages on the chip
+ * @return	Nothing
+ */
+static inline void Chip_LOWPOWER_GetSystemVoltages(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage)
+{
+    void (*p_Chip_LOWPOWER_GetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage);
+    p_Chip_LOWPOWER_GetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage))0x03003de1U;
+
+    p_Chip_LOWPOWER_GetSystemVoltages(p_ldo_voltage);
+}
+
+/**
+ * @brief	Configure System Voltages
+ * @param	p_ldo_voltage: pointer to a structure that contains new voltages to be applied
+ * @return	Nothing
+ */
+static inline void Chip_LOWPOWER_SetSystemVoltages(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage)
+{
+    void (*p_Chip_LOWPOWER_SetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage);
+    p_Chip_LOWPOWER_SetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage))0x03003e99U;
+
+    p_Chip_LOWPOWER_SetSystemVoltages(p_ldo_voltage);
+}
+
+/**
+ * @brief	Configure and enters in low power mode
+ * @param	p_lowpower_cfg: pointer to a structure that contains all low power mode parameters
+ * @return	Nothing
+ */
+static inline void Chip_LOWPOWER_SetLowPowerMode(LPC_LOWPOWER_T *p_lowpower_cfg)
+{
+    void (*p_Chip_LOWPOWER_SetLowPowerMode)(LPC_LOWPOWER_T *p_lowpower_cfg);
+    p_Chip_LOWPOWER_SetLowPowerMode = (void (*)(LPC_LOWPOWER_T *p_lowpower_cfg))0x0300404dU;
+
+    p_Chip_LOWPOWER_SetLowPowerMode(p_lowpower_cfg);
+}
+
+/**
+ * @brief	Perform a Full chip reset using Software reset bit in PMC
+ *
+ *  Power down the flash then perform the full chip reset as POR or Watchdog do,
+ *  The reset includes JTAG debugger, Digital units and Analog modules.
+ *  Use the Software reset bit in PMC
+ *
+ * @return	Nothing
+ */
+static inline void Chip_LOWPOWER_ChipSoftwareReset(void)
+{
+    void (*p_Chip_LOWPOWER_ChipSoftwareReset)(void);
+    p_Chip_LOWPOWER_ChipSoftwareReset = (void (*)(void))0x03003fa1U;
+
+    p_Chip_LOWPOWER_ChipSoftwareReset();
+}
+
+/**
+ * @brief	Perform a digital System reset
+ *
+ *  Power down the flash then perform the Full chip reset as POR or Watchdog,
+ *  The reset includes the digital units but excludes the JTAG debugger, and the analog modules.
+ *  Use the system reset bit in PMC and ARM reset
+ *
+ * @return	Nothing
+ */
+static inline void Chip_LOWPOWER_ArmSoftwareReset(void)
+{
+    void (*p_Chip_LOWPOWER_ArmSoftwareReset)(void);
+    p_Chip_LOWPOWER_ArmSoftwareReset = (void (*)(void))0x0300400dU;
+
+    p_Chip_LOWPOWER_ArmSoftwareReset();
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LOWPOWER_JN518X_H_ */