diff --git a/.travis/script.sh b/.travis/script.sh index bb1c7c4fa..453840d5c 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -128,17 +128,6 @@ build_cc2652() { arm-none-eabi-size output/cc2652/bin/ot-ncp-mtd || die } -build_da15000() { - git checkout -- . || die - git clean -xfd || die - ./bootstrap || die - COMMISSIONER=1 JOINER=1 SLAAC=1 DHCP6_CLIENT=1 DHCP6_SERVER=1 DNS_CLIENT=1 make -f examples/Makefile-da15000 || die - arm-none-eabi-size output/da15000/bin/ot-cli-ftd || die - arm-none-eabi-size output/da15000/bin/ot-cli-mtd || die - arm-none-eabi-size output/da15000/bin/ot-ncp-ftd || die - arm-none-eabi-size output/da15000/bin/ot-ncp-mtd || die -} - build_emsk() { export PATH=/tmp/arc_gnu_2017.03-rc2_prebuilt_elf32_le_linux_install/bin:$PATH || die @@ -265,7 +254,6 @@ build_samr21() { build_cc2538 build_cc2650 build_cc2652 - build_da15000 build_kw41z build_nrf52811 build_nrf52840 @@ -280,7 +268,6 @@ build_samr21() { build_cc2538 build_cc2650 build_cc2652 - build_da15000 build_kw41z build_nrf52811 build_nrf52840 @@ -295,7 +282,6 @@ build_samr21() { build_cc2538 build_cc2650 build_cc2652 - build_da15000 build_kw41z build_nrf52811 build_nrf52840 @@ -312,7 +298,6 @@ build_samr21() { build_cc2538 build_cc2650 build_cc2652 - build_da15000 build_kw41z build_nrf52811 build_nrf52840 @@ -332,13 +317,6 @@ build_samr21() { build_nrf52840 build_qpg6095 build_samr21 - - # DA15000 build failure: - # - # third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c:399:99: \ - # error: bitwise comparison always evaluates to false [-Werror=tautological-compare] - # - # build_da15000 } [ $BUILD_TARGET != posix ] || { diff --git a/README.md b/README.md index be663123e..ff24d8c92 100644 --- a/README.md +++ b/README.md @@ -35,7 +35,7 @@ More information about Thread can be found at [threadgroup.org](http://threadgro # Who supports OpenThread? -ARMCascodaDialogMicrosoftNestNordicNXPParticleQorvoQualcommSTMicroelectronicsSynopsysTexas InstrumentsZephyr Project +ARMCascodaMicrosoftNestNordicNXPParticleQorvoQualcommSTMicroelectronicsSynopsysTexas InstrumentsZephyr Project # Getting started diff --git a/configure.ac b/configure.ac index 5ce636e85..3a6c18d7f 100644 --- a/configure.ac +++ b/configure.ac @@ -1691,12 +1691,12 @@ AC_DEFINE_UNQUOTED([OPENTHREAD_ENABLE_ECDSA], [${OPENTHREAD_ENABLE_ECDSA}], [Def AC_ARG_WITH(examples, [AS_HELP_STRING([--with-examples=TARGET], - [Specify the examples from one of: none, posix, cc1352, cc2538, cc2650, cc2652, da15000, efr32, emsk, gp712, kw41z, nrf52811, nrf52840, qpg6095, samr21 @<:@default=none@:>@.])], + [Specify the examples from one of: none, posix, cc1352, cc2538, cc2650, cc2652, efr32, emsk, gp712, kw41z, nrf52811, nrf52840, qpg6095, samr21 @<:@default=none@:>@.])], [ case "${with_examples}" in none) ;; - posix|cc1352|cc2538|cc2650|cc2652|da15000|efr32|emsk|gp712|kw41z|nrf52811|nrf52840|qpg6095|samr21) + posix|cc1352|cc2538|cc2650|cc2652|efr32|emsk|gp712|kw41z|nrf52811|nrf52840|qpg6095|samr21) if test ${enable_posix_app} = "yes"; then AC_MSG_ERROR([--with-examples must be none when POSIX apps are enabled by --enable-posix-app]) fi @@ -1737,11 +1737,6 @@ case ${with_examples} in AC_DEFINE_UNQUOTED([OPENTHREAD_EXAMPLES_CC2652],[${OPENTHREAD_EXAMPLES_CC2652}],[Define to 1 if you want to use cc2652 examples]) ;; - da15000) - OPENTHREAD_EXAMPLES_DA15000=1 - AC_DEFINE_UNQUOTED([OPENTHREAD_EXAMPLES_DA15000],[${OPENTHREAD_EXAMPLES_DA15000}],[Define to 1 if you want to use da15000 examples]) - ;; - efr32) OPENTHREAD_EXAMPLES_EFR32=1 AC_DEFINE_UNQUOTED([OPENTHREAD_EXAMPLES_EFR32],[${OPENTHREAD_EXAMPLES_EFR32}],[Define to 1 if you want to use efr32 examples]) @@ -1806,9 +1801,6 @@ AM_CONDITIONAL([OPENTHREAD_EXAMPLES_CC2650], [test "${with_examples}" = "cc2650" AC_SUBST(OPENTHREAD_EXAMPLES_CC2652) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_CC2652], [test "${with_examples}" = "cc2652"]) -AC_SUBST(OPENTHREAD_EXAMPLES_DA15000) -AM_CONDITIONAL([OPENTHREAD_EXAMPLES_DA15000], [test "${with_examples}" = "da15000"]) - AC_SUBST(OPENTHREAD_EXAMPLES_EFR32) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32], [test "${with_examples}" = "efr32"]) @@ -1982,7 +1974,6 @@ examples/platforms/cc1352/Makefile examples/platforms/cc2538/Makefile examples/platforms/cc2650/Makefile examples/platforms/cc2652/Makefile -examples/platforms/da15000/Makefile examples/platforms/efr32/Makefile examples/platforms/efr32/sleepy-demo/Makefile examples/platforms/efr32/sleepy-demo/efr32-sleepy-demo-ftd/Makefile diff --git a/doc/Makefile.am b/doc/Makefile.am index c2e34b8c3..2cc0999cf 100644 --- a/doc/Makefile.am +++ b/doc/Makefile.am @@ -34,7 +34,6 @@ EXTRA_DIST = \ $(srcdir)/images/Open-Thread-Logo-200x42.png \ $(srcdir)/images/openthread_logo.png \ $(srcdir)/images/ot-contrib-arm.png \ - $(srcdir)/images/ot-contrib-dialog.png \ $(srcdir)/images/ot-contrib-ms.png \ $(srcdir)/images/ot-contrib-nest.png \ $(srcdir)/images/ot-contrib-nordic.png \ diff --git a/doc/images/ot-contrib-dialog.png b/doc/images/ot-contrib-dialog.png deleted file mode 100644 index 372617e7e..000000000 Binary files a/doc/images/ot-contrib-dialog.png and /dev/null differ diff --git a/examples/Makefile-da15000 b/examples/Makefile-da15000 deleted file mode 100644 index 8d97072c9..000000000 --- a/examples/Makefile-da15000 +++ /dev/null @@ -1,283 +0,0 @@ -# -# Copyright (c) 2016, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -.NOTPARALLEL: - -AR = arm-none-eabi-ar -AS = arm-none-eabi-as -CPP = arm-none-eabi-cpp -CC = arm-none-eabi-gcc -CXX = arm-none-eabi-g++ -LD = arm-none-eabi-ld -STRIP = arm-none-eabi-strip -NM = arm-none-eabi-nm -RANLIB = arm-none-eabi-ranlib -OBJCOPY = arm-none-eabi-objcopy - -BuildJobs ?= 10 - -configure_OPTIONS = \ - --enable-cli \ - --enable-ftd \ - --enable-mtd \ - --enable-ncp \ - --with-ncp-bus=uart \ - --enable-radio-only \ - --enable-linker-map \ - --with-examples=da15000 \ - MBEDTLS_CPPFLAGS="$(DA15000_MBEDTLS_CPPFLAGS)" \ - $(NULL) - -ifneq ($(DISABLE_BUILTIN_MBEDTLS), 1) -configure_OPTIONS += MBEDTLS_CPPFLAGS="$(DA15000_MBEDTLS_CPPFLAGS)" -endif - -TopSourceDir := $(dir $(shell readlink $(firstword $(MAKEFILE_LIST)))).. -AbsTopSourceDir := $(dir $(realpath $(firstword $(MAKEFILE_LIST)))).. - -DA15000_MBEDTLS_CPPFLAGS = -DMBEDTLS_CONFIG_FILE='\"mbedtls-config.h\"' -DA15000_MBEDTLS_CPPFLAGS += -DMBEDTLS_USER_CONFIG_FILE='\"da15000-mbedtls-config.h\"' -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/examples/platforms/da15000/crypto -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK/bsp/include -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK/bsp/peripherals/include -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK/bsp/adapters/include -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK/bsp/memory/include -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK/interfaces/ftdf/include -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK/bsp/config -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/dialog/DialogSDK/interfaces/ftdf/src -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/mbedtls/repo/include -DA15000_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/mbedtls -DA15000_MBEDTLS_CPPFLAGS += -include$(PWD)/examples/platforms/da15000/custom_config_qspi.h - -CONFIG_FILE = OPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-da15000-config.h\"' -CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/da15000/ - -COMMONCFLAGS := \ - -fdata-sections \ - -ffunction-sections \ - -Os \ - -g \ - -D$(CONFIG_FILE) \ - -I$(CONFIG_FILE_PATH) \ - $(NULL) - -include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/common-switches.mk - -CPPFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CPPFLAGS) \ - $(NULL) - -CFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CFLAGS) \ - $(NULL) - -CXXFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CXXFLAGS) \ - -fno-exceptions \ - -fno-rtti \ - $(NULL) - -LDFLAGS += \ - $(COMMONCFLAGS) \ - $(target_LDFLAGS) \ - -nostartfiles \ - -specs=nano.specs \ - -specs=nosys.specs \ - -Wl,--gc-sections \ - $(NULL) - -ECHO := @echo -MAKE := make -MKDIR_P := mkdir -p -LN_S := ln -s -RM_F := rm -f - -INSTALL := /usr/bin/install -INSTALLFLAGS := -p - -BuildPath = build -TopBuildDir = $(BuildPath) -AbsTopBuildDir = $(PWD)/$(TopBuildDir) - -ResultPath = output -TopResultDir = $(ResultPath) -AbsTopResultDir = $(PWD)/$(TopResultDir) - -TargetTuple = da15000 - -ARCHS = cortex-m0 - -TopTargetLibDir = $(TopResultDir)/$(TargetTuple)/lib - -ifndef BuildJobs -BuildJobs := $(shell getconf _NPROCESSORS_ONLN) -endif -JOBSFLAG := -j$(BuildJobs) - -# -# configure-arch -# -# Configure OpenThread for the specified architecture. -# -# arch - The architecture to configure. -# -define configure-arch -$(ECHO) " CONFIG $(TargetTuple)..." -(cd $(BuildPath)/$(TargetTuple) && $(AbsTopSourceDir)/configure \ -INSTALL="$(INSTALL) $(INSTALLFLAGS)" \ -CPP="$(CPP)" CC="$(CC)" CXX="$(CXX)" OBJC="$(OBJC)" OBJCXX="$(OBJCXX)" AR="$(AR)" RANLIB="$(RANLIB)" NM="$(NM)" STRIP="$(STRIP)" CPPFLAGS="$(CPPFLAGS)" CFLAGS="$(CFLAGS)" CXXFLAGS="$(CXXFLAGS)" LDFLAGS="$(LDFLAGS)" \ ---host=arm-none-eabi \ ---prefix=/ \ ---exec-prefix=/$(TargetTuple) \ -$(configure_OPTIONS)) -endef # configure-arch - -# -# build-arch -# -# Build the OpenThread intermediate build products for the specified -# architecture. -# -# arch - The architecture to build. -# -define build-arch -$(ECHO) " BUILD $(TargetTuple)" -$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \ -all -endef # build-arch - -# -# stage-arch -# -# Stage (install) the OpenThread final build products for the specified -# architecture. -# -# arch - The architecture to stage. -# -define stage-arch -$(ECHO) " STAGE $(TargetTuple)" -$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \ -DESTDIR=$(AbsTopResultDir) \ -install -endef # stage-arch - -# -# ARCH_template -# -# Define macros, targets and rules to configure, build, and stage the -# OpenThread for a single architecture. -# -# arch - The architecture to instantiate the template for. -# -define ARCH_template -CONFIGURE_TARGETS += configure-$(1) -BUILD_TARGETS += do-build-$(1) -STAGE_TARGETS += stage-$(1) -BUILD_DIRS += $(BuildPath)/$(TargetTuple) -DIRECTORIES += $(BuildPath)/$(TargetTuple) - -configure-$(1): target_CPPFLAGS=$($(1)_target_CPPFLAGS) -configure-$(1): target_CFLAGS=$($(1)_target_CFLAGS) -configure-$(1): target_CXXFLAGS=$($(1)_target_CXXFLAGS) -configure-$(1): target_LDFLAGS=$($(1)_target_LDFLAGS) - -configure-$(1): $(BuildPath)/$(TargetTuple)/config.status - -$(BuildPath)/$(TargetTuple)/config.status: | $(BuildPath)/$(TargetTuple) - $$(call configure-arch,$(1)) - -do-build-$(1): configure-$(1) - -do-build-$(1): - +$$(call build-arch,$(1)) - -stage-$(1): do-build-$(1) - -stage-$(1): | $(TopResultDir) - $$(call stage-arch,$(1)) - -$(1): stage-$(1) -endef # ARCH_template - -.DEFAULT_GOAL := all - -all: stage - -# -# cortex-m0 -# - -cortex-m0_target_ABI = cortex-m0 -cortex-m0_target_CPPFLAGS = -mcpu=cortex-m0 -mfloat-abi=soft -mthumb -cortex-m0_target_CFLAGS = -mcpu=cortex-m0 -mfloat-abi=soft -mthumb -cortex-m0_target_CXXFLAGS = -mcpu=cortex-m0 -mfloat-abi=soft -mthumb -cortex-m0_target_LDFLAGS = -mcpu=cortex-m0 -mfloat-abi=soft -mthumb - -# Instantiate an architecture-specific build template for each target -# architecture. - -$(foreach arch,$(ARCHS),$(eval $(call ARCH_template,$(arch)))) - -# -# Common / Finalization -# - -configure: $(CONFIGURE_TARGETS) - -build: $(BUILD_TARGETS) - -stage: $(STAGE_TARGETS) - -DIRECTORIES = $(TopResultDir) $(TopResultDir)/$(TargetTuple)/lib $(BUILD_DIRS) - -CLEAN_DIRS = $(TopResultDir) $(BUILD_DIRS) - -all: stage - -$(DIRECTORIES): - $(ECHO) " MKDIR $@" - @$(MKDIR_P) "$@" - -clean: - $(ECHO) " CLEAN" - @$(RM_F) -r $(CLEAN_DIRS) - -help: - $(ECHO) "Simply type 'make -f $(firstword $(MAKEFILE_LIST))' to build OpenThread for the following " - $(ECHO) "architectures: " - $(ECHO) "" - $(ECHO) " $(ARCHS)" - $(ECHO) "" - $(ECHO) "To build only a particular architecture, specify: " - $(ECHO) "" - $(ECHO) " make -f $(firstword $(MAKEFILE_LIST)) " - $(ECHO) "" diff --git a/examples/platforms/Makefile.am b/examples/platforms/Makefile.am index 8ba21e8d8..7a1e05569 100644 --- a/examples/platforms/Makefile.am +++ b/examples/platforms/Makefile.am @@ -35,7 +35,6 @@ DIST_SUBDIRS = \ cc2538 \ cc2650 \ cc2652 \ - da15000 \ efr32 \ emsk \ gp712 \ @@ -70,10 +69,6 @@ if OPENTHREAD_EXAMPLES_CC2652 SUBDIRS += cc2652 endif -if OPENTHREAD_EXAMPLES_DA15000 -SUBDIRS += da15000 -endif - if OPENTHREAD_EXAMPLES_EFR32 SUBDIRS += efr32 endif @@ -121,7 +116,6 @@ PRETTY_SUBDIRS = \ cc2538 \ cc2650 \ cc2652 \ - da15000 \ efr32 \ emsk \ gp712 \ diff --git a/examples/platforms/Makefile.platform.am b/examples/platforms/Makefile.platform.am index 021fab2c3..279d66211 100644 --- a/examples/platforms/Makefile.platform.am +++ b/examples/platforms/Makefile.platform.am @@ -57,10 +57,6 @@ if OPENTHREAD_EXAMPLES_CC2652 include $(top_srcdir)/examples/platforms/cc2652/Makefile.platform.am endif -if OPENTHREAD_EXAMPLES_DA15000 -include $(top_srcdir)/examples/platforms/da15000/Makefile.platform.am -endif - if OPENTHREAD_EXAMPLES_EFR32 include $(top_srcdir)/examples/platforms/efr32/Makefile.platform.am endif diff --git a/examples/platforms/da15000/Makefile.am b/examples/platforms/da15000/Makefile.am deleted file mode 100755 index 71842399a..000000000 --- a/examples/platforms/da15000/Makefile.am +++ /dev/null @@ -1,121 +0,0 @@ -# -# Copyright (c) 2016, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -include $(abs_top_nlbuild_autotools_dir)/automake/pre.am - -lib_LIBRARIES = libopenthread-da15000.a - -# Do not enable -pedantic-errors -override CFLAGS := $(filter-out -pedantic-errors,$(CFLAGS)) -override CXXFLAGS := $(filter-out -pedantic-errors,$(CXXFLAGS)) - -libopenthread_da15000_a_CPPFLAGS = \ - -I$(top_srcdir)/include \ - -I$(top_srcdir)/examples/platforms \ - -I$(top_srcdir)/examples/platforms/da15000 \ - -I$(top_srcdir)/examples/platforms/da15000/crypto \ - -I$(top_srcdir)/src/core \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/config \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/memory/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/osal \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/peripherals/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/include \ - -I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/src \ - -I$(top_srcdir)/third_party/mbedtls/repo/include \ - -include$(top_srcdir)/examples/platforms/da15000/custom_config_qspi.h \ - -Wno-sign-compare \ - -Wno-unused-parameter \ - -Wno-type-limits \ - -Wno-unused-variable \ - -Wno-missing-field-initializers \ - -fno-strict-aliasing \ - $(MBEDTLS_CPPFLAGS) \ - $(NULL) - -PLATFORM_SOURCES = \ - alarm.c \ - flash.c \ - logging.c \ - misc.c \ - radio.c \ - random.c \ - system.c \ - uart.c \ - crypto/aes_alt.c \ - $(NULL) - -DIALOG_SOURCES = \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/config.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c \ - @top_builddir@/third_party/dialog/DialogSDK/bsp/startup/vector_table.S \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c \ - @top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c \ - $(NULL) - -libopenthread_da15000_a_SOURCES = \ - $(PLATFORM_SOURCES) \ - $(DIALOG_SOURCES) \ - $(NULL) - -noinst_HEADERS = \ - custom_config_qspi.h \ - platform-da15000.h \ - $(NULL) - -PRETTY_FILES = \ - $(PLATFORM_SOURCES) \ - $(noinst_HEADERS) \ - $(NULL) - -Dash = - -libopenthread_da15000_a_LIBADD = \ - $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o") - -include $(abs_top_nlbuild_autotools_dir)/automake/post.am diff --git a/examples/platforms/da15000/Makefile.platform.am b/examples/platforms/da15000/Makefile.platform.am deleted file mode 100644 index 0bb1e66d1..000000000 --- a/examples/platforms/da15000/Makefile.platform.am +++ /dev/null @@ -1,39 +0,0 @@ -# -# Copyright (c) 2017, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -# -# da15000 platform-specific Makefile -# - -LDADD_COMMON += \ - $(top_builddir)/examples/platforms/da15000/libopenthread-da15000.a \ - $(NULL) - -LDFLAGS_COMMON += \ - -T $(top_srcdir)/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld \ - $(NULL) diff --git a/examples/platforms/da15000/README.md b/examples/platforms/da15000/README.md deleted file mode 100755 index b2bf70919..000000000 --- a/examples/platforms/da15000/README.md +++ /dev/null @@ -1,146 +0,0 @@ -# Dialog OpenThread DA15000 Example - -This directory contains example platform drivers for the [Dialog Semiconductor DA15000][da15000] - -[da15000]: https://support.dialog-semiconductor.com/connectivity/product/openthread-sandbox - -**NOTE:** Each Thread node requires a unique EUI-64. -Please make sure all Thread nodes in your network have a unique EUI-64 by setting HARDCODED_NODE_ID in radio.c to a unique value. - -**NOTE:** Current version works only with DA15000 - -## Toolchain - -Download and install the [GNU toolchain for ARM -Cortex-M][gnu-toolchain]. - -[gnu-toolchain]: https://launchpad.net/gcc-arm-embedded - -In a Bash terminal, follow these instructions to install the GNU toolchain and -other dependencies. - -```bash -$ cd -$ ./script/bootstrap -``` - -## Build Examples (How to build and flash): -```bash -$ cd -$ ./bootstrap -$ make -f examples/Makefile-da15000 clean -$ make -f examples/Makefile-da15000 -``` - -Execute script to prepare image for flashing: - -**NOTE:** Script is based on Dialog Tools binaries compiled for x86 Linux. - -```bash -$ cd ./third_party/dialog/DialogTools -$ ./imgprep.sh -``` - -Flash Binaries: - -**NOTE:** Flashing process requires JLinkGDBServer. Please visit https://www.segger.com/jlink-gdb-server.html for details. - -1. Open another terminal window in order to start gdb server. Write the command (Linux): - - ```bash - $ JLinkGDBServer -ir -if swd -speed auto -device Cortex-M0 -logtofile on -localhostonly - ``` -2. Return to previous terminal window and execute a command in order to flash the board: - - ```bash - $ ./cli_programmer gdbserver write_qspi_exec ../../../output/da15000/bin/ot-cli-ftd.bin - ``` - -## Interact: - -Board will indicate state of device according to LED blink speed. - -| Frequency | Role | -| --- | --- | -| 5Hz | Leader | -| 2Hz | Router | -| 0.5Hz | End Device | - - -1. Open terminal to /dev/ttyACM0 (serial port settings: 115200 8-N-1). -2. Type help for list of commands - -## Examples: -1. Create Topology and become Leader on channel 13. - ``` - > channel 13 - Done - > panid 0xface - Done - > ifconfig up - Done - > thread start - Done - ``` - Wait and see that LED started to blink with 5Hz. - - Check node state: - ``` - > state - Leader - ``` -2. Attach Router and ping Leader Mesh Local address. - - Open terminal for second device /dev/ttyACM1 and issue commands: - ``` - > channel 13 - Done - > panid 0xface - Done - > ifconfig up - Done - > thread start - ``` - - Wait until LED start to blink. Should blink slower. - - Check node state: - - ``` - > state - Router - ``` - - List addresses on terminal with Leader: - - ``` - > ipaddr - fdde:ad00:beef:0:0:ff:fe00:4400 - fdde:ad00:beef:0:92f5:9844:67ad:a0c9 - fe80:0:0:0:2c11:aba1:ecc1:96da - ``` - - Ping Leader from Router terminal: - - ``` - > ping fdde:ad00:beef:0:92f5:9844:67ad:a0c9 - 16 bytes from fdde:ad00:beef:0:92f5:9844:67ad:a0c9: icmp_seq=2 hlim=64 time=359ms - ``` - -## Remarks -* Validation - - The DA15000 example has been validated by Dialog Semiconductor with commit 1f6528e included. - -* Build environment - - The DA15000 example code and all required dependencies have been complied with gcc version 5.4.0 (20160609). - -## Troubleshooting -* Why can’t I see the VCOM port? - - The Segger Virtual COM port can be disabled by software configuration. If you can see the Segger - driver properly installed but the VCOM not showing up in the device manager, it’s probably disabled - by software. To re-enable it you have to run JLinkExe and issue the command ` vcom enable`.It is - required to power cycle the device to apply the change. - diff --git a/examples/platforms/da15000/alarm.c b/examples/platforms/da15000/alarm.c deleted file mode 100644 index e7ded312e..000000000 --- a/examples/platforms/da15000/alarm.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file alarm.c - * Platform abstraction for the alarm - */ - -#include - -#include "platform-da15000.h" - -#include "hw_timer0.h" - -static bool sIsRunning = false; -static uint32_t sAlarm = 0; -static uint32_t sCounter; -volatile bool sAlarmFired = false; - -static void timer0_interrupt_cb(void) -{ - sCounter++; -} - -void da15000AlarmProcess(otInstance *aInstance) -{ - if ((sIsRunning) && (sAlarm <= sCounter)) - { - sIsRunning = false; - otPlatAlarmMilliFired(aInstance); - } -} - -void da15000AlarmInit(void) -{ - hw_timer0_init(NULL); - hw_timer0_set_clock_source(HW_TIMER0_CLK_SRC_FAST); - hw_timer0_set_pwm_mode(HW_TIMER0_MODE_PWM); - hw_timer0_set_fast_clock_div(HW_TIMER0_FAST_CLK_DIV_4); - hw_timer0_set_t0_reload(0x07D0, 0x07D0); - hw_timer0_register_int(timer0_interrupt_cb); - hw_timer0_set_on_clock_div(false); -} - -uint32_t otPlatAlarmMilliGetNow(void) -{ - return sCounter; -} - -void otPlatAlarmMilliStartAt(otInstance *aInstance, uint32_t t0, uint32_t dt) -{ - OT_UNUSED_VARIABLE(aInstance); - - sAlarm = t0 + dt; - sIsRunning = true; - - if (sCounter == 0) - { - hw_timer0_enable(); - } - - hw_timer0_unfreeze(); -} - -void otPlatAlarmMilliStop(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - sIsRunning = false; - hw_timer0_freeze(); -} diff --git a/examples/platforms/da15000/crypto/aes_alt.c b/examples/platforms/da15000/crypto/aes_alt.c deleted file mode 100644 index 05ca31a8a..000000000 --- a/examples/platforms/da15000/crypto/aes_alt.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "aes_alt.h" - -#ifdef MBEDTLS_AES_ALT - -#include -#include - -#include - -#include "hw_aes_hash.h" -#include -#include "mbedtls/aes.h" - -static void mbedtls_zeroize(void *v, size_t n) -{ - volatile unsigned char *p = (unsigned char *)v; - - while (n--) - { - *p++ = 0; - } -} - -void mbedtls_aes_init(mbedtls_aes_context *ctx) -{ - memset(ctx, 0, sizeof(mbedtls_aes_context)); -} - -void mbedtls_aes_free(mbedtls_aes_context *ctx) -{ - if (ctx == NULL) - { - return; - } - - hw_aes_hash_disable_clock(); - mbedtls_zeroize(ctx, sizeof(mbedtls_aes_context)); -} - -int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) -{ - int retval = 0; - - switch (keybits) - { - case 128: - ctx->hwKeyLen = HW_AES_128; - memcpy(ctx->aes_enc_key, key, 16); - break; - - case 192: - ctx->hwKeyLen = HW_AES_192; - memcpy(ctx->aes_enc_key, key, 24); - break; - - case 256: - ctx->hwKeyLen = HW_AES_256; - memcpy(ctx->aes_enc_key, key, 32); - break; - - default: - retval = MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; - break; - } - - return retval; -} - -int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) -{ - int retval = 0; - - switch (keybits) - { - case 128: - ctx->hwKeyLen = HW_AES_128; - memcpy(ctx->aes_dec_key, key, 16); - break; - - case 192: - ctx->hwKeyLen = HW_AES_192; - memcpy(ctx->aes_enc_key, key, 24); - break; - - case 256: - ctx->hwKeyLen = HW_AES_256; - memcpy(ctx->aes_enc_key, key, 32); - break; - - default: - retval = MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; - break; - } - - return retval; -} - -/** - * \brief AES-ECB block encryption/decryption - * - * \param ctx AES context - * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT - * \param input 16-byte input block - * \param output 16-byte output block - * - * \return 0 if successful - */ -int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16]) -{ - int retval = 0; - - hw_aes_hash_enable_clock(); - hw_aes_hash_mark_input_block_as_last(); - hw_aes_hash_cfg_aes_ecb(ctx->hwKeyLen); - hw_aes_hash_store_keys(ctx->hwKeyLen, ctx->aes_enc_key, HW_AES_PERFORM_KEY_EXPANSION); - hw_aes_hash_cfg_dma((uint8_t *)input, (uint8_t *)output, 16); - - switch (mode) - { - case MBEDTLS_AES_ENCRYPT: - hw_aes_hash_encrypt(); - retval = 0; - break; - - case MBEDTLS_AES_DECRYPT: - hw_aes_hash_decrypt(); - retval = 0; - break; - - default: - retval = -1; - break; - } - - while (hw_aes_hash_is_active()) - { - ; - } - - return retval; -} - -int mbedtls_aes_self_test(int verbose) -{ - OT_UNUSED_VARIABLE(verbose); - - /* 128-bit Key 2b7e151628aed2a6abf7158809cf4f3c */ - const uint8_t key_128b[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, - 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; - - int retval = 0; - mbedtls_aes_context aes; - uint8_t input[16] = {0}; - uint8_t output[16] = {0}; - uint8_t decrypt[16] = {0}; - - strcpy((char *)input, (const char *)"hw_aes_test"); - - mbedtls_aes_init(&aes); - - retval = mbedtls_aes_setkey_enc(&aes, (const unsigned char *)key_128b, 128); - VerifyOrExit(retval != 0, retval = -1); - - retval = mbedtls_aes_setkey_dec(&aes, (const unsigned char *)key_128b, 128); - VerifyOrExit(retval != 0, retval = -1); - - retval = mbedtls_aes_crypt_ecb(&aes, MBEDTLS_AES_ENCRYPT, input, output); - VerifyOrExit(retval != 0, retval = -1); - - retval = mbedtls_aes_crypt_ecb(&aes, MBEDTLS_AES_DECRYPT, output, decrypt); - VerifyOrExit(retval != 0, retval = -1); - - mbedtls_aes_free(&aes); - -exit: - return retval; -} - -#endif /* MBEDTLS_AES_ALT */ diff --git a/examples/platforms/da15000/crypto/aes_alt.h b/examples/platforms/da15000/crypto/aes_alt.h deleted file mode 100644 index 79a872fb0..000000000 --- a/examples/platforms/da15000/crypto/aes_alt.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef MBEDTLS_AES_ALT_H -#define MBEDTLS_AES_ALT_H - -#if !defined(MBEDTLS_CONFIG_FILE) -#include "da15000-mbedtls-config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#ifdef MBEDTLS_AES_ALT - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct -{ - uint8_t hwKeyLen; - unsigned char aes_enc_key[32]; /* Encryption key */ - unsigned char aes_dec_key[32]; /* Decryption key */ -} mbedtls_aes_context; - -/** - * @brief Initialize AES context - * - * @param [in,out] ctx AES context to be initialized - */ -void mbedtls_aes_init(mbedtls_aes_context *ctx); - -/** - * @brief Clear AES context - * - * \param ctx AES context to be cleared - */ -void mbedtls_aes_free(mbedtls_aes_context *ctx); - -/** - * \brief AES key schedule (encryption) - * - * \param ctx AES context to be initialized - * \param key encryption key - * \param keybits must be 128, 192 or 256 - * - * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH - */ -int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits); - -/** - * \brief AES key schedule (decryption) - * - * \param ctx AES context to be initialized - * \param key decryption key - * \param keybits must be 128, 192 or 256 - * - * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH - */ -int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits); - -/** - * \brief AES-ECB block encryption/decryption - * - * \param ctx AES context - * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT - * \param input 16-byte input block - * \param output 16-byte output block - * - * \return 0 if successful - */ -int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, int mode, const unsigned char input[16], - unsigned char output[16]); - -/** - * \brief AES-CBC buffer encryption/decryption - * Length should be a multiple of the block - * size (16 bytes) - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx AES context - * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH - */ -int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); - -/** - * \brief AES-CTR buffer encryption/decryption - * - * Warning: You have to keep the maximum use of your counter in mind! - * - * Note: Due to the nature of CTR you should use the same key schedule for - * both encryption and decryption. So a context initialized with - * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. - * - * \param ctx AES context - * \param length The length of the data - * \param nc_off The offset in the current stream_block (for resuming - * within current cipher stream). The offset pointer to - * should be 0 at the start of a stream. - * \param nonce_counter The 128-bit nonce and counter. - * \param stream_block The saved stream-block for resuming. Is overwritten - * by the function. - * \param input The input data stream - * \param output The output data stream - * - * \return 0 if successful - */ -int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_AES_ALT */ - -#endif /* MBEDTLS_AES_ALT_H */ diff --git a/examples/platforms/da15000/crypto/da15000-mbedtls-config.h b/examples/platforms/da15000/crypto/da15000-mbedtls-config.h deleted file mode 100644 index c929beccd..000000000 --- a/examples/platforms/da15000/crypto/da15000-mbedtls-config.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2018, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DA15000_MBEDTLS_CONFIG_H -#define DA15000_MBEDTLS_CONFIG_H - -#define MBEDTLS_AES_ALT - -#endif // DA15000_MBEDTLS_CONFIG_H diff --git a/examples/platforms/da15000/custom_config_qspi.h b/examples/platforms/da15000/custom_config_qspi.h deleted file mode 100755 index cd4b93f35..000000000 --- a/examples/platforms/da15000/custom_config_qspi.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file custom_config_qspi.h - * Board Support Package. User Configuration file for cached QSPI mode. - */ - -#ifndef CUSTOM_CONFIG_QSPI_H_ -#define CUSTOM_CONFIG_QSPI_H_ - -#include "bsp_definitions.h" - -// clang-format off - -#define dg_configBLACK_ORCA_IC_REV BLACK_ORCA_IC_REV_B -#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_B - -#undef CONFIG_USE_BLE -#define CONFIG_USE_FTDF - -#define __HEAP_SIZE 0x0600 -#define __STACK_SIZE 0x0100 - -#define dg_configUSE_LP_CLK LP_CLK_32768 -#define dg_configEXEC_MODE MODE_IS_CACHED -#define dg_configCODE_LOCATION NON_VOLATILE_IS_FLASH -#define dg_configEXT_CRYSTAL_FREQ EXT_CRYSTAL_IS_16M - -#define dg_configIMAGE_SETUP DEVELOPMENT_MODE -#define dg_configEMULATE_OTP_COPY (0) - -#define dg_configUSER_CAN_USE_TIMER1 (0) - -#define dg_configUSE_WDOG (0) - -#define dg_configFLASH_CONNECTED_TO (FLASH_CONNECTED_TO_1V8) -#define dg_configFLASH_POWER_DOWN (0) - -#define dg_configPOWER_1V8_ACTIVE (1) -#define dg_configPOWER_1V8_SLEEP (1) - -#define dg_configBATTERY_TYPE (BATTERY_TYPE_LIMN2O4) -#define dg_configBATTERY_CHARGE_CURRENT 2 // 30mA -#define dg_configBATTERY_PRECHARGE_CURRENT 20 // 2.1mA -#define dg_configBATTERY_CHARGE_NTC 1 // disabled - -#define dg_configUSE_USB 0 -#define dg_configUSE_USB_CHARGER 0 -#define dg_configALLOW_CHARGING_NOT_ENUM 1 - -#define dg_configUSE_ProDK (1) - -#define dg_configUSE_SW_CURSOR (1) - -#define dg_configDISABLE_BACKGROUND_FLASH_OPS (1) - -/*************************************************************************************************\ - * Memory layout specific config - */ -#define dg_configQSPI_CODE_SIZE (512 * 1024) - -/*************************************************************************************************\ - * FTDF specific config - */ -#define FTDF_NO_CSL /* Define this to disable CSL mode */ -#define FTDF_NO_TSCH /* Define this to disable TSCH mode */ -#define FTDF_LITE /* Define this to enable LITE mode (only transparent mode enabled) */ -#define FTDF_PHY_API /* Define this to enable PHY API mode (no FTDF adapter; - implies FTDF_LITE) */ -#define FTDF_PASS_ACK_FRAME /* Define this to pass ACK frame */ - -/*************************************************************************************************\ - * OS specific config - */ -#define OS_BAREMETAL - -/*************************************************************************************************\ - * Peripheral specific config - */ -#define dg_configRF_ENABLE_RECALIBRATION (0) - -#define dg_configUSE_HW_AES_HASH (1) -#define dg_configUSE_HW_TIMER0 (1) -#define dg_configUSE_HW_TRNG (1) - -#define dg_configFLASH_ADAPTER (0) -#define dg_configRF_ADAPTER (0) -#define dg_configUART_SOFTWARE_FIFO (1) -#define dg_configUART2_SOFTWARE_FIFO_SIZE (256) - -#define dg_configNVMS_ADAPTER (0) -#define dg_configNVMS_VES (0) - -/* Include bsp default values */ -#include "bsp_defaults.h" - -// clang-format on - -#endif /* CUSTOM_CONFIG_QSPI_H_ */ diff --git a/examples/platforms/da15000/flash.c b/examples/platforms/da15000/flash.c deleted file mode 100644 index a385cf326..000000000 --- a/examples/platforms/da15000/flash.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "platform-da15000.h" - -#include "qspi_automode.h" - -#define FLASH_BUFFER_SIZE 0x2000 -#define FLASH_SECTOR_SIZE 0x1000 -#define FLASH_PAGE_SIZE 0x0100 - -/* - * In case that user tries to write data to flash passing as source QSPI mapped flash address - * data must be first copied to RAM as during write QSPI controller can't read flash. - * To achieve this, small on stack buffer will be used to copy data to RAM first. - * This define specifies how much stack can be used for this purpose. - */ -#define ON_STACK_BUFFER_SIZE 16 - -otError utilsFlashInit(void) -{ - return OT_ERROR_NONE; -} - -uint32_t utilsFlashGetSize(void) -{ - return (uint32_t)FLASH_BUFFER_SIZE; -} - -otError utilsFlashErasePage(uint32_t aAddress) -{ - uint32_t flash_offset = aAddress & ~(FLASH_SECTOR_SIZE - 1); - - qspi_automode_erase_flash_sector(flash_offset); - - CACHE->CACHE_CTRL1_REG = CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk; - - return OT_ERROR_NONE; -} - -otError utilsFlashStatusWait(uint32_t aTimeout) -{ - OT_UNUSED_VARIABLE(aTimeout); - - return OT_ERROR_NONE; -} - -static inline bool FlashQspiAddress(const void *aBuf) -{ - if (((uint32_t)aBuf >= MEMORY_QSPIF_BASE) && ((uint32_t)aBuf < MEMORY_QSPIF_END)) - { - return true; - } - - return ((uint32_t)aBuf >= MEMORY_REMAPPED_BASE) && ((uint32_t)aBuf < MEMORY_REMAPPED_END) && - (REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0) == 2); -} - -static size_t FlashWriteFromQspi(uint32_t aAddress, const uint8_t *aQspiBuf, size_t aSize) -{ - size_t written; - size_t offset = 0; - uint8_t buf[ON_STACK_BUFFER_SIZE]; - - /* - * qspi_automode_write_flash_page can't write data if source address points to QSPI mapped - * memory. To write data from QSPI flash, it will be first copied to small on stack - * buffer. This buffer can be accessed when QSPI controller is working in manual mode. - */ - while (offset < aSize) - { - size_t chunk = sizeof(buf) > aSize - offset ? aSize - offset : sizeof(buf); - memcpy(buf, aQspiBuf + offset, chunk); - - written = qspi_automode_write_flash_page(aAddress + offset, buf, chunk); - offset += written; - } - - return offset; -} - -uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize) -{ - size_t written; - size_t offset = 0; - bool buf_from_flash = FlashQspiAddress(aData); - - while (offset < aSize) - { - /* - * If buf is QSPI Flash memory, use function that will copy source data to RAM - * first. - */ - if (buf_from_flash) - { - written = FlashWriteFromQspi(aAddress + offset, aData + offset, aSize - offset); - } - else - { - /* - * Try write everything, lower driver will reduce this value to accommodate - * page boundary and and maximum write size limitation - */ - written = qspi_automode_write_flash_page(aAddress + offset, aData + offset, aSize - offset); - } - - offset += written; - } - - CACHE->CACHE_CTRL1_REG = CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk; - - return aSize; -} - -uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize) -{ - return qspi_automode_read(aAddress, aData, aSize); - ; -} diff --git a/examples/platforms/da15000/logging.c b/examples/platforms/da15000/logging.c deleted file mode 100644 index 4d3023e46..000000000 --- a/examples/platforms/da15000/logging.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file logging.c - * Platform abstraction for the logging - * - */ - -#include -#include -#include -#include - -#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED) || \ - (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_NCP_SPINEL) -OT_TOOL_WEAK void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, ...) -{ - OT_UNUSED_VARIABLE(aLogLevel); - OT_UNUSED_VARIABLE(aLogRegion); - OT_UNUSED_VARIABLE(aFormat); -} -#endif diff --git a/examples/platforms/da15000/misc.c b/examples/platforms/da15000/misc.c deleted file mode 100644 index e324f8efc..000000000 --- a/examples/platforms/da15000/misc.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include "platform-da15000.h" - -#include "hw_cpm.h" -#include "sdk_defs.h" - -void otPlatReset(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - hw_cpm_reboot_system(); -} - -otPlatResetReason otPlatGetResetReason(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return OT_PLAT_RESET_REASON_POWER_ON; -} - -void otPlatWakeHost(void) -{ - // TODO: implement an operation to wake the host from sleep state. -} diff --git a/examples/platforms/da15000/openthread-core-da15000-config.h b/examples/platforms/da15000/openthread-core-da15000-config.h deleted file mode 100644 index 0230e5ab4..000000000 --- a/examples/platforms/da15000/openthread-core-da15000-config.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file includes DA15000 compile-time configuration constants for OpenThread. - */ - -#ifndef OPENTHREAD_CORE_DA15000_CONFIG_H_ -#define OPENTHREAD_CORE_DA15000_CONFIG_H_ - -/** - * @def OPENTHREAD_CONFIG_PLATFORM_INFO - * - * The platform-specific string to insert into the OpenThread version string. - * - */ -#define OPENTHREAD_CONFIG_PLATFORM_INFO "DA15000" - -/** - * @def SETTINGS_CONFIG_BASE_ADDRESS - * - * The base address of the pages to be used for non-volatile-settings storage. - */ -#define SETTINGS_CONFIG_BASE_ADDRESS 0x7B000 - -/** - * @def SETTINGS_CONFIG_PAGE_SIZE - * - * The page size of settings. - * - */ -#define SETTINGS_CONFIG_PAGE_SIZE 0x1000 - -/** - * @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_ACK_TIMEOUT - * - * Define to 1 if you want to enable software ACK timeout logic. - * - */ -#define OPENTHREAD_CONFIG_ENABLE_SOFTWARE_ACK_TIMEOUT 0 - -/** - * @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_RETRANSMIT - * - * Define to 1 if you want to enable software retransmission logic. - * - */ -#define OPENTHREAD_CONFIG_ENABLE_SOFTWARE_RETRANSMIT 0 - -/** - * @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_CSMA_BACKOFF - * - * Define to 1 if you want to enable software CSMA-CA backoff logic. - * - */ -#define OPENTHREAD_CONFIG_ENABLE_SOFTWARE_CSMA_BACKOFF 0 - -/** - * @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_ENERGY_SCAN - * - * Define to 1 if you want to enable software energy scanning logic. - * - */ -#define OPENTHREAD_CONFIG_ENABLE_SOFTWARE_ENERGY_SCAN 1 - -/** - * @def OPENTHREAD_CONFIG_ADDRESS_CACHE_ENTRIES - * - * The number of EID-to-RLOC cache entries. - * - */ -#define OPENTHREAD_CONFIG_ADDRESS_CACHE_ENTRIES 20 - -/** - * @def OPENTHREAD_CONFIG_LOG_OUTPUT - * - * The DA15000 platform provides an otPlatLog() function. - */ -#ifndef OPENTHREAD_CONFIG_LOG_OUTPUT /* allow command line override */ -#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_APP -#endif - -/** - * @def OPENTHREAD_CONFIG_MAX_STATECHANGE_HANDLERS - * - * The maximum number of state-changed callback handlers (set using `otSetStateChangedCallback()`). - * - */ -#define OPENTHREAD_CONFIG_MAX_STATECHANGE_HANDLERS 3 - -#endif // OPENTHREAD_CORE_DA15000_CONFIG_H_ diff --git a/examples/platforms/da15000/platform-da15000.h b/examples/platforms/da15000/platform-da15000.h deleted file mode 100644 index 6a2cfaf6c..000000000 --- a/examples/platforms/da15000/platform-da15000.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef PLATFORM_DA15000_H_ -#define PLATFORM_DA15000_H_ - -#include -#include - -#include - -/** - * This function initializes the radio service used by OpenThread. - * - */ -void da15000RadioInit(void); - -/** - * This function performs radio driver processing. - * - * @param[in] aInstance The OpenThread instance structure. - * - */ -void da15000RadioProcess(otInstance *aInstance); - -/** - * This function initializes the alarm service used by OpenThread. - * - */ -void da15000AlarmInit(void); - -/** - * This function performs alarm driver processing. - * - * @param[in] aInstance The OpenThread instance structure. - * - */ -void da15000AlarmProcess(otInstance *aInstance); - -/** - * This function initializes the random number service used by OpenThread. - * - */ -void da15000RandomInit(void); - -/** - * This function performs UART driver processing. - * - */ -void da15000UartProcess(void); - -#endif /* PLATFORM_PLATFORM_DA15000_H_ */ diff --git a/examples/platforms/da15000/radio.c b/examples/platforms/da15000/radio.c deleted file mode 100644 index dfb284c0b..000000000 --- a/examples/platforms/da15000/radio.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file radio.cpp - * Platform abstraction for radio communication. - */ - -#include -#include - -#include - -#include "platform-da15000.h" -#include "common/logging.hpp" -#include "utils/code_utils.h" - -#include "ad_ftdf.h" -#include "ad_ftdf_phy_api.h" -#include "hw_otpc.h" -#include "hw_rf.h" -#include "internal.h" - -// clang-format off -#define FACTORY_TEST_TIMESTAMP (0x7F8EA08) // Register holds a timestamp of facotry test of a chip -#define FACTORY_TESTER_ID (0x7F8EA0C) // Register holds test machine ID used for factory test - -#define RADIO_DEFAULT_CHANNEL (11) -#define RADIO_EUI64_TABLE_SIZE (8) -#define RADIO_FRAMES_BUFFER_SIZE (32) -// clang-format on - -enum -{ - DA15000_RECEIVE_SENSITIVITY = -100, // dBm -}; - -static ftdf_dbm sRssiReal = -100; // Initialize with the worst power -static otInstance * sThreadInstance; -static otRadioState sRadioState = OT_RADIO_STATE_DISABLED; -static otRadioFrame sReceiveFrame[RADIO_FRAMES_BUFFER_SIZE]; -static otRadioFrame *sReceiveFrameAck; -static otRadioFrame sTransmitFrame; -static otError sTransmitStatus; -static bool sAckFrame = false; -static bool sDropFrame = false; -static bool sRadioPromiscuous = false; -static bool sTransmitDoneFrame = false; -static uint8_t sChannel = RADIO_DEFAULT_CHANNEL; -static uint8_t sEnableRX = 0; -static int8_t sTxPower = OPENTHREAD_CONFIG_DEFAULT_TRANSMIT_POWER; -static uint8_t sReadFrame = 0; -static uint8_t sWriteFrame = 0; -static uint32_t sSleepInitDelay = 0; - -static uint8_t sEui64[RADIO_EUI64_TABLE_SIZE]; -static uint8_t sReceivePsdu[RADIO_FRAMES_BUFFER_SIZE][OT_RADIO_FRAME_MAX_SIZE]; -static uint8_t sTransmitPsdu[OT_RADIO_FRAME_MAX_SIZE]; - -static void da15000OtpRead(void) -{ - hw_otpc_init(); // Start clock. - hw_otpc_disable(); // Make sure it is in standby mode. - hw_otpc_init(); // Restart clock. - hw_otpc_manual_read_on(false); - - __DMB(); - uint32_t *factoryTestTimeStamp = (uint32_t *)FACTORY_TEST_TIMESTAMP; - uint32_t *factoryTestId = (uint32_t *)FACTORY_TESTER_ID; - __DMB(); - - sEui64[0] = 0x80; // 80-EA-CA is for Dialog Semiconductor - sEui64[1] = 0xEA; - sEui64[2] = 0xCA; - sEui64[3] = (*factoryTestId >> 8) & 0xff; - sEui64[4] = (*factoryTestTimeStamp >> 24) & 0xff; - sEui64[5] = (*factoryTestTimeStamp >> 16) & 0xff; - sEui64[6] = (*factoryTestTimeStamp >> 8) & 0xff; - sEui64[7] = *factoryTestTimeStamp & 0xff; - - hw_otpc_manual_read_off(); - hw_otpc_disable(); -} - -void da15000RadioInit(void) -{ - uint16_t ptr; - - /* Wake up power domains */ - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); - - while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) - ; - - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); - - while (REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_UP) == 0x0) - ; - - REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE, 1); - REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); - - hw_rf_poweron(); - hw_rf_system_init(); - - ad_ftdf_init_phy_api(); - - da15000OtpRead(); - - sChannel = RADIO_DEFAULT_CHANNEL; - sTransmitFrame.mPsdu = sTransmitPsdu; - - for (ptr = 0; ptr != RADIO_FRAMES_BUFFER_SIZE; ptr++) - { - sReceiveFrame[ptr].mPsdu = &sReceivePsdu[ptr][0]; - } - - otLogInfoPlat(sThreadInstance, "Radio initialized", NULL); -} - -void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) -{ - OT_UNUSED_VARIABLE(aInstance); - - memcpy(aIeeeEui64, sEui64, RADIO_EUI64_TABLE_SIZE); -} - -void otPlatRadioSetPanId(otInstance *aInstance, uint16_t aPanid) -{ - otLogInfoPlat("Set PanId: %X", aPanid); - - ftdf_set_value(FTDF_PIB_PAN_ID, &aPanid); -} - -void otPlatRadioSetExtendedAddress(otInstance *aInstance, const otExtAddress *aAddress) -{ - otLogInfoPlat("Set Extended Address: %X%X%X%X%X%X%X%X", aAddress->m8[7], aAddress->m8[6], aAddress->m8[5], - aAddress->m8[4], aAddress->m8[3], aAddress->m8[2], aAddress->m8[1], aAddress->m8[0]); - - ftdf_set_value(FTDF_PIB_EXTENDED_ADDRESS, aAddress->m8); -} - -void otPlatRadioSetShortAddress(otInstance *aInstance, uint16_t aAddress) -{ - otLogInfoPlat("Set Short Address: %X", aAddress); - - ftdf_set_value(FTDF_PIB_SHORT_ADDRESS, &aAddress); -} - -otError otPlatRadioEnable(otInstance *aInstance) -{ - ftdf_bitmap32_t options; - otError error = OT_ERROR_NONE; - uint8_t modeCCA; - - otEXPECT_ACTION(sRadioState == OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE); - - sThreadInstance = aInstance; - - sEnableRX = 1; - ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - - ftdf_set_value(FTDF_PIB_CURRENT_CHANNEL, &sChannel); - - modeCCA = FTDF_CCA_MODE_2; - ftdf_set_value(FTDF_PIB_CCA_MODE, &modeCCA); - - options = FTDF_TRANSPARENT_ENABLE_FCS_GENERATION; - options |= FTDF_TRANSPARENT_WAIT_FOR_ACK; - options |= FTDF_TRANSPARENT_AUTO_ACK; - - ftdf_enable_transparent_mode(FTDF_TRUE, options); - otPlatRadioSetPromiscuous(aInstance, false); - - otLogDebgPlat("Radio state: OT_RADIO_STATE_SLEEP", NULL); - sRadioState = OT_RADIO_STATE_SLEEP; - -exit: - return error; -} - -otError otPlatRadioDisable(otInstance *aInstance) -{ - sEnableRX = 0; - ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - ad_ftdf_sleep_when_possible(FTDF_TRUE); - - ftdf_fppr_reset(); - - otLogDebgPlat("Radio state: OT_RADIO_STATE_DISABLED", NULL); - sRadioState = OT_RADIO_STATE_DISABLED; - - return OT_ERROR_NONE; -} - -bool otPlatRadioIsEnabled(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return (sRadioState != OT_RADIO_STATE_DISABLED); -} - -otError otPlatRadioSleep(otInstance *aInstance) -{ - otError error = OT_ERROR_NONE; - - if (sRadioState == OT_RADIO_STATE_RECEIVE && sSleepInitDelay == 0) - { - sSleepInitDelay = otPlatAlarmMilliGetNow(); - return OT_ERROR_NONE; - } - else if ((otPlatAlarmMilliGetNow() - sSleepInitDelay) < dg_configINITIAL_SLEEP_DELAY_TIME) - { - return OT_ERROR_NONE; - } - - otEXPECT_ACTION(sRadioState == OT_RADIO_STATE_RECEIVE, error = OT_ERROR_INVALID_STATE); - - otLogDebgPlat("Radio state: OT_RADIO_STATE_SLEEP", NULL); - sRadioState = OT_RADIO_STATE_SLEEP; - - sEnableRX = 0; - ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - ad_ftdf_sleep_when_possible(FTDF_TRUE); - -exit: - return error; -} - -otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel) -{ - otError error = OT_ERROR_NONE; - - otEXPECT_ACTION(sRadioState != OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE); - - ad_ftdf_wake_up(); - - sEnableRX = 0; - ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - - sChannel = aChannel; - ftdf_set_value(FTDF_PIB_CURRENT_CHANNEL, &aChannel); - - sEnableRX = 1; - ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX); - - otLogDebgPlat("Radio state: OT_RADIO_STATE_RECEIVE", NULL); - sRadioState = OT_RADIO_STATE_RECEIVE; - -exit: - return error; -} - -void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aEnable); -} - -otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress) -{ - otError error = OT_ERROR_NONE; - uint8_t entry; - uint8_t entryIdx; - - // check if address already stored - otEXPECT(!ftdf_fppr_lookup_short_address(aShortAddress, &entry, &entryIdx)); - - otEXPECT_ACTION(ftdf_fppr_get_free_short_address(&entry, &entryIdx), error = OT_ERROR_NO_BUFS); - - otLogDebgPlat("Add ShortAddress entry: %d", entry); - - ftdf_fppr_set_short_address(entry, entryIdx, aShortAddress); - ftdf_fppr_set_short_address_valid(entry, entryIdx, FTDF_TRUE); - -exit: - return error; -} - -otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) -{ - otError error = OT_ERROR_NONE; - uint8_t entry; - ftdf_ext_address_t addr; - uint32_t addrL; - uint64_t addrH; - - addrL = - (aExtAddress->m8[3] << 24) | (aExtAddress->m8[2] << 16) | (aExtAddress->m8[1] << 8) | (aExtAddress->m8[0] << 0); - addrH = - (aExtAddress->m8[7] << 24) | (aExtAddress->m8[6] << 16) | (aExtAddress->m8[5] << 8) | (aExtAddress->m8[4] << 0); - addr = addrL | (addrH << 32); - - // check if address already stored - otEXPECT(!ftdf_fppr_lookup_ext_address(addr, &entry)); - - otEXPECT_ACTION(ftdf_fppr_get_free_ext_address(&entry), error = OT_ERROR_NO_BUFS); - - otLogDebgPlat("Add ExtAddress entry: %d", entry); - - ftdf_fppr_set_ext_address(entry, addr); - ftdf_fppr_set_ext_address_valid(entry, FTDF_TRUE); - -exit: - return error; -} - -otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress) -{ - otError error = OT_ERROR_NONE; - uint8_t entry; - uint8_t entryIdx; - - otEXPECT_ACTION(ftdf_fppr_lookup_short_address(aShortAddress, &entry, &entryIdx), error = OT_ERROR_NO_ADDRESS); - - otLogDebgPlat("Clear ShortAddress entry: %d", entry); - - ftdf_fppr_set_short_address(entry, entryIdx, 0); - ftdf_fppr_set_short_address_valid(entry, entryIdx, FTDF_FALSE); - -exit: - return error; -} - -otError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) -{ - otError error = OT_ERROR_NONE; - uint8_t entry; - ftdf_ext_address_t addr; - uint32_t addrL; - uint64_t addrH; - - addrL = - (aExtAddress->m8[3] << 24) | (aExtAddress->m8[2] << 16) | (aExtAddress->m8[1] << 8) | (aExtAddress->m8[0] << 0); - addrH = - (aExtAddress->m8[7] << 24) | (aExtAddress->m8[6] << 16) | (aExtAddress->m8[5] << 8) | (aExtAddress->m8[4] << 0); - addr = addrL | (addrH << 32); - - otEXPECT_ACTION(ftdf_fppr_lookup_ext_address(addr, &entry), error = OT_ERROR_NO_ADDRESS); - - otLogDebgPlat("Clear ExtAddress entry: %d", entry); - - ftdf_fppr_set_ext_address(entry, 0); - ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); - -exit: - return error; -} - -void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance) -{ - uint8_t i, j; - - otLogDebgPlat("Clear ShortAddress entries", NULL); - - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) - { - for (j = 0; j < 4; j++) - { - if (ftdf_fppr_get_short_address_valid(i, j)) - { - ftdf_fppr_set_short_address_valid(i, j, FTDF_FALSE); - } - } - } -} - -void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance) -{ - uint8_t i; - - otLogDebgPlat("Clear ExtAddress entries", NULL); - - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) - { - if (ftdf_fppr_get_ext_address_valid(i)) - { - ftdf_fppr_set_ext_address_valid(i, FTDF_FALSE); - } - } -} - -otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return &sTransmitFrame; -} - -otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) -{ - otError error = OT_ERROR_NONE; - - otEXPECT_ACTION(sRadioState != OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE); - - otLogDebgPlat("Radio start transmit: %d bytes on channel: %d", aFrame->mLength, aFrame->mChannel); - - ad_ftdf_send_frame_simple(aFrame->mLength, aFrame->mPsdu, aFrame->mChannel, 0, FTDF_TRUE); - - otLogDebgPlat("Radio state: OT_RADIO_STATE_TRANSMIT", NULL); - sRadioState = OT_RADIO_STATE_TRANSMIT; - - otPlatRadioTxStarted(aInstance, aFrame); - -exit: - return error; -} - -int8_t otPlatRadioGetRssi(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return sRssiReal; -} - -otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_TRANSMIT_RETRIES | OT_RADIO_CAPS_CSMA_BACKOFF; -} - -bool otPlatRadioGetPromiscuous(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return sRadioPromiscuous; -} - -void otPlatRadioSetPromiscuous(otInstance *aInstance, bool aEnable) -{ - otLogInfoPlat("Set Promiscuous: %d", aEnable ? 1 : 0); - - ftdf_set_value(FTDF_PIB_PROMISCUOUS_MODE, &aEnable); - sRadioPromiscuous = aEnable; -} - -otError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint16_t aScanDuration) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aScanChannel); - OT_UNUSED_VARIABLE(aScanDuration); - - return OT_ERROR_NOT_IMPLEMENTED; -} - -otError otPlatRadioGetTransmitPower(otInstance *aInstance, int8_t *aPower) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_NONE; - - otEXPECT_ACTION(aPower != NULL, error = OT_ERROR_INVALID_ARGS); - *aPower = sTxPower; - -exit: - return error; -} - -otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower) -{ - otLogInfoPlat("Set DefaultTxPower: %d", aPower); - - sTxPower = aPower; - ftdf_set_value(FTDF_PIB_TX_POWER, &aPower); - - return OT_ERROR_NONE; -} - -void da15000RadioProcess(otInstance *aInstance) -{ - ftdf_frame_header_t frameHeader; - - if (sReadFrame != sWriteFrame) - { - ftdf_get_frame_header(sReceiveFrame[sReadFrame].mPsdu, &frameHeader); - - otLogDebgPlat("Radio received: %d bytes", sReceiveFrame[sReadFrame].mLength); - - if (frameHeader.frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) - { - sReceiveFrameAck = &sReceiveFrame[sReadFrame]; - sAckFrame = true; - } - - // TODO Set this flag only when the packet is really acknowledged with frame pending set. - // See https://github.com/openthread/openthread/pull/3785 - sReceiveFrame[sReadFrame].mInfo.mRxInfo.mAckedWithFramePending = true; - - otPlatRadioReceiveDone(sThreadInstance, &sReceiveFrame[sReadFrame], OT_ERROR_NONE); - - sReadFrame = (sReadFrame + 1) % RADIO_FRAMES_BUFFER_SIZE; - sDropFrame = false; - } - - if (sTransmitDoneFrame) - { - otLogDebgPlat("Radio transmit status: %s", otThreadErrorToString(sTransmitStatus)); - - ftdf_get_frame_header(sTransmitFrame.mPsdu, &frameHeader); - - if ((frameHeader.options & FTDF_OPT_ACK_REQUESTED) == 0 || sTransmitStatus != OT_ERROR_NONE) - { - sRadioState = OT_RADIO_STATE_RECEIVE; - otPlatRadioTxDone(sThreadInstance, &sTransmitFrame, NULL, sTransmitStatus); - } - else - { - otEXPECT(sAckFrame); - sRadioState = OT_RADIO_STATE_RECEIVE; - otPlatRadioTxDone(sThreadInstance, &sTransmitFrame, sReceiveFrameAck, sTransmitStatus); - sAckFrame = false; - } - - sTransmitDoneFrame = false; - - otLogDebgPlat("Radio state: OT_RADIO_STATE_RECEIVE", NULL); - } - -exit: - return; -} - -void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status) -{ - OT_UNUSED_VARIABLE(handle); - - switch (status) - { - case FTDF_TRANSPARENT_SEND_SUCCESSFUL: - sTransmitStatus = OT_ERROR_NONE; - break; - - case FTDF_TRANSPARENT_CSMACA_FAILURE: - sTransmitStatus = OT_ERROR_CHANNEL_ACCESS_FAILURE; - break; - - case FTDF_TRANSPARENT_NO_ACK: - sTransmitStatus = OT_ERROR_NO_ACK; - break; - - default: - sTransmitStatus = OT_ERROR_ABORT; - break; - } - - sTransmitDoneFrame = true; -} - -static void radioRssiCalc(ftdf_link_quality_t link_quality) -{ - sRssiReal = (ftdf_dbm)((0.5239 * (float)link_quality) - 114.8604); -} - -void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length, - ftdf_octet_t * frame, - ftdf_bitmap32_t status, - ftdf_link_quality_t link_quality) -{ - otEXPECT(frame_length <= OT_RADIO_FRAME_MAX_SIZE); - - otEXPECT(sRadioState != OT_RADIO_STATE_DISABLED); - - otEXPECT(!sDropFrame); - - if (status == FTDF_TRANSPARENT_RCV_SUCCESSFUL) - { - radioRssiCalc(link_quality); - - if (otPlatRadioGetPromiscuous(sThreadInstance)) - { - // Timestamp - sReceiveFrame[sWriteFrame].mInfo.mRxInfo.mMsec = otPlatAlarmMilliGetNow(); - sReceiveFrame[sWriteFrame].mInfo.mRxInfo.mUsec = 0; // Don't support microsecond timer for now. - } - - sReceiveFrame[sWriteFrame].mChannel = sChannel; - sReceiveFrame[sWriteFrame].mLength = frame_length; - sReceiveFrame[sWriteFrame].mInfo.mRxInfo.mLqi = OT_RADIO_LQI_NONE; - sReceiveFrame[sWriteFrame].mInfo.mRxInfo.mRssi = otPlatRadioGetRssi(sThreadInstance); - memcpy(sReceiveFrame[sWriteFrame].mPsdu, frame, frame_length); - - sWriteFrame = (sWriteFrame + 1) % RADIO_FRAMES_BUFFER_SIZE; - - if (sWriteFrame == sReadFrame) - { - sDropFrame = true; - } - } - -exit: - return; -} - -int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - return DA15000_RECEIVE_SENSITIVITY; -} diff --git a/examples/platforms/da15000/random.c b/examples/platforms/da15000/random.c deleted file mode 100644 index bdf462c91..000000000 --- a/examples/platforms/da15000/random.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file implements true random number generator. - */ - -#include - -#include - -#include "platform-da15000.h" - -#include "hw_trng.h" -#include "sdk_defs.h" - -#define RANDOM_SIZE_OF_BUFFER 32 - -static uint32_t sRandomNumbers[RANDOM_SIZE_OF_BUFFER]; -static uint8_t sRandomNextNumberIndex = 0; -static bool sRandomGeneratorStarted = false; - -static void RandomCallback(void) -{ - hw_trng_get_numbers(sRandomNumbers, RANDOM_SIZE_OF_BUFFER); - sRandomNextNumberIndex = 0; - hw_trng_stop(); - hw_trng_disable_clk(); - hw_trng_disable_interrupt(); - sRandomGeneratorStarted = false; -} - -static void StartGenerator(void) -{ - hw_trng_enable(RandomCallback); - sRandomGeneratorStarted = true; -} - -void da15000RandomInit(void) -{ - StartGenerator(); -} - -uint32_t otPlatRandomGet(void) -{ - uint32_t randomNumber; - bool randomGet = false; - - do - { - GLOBAL_INT_DISABLE(); - - if (sRandomNextNumberIndex < RANDOM_SIZE_OF_BUFFER) - { - randomNumber = sRandomNumbers[sRandomNextNumberIndex++]; - randomGet = true; - - if (sRandomNextNumberIndex == RANDOM_SIZE_OF_BUFFER) - { - StartGenerator(); - } - } - else if (hw_trng_get_fifo_level() > 0) - { - randomNumber = hw_trng_get_number(); - randomGet = true; - } - else if (!sRandomGeneratorStarted) - { - StartGenerator(); - } - - GLOBAL_INT_RESTORE(); - } while (!randomGet); - - return randomNumber; -} - -otError otPlatRandomGetTrue(uint8_t *aOutput, uint16_t aOutputLength) -{ - uint32_t randomNumber; - - while (aOutputLength) - { - randomNumber = otPlatRandomGet(); - - if (aOutputLength < 4) - { - memcpy(aOutput, &randomNumber, aOutputLength); - aOutputLength = 0; - } - else - { - memcpy(aOutput, &randomNumber, 4); - aOutputLength -= 4; - aOutput += 4; - } - } - - return OT_ERROR_NONE; -} diff --git a/examples/platforms/da15000/system.c b/examples/platforms/da15000/system.c deleted file mode 100644 index 9a26753e6..000000000 --- a/examples/platforms/da15000/system.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file includes the platform-specific initializers. - */ - -#include -#include -#include -#include - -#include "platform-da15000.h" - -#include "hw_cpm.h" -#include "hw_gpio.h" -#include "hw_qspi.h" -#include "hw_watchdog.h" -#include "sdk_defs.h" - -static bool sBlink = false; -static int sMsCounterInit; -static int sMsCounter; - -// clang-format off -#define ALIVE_LED_PERIOD (50000) -#define ALIVE_LED_DUTY (500) -#define LEADER_BLINK_TIME (200) -#define ROUTER_BLINK_TIME (500) -#define CHILD_BLINK_TIME (2000) -// clang-format on - -static otInstance *sInstance = NULL; - -/* - * Example function. Blink LED according to node state - * Leader - 5Hz - * Router - 2Hz - * Child - 0.5Hz - */ -static void ExampleProcess(otInstance *aInstance) -{ - static int aliveLEDcounter = 0; - otDeviceRole devRole; - static int thrValue; - - devRole = otThreadGetDeviceRole(aInstance); - - if (sBlink == false && otPlatAlarmMilliGetNow() != 0) - { - sMsCounterInit = otPlatAlarmMilliGetNow(); - sBlink = true; - } - - sMsCounter = otPlatAlarmMilliGetNow() - sMsCounterInit; - - switch (devRole) - { - case OT_DEVICE_ROLE_LEADER: - thrValue = LEADER_BLINK_TIME; - break; - - case OT_DEVICE_ROLE_ROUTER: - thrValue = ROUTER_BLINK_TIME; - break; - - case OT_DEVICE_ROLE_CHILD: - thrValue = CHILD_BLINK_TIME; - break; - - default: - thrValue = 0x00; - } - - if ((thrValue != 0x00) && (sMsCounter >= thrValue)) - { - hw_gpio_toggle(HW_GPIO_PORT_1, HW_GPIO_PIN_5); - sMsCounterInit = otPlatAlarmMilliGetNow(); - } - - if (thrValue == 0) - { - // No specific role, let's generate 'alive blink' - // to inform that we are running. - // Loop counter is used to run even if timers - // are not initialized yet. - aliveLEDcounter++; - - if (aliveLEDcounter > ALIVE_LED_PERIOD) - { - aliveLEDcounter = 0; - hw_gpio_set_active(HW_GPIO_PORT_1, HW_GPIO_PIN_5); - } - - if (aliveLEDcounter > ALIVE_LED_DUTY) - { - hw_gpio_set_inactive(HW_GPIO_PORT_1, HW_GPIO_PIN_5); - } - } -} - -void otSysInit(int argc, char *argv[]) -{ - OT_UNUSED_VARIABLE(argc); - OT_UNUSED_VARIABLE(argv); - - // Initialize Random number generator - da15000RandomInit(); - // Initialize Alarm - da15000AlarmInit(); - // Initialize Radio - da15000RadioInit(); -} - -bool otSysPseudoResetWasRequested(void) -{ - return false; -} - -#if (OPENTHREAD_MTD || OPENTHREAD_FTD) && (OPENTHREAD_ENABLE_COMMISSIONER || OPENTHREAD_ENABLE_JOINER) -static sys_clk_t ClkGet(void) -{ - sys_clk_t clk = sysclk_RC16; - uint32_t hw_clk = hw_cpm_get_sysclk(); - - switch (hw_clk) - { - case SYS_CLK_IS_RC16: - clk = sysclk_RC16; - break; - - case SYS_CLK_IS_XTAL16M: - if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M) - { - clk = sysclk_XTAL16M; - } - else - { - clk = sysclk_XTAL32M; - } - - break; - - case SYS_CLK_IS_PLL: - if (hw_cpm_get_pll_divider_status() == 1) - { - clk = sysclk_PLL48; - } - else - { - clk = sysclk_PLL96; - } - - break; - - case SYS_CLK_IS_LP: - - // fall-through - - default: - ASSERT_WARNING(0); - break; - } - - return clk; -} - -static void ClkSet(sys_clk_t clock) -{ - switch (clock) - { - case sysclk_XTAL16M: - if (!hw_cpm_check_xtal16m_status()) // XTAL16M disabled - { - hw_cpm_enable_xtal16m(); // Enable XTAL16M - } - - hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M); // Set XTAL16 as sys_clk - hw_watchdog_unfreeze(); // Start watchdog - - while (!hw_cpm_is_xtal16m_started()) - ; // Block until XTAL16M starts - - hw_qspi_set_div(HW_QSPI_DIV_1); - hw_watchdog_freeze(); // Stop watchdog - hw_cpm_set_hclk_div(0); - hw_cpm_set_pclk_div(0); - break; - - case sysclk_PLL48: - if (hw_cpm_is_pll_locked() == 0) - { - hw_cpm_pll_sys_on(); // Turn on PLL - } - - hw_cpm_enable_pll_divider(); // Enable divider (div by 2) - hw_qspi_set_div(HW_QSPI_DIV_1); - hw_cpm_set_sysclk(SYS_CLK_IS_PLL); - hw_cpm_set_hclk_div(0); - hw_cpm_set_pclk_div(0); - break; - - case sysclk_PLL96: - if (hw_cpm_is_pll_locked() == 0) - { - hw_cpm_pll_sys_on(); // Turn on PLL - } - - hw_cpm_disable_pll_divider(); // Disable divider (div by 1) - hw_qspi_set_div(HW_QSPI_DIV_2); - hw_cpm_set_sysclk(SYS_CLK_IS_PLL); - hw_cpm_set_hclk_div(0); - hw_cpm_set_pclk_div(0); - break; - - default: - break; - } -} - -static void ClkChange(sys_clk_t lastClock, sys_clk_t newClock) -{ - if (ClkGet() == lastClock) - { - ClkSet(newClock); - } -} - -static void StateChangedCallback(uint32_t aFlags, void *aContext) -{ - if ((aFlags & OT_CHANGED_COMMISSIONER_STATE) != 0) - { - if (otCommissionerGetState(sInstance) == OT_COMMISSIONER_STATE_ACTIVE) - { - ClkChange(sysclk_XTAL16M, sysclk_PLL96); - } - else - { - ClkChange(sysclk_PLL96, sysclk_XTAL16M); - } - } - - if ((aFlags & OT_CHANGED_JOINER_STATE) != 0) - { - if (otJoinerGetState(sInstance) != OT_JOINER_STATE_IDLE) - { - ClkChange(sysclk_XTAL16M, sysclk_PLL96); - } - else - { - ClkChange(sysclk_PLL96, sysclk_XTAL16M); - } - } -} -#endif // (OPENTHREAD_MTD || OPENTHREAD_FTD) && (OPENTHREAD_ENABLE_COMMISSIONER || OPENTHREAD_ENABLE_JOINER) - -void otSysProcessDrivers(otInstance *aInstance) -{ - if (sInstance == NULL) - { - sInstance = aInstance; -#if (OPENTHREAD_MTD || OPENTHREAD_FTD) && (OPENTHREAD_ENABLE_COMMISSIONER || OPENTHREAD_ENABLE_JOINER) - otSetStateChangedCallback(aInstance, StateChangedCallback, 0); -#endif // (OPENTHREAD_MTD || OPENTHREAD_FTD) && (OPENTHREAD_ENABLE_COMMISSIONER || OPENTHREAD_ENABLE_JOINER) - } - - da15000UartProcess(); - da15000RadioProcess(aInstance); - da15000AlarmProcess(aInstance); - ExampleProcess(aInstance); -} diff --git a/examples/platforms/da15000/uart.c b/examples/platforms/da15000/uart.c deleted file mode 100644 index ae0c4a2f9..000000000 --- a/examples/platforms/da15000/uart.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include "platform-da15000.h" - -#include "hw_gpio.h" -#include "hw_uart.h" - -static bool sUartWriteDone = false; -static bool sUartReadDone = false; -static char * sInitBuf = NULL; -static uint8_t sUartBuf; - -static void UartSignalWrite(void *p, uint16_t transferred) -{ - if (transferred) - { - sUartWriteDone = true; - } -} - -static void UartSignalRead(void *p, uint16_t transferred) -{ - if (transferred) - { - sUartReadDone = true; - } -} - -otError otPlatUartEnable(void) -{ - // clang-format off - uart_config_ex uart_init = - { - .baud_rate = HW_UART_BAUDRATE_115200, - .data = HW_UART_DATABITS_8, - .parity = HW_UART_PARITY_NONE, - .stop = HW_UART_STOPBITS_1, - .auto_flow_control = 0, - .use_fifo = 1, - .use_dma = 1, - .tx_fifo_tr_lvl = 0, - .rx_fifo_tr_lvl = 0, - .tx_dma_channel = HW_DMA_CHANNEL_3, - .rx_dma_channel = HW_DMA_CHANNEL_2, - }; - // clang-format on - - hw_uart_init_ex(HW_UART2, &uart_init); - - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_UART2_TX); - hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_UART2_RX); - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO); - - hw_uart_receive(HW_UART2, &sUartBuf, 1, UartSignalRead, NULL); - - return OT_ERROR_NONE; -} - -otError otPlatUartDisable(void) -{ - return OT_ERROR_NONE; -} - -void da15000UartProcess(void) -{ - if (sUartReadDone) - { - otPlatUartReceived(&sUartBuf, 1); - sUartReadDone = false; - hw_uart_receive(HW_UART2, &sUartBuf, 1, UartSignalRead, NULL); - } - - if (sUartWriteDone) - { - sUartWriteDone = false; - otPlatUartSendDone(); - } - - if (sInitBuf == NULL) - { - sInitBuf = "\n"; - otPlatUartReceived((uint8_t *)sInitBuf, 1); - } -} - -otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength) -{ - hw_uart_send(HW_UART2, aBuf, aBufLength, UartSignalWrite, NULL); - - return OT_ERROR_NONE; -} diff --git a/third_party/Makefile.am b/third_party/Makefile.am index 38e2ea2e4..67e5ca660 100644 --- a/third_party/Makefile.am +++ b/third_party/Makefile.am @@ -29,7 +29,6 @@ include $(abs_top_nlbuild_autotools_dir)/automake/pre.am EXTRA_DIST = \ - dialog \ nxp \ nlbuild-autotools \ openthread-test-driver \ diff --git a/third_party/dialog/DialogSDK/bsp/arm_license.txt b/third_party/dialog/DialogSDK/bsp/arm_license.txt deleted file mode 100755 index e3e89d4cb..000000000 --- a/third_party/dialog/DialogSDK/bsp/arm_license.txt +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ \ No newline at end of file diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h b/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h deleted file mode 100644 index edc26449a..000000000 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h +++ /dev/null @@ -1,650 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup BSP_CONFIG - * \{ - * \addtogroup BSP_DEBUG - * - * \brief Doxygen documentation is not yet available for this module. - * Please check the source code file(s) - * - * \{ -*/ - -/** - **************************************************************************************** - * - * @file bsp_debug.h - * - * @brief Board Support Package. Debug Configuration. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef BSP_DEBUG_H_ -#define BSP_DEBUG_H_ - - -/* --------------------------------- DEBUG GPIO handling macros --------------------------------- */ - -#define DBG_CONFIGURE(flag, name, func) \ -{ \ - if (flag == 1) { \ - name##_MODE_REG = 0x300 + func; \ - } \ -} - -#define DBG_CONFIGURE_HIGH(flag, name) \ -{ \ - if (flag == 1) { \ - name##_SET_REG = name##_PIN; \ - name##_MODE_REG = 0x300; \ - } \ -} - -#define DBG_CONFIGURE_LOW(flag, name) \ -{ \ - if (flag == 1) { \ - name##_RESET_REG = name##_PIN; \ - name##_MODE_REG = 0x300; \ - } \ -} - -#define DBG_SET_HIGH(flag, name) \ -{ \ - if (flag == 1) { \ - name##_SET_REG = name##_PIN; \ - } \ -} - -#define DBG_SET_LOW(flag, name) \ -{ \ - if (flag == 1) { \ - name##_RESET_REG = name##_PIN; \ - } \ -} - -/* ---------------------------------------------------------------------------------------------- */ - - -/* ---------------------------------- HardFault or NMI event ------------------------------------ */ - -#ifndef EXCEPTION_DEBUG -#define EXCEPTION_DEBUG (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - - -/* --------------------------------- Clock and Power Manager ------------------------------------ */ - -#ifndef CPM_DEBUG -#define CPM_DEBUG (0) -#endif - -#ifndef CPM_USE_FUNCTIONAL_DEBUG -#define CPM_USE_FUNCTIONAL_DEBUG (0) // Requires GPIO config. -#endif - -#ifndef CPM_USE_TIMING_DEBUG -#define CPM_USE_TIMING_DEBUG (0) // Requires GPIO config. -#endif - -#ifndef CPM_USE_RCX_DEBUG -#define CPM_USE_RCX_DEBUG (0) // Requires logging. -#endif - -/* Controls which RAM blocks will be retained when the MEASURE_SLEEP_CURRENT test mode is used - * (optional). */ -#ifndef dg_configTESTMODE_RETAIN_RAM -#define dg_configTESTMODE_RETAIN_RAM (0x1F) -#endif - -/* Controls whether the Cache will be retained when the MEASURE_SLEEP_CURRENT test mode is used - * (optional). */ -#ifndef dg_configTESTMODE_RETAIN_CACHE -#define dg_configTESTMODE_RETAIN_CACHE (0) -#endif - -/* Controls whether the ECC RAM will be retained when the MEASURE_SLEEP_CURRENT test mode is used - * (optional). */ -#ifndef dg_config_TESTMODE_RETAIN_ECCRAM -#define dg_config_TESTMODE_RETAIN_ECCRAM (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - - -/* --------------------------------------- USB Charger ------------------------------------------ */ - -#ifndef DEBUG_USB_CHARGER -#define DEBUG_USB_CHARGER (0) -#endif - -#ifndef DEBUG_USB_CHARGER_FSM -#define DEBUG_USB_CHARGER_FSM (0) -#endif - -#ifndef DEBUG_USB_CHARGER_PRINT -#define DEBUG_USB_CHARGER_PRINT (0) -#endif - -#ifndef USB_CHARGER_TIMING_DEBUG -#define USB_CHARGER_TIMING_DEBUG (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - - -/* ------------------------------------------- BLE ---------------------------------------------- */ - -#ifndef BLE_USE_TIMING_DEBUG -#define BLE_USE_TIMING_DEBUG (0) // Requires GPIO config. -#endif - -#ifndef BLE_ADAPTER_DEBUG -#define BLE_ADAPTER_DEBUG (0) // Requires GPIO config. -#endif - -#ifndef BLE_RX_EN_DEBUG -#define BLE_RX_EN_DEBUG (0) // Requires GPIO config. -#endif - -#define BLE_RX_EN_FUNC (57) - -#ifndef BLE_WINDOW_STATISTICS -#define BLE_WINDOW_STATISTICS (0) -#endif - -#ifndef BLE_SLEEP_PERIOD_DEBUG -#define BLE_SLEEP_PERIOD_DEBUG (0) // Requires logging and window statistics. -#endif - -#ifndef BLE_WAKEUP_MONITOR_PERIOD -#define BLE_WAKEUP_MONITOR_PERIOD (1024) -#endif - -#ifndef BLE_MAX_MISSES_ALLOWED -#define BLE_MAX_MISSES_ALLOWED (0) -#endif - -#ifndef BLE_MAX_DELAYS_ALLOWED -#define BLE_MAX_DELAYS_ALLOWED (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - - -/* ------------------------------------------ Flash --------------------------------------------- */ -#ifndef FLASH_DEBUG -#define FLASH_DEBUG (0) // Requires GPIO config. -#endif - -#ifndef __DBG_QSPI_ENABLED -#define __DBG_QSPI_ENABLED (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - - -/* ------------------------------------------ Common -------------------------------------------- */ -#ifndef CMN_TIMING_DEBUG -#define CMN_TIMING_DEBUG (0) // Requires GPIO config. -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/* -------------------------------------------- SPI --------------------------------------------- */ -#ifndef SPI_TIMING_DEBUG -#define SPI_TIMING_DEBUG (0) // Requires GPIO config. -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/* ------------------------------------ GPIO configuration -------------------------------------- */ - -/* Enable/Disable GPIO pin assignment conflict detection - */ -#define DEBUG_GPIO_ALLOC_MONITOR_ENABLED (0) - - -/* Exception handling debug configuration - * - */ -#if (EXCEPTION_DEBUG == 0) -// Exception occurred (initial configuration: low) -#define EXCEPTIONDBG_MODE_REG *(volatile int *)0x20000000 -#define EXCEPTIONDBG_SET_REG *(volatile int *)0x20000000 -#define EXCEPTIONDBG_RESET_REG *(volatile int *)0x20000000 -#define EXCEPTIONDBG_PIN (0) - -#else - -// Tick (P3[0]) -#define EXCEPTIONDBG_MODE_REG GPIO->P30_MODE_REG -#define EXCEPTIONDBG_SET_REG GPIO->P3_SET_DATA_REG -#define EXCEPTIONDBG_RESET_REG GPIO->P3_RESET_DATA_REG -#define EXCEPTIONDBG_PIN (1 << 0) - -#endif - -/* Functional debug configuration - * - * Note that GPIO overlapping is allowed if the tracked events are discrete and the initial GPIO - * configuration is the same! No checking is performed for erroneous configuration though! - * - */ -#if (CPM_USE_FUNCTIONAL_DEBUG == 0) -// Tick (initial configuration: low) -#define CPMDBG_TICK_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_TICK_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_TICK_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_TICK_PIN (0) - -// External Wake-up (initial configuration: low) -#define CPMDBG_EXT_WKUP_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_EXT_WKUP_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_EXT_WKUP_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_EXT_WKUP_PIN (0) - -// Active / Sleep (initial configuration: high) -#define CPMDBG_POWERUP_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_POWERUP_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_POWERUP_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_POWERUP_PIN (0) - -#else - -// Tick (P2[3]) -#define CPMDBG_TICK_MODE_REG GPIO->P23_MODE_REG -#define CPMDBG_TICK_SET_REG GPIO->P2_SET_DATA_REG -#define CPMDBG_TICK_RESET_REG GPIO->P2_RESET_DATA_REG -#define CPMDBG_TICK_PIN (1 << 3) - -// External Wake-up (P3[0]) -#define CPMDBG_EXT_WKUP_MODE_REG GPIO->P30_MODE_REG -#define CPMDBG_EXT_WKUP_SET_REG GPIO->P3_SET_DATA_REG -#define CPMDBG_EXT_WKUP_RESET_REG GPIO->P3_RESET_DATA_REG -#define CPMDBG_EXT_WKUP_PIN (1 << 0) - -// Active / Sleep (P1[4]) -#define CPMDBG_POWERUP_MODE_REG GPIO->P14_MODE_REG -#define CPMDBG_POWERUP_SET_REG GPIO->P1_SET_DATA_REG -#define CPMDBG_POWERUP_RESET_REG GPIO->P1_RESET_DATA_REG -#define CPMDBG_POWERUP_PIN (1 << 4) -#endif - -/* Timing debug configuration - * - * Note that in this mode the pad latches are removed immediately after the execution resumes from - * the __WFI(). Because of this, it is not advised to use this feature in projects that use GPIOS. - * Nevertheless, in case it is used, make sure that the "peripheral initialization" is also done - * at that point, modifying sys_power_mgr.c accordingly. - * - * Note also that GPIO overlapping is allowed if the tracked events are discrete and the initial - * GPIO configuration is the same! No checking is performed for erroneous configuration though! - * - */ -#if (CPM_USE_TIMING_DEBUG == 0) -// CPM: sleep or idle entry (until __WFI() is called) (initial configuration: high) -#define CPMDBG_SLEEP_ENTER_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_SLEEP_ENTER_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_SLEEP_ENTER_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_SLEEP_ENTER_PIN (0) - -// CPM: sleep or idle exit (initial configuration: low) -#define CPMDBG_SLEEP_EXIT_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_SLEEP_EXIT_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_SLEEP_EXIT_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_SLEEP_EXIT_PIN (0) - -// Low clocks (initial configuration: low) -#define CPMDBG_LOWER_CLOCKS_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_LOWER_CLOCKS_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_LOWER_CLOCKS_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_LOWER_CLOCKS_PIN (0) - -// XTAL16M settling (initial configuration: low) -#define CPMDBG_XTAL16M_SETTLED_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_XTAL16M_SETTLED_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_XTAL16M_SETTLED_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_XTAL16M_SETTLED_PIN (0) - -#else - -// CPM: sleep or idle entry (until __WFI() is called) (P1[7]) -#define CPMDBG_SLEEP_ENTER_MODE_REG GPIO->P17_MODE_REG -#define CPMDBG_SLEEP_ENTER_SET_REG GPIO->P1_SET_DATA_REG -#define CPMDBG_SLEEP_ENTER_RESET_REG GPIO->P1_RESET_DATA_REG -#define CPMDBG_SLEEP_ENTER_PIN (1 << 7) - -// CPM: sleep or idle exit (P1[6]) -#define CPMDBG_SLEEP_EXIT_MODE_REG GPIO->P16_MODE_REG -#define CPMDBG_SLEEP_EXIT_SET_REG GPIO->P1_SET_DATA_REG -#define CPMDBG_SLEEP_EXIT_RESET_REG GPIO->P1_RESET_DATA_REG -#define CPMDBG_SLEEP_EXIT_PIN (1 << 6) - -// Low clocks (P1[5]) -#define CPMDBG_LOWER_CLOCKS_MODE_REG GPIO->P15_MODE_REG -#define CPMDBG_LOWER_CLOCKS_SET_REG GPIO->P1_SET_DATA_REG -#define CPMDBG_LOWER_CLOCKS_RESET_REG GPIO->P1_RESET_DATA_REG -#define CPMDBG_LOWER_CLOCKS_PIN (1 << 5) - -// XTAL16M settling (P1[4]) -#define CPMDBG_XTAL16M_SETTLED_MODE_REG GPIO->P14_MODE_REG -#define CPMDBG_XTAL16M_SETTLED_SET_REG GPIO->P1_SET_DATA_REG -#define CPMDBG_XTAL16M_SETTLED_RESET_REG GPIO->P1_RESET_DATA_REG -#define CPMDBG_XTAL16M_SETTLED_PIN (1 << 4) -#endif - -#if (BLE_USE_TIMING_DEBUG == 0) -// BLE LP & GEN irqs (initial configuration: low) -#define CPMDBG_BLE_IRQ_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_BLE_IRQ_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_BLE_IRQ_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_BLE_IRQ_PIN (0) - -// BLE sleep prepare (final stage) (initial configuration: low) -#define CPMDBG_BLE_SLEEP_ENTRY_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_BLE_SLEEP_ENTRY_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_BLE_SLEEP_ENTRY_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_BLE_SLEEP_ENTRY_PIN (0) - -// BLE LP irq signal (diagnostics) (initial configuration: unknown) -#define CPMDBG_BLE_LP_IRQ_MODE_REG *(volatile int *)0x20000000 - -#else - -// BLE LP & GEN ISRs (P1[4]) -#define CPMDBG_BLE_IRQ_MODE_REG GPIO->P14_MODE_REG -#define CPMDBG_BLE_IRQ_SET_REG GPIO->P1_SET_DATA_REG -#define CPMDBG_BLE_IRQ_RESET_REG GPIO->P1_RESET_DATA_REG -#define CPMDBG_BLE_IRQ_PIN (1 << 4) - -// BLE sleep prepare (final stage) (P1[4]) -#define CPMDBG_BLE_SLEEP_ENTRY_MODE_REG GPIO->P14_MODE_REG -#define CPMDBG_BLE_SLEEP_ENTRY_SET_REG GPIO->P1_SET_DATA_REG -#define CPMDBG_BLE_SLEEP_ENTRY_RESET_REG GPIO->P1_RESET_DATA_REG -#define CPMDBG_BLE_SLEEP_ENTRY_PIN (1 << 4) - -// BLE LP irq signal (diagnostics) (P2[3]) -#define CPMDBG_BLE_LP_IRQ_MODE_REG GPIO->P23_MODE_REG -#endif - -#if (BLE_ADAPTER_DEBUG == 0) -#define BLEBDG_ADAPTER_MODE_REG *(volatile int *)0x20000000 -#define BLEBDG_ADAPTER_SET_REG *(volatile int *)0x20000000 -#define BLEBDG_ADAPTER_RESET_REG *(volatile int *)0x20000000 -#define BLEBDG_ADAPTER_PIN (0) - -#else - -#define BLEBDG_ADAPTER_MODE_REG GPIO->P30_MODE_REG -#define BLEBDG_ADAPTER_SET_REG GPIO->P3_SET_DATA_REG -#define BLEBDG_ADAPTER_RESET_REG GPIO->P3_RESET_DATA_REG -#define BLEBDG_ADAPTER_PIN (1 << 0) -#endif - -#if (BLE_RX_EN_DEBUG == 0) -#define BLEBDG_RXEN_MODE_REG *(volatile int *)0x20000000 -#define BLEBDG_RXEN_SET_REG *(volatile int *)0x20000000 -#define BLEBDG_RXEN_RESET_REG *(volatile int *)0x20000000 -#define BLEBDG_RXEN_PIN (0) - -#else - -#define BLEBDG_RXEN_MODE_REG GPIO->P12_MODE_REG -#define BLEBDG_RXEN_SET_REG GPIO->P1_SET_DATA_REG -#define BLEBDG_RXEN_RESET_REG GPIO->P1_RESET_DATA_REG -#define BLEBDG_RXEN_PIN (1 << 2) -#endif - -#if (USB_CHARGER_TIMING_DEBUG == 0) -// CHRG: Inside critical section (initial configuration: low) -#define CHRGDBG_CRITICAL_SECTION_MODE_REG *(volatile int *)0x20000000 -#define CHRGDBG_CRITICAL_SECTION_SET_REG *(volatile int *)0x20000000 -#define CHRGDBG_CRITICAL_SECTION_RESET_REG *(volatile int *)0x20000000 -#define CHRGDBG_CRITICAL_SECTION_PIN (0) - -// CHRG: FSM task (initial configuration: low) -#define CHRGDBG_FSM_TASK_MODE_REG *(volatile int *)0x20000000 -#define CHRGDBG_FSM_TASK_SET_REG *(volatile int *)0x20000000 -#define CHRGDBG_FSM_TASK_RESET_REG *(volatile int *)0x20000000 -#define CHRGDBG_FSM_TASK_PIN (0) - -// CHRG: Control task (initial configuration: low) -#define CPMDBG_CONTROL_TASK_MODE_REG *(volatile int *)0x20000000 -#define CPMDBG_CONTROL_TASK_SET_REG *(volatile int *)0x20000000 -#define CPMDBG_CONTROL_TASK_RESET_REG *(volatile int *)0x20000000 -#define CPMDBG_CONTROL_TASK_PIN (0) - -#else - -// CHRG: Inside critical section (P3[2]) -#define CHRGDBG_CRITICAL_SECTION_MODE_REG GPIO->P32_MODE_REG -#define CHRGDBG_CRITICAL_SECTION_SET_REG GPIO->P3_SET_DATA_REG -#define CHRGDBG_CRITICAL_SECTION_RESET_REG GPIO->P3_RESET_DATA_REG -#define CHRGDBG_CRITICAL_SECTION_PIN (1 << 2) - -// CHRG: FSM task (P3[3]) -#define CHRGDBG_FSM_TASK_MODE_REG GPIO->P33_MODE_REG -#define CHRGDBG_FSM_TASK_SET_REG GPIO->P3_SET_DATA_REG -#define CHRGDBG_FSM_TASK_RESET_REG GPIO->P3_RESET_DATA_REG -#define CHRGDBG_FSM_TASK_PIN (1 << 3) - -// CHRG: Control task (P3[4]) -#define CPMDBG_CONTROL_TASK_MODE_REG GPIO->P34_MODE_REG -#define CPMDBG_CONTROL_TASK_SET_REG GPIO->P3_SET_DATA_REG -#define CPMDBG_CONTROL_TASK_RESET_REG GPIO->P3_RESET_DATA_REG -#define CPMDBG_CONTROL_TASK_PIN (1 << 4) - -#endif - -#if (CMN_TIMING_DEBUG == 0) -// Common: Inside critical section (initial configuration: low) -#define CMNDBG_CRITICAL_SECTION_MODE_REG *(volatile int *)0x20000000 -#define CMNDBG_CRITICAL_SECTION_SET_REG *(volatile int *)0x20000000 -#define CMNDBG_CRITICAL_SECTION_RESET_REG *(volatile int *)0x20000000 -#define CMNDBG_CRITICAL_SECTION_PIN (0) - -#else - -// Common: Inside critical section (P4[6]) -#define CMNDBG_CRITICAL_SECTION_MODE_REG GPIO->P40_MODE_REG -#define CMNDBG_CRITICAL_SECTION_SET_REG GPIO->P4_SET_DATA_REG -#define CMNDBG_CRITICAL_SECTION_RESET_REG GPIO->P4_RESET_DATA_REG -#define CMNDBG_CRITICAL_SECTION_PIN (1 << 0) - -#endif - - -/* Flash debug configuration - * - */ -#if (FLASH_DEBUG == 0) -// Write page (initial configuration: low) -#define FLASHDBG_PAGE_PROG_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_PIN (0) - -// Program page wait loop (initial configuration: low) -#define FLASHDBG_PAGE_PROG_WL_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_WL_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_WL_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_WL_PIN (0) - -// Program page wait loop - pending irq check (initial configuration: low) -#define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (0) - -// Suspend op (initial configuration: low) -#define FLASHDBG_SUSPEND_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_SUSPEND_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_SUSPEND_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_SUSPEND_PIN (0) - -// Erase sector cmd (initial configuration: low) -#define FLASHDBG_SECTOR_ERASE_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_SECTOR_ERASE_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_SECTOR_ERASE_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_SECTOR_ERASE_PIN (0) - -// Notify task (initial configuration: low) -#define FLASHDBG_TASK_NOTIFY_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_TASK_NOTIFY_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_TASK_NOTIFY_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_TASK_NOTIFY_PIN (0) - -// Suspend action (low level) (initial configuration: low) -#define FLASHDBG_SUSPEND_ACTION_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_SUSPEND_ACTION_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_SUSPEND_ACTION_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_SUSPEND_ACTION_PIN (0) - -// Resume op (initial configuration: low) -#define FLASHDBG_RESUME_MODE_REG *(volatile int *)0x20000000 -#define FLASHDBG_RESUME_SET_REG *(volatile int *)0x20000000 -#define FLASHDBG_RESUME_RESET_REG *(volatile int *)0x20000000 -#define FLASHDBG_RESUME_PIN (0) - -#else - -// Write page (initial configuration: low) -#define FLASHDBG_PAGE_PROG_MODE_REG GPIO->P30_MODE_REG -#define FLASHDBG_PAGE_PROG_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_PAGE_PROG_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_PAGE_PROG_PIN (1 << 0) - -// Program page wait loop (initial configuration: low) -#define FLASHDBG_PAGE_PROG_WL_MODE_REG GPIO->P31_MODE_REG -#define FLASHDBG_PAGE_PROG_WL_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_PAGE_PROG_WL_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_PAGE_PROG_WL_PIN (1 << 1) - -// Program page wait loop - pending irq check (initial configuration: low) -#define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG GPIO->P32_MODE_REG -#define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (1 << 2) - -// Suspend op (initial configuration: low) -#define FLASHDBG_SUSPEND_MODE_REG GPIO->P33_MODE_REG -#define FLASHDBG_SUSPEND_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_SUSPEND_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_SUSPEND_PIN (1 << 3) - -// Erase sector cmd (initial configuration: low) -#define FLASHDBG_SECTOR_ERASE_MODE_REG GPIO->P34_MODE_REG -#define FLASHDBG_SECTOR_ERASE_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_SECTOR_ERASE_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_SECTOR_ERASE_PIN (1 << 4) - -// Notify task (initial configuration: low) -#define FLASHDBG_TASK_NOTIFY_MODE_REG GPIO->P35_MODE_REG -#define FLASHDBG_TASK_NOTIFY_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_TASK_NOTIFY_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_TASK_NOTIFY_PIN (1 << 5) - -// Suspend action (low level) (initial configuration: low) -#define FLASHDBG_SUSPEND_ACTION_MODE_REG GPIO->P36_MODE_REG -#define FLASHDBG_SUSPEND_ACTION_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_SUSPEND_ACTION_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_SUSPEND_ACTION_PIN (1 << 6) - -// Resume op (initial configuration: low) -#define FLASHDBG_RESUME_MODE_REG GPIO->P37_MODE_REG -#define FLASHDBG_RESUME_SET_REG GPIO->P3_SET_DATA_REG -#define FLASHDBG_RESUME_RESET_REG GPIO->P3_RESET_DATA_REG -#define FLASHDBG_RESUME_PIN (1 << 7) - -#endif - - -/* Enables the logging of stack (RW) heap memories usage. - * - * The feature shall only be enabled in development/debug mode - */ -#ifndef dg_configLOG_BLE_STACK_MEM_USAGE -#define dg_configLOG_BLE_STACK_MEM_USAGE (0) -#endif - -/** - * \brief Enables BLE diagnostic signals. - * - * There are 5 (4 plus the COEX mode, see next table) diagnostic signal configurations that - * user can choose from. To enable a specific configuration, simply define - * dg_configBLE_DIAGN_CONFIG with the perspective configuration ID. Configuration ID 0 disables - * BLE diagnostics. - * - * ------------------------------------------------------------------------------------------------------ - * | Signal | Pin | Config 1 | Config 2 | Config 3 | Config 4 | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag0 | P2_0 | - | - | - | - | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag1 | P2_1 | - | - | - | - | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag2 | P2_2 | - | - | - | - | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag3 | P1_0 | - | - | - | - | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag4 | P1_1 | ble_slp_irq | radcntl_txen | radcntl_txen | radcntl_txen | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag5 | P1_2 | ble_cscnt_irq | radcntl_rxen | rf_tx_en | radcntl_rxen | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag6 | P1_3 | ble_finetgtim_irq | rf_rx_en | rf_tx_data | ble_rx_irq | - * ------------------------------------------------------------------------------------------------------ - * | ble_diag7 | P2_3 | ble_event_irq | rf_rx_data | rf_tx_data_valid | ble_event_irq | - * ------------------------------------------------------------------------------------------------------ - * - * Coex Mode Diagnostics: The COEX interface multiplexes its diagnostic pins on top of BLE - * diagnostics when option dg_configCOEX_ENABLE_DIAGS is set to 1. However, diagnostic signals - * ble_diag0 and ble_diag1 are unused by the COEX diagnostics and can be used for BLE. More - * specifically, Config 5 enables the following configuration, that can be used simultaneously - * with COEX diagnostics (dg_configCOEX_ENABLE_DIAGS == 1): - * - * ---------------------------------------------- - * | Signal | Pin | Config 5 | - * ---------------------------------------------- - * | ble_diag0 | P3_0 | radcntl_txen | - * ---------------------------------------------- - * | ble_diag1 | P3_1 | radcntl_rxen | - * ---------------------------------------------- - * - */ -#ifndef dg_configBLE_DIAGN_CONFIG -#define dg_configBLE_DIAGN_CONFIG (0) -#endif - -#endif /* BSP_DEBUG_H_ */ - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h b/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h deleted file mode 100644 index 0ac9c45f9..000000000 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h +++ /dev/null @@ -1,3156 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup BSP_CONFIG - * \{ - * \addtogroup BSP_CONFIG_DEFAULTS - * - * \brief Board support package default configuration values - * - * The following tags are used to describe the type of each configuration option. - * - * - **\bsp_config_option_build** : To be changed only in the build configuration - * of the project ("Defined symbols -D" in the - * preprocessor options). - * - * - **\bsp_config_option_app** : To be changed only in the custom_config*.h - * project files. - * - * - **\bsp_config_option_expert_only** : To be changed only by an expert user. - * \{ - */ - -/** - **************************************************************************************** - * - * @file bsp_defaults.h - * - * @brief Board Support Package. System Configuration file default values. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - *************************************************************************************** -*/ - -#ifndef BSP_DEFAULTS_H_ -#define BSP_DEFAULTS_H_ - - - - -/** - * \addtogroup POWER_SETTINGS - * - * \brief Power configuration settings - * \{ - */ -/* -------------------------------------- Power settings ---------------------------------------- */ - -/* - * This is a deprecated configuration hence not to be defined by an application. - * There's a single power configuration setup. - */ -#ifdef dg_configPOWER_CONFIG -#error "Configuration option dg_configPOWER_CONFIG is no longer supported." -#endif - -/** - * \brief When set to 1, the system will go to sleep and never exit allowing for the sleep current to be - * measured. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configTESTMODE_MEASURE_SLEEP_CURRENT -#define dg_configTESTMODE_MEASURE_SLEEP_CURRENT (0) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup IMAGE_CONFIGURATION_SETTINGS - * - * \brief Image configuration settings. - * \{ - */ -/* ------------------------------- Image configuration settings --------------------------------- */ - -/** - * \brief The chip revision that we compile for. - * - * \note There is no default value defined for the target chip revision. The application must\n - * neither explicitly set dg_configBLACK_ORCA_IC_REV, nor set\n - * dg_configUSE_AUTO_CHIP_DETECTION to 1. - * - * \bsp_default_note{\bsp_config_option_build,} - */ -#ifndef dg_configBLACK_ORCA_IC_REV -# if dg_configUSE_AUTO_CHIP_DETECTION != 1 -# error "You must either define dg_configBLACK_ORCA_IC_REV in the build configuration or set dg_configUSE_AUTO_CHIP_DETECTION to 1" -# endif -#endif - -/** - * \brief The chip stepping that we compile for. - * - * \note There is no default value defined for the target chip revision. The application must\n - * either explicitly set dg_configBLACK_ORCA_IC_STEP nor set\n - * dg_configUSE_AUTO_CHIP_DETECTION to 1. - * - * \bsp_default_note{\bsp_config_option_build,} - */ -#ifndef dg_configBLACK_ORCA_IC_STEP -# if dg_configUSE_AUTO_CHIP_DETECTION != 1 -# error "You must either define dg_configBLACK_ORCA_IC_STEP in the build configuration or set dg_configUSE_AUTO_CHIP_DETECTION to 1" -# endif -#endif - -/** - * \brief The motherboard revision we compile for. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configBLACK_ORCA_MB_REV -#define dg_configBLACK_ORCA_MB_REV BLACK_ORCA_MB_REV_D -#endif - -/* - * This is a deprecated configuration hence not to be defined by an application. - * The values of the trim registers are not anymore taken from the Flash. - * - */ -#ifdef dg_configCONFIG_HEADER_IN_FLASH -#error "Configuration option dg_configCONFIG_HEADER_IN_FLASH is no longer supported." -#endif - -/** - * \brief Controls how the image is built. - * - DEVELOPMENT_MODE: various debugging options are included. - * - PRODUCTION_MODE: all code used for debugging is removed. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configIMAGE_SETUP -#define dg_configIMAGE_SETUP DEVELOPMENT_MODE -#endif - -/** - * \brief When set to 1, the delay at the start of execution of the Reset_Handler is skipped. - * - * \details This delay is added in order to facilitate proper programming of the Flash or QSPI\n - * launcher invocation. Without it, there is no guarantee that the execution of the image\n - * will not proceed, altering the default configuration of the system from the one that the\n - * bootloader leaves it. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configSKIP_MAGIC_CHECK_AT_START -#define dg_configSKIP_MAGIC_CHECK_AT_START (0) -#endif - -/** - * \brief When set to 1, the chip version (DA14680/1-01 or DA14682/3-00, DA15XXX-00 ) will be detected\n - * automatically. - * \note It cannot be used in BLE applications because of the different linker scripts\n - * that are used. - * \warning Not to be used by a generic project, applicable for uartboot only. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSE_AUTO_CHIP_DETECTION -#define dg_configUSE_AUTO_CHIP_DETECTION (0) -#else -# if (dg_configUSE_AUTO_CHIP_DETECTION == 1) - #undef dg_configBLACK_ORCA_IC_REV - #define dg_configBLACK_ORCA_IC_REV BLACK_ORCA_IC_REV_AUTO - #undef dg_configBLACK_ORCA_IC_STEP - #define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_AUTO -# endif -#endif - -/** - * \brief When set to 1, the OTP copy will be emulated when in DEVELOPMENT_MODE. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configEMULATE_OTP_COPY -#define dg_configEMULATE_OTP_COPY (0) -#endif - -/** - * \brief When set to 1, the QSPI copy will be emulated when in DEVELOPMENT_MODE (Not Applicable!). - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configEMULATE_QSPI_COPY -#define dg_configEMULATE_QSPI_COPY (0) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup LOW_POWER_CLOCK_SETTINGS - * - * \brief Doxygen documentation is not yet available for this module. - * Please check the source code file(s) - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - * \{ - */ -/* --------------------------------- Low-Power clock settings ----------------------------------- */ - -/* - * Maximum sleep time the sleep timer supports - * - * dg_configTim1Prescaler can be zero. if dg_configTim1Prescaler is not zero then - * ( dg_configTim1Prescaler + 1 ) MUST be a power of 2! */ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#if (dg_configUSE_LP_CLK == LP_CLK_32000) -#define dg_configTim1Prescaler (3) -#define dg_configMaxSleepTime (8) // sec -#elif (dg_configUSE_LP_CLK == LP_CLK_32768) -#define dg_configTim1Prescaler (3) -#define dg_configMaxSleepTime (8) // sec -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) -#define dg_configTim1Prescaler (0) -#define dg_configMaxSleepTime (8) // sec -#elif (dg_configUSE_LP_CLK == LP_CLK_ANY) -/* Assuming that the frequency of the external digital clock is 32000Hz, - * period: 1/32000 = 31.25usec - * Timer1 wrap-around time: 65536 * 31.25 = 2.048sec - * With a prescaler equal to 3, the wrap around time becomes: (1 + 3) * 2.048 = ~8sec. - * If the clock frequency is too slow, i.e. 16000Hz then - * period: 1/16000 = 62.5usec - * Timer1 wrap-around time = 65536 * 62.5 = 4.096sec - * and the prescaler should be 1 so that: (1 + 1) * 4.096 = ~8sec. - * If the clock frequency is too high, i.e. 125000Hz then - * period: 1/125000 = 8usec - * Timer1 wrap-around time = 65536 * 8 = 0.524sec - * and the prescaler should be 3 so that: (1 + 3) * 0.524 = ~2sec. - * The values MUST be defined in the custom_config_<>.h file! - */ -#else -#error "dg_configUSE_LP_CLK has invalid setting" -#endif -#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ -#if (dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768) || (dg_configUSE_LP_CLK == LP_CLK_RCX) -#ifdef dg_configTim1Prescaler -#warning "Timer1 prescaler is not supported in DA14682/3 chips." -#undef dg_configTim1Prescaler -#endif /* dg_configTim1Prescaler */ -#define dg_configMaxSleepTime (134217) // sec -#else -#error "dg_configUSE_LP_CLK has invalid setting" -#endif -#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ - -#if (dg_configTim1Prescaler && (((dg_configTim1Prescaler+1) / 2) * 2) != (dg_configTim1Prescaler+1)) -#error "dg_configTim1Prescaler+1 is not 0 or a power of 2!" -#endif - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#if (dg_configTim1Prescaler == 0) -#define dg_configTim1PrescalerBitRange (0) -#elif (dg_configTim1Prescaler == 1) -#define dg_configTim1PrescalerBitRange (1) -#elif (dg_configTim1Prescaler == 3) -#define dg_configTim1PrescalerBitRange (2) -#else -#error "dg_configTim1Prescaler is larger than 3!" -#endif -#else -#ifdef dg_configTim1PrescalerBitRange -#warning "Timer1 prescaler is not supported in DA14682/3 chips." -#undef dg_configTim1PrescalerBitRange -#endif -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup SYSTEM_CONFIGURATION_SETTINGS - * - * \brief System configuration settings - * - * \{ - */ -/* ------------------------------- System configuration settings -------------------------------- */ - -/** - * \brief Source of Low Power clock used (LP_CLK_IS_ANALOG, LP_CLK_IS_DIGITAL) - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configLP_CLK_SOURCE -#define dg_configLP_CLK_SOURCE LP_CLK_IS_ANALOG -#endif - -# if ((dg_configLP_CLK_SOURCE == LP_CLK_IS_ANALOG) && (dg_configUSE_LP_CLK == LP_CLK_ANY)) -# error "When the LP source is analog (XTAL), the option LP_CLK_ANY is invalid!" -# endif - -# if ((dg_configLP_CLK_SOURCE == LP_CLK_IS_DIGITAL) && (dg_configUSE_LP_CLK == LP_CLK_RCX)) -# error "When the LP source is digital (External), the option LP_CLK_RCX is invalid!" -# endif - -/** - * \brief Low Power clock used (LP_CLK_32000, LP_CLK_32768, LP_CLK_RCX, LP_CLK_ANY) - * - * \bsp_default_note{\bsp_config_option_app,} - */ -# ifndef dg_configUSE_LP_CLK -# define dg_configUSE_LP_CLK LP_CLK_RCX -# endif - -/** - * \brief Code execution mode - * - * - MODE_IS_RAM - * - MODE_IS_MIRRORED - * - MODE_IS_CACHED - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -# ifndef dg_configEXEC_MODE -# define dg_configEXEC_MODE MODE_IS_RAM -# endif - -/** - * \brief Code location - * - * - NON_VOLATILE_IS_OTP - * - NON_VOLATILE_IS_FLASH - * - NON_VOLATILE_IS_NONE (RAM) - * - * \bsp_default_note{\bsp_config_option_app,} - */ -# ifndef dg_configCODE_LOCATION -# define dg_configCODE_LOCATION NON_VOLATILE_IS_NONE -# endif - -/** - * \brief Frequency of the crystal connected to the XTAL Oscillator: 16MHz or 32MHz. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -# ifndef dg_configEXT_CRYSTAL_FREQ -# define dg_configEXT_CRYSTAL_FREQ EXT_CRYSTAL_IS_16M -# endif - -/** - * \brief External LP type - * - * - 0: a crystal is connected to XTAL32Kp and XTALK32Km - * - 1: a digital clock is provided. - * - * \note the frequency of the digital clock must be 32KHz or 32.768KHz and be always running. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -# ifndef dg_configEXT_LP_IS_DIGITAL -# define dg_configEXT_LP_IS_DIGITAL (0) -# endif - -/* - * This is a deprecated configuration hence not to be defined by an application. - * Forcing the system to enter into clockless sleep during deep sleep is no longer supported. - */ -#ifdef dg_configFORCE_DEEP_SLEEP -#error "Configuration option dg_configFORCE_DEEP_SLEEP is no longer supported." -#endif - -/** - * \brief Timer 1 usage - * - * When set to 0, Timer1 is reserved for the OS tick. - * - * \note A setting to 1 is meaningful only for non-RTOS projects. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSER_CAN_USE_TIMER1 -#define dg_configUSER_CAN_USE_TIMER1 (0) -#endif - -/** - * \brief Time needed for the settling of the LP clock, in msec. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configXTAL32K_SETTLE_TIME -#define dg_configXTAL32K_SETTLE_TIME (8000) -#endif - -/** - * \brief Sleep delay time - * - * At startup, the system will stay active for at least this time period before it is allowed to go - * to sleep, in msec. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#if (dg_configXTAL32K_SETTLE_TIME > 8000) -#define dg_configINITIAL_SLEEP_DELAY_TIME (dg_configXTAL32K_SETTLE_TIME) -#else -#define dg_configINITIAL_SLEEP_DELAY_TIME (8000) -#endif - -/** - * \brief XTAL16 settle time - * - * Time needed for the settling of the XTAL16, in LP cycles. To this value, 5 LP cycles, that are - * needed to start the core clock, are added since the SW powers the 1V4 rail after the execution - * is resumed. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configXTAL16_SETTLE_TIME -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #define dg_configXTAL16_SETTLE_TIME (85 + 5) -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #define dg_configXTAL16_SETTLE_TIME cm_rcx_us_2_lpcycles((uint32_t)((85 + 5) * 30.5)) -#else /* LP_CLK_ANY */ -// Must be defined in the custom_config_<>.h file. -#endif -#endif - -/** - * \brief XTAL16 settle time RC32K - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#define dg_configXTAL16_SETTLE_TIME_RC32K (110) - -/** - * \brief RC16 wakeup time - * - * This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code - * using RC16. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#define dg_configWAKEUP_RC16_TIME (16) - -/** - * \brief XTAL16 wakeup time - * - * Wake up N LP cycles before "time 0" to have XTAL16 ready when needed. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#define dg_configWAKEUP_XTAL16_TIME (dg_configXTAL16_SETTLE_TIME + dg_configWAKEUP_RC16_TIME) - -/** - * \brief OS tick restore time - * - * This is the time, in LP cycles, required from the OS to restore the tick timer. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configOS_TICK_RESTORE_TIME -#ifdef RELEASE_BUILD -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - #define dg_configOS_TICK_RESTORE_TIME (dg_configTim1Prescaler ? 2 + dg_configTim1Prescaler : 3) - #else - #if (dg_configIMAGE_SETUP == PRODUCTION_MODE) - #define dg_configOS_TICK_RESTORE_TIME (dg_configTim1Prescaler ? 3 + dg_configTim1Prescaler : 4) - #else - #define dg_configOS_TICK_RESTORE_TIME (dg_configTim1Prescaler ? 3 + dg_configTim1Prescaler : 4) - #endif - #endif -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) - #else - #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) - #endif -#else /* LP_CLK_ANY */ - /* Must be defined in the custom_config_<>.h file. - * For QSPI cached, the dg_configOS_TICK_RESTORE_TIME must be ~120usec when no prescaling is - * used and ~180usec when prescaling is used. - */ -#endif -#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - #define dg_configOS_TICK_RESTORE_TIME (3) - #else - #if (dg_configIMAGE_SETUP == PRODUCTION_MODE) - #define dg_configOS_TICK_RESTORE_TIME (4) - #else - #define dg_configOS_TICK_RESTORE_TIME (4) - #endif - #endif -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) - #else - #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) - #endif -#else /* LP_CLK_ANY */ - /* Must be defined in the custom_config_<>.h file. - * For QSPI cached, the dg_configOS_TICK_RESTORE_TIME must be ~120usec when no prescaling is - * used and ~180usec when prescaling is used. - */ -#endif -#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ -#else // RELEASE_BUILD -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - #define dg_configOS_TICK_RESTORE_TIME (40) - #else - #define dg_configOS_TICK_RESTORE_TIME (72) - #endif -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(1200) - #else - #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(2400) - #endif -#else /* LP_CLK_ANY */ - /* Must be defined in the custom_config_<>.h file. - * Usually, the dg_configOS_TICK_RESTORE_TIME is set to a large value (i.e. 1.2 - 2.4msec) - * in order to allow for a more "relaxed" waking up of the system. - */ -#endif -#endif // RELEASE_BUILD -#endif // dg_configOS_TICK_RESTORE_TIME - -/** - * \brief Image copy time - * - * The number of LP cycles needed for the application's image data to be copied from the OTP - * (or QSPI) to the RAM in mirrored mode. - * - * \warning MUST BE SMALLER THAN #dg_configMIN_SLEEP_TIME !!! - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#if (dg_configEXEC_MODE != MODE_IS_MIRRORED) - #undef dg_configIMAGE_COPY_TIME - #define dg_configIMAGE_COPY_TIME (0) -#elif !defined(dg_configIMAGE_COPY_TIME) - #if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #define dg_configIMAGE_COPY_TIME (64) - #elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #define dg_configIMAGE_COPY_TIME cm_rcx_us_2_lpcycles(1950) - #else /* LP_CLK_ANY */ - // Must be defined in the custom_config_<>.h file. - #endif -#endif - -/** - * \brief Retention memory configuration. - * - * 5 bits field; each bit controls whether the relevant memory block will be retained (1) or not (0). - * - bit 0 : SYSRAM1 - * - bit 1 : SYSRAM2 - * - bit 2 : SYSRAM3 - * - bit 3 : SYSRAM4 - * - bit 4 : SYSRAM5 - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - * - */ -#ifndef dg_configMEM_RETENTION_MODE -#define dg_configMEM_RETENTION_MODE (0x1F) -#endif - -/* - * This is a deprecated configuration hence not to be defined by an application. - */ -#ifdef dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE -#error "dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE is no longer supported." -#endif - -/** - * \brief Memory Shuffling mode. - * - * See SYS_CTRL_REG:REMAP_RAMS field. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configSHUFFLING_MODE -#define dg_configSHUFFLING_MODE (0) -#endif - -/** - * \brief ECC microcode RAM retainment - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configECC_UCODE_RAM_RETAINED -#define dg_configECC_UCODE_RAM_RETAINED (0) -#endif - -/** - * \brief Watchdog Service - * - * - 1: enabled - * - 0: disabled - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSE_WDOG -#define dg_configUSE_WDOG (0) -#endif - -/** - * \brief Brown-out Detection - * - * - 1: used - * - 0: not used - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSE_BOD -#define dg_configUSE_BOD (1) -#endif - -/** - * \brief Reset value for Watchdog. - * - * See WATCHDOG_REG:WDOG_VAL field. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configWDOG_RESET_VALUE -#define dg_configWDOG_RESET_VALUE (0xFF) -#endif - -/** - * \brief Maximum watchdog tasks - * - * Maximum number of tasks that the Watchdog Service can monitor. It can be larger (up to 32) than - * needed, at the expense of increased Retention Memory requirement. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configWDOG_MAX_TASKS_CNT -#define dg_configWDOG_MAX_TASKS_CNT (4) -#endif - -/** - * \brief Watchdog notify interval - * - * Interval (in miliseconds) for common timer which can be used to trigger tasks in order to notify - * watchdog. Can be set to 0 in order to disable timer code entirely. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configWDOG_NOTIFY_TRIGGER_TMO -#define dg_configWDOG_NOTIFY_TRIGGER_TMO (0) -#endif - -/** - * \brief Abort a clock modification if it will cause an error to the SysTick counter - * - * - 1: on - * - 0: off - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configABORT_IF_SYSTICK_CLK_ERR -#define dg_configABORT_IF_SYSTICK_CLK_ERR (0) -#endif - -/** - * \brief Maximum adapters count - * - * Should be equal to the number of Adapters used by the Application. It can be larger (up to 254) - * than needed, at the expense of increased Retention Memory requirements. It cannot be 0. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configPM_MAX_ADAPTERS_CNT -#define dg_configPM_MAX_ADAPTERS_CNT (16) -#endif - -/** - * \brief Maximum sleep defer time - * - * The maximum time sleep can be deferred via a call to pm_defer_sleep_for(). It is in clock cycles - * in the case of the XTAL32K and in usec in the case of RCX. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configPM_MAX_ADAPTER_DEFER_TIME -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #define dg_configPM_MAX_ADAPTER_DEFER_TIME (128) -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #define dg_configPM_MAX_ADAPTER_DEFER_TIME cm_rcx_us_2_lpcycles(4000) -#else /* LP_CLK_ANY */ - // Must be defined in the custom_config_<>.h file. It should be > 3.5msec. -#endif -#endif - -/** - * \brief Minimum sleep time - * - * No power savings if we enter sleep when the sleep time is less than N LP cycles - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configMIN_SLEEP_TIME -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #define dg_configMIN_SLEEP_TIME (33*3) // 3 msec -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #define dg_configMIN_SLEEP_TIME cm_rcx_us_2_lpcycles_low_acc(3000) // 3 msec -#else /* LP_CLK_ANY */ - // Must be defined in the custom_config_<>.h file. It should be ~3msec but this may vary. -#endif -#endif - -/** - * \brief Recharge period - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configSET_RECHARGE_PERIOD -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) -#define dg_configSET_RECHARGE_PERIOD (3000) /** number of Low Power clock cycles for - sampling and / or refreshing. */ -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) -#define dg_configSET_RECHARGE_PERIOD (90000) /** number of msec for sampling and / or - refreshing */ -#else /* LP_CLK_ANY */ - // Must be defined in the custom_config_<>.h file. -#endif -#endif /* dg_configSET_RECHARGE_PERIOD */ - -/** - * \brief When set to 1, the DCDC is used. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSE_DCDC -#define dg_configUSE_DCDC (1) -#endif - -/* - * This is a deprecated configuration hence not to be defined by an application. - * The semantics of dg_configUSE_ADC replaced by dg_configUSE_HW_GPADC. - */ -#ifdef dg_configUSE_ADC -#error "Configuration option dg_configUSE_ADC is no longer supported. Use dg_configUSE_HW_GPADC instead." -#endif - -/** - * \brief Apply ADC Gain Error correction. - * - 1: used - * - 0: not used - * - * The default setting is: 1. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSE_ADC_GAIN_ERROR_CORRECTION -#define dg_configUSE_ADC_GAIN_ERROR_CORRECTION (1) -#endif - -/** - * \brief When set to 1, the USB interface is used for data transfers. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSE_USB -#define dg_configUSE_USB (0) -#endif - -/** - * \addtogroup CHARGER_SETTINGS - * - * \brief Charger configuration settings - * \{ - */ -/* -------------------------------------- Charger settings -------------------------------------- */ - -/** - * \brief Battery type - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configBATTERY_TYPE -#define dg_configBATTERY_TYPE (BATTERY_TYPE_NO_BATTERY) -/** - * \brief Battery charge voltage - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#define dg_configBATTERY_CHARGE_VOLTAGE (0) -/** - * \brief Battery charge current - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#define dg_configBATTERY_CHARGE_CURRENT (0) -/** - * \brief Battery charge NTC - * - * 0: NTC is enabled, 1: NTC is disabled - * - * Note that when NTC is enabled, the P14 and P16 are controlled by the charger and cannot be used - * by the application. P14 is set high (at 3.3V) when the charging starts while P16 is an input. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#define dg_configBATTERY_CHARGE_NTC (0) - -#if (dg_configBATTERY_CHARGE_NTC > 1) -#error "dg_configBATTERY_CHARGE_NTC must be either 0 or 1." -#endif -/** - * \brief Battery pre-charge current - * - * Normal charging : - * - 0 - 15 : as the description of the CHARGER_CTRL1_REG[CHARGE_CUR] field. - * - * Ext charging : "end-of-charge" is not functional when this mode is used. - * - 16 : Reserved - * - 17 : Reserved - * - 18 : 1mA - * - 19 : 1.5mA - * - 20 : 2.1mA - * - 21 : 3.2mA - * - 22 : 4.3mA - * - 23 : Reserved - * - 24 : 6.6mA - * - 25 : 7.8mA - * - 26 : Reserved - * - 27 : 11.3mA - * - 28 : 13.3mA - * - 29 : 15.3mA - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#define dg_configBATTERY_PRECHARGE_CURRENT (0) -#endif - -/** - * \brief When set to 1, the USB Charger is used to charge the battery. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSE_USB_CHARGER -#define dg_configUSE_USB_CHARGER (0) -#else -#if (dg_configUSE_USB_CHARGER == 1) - #undef dg_configUSE_HW_GPADC - #define dg_configUSE_HW_GPADC (1) - #undef dg_configUSE_USB - #define dg_configUSE_USB (1) - #undef dg_configGPADC_ADAPTER - #define dg_configGPADC_ADAPTER (1) - #undef dg_configBATTERY_ADAPTER - #define dg_configBATTERY_ADAPTER (1) -#endif -#endif - -/** - * \brief When set to 1, the USB Charger will try to enumerate, if possible. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSE_USB_ENUMERATION -#define dg_configUSE_USB_ENUMERATION (0) -#else -#if (dg_configUSE_USB_ENUMERATION == 1) - #undef dg_configUSE_USB - #define dg_configUSE_USB (1) -#endif -#endif - -/** - * \brief Controls how the system will behave when the USB i/f is suspended. - * - * \details When the USB Node is suspended by the USB Host, the application may have to act in - * order to comply with the USB specification (consume less than 2.5mA). The available - * options are: - * 0: do nothing - * 1: pause system clock => the LP clock is stopped and only VBUS and USB irqs are handled - * 2: pause application => The system is not paused but the application must stop all - * timers and make sure all tasks are blocked. - * - * Both in modes 1 and 2, the application must make sure that all external peripherals are - * either powered off or placed in the lowest power consumption mode. - */ -#ifndef dg_configUSB_SUSPEND_MODE -#define dg_configUSB_SUSPEND_MODE (0) -#endif - -/** - * \brief When set to 1, the USB Charger will start charging with less than 100mA until enumerated. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configALLOW_CHARGING_NOT_ENUM -#define dg_configALLOW_CHARGING_NOT_ENUM (0) -#endif - -/** - * \brief When set to 1, the USB charger will stop charging from an SDP port (if - * #dg_configALLOW_CHARGING_NOT_ENUM is set to 1) after 45 minutes, if not enumerated. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSE_NOT_ENUM_CHARGING_TIMEOUT -#define dg_configUSE_NOT_ENUM_CHARGING_TIMEOUT (1) -#endif - -/** - * \brief Pre-charging initial measure delay - * - * This is the time to wait (N x 10 ms) before doing the first voltage measurement after starting - * pre-charging. This is to ensure that an initial battery voltage overshoot will not trigger the - * charger to stop pre-charging and move to normal charging. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configPRECHARGING_INITIAL_MEASURE_DELAY -#define dg_configPRECHARGING_INITIAL_MEASURE_DELAY (3) -#endif - -/** - * \brief Pre-charging threshold - * - * When Vbat is below this threshold (in ADC measurement units), pre-charging starts. - * - * The value must be calculated using this equation: - * - * y[ADC units] = (4095 * Vbat[Volts]) / 5 - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configPRECHARGING_THRESHOLD -#define dg_configPRECHARGING_THRESHOLD (0) -#endif - -/** - * \brief Charging threshold - * - * When Vbat is at or above this threshold (in ADC measurement units), pre-charging stops and - * charging starts. - * - * The value must be calculated using this equation: - * - * y[ADC units] = (4095 * Vbat[Volts]) / 5 - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configCHARGING_THRESHOLD -#define dg_configCHARGING_THRESHOLD (0) -#endif - -/** - * \brief Pre-charging timeout - * - * If after this period, the Vbat is not higher than 3.0V then pre-charging stops (N x 10msec). - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configPRECHARGING_TIMEOUT -#define dg_configPRECHARGING_TIMEOUT (15 * 60 * 100) -#endif - -/** - * \brief Charging timeout - * - * If after this period, the charger is still charging then charging stops (N x 10msec). This - * timeout has priority over the next two timeouts. If it is not zero then it is the only one taken - * into account. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configCHARGING_TIMEOUT -#define dg_configCHARGING_TIMEOUT (0) -#endif - -/** - * \brief Charging CC timeout - * - * If after this period, the charger is still in CC mode then charging stops (N x 10msec). - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configCHARGING_CC_TIMEOUT -#define dg_configCHARGING_CC_TIMEOUT (180 * 60 * 100) -#endif - -/** - * \brief Charging CV timeout - * - * If after this period, the charger is still in CC mode then charging stops (N x 10msec). - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configCHARGING_CV_TIMEOUT -#define dg_configCHARGING_CV_TIMEOUT (360 * 60 * 100) -#endif - -/** - * \brief Charginf polling interval - * - * While being attached to a USB cable and the battery has been charged, this is the interval - * (N x 10msec) that the Vbat is polled to decide whether a new charge cycle will be started. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSB_CHARGER_POLLING_INTERVAL -#define dg_configUSB_CHARGER_POLLING_INTERVAL (100) -#endif - -/** - * \brief Battery low level - * - * If not zero, this is the low limit of the battery voltage. If Vbat drops below this limit, the - * system enters hibernation mode, waiting either for the battery to the changed or recharged. - * - * The value must be calculated using this equation: - * - * y[ADC units] = (4095 * Vbat[Volts]) / 5 - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configBATTERY_LOW_LEVEL - #if (dg_configBATTERY_TYPE == BATTERY_TYPE_NO_BATTERY) || (dg_configBATTERY_TYPE == BATTERY_TYPE_NO_RECHARGE) - #define dg_configBATTERY_LOW_LEVEL (0) - #else - #define dg_configBATTERY_LOW_LEVEL (2293) // 2.8V - #endif -#endif - -/* - * This is a deprecated configuration hence not to be defined by an application. - * When entering hibernation mode then: - * A DA14680/1-01 system reboots only via an interrupt from the WKUP Ctrl or VBUS. - * A DA14682/3-00, DA15XXX-00 system reboots only via an interrupt from the WKUP Ctrl. - */ -#ifdef dg_configLOW_VBAT_HANDLING -#error "Configuration option dg_configLOW_VBAT_HANDLING is no longer supported." -#endif - -/** - * \brief Custom battery ADC voltage - * - * In case of a custom battery with unknown voltage level, this parameter must be defined to - * provide the charge level of the battery in ADC measurement units. If not provided for some - * reason, it is set to the lowest level (1.9V). - * - * The value must be calculated using this equation: - * - * y[ADC units] = (4095 * Vbat[Volts]) / 5 - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#if (dg_configBATTERY_TYPE == BATTERY_TYPE_CUSTOM) -#ifndef dg_configBATTERY_TYPE_CUSTOM_ADC_VOLTAGE -#define dg_configBATTERY_TYPE_CUSTOM_ADC_VOLTAGE (1556) -#endif -#endif - -/** - * \brief Battery charge gap - * - * This is the safety limit used in the "Measurement step" of the specification to decide whether - * charging should be started. The default value is 0.1V. - * - * The value must be calculated using this equation: - * - * y[ADC units] = (4095 * Vbat[Volts]) / 5 - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configBATTERY_CHARGE_GAP -#define dg_configBATTERY_CHARGE_GAP (82) -#endif - -/** - * \brief Battery replenish gap - * - * This is the limit below the maximum Vbat level (Vbat - dg_configBATTERY_REPLENISH_GAP), where - * charging will be restarted in order to replenish the battery. The default value is 0.2V. - * - * The value must be calculated using this equation: - * - * y[ADC units] = (4095 * Vbat[Volts]) / 5 - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configBATTERY_REPLENISH_GAP -#define dg_configBATTERY_REPLENISH_GAP (82*2) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} CHARGER_SETTINGS - */ - - -/** - * \brief The Rsense of the SOC in multiples of 0.1Ohm. The default value is (1 x 0.1Ohm). - */ -#ifndef dg_configSOC_RSENSE -#define dg_configSOC_RSENSE (1) // N x 0.1Ohm -#endif - -/** - * \brief When set to 1, the ProDK is used (controls specific settings for this board). - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSE_ProDK -#define dg_configUSE_ProDK (0) -#endif - -/** - * \brief When set to 1, State of Charge function is enabled. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configUSE_SOC -#define dg_configUSE_SOC (0) -#else -# if (dg_configUSE_SOC == 1) -# undef dg_configUSE_HW_SOC -# define dg_configUSE_HW_SOC (1) -# endif -#endif - -/** - * \addtogroup FLASH_SETTINGS - * - * \brief Flash configuration settings - * - * \{ - */ -/* -------------------------------------- Flash settings ---------------------------------------- */ - -/** - * \brief The rail from which the Flash is powered, if a Flash is used. - * - * - FLASH_IS_NOT_CONNECTED - * - FLASH_CONNECTED_TO_1V8 - * - FLASH_CONNECTED_TO_1V8P - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configFLASH_CONNECTED_TO -#error "dg_configFLASH_CONNECTED_TO is not defined!" -#endif - -/* Backward compatibility checks */ -#if defined(dg_configPOWER_EXT_1V8_PERIPHERALS) || defined(dg_configPOWER_FLASH) \ - || defined(dg_configFLASH_POWER_OFF) -#define PRINT_POWER_RAIL_SETUP -#endif - -#if defined(dg_configPOWER_EXT_1V8_PERIPHERALS) && defined(dg_configPOWER_1V8P) -#error "Both dg_configPOWER_EXT_1V8_PERIPHERALS and dg_configPOWER_1V8P are defined! Please use dg_configPOWER_1V8P only!" -#endif - -#ifdef dg_configPOWER_EXT_1V8_PERIPHERALS - #warning "dg_configPOWER_EXT_1V8_PERIPHERALS will be deprecated! Use dg_configPOWER_1V8P instead!" - - #if (dg_configPOWER_EXT_1V8_PERIPHERALS == 0) \ - && (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8P) - #error "Flash is connected to 1V8P but dg_configPOWER_EXT_1V8_PERIPHERALS is 0..." - #endif - - #if (dg_configPOWER_EXT_1V8_PERIPHERALS == 1) - #define dg_configPOWER_1V8P (1) - #else - #define dg_configPOWER_1V8P (0) - #endif - #undef dg_configPOWER_EXT_1V8_PERIPHERALS -#endif - -#if defined(dg_configPOWER_FLASH) && defined(dg_configPOWER_1V8_ACTIVE) -#error "Both dg_configPOWER_FLASH and dg_configPOWER_1V8_ACTIVE are defined! Please use dg_configPOWER_1V8_ACTIVE only!" -#endif - -#if defined(dg_configFLASH_POWER_OFF) && defined(dg_configPOWER_1V8_SLEEP) -#error "Both dg_configFLASH_POWER_OFF and dg_configPOWER_1V8_SLEEP are defined! Please use dg_configPOWER_1V8_SLEEP only!" -#endif - -#ifdef dg_configPOWER_FLASH -#warning "dg_configPOWER_FLASH is deprecated! Use dg_configPOWER_1V8_ACTIVE instead!" -#endif -/* End of backward compatibility checks */ - -/** - * \brief When set to 1, the 1V8 rail is powered, when the system is in active state. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configPOWER_1V8_ACTIVE -#ifndef dg_configPOWER_FLASH - #define dg_configPOWER_1V8_ACTIVE (0) -#else - #if (dg_configPOWER_FLASH == 0) - #if (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8) - #error "Flash is connected to the 1V8 rail but the rail is turned off (1)..." - #else - #define dg_configPOWER_1V8_ACTIVE (0) - #endif - #else - #define dg_configPOWER_1V8_ACTIVE (1) - #endif -#endif -#endif - -/** - * \brief When set to 1, the 1V8 is powered during sleep. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configPOWER_1V8_SLEEP -#ifndef dg_configFLASH_POWER_OFF - #define dg_configPOWER_1V8_SLEEP (0) -#else - #if (dg_configFLASH_POWER_OFF == 0) - #define dg_configPOWER_1V8_SLEEP (1) - #else - #define dg_configPOWER_1V8_SLEEP (0) - #endif -#endif -#endif - -/** - * \brief When set to 1, the Flash (connected to the 1V8 rail) is powered off during sleep. - * - * \note This is an internal define and cannot be overridden! - */ -#undef dg_configFLASH_POWER_OFF -#define dg_configFLASH_POWER_OFF ((dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8) \ - && (dg_configPOWER_1V8_SLEEP == 0)) - -/** - * \brief When set to 1, the 1V8P rail is powered. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configPOWER_1V8P -#define dg_configPOWER_1V8P (0) -#endif - -/** - * \brief When set to 1, the QSPI FLASH is put to power-down state during sleep. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configFLASH_POWER_DOWN -#define dg_configFLASH_POWER_DOWN (0) -#endif - -/** - * \brief Enable the Flash Autodetection mode - * - * \warning THIS WILL GREATLY INCREASE THE CODE SIZE AND RETRAM USAGE!!! MAKE SURE YOUR PROJECT - * CAN SUPPORT THIS. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configFLASH_AUTODETECT -#define dg_configFLASH_AUTODETECT (0) -#endif - -#if dg_configFLASH_AUTODETECT == 0 - -/** - * \brief The Flash Driver header file to include - * - * The header file must be in the include path of the compiler - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configFLASH_HEADER_FILE -#define dg_configFLASH_HEADER_FILE "qspi_w25q80ew.h" -#endif - -/** - * \brief The Flash Manufacturer ID - * - * This must be defined inside the driver header file - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configFLASH_MANUFACTURER_ID -#define dg_configFLASH_MANUFACTURER_ID WINBOND_ID -#endif - -/** - * \brief The Flash Device Type ID - * - * This must be defined inside the driver header file - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configFLASH_DEVICE_TYPE -#define dg_configFLASH_DEVICE_TYPE W25Q80EW -#endif - -/** - * \brief The Flash Device Density ID - * - * This must be defined inside the driver header file - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configFLASH_DENSITY -#define dg_configFLASH_DENSITY W25Q_8Mb_SIZE -#endif - -#endif /* dg_configFLASH_AUTODETECT == 0 */ - -/** - * \brief Offset of the image if not placed at the beginning of QSPI Flash. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configIMAGE_FLASH_OFFSET -#define dg_configIMAGE_FLASH_OFFSET (0) -#endif - -/** - * \brief Set the flash page size. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configFLASH_MAX_WRITE_SIZE -#define dg_configFLASH_MAX_WRITE_SIZE (128) -#endif - -/** - * \brief Disable background operations. - * - * When enabled, outstanding QSPI operations will take place during sleep time - * increasing the efficiency. - * - * - 1 : Disabled - * - 0 : Enabled - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configDISABLE_BACKGROUND_FLASH_OPS -#define dg_configDISABLE_BACKGROUND_FLASH_OPS (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup DEBUG_SETTINGS - * - * \brief Debugging settings - * - * \{ - */ -/* -------------------------------------- Debug settings ---------------------------------------- */ - -/** - * \brief Enable debugger - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configENABLE_DEBUGGER -#define dg_configENABLE_DEBUGGER (1) -#endif - -/** - * \brief Use SW cursor - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSE_SW_CURSOR -# define dg_configUSE_SW_CURSOR (0) -# define SW_CURSOR_PORT (0) -# define SW_CURSOR_PIN (0) -#else -# if dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D -# if !defined SW_CURSOR_PORT && !defined SW_CURSOR_PIN -# define SW_CURSOR_PORT (0) -# define SW_CURSOR_PIN (7) -# endif -# else -# if !defined SW_CURSOR_PORT && !defined SW_CURSOR_PIN -# define SW_CURSOR_PORT (2) -# define SW_CURSOR_PIN (3) -# endif -# endif -#endif -#define SW_CURSOR_GPIO *(SW_CURSOR_PORT == 0 ? \ - (SW_CURSOR_PIN == 0 ? &(GPIO->P00_MODE_REG) : \ - (SW_CURSOR_PIN == 1 ? &(GPIO->P01_MODE_REG) : \ - (SW_CURSOR_PIN == 2 ? &(GPIO->P02_MODE_REG) : \ - (SW_CURSOR_PIN == 3 ? &(GPIO->P03_MODE_REG) : \ - (SW_CURSOR_PIN == 4 ? &(GPIO->P04_MODE_REG) : \ - (SW_CURSOR_PIN == 5 ? &(GPIO->P05_MODE_REG) : \ - (SW_CURSOR_PIN == 6 ? &(GPIO->P06_MODE_REG) : \ - &(GPIO->P07_MODE_REG)))))))) \ - : \ - (SW_CURSOR_PORT == 1 ? \ - (SW_CURSOR_PIN == 0 ? &(GPIO->P10_MODE_REG) : \ - (SW_CURSOR_PIN == 1 ? &(GPIO->P11_MODE_REG) : \ - (SW_CURSOR_PIN == 2 ? &(GPIO->P12_MODE_REG) : \ - (SW_CURSOR_PIN == 3 ? &(GPIO->P13_MODE_REG) : \ - (SW_CURSOR_PIN == 4 ? &(GPIO->P14_MODE_REG) : \ - (SW_CURSOR_PIN == 5 ? &(GPIO->P15_MODE_REG) : \ - (SW_CURSOR_PIN == 6 ? &(GPIO->P16_MODE_REG) : \ - &(GPIO->P17_MODE_REG)))))))) \ - : \ - (SW_CURSOR_PORT == 2 ? \ - (SW_CURSOR_PIN == 0 ? &(GPIO->P20_MODE_REG) : \ - (SW_CURSOR_PIN == 1 ? &(GPIO->P21_MODE_REG) : \ - (SW_CURSOR_PIN == 2 ? &(GPIO->P22_MODE_REG) : \ - (SW_CURSOR_PIN == 3 ? &(GPIO->P23_MODE_REG) : \ - &(GPIO->P24_MODE_REG))))) \ - : \ - (SW_CURSOR_PORT == 3 ? \ - (SW_CURSOR_PIN == 0 ? &(GPIO->P30_MODE_REG) : \ - (SW_CURSOR_PIN == 1 ? &(GPIO->P31_MODE_REG) : \ - (SW_CURSOR_PIN == 2 ? &(GPIO->P32_MODE_REG) : \ - (SW_CURSOR_PIN == 3 ? &(GPIO->P33_MODE_REG) : \ - (SW_CURSOR_PIN == 4 ? &(GPIO->P34_MODE_REG) : \ - (SW_CURSOR_PIN == 5 ? &(GPIO->P35_MODE_REG) : \ - (SW_CURSOR_PIN == 6 ? &(GPIO->P36_MODE_REG) : \ - &(GPIO->P37_MODE_REG)))))))) \ - : \ - (SW_CURSOR_PIN == 0 ? &(GPIO->P40_MODE_REG) : \ - (SW_CURSOR_PIN == 1 ? &(GPIO->P41_MODE_REG) : \ - (SW_CURSOR_PIN == 2 ? &(GPIO->P42_MODE_REG) : \ - (SW_CURSOR_PIN == 3 ? &(GPIO->P43_MODE_REG) : \ - (SW_CURSOR_PIN == 4 ? &(GPIO->P44_MODE_REG) : \ - (SW_CURSOR_PIN == 5 ? &(GPIO->P45_MODE_REG) : \ - (SW_CURSOR_PIN == 6 ? &(GPIO->P46_MODE_REG) : \ - &(GPIO->P47_MODE_REG)))))))))))) - -#define SW_CURSOR_SET *(SW_CURSOR_PORT == 0 ? &(GPIO->P0_SET_DATA_REG) : \ - (SW_CURSOR_PORT == 1 ? &(GPIO->P1_SET_DATA_REG) : \ - (SW_CURSOR_PORT == 2 ? &(GPIO->P2_SET_DATA_REG) : \ - (SW_CURSOR_PORT == 3 ? &(GPIO->P3_SET_DATA_REG) : \ - &(GPIO->P4_SET_DATA_REG))))) - -#define SW_CURSOR_RESET *(SW_CURSOR_PORT == 0 ? &(GPIO->P0_RESET_DATA_REG) : \ - (SW_CURSOR_PORT == 1 ? &(GPIO->P1_RESET_DATA_REG) : \ - (SW_CURSOR_PORT == 2 ? &(GPIO->P2_RESET_DATA_REG) : \ - (SW_CURSOR_PORT == 3 ? &(GPIO->P3_RESET_DATA_REG) : \ - &(GPIO->P4_RESET_DATA_REG))))) -/** - * \brief Enable task monitoring. - * - * \note Task monitoring can only be enabled if RTT or RETARGET is enabled - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configENABLE_TASK_MONITORING -#define dg_configENABLE_TASK_MONITORING (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup CACHE_SETTINGS - * - * \brief Cache configuration settings - * \{ - */ -/* -------------------------------------- Cache settings ---------------------------------------- */ - -/** - * \brief Set the size (in bytes) of the QSPI flash cacheable area. - * - * All reads from offset 0 up to (not including) offset dg_configCACHEABLE_QSPI_AREA_LEN - * will be cached. In addition, any writes to this area will trigger cache flushing, to - * avoid any cache incoherence. - * - * The size must be 64KB-aligned, due to the granularity of CACHE_CTRL2_REG[CACHE_LEN]. - * - * Special values: - * * 0 : Turn off cache. - * * -1 : Don't configure cacheable area size (i.e. leave as set by booter). - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configCACHEABLE_QSPI_AREA_LEN -#define dg_configCACHEABLE_QSPI_AREA_LEN (-1) -#endif - -/** - * \brief Set the associativity of the cache. - * - * Available values: - * - CACHE_ASSOC_AS_IS - * - CACHE_ASSOC_DIRECT_MAP - * - CACHE_ASSOC_2_WAY - * - CACHE_ASSOC_4_WAY - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configCACHE_ASSOCIATIVITY -#define dg_configCACHE_ASSOCIATIVITY CACHE_ASSOC_4_WAY -#endif - -/** - * \brief Set the line size of the cache. - * - * \bsp_default_note{\bsp_config_option_app,} - * - * Available values: - * - CACHE_LINESZ_AS_IS - * - CACHE_LINESZ_8_BYTES - * - CACHE_LINESZ_16_BYTES - * - CACHE_LINESZ_32_BYTES - */ -#ifndef dg_configCACHE_LINESZ -#define dg_configCACHE_LINESZ CACHE_LINESZ_8_BYTES -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup ARBITER_SETTINGS - * - * \brief Arbiter configuration settings - * \{ - */ -/* ------------------------------- Arbiter configuration settings ------------------------------- */ - -/** - * \brief Custom arbiter configuration support - * When defined, coex is configurable and priorities can be set: - * -either manually, per mac, using coex api - * -or automatically, by the PTIs provided by each mac - * - * When not defined, coex operates with the default/fixed priority scheme: - * BLE traffic has always higher priority than FTDF. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configCOEX_ENABLE_CONFIG -#define dg_configCOEX_ENABLE_CONFIG (0) -#endif - -/** - * \brief Arbiter statistics - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configCOEX_ENABLE_STATS -#define dg_configCOEX_ENABLE_STATS (0) -#endif - -/** - * \brief Arbiter diagnostics enable - * - * This automatically enables arbiter diagnostic signals (when RF PD is on) - * - * See hw_coex.h for more information. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configCOEX_ENABLE_DIAGS -#define dg_configCOEX_ENABLE_DIAGS (0) -#endif - -/** - * \brief Arbiter diagnostics mode - * - * This is the default mode for arbiter diagnostics. - * - * See hw_coex.h for more information. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configCOEX_DIAGS_MODE -#define dg_configCOEX_DIAGS_MODE (HW_COEX_DIAG_MODE_3) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup PERIPHERAL_SELECTION - * - * \brief Peripheral selection - * - * When enabled the specific low level driver is included in the compilation of the SDK. - * - 0 : Disabled - * - 1 : Enabled - * - * The default option can be overridden in the application configuration file. - * - * \{ - Driver | Setting | Default option - ------------------------------ | -------------------------------------- | :------------------: - AES HASH | dg_configUSE_HW_AES_HASH | 0 - Radio MAC Arbiter | dg_configUSE_HW_COEX | 0 - Clock and Power Manager | dg_configUSE_HW_CPM | 1 - Direct Memory Access | dg_configUSE_HW_DMA | 1 - Elliptic Curve Controller | dg_configUSE_HW_ECC | 1 - Analog to Digital Converter | dg_configUSE_HW_GPADC | 1 - General Purpose I/O | dg_configUSE_HW_GPIO | 1 - Inter-Integrated Circuit | dg_configUSE_HW_I2C | 0 - Infra Red Generator | dg_configUSE_HW_IRGEN | 0 - Keyboard scanner | dg_configUSE_HW_KEYBOARD_SCANNER | 0 - OTP controller | dg_configUSE_HW_OTPC | 1 - QSPI controller | dg_configUSE_HW_QSPI | 1 - Quadrature decoder | dg_configUSE_HW_QUAD | 0 - Radio module | dg_configUSE_HW_RF | 1 - State of charge module | dg_configUSE_HW_SOC | 0 - Timer 0 | dg_configUSE_HW_TIMER0 | 0 - Timer 1 | dg_configUSE_HW_TIMER1 | 1 - Timer 2 | dg_configUSE_HW_TIMER2 | 0 - True Random Generator | dg_configUSE_HW_TRNG | 1 - UART | dg_configUSE_HW_UART | 1 - USB charger | dg_configUSE_HW_USB_CHARGER | 1 - Wakeup timer | dg_configUSE_HW_WKUP | 1 - PDM interface | dg_configUSE_IF_PDM | 0 - * - * \bsp_default_note{\bsp_config_option_app,} - */ - -/* -------------------------------- Peripherals (hw_*) selection -------------------------------- */ - -#ifndef dg_configUSE_HW_AES_HASH -#define dg_configUSE_HW_AES_HASH (0) -#endif - -#ifndef dg_configUSE_HW_COEX -#define dg_configUSE_HW_COEX (0) -#endif - -#ifndef dg_configUSE_HW_CPM -#define dg_configUSE_HW_CPM (1) -#endif - -#ifndef dg_configUSE_HW_DMA -#define dg_configUSE_HW_DMA (1) -#endif - -#ifndef dg_configUSE_HW_ECC -#define dg_configUSE_HW_ECC (1) -#endif - -#ifndef dg_configUSE_HW_GPADC -#define dg_configUSE_HW_GPADC (1) -#endif - -#ifndef dg_configUSE_HW_GPIO -#define dg_configUSE_HW_GPIO (1) -#endif - -#ifndef dg_configUSE_HW_I2C -#define dg_configUSE_HW_I2C (0) -#endif - -#ifndef dg_configUSE_HW_IRGEN -#define dg_configUSE_HW_IRGEN (0) -#endif - -#ifndef dg_configUSE_HW_KEYBOARD_SCANNER -#define dg_configUSE_HW_KEYBOARD_SCANNER (0) -#endif - -#ifndef dg_configUSE_HW_OTPC -#define dg_configUSE_HW_OTPC (1) -#endif - -#ifndef dg_configUSE_HW_QSPI -#define dg_configUSE_HW_QSPI (1) -#endif - -#ifndef dg_configUSE_HW_QUAD -#define dg_configUSE_HW_QUAD (0) -#endif - -#ifndef dg_configUSE_HW_RF -#define dg_configUSE_HW_RF (1) -#endif - -#ifndef dg_configUSE_HW_SOC -#define dg_configUSE_HW_SOC (0) -#endif - -#ifndef dg_configUSE_HW_SPI -#define dg_configUSE_HW_SPI (0) -#endif - -#ifndef dg_configUSE_HW_TEMPSENS -#define dg_configUSE_HW_TEMPSENS (1) -#endif - -#ifndef dg_configUSE_HW_TIMER0 -#define dg_configUSE_HW_TIMER0 (0) -#endif - -#ifndef dg_configUSE_HW_TIMER1 -#define dg_configUSE_HW_TIMER1 (1) -#endif - -#ifndef dg_configUSE_HW_TIMER2 -#define dg_configUSE_HW_TIMER2 (0) -#endif - -#ifndef dg_configUSE_HW_TRNG -#define dg_configUSE_HW_TRNG (1) -#endif - -#ifndef dg_configUSE_HW_UART -#define dg_configUSE_HW_UART (1) -#endif - -#ifndef dg_configUSE_HW_USB_CHARGER -#define dg_configUSE_HW_USB_CHARGER (1) -#endif - -#ifndef dg_configUSE_HW_WKUP -#define dg_configUSE_HW_WKUP (1) -#endif - -#ifndef dg_configUSE_HW_USB -#define dg_configUSE_HW_USB (0) -#endif - -#ifndef dg_configUSE_IF_PDM -#define dg_configUSE_IF_PDM (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ------------------------------- USB settings ------------------------------------------------ */ - -/** - * \addtogroup USB_SETTINGS - * - * \brief USB DMA enable configuration settings - * - * The macros in this section are used to enable the DMA with USB and to define the two possible end point to use the DMA for data transfers. - * \{ - */ - -/** - * \brief Enable the DMA for reading/writing data to USB EP.\n - * By default the USB DMA is not enabled.\n - * To enable the DMA for the USB, set this the macro to value (1) in the custom_config_xxx.h file.\n - * When the USB DMA is enabled, the default end points with DMA are EP1 and EP2. \n - * It is possible only one TX and one RX end point to use DMA.\n - * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n - * To change the end points using DMA, set in the the custom_config_xxx.h file the desired values for the macros: - * \par \c dg_configUSB_TX_DMA_EP - * valid values: 1,3,5\n - * default value: 1 - * \par \c dg_configUSB_RX_DMA_EP - * valid values: 2,4,6\n - * default value: 2 - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSB_DMA_SUPPORT -#define dg_configUSB_DMA_SUPPORT (0) -#endif - - -/** - * \brief The USB TX end point (D-->H) to enable the DMA.\n - * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n - * To change the TX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros. - * \par \c dg_configUSB_TX_DMA_EP - * valid values: 1,3,5\n - * default value: 1 - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSB_TX_DMA_EP -#define dg_configUSB_TX_DMA_EP (1) -#endif - -/** - * \brief The USB RX end point (D-->H) to enable the DMA.\n - * User can choose a different pair of end points to use the DMA as needed according to app requirements.\n - * To change the RX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros. - * \par \c dg_configUSB_RX_DMA_EP - * valid values: 2,4,6\n - * default value: 2 - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUSB_RX_DMA_EP -#define dg_configUSB_RX_DMA_EP (2) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - - - -/* ------------------------------- WKUP settings ------------------------------------------------ */ - -/** - * \addtogroup WKUP_SETTINGS - * - * \brief WKUP configuration settings - * \{ - */ - -/* ------------------------------- LATCH settings ------------------------------------------------ */ - -/** - * \addtogroup WKUP_LATCH_SETTINGS - * - * \brief WKUP LATCH configuration settings - * \{ - */ - -/** - * \brief WKUP latch wakeup (io) source support - * - * \note In chip revision DA14680/1-01, this feature is implemented in s/w - * \note In chip revision DA14682/3-00, DA15XXX-00, this feature is implemented in h/w - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#if (!defined(dg_configLATCH_WKUP_SOURCE)) || (dg_configUSE_HW_WKUP == 0) - #undef dg_configLATCH_WKUP_SOURCE - #define dg_configLATCH_WKUP_SOURCE (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ------------------------------- UART settings ------------------------------------------------ */ - -/** - * \addtogroup UART_SETTINGS - * - * \brief UART FIFO configuration settings - * \{ - */ - -/* ------------------------------- FIFO settings ------------------------------------------------ */ - -/** - * \addtogroup UART_FIFO_SETTINGS - * - * \brief UART FIFO configuration settings - * \{ - */ - -/** - * \brief Software FIFO support - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUART_SOFTWARE_FIFO -#define dg_configUART_SOFTWARE_FIFO (0) -#endif - -/** - * \brief UART1's software FIFO size - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUART1_SOFTWARE_FIFO_SIZE -# define dg_configUART1_SOFTWARE_FIFO_SIZE (0) -#endif - -/** - * \brief UART2's software FIFO size - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUART2_SOFTWARE_FIFO_SIZE -# define dg_configUART2_SOFTWARE_FIFO_SIZE (0) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ------------------------------- Circular DMA for RX settings --------------------------------- */ - -/** - * \addtogroup UART_CIRCULAR_DMA_FOR_RX_SETTINGS - * - * \brief UART FIFO configuration settings - * \{ - */ - -/** - * \brief Circular DMA support for RX - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUART_RX_CIRCULAR_DMA -#define dg_configUART_RX_CIRCULAR_DMA (0) -#endif - -/** - * \brief UART1's Circular DMA buffer size for RX - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE -#define dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE (0) -#endif - -/** - * \brief UART2's Circular DMA buffer size for RX - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE -#define dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup ADAPTER_SELECTION - * - * \brief Adapter selection - * - * When enabled the specific adapter is included in the compilation of the SDK. - * - 0 : Disabled - * - 1 : Enabled - * - * The default option can be overridden in the application configuration file. - * - * \{ - Adapter | Setting | Default option - ------------------------------ | -------------------------------------- | :------------------: - Flash | dg_configFLASH_ADAPTER | 1 - Inter-Integrated Circuit | dg_configI2C_ADAPTER | 0 - Non Volatile Memory Storage | dg_configNVMS_ADAPTER | 1 - Virtual EERPOM Storage | dg_configNVMS_VES | 1 - Radio | dg_configRF_ADAPTER | 1 - Serial Peripheral Interface | dg_configSPI_ADAPTER | 0 - UART | dg_configUART_ADAPTER | 0 - UART for BLE | dg_configUART_BLE_ADAPTER | 0 - Analog to Digital Converter | dg_configGPADC_ADAPTER | 0 - Temperature Sensor | dg_configTEMPSENS_ADAPTER | 0 - Battery | dg_configBATTERY_ADAPTER | 0 - Non Volatile Parameters | dg_configNVPARAM_ADAPTER | 0 - Crypto | dg_configCRYPTO_ADAPTER | 1 - Keyboard scanner | dg_configKEYBOARD_SCANNER_ADAPTER | 0 - * - * - * \bsp_default_note{\bsp_config_option_app,} - */ - - -/* -------------------------------- Adapters (ad_*) selection -------------------------------- */ - -#ifndef dg_configFLASH_ADAPTER -#define dg_configFLASH_ADAPTER (1) -#endif - -#ifndef dg_configI2C_ADAPTER -#define dg_configI2C_ADAPTER (0) -#endif - -#ifndef dg_configNVMS_ADAPTER -#define dg_configNVMS_ADAPTER (1) -#endif - -#ifndef dg_configNVMS_FLASH_CACHE -#define dg_configNVMS_FLASH_CACHE (0) -#endif - -#ifndef dg_configNVMS_VES -#define dg_configNVMS_VES (1) -#endif - -#ifndef dg_configRF_ADAPTER -#define dg_configRF_ADAPTER (1) -#endif - -#ifndef dg_configSPI_ADAPTER -#define dg_configSPI_ADAPTER (0) -#endif - -#ifndef dg_configUART_ADAPTER -#define dg_configUART_ADAPTER (0) -#endif - -#ifndef dg_configUART_BLE_ADAPTER -#define dg_configUART_BLE_ADAPTER (0) -#endif - -#ifndef dg_configGPADC_ADAPTER -#define dg_configGPADC_ADAPTER (0) -#endif - -#ifndef dg_configTEMPSENS_ADAPTER -#define dg_configTEMPSENS_ADAPTER (0) -#endif - -#ifndef dg_configBATTERY_ADAPTER -#define dg_configBATTERY_ADAPTER (0) -#endif - -#ifndef dg_configNVPARAM_ADAPTER -#define dg_configNVPARAM_ADAPTER (0) -#endif - -#ifndef dg_configCRYPTO_ADAPTER -#define dg_configCRYPTO_ADAPTER (1) -#endif - -#ifndef dg_configKEYBOARD_SCANNER_ADAPTER -#define dg_configKEYBOARD_SCANNER_ADAPTER (0) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup CONSOLE_IO_SETTINGS - * - * \brief Console IO configuration settings - * - * \{ - Description | Setting | Default option - ----------------------------------------- | -------------------------- | :---------------: - Enable serial console module | dg_configUSE_CONSOLE | 0 - Enable serial console stubbed API | dg_configUSE_CONSOLE_STUBS | 0 - Enable Command Line Interface module | dg_configUSE_CLI | 0 - Enable Command Line Interface stubbed API | dg_configUSE_CLI_STUBS | 0 - - \see console.h cli.h - - \note CLI module requires dg_configUSE_CONSOLE to be enabled. - * - * \bsp_default_note{\bsp_config_option_app,} - */ - -/* -------------------------------------- Console IO configuration settings --------------------- */ - -#ifndef dg_configUSE_CONSOLE -#define dg_configUSE_CONSOLE (0) -#endif - -#ifndef dg_configUSE_CONSOLE_STUBS -#define dg_configUSE_CONSOLE_STUBS (0) -#endif - -#ifndef dg_configUSE_CLI -#define dg_configUSE_CLI (0) -#endif - -#ifndef dg_configUSE_CLI_STUBS -#define dg_configUSE_CLI_STUBS (0) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ----------------------------- DGTL ----------------------------------------------------------- */ - -/** - * \brief Enable D.GTL interface - * - * When this macro is enabled, the DGTL framework is available for use. - * The framework must furthermore be initialized in the application using - * dgtl_init(). Additionally, the UART adapter must be initialized accordingly. - * - * Please see sdk/middleware/dgtl/include/ for further DGTL configuration - * (in dgtl_config.h) and API. - * - * \bsp_default_note{\bsp_config_option_app,} - * - */ -#ifndef dg_configUSE_DGTL -#define dg_configUSE_DGTL (0) -#endif - -/** - * \addtogroup DEBUG_SETTINGS - * \{ - * \addtogroup SYSTEM_VIEW - * - * \brief System View configuration settings - * \{ - */ - -/* ----------------------------- Segger System View configuration ------------------------------- */ - -/** - * \brief Segger's System View - * - * When enabled the application should also call SEGGER_SYSVIEW_Conf() to enable system monitoring. - * configTOTAL_HEAP_SIZE should be increased by dg_configSYSTEMVIEW_STACK_OVERHEAD bytes for each system task. - * For example, if there are 8 system tasks configTOTAL_HEAP_SIZE should be increased by - * (8 * dg_configSYSTEMVIEW_STACK_OVERHEAD) bytes. - * - * - 0 : Disabled - * - 1 : Enabled - * - * \bsp_default_note{\bsp_config_option_app,} - * - */ -#ifndef dg_configSYSTEMVIEW -#define dg_configSYSTEMVIEW (0) -#endif - -/** - * \brief Stack size overhead when System View API is used - * - * All thread stack sizes plus the the stack of IRQ handlers will be increased by that amount - * to avoid stack overflow when System View is monitoring the system. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configSYSTEMVIEW_STACK_OVERHEAD -#define dg_configSYSTEMVIEW_STACK_OVERHEAD (256) -#endif - -/* - * Enable/Disable System View monitoring time critical interrupt handlers (BLE, CPM, USB). - * Disabling ISR monitoring could help reducing assertions triggered by System View monitoring overhead. - * - */ - -/** - * \brief Let System View monitor BLE related ISRs (BLE_GEN_Handler / BLE_WAKEUP_LP_Handler). - * - * - 0 : Disabled - * - 1 : Enabled - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configSYSTEMVIEW_MONITOR_BLE_ISR -#define dg_configSYSTEMVIEW_MONITOR_BLE_ISR (1) -#endif - -/** - * \brief Let System View monitor CPM related ISRs (SWTIM1_Handler / WKUP_GPIO_Handler). - * - * - 0 : Disabled - * - 1 : Enabled - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configSYSTEMVIEW_MONITOR_CPM_ISR -#define dg_configSYSTEMVIEW_MONITOR_CPM_ISR (1) -#endif - -/** - * \brief Let System View monitor USB related ISRs (USB_Handler / VBUS_Handler). - * - * - 0 : Disabled - * - 1 : Enabled - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configSYSTEMVIEW_MONITOR_USB_ISR -#define dg_configSYSTEMVIEW_MONITOR_USB_ISR (1) -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - * \} - */ - -/** - * \addtogroup RF_DRIVER_SETTINGS - * - * \brief Doxygen documentation is not yet available for this module. - * Please check the source code file(s) - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - * \{ - */ -/* ------------------------------- RF driver configuration settings ----------------------------- */ - -/* Set to 1 to enable the recalibration procedure */ -#ifndef dg_configRF_ENABLE_RECALIBRATION -#define dg_configRF_ENABLE_RECALIBRATION (1) -#endif - -/* If RF recalibration is enabled, we need to enable GPADC as well */ -#if dg_configRF_ENABLE_RECALIBRATION -#undef dg_configUSE_HW_GPADC -#define dg_configUSE_HW_GPADC (1) -#undef dg_configGPADC_ADAPTER -#define dg_configGPADC_ADAPTER (1) -#undef dg_configTEMPSENS_ADAPTER -#define dg_configTEMPSENS_ADAPTER (1) -#endif - -/* If RF is enabled, we need to enable GPADC adapter as well */ -#if dg_configRF_ADAPTER -#undef dg_configGPADC_ADAPTER -#define dg_configGPADC_ADAPTER (1) -#endif - -/* Minimum time before performing an RF recalibration, in FreeRTOS scheduler ticks */ -#ifndef dg_configRF_MIN_RECALIBRATION_TIMEOUT -#if (dg_configUSE_LP_CLK == LP_CLK_32000) -#define dg_configRF_MIN_RECALIBRATION_TIMEOUT (1000) // ~2 secs -#elif (dg_configUSE_LP_CLK == LP_CLK_32768) -#define dg_configRF_MIN_RECALIBRATION_TIMEOUT (1024) // ~2 secs -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) -#define dg_configRF_MIN_RECALIBRATION_TIMEOUT (1000) -#else /* LP_CLK_ANY */ -// Must be defined in the custom_config_<>.h file. Should result in ~2sec. -#endif -#endif - -/* Maximum time before performing an RF recalibration, in FreeRTOS scheduler ticks - * If this time has elapsed, and RF is about to be powered off, recalibration will - * be done unconditionally. Set to 0 to disable this functionality */ -#ifndef dg_configRF_MAX_RECALIBRATION_TIMEOUT -#define dg_configRF_MAX_RECALIBRATION_TIMEOUT (0) // Disabled -#endif - -/* Timeout value (in FreeRTOS scheduler ticks) for timer to initiate RF recalibration. - * This will happen at ANY TIME RF is ON and CONFIGURED, EVEN IF A MAC IS RX/TXing DURING - * THIS TIME, in contrary to dg_configRF_MAX_RECALIBRATION_TIMEOUT, that will be - * performed ONLY when powering off RF. - * This is intended for applications where RF is always on, so there is no - * opportunity to be recalibrated the normal way (i.e. during poweroff) - * - * Set to 0 to disable this functionality */ -#ifndef dg_configRF_RECALIBRATION_TIMER_TIMEOUT -#define dg_configRF_RECALIBRATION_TIMER_TIMEOUT (0) // Disabled -#endif - - -/* Minimum temp difference before performing an RF recalibration, in oC*/ -#ifndef dg_configRF_MIN_RECALIBRATION_TEMP_DIFF -#ifdef CONFIG_USE_FTDF - #define dg_configRF_MIN_RECALIBRATION_TEMP_DIFF (5) -#else - #define dg_configRF_MIN_RECALIBRATION_TEMP_DIFF (10) -#endif -#endif - -/* Duration of recalibration procedure, in lp clk cycles */ -#ifndef dg_configRF_RECALIBRATION_DURATION -# if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) -# if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) -# define dg_configRF_RECALIBRATION_DURATION (230) -# elif (dg_configUSE_LP_CLK == LP_CLK_RCX) -# define dg_configRF_RECALIBRATION_DURATION cm_rcx_us_2_lpcycles((uint32_t)(230 * 30.5)) -# else /* LP_CLK_ANY */ - // Must be defined in the custom_config_<>.h file. It should be ~7msec. -# endif -# else -# if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) -# define dg_configRF_RECALIBRATION_DURATION (131) -# elif (dg_configUSE_LP_CLK == LP_CLK_RCX) -# define dg_configRF_RECALIBRATION_DURATION cm_rcx_us_2_lpcycles((uint32_t)(131 * 30.5)) -# else /* LP_CLK_ANY */ - // Must be defined in the custom_config_<>.h file. It should be ~4msec. -# endif -# endif -#endif - -#ifndef dg_configRF_IFF_CALIBRATION_TIMEOUT -#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) - #define dg_configRF_IFF_CALIBRATION_TIMEOUT (40) -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) - #define dg_configRF_IFF_CALIBRATION_TIMEOUT cm_rcx_us_2_lpcycles((uint32_t)(40 * 30.5)) -#else /* LP_CLK_ANY */ -// Must be defined in the custom_config_<>.h file. It should be ~1.2msec. -# endif -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup BLE_EVENT_NOTIFICATIONS - * - * \brief Doxygen documentation is not yet available for this module. - * Please check the source code file(s) - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - * - * \{ - */ -/* -----------------------------------BLE event notifications configuration --------------------- */ - -/* - * BLE ISR event Notifications - * - * This facility enables the user app to receive notifications for BLE - * ISR events. These events can be received either directly from inside - * the BLE ISR, or as task notifications to the Application Task - * registered to the BLE manager. - * - * To enable, define dg_configBLE_EVENT_NOTIF_TYPE to either - * BLE_EVENT_NOTIF_USER_ISR or BLE_EVENT_NOTIF_USER_TASK. - * - * - When dg_configBLE_EVENT_NOTIF_TYPE == BLE_EVENT_NOTIF_USER_ISR, the user - * can define the following macros on his app configuration: - * - * dg_configBLE_EVENT_NOTIF_HOOK_END_EVENT : The BLE End Event - * dg_configBLE_EVENT_NOTIF_HOOK_CSCNT_EVENT : The BLE CSCNT Event - * dg_configBLE_EVENT_NOTIF_HOOK_FINE_EVENT : The BLE FINE Event - * - * These macros must be actually set to the names of functions defined inside - * the user application, having a prototype of - * - * void func(void); - * - * (The user app does not need to explicitly define the prototype). - * - * If one of these macros is not defined, the respective notification - * will be suppressed. - * - * Note that these functions will be called in ISR context, directly from the - * BLE ISR. They should therefore be very fast and should NEVER block. - * - * - When dg_configBLE_EVENT_NOTIF_TYPE == BLE_EVENT_NOTIF_USER_TASK, the user - * app will receive task notifications on the task registered to the BLE - * manager. - * - * Notifications will be received using the following bit masks: - * - * - dg_configBLE_EVENT_NOTIF_MASK_END_EVENT: End Event Mask (Def: bit 24) - * - dg_configBLE_EVENT_NOTIF_MASK_CSCNT_EVENT: CSCNT Event Mask (Def: bit 25) - * - dg_configBLE_EVENT_NOTIF_MASK_FINE_EVENT: FINE Event Mask (Def: bit 26) - * - * These macros, defining the task notification bit masks, can be redefined as - * needed. - * - * If one of the macros for callback functions presented in the previous - * section (for direct ISR notifications) is defined, while in this mode, - * the function with the same name will be called directly from the isr - * instead of sending a task notification for this particular event to - * the app task. - * - * Macro dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL (Default: 1) enables/disables - * runtime control/masking of notifications. - * - * If dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL == 1, then task notifications - * must be enabled/disabled using the - * ble_event_notif_[enable|disable]_[end|cscnt|fine]_event() functions. - * By default all notifications are disabled. - * - * If dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL == 0, all notifications will - * be sent unconditionally to the application task. - * - */ -#ifndef dg_configBLE_EVENT_NOTIF_TYPE -# define dg_configBLE_EVENT_NOTIF_TYPE BLE_EVENT_NOTIF_USER_ISR -#endif - -#if dg_configBLE_EVENT_NOTIF_TYPE == BLE_EVENT_NOTIF_USER_TASK - -/* Default implementation of BLE event task notifications. This - * implementation allows a user task to register for notifications, - * and to get task notifications for the available events - */ - -/* Default task notification masks for the various events for which - * the framework provides notifications - */ -# ifndef dg_configBLE_EVENT_NOTIF_MASK_END_EVENT -# define dg_configBLE_EVENT_NOTIF_MASK_END_EVENT (1 << 24) -# endif - -# ifndef dg_configBLE_EVENT_NOTIF_MASK_CSCNT_EVENT -# define dg_configBLE_EVENT_NOTIF_MASK_CSCNT_EVENT (1 << 25) -# endif - -# ifndef dg_configBLE_EVENT_NOTIF_MASK_FINE_EVENT -# define dg_configBLE_EVENT_NOTIF_MASK_FINE_EVENT (1 << 26) -# endif - -/* Implement event hook functions */ -# ifndef dg_configBLE_EVENT_NOTIF_HOOK_END_EVENT -# define dg_configBLE_EVENT_NOTIF_HOOK_END_EVENT ble_event_notif_app_task_end_event -# endif - -# ifndef dg_configBLE_EVENT_NOTIF_HOOK_CSCNT_EVENT -# define dg_configBLE_EVENT_NOTIF_HOOK_CSCNT_EVENT ble_event_notif_app_task_cscnt_event -# endif - -# ifndef dg_configBLE_EVENT_NOTIF_HOOK_FINE_EVENT -# define dg_configBLE_EVENT_NOTIF_HOOK_FINE_EVENT ble_event_notif_app_task_fine_event -# endif - -/* - * Allow runtime control of (un)masking notifications - */ -# ifndef dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL -# define dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL 1 -# endif - -#endif -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ----------------------------------- BLE hooks configuration ---------------------------------- */ - -/* Name of the function that is called to block BLE from sleeping under certain conditions - * - * The function must be declared as: - * unsigned char my_block_sleep(void); - * The return value of the function controls whether the BLE will be allowed to go to sleep or not, - * 0: the BLE may go to sleep, if possible - * 1: the BLE is not allowed to go to sleep. The caller (BLE Adapter) may block or not, - * depending on the BLE stack status. - * - * dg_configBLE_HOOK_BLOCK_SLEEP should be set to my_block_sleep in this example. - */ -#ifndef dg_configBLE_HOOK_BLOCK_SLEEP -/* Already undefined - Nothing to do. */ -#endif - -/* Name of the function that is called to modify the PTI value (Payload Type Indication) when - * arbitration is used - * - * Arbitration is needed only when another external radio is present. The function must be declared - * as: - * unsigned char my_pti_modify(void); - * Details for the implementation of such a function will be provided when the external radio - * arbitration functionality is integrated. - * - * dg_configBLE_HOOK_PTI_MODIFY should be set to my_pti_modify in this example. - * - * See also the comment about the in ble_config.h for more info. - */ -#ifndef dg_configBLE_HOOK_PTI_MODIFY -/* Already undefined - Nothing to do. */ -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \addtogroup DEBUG_SETTINGS - * - * \{ - */ -/* ---------------------------------- OS related configuration ---------------------------------- */ - -/** - * \brief Monitor OS heap allocations - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configTRACK_OS_HEAP -#define dg_configTRACK_OS_HEAP (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ---------------------------------- Heap size configuration ----------------------------------- */ - -/** - * \brief Heap size for used libc malloc() - * - * Specifies the amount of RAM that will be used as heap for libc malloc() function. - * It can be configured in bare metal projects to match application's requirements. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef __HEAP_SIZE -# if defined (CONFIG_RETARGET) || defined (CONFIG_RTT) -# define __HEAP_SIZE 0x0600 -# else -# define __HEAP_SIZE 0x0100 -# endif -#endif - -/* flag used by linker scripts */ -#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) -#define __HEAP_IS_LESS_THAN_0x200 (__HEAP_SIZE < 0x200) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/* --------------------------------- Stack size configuration ----------------------------------- */ - -/** - * \brief Stack size for main() function and interrupt handlers. - * - * Specifies the amount of RAM that will be used as stack for the main() function and the interrupt - * handlers. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef __STACK_SIZE -#define __STACK_SIZE 0x0200 -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/* ----------------------------------- RF FEM CONFIGURATION ------------------------------------- */ - -#include "bsp_fem.h" - -/* ---------------------------------------------------------------------------------------------- */ - - -/* ----------------------------------- DEBUG CONFIGURATION -------------------------------------- */ - -#include "bsp_debug.h" - -/* ---------------------------------------------------------------------------------------------- */ - -/* ---------------------------------- MEMORY LAYOUT CONFIGURATION ------------------------------- */ - -/** - * \addtogroup MEMORY_LAYOUT_SETTINGS - * - * \brief Memory layout configuration settings. - * \{ - */ - -/** - * \brief Controls the retention RAM optimization. - * - * - 0 : All RAM is retained. - * - 1 : Retention memory size is optimal. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configOPTIMAL_RETRAM -#define dg_configOPTIMAL_RETRAM (0) -#endif -/** - * \addtogroup OTP_PROJECT_MEMORY_LAYOUT_SETTINGS - * - * \brief Memory layout configuration settings for a OTP project. - * \{ - */ - -/** - * \brief Code size in OTP projects, no product specific. - * - * \note Code size cannot be more than 58K. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CODE_SIZE -#define dg_configOTP_CODE_SIZE ( 58 * 1024) -#endif - -/** - * \brief RAM-block size in cached mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RAM_SIZE -#define dg_configOTP_CACHED_RAM_SIZE (64 * 1024) -#endif - -/** - * \brief Retained-RAM-0-block size in cached mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE -#define dg_configOTP_CACHED_RETRAM_0_SIZE ( 64 * 1024) -#endif - -/** - * \brief Retained-RAM-1-block size in cached mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE -#define dg_configOTP_CACHED_RETRAM_1_SIZE ( 0 * 1024) -#endif - -/** - * \brief Retained-RAM-0-block size in mirror mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RETRAM_0_SIZE -#define dg_configOTP_MIRROR_RETRAM_0_SIZE ( 48 * 1024) -#endif - -/** - * \brief Retained-RAM-1-block size in mirror mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE -#define dg_configOTP_MIRROR_RETRAM_1_SIZE ( 0 * 1024) -#endif - - - -/** - * \brief Retained-RAM-0-block size for optimal retention memory in cached mode, no product specific. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE -#define dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE ( 32 * 1024) -#endif - -/** - * \brief Retained-RAM-1-block size for optimal retention memory in cached mode, no product specific. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE -#define dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE ( 32 * 1024) -#endif - -/** - * \brief RAM-block size in mirror mode, no product specific. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RAM_SIZE -#define dg_configOTP_MIRROR_RAM_SIZE ( 16 * 1024) -#endif - -/** - * \brief Code size in OTP projects for DA14680/1-01. - * - * \note Code size cannot be more than 58K. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CODE_SIZE_AE -#define dg_configOTP_CODE_SIZE_AE dg_configOTP_CODE_SIZE -#endif - -/** - * \brief Code size in OTP projects for DA14682/3-00, DA15XXX-00. - * - * \note Code size cannot be more than 58K. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CODE_SIZE_BB -#define dg_configOTP_CODE_SIZE_BB dg_configOTP_CODE_SIZE -#endif - -/** - * \brief RAM-block size in cached mode for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RAM_SIZE_AE -#define dg_configOTP_CACHED_RAM_SIZE_AE dg_configOTP_CACHED_RAM_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size in cached mode for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE_AE -#define dg_configOTP_CACHED_RETRAM_0_SIZE_AE dg_configOTP_CACHED_RETRAM_0_SIZE -#endif - -/** - * \brief Retained-RAM-1-block size in cached mode for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE_AE -#define dg_configOTP_CACHED_RETRAM_1_SIZE_AE dg_configOTP_CACHED_RETRAM_1_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size for optimal retention memory in cached mode for DA14680/1-01. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE_AE -#define dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE_AE dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE -#endif - -/** - * \brief Retained-RAM-1-block size for optimal retention memory in cached mode for DA14680/1-01. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE_AE -#define dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE_AE dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE -#endif - -/** - * \brief RAM-block size in cached mode for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RAM_SIZE_BB -#define dg_configOTP_CACHED_RAM_SIZE_BB dg_configOTP_CACHED_RAM_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size in cached mode for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE_BB -#define dg_configOTP_CACHED_RETRAM_0_SIZE_BB dg_configOTP_CACHED_RETRAM_0_SIZE -#endif - -/** - * \brief Retained-RAM-1-block size in cached mode for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE_BB -#define dg_configOTP_CACHED_RETRAM_1_SIZE_BB dg_configOTP_CACHED_RETRAM_1_SIZE -#endif - -/** - * \brief RAM-block size in mirror mode for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RAM_SIZE_AE -#define dg_configOTP_MIRROR_RAM_SIZE_AE dg_configOTP_MIRROR_RAM_SIZE -#endif - -/** - * \brief Retained-RAM-1-block size in mirror mode for DA14680/1-01 - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE_AE -#define dg_configOTP_MIRROR_RETRAM_1_SIZE_AE dg_configOTP_MIRROR_RETRAM_1_SIZE -#endif - -/** - * \brief RAM-block size in mirror mode for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RAM_SIZE_BB -#define dg_configOTP_MIRROR_RAM_SIZE_BB dg_configOTP_MIRROR_RAM_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size in mirror mode for DA14682/3-00, DA15XXX-00 - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RETRAM_0_SIZE_BB -#define dg_configOTP_MIRROR_RETRAM_0_SIZE_BB dg_configOTP_MIRROR_RETRAM_0_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size in mirror mode for DA14682/3-00, DA15XXX-00 - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE_BB -#define dg_configOTP_MIRROR_RETRAM_1_SIZE_BB dg_configOTP_MIRROR_RETRAM_1_SIZE -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup QSPI_PROJECT_MEMORY_LAYOUT_SETTINGS - * - * \brief Memory layout configuration settings for a QSPI project - * \{ - */ - -/** - * \brief Code size in QSPI projects, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CODE_SIZE -#define dg_configQSPI_CODE_SIZE (128 * 1024) -#endif - -/** - * \brief RAM-block size in cached mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RAM_SIZE -#define dg_configQSPI_CACHED_RAM_SIZE ( 64 * 1024) -#endif - -/** - * \brief Retained-RAM-0-block size in cached mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE -#define dg_configQSPI_CACHED_RETRAM_0_SIZE ( 64 * 1024) -#endif - -/** - * \brief Retained-RAM-1-block size in cached mode, no product specific. - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE -#define dg_configQSPI_CACHED_RETRAM_1_SIZE ( 0 * 1024) -#endif - -/** - * \brief Retained-RAM-0-block size for optimal retention memory in cached mode, no product specific. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE -#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE ( 32 * 1024) -#endif - -/** - * \brief Retained-RAM-1-block size for optimal retention memory in cached mode, no product specific. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \note Defining the corresponding product-specific configuration macro will override - * this one. - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE -#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE ( 32 * 1024) -#endif - -/** - * \brief Code size in QSPI projects for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CODE_SIZE_AE -#define dg_configQSPI_CODE_SIZE_AE dg_configQSPI_CODE_SIZE -#endif - -/** - * \brief Code size in QSPI projects for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CODE_SIZE_BB -#define dg_configQSPI_CODE_SIZE_BB dg_configQSPI_CODE_SIZE -#endif - -/** - * \brief RAM-block size in cached mode for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RAM_SIZE_AE -#define dg_configQSPI_CACHED_RAM_SIZE_AE dg_configQSPI_CACHED_RAM_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size in cached mode for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE_AE -#define dg_configQSPI_CACHED_RETRAM_0_SIZE_AE dg_configQSPI_CACHED_RETRAM_0_SIZE -#endif - -/** - * \brief Retained-RAM-1-block size in cached mode for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE_AE -#define dg_configQSPI_CACHED_RETRAM_1_SIZE_AE dg_configQSPI_CACHED_RETRAM_1_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size for optimal retention memory in cached mode for DA14680/1-01. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE_AE -#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE_AE dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE -#endif - -/** - * \brief Retained-RAM-1-block size for optimal retention memory in cached mode for DA14680/1-01. - * - * \see dg_configOPTIMAL_RETRAM option - * - * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} - */ -#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE_AE -#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE_AE dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE -#endif - -/** - * \brief RAM-block size in cached mode for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RAM_SIZE_BB -#define dg_configQSPI_CACHED_RAM_SIZE_BB dg_configQSPI_CACHED_RAM_SIZE -#endif - -/** - * \brief Retained-RAM-0-block size in cached mode for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE_BB -#define dg_configQSPI_CACHED_RETRAM_0_SIZE_BB dg_configQSPI_CACHED_RETRAM_0_SIZE -#endif - -/** - * \brief Retained-RAM-1-block size in cached mode for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE_BB -#define dg_configQSPI_CACHED_RETRAM_1_SIZE_BB dg_configQSPI_CACHED_RETRAM_1_SIZE -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/** - * \addtogroup RAM_PROJECT_MEMORY_LAYOUT_SETTINGS - * - * \brief Memory layout configuration settings for a RAM project - * \{ - */ - -/** - * \brief Code size in RAM projects for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_CODE_SIZE_AE -#define dg_configRAM_CODE_SIZE_AE ( 79 * 1024) -#endif - -/** - * \brief RAM-block size for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_RAM_SIZE_AE -#define dg_configRAM_RAM_SIZE_AE ( 16 * 1024) -#endif - -/** - * \brief Retained-RAM-0-block size for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_RETRAM_0_SIZE_AE -#define dg_configRAM_RETRAM_0_SIZE_AE (128 * 1024 - dg_configRAM_CODE_SIZE_AE) -#endif - -/** - * \brief Retained-RAM-1-block size for DA14680/1-01. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_RETRAM_1_SIZE_AE -#define dg_configRAM_RETRAM_1_SIZE_AE ( 0 * 1024) -#endif - -/** - * \brief Code size in RAM projects for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_CODE_SIZE_BB -#define dg_configRAM_CODE_SIZE_BB (144 * 1024) -#endif - -/** - * \brief RAM-block size for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_RAM_SIZE_BB -#define dg_configRAM_RAM_SIZE_BB ( 15 * 1024) -#endif - -/** - * \brief Retained-RAM-0-block size for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_RETRAM_0_SIZE_BB -#define dg_configRAM_RETRAM_0_SIZE_BB ( 49 * 1024) -#endif - -/** - * \brief Retained-RAM-0-block size for DA14682/3-00, DA15XXX-00. - * - * \bsp_default_note{\bsp_config_option_app,} - */ -#ifndef dg_configRAM_RETRAM_1_SIZE_BB -#define dg_configRAM_RETRAM_1_SIZE_BB ( 0 * 1024) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} - */ - - -/** - * \} - */ - -#endif /* BSP_DEFAULTS_H_ */ - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h b/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h deleted file mode 100644 index 63dd13ce1..000000000 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup BSP_CONFIG - * \{ - * \addtogroup BSP_CONFIG_DEFINITIONS - * - * \brief Doxygen documentation is not yet available for this module. - * Please check the source code file(s) - * - *\{ - */ - -/** - **************************************************************************************** - * - * @file bsp_definitions.h - * - * @brief Board Support Package. System Configuration file definitions. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef BSP_DEFINITIONS_H_ -#define BSP_DEFINITIONS_H_ - - -/* ------------------------------------ Generic definitions ------------------------------------- */ - -#define LP_CLK_32000 0 -#define LP_CLK_32768 1 -#define LP_CLK_RCX 2 -#define LP_CLK_ANY 3 - -#define LP_CLK_IS_ANALOG 0 -#define LP_CLK_IS_DIGITAL 1 - -#define MODE_IS_MIRRORED 0 -#define MODE_IS_CACHED 1 -#define MODE_IS_RAM MODE_IS_MIRRORED - -#define NON_VOLATILE_IS_OTP 0 // Code is in OTP -#define NON_VOLATILE_IS_FLASH 1 // Code is in QSPI Flash -#define NON_VOLATILE_IS_NONE 2 // Debug mode! Code is in RAM! - -#define EXT_CRYSTAL_IS_16M 0 -#define EXT_CRYSTAL_IS_32M 1 - -#define DEVELOPMENT_MODE 0 // Code is built for debugging -#define PRODUCTION_MODE 1 // Code is built for production - -#define FLASH_IS_NOT_CONNECTED 0 -#define FLASH_CONNECTED_TO_1V8 1 -#define FLASH_CONNECTED_TO_1V8P 2 - -#define BATTERY_TYPE_2xNIMH 0 -#define BATTERY_TYPE_3xNIMH 1 -#define BATTERY_TYPE_LICOO2 2 // 2.5V discharge voltage, 4.20V charge voltage -#define BATTERY_TYPE_LIMN2O4 3 // 2.5V discharge voltage, 4.20V charge voltage -#define BATTERY_TYPE_NMC 4 // 2.5V discharge voltage, 4.20V charge voltage -#define BATTERY_TYPE_LIFEPO4 5 // 2.5V discharge voltage, 3.65V charge voltage -#define BATTERY_TYPE_LINICOAIO2 6 // 3.0V discharge voltage, 4.20V charge voltage -#define BATTERY_TYPE_CUSTOM 7 -#define BATTERY_TYPE_NO_RECHARGE 8 -#define BATTERY_TYPE_NO_BATTERY 9 - -#define BATTERY_TYPE_2xNIMH_ADC_VOLTAGE (2785) -#define BATTERY_TYPE_3xNIMH_ADC_VOLTAGE (4013) -#define BATTERY_TYPE_LICOO2_ADC_VOLTAGE (3440) -#define BATTERY_TYPE_LIMN2O4_ADC_VOLTAGE (3440) -#define BATTERY_TYPE_NMC_ADC_VOLTAGE (3440) -#define BATTERY_TYPE_LIFEPO4_ADC_VOLTAGE (2989) -#define BATTERY_TYPE_LINICOAIO2_ADC_VOLTAGE (3440) - -/* - * The supported chip revisions. - */ -#define BLACK_ORCA_IC_REV_AUTO (-1) -#define BLACK_ORCA_IC_REV_A 0 -#define BLACK_ORCA_IC_REV_B 1 - -/* - * The supported chip steppings. - */ -#define BLACK_ORCA_IC_STEP_AUTO (-1) -#define BLACK_ORCA_IC_STEP_A 0 -#define BLACK_ORCA_IC_STEP_B 1 -#define BLACK_ORCA_IC_STEP_C 2 -#define BLACK_ORCA_IC_STEP_D 3 -#define BLACK_ORCA_IC_STEP_E 7 - -/* - * Legacy DK motherboards, which are not supported by the SDK. - * The definitions exist just so that we don't break compilation of old projects. - */ -#define BLACK_ORCA_MB_REV_A 0 -#define BLACK_ORCA_MB_REV_B 1 -/* - * The supported DK motherboards. - */ -#define BLACK_ORCA_MB_REV_D 2 - -/* - * The cache associativity options. - */ -#define CACHE_ASSOC_AS_IS (-1) /// leave as set by the ROM booter -#define CACHE_ASSOC_DIRECT_MAP 0 /// direct-mapped -#define CACHE_ASSOC_2_WAY 1 /// 2-way set associative -#define CACHE_ASSOC_4_WAY 2 /// 4-way set associative - -/* - * The cache line size options. - */ -#define CACHE_LINESZ_AS_IS (-1) /// leave as set by the ROM booter -#define CACHE_LINESZ_8_BYTES 0 /// 8 bytes -#define CACHE_LINESZ_16_BYTES 1 /// 16 bytes -#define CACHE_LINESZ_32_BYTES 2 /// 32 bytes - -/* - * The supported RF Front-End Modules - */ -#define FEM_NOFEM 0 -#define FEM_SKY66112_11 1 - -/* - * The BLE event notification user hook types - */ -#define BLE_EVENT_NOTIF_USER_ISR 0 /// User-defined hooks directly from ISR context -#define BLE_EVENT_NOTIF_USER_TASK 1 /// Notification of the user task, using task notifications. - -#endif /* BSP_DEFINITIONS_H_ */ - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h b/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h deleted file mode 100644 index 1a9b24033..000000000 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h +++ /dev/null @@ -1,149 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup BSP_CONFIG - * \{ - * \addtogroup RF_FEM - * - * \brief RF Front-End module confguration - * - *\{ - */ - -/** - *************************************************************************************** - * - * @file bsp_fem.h - * - * @brief Board Support Package. RF Front-End Module definitions. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - *************************************************************************************** - */ - -#ifndef BSP_FEM_H_ -#define BSP_FEM_H_ - -/* ------------------------------- RF FEM driver (SKY66112-11) configuration settings ----------- */ - -#ifdef dg_configFEM_DLG_REF_BOARD - -#define dg_configFEM FEM_SKY66112_11 - -#if dg_configPOWER_1V8P == 0 -#warning Setting dg_configPOWER_1V8P to 1 for FEM to work -#undef dg_configPOWER_1V8P -#define dg_configPOWER_1V8P 1 -#endif - -#define dg_configFEM_SKY66112_11_FEM_BIAS_V18P -#define dg_configFEM_SKY66112_11_FEM_BIAS2_V18 - -#ifndef dg_configFEM_SKY66112_11_CSD_PORT -#define dg_configFEM_SKY66112_11_CSD_PORT HW_GPIO_PORT_4 -#endif - -#ifndef dg_configFEM_SKY66112_11_CSD_PIN -#define dg_configFEM_SKY66112_11_CSD_PIN HW_GPIO_PIN_3 -#endif - -#ifndef dg_configFEM_SKY66112_11_CPS_PORT -#define dg_configFEM_SKY66112_11_CPS_PORT HW_GPIO_PORT_4 -#endif - -#ifndef dg_configFEM_SKY66112_11_CPS_PIN -#define dg_configFEM_SKY66112_11_CPS_PIN HW_GPIO_PIN_6 -#endif - -#ifndef dg_configFEM_SKY66112_11_CRX_PORT -#define dg_configFEM_SKY66112_11_CRX_PORT HW_GPIO_PORT_4 -#endif - -#ifndef dg_configFEM_SKY66112_11_CRX_PIN -#define dg_configFEM_SKY66112_11_CRX_PIN HW_GPIO_PIN_2 -#endif - -#ifndef dg_configFEM_SKY66112_11_CTX_PORT -#define dg_configFEM_SKY66112_11_CTX_PORT HW_GPIO_PORT_4 -#endif - -#ifndef dg_configFEM_SKY66112_11_CTX_PIN -#define dg_configFEM_SKY66112_11_CTX_PIN HW_GPIO_PIN_5 -#endif - -#ifndef dg_configFEM_SKY66112_11_CHL_PORT -#define dg_configFEM_SKY66112_11_CHL_PORT HW_GPIO_PORT_4 -#endif - -#ifndef dg_configFEM_SKY66112_11_CHL_PIN -#define dg_configFEM_SKY66112_11_CHL_PIN HW_GPIO_PIN_4 -#endif - -#ifndef dg_configFEM_SKY66112_11_ANTSEL_PORT -#define dg_configFEM_SKY66112_11_ANTSEL_PORT HW_GPIO_PORT_4 -#endif - -#ifndef dg_configFEM_SKY66112_11_ANTSEL_PIN -#define dg_configFEM_SKY66112_11_ANTSEL_PIN HW_GPIO_PIN_0 -#endif - -#endif /* dg_configFEM_DLG_REF_BOARD */ - -#ifndef dg_configFEM -#define dg_configFEM FEM_NOFEM -#endif - -#if dg_configFEM == FEM_SKY66112_11 -#ifndef dg_configFEM_SKY66112_11_CSD_USE_DCF -#define dg_configFEM_SKY66112_11_CSD_USE_DCF 1 -#endif - -#ifndef dg_configFEM_SKY66112_11_TXSET_DCF -#define dg_configFEM_SKY66112_11_TXSET_DCF 47 -#endif - -#ifndef dg_configFEM_SKY66112_11_TXRESET_DCF -#define dg_configFEM_SKY66112_11_TXRESET_DCF 0 -#endif - -#ifndef dg_configFEM_SKY66112_11_RXSET_DCF -#define dg_configFEM_SKY66112_11_RXSET_DCF 1 -#endif - -#ifndef dg_configFEM_SKY66112_11_RXRESET_DCF -#define dg_configFEM_SKY66112_11_RXRESET_DCF 20 -#endif -#endif /* dg_configFEM == FEM_SKY66112_11 */ - -#endif /* BSP_FEM_H_ */ - -/** -\} -\} -\} -*/ - diff --git a/third_party/dialog/DialogSDK/bsp/include/ARMCM0.h b/third_party/dialog/DialogSDK/bsp/include/ARMCM0.h deleted file mode 100644 index 22e3be182..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/ARMCM0.h +++ /dev/null @@ -1,43 +0,0 @@ -/**************************************************************************//** - * @file ARMCM0.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * ARMCM0 Device Series - * @version V3.00 - * @date 16. October 2015 - ******************************************************************************/ -/* Copyright (c) 2011 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef ARMCM0_H -#define ARMCM0_H - - -#include /* Cortex-M0 processor and core peripherals */ -#include "system_ARMCM0.h" /* System Header */ - -#endif /* ARMCM0_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/DA14680BB.h b/third_party/dialog/DialogSDK/bsp/include/DA14680BB.h deleted file mode 100755 index 801e5161a..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/DA14680BB.h +++ /dev/null @@ -1,12153 +0,0 @@ - /** - **************************************************************************************** - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * @file DA14680BB.h - * - * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for - * DA14680BB from Dialog. - * - * @version V1.2 - * @date 14. June 2017 - * - * @note Generated with SVDConv V2.87l - * from CMSIS SVD File 'DA14680BB.xml' Version 1.2, - * - ***************************************************************************************** - */ - - - -/** @addtogroup Dialog - * @{ - */ - -/** @addtogroup DA14680BB - * @{ - */ - -#ifndef DA14680BB_H -#define DA14680BB_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -/** - * @brief Interrupt Number Definition - */ - -typedef enum { -/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* -------------------- DA14680BB Specific Interrupt Numbers -------------------- */ - BLE_WAKEUP_LP_IRQn = 0, /*!< 0 BLE_WAKEUP_LP */ - BLE_GEN_IRQn = 1, /*!< 1 BLE_GEN */ - FTDF_WAKEUP_IRQn = 2, /*!< 2 FTDF_WAKEUP */ - FTDF_GEN_IRQn = 3, /*!< 3 FTDF_GEN */ - RFCAL_IRQn = 4, /*!< 4 RFCAL */ - COEX_IRQn = 5, /*!< 5 COEX */ - CRYPTO_IRQn = 6, /*!< 6 CRYPTO */ - MRM_IRQn = 7, /*!< 7 MRM */ - UART_IRQn = 8, /*!< 8 UART */ - UART2_IRQn = 9, /*!< 9 UART2 */ - I2C_IRQn = 10, /*!< 10 I2C */ - I2C2_IRQn = 11, /*!< 11 I2C2 */ - SPI_IRQn = 12, /*!< 12 SPI */ - SPI2_IRQn = 13, /*!< 13 SPI2 */ - ADC_IRQn = 14, /*!< 14 ADC */ - KEYBRD_IRQn = 15, /*!< 15 KEYBRD */ - IRGEN_IRQn = 16, /*!< 16 IRGEN */ - WKUP_GPIO_IRQn = 17, /*!< 17 WKUP_GPIO */ - SWTIM0_IRQn = 18, /*!< 18 SWTIM0 */ - SWTIM1_IRQn = 19, /*!< 19 SWTIM1 */ - QUADEC_IRQn = 20, /*!< 20 QUADEC */ - USB_IRQn = 21, /*!< 21 USB */ - PCM_IRQn = 22, /*!< 22 PCM */ - SRC_IN_IRQn = 23, /*!< 23 SRC_IN */ - SRC_OUT_IRQn = 24, /*!< 24 SRC_OUT */ - VBUS_IRQn = 25, /*!< 25 VBUS */ - DMA_IRQn = 26, /*!< 26 DMA */ - RF_DIAG_IRQn = 27, /*!< 27 RF_DIAG */ - TRNG_IRQn = 28, /*!< 28 TRNG */ - DCDC_IRQn = 29, /*!< 29 DCDC */ - XTAL16RDY_IRQn = 30, /*!< 30 XTAL16RDY */ - PLL_LOCK_IRQn = 31 /*!< 31 PLL_LOCK */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS_DA14680BB - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ -#define __CM0_REV 0x0100 /*!< Cortex-M0 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_DA14680.h" /*!< DA14680BB System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers_DA14680BB - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - - - - - - - - -/* ================================================================================ */ -/* ================ AES_HASH ================ */ -/* ================================================================================ */ - - -/** - * @brief AES_HASH registers (AES_HASH) - */ - -typedef struct { /*!< (@ 0x40020000) AES_HASH Structure */ - __IO uint32_t CRYPTO_CTRL_REG; /*!< (@ 0x40020000) Crypto Control register */ - __IO uint32_t CRYPTO_START_REG; /*!< (@ 0x40020004) Crypto Start calculation */ - __IO uint32_t CRYPTO_FETCH_ADDR_REG; /*!< (@ 0x40020008) Crypto DMA fetch register */ - __IO uint32_t CRYPTO_LEN_REG; /*!< (@ 0x4002000C) Crypto Length of the input block in bytes */ - __IO uint32_t CRYPTO_DEST_ADDR_REG; /*!< (@ 0x40020010) Crypto DMA destination memory */ - __IO uint32_t CRYPTO_STATUS_REG; /*!< (@ 0x40020014) Crypto Status register */ - __IO uint32_t CRYPTO_CLRIRQ_REG; /*!< (@ 0x40020018) Crypto Clear interrupt request */ - __IO uint32_t CRYPTO_MREG0_REG; /*!< (@ 0x4002001C) Crypto Mode depended register 0 */ - __IO uint32_t CRYPTO_MREG1_REG; /*!< (@ 0x40020020) Crypto Mode depended register 1 */ - __IO uint32_t CRYPTO_MREG2_REG; /*!< (@ 0x40020024) Crypto Mode depended register 2 */ - __IO uint32_t CRYPTO_MREG3_REG; /*!< (@ 0x40020028) Crypto Mode depended register 3 */ - __I uint32_t RESERVED[53]; - __IO uint32_t CRYPTO_KEYS_START; /*!< (@ 0x40020100) Crypto First position of the AES keys storage - memory */ -} AES_HASH_Type; - - -/* ================================================================================ */ -/* ================ ANAMISC ================ */ -/* ================================================================================ */ - - -/** - * @brief ANAMISC registers (ANAMISC) - */ - -typedef struct { /*!< (@ 0x50001B00) ANAMISC Structure */ - __I uint16_t RESERVED; - __IO uint16_t ANA_TEST_REG; /*!< (@ 0x50001B02) Analog test registers */ - __I uint32_t RESERVED1; - __IO uint16_t CHARGER_CTRL1_REG; /*!< (@ 0x50001B08) Charger control register 1 */ - __IO uint16_t CHARGER_CTRL2_REG; /*!< (@ 0x50001B0A) Charger control register 2 */ - __IO uint16_t CHARGER_STATUS_REG; /*!< (@ 0x50001B0C) Charger status and trimming register */ - __I uint16_t RESERVED2[25]; - __IO uint16_t SOC_CTRL1_REG; /*!< (@ 0x50001B40) Fuel Gauge Control register 1 */ - __IO uint16_t SOC_CTRL2_REG; /*!< (@ 0x50001B42) Fuel Gauge Control register 2 */ - __IO uint16_t SOC_CTRL3_REG; /*!< (@ 0x50001B44) Fuel Gauge Control register 3 */ - __IO uint16_t SOC_ADD2CH_REG; /*!< (@ 0x50001B46) Fuel Gauge manually add extra charge to SOC_CHARGE_CNTRx_RE - G */ - __IO uint16_t SOC_CHARGE_CNTR1_REG; /*!< (@ 0x50001B48) Fuel Gauge Charge counter bits 15-0 */ - __IO uint16_t SOC_CHARGE_CNTR2_REG; /*!< (@ 0x50001B4A) Fuel Gauge Charge counter bits 31-16 */ - __IO uint16_t SOC_CHARGE_CNTR3_REG; /*!< (@ 0x50001B4C) Fuel Gauge Charge counter bits 39-32 */ - __I uint16_t RESERVED3; - __IO uint16_t SOC_CHARGE_AVG_REG; /*!< (@ 0x50001B50) Fuel Gauge Average charge counter */ - __IO uint16_t SOC_STATUS_REG; /*!< (@ 0x50001B52) Fuel Gauge Status register */ - __IO uint16_t SOC_EXT_IN_REG; /*!< (@ 0x50001B54) Fuel Gauge input test register */ - __IO uint16_t SOC_EXT_OUT_REG; /*!< (@ 0x50001B56) Fuel Gauge output test register */ - __I uint32_t RESERVED4[2]; - __IO uint16_t CLK_REF_SEL_REG; /*!< (@ 0x50001B60) Select clock for oscillator calibration */ - __IO uint16_t CLK_REF_CNT_REG; /*!< (@ 0x50001B62) Count value for oscillator calibration */ - __IO uint16_t CLK_REF_VAL_L_REG; /*!< (@ 0x50001B64) DIVN reference cycles, lower 16 bits */ - __IO uint16_t CLK_REF_VAL_H_REG; /*!< (@ 0x50001B66) DIVN reference cycles, upper 16 bits */ -} ANAMISC_Type; - - -/* ================================================================================ */ -/* ================ APU ================ */ -/* ================================================================================ */ - - -/** - * @brief APU registers (APU) - */ - -typedef struct { /*!< (@ 0x50004000) APU Structure */ - __IO uint32_t SRC1_CTRL_REG; /*!< (@ 0x50004000) SRC1 control register */ - __IO uint32_t SRC1_IN_FS_REG; /*!< (@ 0x50004004) SRC1 Sample input rate */ - __IO uint32_t SRC1_OUT_FS_REG; /*!< (@ 0x50004008) SRC1 Sample output rate */ - __IO uint32_t SRC1_IN1_REG; /*!< (@ 0x5000400C) SRC1 data in 1 */ - __IO uint32_t SRC1_IN2_REG; /*!< (@ 0x50004010) SRC1 data in 2 */ - __IO uint32_t SRC1_OUT1_REG; /*!< (@ 0x50004014) SRC1 data out 1 */ - __IO uint32_t SRC1_OUT2_REG; /*!< (@ 0x50004018) SRC1 data out 2 */ - __IO uint32_t APU_MUX_REG; /*!< (@ 0x5000401C) APU mux register */ - __IO uint32_t COEF10_SET1_REG; /*!< (@ 0x50004020) SRC coefficient 1,0 set 1 */ - __IO uint32_t COEF32_SET1_REG; /*!< (@ 0x50004024) SRC coefficient 3,2 set 1 */ - __IO uint32_t COEF54_SET1_REG; /*!< (@ 0x50004028) SRC coefficient 5,4 set 1 */ - __IO uint32_t COEF76_SET1_REG; /*!< (@ 0x5000402C) SRC coefficient 7,6 set 1 */ - __IO uint32_t COEF98_SET1_REG; /*!< (@ 0x50004030) SRC coefficient 9,8 set 1 */ - __IO uint32_t COEF0A_SET1_REG; /*!< (@ 0x50004034) SRC coefficient 10 set 1 */ - __I uint32_t RESERVED[50]; - __IO uint32_t PCM1_CTRL_REG; /*!< (@ 0x50004100) PCM1 Control register */ - __IO uint32_t PCM1_IN1_REG; /*!< (@ 0x50004104) PCM1 data in 1 */ - __IO uint32_t PCM1_IN2_REG; /*!< (@ 0x50004108) PCM1 data in 2 */ - __IO uint32_t PCM1_OUT1_REG; /*!< (@ 0x5000410C) PCM1 data out 1 */ - __IO uint32_t PCM1_OUT2_REG; /*!< (@ 0x50004110) PCM1 data out 2 */ -} APU_Type; - - -/* ================================================================================ */ -/* ================ BLE ================ */ -/* ================================================================================ */ - - -/** - * @brief BLE registers (BLE) - */ - -typedef struct { /*!< (@ 0x40000000) BLE Structure */ - __IO uint32_t BLE_RWBLECNTL_REG; /*!< (@ 0x40000000) BLE Control register */ - __IO uint32_t BLE_VERSION_REG; /*!< (@ 0x40000004) Version register */ - __IO uint32_t BLE_RWBLECONF_REG; /*!< (@ 0x40000008) Configuration register */ - __IO uint32_t BLE_INTCNTL_REG; /*!< (@ 0x4000000C) Interrupt controller register */ - __IO uint32_t BLE_INTSTAT_REG; /*!< (@ 0x40000010) Interrupt status register */ - __IO uint32_t BLE_INTRAWSTAT_REG; /*!< (@ 0x40000014) Interrupt raw status register */ - __IO uint32_t BLE_INTACK_REG; /*!< (@ 0x40000018) Interrupt acknowledge register */ - __IO uint32_t BLE_BASETIMECNT_REG; /*!< (@ 0x4000001C) Base time reference counter */ - __IO uint32_t BLE_FINETIMECNT_REG; /*!< (@ 0x40000020) Fine time reference counter */ - __IO uint32_t BLE_BDADDRL_REG; /*!< (@ 0x40000024) BLE device address LSB register */ - __IO uint32_t BLE_BDADDRU_REG; /*!< (@ 0x40000028) BLE device address MSB register */ - __IO uint32_t BLE_CURRENTRXDESCPTR_REG; /*!< (@ 0x4000002C) Rx Descriptor Pointer for the Receive Buffer - Chained List */ - __IO uint32_t BLE_DEEPSLCNTL_REG; /*!< (@ 0x40000030) Deep-Sleep control register */ - __IO uint32_t BLE_DEEPSLWKUP_REG; /*!< (@ 0x40000034) Time (measured in Low Power clock cycles) in - Deep Sleep Mode before waking-up the device */ - __IO uint32_t BLE_DEEPSLSTAT_REG; /*!< (@ 0x40000038) Duration of the last deep sleep phase register */ - __IO uint32_t BLE_ENBPRESET_REG; /*!< (@ 0x4000003C) Time in low power oscillator cycles register */ - __IO uint32_t BLE_FINECNTCORR_REG; /*!< (@ 0x40000040) Phase correction value register */ - __IO uint32_t BLE_BASETIMECNTCORR_REG; /*!< (@ 0x40000044) Base Time Counter */ - __I uint32_t RESERVED[2]; - __IO uint32_t BLE_DIAGCNTL_REG; /*!< (@ 0x40000050) Diagnostics Register */ - __IO uint32_t BLE_DIAGSTAT_REG; /*!< (@ 0x40000054) Debug use only */ - __IO uint32_t BLE_DEBUGADDMAX_REG; /*!< (@ 0x40000058) Upper limit for the memory zone */ - __IO uint32_t BLE_DEBUGADDMIN_REG; /*!< (@ 0x4000005C) Lower limit for the memory zone */ - __IO uint32_t BLE_ERRORTYPESTAT_REG; /*!< (@ 0x40000060) Error Type Status registers */ - __IO uint32_t BLE_SWPROFILING_REG; /*!< (@ 0x40000064) Software Profiling register */ - __I uint32_t RESERVED1[2]; - __IO uint32_t BLE_RADIOCNTL0_REG; /*!< (@ 0x40000070) Radio interface control register */ - __IO uint32_t BLE_RADIOCNTL1_REG; /*!< (@ 0x40000074) Radio interface control register */ - __IO uint32_t BLE_RADIOCNTL2_REG; /*!< (@ 0x40000078) Radio interface control register */ - __IO uint32_t BLE_RADIOCNTL3_REG; /*!< (@ 0x4000007C) Radio interface control register */ - __IO uint32_t BLE_RADIOPWRUPDN_REG; /*!< (@ 0x40000080) RX/TX power up/down phase register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t BLE_ADVCHMAP_REG; /*!< (@ 0x40000090) Advertising Channel Map */ - __I uint32_t RESERVED3[3]; - __IO uint32_t BLE_ADVTIM_REG; /*!< (@ 0x400000A0) Advertising Packet Interval */ - __IO uint32_t BLE_ACTSCANSTAT_REG; /*!< (@ 0x400000A4) Active scan register */ - __I uint32_t RESERVED4[2]; - __IO uint32_t BLE_WLPUBADDPTR_REG; /*!< (@ 0x400000B0) Start address of public devices list */ - __IO uint32_t BLE_WLPRIVADDPTR_REG; /*!< (@ 0x400000B4) Start address of private devices list */ - __IO uint32_t BLE_WLNBDEV_REG; /*!< (@ 0x400000B8) Devices in white list */ - __I uint32_t RESERVED5; - __IO uint32_t BLE_AESCNTL_REG; /*!< (@ 0x400000C0) Start AES register */ - __IO uint32_t BLE_AESKEY31_0_REG; /*!< (@ 0x400000C4) AES encryption key */ - __IO uint32_t BLE_AESKEY63_32_REG; /*!< (@ 0x400000C8) AES encryption key */ - __IO uint32_t BLE_AESKEY95_64_REG; /*!< (@ 0x400000CC) AES encryption key */ - __IO uint32_t BLE_AESKEY127_96_REG; /*!< (@ 0x400000D0) AES encryption key */ - __IO uint32_t BLE_AESPTR_REG; /*!< (@ 0x400000D4) Pointer to the block to encrypt/decrypt */ - __IO uint32_t BLE_TXMICVAL_REG; /*!< (@ 0x400000D8) AES / CCM plain MIC value */ - __IO uint32_t BLE_RXMICVAL_REG; /*!< (@ 0x400000DC) AES / CCM plain MIC value */ - __IO uint32_t BLE_RFTESTCNTL_REG; /*!< (@ 0x400000E0) RF Testing Register */ - __IO uint32_t BLE_RFTESTTXSTAT_REG; /*!< (@ 0x400000E4) RF Testing Register */ - __IO uint32_t BLE_RFTESTRXSTAT_REG; /*!< (@ 0x400000E8) RF Testing Register */ - __I uint32_t RESERVED6; - __IO uint32_t BLE_TIMGENCNTL_REG; /*!< (@ 0x400000F0) Timing Generator Register */ - __IO uint32_t BLE_GROSSTIMTGT_REG; /*!< (@ 0x400000F4) Gross Timer Target value */ - __IO uint32_t BLE_FINETIMTGT_REG; /*!< (@ 0x400000F8) Fine Timer Target value */ - __IO uint32_t BLE_SAMPLECLK_REG; /*!< (@ 0x400000FC) Samples the Base Time Counter */ - __IO uint32_t BLE_COEXIFCNTL0_REG; /*!< (@ 0x40000100) Coexistence interface Control 0 Register */ - __IO uint32_t BLE_COEXIFCNTL1_REG; /*!< (@ 0x40000104) Coexistence interface Control 1 Register */ - __IO uint32_t BLE_BLEMPRIO0_REG; /*!< (@ 0x40000108) Coexistence interface Priority 0 Register */ - __IO uint32_t BLE_BLEMPRIO1_REG; /*!< (@ 0x4000010C) Coexistence interface Priority 1 Register */ - __I uint32_t RESERVED7[60]; - __IO uint32_t BLE_CNTL2_REG; /*!< (@ 0x40000200) BLE Control Register 2 */ - __I uint32_t RESERVED8; - __IO uint32_t BLE_EM_BASE_REG; /*!< (@ 0x40000208) Exchange Memory Base Register */ - __IO uint32_t BLE_DIAGCNTL2_REG; /*!< (@ 0x4000020C) Debug use only */ - __IO uint32_t BLE_DIAGCNTL3_REG; /*!< (@ 0x40000210) Debug use only */ -} BLE_Type; - - -/* ================================================================================ */ -/* ================ CACHE ================ */ -/* ================================================================================ */ - - -/** - * @brief CACHE registers (CACHE) - */ - -typedef struct { /*!< (@ 0x400C3000) CACHE Structure */ - __IO uint32_t CACHE_CTRL1_REG; /*!< (@ 0x400C3000) Cache control register 1 */ - __IO uint32_t CACHE_LNSIZECFG_REG; /*!< (@ 0x400C3004) Cache line size configuration register */ - __IO uint32_t CACHE_ASSOCCFG_REG; /*!< (@ 0x400C3008) Cache associativity configuration register */ - __I uint32_t RESERVED[5]; - __IO uint32_t CACHE_CTRL2_REG; /*!< (@ 0x400C3020) Cache control register 2 */ - __IO uint32_t CACHE_CTRL3_REG; /*!< (@ 0x400C3024) Cache control register 3 (for the Cache Controller - configuration reset values) */ - __IO uint32_t CACHE_MRM_HITS_REG; /*!< (@ 0x400C3028) Cache MRM (Miss Rate Monitor) HITS register */ - __IO uint32_t CACHE_MRM_MISSES_REG; /*!< (@ 0x400C302C) Cache MRM (Miss Rate Monitor) MISSES register */ - __IO uint32_t CACHE_MRM_CTRL_REG; /*!< (@ 0x400C3030) Cache MRM (Miss Rate Monitor) CONTROL register */ - __IO uint32_t CACHE_MRM_TINT_REG; /*!< (@ 0x400C3034) Cache MRM (Miss Rate Monitor) TIME INTERVAL register */ - __IO uint32_t CACHE_MRM_THRES_REG; /*!< (@ 0x400C3038) Cache MRM (Miss Rate Monitor) THRESHOLD register */ - __I uint32_t RESERVED1[5]; - __IO uint32_t SWD_RESET_REG; /*!< (@ 0x400C3050) SWD HW reset control register */ -} CACHE_Type; - - -/* ================================================================================ */ -/* ================ CHIP_VERSION ================ */ -/* ================================================================================ */ - - -/** - * @brief CHIP_VERSION registers (CHIP_VERSION) - */ - -typedef struct { /*!< (@ 0x50003200) CHIP_VERSION Structure */ - __IO uint8_t CHIP_ID1_REG; /*!< (@ 0x50003200) Chip identification register 1. */ - __IO uint8_t CHIP_ID2_REG; /*!< (@ 0x50003201) Chip identification register 2. */ - __IO uint8_t CHIP_ID3_REG; /*!< (@ 0x50003202) Chip identification register 3. */ - __IO uint8_t CHIP_SWC_REG; /*!< (@ 0x50003203) Software compatibility register. */ - __IO uint8_t CHIP_REVISION_REG; /*!< (@ 0x50003204) Chip revision register. */ - __IO uint8_t CHIP_CONFIG1_REG; /*!< (@ 0x50003205) Chip configuration register 1. */ - __IO uint8_t CHIP_CONFIG2_REG; /*!< (@ 0x50003206) Chip configuration register 2. */ - __IO uint8_t CHIP_CONFIG3_REG; /*!< (@ 0x50003207) Chip configuration register 3. */ - __I uint16_t RESERVED; - __IO uint8_t CHIP_TEST1_REG; /*!< (@ 0x5000320A) Chip test register 1. */ - __IO uint8_t CHIP_TEST2_REG; /*!< (@ 0x5000320B) Chip test register 2. */ - __IO uint8_t CHIP_TEST3_REG; /*!< (@ 0x5000320C) Chip test register 3. */ -} CHIP_VERSION_Type; - - -/* ================================================================================ */ -/* ================ COEX ================ */ -/* ================================================================================ */ - - -/** - * @brief COEX registers (COEX) - */ - -typedef struct { /*!< (@ 0x50002F00) COEX Structure */ - __IO uint16_t COEX_CTRL_REG; /*!< (@ 0x50002F00) COEX Control Register */ - __IO uint16_t COEX_STAT_REG; /*!< (@ 0x50002F02) COEX Status Register */ - __IO uint16_t COEX_STAT2_REG; /*!< (@ 0x50002F04) COEX Status 2 Register */ - __IO uint16_t COEX_INT_MASK_REG; /*!< (@ 0x50002F06) COEX Interrupt Mask Register */ - __IO uint16_t COEX_INT_STAT_REG; /*!< (@ 0x50002F08) COEX Interrupt Status Register */ - __IO uint16_t COEX_BLE_PTI_REG; /*!< (@ 0x50002F0A) COEX BLE PTI Control Register */ - __IO uint16_t COEX_FTDF_PTI_REG; /*!< (@ 0x50002F0C) COEX FTDF PTI Control Register */ - __I uint16_t RESERVED[2]; - __IO uint16_t COEX_PRI1_REG; /*!< (@ 0x50002F12) COEX Priority Register */ - __IO uint16_t COEX_PRI2_REG; /*!< (@ 0x50002F14) COEX Priority Register */ - __IO uint16_t COEX_PRI3_REG; /*!< (@ 0x50002F16) COEX Priority Register */ - __IO uint16_t COEX_PRI4_REG; /*!< (@ 0x50002F18) COEX Priority Register */ - __IO uint16_t COEX_PRI5_REG; /*!< (@ 0x50002F1A) COEX Priority Register */ - __IO uint16_t COEX_PRI6_REG; /*!< (@ 0x50002F1C) COEX Priority Register */ - __IO uint16_t COEX_PRI7_REG; /*!< (@ 0x50002F1E) COEX Priority Register */ - __IO uint16_t COEX_PRI8_REG; /*!< (@ 0x50002F20) COEX Priority Register */ - __IO uint16_t COEX_PRI9_REG; /*!< (@ 0x50002F22) COEX Priority Register */ - __IO uint16_t COEX_PRI10_REG; /*!< (@ 0x50002F24) COEX Priority Register */ - __IO uint16_t COEX_PRI11_REG; /*!< (@ 0x50002F26) COEX Priority Register */ - __IO uint16_t COEX_PRI12_REG; /*!< (@ 0x50002F28) COEX Priority Register */ - __IO uint16_t COEX_PRI13_REG; /*!< (@ 0x50002F2A) COEX Priority Register */ - __IO uint16_t COEX_PRI14_REG; /*!< (@ 0x50002F2C) COEX Priority Register */ - __IO uint16_t COEX_PRI15_REG; /*!< (@ 0x50002F2E) COEX Priority Register */ -} COEX_Type; - - -/* ================================================================================ */ -/* ================ CRG_PER ================ */ -/* ================================================================================ */ - - -/** - * @brief CRG_PER registers (CRG_PER) - */ - -typedef struct { /*!< (@ 0x50001C00) CRG_PER Structure */ - __I uint32_t RESERVED; - __IO uint16_t CLK_PER_REG; /*!< (@ 0x50001C04) Peripheral divider register */ - __I uint16_t RESERVED1[29]; - __IO uint16_t PCM_DIV_REG; /*!< (@ 0x50001C40) PCM divider and enables */ - __IO uint16_t PCM_FDIV_REG; /*!< (@ 0x50001C42) PCM fractional division register */ - __IO uint16_t PDM_DIV_REG; /*!< (@ 0x50001C44) PDM divider and enables */ - __IO uint16_t SRC_DIV_REG; /*!< (@ 0x50001C46) SRC divider and enables */ - __IO uint16_t EH_REG; /*!< (@ 0x50001C48) EH_REG */ - __IO uint16_t USBPAD_REG; /*!< (@ 0x50001C4A) USB pads control register */ -} CRG_PER_Type; - - -/* ================================================================================ */ -/* ================ CRG_TOP ================ */ -/* ================================================================================ */ - - -/** - * @brief CRG_TOP registers (CRG_TOP) - */ - -typedef struct { /*!< (@ 0x50000000) CRG_TOP Structure */ - __IO uint16_t CLK_AMBA_REG; /*!< (@ 0x50000000) HCLK, PCLK, divider and clock gates */ - __IO uint16_t CLK_FREQ_TRIM_REG; /*!< (@ 0x50000002) Xtal frequency trimming register. */ - __I uint32_t RESERVED; - __IO uint16_t CLK_RADIO_REG; /*!< (@ 0x50000008) Radio PLL control register */ - __IO uint16_t CLK_CTRL_REG; /*!< (@ 0x5000000A) Clock control register */ - __IO uint16_t CLK_TMR_REG; /*!< (@ 0x5000000C) Clock control for the timers */ - __I uint16_t RESERVED1; - __IO uint16_t PMU_CTRL_REG; /*!< (@ 0x50000010) Power Management Unit control register */ - __IO uint16_t SYS_CTRL_REG; /*!< (@ 0x50000012) System Control register */ - __IO uint16_t SYS_STAT_REG; /*!< (@ 0x50000014) System status register */ - __IO uint16_t TRIM_CTRL_REG; /*!< (@ 0x50000016) Control trimming of the XTAL16M */ - __I uint32_t RESERVED2[2]; - __IO uint16_t CLK_32K_REG; /*!< (@ 0x50000020) 32 kHz oscillator register */ - __IO uint16_t CLK_16M_REG; /*!< (@ 0x50000022) 16 MHz RC and xtal oscillator register */ - __IO uint16_t CLK_RCX20K_REG; /*!< (@ 0x50000024) RCX-oscillator control register */ - __I uint16_t RESERVED3; - __IO uint16_t BANDGAP_REG; /*!< (@ 0x50000028) bandgap trimming */ - __IO uint16_t ANA_STATUS_REG; /*!< (@ 0x5000002A) status bit of analog (power management) circuits */ - __IO uint16_t STARTUP_STATUS_REG; /*!< (@ 0x5000002C) Startup timeout bits */ - __I uint16_t RESERVED4; - __IO uint16_t VBUS_IRQ_MASK_REG; /*!< (@ 0x50000030) IRQ masking */ - __IO uint16_t VBUS_IRQ_CLEAR_REG; /*!< (@ 0x50000032) Clear pending IRQ register */ - __IO uint16_t BOD_CTRL_REG; /*!< (@ 0x50000034) Brown Out Detection control register */ - __IO uint16_t BOD_CTRL2_REG; /*!< (@ 0x50000036) Brown Out Detection control register */ - __IO uint16_t BOD_STATUS_REG; /*!< (@ 0x50000038) Brown Out Detection status register */ - __IO uint16_t LDO_CTRL1_REG; /*!< (@ 0x5000003A) LDO control register */ - __IO uint16_t LDO_CTRL2_REG; /*!< (@ 0x5000003C) LDO control register */ - __IO uint16_t SLEEP_TIMER_REG; /*!< (@ 0x5000003E) Timer for regulated sleep */ - __IO uint16_t POWER_CTRL_REG; /*!< (@ 0x50000040) Power control register */ - __IO uint16_t POR_VBAT_CTRL_REG; /*!< (@ 0x50000042) Controls the POR on VBAT */ - __I uint32_t RESERVED5[3]; - __IO uint16_t XTALRDY_CTRL_REG; /*!< (@ 0x50000050) Control register for XTALRDY IRQ */ - __IO uint16_t XTALRDY_STAT_REG; /*!< (@ 0x50000052) Difference between XTAL_OK and XTALRDY_IRQ in - LP clock cycles */ - __IO uint16_t LDO_CTRL3_REG; /*!< (@ 0x50000054) Retention LDO control register */ - __IO uint16_t XTAL16M_CTRL_REG; /*!< (@ 0x50000056) Control register for XTAL16M */ - __IO uint16_t XTAL16M_START_REG; /*!< (@ 0x50000058) Xtal frequency trimming register during startup */ - __IO uint16_t XTAL16M_RAMP_REG; /*!< (@ 0x5000005A) Xtal frequency trimming register during ramping */ - __IO uint16_t XTAL16M_TRSTAT_REG; /*!< (@ 0x5000005C) Read back value of current XTAL trimming */ - __IO uint16_t RESET_STAT_REG; /*!< (@ 0x5000005E) Reset status register */ - __IO uint16_t FORCE_SLEEP_REG; /*!< (@ 0x50000060) Force FTDF/BLE to sleep */ - __IO uint16_t LDOS_DISABLE_REG; /*!< (@ 0x50000062) Force off all LDOs */ - __IO uint16_t AON_SPARE_REG; /*!< (@ 0x50000064) Spare register */ - __IO uint16_t SECURE_BOOT_REG; /*!< (@ 0x50000066) Controls secure booting */ - __IO uint16_t PMU_RESET_RAIL_REG; /*!< (@ 0x50000068) Controls rail resetting when RST is pulsed */ - __IO uint16_t DISCHARGE_RAIL_REG; /*!< (@ 0x5000006A) Immediate rail resetting. There is no LDO/DCDC - gating */ -} CRG_TOP_Type; - - -/* ================================================================================ */ -/* ================ DCDC ================ */ -/* ================================================================================ */ - - -/** - * @brief DCDC registers (DCDC) - */ - -typedef struct { /*!< (@ 0x50000080) DCDC Structure */ - __I uint16_t RESERVED; - __IO uint16_t DCDC_CTRL_0_REG; /*!< (@ 0x50000082) DCDC First Control Register */ - __IO uint16_t DCDC_CTRL_1_REG; /*!< (@ 0x50000084) DCDC Second Control Register */ - __IO uint16_t DCDC_CTRL_2_REG; /*!< (@ 0x50000086) DCDC Third Control Register */ - __IO uint16_t DCDC_V14_0_REG; /*!< (@ 0x50000088) DCDC V14 First Control Register */ - __IO uint16_t DCDC_V14_1_REG; /*!< (@ 0x5000008A) DCDC V14 Second Control Register */ - __IO uint16_t DCDC_V18_0_REG; /*!< (@ 0x5000008C) DCDC V18 First Control Register */ - __IO uint16_t DCDC_V18_1_REG; /*!< (@ 0x5000008E) DCDC V18 Second Control Register */ - __IO uint16_t DCDC_VDD_0_REG; /*!< (@ 0x50000090) DCDC VDD First Control Register */ - __IO uint16_t DCDC_VDD_1_REG; /*!< (@ 0x50000092) DCDC VDD Second Control Register */ - __IO uint16_t DCDC_V18P_0_REG; /*!< (@ 0x50000094) DCDC VPA First Control Register */ - __IO uint16_t DCDC_V18P_1_REG; /*!< (@ 0x50000096) DCDC VPA Second Control Register */ - __IO uint16_t DCDC_RET_0_REG; /*!< (@ 0x50000098) DCDC First Retention Mode Register */ - __IO uint16_t DCDC_RET_1_REG; /*!< (@ 0x5000009A) DCDC Second Retention Mode Register */ - __IO uint16_t DCDC_TRIM_REG; /*!< (@ 0x5000009C) DCDC Comparator Trim Register */ - __IO uint16_t DCDC_TEST_0_REG; /*!< (@ 0x5000009E) DCDC Test Register */ - __IO uint16_t DCDC_TEST_1_REG; /*!< (@ 0x500000A0) DCDC Test Register */ - __IO uint16_t DCDC_STATUS_0_REG; /*!< (@ 0x500000A2) DCDC First Status Register */ - __IO uint16_t DCDC_STATUS_1_REG; /*!< (@ 0x500000A4) DCDC Second Status Register */ - __IO uint16_t DCDC_STATUS_2_REG; /*!< (@ 0x500000A6) DCDC Third Status Register */ - __IO uint16_t DCDC_STATUS_3_REG; /*!< (@ 0x500000A8) DCDC Fourth Status Register */ - __IO uint16_t DCDC_STATUS_4_REG; /*!< (@ 0x500000AA) DCDC Fifth Status Register */ - __IO uint16_t DCDC_TRIM_0_REG; /*!< (@ 0x500000AC) DCDC V14 Comparator Trim Register */ - __IO uint16_t DCDC_TRIM_1_REG; /*!< (@ 0x500000AE) DCDC V18 Comparator Trim Register */ - __IO uint16_t DCDC_TRIM_2_REG; /*!< (@ 0x500000B0) DCDC VDD Comparator Trim Register */ - __IO uint16_t DCDC_TRIM_3_REG; /*!< (@ 0x500000B2) DCDC VPA Comparator Trim Register */ - __IO uint16_t DCDC_IRQ_STATUS_REG; /*!< (@ 0x500000B4) DCDC Interrupt Status Register */ - __IO uint16_t DCDC_IRQ_CLEAR_REG; /*!< (@ 0x500000B6) DCDC Interrupt Clear Register */ - __IO uint16_t DCDC_IRQ_MASK_REG; /*!< (@ 0x500000B8) DCDC Interrupt Clear Register */ -} DCDC_Type; - - -/* ================================================================================ */ -/* ================ DEM ================ */ -/* ================================================================================ */ - - -/** - * @brief DEM registers (DEM) - */ - -typedef struct { /*!< (@ 0x50002E00) DEM Structure */ - __IO uint16_t RF_DEM_CTRL_REG; /*!< (@ 0x50002E00) RF_DEM_CTRL_REG */ - __IO uint16_t RF_AGC_LUT_01_REG; /*!< (@ 0x50002E02) RF_AGC_LUT_01_REG */ - __IO uint16_t RF_AGC_LUT_23_REG; /*!< (@ 0x50002E04) RF_AGC_LUT_23_REG */ - __IO uint16_t RF_AGC_LUT_45_REG; /*!< (@ 0x50002E06) RF_AGC_LUT_45_REG */ - __IO uint16_t RF_AGC_LUT_67_REG; /*!< (@ 0x50002E08) RF_AGC_LUT_67_REG */ - __IO uint16_t RF_AGC_LUT_89_REG; /*!< (@ 0x50002E0A) RF_AGC_LUT_89_REG */ - __IO uint16_t RF_AGC_CTRL1_REG; /*!< (@ 0x50002E0C) RF_AGC_CTRL1_REG */ - __IO uint16_t RF_AGC_CTRL2_REG; /*!< (@ 0x50002E0E) RF_AGC_CTRL2_REG */ - __IO uint16_t RF_AFC_CTRL_REG; /*!< (@ 0x50002E10) RF_AFC_CTRL_REG */ - __IO uint16_t RF_DC_OFFSET_CTRL1_REG; /*!< (@ 0x50002E12) RF_DC_OFFSET_CTRL1_REG */ - __IO uint16_t RF_DC_OFFSET_CTRL2_REG; /*!< (@ 0x50002E14) RF_DC_OFFSET_CTRL2_REG */ - __IO uint16_t RF_DC_OFFSET_CTRL3_REG; /*!< (@ 0x50002E16) RF_DC_OFFSET_CTRL3_REG */ - __IO uint16_t RF_DC_OFFSET_CTRL4_REG; /*!< (@ 0x50002E18) RF_DC_OFFSET_CTRL4_REG */ - __I uint16_t RESERVED; - __IO uint16_t RF_AGC_RESULT_REG; /*!< (@ 0x50002E1C) RF_AGC_RESULT_REG */ - __IO uint16_t RF_RSSI_RESULT_REG; /*!< (@ 0x50002E1E) RF_RSSI_RESULT_REG */ - __IO uint16_t RF_DC_OFFSET_RESULT_REG; /*!< (@ 0x50002E20) Must be Retained */ - __IO uint16_t RF_RSSI_COMP_CTRL_REG; /*!< (@ 0x50002E22) RF_RSSI_COMP_CTRL_REG */ - __I uint32_t RESERVED1[3]; - __IO uint16_t RF_FTDF_CTRL1_REG; /*!< (@ 0x50002E30) RF_FTDF_CTRL1_REG */ - __IO uint16_t RF_FTDF_CTRL2_REG; /*!< (@ 0x50002E32) RF_FTDF_CTRL2_REG */ - __IO uint16_t RF_FTDF_CTRL3_REG; /*!< (@ 0x50002E34) RF_FTDF_CTRL3_REG */ - __IO uint16_t RF_FTDF_CTRL4_REG; /*!< (@ 0x50002E36) RF_FTDF_CTRL4_REG */ - __IO uint16_t RF_FTDF_LOOP_GAIN_PD_REG; /*!< (@ 0x50002E38) RF_FTDF_LOOP_GAIN_PD_REG */ - __IO uint16_t RF_FTDF_LOOP_GAIN_DS_REG; /*!< (@ 0x50002E3A) RF_FTDF_LOOP_GAIN_DS_REG */ - __IO uint16_t RF_FTDF_CTRL5_REG; /*!< (@ 0x50002E3C) RF_FTDF_CTRL5_REG */ - __IO uint16_t RF_FTDF_COBI_LOW_REG; /*!< (@ 0x50002E3E) RF_FTDF_COBI_LOW_REG */ - __IO uint16_t RF_FTDF_COBI_HIGH_REG; /*!< (@ 0x50002E40) RF_FTDF_COBI_HIGH_REG */ - __IO uint16_t RF_DEM_TESTMODE_REG; /*!< (@ 0x50002E42) RF_DEM_TESTMODE_REG */ - __IO uint16_t RF_DEM_IQCORRECT_REG; /*!< (@ 0x50002E44) RF_DEM_IQCORRECT_REG */ - __IO uint16_t RF_PAD_CNT_CTRL_REG; /*!< (@ 0x50002E46) RF_PAD_CNT_CTRL_REG */ - __IO uint16_t RF_PAD_CNT_RESULT_REG; /*!< (@ 0x50002E48) RF_PAD_CNT_RESULT_REG */ - __I uint16_t RESERVED2[3]; - __IO uint16_t RF_FSSS_I_RESULT_REG; /*!< (@ 0x50002E50) RF_FSSS_I_RESULT_REG */ - __IO uint16_t RF_FSSS_Q_RESULT_REG; /*!< (@ 0x50002E52) RF_FSSS_Q_RESULT_REG */ - __IO uint16_t RF_FSSS_MAG_RESULT_REG; /*!< (@ 0x50002E54) RF_FSSS_MAG_RESULT_REG */ - __IO uint16_t RF_CCA_RSSITH_REG; /*!< (@ 0x50002E56) RF_CCA_RSSITH_REG */ - __IO uint16_t RF_FTDF_SIGDET_CTRL_REG; /*!< (@ 0x50002E58) RF_FTDF_SIGDET_CTRL_REG */ -} DEM_Type; - - -/* ================================================================================ */ -/* ================ DMA ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA registers (DMA) - */ - -typedef struct { /*!< (@ 0x50003500) DMA Structure */ - __IO uint16_t DMA0_A_STARTL_REG; /*!< (@ 0x50003500) Start address Low A of DMA channel 0 */ - __IO uint16_t DMA0_A_STARTH_REG; /*!< (@ 0x50003502) Start address High A of DMA channel 0 */ - __IO uint16_t DMA0_B_STARTL_REG; /*!< (@ 0x50003504) Start address Low B of DMA channel 0 */ - __IO uint16_t DMA0_B_STARTH_REG; /*!< (@ 0x50003506) Start address High B of DMA channel 0 */ - __IO uint16_t DMA0_INT_REG; /*!< (@ 0x50003508) DMA receive interrupt register channel 0 */ - __IO uint16_t DMA0_LEN_REG; /*!< (@ 0x5000350A) DMA receive length register channel 0 */ - __IO uint16_t DMA0_CTRL_REG; /*!< (@ 0x5000350C) Control register for the DMA channel 0 */ - __IO uint16_t DMA0_IDX_REG; /*!< (@ 0x5000350E) Index value of DMA channel 0 */ - __IO uint16_t DMA1_A_STARTL_REG; /*!< (@ 0x50003510) Start address Low A of DMA channel 1 */ - __IO uint16_t DMA1_A_STARTH_REG; /*!< (@ 0x50003512) Start address High A of DMA channel 1 */ - __IO uint16_t DMA1_B_STARTL_REG; /*!< (@ 0x50003514) Start address Low B of DMA channel 1 */ - __IO uint16_t DMA1_B_STARTH_REG; /*!< (@ 0x50003516) Start address High B of DMA channel 1 */ - __IO uint16_t DMA1_INT_REG; /*!< (@ 0x50003518) DMA receive interrupt register channel 1 */ - __IO uint16_t DMA1_LEN_REG; /*!< (@ 0x5000351A) DMA receive length register channel 1 */ - __IO uint16_t DMA1_CTRL_REG; /*!< (@ 0x5000351C) Control register for the DMA channel 1 */ - __IO uint16_t DMA1_IDX_REG; /*!< (@ 0x5000351E) Index value of DMA channel 1 */ - __IO uint16_t DMA2_A_STARTL_REG; /*!< (@ 0x50003520) Start address Low A of DMA channel 2 */ - __IO uint16_t DMA2_A_STARTH_REG; /*!< (@ 0x50003522) Start address High A of DMA channel 2 */ - __IO uint16_t DMA2_B_STARTL_REG; /*!< (@ 0x50003524) Start address Low B of DMA channel 2 */ - __IO uint16_t DMA2_B_STARTH_REG; /*!< (@ 0x50003526) Start address High B of DMA channel 2 */ - __IO uint16_t DMA2_INT_REG; /*!< (@ 0x50003528) DMA receive interrupt register channel 2 */ - __IO uint16_t DMA2_LEN_REG; /*!< (@ 0x5000352A) DMA receive length register channel 2 */ - __IO uint16_t DMA2_CTRL_REG; /*!< (@ 0x5000352C) Control register for the DMA channel 2 */ - __IO uint16_t DMA2_IDX_REG; /*!< (@ 0x5000352E) Index value of DMA channel 2 */ - __IO uint16_t DMA3_A_STARTL_REG; /*!< (@ 0x50003530) Start address Low A of DMA channel 3 */ - __IO uint16_t DMA3_A_STARTH_REG; /*!< (@ 0x50003532) Start address High A of DMA channel 3 */ - __IO uint16_t DMA3_B_STARTL_REG; /*!< (@ 0x50003534) Start address Low B of DMA channel 3 */ - __IO uint16_t DMA3_B_STARTH_REG; /*!< (@ 0x50003536) Start address High B of DMA channel 3 */ - __IO uint16_t DMA3_INT_REG; /*!< (@ 0x50003538) DMA receive interrupt register channel 3 */ - __IO uint16_t DMA3_LEN_REG; /*!< (@ 0x5000353A) DMA receive length register channel 3 */ - __IO uint16_t DMA3_CTRL_REG; /*!< (@ 0x5000353C) Control register for the DMA channel 3 */ - __IO uint16_t DMA3_IDX_REG; /*!< (@ 0x5000353E) Index value of DMA channel 3 */ - __IO uint16_t DMA4_A_STARTL_REG; /*!< (@ 0x50003540) Start address Low A of DMA channel 4 */ - __IO uint16_t DMA4_A_STARTH_REG; /*!< (@ 0x50003542) Start address High A of DMA channel 4 */ - __IO uint16_t DMA4_B_STARTL_REG; /*!< (@ 0x50003544) Start address Low B of DMA channel 4 */ - __IO uint16_t DMA4_B_STARTH_REG; /*!< (@ 0x50003546) Start address High B of DMA channel 4 */ - __IO uint16_t DMA4_INT_REG; /*!< (@ 0x50003548) DMA receive interrupt register channel 4 */ - __IO uint16_t DMA4_LEN_REG; /*!< (@ 0x5000354A) DMA receive length register channel 4 */ - __IO uint16_t DMA4_CTRL_REG; /*!< (@ 0x5000354C) Control register for the DMA channel 4 */ - __IO uint16_t DMA4_IDX_REG; /*!< (@ 0x5000354E) Index value of DMA channel 4 */ - __IO uint16_t DMA5_A_STARTL_REG; /*!< (@ 0x50003550) Start address Low A of DMA channel 5 */ - __IO uint16_t DMA5_A_STARTH_REG; /*!< (@ 0x50003552) Start address High A of DMA channel 5 */ - __IO uint16_t DMA5_B_STARTL_REG; /*!< (@ 0x50003554) Start address Low B of DMA channel 5 */ - __IO uint16_t DMA5_B_STARTH_REG; /*!< (@ 0x50003556) Start address High B of DMA channel 5 */ - __IO uint16_t DMA5_INT_REG; /*!< (@ 0x50003558) DMA receive interrupt register channel 5 */ - __IO uint16_t DMA5_LEN_REG; /*!< (@ 0x5000355A) DMA receive length register channel 5 */ - __IO uint16_t DMA5_CTRL_REG; /*!< (@ 0x5000355C) Control register for the DMA channel 5 */ - __IO uint16_t DMA5_IDX_REG; /*!< (@ 0x5000355E) Index value of DMA channel 5 */ - __IO uint16_t DMA6_A_STARTL_REG; /*!< (@ 0x50003560) Start address Low A of DMA channel 6 */ - __IO uint16_t DMA6_A_STARTH_REG; /*!< (@ 0x50003562) Start address High A of DMA channel 6 */ - __IO uint16_t DMA6_B_STARTL_REG; /*!< (@ 0x50003564) Start address Low B of DMA channel 6 */ - __IO uint16_t DMA6_B_STARTH_REG; /*!< (@ 0x50003566) Start address High B of DMA channel 6 */ - __IO uint16_t DMA6_INT_REG; /*!< (@ 0x50003568) DMA receive interrupt register channel 6 */ - __IO uint16_t DMA6_LEN_REG; /*!< (@ 0x5000356A) DMA receive length register channel 6 */ - __IO uint16_t DMA6_CTRL_REG; /*!< (@ 0x5000356C) Control register for the DMA channel 6 */ - __IO uint16_t DMA6_IDX_REG; /*!< (@ 0x5000356E) Index value of DMA channel 6 */ - __IO uint16_t DMA7_A_STARTL_REG; /*!< (@ 0x50003570) Start address Low A of DMA channel 7 */ - __IO uint16_t DMA7_A_STARTH_REG; /*!< (@ 0x50003572) Start address High A of DMA channel 7 */ - __IO uint16_t DMA7_B_STARTL_REG; /*!< (@ 0x50003574) Start address Low B of DMA channel 7 */ - __IO uint16_t DMA7_B_STARTH_REG; /*!< (@ 0x50003576) Start address High B of DMA channel 7 */ - __IO uint16_t DMA7_INT_REG; /*!< (@ 0x50003578) DMA receive interrupt register channel 7 */ - __IO uint16_t DMA7_LEN_REG; /*!< (@ 0x5000357A) DMA receive length register channel 7 */ - __IO uint16_t DMA7_CTRL_REG; /*!< (@ 0x5000357C) Control register for the DMA channel 7 */ - __IO uint16_t DMA7_IDX_REG; /*!< (@ 0x5000357E) Index value of DMA channel 7 */ - __IO uint16_t DMA_REQ_MUX_REG; /*!< (@ 0x50003580) DMA channel assignments */ - __IO uint16_t DMA_INT_STATUS_REG; /*!< (@ 0x50003582) DMA interrupt status register */ - __IO uint16_t DMA_CLEAR_INT_REG; /*!< (@ 0x50003584) DMA clear interrupt register */ -} DMA_Type; - - -/* ================================================================================ */ -/* ================ ECC ================ */ -/* ================================================================================ */ - - -/** - * @brief ECC registers (ECC) - */ - -typedef struct { /*!< (@ 0x50006000) ECC Structure */ - __IO uint32_t ECC_CONFIG_REG; /*!< (@ 0x50006000) Configuration register */ - __IO uint32_t ECC_COMMAND_REG; /*!< (@ 0x50006004) Command register */ - __IO uint32_t ECC_CONTROL_REG; /*!< (@ 0x50006008) Control register */ - __IO uint32_t ECC_STATUS_REG; /*!< (@ 0x5000600C) Status register */ - __IO uint32_t ECC_VERSION_REG; /*!< (@ 0x50006010) Version register */ -} ECC_Type; - - -/* ================================================================================ */ -/* ================ FTDF ================ */ -/* ================================================================================ */ - - -/** - * @brief FTDF registers (FTDF) - */ - -typedef struct { /*!< (@ 0x40080000) FTDF Structure */ - __IO uint32_t FTDF_TX_FIFO_0_0_REG; /*!< (@ 0x40080000) Address transmit fifo 0 */ - __I uint32_t RESERVED[31]; - __IO uint32_t FTDF_TX_FIFO_1_0_REG; /*!< (@ 0x40080080) Address transmit fifo 1 */ - __I uint32_t RESERVED1[31]; - __IO uint32_t FTDF_TX_FIFO_2_0_REG; /*!< (@ 0x40080100) Address transmit fifo 2 */ - __I uint32_t RESERVED2[31]; - __IO uint32_t FTDF_TX_FIFO_3_0_REG; /*!< (@ 0x40080180) Address transmit fifo 3 */ - __I uint32_t RESERVED3[31]; - __IO uint32_t FTDF_TX_META_DATA_0_0_REG; /*!< (@ 0x40080200) Transmit metadata register 0 */ - __IO uint32_t FTDF_TX_META_DATA_1_0_REG; /*!< (@ 0x40080204) Transmit metadata register 0 */ - __I uint32_t RESERVED4[2]; - __IO uint32_t FTDF_TX_META_DATA_0_1_REG; /*!< (@ 0x40080210) Transmit metadata register 1 */ - __IO uint32_t FTDF_TX_META_DATA_1_1_REG; /*!< (@ 0x40080214) Transmit metadata register 1 */ - __I uint32_t RESERVED5[2]; - __IO uint32_t FTDF_TX_META_DATA_0_2_REG; /*!< (@ 0x40080220) Transmit metadata register 2 */ - __IO uint32_t FTDF_TX_META_DATA_1_2_REG; /*!< (@ 0x40080224) Transmit metadata register 2 */ - __I uint32_t RESERVED6[2]; - __IO uint32_t FTDF_TX_META_DATA_0_3_REG; /*!< (@ 0x40080230) Transmit metadata register 3 */ - __IO uint32_t FTDF_TX_META_DATA_1_3_REG; /*!< (@ 0x40080234) Transmit metadata register 3 */ - __I uint32_t RESERVED7[2]; - __IO uint32_t FTDF_TX_RETURN_STATUS_0_0_REG; /*!< (@ 0x40080240) Transmit status register 0 */ - __IO uint32_t FTDF_TX_RETURN_STATUS_1_0_REG; /*!< (@ 0x40080244) Transmit status register 0 */ - __I uint32_t RESERVED8[2]; - __IO uint32_t FTDF_TX_RETURN_STATUS_0_1_REG; /*!< (@ 0x40080250) Transmit status register 1 */ - __IO uint32_t FTDF_TX_RETURN_STATUS_1_1_REG; /*!< (@ 0x40080254) Transmit status register 1 */ - __I uint32_t RESERVED9[2]; - __IO uint32_t FTDF_TX_RETURN_STATUS_0_2_REG; /*!< (@ 0x40080260) Transmit status register 2 */ - __IO uint32_t FTDF_TX_RETURN_STATUS_1_2_REG; /*!< (@ 0x40080264) Transmit status register 2 */ - __I uint32_t RESERVED10[2]; - __IO uint32_t FTDF_TX_RETURN_STATUS_0_3_REG; /*!< (@ 0x40080270) Transmit status register 3 */ - __IO uint32_t FTDF_TX_RETURN_STATUS_1_3_REG; /*!< (@ 0x40080274) Transmit status register 3 */ - __I uint32_t RESERVED11[2]; - __IO uint32_t FTDF_RX_META_0_0_REG; /*!< (@ 0x40080280) Receive metadata register 0 */ - __IO uint32_t FTDF_RX_META_1_0_REG; /*!< (@ 0x40080284) Receive metadata register 0 */ - __I uint32_t RESERVED12[2]; - __IO uint32_t FTDF_RX_META_0_1_REG; /*!< (@ 0x40080290) Receive metadata register 1 */ - __IO uint32_t FTDF_RX_META_1_1_REG; /*!< (@ 0x40080294) Receive metadata register 1 */ - __I uint32_t RESERVED13[2]; - __IO uint32_t FTDF_RX_META_0_2_REG; /*!< (@ 0x400802A0) Receive metadata register 2 */ - __IO uint32_t FTDF_RX_META_1_2_REG; /*!< (@ 0x400802A4) Receive metadata register 2 */ - __I uint32_t RESERVED14[2]; - __IO uint32_t FTDF_RX_META_0_3_REG; /*!< (@ 0x400802B0) Receive metadata register 3 */ - __IO uint32_t FTDF_RX_META_1_3_REG; /*!< (@ 0x400802B4) Receive metadata register 3 */ - __I uint32_t RESERVED15[2]; - __IO uint32_t FTDF_RX_META_0_4_REG; /*!< (@ 0x400802C0) Receive metadata register 4 */ - __IO uint32_t FTDF_RX_META_1_4_REG; /*!< (@ 0x400802C4) Receive metadata register 4 */ - __I uint32_t RESERVED16[2]; - __IO uint32_t FTDF_RX_META_0_5_REG; /*!< (@ 0x400802D0) Receive metadata register 5 */ - __IO uint32_t FTDF_RX_META_1_5_REG; /*!< (@ 0x400802D4) Receive metadata register 5 */ - __I uint32_t RESERVED17[2]; - __IO uint32_t FTDF_RX_META_0_6_REG; /*!< (@ 0x400802E0) Receive metadata register 6 */ - __IO uint32_t FTDF_RX_META_1_6_REG; /*!< (@ 0x400802E4) Receive metadata register 6 */ - __I uint32_t RESERVED18[2]; - __IO uint32_t FTDF_RX_META_0_7_REG; /*!< (@ 0x400802F0) Receive metadata register 7 */ - __IO uint32_t FTDF_RX_META_1_7_REG; /*!< (@ 0x400802F4) Receive metadata register 7 */ - __I uint32_t RESERVED19[8002]; - __IO uint32_t FTDF_RX_FIFO_0_0_REG; /*!< (@ 0x40088000) Address receive fifo 0 */ - __I uint32_t RESERVED20[31]; - __IO uint32_t FTDF_RX_FIFO_1_0_REG; /*!< (@ 0x40088080) Address transmit fifo 1 */ - __I uint32_t RESERVED21[31]; - __IO uint32_t FTDF_RX_FIFO_2_0_REG; /*!< (@ 0x40088100) Address transmit fifo 2 */ - __I uint32_t RESERVED22[31]; - __IO uint32_t FTDF_RX_FIFO_3_0_REG; /*!< (@ 0x40088180) Address transmit fifo 3 */ - __I uint32_t RESERVED23[31]; - __IO uint32_t FTDF_RX_FIFO_4_0_REG; /*!< (@ 0x40088200) Address transmit fifo 4 */ - __I uint32_t RESERVED24[31]; - __IO uint32_t FTDF_RX_FIFO_5_0_REG; /*!< (@ 0x40088280) Address transmit fifo 5 */ - __I uint32_t RESERVED25[31]; - __IO uint32_t FTDF_RX_FIFO_6_0_REG; /*!< (@ 0x40088300) Address transmit fifo 6 */ - __I uint32_t RESERVED26[31]; - __IO uint32_t FTDF_RX_FIFO_7_0_REG; /*!< (@ 0x40088380) Address transmit fifo 7 */ - __I uint32_t RESERVED27[7967]; - __IO uint32_t FTDF_REL_NAME_0_REG; /*!< (@ 0x40090000) Name of the release */ - __IO uint32_t FTDF_REL_NAME_1_REG; /*!< (@ 0x40090004) Name of the release */ - __IO uint32_t FTDF_REL_NAME_2_REG; /*!< (@ 0x40090008) Name of the release */ - __IO uint32_t FTDF_REL_NAME_3_REG; /*!< (@ 0x4009000C) Name of the release */ - __IO uint32_t FTDF_BUILDTIME_0_REG; /*!< (@ 0x40090010) Build time */ - __IO uint32_t FTDF_BUILDTIME_1_REG; /*!< (@ 0x40090014) Build time */ - __IO uint32_t FTDF_BUILDTIME_2_REG; /*!< (@ 0x40090018) Build time */ - __IO uint32_t FTDF_BUILDTIME_3_REG; /*!< (@ 0x4009001C) Build time */ - __IO uint32_t FTDF_GLOB_CONTROL_0_REG; /*!< (@ 0x40090020) Global control register */ - __IO uint32_t FTDF_GLOB_CONTROL_1_REG; /*!< (@ 0x40090024) Global control register */ - __IO uint32_t FTDF_GLOB_CONTROL_2_REG; /*!< (@ 0x40090028) Global control register */ - __IO uint32_t FTDF_GLOB_CONTROL_3_REG; /*!< (@ 0x4009002C) Global control register */ - __IO uint32_t FTDF_LMAC_CONTROL_0_REG; /*!< (@ 0x40090030) Lmac control register */ - __IO uint32_t FTDF_TXPIPEPROPDELAY_REG; /*!< (@ 0x40090034) Prop delay transmit register */ - __IO uint32_t FTDF_MACACKWAITDURATION_REG; /*!< (@ 0x40090038) Maximum time to wait for a ACK */ - __IO uint32_t FTDF_MACENHACKWAITDURATION_REG; /*!< (@ 0x4009003C) Maximum time to wait for an enhanced ACK frame */ - __IO uint32_t FTDF_LMAC_CONTROL_1_REG; /*!< (@ 0x40090040) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_2_REG; /*!< (@ 0x40090044) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_3_REG; /*!< (@ 0x40090048) Lmac control register */ - __I uint32_t RESERVED28; - __IO uint32_t FTDF_LMAC_CONTROL_OS_REG; /*!< (@ 0x40090050) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_STATUS_REG; /*!< (@ 0x40090054) Lmac status register */ - __IO uint32_t FTDF_EVENTCURRVAL_REG; /*!< (@ 0x40090058) Value of event generator */ - __IO uint32_t FTDF_TIMESTAMPCURRVAL_REG; /*!< (@ 0x4009005C) Value of timestamp generator */ - __IO uint32_t FTDF_LMAC_CONTROL_4_REG; /*!< (@ 0x40090060) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_5_REG; /*!< (@ 0x40090064) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_6_REG; /*!< (@ 0x40090068) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_11_REG; /*!< (@ 0x4009006C) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_DELTA_REG; /*!< (@ 0x40090070) Lmac delta control register */ - __IO uint32_t FTDF_TIMESTAMPCURRPHASEVAL_REG; /*!< (@ 0x40090074) Value of timestamp generator phase within a symbol */ - __IO uint32_t FTDF_MACTSTXACKDELAYVAL_REG; /*!< (@ 0x40090078) Time left until next ACK is sent (us) */ - __I uint32_t RESERVED29; - __IO uint32_t FTDF_LMAC_CONTROL_MASK_REG; /*!< (@ 0x40090080) Lmac mask control register */ - __I uint32_t RESERVED30[3]; - __IO uint32_t FTDF_LMAC_EVENT_REG; /*!< (@ 0x40090090) Lmac event regsiter */ - __IO uint32_t FTDF_LMAC_MASK_REG; /*!< (@ 0x40090094) Lmac mask register */ - __I uint32_t RESERVED31[2]; - __IO uint32_t FTDF_LMAC_MANUAL_1_REG; /*!< (@ 0x400900A0) Lmax manual PHY register */ - __IO uint32_t FTDF_LMAC_MANUAL_OS_REG; /*!< (@ 0x400900A4) One shot register triggers transmission in manual - mode */ - __IO uint32_t FTDF_LMAC_MANUAL_STATUS_REG; /*!< (@ 0x400900A8) Lmac status register in manual mode */ - __I uint32_t RESERVED32[21]; - __IO uint32_t FTDF_LMAC_CONTROL_7_REG; /*!< (@ 0x40090100) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_8_REG; /*!< (@ 0x40090104) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_9_REG; /*!< (@ 0x40090108) Lmac control register */ - __IO uint32_t FTDF_LMAC_CONTROL_10_REG; /*!< (@ 0x4009010C) Lmac control register */ - __IO uint32_t FTDF_SECURITY_0_REG; /*!< (@ 0x40090110) Security register */ - __IO uint32_t FTDF_SECURITY_1_REG; /*!< (@ 0x40090114) Security register */ - __IO uint32_t FTDF_SECKEY_0_REG; /*!< (@ 0x40090118) Seckey register */ - __IO uint32_t FTDF_SECKEY_1_REG; /*!< (@ 0x4009011C) Seckey register */ - __IO uint32_t FTDF_SECKEY_2_REG; /*!< (@ 0x40090120) SecKey register */ - __IO uint32_t FTDF_SECKEY_3_REG; /*!< (@ 0x40090124) Seckey register */ - __IO uint32_t FTDF_SECNONCE_0_REG; /*!< (@ 0x40090128) Nonce register used for encryption/decryption */ - __IO uint32_t FTDF_SECNONCE_1_REG; /*!< (@ 0x4009012C) Nonce register used for encryption/decryption */ - __IO uint32_t FTDF_SECNONCE_2_REG; /*!< (@ 0x40090130) Nonce register used for encryption/decryption */ - __IO uint32_t FTDF_SECNONCE_3_REG; /*!< (@ 0x40090134) Nonce register used for encryption/decryption */ - __IO uint32_t FTDF_SECURITY_OS_REG; /*!< (@ 0x40090138) One shot register to start encryption/decryption */ - __I uint32_t RESERVED33; - __IO uint32_t FTDF_SECURITY_STATUS_REG; /*!< (@ 0x40090140) Security status register */ - __I uint32_t RESERVED34[3]; - __IO uint32_t FTDF_SECURITY_EVENT_REG; /*!< (@ 0x40090150) security event register */ - __IO uint32_t FTDF_SECURITY_EVENTMASK_REG; /*!< (@ 0x40090154) security event mask register */ - __I uint32_t RESERVED35[2]; - __IO uint32_t FTDF_TSCH_CONTROL_0_REG; /*!< (@ 0x40090160) Lmac tsch control register */ - __IO uint32_t FTDF_TSCH_CONTROL_1_REG; /*!< (@ 0x40090164) Lmac tsch control register */ - __IO uint32_t FTDF_TSCH_CONTROL_2_REG; /*!< (@ 0x40090168) Lmac tsch control register */ - __I uint32_t RESERVED36[5]; - __IO uint32_t FTDF_PHY_PARAMETERS_0_REG; /*!< (@ 0x40090180) Lmac PHY parameter register */ - __IO uint32_t FTDF_PHY_PARAMETERS_1_REG; /*!< (@ 0x40090184) Lmac PHY parameter register */ - __IO uint32_t FTDF_PHY_PARAMETERS_2_REG; /*!< (@ 0x40090188) Lmac PHY parameter register */ - __IO uint32_t FTDF_PHY_PARAMETERS_3_REG; /*!< (@ 0x4009018C) Lmac PHY parameter register */ - __I uint32_t RESERVED37[28]; - __IO uint32_t FTDF_RX_CONTROL_0_REG; /*!< (@ 0x40090200) Receive control register */ - __IO uint32_t FTDF_RX_EVENT_REG; /*!< (@ 0x40090204) Receive event register */ - __IO uint32_t FTDF_RX_MASK_REG; /*!< (@ 0x40090208) Receive event mask register */ - __IO uint32_t FTDF_RX_STATUS_REG; /*!< (@ 0x4009020C) Receive status register */ - __IO uint32_t FTDF_SYMBOLTIMESNAPSHOTVAL_REG; /*!< (@ 0x40090210) Value timestamp generator */ - __I uint32_t RESERVED38[3]; - __IO uint32_t FTDF_RX_STATUS_DELTA_REG; /*!< (@ 0x40090220) Receive status delta register */ - __IO uint32_t FTDF_RX_STATUS_MASK_REG; /*!< (@ 0x40090224) Receive status delta mask register */ - __I uint32_t RESERVED39[6]; - __IO uint32_t FTDF_TX_CONTROL_0_REG; /*!< (@ 0x40090240) Transmit control register */ - __I uint32_t RESERVED40[3]; - __IO uint32_t FTDF_FTDF_CE_REG; /*!< (@ 0x40090250) Selection register events */ - __IO uint32_t FTDF_FTDF_CM_REG; /*!< (@ 0x40090254) Mask selection register events */ - __I uint32_t RESERVED41[43]; - __IO uint32_t FTDF_SYNCTIMESTAMPTHR_REG; /*!< (@ 0x40090304) Threshold timestamp generator */ - __IO uint32_t FTDF_SYNCTIMESTAMPVAL_REG; /*!< (@ 0x40090308) Value timestamp generator */ - __IO uint32_t FTDF_TIMER_CONTROL_1_REG; /*!< (@ 0x4009030C) Timer control register */ - __IO uint32_t FTDF_MACTXSTDACKFRMCNT_REG; /*!< (@ 0x40090310) Transmitted acknowledgment frames */ - __IO uint32_t FTDF_MACRXSTDACKFRMOKCNT_REG; /*!< (@ 0x40090314) Received acknowledgment frames */ - __IO uint32_t FTDF_MACRXADDRFAILFRMCNT_REG; /*!< (@ 0x40090318) Discarded frames register */ - __IO uint32_t FTDF_MACRXUNSUPFRMCNT_REG; /*!< (@ 0x4009031C) Unsupported frames register */ - __IO uint32_t FTDF_SYNCTIMESTAMPPHASEVAL_REG; /*!< (@ 0x40090320) Timestamp phase value regsiter */ - __I uint32_t RESERVED42[7]; - __IO uint32_t FTDF_MACFCSERRORCOUNT_REG; /*!< (@ 0x40090340) Lmac FCS error register */ - __I uint32_t RESERVED43[7]; - __IO uint32_t FTDF_LMACRESET_REG; /*!< (@ 0x40090360) Lmax reset register */ - __IO uint32_t FTDF_WAKEUP_CONTROL_OS_REG; /*!< (@ 0x40090364) FTDF_WAKEUP_CONTROL_OS_REG */ - __I uint32_t RESERVED44[6]; - __IO uint32_t FTDF_SYMBOLTIMETHR_REG; /*!< (@ 0x40090380) Symboltime threshold register 1 */ - __IO uint32_t FTDF_SYMBOLTIME2THR_REG; /*!< (@ 0x40090384) Symboltime threshold register 2 */ - __I uint32_t RESERVED45[2]; - __IO uint32_t FTDF_DEBUGCONTROL_REG; /*!< (@ 0x40090390) Debug control register */ - __IO uint32_t FTDF_TXBYTE_E_REG; /*!< (@ 0x40090394) Transmit first byte register */ - __IO uint32_t FTDF_TXBYTE_M_REG; /*!< (@ 0x40090398) Transmit first byte mask register */ - __I uint32_t RESERVED46[25]; - __IO uint32_t FTDF_TX_FLAG_S_0_REG; /*!< (@ 0x40090400) Transmit packet ready for transmission register - 0 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_E_0_REG; /*!< (@ 0x40090404) Clear flag register 0 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_M_0_REG; /*!< (@ 0x40090408) Mask flag register 0 */ - __I uint32_t RESERVED47; - __IO uint32_t FTDF_TX_PRIORITY_0_REG; /*!< (@ 0x40090410) Transmit priority register 0 */ - __I uint32_t RESERVED48[3]; - __IO uint32_t FTDF_TX_FLAG_S_1_REG; /*!< (@ 0x40090420) Transmit packet ready for transmission register - 1 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_E_1_REG; /*!< (@ 0x40090424) Clear flag register 1 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_M_1_REG; /*!< (@ 0x40090428) Mask flag register 1 */ - __I uint32_t RESERVED49; - __IO uint32_t FTDF_TX_PRIORITY_1_REG; /*!< (@ 0x40090430) Transmit priority register 1 */ - __I uint32_t RESERVED50[3]; - __IO uint32_t FTDF_TX_FLAG_S_2_REG; /*!< (@ 0x40090440) Transmit packet ready for transmission register - 2 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_E_2_REG; /*!< (@ 0x40090444) Clear flag register 2 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_M_2_REG; /*!< (@ 0x40090448) Clear flag register 2 */ - __I uint32_t RESERVED51; - __IO uint32_t FTDF_TX_PRIORITY_2_REG; /*!< (@ 0x40090450) Transmit priority register 2 */ - __I uint32_t RESERVED52[3]; - __IO uint32_t FTDF_TX_FLAG_S_3_REG; /*!< (@ 0x40090460) Transmit packet ready for transmission register - 3 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_E_3_REG; /*!< (@ 0x40090464) Clear flag register 3 */ - __IO uint32_t FTDF_TX_FLAG_CLEAR_M_3_REG; /*!< (@ 0x40090468) Clear flag register 3 */ - __I uint32_t RESERVED53; - __IO uint32_t FTDF_TX_PRIORITY_3_REG; /*!< (@ 0x40090470) Transmit priority register 3 */ - __I uint32_t RESERVED54[3]; - __IO uint32_t FTDF_TX_SET_OS_REG; /*!< (@ 0x40090480) One shot register to set flag */ - __IO uint32_t FTDF_TX_CLEAR_OS_REG; /*!< (@ 0x40090484) One shot register to clear flag */ - __I uint32_t RESERVED55[734]; - __IO uint32_t FTDF_WAKEUP_CONTROL_REG; /*!< (@ 0x40091000) Wakeup timer vcontrol register */ - __I uint32_t RESERVED56[1023]; - __IO uint32_t FTDF_LONG_ADDR_0_0_REG; /*!< (@ 0x40092000) FTDF_LONG_ADDR_0_0_REG */ - __IO uint32_t FTDF_LONG_ADDR_1_0_REG; /*!< (@ 0x40092004) FTDF_LONG_ADDR_1_0_REG */ - __IO uint32_t FTDF_SIZE_AND_VAL_0_REG; /*!< (@ 0x40092008) FTDF_SIZE_AND_VAL_0_REG */ -} FTDF_Type; - - -/* ================================================================================ */ -/* ================ GP_TIMERS ================ */ -/* ================================================================================ */ - - -/** - * @brief GP_TIMERS registers (GP_TIMERS) - */ - -typedef struct { /*!< (@ 0x50003400) GP_TIMERS Structure */ - __IO uint16_t TIMER0_CTRL_REG; /*!< (@ 0x50003400) Timer0 control register */ - __IO uint16_t TIMER0_ON_REG; /*!< (@ 0x50003402) Timer0 on control register */ - __IO uint16_t TIMER0_RELOAD_M_REG; /*!< (@ 0x50003404) 16 bits reload value for Timer0 */ - __IO uint16_t TIMER0_RELOAD_N_REG; /*!< (@ 0x50003406) 16 bits reload value for Timer0 */ - __IO uint16_t PWM2_START_CYCLE; /*!< (@ 0x50003408) Defines start Cycle for PWM2 */ - __IO uint16_t PWM3_START_CYCLE; /*!< (@ 0x5000340A) Defines start Cycle for PWM3 */ - __IO uint16_t PWM4_START_CYCLE; /*!< (@ 0x5000340C) Defines start Cycle for PWM4 */ - __IO uint16_t PWM2_END_CYCLE; /*!< (@ 0x5000340E) Defines end Cycle for PWM2 */ - __IO uint16_t PWM3_END_CYCLE; /*!< (@ 0x50003410) Defines end Cycle for PWM3 */ - __IO uint16_t PWM4_END_CYCLE; /*!< (@ 0x50003412) Defines end Cycle for PWM4 */ - __IO uint16_t TRIPLE_PWM_FREQUENCY; /*!< (@ 0x50003414) Defines the PMW2,3,4 frequency */ - __IO uint16_t TRIPLE_PWM_CTRL_REG; /*!< (@ 0x50003416) PWM 2 3 4 Control register */ - __IO uint16_t BREATH_CFG_REG; /*!< (@ 0x50003418) Breath configuration register */ - __IO uint16_t BREATH_DUTY_MAX_REG; /*!< (@ 0x5000341A) Breath max duty cycle register */ - __IO uint16_t BREATH_DUTY_MIN_REG; /*!< (@ 0x5000341C) Breath min duty cycle register */ - __IO uint16_t BREATH_CTRL_REG; /*!< (@ 0x5000341E) Breath control register */ -} GP_TIMERS_Type; - - -/* ================================================================================ */ -/* ================ GPADC ================ */ -/* ================================================================================ */ - - -/** - * @brief GPADC registers (GPADC) - */ - -typedef struct { /*!< (@ 0x50001900) GPADC Structure */ - __IO uint16_t GP_ADC_CTRL_REG; /*!< (@ 0x50001900) General Purpose ADC Control Register */ - __IO uint16_t GP_ADC_CTRL2_REG; /*!< (@ 0x50001902) General Purpose ADC Second Control Register */ - __IO uint16_t GP_ADC_CTRL3_REG; /*!< (@ 0x50001904) General Purpose ADC Third Control Register */ - __IO uint16_t GP_ADC_OFFP_REG; /*!< (@ 0x50001906) General Purpose ADC Positive Offset Register */ - __IO uint16_t GP_ADC_OFFN_REG; /*!< (@ 0x50001908) General Purpose ADC Negative Offset Register */ - __IO uint16_t GP_ADC_CLEAR_INT_REG; /*!< (@ 0x5000190A) General Purpose ADC Clear Interrupt Register */ - __IO uint16_t GP_ADC_RESULT_REG; /*!< (@ 0x5000190C) General Purpose ADC Result Register */ -} GPADC_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO registers (GPIO) - */ - -typedef struct { /*!< (@ 0x50003000) GPIO Structure */ - __IO uint16_t P0_DATA_REG; /*!< (@ 0x50003000) P0 Data input / output Register */ - __IO uint16_t P1_DATA_REG; /*!< (@ 0x50003002) P1 Data input / output Register */ - __IO uint16_t P2_DATA_REG; /*!< (@ 0x50003004) P2 Data input / output Register */ - __IO uint16_t P3_DATA_REG; /*!< (@ 0x50003006) P3 Data input / output Register */ - __IO uint16_t P4_DATA_REG; /*!< (@ 0x50003008) P4 Data input / output Register */ - __IO uint16_t P0_SET_DATA_REG; /*!< (@ 0x5000300A) P0 Set port pins Register */ - __IO uint16_t P1_SET_DATA_REG; /*!< (@ 0x5000300C) P1 Set port pins Register */ - __IO uint16_t P2_SET_DATA_REG; /*!< (@ 0x5000300E) P2 Set port pins Register */ - __IO uint16_t P3_SET_DATA_REG; /*!< (@ 0x50003010) P3 Set port pins Register */ - __IO uint16_t P4_SET_DATA_REG; /*!< (@ 0x50003012) P4 Set port pins Register */ - __IO uint16_t P0_RESET_DATA_REG; /*!< (@ 0x50003014) P0 Reset port pins Register */ - __IO uint16_t P1_RESET_DATA_REG; /*!< (@ 0x50003016) P1 Reset port pins Register */ - __IO uint16_t P2_RESET_DATA_REG; /*!< (@ 0x50003018) P2 Reset port pins Register */ - __IO uint16_t P3_RESET_DATA_REG; /*!< (@ 0x5000301A) P3 Reset port pins Register */ - __IO uint16_t P4_RESET_DATA_REG; /*!< (@ 0x5000301C) P4 Reset port pins Register */ - __IO uint16_t P00_MODE_REG; /*!< (@ 0x5000301E) P00 Mode Register */ - __IO uint16_t P01_MODE_REG; /*!< (@ 0x50003020) P01 Mode Register */ - __IO uint16_t P02_MODE_REG; /*!< (@ 0x50003022) P02 Mode Register */ - __IO uint16_t P03_MODE_REG; /*!< (@ 0x50003024) P03 Mode Register */ - __IO uint16_t P04_MODE_REG; /*!< (@ 0x50003026) P04 Mode Register */ - __IO uint16_t P05_MODE_REG; /*!< (@ 0x50003028) P05 Mode Register */ - __IO uint16_t P06_MODE_REG; /*!< (@ 0x5000302A) P06 Mode Register */ - __IO uint16_t P07_MODE_REG; /*!< (@ 0x5000302C) P07 Mode Register */ - __IO uint16_t P10_MODE_REG; /*!< (@ 0x5000302E) P10 Mode Register */ - __IO uint16_t P11_MODE_REG; /*!< (@ 0x50003030) P11 Mode Register */ - __IO uint16_t P12_MODE_REG; /*!< (@ 0x50003032) P12 Mode Register */ - __IO uint16_t P13_MODE_REG; /*!< (@ 0x50003034) P13 Mode Register */ - __IO uint16_t P14_MODE_REG; /*!< (@ 0x50003036) P14 Mode Register */ - __IO uint16_t P15_MODE_REG; /*!< (@ 0x50003038) P15 Mode Register */ - __IO uint16_t P16_MODE_REG; /*!< (@ 0x5000303A) P24 Mode Register */ - __IO uint16_t P17_MODE_REG; /*!< (@ 0x5000303C) P25 Mode Register */ - __IO uint16_t P20_MODE_REG; /*!< (@ 0x5000303E) P20 Mode Register */ - __IO uint16_t P21_MODE_REG; /*!< (@ 0x50003040) P21 Mode Register */ - __IO uint16_t P22_MODE_REG; /*!< (@ 0x50003042) P22 Mode Register */ - __IO uint16_t P23_MODE_REG; /*!< (@ 0x50003044) P23 Mode Register */ - __IO uint16_t P24_MODE_REG; /*!< (@ 0x50003046) P24 Mode Register */ - __I uint16_t RESERVED[3]; - __IO uint16_t P30_MODE_REG; /*!< (@ 0x5000304E) P30 Mode Register */ - __IO uint16_t P31_MODE_REG; /*!< (@ 0x50003050) P31 Mode Register */ - __IO uint16_t P32_MODE_REG; /*!< (@ 0x50003052) P32 Mode Register */ - __IO uint16_t P33_MODE_REG; /*!< (@ 0x50003054) P33 Mode Register */ - __IO uint16_t P34_MODE_REG; /*!< (@ 0x50003056) P34 Mode Register */ - __IO uint16_t P35_MODE_REG; /*!< (@ 0x50003058) P35 Mode Register */ - __IO uint16_t P36_MODE_REG; /*!< (@ 0x5000305A) P36 Mode Register */ - __IO uint16_t P37_MODE_REG; /*!< (@ 0x5000305C) P37 Mode Register */ - __IO uint16_t P40_MODE_REG; /*!< (@ 0x5000305E) P40 Mode Register */ - __IO uint16_t P41_MODE_REG; /*!< (@ 0x50003060) P41 Mode Register */ - __IO uint16_t P42_MODE_REG; /*!< (@ 0x50003062) P42 Mode Register */ - __IO uint16_t P43_MODE_REG; /*!< (@ 0x50003064) P43 Mode Register */ - __IO uint16_t P44_MODE_REG; /*!< (@ 0x50003066) P44 Mode Register */ - __IO uint16_t P45_MODE_REG; /*!< (@ 0x50003068) P45 Mode Register */ - __IO uint16_t P46_MODE_REG; /*!< (@ 0x5000306A) P46 Mode Register */ - __IO uint16_t P47_MODE_REG; /*!< (@ 0x5000306C) P47 Mode Register */ - __I uint16_t RESERVED1[41]; - __IO uint16_t P0_PADPWR_CTRL_REG; /*!< (@ 0x500030C0) P0 Output Power Control Register */ - __IO uint16_t P1_PADPWR_CTRL_REG; /*!< (@ 0x500030C2) P1 Output Power Control Register */ - __IO uint16_t P2_PADPWR_CTRL_REG; /*!< (@ 0x500030C4) P2 Output Power Control Register */ - __IO uint16_t P3_PADPWR_CTRL_REG; /*!< (@ 0x500030C6) P3 Output Power Control Register */ - __IO uint16_t P4_PADPWR_CTRL_REG; /*!< (@ 0x500030C8) P4 Output Power Control Register */ - __I uint16_t RESERVED2[3]; - __IO uint16_t GPIO_CLK_SEL; /*!< (@ 0x500030D0) Select which clock to map on port in PPA */ - __I uint16_t RESERVED3[7]; - __IO uint16_t BIST_CTRL_REG; /*!< (@ 0x500030E0) BIST_CTRL_REG */ - __IO uint16_t RAMBIST_STATUS1_REG; /*!< (@ 0x500030E2) RAMBIST_STATUS1_REG */ - __IO uint16_t RAMBIST_STATUS2_REG; /*!< (@ 0x500030E4) RAMBIST_STATUS2_REG */ - __IO uint16_t RAMBIST_STATUS3_REG; /*!< (@ 0x500030E6) RAMBIST_STATUS3_REG */ - __IO uint16_t ROMBIST_RESULTL_REG; /*!< (@ 0x500030E8) ROMBIST_RESULTL_REG */ - __IO uint16_t ROMBIST_RESULTH_REG; /*!< (@ 0x500030EA) ROMBIST_RESULTH_REG */ - __I uint32_t RESERVED4; - __IO uint16_t TEST_CTRL_REG; /*!< (@ 0x500030F0) TEST_CTRL_REG */ - __IO uint16_t TEST_CTRL2_REG; /*!< (@ 0x500030F2) TEST_CTRL2_REG */ - __IO uint16_t TEST_CTRL3_REG; /*!< (@ 0x500030F4) TEST_CTRL3_REG */ - __IO uint16_t TEST_CTRL4_REG; /*!< (@ 0x500030F6) TEST_CTRL4_REG */ - __IO uint16_t TEST_CTRL5_REG; /*!< (@ 0x500030F8) TEST_CTRL5_REG */ -} GPIO_Type; - - -/* ================================================================================ */ -/* ================ GPREG ================ */ -/* ================================================================================ */ - - -/** - * @brief GPREG registers (GPREG) - */ - -typedef struct { /*!< (@ 0x50003300) GPREG Structure */ - __IO uint16_t SET_FREEZE_REG; /*!< (@ 0x50003300) Controls freezing of various timers/counters - (incl. DMA and USB). */ - __IO uint16_t RESET_FREEZE_REG; /*!< (@ 0x50003302) Controls unfreezing of various timers/counters - (incl. DMA and USB). */ - __IO uint16_t DEBUG_REG; /*!< (@ 0x50003304) Various debug information register. */ - __IO uint16_t GP_STATUS_REG; /*!< (@ 0x50003306) General purpose system status register. */ - __IO uint16_t GP_CONTROL_REG; /*!< (@ 0x50003308) General purpose system control register. */ - __IO uint16_t ECC_BASE_ADDR_REG; /*!< (@ 0x5000330A) Base address of the ECC Crypto memory register. */ - __IO uint16_t LED_CONTROL_REG; /*!< (@ 0x5000330C) Controls muxing and enabling of the LEDs. */ - __IO uint16_t BLE_FINECNT_SAMP_REG; /*!< (@ 0x5000330E) BLE FINECNT sampled value while in deep sleep - state. */ - __IO uint16_t PLL_SYS_CTRL1_REG; /*!< (@ 0x50003310) System PLL control register 1. */ - __IO uint16_t PLL_SYS_CTRL2_REG; /*!< (@ 0x50003312) System PLL control register 2. */ - __IO uint16_t PLL_SYS_CTRL3_REG; /*!< (@ 0x50003314) System PLL control register 3. */ - __IO uint16_t PLL_SYS_STATUS_REG; /*!< (@ 0x50003316) System PLL status register. */ - __IO uint16_t PLL_SYS_TEST_REG; /*!< (@ 0x50003318) System PLL test register. */ -} GPREG_Type; - - -/* ================================================================================ */ -/* ================ I2C ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C registers (I2C) - */ - -typedef struct { /*!< (@ 0x50001400) I2C Structure */ - __IO uint16_t I2C_CON_REG; /*!< (@ 0x50001400) I2C Control Register */ - __I uint16_t RESERVED; - __IO uint16_t I2C_TAR_REG; /*!< (@ 0x50001404) I2C Target Address Register */ - __I uint16_t RESERVED1; - __IO uint16_t I2C_SAR_REG; /*!< (@ 0x50001408) I2C Slave Address Register */ - __I uint16_t RESERVED2[3]; - __IO uint16_t I2C_DATA_CMD_REG; /*!< (@ 0x50001410) I2C Rx/Tx Data Buffer and Command Register */ - __I uint16_t RESERVED3; - __IO uint16_t I2C_SS_SCL_HCNT_REG; /*!< (@ 0x50001414) Standard Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED4; - __IO uint16_t I2C_SS_SCL_LCNT_REG; /*!< (@ 0x50001418) Standard Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED5; - __IO uint16_t I2C_FS_SCL_HCNT_REG; /*!< (@ 0x5000141C) Fast Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED6; - __IO uint16_t I2C_FS_SCL_LCNT_REG; /*!< (@ 0x50001420) Fast Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED7[5]; - __IO uint16_t I2C_INTR_STAT_REG; /*!< (@ 0x5000142C) I2C Interrupt Status Register */ - __I uint16_t RESERVED8; - __IO uint16_t I2C_INTR_MASK_REG; /*!< (@ 0x50001430) I2C Interrupt Mask Register */ - __I uint16_t RESERVED9; - __IO uint16_t I2C_RAW_INTR_STAT_REG; /*!< (@ 0x50001434) I2C Raw Interrupt Status Register */ - __I uint16_t RESERVED10; - __IO uint16_t I2C_RX_TL_REG; /*!< (@ 0x50001438) I2C Receive FIFO Threshold Register */ - __I uint16_t RESERVED11; - __IO uint16_t I2C_TX_TL_REG; /*!< (@ 0x5000143C) I2C Transmit FIFO Threshold Register */ - __I uint16_t RESERVED12; - __IO uint16_t I2C_CLR_INTR_REG; /*!< (@ 0x50001440) Clear Combined and Individual Interrupt Register */ - __I uint16_t RESERVED13; - __IO uint16_t I2C_CLR_RX_UNDER_REG; /*!< (@ 0x50001444) Clear RX_UNDER Interrupt Register */ - __I uint16_t RESERVED14; - __IO uint16_t I2C_CLR_RX_OVER_REG; /*!< (@ 0x50001448) Clear RX_OVER Interrupt Register */ - __I uint16_t RESERVED15; - __IO uint16_t I2C_CLR_TX_OVER_REG; /*!< (@ 0x5000144C) Clear TX_OVER Interrupt Register */ - __I uint16_t RESERVED16; - __IO uint16_t I2C_CLR_RD_REQ_REG; /*!< (@ 0x50001450) Clear RD_REQ Interrupt Register */ - __I uint16_t RESERVED17; - __IO uint16_t I2C_CLR_TX_ABRT_REG; /*!< (@ 0x50001454) Clear TX_ABRT Interrupt Register */ - __I uint16_t RESERVED18; - __IO uint16_t I2C_CLR_RX_DONE_REG; /*!< (@ 0x50001458) Clear RX_DONE Interrupt Register */ - __I uint16_t RESERVED19; - __IO uint16_t I2C_CLR_ACTIVITY_REG; /*!< (@ 0x5000145C) Clear ACTIVITY Interrupt Register */ - __I uint16_t RESERVED20; - __IO uint16_t I2C_CLR_STOP_DET_REG; /*!< (@ 0x50001460) Clear STOP_DET Interrupt Register */ - __I uint16_t RESERVED21; - __IO uint16_t I2C_CLR_START_DET_REG; /*!< (@ 0x50001464) Clear START_DET Interrupt Register */ - __I uint16_t RESERVED22; - __IO uint16_t I2C_CLR_GEN_CALL_REG; /*!< (@ 0x50001468) Clear GEN_CALL Interrupt Register */ - __I uint16_t RESERVED23; - __IO uint16_t I2C_ENABLE_REG; /*!< (@ 0x5000146C) I2C Enable Register */ - __I uint16_t RESERVED24; - __IO uint16_t I2C_STATUS_REG; /*!< (@ 0x50001470) I2C Status Register */ - __I uint16_t RESERVED25; - __IO uint16_t I2C_TXFLR_REG; /*!< (@ 0x50001474) I2C Transmit FIFO Level Register */ - __I uint16_t RESERVED26; - __IO uint16_t I2C_RXFLR_REG; /*!< (@ 0x50001478) I2C Receive FIFO Level Register */ - __I uint16_t RESERVED27; - __IO uint16_t I2C_SDA_HOLD_REG; /*!< (@ 0x5000147C) I2C SDA Hold Time Length Register */ - __I uint16_t RESERVED28; - __IO uint16_t I2C_TX_ABRT_SOURCE_REG; /*!< (@ 0x50001480) I2C Transmit Abort Source Register */ - __I uint16_t RESERVED29[3]; - __IO uint16_t I2C_DMA_CR_REG; /*!< (@ 0x50001488) DMA Control Register */ - __I uint16_t RESERVED30; - __IO uint16_t I2C_DMA_TDLR_REG; /*!< (@ 0x5000148C) DMA Transmit Data Level Register */ - __I uint16_t RESERVED31; - __IO uint16_t I2C_DMA_RDLR_REG; /*!< (@ 0x50001490) I2C Receive Data Level Register */ - __I uint16_t RESERVED32; - __IO uint16_t I2C_SDA_SETUP_REG; /*!< (@ 0x50001494) I2C SDA Setup Register */ - __I uint16_t RESERVED33; - __IO uint16_t I2C_ACK_GENERAL_CALL_REG; /*!< (@ 0x50001498) I2C ACK General Call Register */ - __I uint16_t RESERVED34; - __IO uint16_t I2C_ENABLE_STATUS_REG; /*!< (@ 0x5000149C) I2C Enable Status Register */ - __I uint16_t RESERVED35; - __IO uint16_t I2C_IC_FS_SPKLEN_REG; /*!< (@ 0x500014A0) I2C SS and FS spike suppression limit Size */ - __I uint16_t RESERVED36[41]; - __IO uint16_t I2C_COMP_PARAM1_REG; /*!< (@ 0x500014F4) Component Parameter Register */ - __IO uint16_t I2C_COMP_PARAM2_REG; /*!< (@ 0x500014F6) Component Parameter Register 2 */ - __IO uint16_t I2C_COMP_VERSION_REG; /*!< (@ 0x500014F8) I2C Component Version Register */ - __IO uint16_t I2C_COMP2_VERSION; /*!< (@ 0x500014FA) I2C Component2 Version Register */ - __IO uint16_t I2C_COMP_TYPE_REG; /*!< (@ 0x500014FC) I2C Component Type Register */ - __IO uint16_t I2C_COMP_TYPE2_REG; /*!< (@ 0x500014FE) I2C Component2 Type Register */ -} I2C_Type; - - -/* ================================================================================ */ -/* ================ I2C2 ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C2 registers (I2C2) - */ - -typedef struct { /*!< (@ 0x50001500) I2C2 Structure */ - __IO uint16_t I2C2_CON_REG; /*!< (@ 0x50001500) I2C Control Register */ - __I uint16_t RESERVED; - __IO uint16_t I2C2_TAR_REG; /*!< (@ 0x50001504) I2C Target Address Register */ - __I uint16_t RESERVED1; - __IO uint16_t I2C2_SAR_REG; /*!< (@ 0x50001508) I2C Slave Address Register */ - __I uint16_t RESERVED2[3]; - __IO uint16_t I2C2_DATA_CMD_REG; /*!< (@ 0x50001510) I2C Rx/Tx Data Buffer and Command Register */ - __I uint16_t RESERVED3; - __IO uint16_t I2C2_SS_SCL_HCNT_REG; /*!< (@ 0x50001514) Standard Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED4; - __IO uint16_t I2C2_SS_SCL_LCNT_REG; /*!< (@ 0x50001518) Standard Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED5; - __IO uint16_t I2C2_FS_SCL_HCNT_REG; /*!< (@ 0x5000151C) Fast Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED6; - __IO uint16_t I2C2_FS_SCL_LCNT_REG; /*!< (@ 0x50001520) Fast Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED7[5]; - __IO uint16_t I2C2_INTR_STAT_REG; /*!< (@ 0x5000152C) I2C Interrupt Status Register */ - __I uint16_t RESERVED8; - __IO uint16_t I2C2_INTR_MASK_REG; /*!< (@ 0x50001530) I2C Interrupt Mask Register */ - __I uint16_t RESERVED9; - __IO uint16_t I2C2_RAW_INTR_STAT_REG; /*!< (@ 0x50001534) I2C Raw Interrupt Status Register */ - __I uint16_t RESERVED10; - __IO uint16_t I2C2_RX_TL_REG; /*!< (@ 0x50001538) I2C Receive FIFO Threshold Register */ - __I uint16_t RESERVED11; - __IO uint16_t I2C2_TX_TL_REG; /*!< (@ 0x5000153C) I2C Transmit FIFO Threshold Register */ - __I uint16_t RESERVED12; - __IO uint16_t I2C2_CLR_INTR_REG; /*!< (@ 0x50001540) Clear Combined and Individual Interrupt Register */ - __I uint16_t RESERVED13; - __IO uint16_t I2C2_CLR_RX_UNDER_REG; /*!< (@ 0x50001544) Clear RX_UNDER Interrupt Register */ - __I uint16_t RESERVED14; - __IO uint16_t I2C2_CLR_RX_OVER_REG; /*!< (@ 0x50001548) Clear RX_OVER Interrupt Register */ - __I uint16_t RESERVED15; - __IO uint16_t I2C2_CLR_TX_OVER_REG; /*!< (@ 0x5000154C) Clear TX_OVER Interrupt Register */ - __I uint16_t RESERVED16; - __IO uint16_t I2C2_CLR_RD_REQ_REG; /*!< (@ 0x50001550) Clear RD_REQ Interrupt Register */ - __I uint16_t RESERVED17; - __IO uint16_t I2C2_CLR_TX_ABRT_REG; /*!< (@ 0x50001554) Clear TX_ABRT Interrupt Register */ - __I uint16_t RESERVED18; - __IO uint16_t I2C2_CLR_RX_DONE_REG; /*!< (@ 0x50001558) Clear RX_DONE Interrupt Register */ - __I uint16_t RESERVED19; - __IO uint16_t I2C2_CLR_ACTIVITY_REG; /*!< (@ 0x5000155C) Clear ACTIVITY Interrupt Register */ - __I uint16_t RESERVED20; - __IO uint16_t I2C2_CLR_STOP_DET_REG; /*!< (@ 0x50001560) Clear STOP_DET Interrupt Register */ - __I uint16_t RESERVED21; - __IO uint16_t I2C2_CLR_START_DET_REG; /*!< (@ 0x50001564) Clear START_DET Interrupt Register */ - __I uint16_t RESERVED22; - __IO uint16_t I2C2_CLR_GEN_CALL_REG; /*!< (@ 0x50001568) Clear GEN_CALL Interrupt Register */ - __I uint16_t RESERVED23; - __IO uint16_t I2C2_ENABLE_REG; /*!< (@ 0x5000156C) I2C Enable Register */ - __I uint16_t RESERVED24; - __IO uint16_t I2C2_STATUS_REG; /*!< (@ 0x50001570) I2C Status Register */ - __I uint16_t RESERVED25; - __IO uint16_t I2C2_TXFLR_REG; /*!< (@ 0x50001574) I2C Transmit FIFO Level Register */ - __I uint16_t RESERVED26; - __IO uint16_t I2C2_RXFLR_REG; /*!< (@ 0x50001578) I2C Receive FIFO Level Register */ - __I uint16_t RESERVED27; - __IO uint16_t I2C2_SDA_HOLD_REG; /*!< (@ 0x5000157C) I2C SDA Hold Time Length Register */ - __I uint16_t RESERVED28; - __IO uint16_t I2C2_TX_ABRT_SOURCE_REG; /*!< (@ 0x50001580) I2C Transmit Abort Source Register */ - __I uint16_t RESERVED29[3]; - __IO uint16_t I2C2_DMA_CR_REG; /*!< (@ 0x50001588) DMA Control Register */ - __I uint16_t RESERVED30; - __IO uint16_t I2C2_DMA_TDLR_REG; /*!< (@ 0x5000158C) DMA Transmit Data Level Register */ - __I uint16_t RESERVED31; - __IO uint16_t I2C2_DMA_RDLR_REG; /*!< (@ 0x50001590) I2C Receive Data Level Register */ - __I uint16_t RESERVED32; - __IO uint16_t I2C2_SDA_SETUP_REG; /*!< (@ 0x50001594) I2C SDA Setup Register */ - __I uint16_t RESERVED33; - __IO uint16_t I2C2_ACK_GENERAL_CALL_REG; /*!< (@ 0x50001598) I2C ACK General Call Register */ - __I uint16_t RESERVED34; - __IO uint16_t I2C2_ENABLE_STATUS_REG; /*!< (@ 0x5000159C) I2C Enable Status Register */ - __I uint16_t RESERVED35; - __IO uint16_t I2C2_IC_FS_SPKLEN_REG; /*!< (@ 0x500015A0) I2C SS and FS spike suppression limit Size */ - __I uint16_t RESERVED36[41]; - __IO uint16_t I2C2_COMP_PARAM1_REG; /*!< (@ 0x500015F4) Component Parameter Register */ - __IO uint16_t I2C2_COMP_PARAM2_REG; /*!< (@ 0x500015F6) Component Parameter Register 2 */ - __IO uint16_t I2C2_COMP_VERSION_REG; /*!< (@ 0x500015F8) I2C Component Version Register */ - __IO uint16_t I2C2_COMP2_VERSION; /*!< (@ 0x500015FA) I2C Component2 Version Register */ - __IO uint16_t I2C2_COMP_TYPE_REG; /*!< (@ 0x500015FC) I2C Component Type Register */ - __IO uint16_t I2C2_COMP_TYPE2_REG; /*!< (@ 0x500015FE) I2C Component2 Type Register */ -} I2C2_Type; - - -/* ================================================================================ */ -/* ================ IR ================ */ -/* ================================================================================ */ - - -/** - * @brief IR registers (IR) - */ - -typedef struct { /*!< (@ 0x50001700) IR Structure */ - __IO uint16_t IR_FREQ_CARRIER_ON_REG; /*!< (@ 0x50001700) Defines the carrier signal high duration */ - __IO uint16_t IR_FREQ_CARRIER_OFF_REG; /*!< (@ 0x50001702) Defnes the carrier signal low duration */ - __IO uint16_t IR_LOGIC_ONE_TIME_REG; /*!< (@ 0x50001704) Defines the logic one waveform */ - __IO uint16_t IR_LOGIC_ZERO_TIME_REG; /*!< (@ 0x50001706) Defines the logic zero wavefrom */ - __IO uint16_t IR_CTRL_REG; /*!< (@ 0x50001708) IR control register */ - __IO uint16_t IR_STATUS_REG; /*!< (@ 0x5000170A) IR status register */ - __IO uint16_t IR_REPEAT_TIME_REG; /*!< (@ 0x5000170C) Defines the repeat time */ - __IO uint16_t IR_MAIN_FIFO_REG; /*!< (@ 0x5000170E) Main fifo write register */ - __IO uint16_t IR_REPEAT_FIFO_REG; /*!< (@ 0x50001710) Repeat fifo write register */ - __IO uint16_t IR_IRQ_STATUS_REG; /*!< (@ 0x50001712) IR interrupt status register */ -} IR_Type; - - -/* ================================================================================ */ -/* ================ KBSCAN ================ */ -/* ================================================================================ */ - - -/** - * @brief KBSCAN registers (KBSCAN) - */ - -typedef struct { /*!< (@ 0x50001600) KBSCAN Structure */ - __IO uint16_t KBSCN_CTRL_REG; /*!< (@ 0x50001600) Keyboard scanner control register */ - __IO uint16_t KBSCN_CTRL2_REG; /*!< (@ 0x50001602) Keyboard scanner control 2 register */ - __IO uint16_t KBSCN_MATRIX_SIZE_REG; /*!< (@ 0x50001604) Defines the number of rows and columns of the - matrix */ - __IO uint16_t KBSCN_DEBOUNCE_REG; /*!< (@ 0x50001606) Defines the debounce time for key press and release */ - __IO uint16_t KBSCN_STATUS_REG; /*!< (@ 0x50001608) keyboard scanner Interrupt status register */ - __IO uint16_t KBSCN_MESSAGE_KEY_REG; /*!< (@ 0x5000160A) Returns a key message from the message queue */ - __IO uint16_t KBSCN_P00_MODE_REG; /*!< (@ 0x5000160C) Defines the keyboard mode for P00 */ - __IO uint16_t KBSCN_P01_MODE_REG; /*!< (@ 0x5000160E) Defines the keyboard mode for P01 */ - __IO uint16_t KBSCN_P02_MODE_REG; /*!< (@ 0x50001610) Defines the keyboard mode for P02 */ - __IO uint16_t KBSCN_P03_MODE_REG; /*!< (@ 0x50001612) Defines the keyboard mode for P03 */ - __IO uint16_t KBSCN_P04_MODE_REG; /*!< (@ 0x50001614) Defines the keyboard mode for P04 */ - __IO uint16_t KBSCN_P05_MODE_REG; /*!< (@ 0x50001616) Defines the keyboard mode for P05 */ - __IO uint16_t KBSCN_P06_MODE_REG; /*!< (@ 0x50001618) Defines the keyboard mode for P06 */ - __IO uint16_t KBSCN_P07_MODE_REG; /*!< (@ 0x5000161A) Defines the keyboard mode for P07 */ - __IO uint16_t KBSCN_P10_MODE_REG; /*!< (@ 0x5000161C) Defines the keyboard mode for P10 */ - __IO uint16_t KBSCN_P11_MODE_REG; /*!< (@ 0x5000161E) Defines the keyboard mode for P11 */ - __IO uint16_t KBSCN_P12_MODE_REG; /*!< (@ 0x50001620) Defines the keyboard mode for P12 */ - __IO uint16_t KBSCN_P13_MODE_REG; /*!< (@ 0x50001622) Defines the keyboard mode for P13 */ - __IO uint16_t KBSCN_P14_MODE_REG; /*!< (@ 0x50001624) Defines the keyboard mode for P14 */ - __IO uint16_t KBSCN_P15_MODE_REG; /*!< (@ 0x50001626) Defines the keyboard mode for P15 */ - __IO uint16_t KBSCN_P16_MODE_REG; /*!< (@ 0x50001628) Defines the keyboard mode for P16 */ - __IO uint16_t KBSCN_P17_MODE_REG; /*!< (@ 0x5000162A) Defines the keyboard mode for P17 */ - __IO uint16_t KBSCN_P20_MODE_REG; /*!< (@ 0x5000162C) Defines the keyboard mode for P20 */ - __IO uint16_t KBSCN_P21_MODE_REG; /*!< (@ 0x5000162E) Defines the keyboard mode for P21 */ - __IO uint16_t KBSCN_P22_MODE_REG; /*!< (@ 0x50001630) Defines the keyboard mode for P22 */ - __IO uint16_t KBSCN_P23_MODE_REG; /*!< (@ 0x50001632) Defines the keyboard mode for P23 */ - __IO uint16_t KBSCN_P24_MODE_REG; /*!< (@ 0x50001634) Defines the keyboard mode for P24 */ - __I uint16_t RESERVED[3]; - __IO uint16_t KBSCN_P30_MODE_REG; /*!< (@ 0x5000163C) Defines the keyboard mode for P30 */ - __IO uint16_t KBSCN_P31_MODE_REG; /*!< (@ 0x5000163E) Defines the keyboard mode for P31 */ - __IO uint16_t KBSCN_P32_MODE_REG; /*!< (@ 0x50001640) Defines the keyboard mode for P32 */ - __IO uint16_t KBSCN_P33_MODE_REG; /*!< (@ 0x50001642) Defines the keyboard mode for P33 */ - __IO uint16_t KBSCN_P34_MODE_REG; /*!< (@ 0x50001644) Defines the keyboard mode for P34 */ - __IO uint16_t KBSCN_P35_MODE_REG; /*!< (@ 0x50001646) Defines the keyboard mode for P35 */ - __IO uint16_t KBSCN_P36_MODE_REG; /*!< (@ 0x50001648) Defines the keyboard mode for P36 */ - __IO uint16_t KBSCN_P37_MODE_REG; /*!< (@ 0x5000164A) Defines the keyboard mode for P37 */ - __IO uint16_t KBSCN_P40_MODE_REG; /*!< (@ 0x5000164C) Defines the keyboard mode for P40 */ - __IO uint16_t KBSCN_P41_MODE_REG; /*!< (@ 0x5000164E) Defines the keyboard mode for P41 */ - __IO uint16_t KBSCN_P42_MODE_REG; /*!< (@ 0x50001650) Defines the keyboard mode for P42 */ - __IO uint16_t KBSCN_P43_MODE_REG; /*!< (@ 0x50001652) Defines the keyboard mode for P43 */ - __IO uint16_t KBSCN_P44_MODE_REG; /*!< (@ 0x50001654) Defines the keyboard mode for P44 */ - __IO uint16_t KBSCN_P45_MODE_REG; /*!< (@ 0x50001656) Defines the keyboard mode for P45 */ - __IO uint16_t KBSCN_P46_MODE_REG; /*!< (@ 0x50001658) Defines the keyboard mode for P46 */ - __IO uint16_t KBSCN_P47_MODE_REG; /*!< (@ 0x5000165A) Defines the keyboard mode for P47 */ -} KBSCAN_Type; - - -/* ================================================================================ */ -/* ================ OTPC ================ */ -/* ================================================================================ */ - - -/** - * @brief OTPC registers (OTPC) - */ - -typedef struct { /*!< (@ 0x07F40000) OTPC Structure */ - __IO uint32_t OTPC_MODE_REG; /*!< (@ 0x07F40000) Mode register */ - __IO uint32_t OTPC_PCTRL_REG; /*!< (@ 0x07F40004) Bit-programming control register */ - __IO uint32_t OTPC_STAT_REG; /*!< (@ 0x07F40008) Status register */ - __IO uint32_t OTPC_AHBADR_REG; /*!< (@ 0x07F4000C) AHB master start address */ - __IO uint32_t OTPC_CELADR_REG; /*!< (@ 0x07F40010) Macrocell start address */ - __IO uint32_t OTPC_NWORDS_REG; /*!< (@ 0x07F40014) Number of words */ - __IO uint32_t OTPC_FFPRT_REG; /*!< (@ 0x07F40018) Ports access to fifo logic */ - __IO uint32_t OTPC_FFRD_REG; /*!< (@ 0x07F4001C) The data which have taken with the latest read - from the OTPC_FFPRT_REG */ - __IO uint32_t OTPC_PWORDL_REG; /*!< (@ 0x07F40020) The 32 lower bits of the 64-bit word that will - be programmed, when the MPROG mode is used. */ - __IO uint32_t OTPC_PWORDH_REG; /*!< (@ 0x07F40024) The 32 higher bits of the 64-bit word that will - be programmed, when the MPROG mode is used. */ - __IO uint32_t OTPC_TIM1_REG; /*!< (@ 0x07F40028) Various timing parameters of the OTP cell. */ - __IO uint32_t OTPC_TIM2_REG; /*!< (@ 0x07F4002C) Various timing parameters of the OTP cell. */ - __IO uint32_t OTPC_TEST_REG; /*!< (@ 0x07F40030) OTPC_TEST_REG */ -} OTPC_Type; - - -/* ================================================================================ */ -/* ================ PATCH ================ */ -/* ================================================================================ */ - - -/** - * @brief PATCH registers (PATCH) - */ - -typedef struct { /*!< (@ 0x40050000) PATCH Structure */ - __IO uint32_t PATCH_VALID_REG; /*!< (@ 0x40050000) Validity Control Register */ - __IO uint32_t PATCH_VALID_SET_REG; /*!< (@ 0x40050004) Validity Set Control Register */ - __IO uint32_t PATCH_VALID_RESET_REG; /*!< (@ 0x40050008) Validity Reset Control Register */ - __I uint32_t RESERVED[5]; - __IO uint32_t PATCH_ADDR0_REG; /*!< (@ 0x40050020) Patch Address field */ - __I uint32_t RESERVED1; - __IO uint32_t PATCH_ADDR1_REG; /*!< (@ 0x40050028) Patch Address field */ - __I uint32_t RESERVED2; - __IO uint32_t PATCH_ADDR2_REG; /*!< (@ 0x40050030) Patch Address field */ - __I uint32_t RESERVED3; - __IO uint32_t PATCH_ADDR3_REG; /*!< (@ 0x40050038) Patch Address field */ - __I uint32_t RESERVED4; - __IO uint32_t PATCH_ADDR4_REG; /*!< (@ 0x40050040) Patch Address field */ - __I uint32_t RESERVED5; - __IO uint32_t PATCH_ADDR5_REG; /*!< (@ 0x40050048) Patch Address field */ - __I uint32_t RESERVED6; - __IO uint32_t PATCH_ADDR6_REG; /*!< (@ 0x40050050) Patch Address field */ - __I uint32_t RESERVED7; - __IO uint32_t PATCH_ADDR7_REG; /*!< (@ 0x40050058) Patch Address field */ - __I uint32_t RESERVED8; - __IO uint32_t PATCH_ADDR8_REG; /*!< (@ 0x40050060) Patch Address field */ - __I uint32_t RESERVED9; - __IO uint32_t PATCH_ADDR9_REG; /*!< (@ 0x40050068) Patch Address field */ - __I uint32_t RESERVED10; - __IO uint32_t PATCH_ADDR10_REG; /*!< (@ 0x40050070) Patch Address field */ - __I uint32_t RESERVED11; - __IO uint32_t PATCH_ADDR11_REG; /*!< (@ 0x40050078) Patch Address field */ - __I uint32_t RESERVED12; - __IO uint32_t PATCH_ADDR12_REG; /*!< (@ 0x40050080) Patch Address field */ - __I uint32_t RESERVED13; - __IO uint32_t PATCH_ADDR13_REG; /*!< (@ 0x40050088) Patch Address field */ - __I uint32_t RESERVED14; - __IO uint32_t PATCH_ADDR14_REG; /*!< (@ 0x40050090) Patch Address field */ - __I uint32_t RESERVED15; - __IO uint32_t PATCH_ADDR15_REG; /*!< (@ 0x40050098) Patch Address field */ - __I uint32_t RESERVED16; - __IO uint32_t PATCH_ADDR16_REG; /*!< (@ 0x400500A0) Patch Address field */ - __I uint32_t RESERVED17; - __IO uint32_t PATCH_ADDR17_REG; /*!< (@ 0x400500A8) Patch Address field */ - __I uint32_t RESERVED18; - __IO uint32_t PATCH_ADDR18_REG; /*!< (@ 0x400500B0) Patch Address field */ - __I uint32_t RESERVED19; - __IO uint32_t PATCH_ADDR19_REG; /*!< (@ 0x400500B8) Patch Address field */ - __I uint32_t RESERVED20; - __IO uint32_t PATCH_ADDR20_REG; /*!< (@ 0x400500C0) Patch Address field */ - __IO uint32_t PATCH_DATA20_REG; /*!< (@ 0x400500C4) Patch Data field */ - __IO uint32_t PATCH_ADDR21_REG; /*!< (@ 0x400500C8) Patch Address field */ - __IO uint32_t PATCH_DATA21_REG; /*!< (@ 0x400500CC) Patch Data field */ - __IO uint32_t PATCH_ADDR22_REG; /*!< (@ 0x400500D0) Patch Address field */ - __IO uint32_t PATCH_DATA22_REG; /*!< (@ 0x400500D4) Patch Data field */ - __IO uint32_t PATCH_ADDR23_REG; /*!< (@ 0x400500D8) Patch Address field */ - __IO uint32_t PATCH_DATA23_REG; /*!< (@ 0x400500DC) Patch Data field */ - __IO uint32_t PATCH_ADDR24_REG; /*!< (@ 0x400500E0) Patch Address field */ - __IO uint32_t PATCH_DATA24_REG; /*!< (@ 0x400500E4) Patch Data field */ - __IO uint32_t PATCH_ADDR25_REG; /*!< (@ 0x400500E8) Patch Address field */ - __IO uint32_t PATCH_DATA25_REG; /*!< (@ 0x400500EC) Patch Data field */ - __IO uint32_t PATCH_ADDR26_REG; /*!< (@ 0x400500F0) Patch Address field */ - __IO uint32_t PATCH_DATA26_REG; /*!< (@ 0x400500F4) Patch Data field */ - __IO uint32_t PATCH_ADDR27_REG; /*!< (@ 0x400500F8) Patch Address field */ - __IO uint32_t PATCH_DATA27_REG; /*!< (@ 0x400500FC) Patch Data field */ -} PATCH_Type; - - -/* ================================================================================ */ -/* ================ PLLDIG ================ */ -/* ================================================================================ */ - - -/** - * @brief PLLDIG registers (PLLDIG) - */ - -typedef struct { /*!< (@ 0x50002D00) PLLDIG Structure */ - __IO uint16_t RF_SYNTH_CTRL1_BLE_REG; /*!< (@ 0x50002D00) RF_SYNTH_CTRL1_BLE_REG */ - __IO uint16_t RF_SYNTH_CTRL1_FTDF_REG; /*!< (@ 0x50002D02) RF_SYNTH_CTRL1_FTDF_REG */ - __IO uint16_t RF_SYNTH_CTRL2_BLE_REG; /*!< (@ 0x50002D04) RF_SYNTH_CTRL2_BLE_REG */ - __IO uint16_t RF_SYNTH_CTRL2_FTDF_REG; /*!< (@ 0x50002D06) RF_SYNTH_CTRL2_FTDF_REG */ - __IO uint16_t RF_SYNTH_CTRL3_REG; /*!< (@ 0x50002D08) RF_SYNTH_CTRL3_REG */ - __IO uint16_t RF_VCOCAL_CTRL_REG; /*!< (@ 0x50002D0A) RF_VCOCAL_CTRL_REG */ - __IO uint16_t RF_MGAIN_CTRL_BLE_REG; /*!< (@ 0x50002D0C) RF_MGAIN_CTRL_BLE_REG */ - __IO uint16_t RF_MGAIN_CTRL_FTDF_REG; /*!< (@ 0x50002D0E) RF_MGAIN_CTRL_FTDF_REG */ - __IO uint16_t RF_MGAIN_CTRL2_REG; /*!< (@ 0x50002D10) RF_MGAIN_CTRL2_REG */ - __IO uint16_t RF_VCO_CALCAP_BIT14_REG; /*!< (@ 0x50002D12) RF_VCO_CALCAP_BIT14_REG */ - __IO uint16_t RF_VCO_CALCAP_BIT15_REG; /*!< (@ 0x50002D14) RF_VCO_CALCAP_BIT15_REG */ - __IO uint16_t RF_BMCW_REG; /*!< (@ 0x50002D16) RF_BMCW_REG */ - __IO uint16_t RF_KMOD_ALPHA_BLE_REG; /*!< (@ 0x50002D18) RF_KMOD_ALPHA_BLE_REG */ - __IO uint16_t RF_KMOD_ALPHA_FTDF_REG; /*!< (@ 0x50002D1A) RF_KMOD_ALPHA_FTDF_REG */ - __I uint16_t RESERVED; - __IO uint16_t RF_SYNTH_RESULT_BLE_REG; /*!< (@ 0x50002D1E) Must be Retained */ - __IO uint16_t RF_SYNTH_RESULT_FTDF_REG; /*!< (@ 0x50002D20) Must be Retained */ - __IO uint16_t RF_SYNTH_RESULT2_BLE_REG; /*!< (@ 0x50002D22) Must be Retained */ - __IO uint16_t RF_SYNTH_RESULT2_FTDF_REG; /*!< (@ 0x50002D24) Must be Retained */ - __IO uint16_t RF_SYNTH_RESULT3_FTDF_REG; /*!< (@ 0x50002D26) RF_SYNTH_RESULT3_FTDF_REG */ - __IO uint16_t RF_CALCAP1_REG; /*!< (@ 0x50002D28) RF_CALCAP1_REG */ - __IO uint16_t RF_CALCAP2_REG; /*!< (@ 0x50002D2A) RF_CALCAP2_REG */ - __IO uint16_t RF_NMD_OFFSET_REG; /*!< (@ 0x50002D2C) Offset values for phase alignment after VCO calibration. */ - __I uint16_t RESERVED1; - __IO uint16_t RF_FTDF_PHYATTR_REG; /*!< (@ 0x50002D30) RF_FTDF_PHYATTR_REG */ - __IO uint16_t RF_CALTRIM_STEP1_REG; /*!< (@ 0x50002D32) RF_CALTRIM_STEP1_REG */ - __IO uint16_t RF_CALTRIM_STEP2_REG; /*!< (@ 0x50002D34) RF_CALTRIM_STEP2_REG */ - __IO uint16_t RF_CALTRIM_STEP3_REG; /*!< (@ 0x50002D36) RF_CALTRIM_STEP3_REG */ - __IO uint16_t RF_CALTRIM_STEP4_REG; /*!< (@ 0x50002D38) RF_CALTRIM_STEP4_REG */ - __IO uint16_t RF_MGAIN_CTRL3_REG; /*!< (@ 0x50002D3A) RF_MGAIN_CTRL3_REG */ - __IO uint16_t RF_VCO_FREQ_EST_REG; /*!< (@ 0x50002D3C) RF_VCO_FREQ_EST_REG */ - __I uint16_t RESERVED2; - __IO uint16_t RF_SYNTH_SPARE_REG; /*!< (@ 0x50002D40) MSK modulator control register */ - __IO uint16_t RF_MSKMOD_CTRL1_REG; /*!< (@ 0x50002D42) MSK modulator control register */ - __IO uint16_t RF_MSKMOD_CHIPL_REG; /*!< (@ 0x50002D44) MSK modulator CHIP control lower 16 bit */ - __IO uint16_t RF_MSKMOD_CHIPH_REG; /*!< (@ 0x50002D46) MSK modulator CHIP control upper 16 bit */ - __IO uint16_t RF_TXDAC_TEST_REG; /*!< (@ 0x50002D48) Register to provide value to TXDAC */ - __I uint16_t RESERVED3[3]; - __IO uint16_t RF_MGAIN_COMP_VAL0_REG; /*!< (@ 0x50002D50) RF_MGAIN_COMP_VAL0_REG */ - __IO uint16_t RF_MGAIN_COMP_VAL1_REG; /*!< (@ 0x50002D52) RF_MGAIN_COMP_VAL1_REG */ - __IO uint16_t RF_MGAIN_COMP_VAL2_REG; /*!< (@ 0x50002D54) RF_MGAIN_COMP_VAL2_REG */ - __IO uint16_t RF_MGAIN_COMP_VAL3_REG; /*!< (@ 0x50002D56) RF_MGAIN_COMP_VAL3_REG */ - __IO uint16_t RF_MGAIN_COMP_VAL4_REG; /*!< (@ 0x50002D58) RF_MGAIN_COMP_VAL4_REG */ - __IO uint16_t RF_MGAIN_COMP_VAL5_REG; /*!< (@ 0x50002D5A) RF_MGAIN_COMP_VAL5_REG */ - __IO uint16_t RF_MGAIN_COMP_VAL6_REG; /*!< (@ 0x50002D5C) RF_MGAIN_COMP_VAL6_REG */ - __IO uint16_t RF_MGAIN_COMP_VAL7_REG; /*!< (@ 0x50002D5E) RF_MGAIN_COMP_VAL7_REG */ - __IO uint16_t RF_PULSE_TBL_0_REG; /*!< (@ 0x50002D60) RF_PULSE_TBL_0_REG */ - __IO uint16_t RF_PULSE_TBL_1_REG; /*!< (@ 0x50002D62) RF_PULSE_TBL_1_REG */ - __IO uint16_t RF_PULSE_TBL_2_REG; /*!< (@ 0x50002D64) RF_PULSE_TBL_2_REG */ - __IO uint16_t RF_PULSE_TBL_3_REG; /*!< (@ 0x50002D66) RF_PULSE_TBL_3_REG */ - __IO uint16_t RF_PULSE_TBL_4_REG; /*!< (@ 0x50002D68) RF_PULSE_TBL_4_REG */ - __IO uint16_t RF_PULSE_TBL_5_REG; /*!< (@ 0x50002D6A) RF_PULSE_TBL_5_REG */ - __IO uint16_t RF_PULSE_TBL_6_REG; /*!< (@ 0x50002D6C) RF_PULSE_TBL_6_REG */ - __IO uint16_t RF_PULSE_TBL_7_REG; /*!< (@ 0x50002D6E) RF_PULSE_TBL_7_REG */ - __IO uint16_t RF_PULSE_CTRL_REG; /*!< (@ 0x50002D70) RF_PULSE_CTRL_REG */ -} PLLDIG_Type; - - -/* ================================================================================ */ -/* ================ QSPIC ================ */ -/* ================================================================================ */ - - -/** - * @brief QSPIC registers (QSPIC) - */ - -typedef struct { /*!< (@ 0x0C000000) QSPIC Structure */ - __IO uint32_t QSPIC_CTRLBUS_REG; /*!< (@ 0x0C000000) SPI Bus control register for the Manual mode */ - __IO uint32_t QSPIC_CTRLMODE_REG; /*!< (@ 0x0C000004) Mode Control register */ - __IO uint32_t QSPIC_RECVDATA_REG; /*!< (@ 0x0C000008) Received data for the Manual mode */ - __IO uint32_t QSPIC_BURSTCMDA_REG; /*!< (@ 0x0C00000C) The way of reading in Auto mode (command register - A) */ - __IO uint32_t QSPIC_BURSTCMDB_REG; /*!< (@ 0x0C000010) The way of reading in Auto mode (command register - B) */ - __IO uint32_t QSPIC_STATUS_REG; /*!< (@ 0x0C000014) The status register of the QSPI controller */ - __IO uint32_t QSPIC_WRITEDATA_REG; /*!< (@ 0x0C000018) Write data to SPI Bus for the Manual mode */ - __IO uint32_t QSPIC_READDATA_REG; /*!< (@ 0x0C00001C) Read data from SPI Bus for the Manual mode */ - __IO uint32_t QSPIC_DUMMYDATA_REG; /*!< (@ 0x0C000020) Send dummy clocks to SPI Bus for the Manual mode */ - __IO uint32_t QSPIC_ERASECTRL_REG; /*!< (@ 0x0C000024) QSPI Erase control register */ - __IO uint32_t QSPIC_ERASECMDA_REG; /*!< (@ 0x0C000028) The way of erasing in Auto mode (command register - A) */ - __IO uint32_t QSPIC_ERASECMDB_REG; /*!< (@ 0x0C00002C) The way of erasing in Auto mode (command register - B) */ - __IO uint32_t QSPIC_BURSTBRK_REG; /*!< (@ 0x0C000030) Read break sequence in Auto mode */ - __IO uint32_t QSPIC_STATUSCMD_REG; /*!< (@ 0x0C000034) The way of reading the status of external device - in Auto mode */ - __IO uint32_t QSPIC_CHCKERASE_REG; /*!< (@ 0x0C000038) Check erase progress in Auto mode */ - __IO uint32_t QSPIC_GP_REG; /*!< (@ 0x0C00003C) QSPI General Purpose control register */ - __IO uint32_t QSPIC_UCODE_START; /*!< (@ 0x0C000040) QSPIC uCode memory */ -} QSPIC_Type; - - -/* ================================================================================ */ -/* ================ QUAD ================ */ -/* ================================================================================ */ - - -/** - * @brief QUAD registers (QUAD) - */ - -typedef struct { /*!< (@ 0x50001A00) QUAD Structure */ - __IO uint16_t QDEC_CTRL_REG; /*!< (@ 0x50001A00) Quad decoder control register */ - __IO uint16_t QDEC_XCNT_REG; /*!< (@ 0x50001A02) Counter value of the X Axis */ - __IO uint16_t QDEC_YCNT_REG; /*!< (@ 0x50001A04) Counter value of the Y Axis */ - __IO uint16_t QDEC_ZCNT_REG; /*!< (@ 0x50001A06) Counter value of the Z Axis */ - __IO uint16_t QDEC_CLOCKDIV_REG; /*!< (@ 0x50001A08) Quad decoder clock divider register */ -} QUAD_Type; - - -/* ================================================================================ */ -/* ================ RFCU ================ */ -/* ================================================================================ */ - - -/** - * @brief RFCU registers (RFCU) - */ - -typedef struct { /*!< (@ 0x50002000) RFCU Structure */ - __I uint32_t RESERVED[4]; - __IO uint16_t RF_OVERRULE_REG; /*!< (@ 0x50002010) RF_OVERRULE_REG */ - __IO uint16_t RF_DIAGIRQ01_REG; /*!< (@ 0x50002012) BLE/RF Diagnostic IRQ Control Register */ - __IO uint16_t RF_DIAGIRQ23_REG; /*!< (@ 0x50002014) BLE/RF Diagnostic IRQ Control Register */ - __IO uint16_t RF_DIAGIRQ_STAT_REG; /*!< (@ 0x50002016) BLE/RF Diagnostic IRQ Status Register */ - __IO uint16_t RF_AGC_EXT1_LUT_REG; /*!< (@ 0x50002018) RF_AGC_EXT1_LUT_REG */ - __I uint16_t RESERVED1[3]; - __IO uint16_t RF_CALSTATE_REG; /*!< (@ 0x50002020) RF_CALSTATE_REG */ - __I uint16_t RESERVED2[15]; - __IO uint16_t RF_SCAN_FEEDBACK_REG; /*!< (@ 0x50002040) RF_SCAN_FEEDBACK_REG */ - __IO uint16_t RF_REF_OSC_BLE_REG; /*!< (@ 0x50002042) RF_REF_OSC_BLE_REG */ - __IO uint16_t RF_REF_OSC_FTDF_REG; /*!< (@ 0x50002044) RF_REF_OSC_FTDF_REG */ - __I uint16_t RESERVED3[5]; - __IO uint16_t RF_CAL_CTRL_REG; /*!< (@ 0x50002050) RF_CAL_CTRL_REG */ - __I uint16_t RESERVED4; - __IO uint16_t RF_IRQ_CTRL_REG; /*!< (@ 0x50002054) RF_IRQ_CTRL_REG */ - __I uint16_t RESERVED5; - __IO uint16_t RF_ADCI_DC_OFFSET_REG; /*!< (@ 0x50002058) Must be Retained */ - __IO uint16_t RF_ADCQ_DC_OFFSET_REG; /*!< (@ 0x5000205A) Must be Retained */ - __I uint32_t RESERVED6[9]; - __IO uint16_t RF_SPARE1_BLE_REG; /*!< (@ 0x50002080) RF_SPARE1_BLE_REG */ - __IO uint16_t RF_SPARE1_FTDF_REG; /*!< (@ 0x50002082) RF_SPARE1_FTDF_REG */ - __IO uint16_t RF_BIAS_CTRL1_BLE_REG; /*!< (@ 0x50002084) RF_BIAS_CTRL1_BLE_REG */ - __IO uint16_t RF_BIAS_CTRL1_FTDF_REG; /*!< (@ 0x50002086) RF_BIAS_CTRL1_FTDF_REG */ - __IO uint16_t RF_IFF_CTRL1_REG; /*!< (@ 0x50002088) RF_IFF_CTRL1_REG */ - __IO uint16_t RF_ADC_CTRL1_REG; /*!< (@ 0x5000208A) RF_ADC_CTRL1_REG */ - __IO uint16_t RF_ADC_CTRL2_REG; /*!< (@ 0x5000208C) RF_ADC_CTRL2_REG */ - __IO uint16_t RF_ADC_CTRL3_REG; /*!< (@ 0x5000208E) RF_ADC_CTRL3_REG */ - __IO uint16_t RF_PA_CTRL_REG; /*!< (@ 0x50002090) Removed obsolete values of bits 10:7, pa_pw back - to 4 */ - __IO uint16_t RF_MGC_CTRL_REG; /*!< (@ 0x50002092) RF_MGC_CTRL_REG */ - __IO uint16_t RF_VCOVAR_CTRL_REG; /*!< (@ 0x50002094) RF_VCOVAR_CTRL_REG */ - __IO uint16_t RF_PFD_CTRL_REG; /*!< (@ 0x50002096) RF_PFD_CTRL_REG */ - __IO uint16_t RF_CP_CTRL_BLE_REG; /*!< (@ 0x50002098) RF_CP_CTRL_BLE_REG */ - __IO uint16_t RF_CP_CTRL_FTDF_REG; /*!< (@ 0x5000209A) RF_CP_CTRL_FTDF_REG */ - __IO uint16_t RF_LF_RES_CTRL_BLE_REG; /*!< (@ 0x5000209C) LF resistor setting in BLE mode */ - __IO uint16_t RF_LF_RES_CTRL_FTDF_REG; /*!< (@ 0x5000209E) LF resistor setting in FTDF mode */ - __IO uint16_t RF_MIXER_CTRL1_BLE_REG; /*!< (@ 0x500020A0) RF_MIXER_CTRL1_BLE_REG */ - __IO uint16_t RF_MIXER_CTRL1_FTDF_REG; /*!< (@ 0x500020A2) RF_MIXER_CTRL1_FTDF_REG */ - __IO uint16_t RF_MIXER_CTRL2_REG; /*!< (@ 0x500020A4) RF_MIXER_CTRL2_REG */ - __IO uint16_t RF_LF_CTRL_REG; /*!< (@ 0x500020A6) RF_LF_CTRL_REG */ - __IO uint16_t RF_TDC_CTRL_REG; /*!< (@ 0x500020A8) TDC settings */ - __IO uint16_t RF_IO_CTRL1_REG; /*!< (@ 0x500020AA) RF_IO_CTRL1_REG */ - __IO uint16_t RF_LNA_CTRL1_REG; /*!< (@ 0x500020AC) RF_LNA_CTRL1_REG */ - __IO uint16_t RF_LNA_CTRL2_REG; /*!< (@ 0x500020AE) RF_LNA_CTRL2_REG */ - __IO uint16_t RF_LNA_CTRL3_REG; /*!< (@ 0x500020B0) RF_LNA_CTRL3_REG */ - __IO uint16_t RF_VCO_AMP_CTRL1_REG; /*!< (@ 0x500020B2) RF_VCO_AMP_CTRL1_REG */ - __IO uint16_t RF_VCO_AMP_CTRL2_REG; /*!< (@ 0x500020B4) RF_VCO_AMP_CTRL2_REG */ - __I uint16_t RESERVED7[5]; - __IO uint16_t RF_TX_PWR_BLE_REG; /*!< (@ 0x500020C0) TX Power setting */ - __IO uint16_t RF_TX_PWR_LUT_1_REG; /*!< (@ 0x500020C2) TX Power setting 1 */ - __IO uint16_t RF_TX_PWR_LUT_2_REG; /*!< (@ 0x500020C4) TX Power setting 2 */ - __IO uint16_t RF_TX_PWR_LUT_3_REG; /*!< (@ 0x500020C6) TX Power setting 3 */ - __IO uint16_t RF_TX_PWR_LUT_4_REG; /*!< (@ 0x500020C8) TX Power setting 4 */ - __IO uint16_t RF_TX_PWR_LUT_5_REG; /*!< (@ 0x500020CA) TX Power setting 5 */ - __IO uint16_t RF_TX_PWR_LUT_6_REG; /*!< (@ 0x500020CC) TX Power setting 6 */ - __IO uint16_t RF_TX_PWR_LUT_7_REG; /*!< (@ 0x500020CE) TX Power setting 7 */ - __IO uint16_t RF_TX_PWR_FTDF_REG; /*!< (@ 0x500020D0) TX Power setting */ - __IO uint16_t RF_TX_PWR_LUT_RD_REG; /*!< (@ 0x500020D2) TX Power read back */ - __IO uint16_t RF_DIV_IQ_RX_REG; /*!< (@ 0x500020D4) Bias trimming of IQ divider */ - __IO uint16_t RF_DIV_IQ_TX_REG; /*!< (@ 0x500020D6) Bias trimming of IQ divider */ - __IO uint16_t RF_LO_IQ_TRIM_REG; /*!< (@ 0x500020D8) Trim settings for IQ LO path */ - __IO uint16_t RF_TXDAC_CTRL_REG; /*!< (@ 0x500020DA) Control settings for the TXDAC */ - __IO uint16_t RF_TXDAC_CAL_CAP_STAT_REG; /*!< (@ 0x500020DC) Current CAL CAP value for TXDAC */ - __I uint16_t RESERVED8; - __IO uint16_t RF_IFF_RESULT_REG; /*!< (@ 0x500020E0) Not retained */ - __IO uint16_t RF_IFF_CC_BLE_SET1_REG; /*!< (@ 0x500020E2) Must be retained */ - __IO uint16_t RF_IFF_CC_BLE_SET2_REG; /*!< (@ 0x500020E4) Must be retained */ - __IO uint16_t RF_IFF_CC_FTDF_SET1_REG; /*!< (@ 0x500020E6) Must be retained */ - __IO uint16_t RF_IFF_CC_FTDF_SET2_REG; /*!< (@ 0x500020E8) Must be retained */ - __IO uint16_t RF_IFF_CAL_CAP_STAT_REG; /*!< (@ 0x500020EA) Current CAL_CAP value applied to IF */ - __IO uint16_t RF_MIX_CAL_CAP_STAT_REG; /*!< (@ 0x500020EC) Current CAL_CAP value applied to IF */ - __IO uint16_t RF_LF_CAL_CAP_STAT_REG; /*!< (@ 0x500020EE) Current CAL_CAP value applied to IF */ -} RFCU_Type; - - -/* ================================================================================ */ -/* ================ RFCU_POWER ================ */ -/* ================================================================================ */ - - -/** - * @brief RFCU_POWER registers (RFCU_POWER) - */ - -typedef struct { /*!< (@ 0x50002200) RFCU_POWER Structure */ - __IO uint16_t RF_ENABLE_CONFIG0_REG; /*!< (@ 0x50002200) RF_ENABLE_CONFIG0_REG */ - __IO uint16_t RF_ENABLE_CONFIG1_REG; /*!< (@ 0x50002202) RF_ENABLE_CONFIG1_REG */ - __IO uint16_t RF_ENABLE_CONFIG2_REG; /*!< (@ 0x50002204) RF_ENABLE_CONFIG2_REG */ - __IO uint16_t RF_ENABLE_CONFIG3_REG; /*!< (@ 0x50002206) RF_ENABLE_CONFIG3_REG */ - __IO uint16_t RF_ENABLE_CONFIG4_REG; /*!< (@ 0x50002208) RF_ENABLE_CONFIG4_REG */ - __IO uint16_t RF_ENABLE_CONFIG5_REG; /*!< (@ 0x5000220A) RF_ENABLE_CONFIG5_REG */ - __IO uint16_t RF_ENABLE_CONFIG6_REG; /*!< (@ 0x5000220C) RF_ENABLE_CONFIG6_REG */ - __IO uint16_t RF_ENABLE_CONFIG7_REG; /*!< (@ 0x5000220E) RF_ENABLE_CONFIG7_REG */ - __IO uint16_t RF_ENABLE_CONFIG8_REG; /*!< (@ 0x50002210) RF_ENABLE_CONFIG8_REG */ - __IO uint16_t RF_ENABLE_CONFIG9_REG; /*!< (@ 0x50002212) RF_ENABLE_CONFIG9_REG */ - __IO uint16_t RF_ENABLE_CONFIG10_REG; /*!< (@ 0x50002214) RF_ENABLE_CONFIG10_REG */ - __IO uint16_t RF_ENABLE_CONFIG11_REG; /*!< (@ 0x50002216) RF_ENABLE_CONFIG11_REG */ - __IO uint16_t RF_ENABLE_CONFIG12_REG; /*!< (@ 0x50002218) RF_ENABLE_CONFIG12_REG */ - __IO uint16_t RF_ENABLE_CONFIG13_REG; /*!< (@ 0x5000221A) RF_ENABLE_CONFIG13_REG */ - __IO uint16_t RF_ENABLE_CONFIG14_REG; /*!< (@ 0x5000221C) RF_ENABLE_CONFIG14_REG */ - __IO uint16_t RF_ENABLE_CONFIG15_REG; /*!< (@ 0x5000221E) RF_ENABLE_CONFIG15_REG */ - __IO uint16_t RF_ENABLE_CONFIG16_REG; /*!< (@ 0x50002220) RF_ENABLE_CONFIG16_REG */ - __IO uint16_t RF_ENABLE_CONFIG17_REG; /*!< (@ 0x50002222) RF_ENABLE_CONFIG17_REG */ - __IO uint16_t RF_ENABLE_CONFIG18_REG; /*!< (@ 0x50002224) RF_ENABLE_CONFIG18_REG */ - __IO uint16_t RF_ENABLE_CONFIG19_REG; /*!< (@ 0x50002226) RF_ENABLE_CONFIG19_REG */ - __IO uint16_t RF_ENABLE_CONFIG20_REG; /*!< (@ 0x50002228) RF_ENABLE_CONFIG20_REG */ - __IO uint16_t RF_ENABLE_CONFIG21_REG; /*!< (@ 0x5000222A) RF_ENABLE_CONFIG21_REG */ - __IO uint16_t RF_ENABLE_CONFIG22_REG; /*!< (@ 0x5000222C) RF_ENABLE_CONFIG22_REG */ - __IO uint16_t RF_ENABLE_CONFIG23_BLE_REG; /*!< (@ 0x5000222E) RF_ENABLE_CONFIG23_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG24_BLE_REG; /*!< (@ 0x50002230) RF_ENABLE_CONFIG24_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG25_REG; /*!< (@ 0x50002232) RF_ENABLE_CONFIG25_REG */ - __IO uint16_t RF_ENABLE_CONFIG26_REG; /*!< (@ 0x50002234) RF_ENABLE_CONFIG26_REG */ - __IO uint16_t RF_ENABLE_CONFIG27_REG; /*!< (@ 0x50002236) RF_ENABLE_CONFIG27_REG */ - __IO uint16_t RF_ENABLE_CONFIG28_REG; /*!< (@ 0x50002238) RF_ENABLE_CONFIG28_REG */ - __IO uint16_t RF_ENABLE_CONFIG29_REG; /*!< (@ 0x5000223A) RF_ENABLE_CONFIG29_REG */ - __IO uint16_t RF_ENABLE_CONFIG30_REG; /*!< (@ 0x5000223C) RF_ENABLE_CONFIG30_REG */ - __IO uint16_t RF_ENABLE_CONFIG31_BLE_REG; /*!< (@ 0x5000223E) RF_ENABLE_CONFIG31_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG32_REG; /*!< (@ 0x50002240) RF_ENABLE_CONFIG32_REG */ - __IO uint16_t RF_ENABLE_CONFIG33_REG; /*!< (@ 0x50002242) RF_ENABLE_CONFIG33_REG */ - __IO uint16_t RF_ENABLE_CONFIG34_REG; /*!< (@ 0x50002244) RF_ENABLE_CONFIG34_REG */ - __IO uint16_t RF_ENABLE_CONFIG35_BLE_REG; /*!< (@ 0x50002246) RF_ENABLE_CONFIG35_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG36_REG; /*!< (@ 0x50002248) RF_ENABLE_CONFIG36_REG */ - __IO uint16_t RF_ENABLE_CONFIG37_BLE_REG; /*!< (@ 0x5000224A) RF_ENABLE_CONFIG37_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG38_BLE_REG; /*!< (@ 0x5000224C) RF_ENABLE_CONFIG38_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG39_REG; /*!< (@ 0x5000224E) RF_ENABLE_CONFIG39_REG */ - __IO uint16_t RF_ENABLE_CONFIG40_REG; /*!< (@ 0x50002250) RF_ENABLE_CONFIG40_REG */ - __IO uint16_t RF_ENABLE_CONFIG41_REG; /*!< (@ 0x50002252) RF_ENABLE_CONFIG41_REG */ - __IO uint16_t RF_ENABLE_CONFIG42_REG; /*!< (@ 0x50002254) RF_ENABLE_CONFIG42_REG */ - __IO uint16_t RF_ENABLE_CONFIG43_REG; /*!< (@ 0x50002256) RF_ENABLE_CONFIG43_REG */ - __IO uint16_t RF_ENABLE_CONFIG44_BLE_REG; /*!< (@ 0x50002258) RF_ENABLE_CONFIG44_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG45_BLE_REG; /*!< (@ 0x5000225A) RF_ENABLE_CONFIG45_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG46_BLE_REG; /*!< (@ 0x5000225C) RF_ENABLE_CONFIG46_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG47_BLE_REG; /*!< (@ 0x5000225E) RF_ENABLE_CONFIG47_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG48_BLE_REG; /*!< (@ 0x50002260) RF_ENABLE_CONFIG48_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG49_BLE_REG; /*!< (@ 0x50002262) RF_ENABLE_CONFIG49_BLE_REG */ - __I uint16_t RESERVED[37]; - __IO uint16_t RF_ENABLE_CONFIG23_FTDF_REG; /*!< (@ 0x500022AE) RF_ENABLE_CONFIG23_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG24_FTDF_REG; /*!< (@ 0x500022B0) RF_ENABLE_CONFIG24_FTDF_REG */ - __I uint16_t RESERVED1[6]; - __IO uint16_t RF_ENABLE_CONFIG31_FTDF_REG; /*!< (@ 0x500022BE) RF_ENABLE_CONFIG31_FTDF_REG */ - __I uint16_t RESERVED2[3]; - __IO uint16_t RF_ENABLE_CONFIG35_FTDF_REG; /*!< (@ 0x500022C6) RF_ENABLE_CONFIG35_FTDF_REG */ - __I uint16_t RESERVED3; - __IO uint16_t RF_ENABLE_CONFIG37_FTDF_REG; /*!< (@ 0x500022CA) RF_ENABLE_CONFIG37_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG38_FTDF_REG; /*!< (@ 0x500022CC) RF_ENABLE_CONFIG38_FTDF_REG */ - __I uint16_t RESERVED4[5]; - __IO uint16_t RF_ENABLE_CONFIG44_FTDF_REG; /*!< (@ 0x500022D8) RF_ENABLE_CONFIG44_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG45_FTDF_REG; /*!< (@ 0x500022DA) RF_ENABLE_CONFIG45_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG46_FTDF_REG; /*!< (@ 0x500022DC) RF_ENABLE_CONFIG46_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG47_FTDF_REG; /*!< (@ 0x500022DE) RF_ENABLE_CONFIG47_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG48_FTDF_REG; /*!< (@ 0x500022E0) RF_ENABLE_CONFIG48_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG49_FTDF_REG; /*!< (@ 0x500022E2) RF_ENABLE_CONFIG49_FTDF_REG */ - __I uint16_t RESERVED5[15]; - __IO uint16_t RF_CNTRL_TIMER_1_REG; /*!< (@ 0x50002302) RF_CNTRL_TIMER_1_REG */ - __IO uint16_t RF_CNTRL_TIMER_2_REG; /*!< (@ 0x50002304) RF_CNTRL_TIMER_2_REG */ - __IO uint16_t RF_CNTRL_TIMER_3_REG; /*!< (@ 0x50002306) RF_CNTRL_TIMER_3_REG */ - __IO uint16_t RF_CNTRL_TIMER_4_REG; /*!< (@ 0x50002308) RF_CNTRL_TIMER_4_REG */ - __IO uint16_t RF_CNTRL_TIMER_5_REG; /*!< (@ 0x5000230A) RF_CNTRL_TIMER_5_REG */ - __IO uint16_t RF_CNTRL_TIMER_6_REG; /*!< (@ 0x5000230C) RF_CNTRL_TIMER_6_REG */ - __IO uint16_t RF_CNTRL_TIMER_7_REG; /*!< (@ 0x5000230E) RF_CNTRL_TIMER_7_REG */ - __IO uint16_t RF_CNTRL_TIMER_8_REG; /*!< (@ 0x50002310) RF_CNTRL_TIMER_8_REG */ - __IO uint16_t RF_CNTRL_TIMER_9_REG; /*!< (@ 0x50002312) RF_CNTRL_TIMER_9_REG */ - __IO uint16_t RF_CNTRL_TIMER_10_REG; /*!< (@ 0x50002314) RF_CNTRL_TIMER_10_REG */ - __IO uint16_t RF_CNTRL_TIMER_11_REG; /*!< (@ 0x50002316) RF_CNTRL_TIMER_11_REG */ - __IO uint16_t RF_CNTRL_TIMER_12_REG; /*!< (@ 0x50002318) RF_CNTRL_TIMER_12_REG */ - __IO uint16_t RF_CNTRL_TIMER_13_REG; /*!< (@ 0x5000231A) RF_CNTRL_TIMER_13_REG */ - __IO uint16_t RF_CNTRL_TIMER_14_REG; /*!< (@ 0x5000231C) RF_CNTRL_TIMER_14_REG */ - __IO uint16_t RF_CNTRL_TIMER_15_REG; /*!< (@ 0x5000231E) RF_CNTRL_TIMER_15_REG */ - __IO uint16_t RF_CNTRL_TIMER_16_REG; /*!< (@ 0x50002320) RF_CNTRL_TIMER_16_REG */ - __IO uint16_t RF_CNTRL_TIMER_17_REG; /*!< (@ 0x50002322) RF_CNTRL_TIMER_17_REG */ - __IO uint16_t RF_CNTRL_TIMER_18_REG; /*!< (@ 0x50002324) RF_CNTRL_TIMER_18_REG */ - __IO uint16_t RF_CNTRL_TIMER_19_REG; /*!< (@ 0x50002326) RF_CNTRL_TIMER_19_REG */ - __IO uint16_t RF_CNTRL_TIMER_20_REG; /*!< (@ 0x50002328) RF_CNTRL_TIMER_20_REG */ - __IO uint16_t RF_CNTRL_TIMER_21_REG; /*!< (@ 0x5000232A) RF_CNTRL_TIMER_21_REG */ - __IO uint16_t RF_CNTRL_TIMER_22_REG; /*!< (@ 0x5000232C) RF_CNTRL_TIMER_22_REG */ - __IO uint16_t RF_CNTRL_TIMER_23_REG; /*!< (@ 0x5000232E) RF_CNTRL_TIMER_23_REG */ - __IO uint16_t RF_CNTRL_TIMER_24_REG; /*!< (@ 0x50002330) RF_CNTRL_TIMER_24_REG */ - __IO uint16_t RF_CNTRL_TIMER_25_REG; /*!< (@ 0x50002332) RF_CNTRL_TIMER_25_REG */ - __IO uint16_t RF_CNTRL_TIMER_26_REG; /*!< (@ 0x50002334) RF_CNTRL_TIMER_26_REG */ - __IO uint16_t RF_CNTRL_TIMER_27_REG; /*!< (@ 0x50002336) RF_CNTRL_TIMER_27_REG */ - __IO uint16_t RF_CNTRL_TIMER_28_REG; /*!< (@ 0x50002338) RF_CNTRL_TIMER_28_REG */ - __IO uint16_t RF_CNTRL_TIMER_29_REG; /*!< (@ 0x5000233A) RF_CNTRL_TIMER_29_REG */ - __IO uint16_t RF_CNTRL_TIMER_30_REG; /*!< (@ 0x5000233C) RF_CNTRL_TIMER_30_REG */ - __IO uint16_t RF_CNTRL_TIMER_31_REG; /*!< (@ 0x5000233E) RF_CNTRL_TIMER_31_REG */ - __I uint32_t RESERVED6[16]; - __IO uint16_t RF_ALWAYS_EN1_REG; /*!< (@ 0x50002380) RF_ALWAYS_EN1_REG */ - __IO uint16_t RF_ALWAYS_EN2_REG; /*!< (@ 0x50002382) RF_ALWAYS_EN2_REG */ - __IO uint16_t RF_ALWAYS_EN3_REG; /*!< (@ 0x50002384) RF_ALWAYS_EN3_REG */ - __IO uint16_t RF_ALWAYS_EN4_REG; /*!< (@ 0x50002386) RF_ALWAYS_EN4_REG */ - __IO uint16_t RF_PORT_EN_BLE_REG; /*!< (@ 0x50002388) RF_PORT_EN_BLE_REG */ - __IO uint16_t RF_PORT_EN_FTDF_REG; /*!< (@ 0x5000238A) RF_PORT_EN_FTDF_REG */ - __IO uint16_t RF_PORT_POL_REG; /*!< (@ 0x5000238C) RF_PORT_POL_REG */ -} RFCU_POWER_Type; - - -/* ================================================================================ */ -/* ================ RFPT ================ */ -/* ================================================================================ */ - - -/** - * @brief RFPT registers (RFPT) - */ - -typedef struct { /*!< (@ 0x50003600) RFPT Structure */ - __IO uint16_t RFPT_CTRL_REG; /*!< (@ 0x50003600) Control register */ - __IO uint16_t RFPT_ADDRL_REG; /*!< (@ 0x50003602) AHB master start address (Low part) */ - __IO uint16_t RFPT_ADDRH_REG; /*!< (@ 0x50003604) AHB master start address (High part) */ - __IO uint16_t RFPT_LEN_REG; /*!< (@ 0x50003606) Data length register */ - __IO uint16_t RFPT_STAT_REG; /*!< (@ 0x50003608) Status register */ - __IO uint16_t RFPT_CRV_ADDRL_REG; /*!< (@ 0x5000360A) AHB master current address (Low part) */ - __IO uint16_t RFPT_CRV_ADDRH_REG; /*!< (@ 0x5000360C) AHB master current address (High part) */ - __IO uint16_t RFPT_CRV_LEN_REG; /*!< (@ 0x5000360E) The remaining data to be transferred */ -} RFPT_Type; - - -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI registers (SPI) - */ - -typedef struct { /*!< (@ 0x50001200) SPI Structure */ - __IO uint16_t SPI_CTRL_REG; /*!< (@ 0x50001200) SPI control register 0 */ - __IO uint16_t SPI_RX_TX_REG0; /*!< (@ 0x50001202) SPI RX/TX register0 */ - __IO uint16_t SPI_RX_TX_REG1; /*!< (@ 0x50001204) SPI RX/TX register1 */ - __IO uint16_t SPI_CLEAR_INT_REG; /*!< (@ 0x50001206) SPI clear interrupt register */ - __IO uint16_t SPI_CTRL_REG1; /*!< (@ 0x50001208) SPI control register 1 */ -} SPI_Type; - - -/* ================================================================================ */ -/* ================ SPI2 ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI2 registers (SPI2) - */ - -typedef struct { /*!< (@ 0x50001300) SPI2 Structure */ - __IO uint16_t SPI2_CTRL_REG; /*!< (@ 0x50001300) SPI control register 0 */ - __IO uint16_t SPI2_RX_TX_REG0; /*!< (@ 0x50001302) SPI RX/TX register0 */ - __IO uint16_t SPI2_RX_TX_REG1; /*!< (@ 0x50001304) SPI RX/TX register1 */ - __IO uint16_t SPI2_CLEAR_INT_REG; /*!< (@ 0x50001306) SPI clear interrupt register */ - __IO uint16_t SPI2_CTRL_REG1; /*!< (@ 0x50001308) SPI control register 1 */ -} SPI2_Type; - - -/* ================================================================================ */ -/* ================ TIMER1 ================ */ -/* ================================================================================ */ - - -/** - * @brief TIMER1 registers (TIMER1) - */ - -typedef struct { /*!< (@ 0x50000200) TIMER1 Structure */ - __IO uint16_t CAPTIM_CTRL_REG; /*!< (@ 0x50000200) Capture Timer control register */ - __IO uint16_t CAPTIM_TIMER_VAL_REG; /*!< (@ 0x50000202) Capture Timer counter value */ - __IO uint16_t CAPTIM_STATUS_REG; /*!< (@ 0x50000204) Capture Timer status register */ - __IO uint16_t CAPTIM_GPIO1_CONF_REG; /*!< (@ 0x50000206) Capture Timer gpio1 selection */ - __IO uint16_t CAPTIM_GPIO2_CONF_REG; /*!< (@ 0x50000208) Capture Timer gpio2 selection */ - __IO uint16_t CAPTIM_RELOAD_REG; /*!< (@ 0x5000020A) Capture Timer reload value and Delay in shot - mode */ - __IO uint16_t CAPTIM_SHOTWIDTH_REG; /*!< (@ 0x5000020C) Capture Timer Shot duration in shot mode */ - __IO uint16_t CAPTIM_PRESCALER_REG; /*!< (@ 0x5000020E) Capture Timer prescaler value */ - __IO uint16_t CAPTIM_CAPTURE_GPIO1_REG; /*!< (@ 0x50000210) Capture Timer value for event on GPIO1 */ - __IO uint16_t CAPTIM_CAPTURE_GPIO2_REG; /*!< (@ 0x50000212) Capture Timer value for event on GPIO2 */ - __IO uint16_t CAPTIM_PRESCALER_VAL_REG; /*!< (@ 0x50000214) Capture Timer interrupt status register */ - __IO uint16_t CAPTIM_PWM_FREQ_REG; /*!< (@ 0x50000216) Capture Timer pwm frequency register */ - __IO uint16_t CAPTIM_PWM_DC_REG; /*!< (@ 0x50000218) Capture Timer pwm dc register */ - __IO uint16_t CAPTIM_TIMER_HVAL_REG; /*!< (@ 0x5000021A) Capture Timer counter high value */ - __IO uint16_t CAPTIM_RELOAD_HIGH_REG; /*!< (@ 0x5000021C) Capture Timer reload high value and Delay in - shot mode */ - __IO uint16_t CAPTIM_CAPTURE_HIGH_GPIO1_REG; /*!< (@ 0x5000021E) Capture Timer high value for event on GPIO01 */ - __IO uint16_t CAPTIM_CAPTURE_HIGH_GPIO2_REG; /*!< (@ 0x50000220) Capture Timer high value for event on GPIO02 */ - __IO uint16_t CAPTIM_SHOTWIDTH_HIGH_REG; /*!< (@ 0x50000222) Capture Timer Shot high duration in shot mode */ -} TIMER1_Type; - - -/* ================================================================================ */ -/* ================ TRNG ================ */ -/* ================================================================================ */ - - -/** - * @brief TRNG registers (TRNG) - */ - -typedef struct { /*!< (@ 0x50005000) TRNG Structure */ - __IO uint32_t TRNG_CTRL_REG; /*!< (@ 0x50005000) TRNG control register */ - __IO uint32_t TRNG_FIFOLVL_REG; /*!< (@ 0x50005004) TRNG FIFO level register */ - __IO uint32_t TRNG_VER_REG; /*!< (@ 0x50005008) TRNG Version register */ -} TRNG_Type; - - -/* ================================================================================ */ -/* ================ UART ================ */ -/* ================================================================================ */ - - -/** - * @brief UART registers (UART) - */ - -typedef struct { /*!< (@ 0x50001000) UART Structure */ - __IO uint16_t UART_RBR_THR_DLL_REG; /*!< (@ 0x50001000) Receive Buffer Register/Transmit Holding Register/Divisor - Latch Low */ - __I uint16_t RESERVED; - __IO uint16_t UART_IER_DLH_REG; /*!< (@ 0x50001004) Interrupt Enable Register/Divisor Latch High */ - __I uint16_t RESERVED1; - __IO uint16_t UART_IIR_FCR_REG; /*!< (@ 0x50001008) Interrupt Identification Register/FIFO Control - Register */ - __I uint16_t RESERVED2; - __IO uint16_t UART_LCR_REG; /*!< (@ 0x5000100C) Line Control Register */ - __I uint16_t RESERVED3; - __IO uint16_t UART_MCR_REG; /*!< (@ 0x50001010) Modem Control Register */ - __I uint16_t RESERVED4; - __IO uint16_t UART_LSR_REG; /*!< (@ 0x50001014) Line Status Register */ - __I uint16_t RESERVED5[3]; - __IO uint16_t UART_SCR_REG; /*!< (@ 0x5000101C) Scratchpad Register */ - __I uint16_t RESERVED6[47]; - __IO uint16_t UART_USR_REG; /*!< (@ 0x5000107C) UART Status register. */ - __I uint16_t RESERVED7[5]; - __IO uint16_t UART_SRR_REG; /*!< (@ 0x50001088) Software Reset Register. */ - __I uint16_t RESERVED8[3]; - __IO uint16_t UART_SBCR_REG; /*!< (@ 0x50001090) Shadow Break Control Register */ - __I uint16_t RESERVED9[11]; - __IO uint16_t UART_DMASA_REG; /*!< (@ 0x500010A8) DMA Software Acknowledge */ - __I uint16_t RESERVED10[11]; - __IO uint16_t UART_DLF_REG; /*!< (@ 0x500010C0) Divisor Latch Fraction Register */ - __I uint16_t RESERVED11[25]; - __IO uint16_t UART_CPR_REG; /*!< (@ 0x500010F4) Component Parameter Register */ - __I uint16_t RESERVED12; - __IO uint16_t UART_UCV_REG; /*!< (@ 0x500010F8) Component Version */ - __I uint16_t RESERVED13; - __IO uint16_t UART_CTR_REG; /*!< (@ 0x500010FC) Component Type Register */ -} UART_Type; - - -/* ================================================================================ */ -/* ================ UART2 ================ */ -/* ================================================================================ */ - - -/** - * @brief UART2 registers (UART2) - */ - -typedef struct { /*!< (@ 0x50001100) UART2 Structure */ - __IO uint16_t UART2_RBR_THR_DLL_REG; /*!< (@ 0x50001100) Receive Buffer Register/Transmit Holding Register/Divisor - Latch Low */ - __I uint16_t RESERVED; - __IO uint16_t UART2_IER_DLH_REG; /*!< (@ 0x50001104) Interrupt Enable Register/Divisor Latch High */ - __I uint16_t RESERVED1; - __IO uint16_t UART2_IIR_FCR_REG; /*!< (@ 0x50001108) Interrupt Identification Register/FIFO Control - Register */ - __I uint16_t RESERVED2; - __IO uint16_t UART2_LCR_REG; /*!< (@ 0x5000110C) Line Control Register */ - __I uint16_t RESERVED3; - __IO uint16_t UART2_MCR_REG; /*!< (@ 0x50001110) Modem Control Register */ - __I uint16_t RESERVED4; - __IO uint16_t UART2_LSR_REG; /*!< (@ 0x50001114) Line Status Register */ - __I uint16_t RESERVED5; - __IO uint16_t UART2_MSR_REG; /*!< (@ 0x50001118) Modem Status Register */ - __I uint16_t RESERVED6; - __IO uint16_t UART2_SCR_REG; /*!< (@ 0x5000111C) Scratchpad Register */ - __I uint16_t RESERVED7[9]; - __IO uint16_t UART2_SRBR_STHR0_REG; /*!< (@ 0x50001130) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED8; - __IO uint16_t UART2_SRBR_STHR1_REG; /*!< (@ 0x50001134) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED9; - __IO uint16_t UART2_SRBR_STHR2_REG; /*!< (@ 0x50001138) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED10; - __IO uint16_t UART2_SRBR_STHR3_REG; /*!< (@ 0x5000113C) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED11; - __IO uint16_t UART2_SRBR_STHR4_REG; /*!< (@ 0x50001140) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED12; - __IO uint16_t UART2_SRBR_STHR5_REG; /*!< (@ 0x50001144) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED13; - __IO uint16_t UART2_SRBR_STHR6_REG; /*!< (@ 0x50001148) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED14; - __IO uint16_t UART2_SRBR_STHR7_REG; /*!< (@ 0x5000114C) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED15; - __IO uint16_t UART2_SRBR_STHR8_REG; /*!< (@ 0x50001150) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED16; - __IO uint16_t UART2_SRBR_STHR9_REG; /*!< (@ 0x50001154) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED17; - __IO uint16_t UART2_SRBR_STHR10_REG; /*!< (@ 0x50001158) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED18; - __IO uint16_t UART2_SRBR_STHR11_REG; /*!< (@ 0x5000115C) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED19; - __IO uint16_t UART2_SRBR_STHR12_REG; /*!< (@ 0x50001160) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED20; - __IO uint16_t UART2_SRBR_STHR13_REG; /*!< (@ 0x50001164) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED21; - __IO uint16_t UART2_SRBR_STHR14_REG; /*!< (@ 0x50001168) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED22; - __IO uint16_t UART2_SRBR_STHR15_REG; /*!< (@ 0x5000116C) Shadow Receive/Transmit Buffer Register */ - __I uint16_t RESERVED23; - __IO uint16_t UART2_FAR_REG; /*!< (@ 0x50001170) FIFO Access Register */ - __I uint16_t RESERVED24[5]; - __IO uint16_t UART2_USR_REG; /*!< (@ 0x5000117C) UART Status Register */ - __I uint16_t RESERVED25; - __IO uint16_t UART2_TFL_REG; /*!< (@ 0x50001180) Transmit FIFO Level */ - __I uint16_t RESERVED26; - __IO uint16_t UART2_RFL_REG; /*!< (@ 0x50001184) Receive FIFO Level */ - __I uint16_t RESERVED27; - __IO uint16_t UART2_SRR_REG; /*!< (@ 0x50001188) Software Reset Register. */ - __I uint16_t RESERVED28; - __IO uint16_t UART2_SRTS_REG; /*!< (@ 0x5000118C) Shadow Request to Send */ - __I uint16_t RESERVED29; - __IO uint16_t UART2_SBCR_REG; /*!< (@ 0x50001190) Shadow Break Control Register */ - __I uint16_t RESERVED30; - __IO uint16_t UART2_SDMAM_REG; /*!< (@ 0x50001194) Shadow DMA Mode */ - __I uint16_t RESERVED31; - __IO uint16_t UART2_SFE_REG; /*!< (@ 0x50001198) Shadow FIFO Enable */ - __I uint16_t RESERVED32; - __IO uint16_t UART2_SRT_REG; /*!< (@ 0x5000119C) Shadow RCVR Trigger */ - __I uint16_t RESERVED33; - __IO uint16_t UART2_STET_REG; /*!< (@ 0x500011A0) Shadow TX Empty Trigger */ - __I uint16_t RESERVED34; - __IO uint16_t UART2_HTX_REG; /*!< (@ 0x500011A4) Halt TX */ - __I uint16_t RESERVED35; - __IO uint16_t UART2_DMASA_REG; /*!< (@ 0x500011A8) DMA Software Acknowledge */ - __I uint16_t RESERVED36[11]; - __IO uint16_t UART2_DLF_REG; /*!< (@ 0x500011C0) Divisor Latch Fraction Register */ - __I uint16_t RESERVED37[25]; - __IO uint16_t UART2_CPR_REG; /*!< (@ 0x500011F4) Component Parameter Register */ - __I uint16_t RESERVED38; - __IO uint16_t UART2_UCV_REG; /*!< (@ 0x500011F8) Component Version */ - __I uint16_t RESERVED39; - __IO uint16_t UART2_CTR_REG; /*!< (@ 0x500011FC) Component Type Register */ -} UART2_Type; - - -/* ================================================================================ */ -/* ================ USB ================ */ -/* ================================================================================ */ - - -/** - * @brief USB registers (USB) - */ - -typedef struct { /*!< (@ 0x50001800) USB Structure */ - __IO uint16_t USB_MCTRL_REG; /*!< (@ 0x50001800) Main Control Register) */ - __IO uint16_t USB_XCVDIAG_REG; /*!< (@ 0x50001802) Transceiver diagnostic Register (for test purpose - only) */ - __IO uint16_t USB_TCR_REG; /*!< (@ 0x50001804) Transceiver configuration Register */ - __IO uint16_t USB_UTR_REG; /*!< (@ 0x50001806) USB test Register (for test purpose only) */ - __IO uint16_t USB_FAR_REG; /*!< (@ 0x50001808) Function Address Register */ - __IO uint16_t USB_NFSR_REG; /*!< (@ 0x5000180A) Node Functional State Register */ - __IO uint16_t USB_MAEV_REG; /*!< (@ 0x5000180C) Main Event Register */ - __IO uint16_t USB_MAMSK_REG; /*!< (@ 0x5000180E) Main Mask Register */ - __IO uint16_t USB_ALTEV_REG; /*!< (@ 0x50001810) Alternate Event Register */ - __IO uint16_t USB_ALTMSK_REG; /*!< (@ 0x50001812) Alternate Mask Register */ - __IO uint16_t USB_TXEV_REG; /*!< (@ 0x50001814) Transmit Event Register */ - __IO uint16_t USB_TXMSK_REG; /*!< (@ 0x50001816) Transmit Mask Register */ - __IO uint16_t USB_RXEV_REG; /*!< (@ 0x50001818) Receive Event Register */ - __IO uint16_t USB_RXMSK_REG; /*!< (@ 0x5000181A) Receive Mask Register */ - __IO uint16_t USB_NAKEV_REG; /*!< (@ 0x5000181C) NAK Event Register */ - __IO uint16_t USB_NAKMSK_REG; /*!< (@ 0x5000181E) NAK Mask Register */ - __IO uint16_t USB_FWEV_REG; /*!< (@ 0x50001820) FIFO Warning Event Register */ - __IO uint16_t USB_FWMSK_REG; /*!< (@ 0x50001822) FIFO Warning Mask Register */ - __IO uint16_t USB_FNH_REG; /*!< (@ 0x50001824) Frame Number High Byte Register */ - __IO uint16_t USB_FNL_REG; /*!< (@ 0x50001826) Frame Number Low Byte Register */ - __I uint16_t RESERVED[11]; - __IO uint16_t USB_UX20CDR_REG; /*!< (@ 0x5000183E) Transceiver 2.0 Configuration and Diagnostics - Register(for test purpose only) */ - __IO uint16_t USB_EPC0_REG; /*!< (@ 0x50001840) Endpoint Control 0 Register */ - __IO uint16_t USB_TXD0_REG; /*!< (@ 0x50001842) Transmit Data 0 Register */ - __IO uint16_t USB_TXS0_REG; /*!< (@ 0x50001844) Transmit Status 0 Register */ - __IO uint16_t USB_TXC0_REG; /*!< (@ 0x50001846) Transmit command 0 Register */ - __IO uint16_t USB_EP0_NAK_REG; /*!< (@ 0x50001848) EP0 INNAK and OUTNAK Register */ - __IO uint16_t USB_RXD0_REG; /*!< (@ 0x5000184A) Receive Data 0 Register */ - __IO uint16_t USB_RXS0_REG; /*!< (@ 0x5000184C) Receive Status 0 Register */ - __IO uint16_t USB_RXC0_REG; /*!< (@ 0x5000184E) Receive Command 0 Register */ - __IO uint16_t USB_EPC1_REG; /*!< (@ 0x50001850) Endpoint Control Register 1 */ - __IO uint16_t USB_TXD1_REG; /*!< (@ 0x50001852) Transmit Data Register 1 */ - __IO uint16_t USB_TXS1_REG; /*!< (@ 0x50001854) Transmit Status Register 1 */ - __IO uint16_t USB_TXC1_REG; /*!< (@ 0x50001856) Transmit Command Register 1 */ - __IO uint16_t USB_EPC2_REG; /*!< (@ 0x50001858) Endpoint Control Register 2 */ - __IO uint16_t USB_RXD1_REG; /*!< (@ 0x5000185A) Receive Data Register,1 */ - __IO uint16_t USB_RXS1_REG; /*!< (@ 0x5000185C) Receive Status Register 1 */ - __IO uint16_t USB_RXC1_REG; /*!< (@ 0x5000185E) Receive Command Register 1 */ - __IO uint16_t USB_EPC3_REG; /*!< (@ 0x50001860) Endpoint Control Register 3 */ - __IO uint16_t USB_TXD2_REG; /*!< (@ 0x50001862) Transmit Data Register 2 */ - __IO uint16_t USB_TXS2_REG; /*!< (@ 0x50001864) Transmit Status Register 2 */ - __IO uint16_t USB_TXC2_REG; /*!< (@ 0x50001866) Transmit Command Register 2 */ - __IO uint16_t USB_EPC4_REG; /*!< (@ 0x50001868) Endpoint Control Register 4 */ - __IO uint16_t USB_RXD2_REG; /*!< (@ 0x5000186A) Receive Data Register 2 */ - __IO uint16_t USB_RXS2_REG; /*!< (@ 0x5000186C) Receive Status Register 2 */ - __IO uint16_t USB_RXC2_REG; /*!< (@ 0x5000186E) Receive Command Register 2 */ - __IO uint16_t USB_EPC5_REG; /*!< (@ 0x50001870) Endpoint Control Register 5 */ - __IO uint16_t USB_TXD3_REG; /*!< (@ 0x50001872) Transmit Data Register 3 */ - __IO uint16_t USB_TXS3_REG; /*!< (@ 0x50001874) Transmit Status Register 3 */ - __IO uint16_t USB_TXC3_REG; /*!< (@ 0x50001876) Transmit Command Register 3 */ - __IO uint16_t USB_EPC6_REG; /*!< (@ 0x50001878) Endpoint Control Register 6 */ - __IO uint16_t USB_RXD3_REG; /*!< (@ 0x5000187A) Receive Data Register 3 */ - __IO uint16_t USB_RXS3_REG; /*!< (@ 0x5000187C) Receive Status Register 3 */ - __IO uint16_t USB_RXC3_REG; /*!< (@ 0x5000187E) Receive Command Register 3 */ - __I uint32_t RESERVED1[20]; - __IO uint16_t USB_DMA_CTRL_REG; /*!< (@ 0x500018D0) USB DMA control register */ - __I uint16_t RESERVED2; - __IO uint16_t USB_CHARGER_CTRL_REG; /*!< (@ 0x500018D4) USB Charger Control Register */ - __IO uint16_t USB_CHARGER_STAT_REG; /*!< (@ 0x500018D6) USB Charger Status Register */ -} USB_Type; - - -/* ================================================================================ */ -/* ================ WAKEUP ================ */ -/* ================================================================================ */ - - -/** - * @brief WAKEUP registers (WAKEUP) - */ - -typedef struct { /*!< (@ 0x50000100) WAKEUP Structure */ - __IO uint16_t WKUP_CTRL_REG; /*!< (@ 0x50000100) Control register for the wakeup counter */ - __I uint16_t RESERVED; - __IO uint16_t WKUP_RESET_IRQ_REG; /*!< (@ 0x50000104) Reset wakeup interrupt */ - __I uint16_t RESERVED1[2]; - __IO uint16_t WKUP_SELECT_P0_REG; /*!< (@ 0x5000010A) select which inputs from P0 port can trigger - wkup counter */ - __IO uint16_t WKUP_SELECT_P1_REG; /*!< (@ 0x5000010C) select which inputs from P1 port can trigger - wkup counter */ - __IO uint16_t WKUP_SELECT_P2_REG; /*!< (@ 0x5000010E) select which inputs from P2 port can trigger - wkup counter */ - __IO uint16_t WKUP_SELECT_P3_REG; /*!< (@ 0x50000110) select which inputs from P3 port can trigger - wkup counter */ - __IO uint16_t WKUP_SELECT_P4_REG; /*!< (@ 0x50000112) select which inputs from P3 port can trigger - wkup counter */ - __IO uint16_t WKUP_POL_P0_REG; /*!< (@ 0x50000114) select the sesitivity polarity for each P0 input */ - __IO uint16_t WKUP_POL_P1_REG; /*!< (@ 0x50000116) select the sesitivity polarity for each P1 input */ - __IO uint16_t WKUP_POL_P2_REG; /*!< (@ 0x50000118) select the sesitivity polarity for each P2 input */ - __IO uint16_t WKUP_POL_P3_REG; /*!< (@ 0x5000011A) select the sesitivity polarity for each P3 input */ - __IO uint16_t WKUP_POL_P4_REG; /*!< (@ 0x5000011C) select the sesitivity polarity for each P3 input */ - __IO uint16_t WKUP_STATUS_0_REG; /*!< (@ 0x5000011E) Event status register for P0 and P1 */ - __IO uint16_t WKUP_STATUS_1_REG; /*!< (@ 0x50000120) Event status register for P2 */ - __IO uint16_t WKUP_STATUS_2_REG; /*!< (@ 0x50000122) Event status register for P3 and P4 */ - __IO uint16_t WKUP_CLEAR_0_REG; /*!< (@ 0x50000124) Clear event register for P0 and P1 */ - __IO uint16_t WKUP_CLEAR_1_REG; /*!< (@ 0x50000126) Clear event register for P2 */ - __IO uint16_t WKUP_CLEAR_2_REG; /*!< (@ 0x50000128) Clear event register for P3 and P4 */ - __IO uint16_t WKUP_SEL_GPIO_P0_REG; /*!< (@ 0x5000012A) select which inputs from P0 port can trigger - interrupt */ - __IO uint16_t WKUP_SEL_GPIO_P1_REG; /*!< (@ 0x5000012C) select which inputs from P1 port can trigger - interrupt */ - __IO uint16_t WKUP_SEL_GPIO_P2_REG; /*!< (@ 0x5000012E) select which inputs from P2 port can trigger - interrupt */ - __IO uint16_t WKUP_SEL_GPIO_P3_REG; /*!< (@ 0x50000130) select which inputs from P3 port can trigger - interrupt */ - __IO uint16_t WKUP_SEL_GPIO_P4_REG; /*!< (@ 0x50000132) select which inputs from P3 port can trigger - interrupt */ -} WAKEUP_Type; - - -/* ================================================================================ */ -/* ================ WDOG ================ */ -/* ================================================================================ */ - - -/** - * @brief WDOG registers (WDOG) - */ - -typedef struct { /*!< (@ 0x50003100) WDOG Structure */ - __IO uint16_t WATCHDOG_REG; /*!< (@ 0x50003100) Watchdog timer register. */ - __IO uint16_t WATCHDOG_CTRL_REG; /*!< (@ 0x50003102) Watchdog control register. */ -} WDOG_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - -/* ================================================================================ */ -/* ================ struct 'NVIC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------------- NVIC_ISER --------------------------------- */ -#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Pos (0UL) /*!< NVIC ISER: BLE_WAKEUP_LP_IRQn (Bit 0) */ -#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Msk (0x1UL) /*!< NVIC ISER: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_BLE_GEN_IRQn_Pos (1UL) /*!< NVIC ISER: BLE_GEN_IRQn (Bit 1) */ -#define NVIC_ISER_BLE_GEN_IRQn_Msk (0x2UL) /*!< NVIC ISER: BLE_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_FTDF_WAKEUP_IRQn_Pos (2UL) /*!< NVIC ISER: FTDF_WAKEUP_IRQn (Bit 2) */ -#define NVIC_ISER_FTDF_WAKEUP_IRQn_Msk (0x4UL) /*!< NVIC ISER: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_FTDF_GEN_IRQn_Pos (3UL) /*!< NVIC ISER: FTDF_GEN_IRQn (Bit 3) */ -#define NVIC_ISER_FTDF_GEN_IRQn_Msk (0x8UL) /*!< NVIC ISER: FTDF_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_RFCAL_IRQn_Pos (4UL) /*!< NVIC ISER: RFCAL_IRQn (Bit 4) */ -#define NVIC_ISER_RFCAL_IRQn_Msk (0x10UL) /*!< NVIC ISER: RFCAL_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_COEX_IRQn_Pos (5UL) /*!< NVIC ISER: COEX_IRQn (Bit 5) */ -#define NVIC_ISER_COEX_IRQn_Msk (0x20UL) /*!< NVIC ISER: COEX_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_CRYPTO_IRQn_Pos (6UL) /*!< NVIC ISER: CRYPTO_IRQn (Bit 6) */ -#define NVIC_ISER_CRYPTO_IRQn_Msk (0x40UL) /*!< NVIC ISER: CRYPTO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_MRM_IRQn_Pos (7UL) /*!< NVIC ISER: MRM_IRQn (Bit 7) */ -#define NVIC_ISER_MRM_IRQn_Msk (0x80UL) /*!< NVIC ISER: MRM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_UART_IRQn_Pos (8UL) /*!< NVIC ISER: UART_IRQn (Bit 8) */ -#define NVIC_ISER_UART_IRQn_Msk (0x100UL) /*!< NVIC ISER: UART_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_UART2_IRQn_Pos (9UL) /*!< NVIC ISER: UART2_IRQn (Bit 9) */ -#define NVIC_ISER_UART2_IRQn_Msk (0x200UL) /*!< NVIC ISER: UART2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_I2C_IRQn_Pos (10UL) /*!< NVIC ISER: I2C_IRQn (Bit 10) */ -#define NVIC_ISER_I2C_IRQn_Msk (0x400UL) /*!< NVIC ISER: I2C_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_I2C2_IRQn_Pos (11UL) /*!< NVIC ISER: I2C2_IRQn (Bit 11) */ -#define NVIC_ISER_I2C2_IRQn_Msk (0x800UL) /*!< NVIC ISER: I2C2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_SPI_IRQn_Pos (12UL) /*!< NVIC ISER: SPI_IRQn (Bit 12) */ -#define NVIC_ISER_SPI_IRQn_Msk (0x1000UL) /*!< NVIC ISER: SPI_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_SPI2_IRQn_Pos (13UL) /*!< NVIC ISER: SPI2_IRQn (Bit 13) */ -#define NVIC_ISER_SPI2_IRQn_Msk (0x2000UL) /*!< NVIC ISER: SPI2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_ADC_IRQn_Pos (14UL) /*!< NVIC ISER: ADC_IRQn (Bit 14) */ -#define NVIC_ISER_ADC_IRQn_Msk (0x4000UL) /*!< NVIC ISER: ADC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_KEYBRD_IRQn_Pos (15UL) /*!< NVIC ISER: KEYBRD_IRQn (Bit 15) */ -#define NVIC_ISER_KEYBRD_IRQn_Msk (0x8000UL) /*!< NVIC ISER: KEYBRD_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_IRGEN_IRQn_Pos (16UL) /*!< NVIC ISER: IRGEN_IRQn (Bit 16) */ -#define NVIC_ISER_IRGEN_IRQn_Msk (0x10000UL) /*!< NVIC ISER: IRGEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_WKUP_GPIO_IRQn_Pos (17UL) /*!< NVIC ISER: WKUP_GPIO_IRQn (Bit 17) */ -#define NVIC_ISER_WKUP_GPIO_IRQn_Msk (0x20000UL) /*!< NVIC ISER: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_SWTIM0_IRQn_Pos (18UL) /*!< NVIC ISER: SWTIM0_IRQn (Bit 18) */ -#define NVIC_ISER_SWTIM0_IRQn_Msk (0x40000UL) /*!< NVIC ISER: SWTIM0_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_SWTIM1_IRQn_Pos (19UL) /*!< NVIC ISER: SWTIM1_IRQn (Bit 19) */ -#define NVIC_ISER_SWTIM1_IRQn_Msk (0x80000UL) /*!< NVIC ISER: SWTIM1_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_QUADEC_IRQn_Pos (20UL) /*!< NVIC ISER: QUADEC_IRQn (Bit 20) */ -#define NVIC_ISER_QUADEC_IRQn_Msk (0x100000UL) /*!< NVIC ISER: QUADEC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_USB_IRQn_Pos (21UL) /*!< NVIC ISER: USB_IRQn (Bit 21) */ -#define NVIC_ISER_USB_IRQn_Msk (0x200000UL) /*!< NVIC ISER: USB_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_PCM_IRQn_Pos (22UL) /*!< NVIC ISER: PCM_IRQn (Bit 22) */ -#define NVIC_ISER_PCM_IRQn_Msk (0x400000UL) /*!< NVIC ISER: PCM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_SRC_IN_IRQn_Pos (23UL) /*!< NVIC ISER: SRC_IN_IRQn (Bit 23) */ -#define NVIC_ISER_SRC_IN_IRQn_Msk (0x800000UL) /*!< NVIC ISER: SRC_IN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_SRC_OUT_IRQn_Pos (24UL) /*!< NVIC ISER: SRC_OUT_IRQn (Bit 24) */ -#define NVIC_ISER_SRC_OUT_IRQn_Msk (0x1000000UL) /*!< NVIC ISER: SRC_OUT_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_VBUS_IRQn_Pos (25UL) /*!< NVIC ISER: VBUS_IRQn (Bit 25) */ -#define NVIC_ISER_VBUS_IRQn_Msk (0x2000000UL) /*!< NVIC ISER: VBUS_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_DMA_IRQn_Pos (26UL) /*!< NVIC ISER: DMA_IRQn (Bit 26) */ -#define NVIC_ISER_DMA_IRQn_Msk (0x4000000UL) /*!< NVIC ISER: DMA_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_RF_DIAG_IRQn_Pos (27UL) /*!< NVIC ISER: RF_DIAG_IRQn (Bit 27) */ -#define NVIC_ISER_RF_DIAG_IRQn_Msk (0x8000000UL) /*!< NVIC ISER: RF_DIAG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_TRNG_IRQn_Pos (28UL) /*!< NVIC ISER: TRNG_IRQn (Bit 28) */ -#define NVIC_ISER_TRNG_IRQn_Msk (0x10000000UL) /*!< NVIC ISER: TRNG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_DCDC_IRQn_Pos (29UL) /*!< NVIC ISER: DCDC_IRQn (Bit 29) */ -#define NVIC_ISER_DCDC_IRQn_Msk (0x20000000UL) /*!< NVIC ISER: DCDC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_XTAL16RDY_IRQn_Pos (30UL) /*!< NVIC ISER: XTAL16RDY_IRQn (Bit 30) */ -#define NVIC_ISER_XTAL16RDY_IRQn_Msk (0x40000000UL) /*!< NVIC ISER: XTAL16RDY_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISER_Rsvd__irq__n_Pos (31UL) /*!< NVIC ISER: Rsvd__irq__n (Bit 31) */ -#define NVIC_ISER_Rsvd__irq__n_Msk (0x80000000UL) /*!< NVIC ISER: Rsvd__irq__n (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- NVIC_ICER --------------------------------- */ -#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Pos (0UL) /*!< NVIC ICER: BLE_WAKEUP_LP_IRQn (Bit 0) */ -#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Msk (0x1UL) /*!< NVIC ICER: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_BLE_GEN_IRQn_Pos (1UL) /*!< NVIC ICER: BLE_GEN_IRQn (Bit 1) */ -#define NVIC_ICER_BLE_GEN_IRQn_Msk (0x2UL) /*!< NVIC ICER: BLE_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_FTDF_WAKEUP_IRQn_Pos (2UL) /*!< NVIC ICER: FTDF_WAKEUP_IRQn (Bit 2) */ -#define NVIC_ICER_FTDF_WAKEUP_IRQn_Msk (0x4UL) /*!< NVIC ICER: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_FTDF_GEN_IRQn_Pos (3UL) /*!< NVIC ICER: FTDF_GEN_IRQn (Bit 3) */ -#define NVIC_ICER_FTDF_GEN_IRQn_Msk (0x8UL) /*!< NVIC ICER: FTDF_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_RFCAL_IRQn_Pos (4UL) /*!< NVIC ICER: RFCAL_IRQn (Bit 4) */ -#define NVIC_ICER_RFCAL_IRQn_Msk (0x10UL) /*!< NVIC ICER: RFCAL_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_COEX_IRQn_Pos (5UL) /*!< NVIC ICER: COEX_IRQn (Bit 5) */ -#define NVIC_ICER_COEX_IRQn_Msk (0x20UL) /*!< NVIC ICER: COEX_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_CRYPTO_IRQn_Pos (6UL) /*!< NVIC ICER: CRYPTO_IRQn (Bit 6) */ -#define NVIC_ICER_CRYPTO_IRQn_Msk (0x40UL) /*!< NVIC ICER: CRYPTO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_MRM_IRQn_Pos (7UL) /*!< NVIC ICER: MRM_IRQn (Bit 7) */ -#define NVIC_ICER_MRM_IRQn_Msk (0x80UL) /*!< NVIC ICER: MRM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_UART_IRQn_Pos (8UL) /*!< NVIC ICER: UART_IRQn (Bit 8) */ -#define NVIC_ICER_UART_IRQn_Msk (0x100UL) /*!< NVIC ICER: UART_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_UART2_IRQn_Pos (9UL) /*!< NVIC ICER: UART2_IRQn (Bit 9) */ -#define NVIC_ICER_UART2_IRQn_Msk (0x200UL) /*!< NVIC ICER: UART2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_I2C_IRQn_Pos (10UL) /*!< NVIC ICER: I2C_IRQn (Bit 10) */ -#define NVIC_ICER_I2C_IRQn_Msk (0x400UL) /*!< NVIC ICER: I2C_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_I2C2_IRQn_Pos (11UL) /*!< NVIC ICER: I2C2_IRQn (Bit 11) */ -#define NVIC_ICER_I2C2_IRQn_Msk (0x800UL) /*!< NVIC ICER: I2C2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_SPI_IRQn_Pos (12UL) /*!< NVIC ICER: SPI_IRQn (Bit 12) */ -#define NVIC_ICER_SPI_IRQn_Msk (0x1000UL) /*!< NVIC ICER: SPI_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_SPI2_IRQn_Pos (13UL) /*!< NVIC ICER: SPI2_IRQn (Bit 13) */ -#define NVIC_ICER_SPI2_IRQn_Msk (0x2000UL) /*!< NVIC ICER: SPI2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_ADC_IRQn_Pos (14UL) /*!< NVIC ICER: ADC_IRQn (Bit 14) */ -#define NVIC_ICER_ADC_IRQn_Msk (0x4000UL) /*!< NVIC ICER: ADC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_KEYBRD_IRQn_Pos (15UL) /*!< NVIC ICER: KEYBRD_IRQn (Bit 15) */ -#define NVIC_ICER_KEYBRD_IRQn_Msk (0x8000UL) /*!< NVIC ICER: KEYBRD_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_IRGEN_IRQn_Pos (16UL) /*!< NVIC ICER: IRGEN_IRQn (Bit 16) */ -#define NVIC_ICER_IRGEN_IRQn_Msk (0x10000UL) /*!< NVIC ICER: IRGEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_WKUP_GPIO_IRQn_Pos (17UL) /*!< NVIC ICER: WKUP_GPIO_IRQn (Bit 17) */ -#define NVIC_ICER_WKUP_GPIO_IRQn_Msk (0x20000UL) /*!< NVIC ICER: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_SWTIM0_IRQn_Pos (18UL) /*!< NVIC ICER: SWTIM0_IRQn (Bit 18) */ -#define NVIC_ICER_SWTIM0_IRQn_Msk (0x40000UL) /*!< NVIC ICER: SWTIM0_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_SWTIM1_IRQn_Pos (19UL) /*!< NVIC ICER: SWTIM1_IRQn (Bit 19) */ -#define NVIC_ICER_SWTIM1_IRQn_Msk (0x80000UL) /*!< NVIC ICER: SWTIM1_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_QUADEC_IRQn_Pos (20UL) /*!< NVIC ICER: QUADEC_IRQn (Bit 20) */ -#define NVIC_ICER_QUADEC_IRQn_Msk (0x100000UL) /*!< NVIC ICER: QUADEC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_USB_IRQn_Pos (21UL) /*!< NVIC ICER: USB_IRQn (Bit 21) */ -#define NVIC_ICER_USB_IRQn_Msk (0x200000UL) /*!< NVIC ICER: USB_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_PCM_IRQn_Pos (22UL) /*!< NVIC ICER: PCM_IRQn (Bit 22) */ -#define NVIC_ICER_PCM_IRQn_Msk (0x400000UL) /*!< NVIC ICER: PCM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_SRC_IN_IRQn_Pos (23UL) /*!< NVIC ICER: SRC_IN_IRQn (Bit 23) */ -#define NVIC_ICER_SRC_IN_IRQn_Msk (0x800000UL) /*!< NVIC ICER: SRC_IN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_SRC_OUT_IRQn_Pos (24UL) /*!< NVIC ICER: SRC_OUT_IRQn (Bit 24) */ -#define NVIC_ICER_SRC_OUT_IRQn_Msk (0x1000000UL) /*!< NVIC ICER: SRC_OUT_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_VBUS_IRQn_Pos (25UL) /*!< NVIC ICER: VBUS_IRQn (Bit 25) */ -#define NVIC_ICER_VBUS_IRQn_Msk (0x2000000UL) /*!< NVIC ICER: VBUS_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_DMA_IRQn_Pos (26UL) /*!< NVIC ICER: DMA_IRQn (Bit 26) */ -#define NVIC_ICER_DMA_IRQn_Msk (0x4000000UL) /*!< NVIC ICER: DMA_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_RF_DIAG_IRQn_Pos (27UL) /*!< NVIC ICER: RF_DIAG_IRQn (Bit 27) */ -#define NVIC_ICER_RF_DIAG_IRQn_Msk (0x8000000UL) /*!< NVIC ICER: RF_DIAG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_TRNG_IRQn_Pos (28UL) /*!< NVIC ICER: TRNG_IRQn (Bit 28) */ -#define NVIC_ICER_TRNG_IRQn_Msk (0x10000000UL) /*!< NVIC ICER: TRNG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_DCDC_IRQn_Pos (29UL) /*!< NVIC ICER: DCDC_IRQn (Bit 29) */ -#define NVIC_ICER_DCDC_IRQn_Msk (0x20000000UL) /*!< NVIC ICER: DCDC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_XTAL16RDY_IRQn_Pos (30UL) /*!< NVIC ICER: XTAL16RDY_IRQn (Bit 30) */ -#define NVIC_ICER_XTAL16RDY_IRQn_Msk (0x40000000UL) /*!< NVIC ICER: XTAL16RDY_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICER_Rsvd__irq__n_Pos (31UL) /*!< NVIC ICER: Rsvd__irq__n (Bit 31) */ -#define NVIC_ICER_Rsvd__irq__n_Msk (0x80000000UL) /*!< NVIC ICER: Rsvd__irq__n (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- NVIC_ISPR --------------------------------- */ -#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Pos (0UL) /*!< NVIC ISPR: BLE_WAKEUP_LP_IRQn (Bit 0) */ -#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Msk (0x1UL) /*!< NVIC ISPR: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_BLE_GEN_IRQn_Pos (1UL) /*!< NVIC ISPR: BLE_GEN_IRQn (Bit 1) */ -#define NVIC_ISPR_BLE_GEN_IRQn_Msk (0x2UL) /*!< NVIC ISPR: BLE_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Pos (2UL) /*!< NVIC ISPR: FTDF_WAKEUP_IRQn (Bit 2) */ -#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Msk (0x4UL) /*!< NVIC ISPR: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_FTDF_GEN_IRQn_Pos (3UL) /*!< NVIC ISPR: FTDF_GEN_IRQn (Bit 3) */ -#define NVIC_ISPR_FTDF_GEN_IRQn_Msk (0x8UL) /*!< NVIC ISPR: FTDF_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_RFCAL_IRQn_Pos (4UL) /*!< NVIC ISPR: RFCAL_IRQn (Bit 4) */ -#define NVIC_ISPR_RFCAL_IRQn_Msk (0x10UL) /*!< NVIC ISPR: RFCAL_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_COEX_IRQn_Pos (5UL) /*!< NVIC ISPR: COEX_IRQn (Bit 5) */ -#define NVIC_ISPR_COEX_IRQn_Msk (0x20UL) /*!< NVIC ISPR: COEX_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_CRYPTO_IRQn_Pos (6UL) /*!< NVIC ISPR: CRYPTO_IRQn (Bit 6) */ -#define NVIC_ISPR_CRYPTO_IRQn_Msk (0x40UL) /*!< NVIC ISPR: CRYPTO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_MRM_IRQn_Pos (7UL) /*!< NVIC ISPR: MRM_IRQn (Bit 7) */ -#define NVIC_ISPR_MRM_IRQn_Msk (0x80UL) /*!< NVIC ISPR: MRM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_UART_IRQn_Pos (8UL) /*!< NVIC ISPR: UART_IRQn (Bit 8) */ -#define NVIC_ISPR_UART_IRQn_Msk (0x100UL) /*!< NVIC ISPR: UART_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_UART2_IRQn_Pos (9UL) /*!< NVIC ISPR: UART2_IRQn (Bit 9) */ -#define NVIC_ISPR_UART2_IRQn_Msk (0x200UL) /*!< NVIC ISPR: UART2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_I2C_IRQn_Pos (10UL) /*!< NVIC ISPR: I2C_IRQn (Bit 10) */ -#define NVIC_ISPR_I2C_IRQn_Msk (0x400UL) /*!< NVIC ISPR: I2C_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_I2C2_IRQn_Pos (11UL) /*!< NVIC ISPR: I2C2_IRQn (Bit 11) */ -#define NVIC_ISPR_I2C2_IRQn_Msk (0x800UL) /*!< NVIC ISPR: I2C2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_SPI_IRQn_Pos (12UL) /*!< NVIC ISPR: SPI_IRQn (Bit 12) */ -#define NVIC_ISPR_SPI_IRQn_Msk (0x1000UL) /*!< NVIC ISPR: SPI_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_SPI2_IRQn_Pos (13UL) /*!< NVIC ISPR: SPI2_IRQn (Bit 13) */ -#define NVIC_ISPR_SPI2_IRQn_Msk (0x2000UL) /*!< NVIC ISPR: SPI2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_ADC_IRQn_Pos (14UL) /*!< NVIC ISPR: ADC_IRQn (Bit 14) */ -#define NVIC_ISPR_ADC_IRQn_Msk (0x4000UL) /*!< NVIC ISPR: ADC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_KEYBRD_IRQn_Pos (15UL) /*!< NVIC ISPR: KEYBRD_IRQn (Bit 15) */ -#define NVIC_ISPR_KEYBRD_IRQn_Msk (0x8000UL) /*!< NVIC ISPR: KEYBRD_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_IRGEN_IRQn_Pos (16UL) /*!< NVIC ISPR: IRGEN_IRQn (Bit 16) */ -#define NVIC_ISPR_IRGEN_IRQn_Msk (0x10000UL) /*!< NVIC ISPR: IRGEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_WKUP_GPIO_IRQn_Pos (17UL) /*!< NVIC ISPR: WKUP_GPIO_IRQn (Bit 17) */ -#define NVIC_ISPR_WKUP_GPIO_IRQn_Msk (0x20000UL) /*!< NVIC ISPR: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_SWTIM0_IRQn_Pos (18UL) /*!< NVIC ISPR: SWTIM0_IRQn (Bit 18) */ -#define NVIC_ISPR_SWTIM0_IRQn_Msk (0x40000UL) /*!< NVIC ISPR: SWTIM0_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_SWTIM1_IRQn_Pos (19UL) /*!< NVIC ISPR: SWTIM1_IRQn (Bit 19) */ -#define NVIC_ISPR_SWTIM1_IRQn_Msk (0x80000UL) /*!< NVIC ISPR: SWTIM1_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_QUADEC_IRQn_Pos (20UL) /*!< NVIC ISPR: QUADEC_IRQn (Bit 20) */ -#define NVIC_ISPR_QUADEC_IRQn_Msk (0x100000UL) /*!< NVIC ISPR: QUADEC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_USB_IRQn_Pos (21UL) /*!< NVIC ISPR: USB_IRQn (Bit 21) */ -#define NVIC_ISPR_USB_IRQn_Msk (0x200000UL) /*!< NVIC ISPR: USB_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_PCM_IRQn_Pos (22UL) /*!< NVIC ISPR: PCM_IRQn (Bit 22) */ -#define NVIC_ISPR_PCM_IRQn_Msk (0x400000UL) /*!< NVIC ISPR: PCM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_SRC_IN_IRQn_Pos (23UL) /*!< NVIC ISPR: SRC_IN_IRQn (Bit 23) */ -#define NVIC_ISPR_SRC_IN_IRQn_Msk (0x800000UL) /*!< NVIC ISPR: SRC_IN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_SRC_OUT_IRQn_Pos (24UL) /*!< NVIC ISPR: SRC_OUT_IRQn (Bit 24) */ -#define NVIC_ISPR_SRC_OUT_IRQn_Msk (0x1000000UL) /*!< NVIC ISPR: SRC_OUT_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_VBUS_IRQn_Pos (25UL) /*!< NVIC ISPR: VBUS_IRQn (Bit 25) */ -#define NVIC_ISPR_VBUS_IRQn_Msk (0x2000000UL) /*!< NVIC ISPR: VBUS_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_DMA_IRQn_Pos (26UL) /*!< NVIC ISPR: DMA_IRQn (Bit 26) */ -#define NVIC_ISPR_DMA_IRQn_Msk (0x4000000UL) /*!< NVIC ISPR: DMA_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_RF_DIAG_IRQn_Pos (27UL) /*!< NVIC ISPR: RF_DIAG_IRQn (Bit 27) */ -#define NVIC_ISPR_RF_DIAG_IRQn_Msk (0x8000000UL) /*!< NVIC ISPR: RF_DIAG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_TRNG_IRQn_Pos (28UL) /*!< NVIC ISPR: TRNG_IRQn (Bit 28) */ -#define NVIC_ISPR_TRNG_IRQn_Msk (0x10000000UL) /*!< NVIC ISPR: TRNG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_DCDC_IRQn_Pos (29UL) /*!< NVIC ISPR: DCDC_IRQn (Bit 29) */ -#define NVIC_ISPR_DCDC_IRQn_Msk (0x20000000UL) /*!< NVIC ISPR: DCDC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_XTAL16RDY_IRQn_Pos (30UL) /*!< NVIC ISPR: XTAL16RDY_IRQn (Bit 30) */ -#define NVIC_ISPR_XTAL16RDY_IRQn_Msk (0x40000000UL) /*!< NVIC ISPR: XTAL16RDY_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ISPR_Rsvd__irq__n_Pos (31UL) /*!< NVIC ISPR: Rsvd__irq__n (Bit 31) */ -#define NVIC_ISPR_Rsvd__irq__n_Msk (0x80000000UL) /*!< NVIC ISPR: Rsvd__irq__n (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- NVIC_ICPR --------------------------------- */ -#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Pos (0UL) /*!< NVIC ICPR: BLE_WAKEUP_LP_IRQn (Bit 0) */ -#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Msk (0x1UL) /*!< NVIC ICPR: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_BLE_GEN_IRQn_Pos (1UL) /*!< NVIC ICPR: BLE_GEN_IRQn (Bit 1) */ -#define NVIC_ICPR_BLE_GEN_IRQn_Msk (0x2UL) /*!< NVIC ICPR: BLE_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Pos (2UL) /*!< NVIC ICPR: FTDF_WAKEUP_IRQn (Bit 2) */ -#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Msk (0x4UL) /*!< NVIC ICPR: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_FTDF_GEN_IRQn_Pos (3UL) /*!< NVIC ICPR: FTDF_GEN_IRQn (Bit 3) */ -#define NVIC_ICPR_FTDF_GEN_IRQn_Msk (0x8UL) /*!< NVIC ICPR: FTDF_GEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_RFCAL_IRQn_Pos (4UL) /*!< NVIC ICPR: RFCAL_IRQn (Bit 4) */ -#define NVIC_ICPR_RFCAL_IRQn_Msk (0x10UL) /*!< NVIC ICPR: RFCAL_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_COEX_IRQn_Pos (5UL) /*!< NVIC ICPR: COEX_IRQn (Bit 5) */ -#define NVIC_ICPR_COEX_IRQn_Msk (0x20UL) /*!< NVIC ICPR: COEX_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_CRYPTO_IRQn_Pos (6UL) /*!< NVIC ICPR: CRYPTO_IRQn (Bit 6) */ -#define NVIC_ICPR_CRYPTO_IRQn_Msk (0x40UL) /*!< NVIC ICPR: CRYPTO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_MRM_IRQn_Pos (7UL) /*!< NVIC ICPR: MRM_IRQn (Bit 7) */ -#define NVIC_ICPR_MRM_IRQn_Msk (0x80UL) /*!< NVIC ICPR: MRM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_UART_IRQn_Pos (8UL) /*!< NVIC ICPR: UART_IRQn (Bit 8) */ -#define NVIC_ICPR_UART_IRQn_Msk (0x100UL) /*!< NVIC ICPR: UART_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_UART2_IRQn_Pos (9UL) /*!< NVIC ICPR: UART2_IRQn (Bit 9) */ -#define NVIC_ICPR_UART2_IRQn_Msk (0x200UL) /*!< NVIC ICPR: UART2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_I2C_IRQn_Pos (10UL) /*!< NVIC ICPR: I2C_IRQn (Bit 10) */ -#define NVIC_ICPR_I2C_IRQn_Msk (0x400UL) /*!< NVIC ICPR: I2C_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_I2C2_IRQn_Pos (11UL) /*!< NVIC ICPR: I2C2_IRQn (Bit 11) */ -#define NVIC_ICPR_I2C2_IRQn_Msk (0x800UL) /*!< NVIC ICPR: I2C2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_SPI_IRQn_Pos (12UL) /*!< NVIC ICPR: SPI_IRQn (Bit 12) */ -#define NVIC_ICPR_SPI_IRQn_Msk (0x1000UL) /*!< NVIC ICPR: SPI_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_SPI2_IRQn_Pos (13UL) /*!< NVIC ICPR: SPI2_IRQn (Bit 13) */ -#define NVIC_ICPR_SPI2_IRQn_Msk (0x2000UL) /*!< NVIC ICPR: SPI2_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_ADC_IRQn_Pos (14UL) /*!< NVIC ICPR: ADC_IRQn (Bit 14) */ -#define NVIC_ICPR_ADC_IRQn_Msk (0x4000UL) /*!< NVIC ICPR: ADC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_KEYBRD_IRQn_Pos (15UL) /*!< NVIC ICPR: KEYBRD_IRQn (Bit 15) */ -#define NVIC_ICPR_KEYBRD_IRQn_Msk (0x8000UL) /*!< NVIC ICPR: KEYBRD_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_IRGEN_IRQn_Pos (16UL) /*!< NVIC ICPR: IRGEN_IRQn (Bit 16) */ -#define NVIC_ICPR_IRGEN_IRQn_Msk (0x10000UL) /*!< NVIC ICPR: IRGEN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_WKUP_GPIO_IRQn_Pos (17UL) /*!< NVIC ICPR: WKUP_GPIO_IRQn (Bit 17) */ -#define NVIC_ICPR_WKUP_GPIO_IRQn_Msk (0x20000UL) /*!< NVIC ICPR: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_SWTIM0_IRQn_Pos (18UL) /*!< NVIC ICPR: SWTIM0_IRQn (Bit 18) */ -#define NVIC_ICPR_SWTIM0_IRQn_Msk (0x40000UL) /*!< NVIC ICPR: SWTIM0_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_SWTIM1_IRQn_Pos (19UL) /*!< NVIC ICPR: SWTIM1_IRQn (Bit 19) */ -#define NVIC_ICPR_SWTIM1_IRQn_Msk (0x80000UL) /*!< NVIC ICPR: SWTIM1_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_QUADEC_IRQn_Pos (20UL) /*!< NVIC ICPR: QUADEC_IRQn (Bit 20) */ -#define NVIC_ICPR_QUADEC_IRQn_Msk (0x100000UL) /*!< NVIC ICPR: QUADEC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_USB_IRQn_Pos (21UL) /*!< NVIC ICPR: USB_IRQn (Bit 21) */ -#define NVIC_ICPR_USB_IRQn_Msk (0x200000UL) /*!< NVIC ICPR: USB_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_PCM_IRQn_Pos (22UL) /*!< NVIC ICPR: PCM_IRQn (Bit 22) */ -#define NVIC_ICPR_PCM_IRQn_Msk (0x400000UL) /*!< NVIC ICPR: PCM_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_SRC_IN_IRQn_Pos (23UL) /*!< NVIC ICPR: SRC_IN_IRQn (Bit 23) */ -#define NVIC_ICPR_SRC_IN_IRQn_Msk (0x800000UL) /*!< NVIC ICPR: SRC_IN_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_SRC_OUT_IRQn_Pos (24UL) /*!< NVIC ICPR: SRC_OUT_IRQn (Bit 24) */ -#define NVIC_ICPR_SRC_OUT_IRQn_Msk (0x1000000UL) /*!< NVIC ICPR: SRC_OUT_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_VBUS_IRQn_Pos (25UL) /*!< NVIC ICPR: VBUS_IRQn (Bit 25) */ -#define NVIC_ICPR_VBUS_IRQn_Msk (0x2000000UL) /*!< NVIC ICPR: VBUS_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_DMA_IRQn_Pos (26UL) /*!< NVIC ICPR: DMA_IRQn (Bit 26) */ -#define NVIC_ICPR_DMA_IRQn_Msk (0x4000000UL) /*!< NVIC ICPR: DMA_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_RF_DIAG_IRQn_Pos (27UL) /*!< NVIC ICPR: RF_DIAG_IRQn (Bit 27) */ -#define NVIC_ICPR_RF_DIAG_IRQn_Msk (0x8000000UL) /*!< NVIC ICPR: RF_DIAG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_TRNG_IRQn_Pos (28UL) /*!< NVIC ICPR: TRNG_IRQn (Bit 28) */ -#define NVIC_ICPR_TRNG_IRQn_Msk (0x10000000UL) /*!< NVIC ICPR: TRNG_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_DCDC_IRQn_Pos (29UL) /*!< NVIC ICPR: DCDC_IRQn (Bit 29) */ -#define NVIC_ICPR_DCDC_IRQn_Msk (0x20000000UL) /*!< NVIC ICPR: DCDC_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_XTAL16RDY_IRQn_Pos (30UL) /*!< NVIC ICPR: XTAL16RDY_IRQn (Bit 30) */ -#define NVIC_ICPR_XTAL16RDY_IRQn_Msk (0x40000000UL) /*!< NVIC ICPR: XTAL16RDY_IRQn (Bitfield-Mask: 0x01) */ -#define NVIC_ICPR_Rsvd__irq__n_Pos (31UL) /*!< NVIC ICPR: Rsvd__irq__n (Bit 31) */ -#define NVIC_ICPR_Rsvd__irq__n_Msk (0x80000000UL) /*!< NVIC ICPR: Rsvd__irq__n (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- NVIC_IPR0 --------------------------------- */ -#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Pos (0UL) /*!< NVIC IPR0: BLE_WAKEUP_LP_IRQn_prio (Bit 0) */ -#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR0: BLE_WAKEUP_LP_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR0_BLE_GEN_IRQn_prio_Pos (8UL) /*!< NVIC IPR0: BLE_GEN_IRQn_prio (Bit 8) */ -#define NVIC_IPR0_BLE_GEN_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR0: BLE_GEN_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Pos (16UL) /*!< NVIC IPR0: FTDF_WAKEUP_IRQn_prio (Bit 16) */ -#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR0: FTDF_WAKEUP_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Pos (24UL) /*!< NVIC IPR0: FTDF_GEN_IRQn_prio (Bit 24) */ -#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Msk (0xff000000UL) /*!< NVIC IPR0: FTDF_GEN_IRQn_prio (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- NVIC_IPR1 --------------------------------- */ -#define NVIC_IPR1_RFCAL_IRQn_prio_Pos (0UL) /*!< NVIC IPR1: RFCAL_IRQn_prio (Bit 0) */ -#define NVIC_IPR1_RFCAL_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR1: RFCAL_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR1_COEX_IRQn_prio_Pos (8UL) /*!< NVIC IPR1: COEX_IRQn_prio (Bit 8) */ -#define NVIC_IPR1_COEX_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR1: COEX_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR1_CRYPTO_IRQn_prio_Pos (16UL) /*!< NVIC IPR1: CRYPTO_IRQn_prio (Bit 16) */ -#define NVIC_IPR1_CRYPTO_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR1: CRYPTO_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR1_MRM_IRQn_prio_Pos (24UL) /*!< NVIC IPR1: MRM_IRQn_prio (Bit 24) */ -#define NVIC_IPR1_MRM_IRQn_prio_Msk (0xff000000UL) /*!< NVIC IPR1: MRM_IRQn_prio (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- NVIC_IPR2 --------------------------------- */ -#define NVIC_IPR2_UART_IRQn_prio_Pos (0UL) /*!< NVIC IPR2: UART_IRQn_prio (Bit 0) */ -#define NVIC_IPR2_UART_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR2: UART_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR2_UART2_IRQn_prio_Pos (8UL) /*!< NVIC IPR2: UART2_IRQn_prio (Bit 8) */ -#define NVIC_IPR2_UART2_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR2: UART2_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR2_I2C_IRQn_prio_Pos (16UL) /*!< NVIC IPR2: I2C_IRQn_prio (Bit 16) */ -#define NVIC_IPR2_I2C_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR2: I2C_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR2_I2C2_IRQn_prio_Pos (24UL) /*!< NVIC IPR2: I2C2_IRQn_prio (Bit 24) */ -#define NVIC_IPR2_I2C2_IRQn_prio_Msk (0xff000000UL) /*!< NVIC IPR2: I2C2_IRQn_prio (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- NVIC_IPR3 --------------------------------- */ -#define NVIC_IPR3_SPI_IRQn_prio_Pos (0UL) /*!< NVIC IPR3: SPI_IRQn_prio (Bit 0) */ -#define NVIC_IPR3_SPI_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR3: SPI_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR3_SPI2_IRQn_prio_Pos (8UL) /*!< NVIC IPR3: SPI2_IRQn_prio (Bit 8) */ -#define NVIC_IPR3_SPI2_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR3: SPI2_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR3_ADC_IRQn_prio_Pos (16UL) /*!< NVIC IPR3: ADC_IRQn_prio (Bit 16) */ -#define NVIC_IPR3_ADC_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR3: ADC_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR3_KEYBRD_IRQn_prio_Pos (24UL) /*!< NVIC IPR3: KEYBRD_IRQn_prio (Bit 24) */ -#define NVIC_IPR3_KEYBRD_IRQn_prio_Msk (0xff000000UL) /*!< NVIC IPR3: KEYBRD_IRQn_prio (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- NVIC_IPR4 --------------------------------- */ -#define NVIC_IPR4_IRGEN_IRQn_prio_Pos (0UL) /*!< NVIC IPR4: IRGEN_IRQn_prio (Bit 0) */ -#define NVIC_IPR4_IRGEN_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR4: IRGEN_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Pos (8UL) /*!< NVIC IPR4: WKUP_GPIO_IRQn_prio (Bit 8) */ -#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR4: WKUP_GPIO_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR4_SWTIM0_IRQn_prio_Pos (16UL) /*!< NVIC IPR4: SWTIM0_IRQn_prio (Bit 16) */ -#define NVIC_IPR4_SWTIM0_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR4: SWTIM0_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR4_SWTIM1_IRQn_prio_Pos (24UL) /*!< NVIC IPR4: SWTIM1_IRQn_prio (Bit 24) */ -#define NVIC_IPR4_SWTIM1_IRQn_prio_Msk (0xff000000UL) /*!< NVIC IPR4: SWTIM1_IRQn_prio (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- NVIC_IPR5 --------------------------------- */ -#define NVIC_IPR5_QUADEC_IRQn_prio_Pos (0UL) /*!< NVIC IPR5: QUADEC_IRQn_prio (Bit 0) */ -#define NVIC_IPR5_QUADEC_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR5: QUADEC_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR5_USB_IRQn_prio_Pos (8UL) /*!< NVIC IPR5: USB_IRQn_prio (Bit 8) */ -#define NVIC_IPR5_USB_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR5: USB_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR5_PCM_IRQn_prio_Pos (16UL) /*!< NVIC IPR5: PCM_IRQn_prio (Bit 16) */ -#define NVIC_IPR5_PCM_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR5: PCM_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR5_SRC_IN_IRQn_prio_Pos (24UL) /*!< NVIC IPR5: SRC_IN_IRQn_prio (Bit 24) */ -#define NVIC_IPR5_SRC_IN_IRQn_prio_Msk (0xff000000UL) /*!< NVIC IPR5: SRC_IN_IRQn_prio (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- NVIC_IPR6 --------------------------------- */ -#define NVIC_IPR6_SRC_OUT_IRQn_prio_Pos (0UL) /*!< NVIC IPR6: SRC_OUT_IRQn_prio (Bit 0) */ -#define NVIC_IPR6_SRC_OUT_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR6: SRC_OUT_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR6_VBUS_IRQn_prio_Pos (8UL) /*!< NVIC IPR6: VBUS_IRQn_prio (Bit 8) */ -#define NVIC_IPR6_VBUS_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR6: VBUS_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR6_DMA_IRQn_prio_Pos (16UL) /*!< NVIC IPR6: DMA_IRQn_prio (Bit 16) */ -#define NVIC_IPR6_DMA_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR6: DMA_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR6_RF_DIAG_IRQn_prio_Pos (24UL) /*!< NVIC IPR6: RF_DIAG_IRQn_prio (Bit 24) */ -#define NVIC_IPR6_RF_DIAG_IRQn_prio_Msk (0xff000000UL) /*!< NVIC IPR6: RF_DIAG_IRQn_prio (Bitfield-Mask: 0xff) */ - -/* ---------------------------------- NVIC_IPR7 --------------------------------- */ -#define NVIC_IPR7_TRNG_IRQn_prio_Pos (0UL) /*!< NVIC IPR7: TRNG_IRQn_prio (Bit 0) */ -#define NVIC_IPR7_TRNG_IRQn_prio_Msk (0xffUL) /*!< NVIC IPR7: TRNG_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR7_DCDC_IRQn_prio_Pos (8UL) /*!< NVIC IPR7: DCDC_IRQn_prio (Bit 8) */ -#define NVIC_IPR7_DCDC_IRQn_prio_Msk (0xff00UL) /*!< NVIC IPR7: DCDC_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Pos (16UL) /*!< NVIC IPR7: XTAL16RDY_IRQn_prio (Bit 16) */ -#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Msk (0xff0000UL) /*!< NVIC IPR7: XTAL16RDY_IRQn_prio (Bitfield-Mask: 0xff) */ -#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Pos (24UL) /*!< NVIC IPR7: RESERVED31_IRQn_DONT_USE (Bit 24) */ -#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Msk (0xff000000UL) /*!< NVIC IPR7: RESERVED31_IRQn_DONT_USE (Bitfield-Mask: 0xff) */ - - - - - - -/* ================================================================================ */ -/* ================ struct 'AES_HASH' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- AES_HASH_CRYPTO_CTRL_REG -------------------------- */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG (Bit 0) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG (Bitfield-Mask: 0x03) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG_MD (Bit 2) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG_MD (Bitfield-Mask: 0x03) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_OUT_MD (Bit 4) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_OUT_MD (Bitfield-Mask: 0x01) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEY_SZ (Bit 5) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEY_SZ (Bitfield-Mask: 0x03) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ENCDEC (Bit 7) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_ENCDEC (Bitfield-Mask: 0x01) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_IRQ_EN (Bit 8) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_IRQ_EN (Bitfield-Mask: 0x01) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_SEL (Bit 9) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_SEL (Bitfield-Mask: 0x01) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_OUT_LEN (Bit 10) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0xfc00UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_OUT_LEN (Bitfield-Mask: 0x3f) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (16UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_MORE_IN (Bit 16) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x10000UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_MORE_IN (Bitfield-Mask: 0x01) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (17UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEXP (Bit 17) */ -#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x20000UL) /*!< AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEXP (Bitfield-Mask: 0x01) */ - -/* -------------------------- AES_HASH_CRYPTO_START_REG ------------------------- */ -#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL) /*!< AES_HASH CRYPTO_START_REG: CRYPTO_START (Bit 0) */ -#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL) /*!< AES_HASH CRYPTO_START_REG: CRYPTO_START (Bitfield-Mask: 0x01) */ - -/* ----------------------- AES_HASH_CRYPTO_FETCH_ADDR_REG ----------------------- */ -#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL) /*!< AES_HASH CRYPTO_FETCH_ADDR_REG: CRYPTO_FETCH_ADDR (Bit 0) */ -#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_FETCH_ADDR_REG: CRYPTO_FETCH_ADDR (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- AES_HASH_CRYPTO_LEN_REG -------------------------- */ -#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL) /*!< AES_HASH CRYPTO_LEN_REG: CRYPTO_LEN (Bit 0) */ -#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL) /*!< AES_HASH CRYPTO_LEN_REG: CRYPTO_LEN (Bitfield-Mask: 0xffffff) */ - -/* ------------------------ AES_HASH_CRYPTO_DEST_ADDR_REG ----------------------- */ -#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL) /*!< AES_HASH CRYPTO_DEST_ADDR_REG: CRYPTO_DEST_ADDR (Bit 0) */ -#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_DEST_ADDR_REG: CRYPTO_DEST_ADDR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- AES_HASH_CRYPTO_STATUS_REG ------------------------- */ -#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL) /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_INACTIVE (Bit 0) */ -#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL) /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_INACTIVE (Bitfield-Mask: 0x01) */ -#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL) /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_WAIT_FOR_IN (Bit 1) */ -#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL) /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_WAIT_FOR_IN (Bitfield-Mask: 0x01) */ -#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL) /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_IRQ_ST (Bit 2) */ -#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL) /*!< AES_HASH CRYPTO_STATUS_REG: CRYPTO_IRQ_ST (Bitfield-Mask: 0x01) */ - -/* ------------------------- AES_HASH_CRYPTO_CLRIRQ_REG ------------------------- */ -#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL) /*!< AES_HASH CRYPTO_CLRIRQ_REG: CRYPTO_CLRIRQ (Bit 0) */ -#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL) /*!< AES_HASH CRYPTO_CLRIRQ_REG: CRYPTO_CLRIRQ (Bitfield-Mask: 0x01) */ - -/* -------------------------- AES_HASH_CRYPTO_MREG0_REG ------------------------- */ -#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL) /*!< AES_HASH CRYPTO_MREG0_REG: CRYPTO_MREG0 (Bit 0) */ -#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_MREG0_REG: CRYPTO_MREG0 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- AES_HASH_CRYPTO_MREG1_REG ------------------------- */ -#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL) /*!< AES_HASH CRYPTO_MREG1_REG: CRYPTO_MREG1 (Bit 0) */ -#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_MREG1_REG: CRYPTO_MREG1 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- AES_HASH_CRYPTO_MREG2_REG ------------------------- */ -#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL) /*!< AES_HASH CRYPTO_MREG2_REG: CRYPTO_MREG2 (Bit 0) */ -#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_MREG2_REG: CRYPTO_MREG2 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- AES_HASH_CRYPTO_MREG3_REG ------------------------- */ -#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL) /*!< AES_HASH CRYPTO_MREG3_REG: CRYPTO_MREG3 (Bit 0) */ -#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_MREG3_REG: CRYPTO_MREG3 (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- AES_HASH_CRYPTO_KEYS_START ------------------------- */ -#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL) /*!< AES_HASH CRYPTO_KEYS_START: CRYPTO_KEY_X (Bit 0) */ -#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL) /*!< AES_HASH CRYPTO_KEYS_START: CRYPTO_KEY_X (Bitfield-Mask: 0xffffffff) */ - - -/* ================================================================================ */ -/* ================ struct 'ANAMISC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- ANAMISC_ANA_TEST_REG ---------------------------- */ -#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Pos (0UL) /*!< ANAMISC ANA_TEST_REG: TEST_STRUCTURE (Bit 0) */ -#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Msk (0xfUL) /*!< ANAMISC ANA_TEST_REG: TEST_STRUCTURE (Bitfield-Mask: 0x0f) */ -#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Pos (4UL) /*!< ANAMISC ANA_TEST_REG: ACORE_TESTBUS_EN (Bit 4) */ -#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Msk (0x10UL) /*!< ANAMISC ANA_TEST_REG: ACORE_TESTBUS_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- ANAMISC_CHARGER_CTRL1_REG ------------------------- */ -#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Pos (0UL) /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_LEVEL (Bit 0) */ -#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Msk (0x1fUL) /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_LEVEL (Bitfield-Mask: 0x1f) */ -#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Pos (5UL) /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_ON (Bit 5) */ -#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Msk (0x20UL) /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_ON (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Pos (6UL) /*!< ANAMISC CHARGER_CTRL1_REG: NTC_DISABLE (Bit 6) */ -#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Msk (0x40UL) /*!< ANAMISC CHARGER_CTRL1_REG: NTC_DISABLE (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Pos (7UL) /*!< ANAMISC CHARGER_CTRL1_REG: NTC_LOW_DISABLE (Bit 7) */ -#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Msk (0x80UL) /*!< ANAMISC CHARGER_CTRL1_REG: NTC_LOW_DISABLE (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Pos (8UL) /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_CUR (Bit 8) */ -#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Msk (0xf00UL) /*!< ANAMISC CHARGER_CTRL1_REG: CHARGE_CUR (Bitfield-Mask: 0x0f) */ -#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Pos (12UL) /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_SET (Bit 12) */ -#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Msk (0x3000UL) /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_SET (Bitfield-Mask: 0x03) */ -#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Pos (14UL) /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_DISABLE (Bit 14) */ -#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Msk (0x4000UL) /*!< ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_DISABLE (Bitfield-Mask: 0x01) */ - -/* -------------------------- ANAMISC_CHARGER_CTRL2_REG ------------------------- */ -#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Pos (0UL) /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_GAIN_TRIM (Bit 0) */ -#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Msk (0xfUL) /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_GAIN_TRIM (Bitfield-Mask: 0x0f) */ -#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Pos (4UL) /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_VFLOAT_ADJ (Bit 4) */ -#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Msk (0xf0UL) /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_VFLOAT_ADJ (Bitfield-Mask: 0x0f) */ -#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Pos (8UL) /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_OFFSET_TRIM (Bit 8) */ -#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Msk (0x1f00UL) /*!< ANAMISC CHARGER_CTRL2_REG: CURRENT_OFFSET_TRIM (Bitfield-Mask: 0x1f) */ -#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Pos (13UL) /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_TEST (Bit 13) */ -#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Msk (0xe000UL) /*!< ANAMISC CHARGER_CTRL2_REG: CHARGER_TEST (Bitfield-Mask: 0x07) */ - -/* ------------------------- ANAMISC_CHARGER_STATUS_REG ------------------------- */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos (0UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CC_MODE (Bit 0) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk (0x1UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CC_MODE (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos (1UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CV_MODE (Bit 1) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk (0x2UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_CV_MODE (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Pos (2UL) /*!< ANAMISC CHARGER_STATUS_REG: END_OF_CHARGE (Bit 2) */ -#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Msk (0x4UL) /*!< ANAMISC CHARGER_STATUS_REG: END_OF_CHARGE (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Pos (3UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_LOW (Bit 3) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Msk (0x8UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_LOW (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Pos (4UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_OK (Bit 4) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Msk (0x10UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_OK (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Pos (5UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_HIGH (Bit 5) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Msk (0x20UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_HIGH (Bitfield-Mask: 0x01) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Pos (6UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_TMODE_PROT (Bit 6) */ -#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Msk (0x40UL) /*!< ANAMISC CHARGER_STATUS_REG: CHARGER_TMODE_PROT (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ANAMISC_SOC_CTRL1_REG --------------------------- */ -#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Pos (0UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_ENABLE (Bit 0) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Msk (0x1UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_ENABLE (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Pos (1UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_CHARGE (Bit 1) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Msk (0x2UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_CHARGE (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Pos (2UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_AVG (Bit 2) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Msk (0x4UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_RESET_AVG (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Pos (3UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_MUTE (Bit 3) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Msk (0x8UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_MUTE (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Pos (4UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_GPIO (Bit 4) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Msk (0x10UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_GPIO (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Pos (5UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_SIGN (Bit 5) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Msk (0x20UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_SIGN (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Pos (6UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_IDAC (Bit 6) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Msk (0xc0UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_IDAC (Bitfield-Mask: 0x03) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Pos (8UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_LPF (Bit 8) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Msk (0x100UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_LPF (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Pos (9UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_CLK (Bit 9) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Msk (0xe00UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_CLK (Bitfield-Mask: 0x07) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Pos (12UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_BIAS (Bit 12) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Msk (0x3000UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_BIAS (Bitfield-Mask: 0x03) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Pos (14UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_CINT (Bit 14) */ -#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Msk (0xc000UL) /*!< ANAMISC SOC_CTRL1_REG: SOC_CINT (Bitfield-Mask: 0x03) */ - -/* ---------------------------- ANAMISC_SOC_CTRL2_REG --------------------------- */ -#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Pos (0UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_RVI (Bit 0) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Msk (0x3UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_RVI (Bitfield-Mask: 0x03) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Pos (2UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_SCYCLE (Bit 2) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Msk (0x1cUL) /*!< ANAMISC SOC_CTRL2_REG: SOC_SCYCLE (Bitfield-Mask: 0x07) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Pos (5UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_DCYCLE (Bit 5) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Msk (0x20UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_DCYCLE (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Pos (6UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_ICM (Bit 6) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Msk (0xc0UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_ICM (Bitfield-Mask: 0x03) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Pos (8UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_CHOP (Bit 8) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Msk (0x700UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_CHOP (Bitfield-Mask: 0x07) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Pos (11UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_CMIREG_ENABLE (Bit 11) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Msk (0x800UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_CMIREG_ENABLE (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Pos (12UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_MAW (Bit 12) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Msk (0x7000UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_MAW (Bitfield-Mask: 0x07) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Pos (15UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_DYNAVG (Bit 15) */ -#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Msk (0x8000UL) /*!< ANAMISC SOC_CTRL2_REG: SOC_DYNAVG (Bitfield-Mask: 0x01) */ - -/* ---------------------------- ANAMISC_SOC_CTRL3_REG --------------------------- */ -#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Pos (0UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_VSAT (Bit 0) */ -#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Msk (0x3UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_VSAT (Bitfield-Mask: 0x03) */ -#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Pos (2UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNTARG (Bit 2) */ -#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Msk (0x4UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNTARG (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Pos (3UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNHYS (Bit 3) */ -#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Msk (0x8UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_DYNHYS (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Pos (4UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_VCMI (Bit 4) */ -#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Msk (0x30UL) /*!< ANAMISC SOC_CTRL3_REG: SOC_VCMI (Bitfield-Mask: 0x03) */ - -/* --------------------------- ANAMISC_SOC_ADD2CH_REG --------------------------- */ -#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Pos (0UL) /*!< ANAMISC SOC_ADD2CH_REG: SOC_ADD2CH (Bit 0) */ -#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Msk (0xffffUL) /*!< ANAMISC SOC_ADD2CH_REG: SOC_ADD2CH (Bitfield-Mask: 0xffff) */ - -/* ------------------------ ANAMISC_SOC_CHARGE_CNTR1_REG ------------------------ */ -#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Pos (0UL) /*!< ANAMISC SOC_CHARGE_CNTR1_REG: CHARGE_CNT1 (Bit 0) */ -#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Msk (0xffffUL) /*!< ANAMISC SOC_CHARGE_CNTR1_REG: CHARGE_CNT1 (Bitfield-Mask: 0xffff) */ - -/* ------------------------ ANAMISC_SOC_CHARGE_CNTR2_REG ------------------------ */ -#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Pos (0UL) /*!< ANAMISC SOC_CHARGE_CNTR2_REG: CHARGE_CNT2 (Bit 0) */ -#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Msk (0xffffUL) /*!< ANAMISC SOC_CHARGE_CNTR2_REG: CHARGE_CNT2 (Bitfield-Mask: 0xffff) */ - -/* ------------------------ ANAMISC_SOC_CHARGE_CNTR3_REG ------------------------ */ -#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Pos (0UL) /*!< ANAMISC SOC_CHARGE_CNTR3_REG: CHARGE_CNT3 (Bit 0) */ -#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Msk (0xffUL) /*!< ANAMISC SOC_CHARGE_CNTR3_REG: CHARGE_CNT3 (Bitfield-Mask: 0xff) */ - -/* ------------------------- ANAMISC_SOC_CHARGE_AVG_REG ------------------------- */ -#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Pos (0UL) /*!< ANAMISC SOC_CHARGE_AVG_REG: CHARGE_AVG (Bit 0) */ -#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Msk (0xffffUL) /*!< ANAMISC SOC_CHARGE_AVG_REG: CHARGE_AVG (Bitfield-Mask: 0xffff) */ - -/* --------------------------- ANAMISC_SOC_STATUS_REG --------------------------- */ -#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Pos (0UL) /*!< ANAMISC SOC_STATUS_REG: SOC_INT_OVERLOAD (Bit 0) */ -#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Msk (0x1UL) /*!< ANAMISC SOC_STATUS_REG: SOC_INT_OVERLOAD (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Pos (1UL) /*!< ANAMISC SOC_STATUS_REG: SOC_INT_LOCKED (Bit 1) */ -#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Msk (0x2UL) /*!< ANAMISC SOC_STATUS_REG: SOC_INT_LOCKED (Bitfield-Mask: 0x01) */ - -/* --------------------------- ANAMISC_SOC_EXT_IN_REG --------------------------- */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Pos (0UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_VAL (Bit 0) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Msk (0x1ffUL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_VAL (Bitfield-Mask: 0x1ff) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Pos (9UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_SIGN (Bit 9) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Msk (0x200UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_IDAC_SIGN (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Pos (10UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_RDAC_DIS (Bit 10) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Msk (0x400UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_RDAC_DIS (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Pos (11UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_NR_SCYCLE (Bit 11) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Msk (0x3800UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_NR_SCYCLE (Bitfield-Mask: 0x07) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Pos (14UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_SCYCLE_EN (Bit 14) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Msk (0x4000UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_SCYCLE_EN (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Pos (15UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_IDAC_EN (Bit 15) */ -#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Msk (0x8000UL) /*!< ANAMISC SOC_EXT_IN_REG: SOC_EXT_IDAC_EN (Bitfield-Mask: 0x01) */ - -/* --------------------------- ANAMISC_SOC_EXT_OUT_REG -------------------------- */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Pos (0UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_HIGH_LIM (Bit 0) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Msk (0x1UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_HIGH_LIM (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Pos (1UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_LOWLIM_COMP (Bit 1) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Msk (0x2UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_LOWLIM_COMP (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Pos (2UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_POS_COMP (Bit 2) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Msk (0x4UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_POS_COMP (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Pos (3UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_RISING_COMP (Bit 3) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Msk (0x8UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_RISING_COMP (Bitfield-Mask: 0x01) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Pos (4UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_STATE (Bit 4) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Msk (0xf0UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_STATE (Bitfield-Mask: 0x0f) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Pos (8UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_CTRL_EVENT (Bit 8) */ -#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Msk (0x100UL) /*!< ANAMISC SOC_EXT_OUT_REG: SOC_CTRL_EVENT (Bitfield-Mask: 0x01) */ - -/* --------------------------- ANAMISC_CLK_REF_SEL_REG -------------------------- */ -#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL) /*!< ANAMISC CLK_REF_SEL_REG: REF_CLK_SEL (Bit 0) */ -#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x3UL) /*!< ANAMISC CLK_REF_SEL_REG: REF_CLK_SEL (Bitfield-Mask: 0x03) */ -#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Pos (2UL) /*!< ANAMISC CLK_REF_SEL_REG: REF_CAL_START (Bit 2) */ -#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x4UL) /*!< ANAMISC CLK_REF_SEL_REG: REF_CAL_START (Bitfield-Mask: 0x01) */ - -/* --------------------------- ANAMISC_CLK_REF_CNT_REG -------------------------- */ -#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL) /*!< ANAMISC CLK_REF_CNT_REG: REF_CNT_VAL (Bit 0) */ -#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL) /*!< ANAMISC CLK_REF_CNT_REG: REF_CNT_VAL (Bitfield-Mask: 0xffff) */ - -/* -------------------------- ANAMISC_CLK_REF_VAL_L_REG ------------------------- */ -#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Pos (0UL) /*!< ANAMISC CLK_REF_VAL_L_REG: XTAL_CNT_VAL (Bit 0) */ -#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Msk (0xffffUL) /*!< ANAMISC CLK_REF_VAL_L_REG: XTAL_CNT_VAL (Bitfield-Mask: 0xffff) */ - -/* -------------------------- ANAMISC_CLK_REF_VAL_H_REG ------------------------- */ -#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Pos (0UL) /*!< ANAMISC CLK_REF_VAL_H_REG: XTAL_CNT_VAL (Bit 0) */ -#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Msk (0xffffUL) /*!< ANAMISC CLK_REF_VAL_H_REG: XTAL_CNT_VAL (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'APU' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------ APU_SRC1_CTRL_REG ----------------------------- */ -#define APU_SRC1_CTRL_REG_SRC_EN_Pos (0UL) /*!< APU SRC1_CTRL_REG: SRC_EN (Bit 0) */ -#define APU_SRC1_CTRL_REG_SRC_EN_Msk (0x1UL) /*!< APU SRC1_CTRL_REG: SRC_EN (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos (1UL) /*!< APU SRC1_CTRL_REG: SRC_IN_AMODE (Bit 1) */ -#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL) /*!< APU SRC1_CTRL_REG: SRC_IN_AMODE (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL) /*!< APU SRC1_CTRL_REG: SRC_IN_CAL_BYPASS (Bit 2) */ -#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL) /*!< APU SRC1_CTRL_REG: SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_IN_DS_Pos (4UL) /*!< APU SRC1_CTRL_REG: SRC_IN_DS (Bit 4) */ -#define APU_SRC1_CTRL_REG_SRC_IN_DS_Msk (0x30UL) /*!< APU SRC1_CTRL_REG: SRC_IN_DS (Bitfield-Mask: 0x03) */ -#define APU_SRC1_CTRL_REG_SRC_IN_OK_Pos (6UL) /*!< APU SRC1_CTRL_REG: SRC_IN_OK (Bit 6) */ -#define APU_SRC1_CTRL_REG_SRC_IN_OK_Msk (0x40UL) /*!< APU SRC1_CTRL_REG: SRC_IN_OK (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL) /*!< APU SRC1_CTRL_REG: SRC_DITHER_DISABLE (Bit 7) */ -#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL) /*!< APU SRC1_CTRL_REG: SRC_DITHER_DISABLE (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos (13UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_AMODE (Bit 13) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_AMODE (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_CAL_BYPASS (Bit 14) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_US_Pos (16UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_US (Bit 16) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk (0x30000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_US (Bitfield-Mask: 0x03) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos (18UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_OK (Bit 18) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_OK (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos (19UL) /*!< APU SRC1_CTRL_REG: SRC_RESYNC (Bit 19) */ -#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk (0x80000UL) /*!< APU SRC1_CTRL_REG: SRC_RESYNC (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL) /*!< APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bit 20) */ -#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL) /*!< APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL) /*!< APU SRC1_CTRL_REG: SRC_IN_UNFLOW (Bit 21) */ -#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL) /*!< APU SRC1_CTRL_REG: SRC_IN_UNFLOW (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_OVFLOW (Bit 22) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_OVFLOW (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_UNFLOW (Bit 23) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_UNFLOW (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL) /*!< APU SRC1_CTRL_REG: SRC_IN_FLOWCLR (Bit 24) */ -#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL) /*!< APU SRC1_CTRL_REG: SRC_IN_FLOWCLR (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bit 25) */ -#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01) */ -#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bit 26) */ -#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bitfield-Mask: 0x03) */ -#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_MODE (Bit 28) */ -#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_MODE (Bitfield-Mask: 0x03) */ -#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bit 30) */ -#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bitfield-Mask: 0x03) */ - -/* ----------------------------- APU_SRC1_IN_FS_REG ----------------------------- */ -#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos (0UL) /*!< APU SRC1_IN_FS_REG: SRC_IN_FS (Bit 0) */ -#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL) /*!< APU SRC1_IN_FS_REG: SRC_IN_FS (Bitfield-Mask: 0xffffff) */ - -/* ----------------------------- APU_SRC1_OUT_FS_REG ---------------------------- */ -#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos (0UL) /*!< APU SRC1_OUT_FS_REG: SRC_OUT_FS (Bit 0) */ -#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL) /*!< APU SRC1_OUT_FS_REG: SRC_OUT_FS (Bitfield-Mask: 0xffffff) */ - -/* ------------------------------ APU_SRC1_IN1_REG ------------------------------ */ -#define APU_SRC1_IN1_REG_SRC_IN_Pos (8UL) /*!< APU SRC1_IN1_REG: SRC_IN (Bit 8) */ -#define APU_SRC1_IN1_REG_SRC_IN_Msk (0xffffff00UL) /*!< APU SRC1_IN1_REG: SRC_IN (Bitfield-Mask: 0xffffff) */ - -/* ------------------------------ APU_SRC1_IN2_REG ------------------------------ */ -#define APU_SRC1_IN2_REG_SRC_IN_Pos (8UL) /*!< APU SRC1_IN2_REG: SRC_IN (Bit 8) */ -#define APU_SRC1_IN2_REG_SRC_IN_Msk (0xffffff00UL) /*!< APU SRC1_IN2_REG: SRC_IN (Bitfield-Mask: 0xffffff) */ - -/* ------------------------------ APU_SRC1_OUT1_REG ----------------------------- */ -#define APU_SRC1_OUT1_REG_SRC_OUT_Pos (8UL) /*!< APU SRC1_OUT1_REG: SRC_OUT (Bit 8) */ -#define APU_SRC1_OUT1_REG_SRC_OUT_Msk (0xffffff00UL) /*!< APU SRC1_OUT1_REG: SRC_OUT (Bitfield-Mask: 0xffffff) */ - -/* ------------------------------ APU_SRC1_OUT2_REG ----------------------------- */ -#define APU_SRC1_OUT2_REG_SRC_OUT_Pos (8UL) /*!< APU SRC1_OUT2_REG: SRC_OUT (Bit 8) */ -#define APU_SRC1_OUT2_REG_SRC_OUT_Msk (0xffffff00UL) /*!< APU SRC1_OUT2_REG: SRC_OUT (Bitfield-Mask: 0xffffff) */ - -/* ------------------------------- APU_APU_MUX_REG ------------------------------ */ -#define APU_APU_MUX_REG_SRC1_MUX_IN_Pos (0UL) /*!< APU APU_MUX_REG: SRC1_MUX_IN (Bit 0) */ -#define APU_APU_MUX_REG_SRC1_MUX_IN_Msk (0x7UL) /*!< APU APU_MUX_REG: SRC1_MUX_IN (Bitfield-Mask: 0x07) */ -#define APU_APU_MUX_REG_PCM1_MUX_IN_Pos (3UL) /*!< APU APU_MUX_REG: PCM1_MUX_IN (Bit 3) */ -#define APU_APU_MUX_REG_PCM1_MUX_IN_Msk (0x38UL) /*!< APU APU_MUX_REG: PCM1_MUX_IN (Bitfield-Mask: 0x07) */ -#define APU_APU_MUX_REG_PDM1_MUX_IN_Pos (6UL) /*!< APU APU_MUX_REG: PDM1_MUX_IN (Bit 6) */ -#define APU_APU_MUX_REG_PDM1_MUX_IN_Msk (0x40UL) /*!< APU APU_MUX_REG: PDM1_MUX_IN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- APU_COEF10_SET1_REG ---------------------------- */ -#define APU_COEF10_SET1_REG_SRC_COEF0_Pos (0UL) /*!< APU COEF10_SET1_REG: SRC_COEF0 (Bit 0) */ -#define APU_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL) /*!< APU COEF10_SET1_REG: SRC_COEF0 (Bitfield-Mask: 0xffff) */ -#define APU_COEF10_SET1_REG_SRC_COEF1_Pos (16UL) /*!< APU COEF10_SET1_REG: SRC_COEF1 (Bit 16) */ -#define APU_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL) /*!< APU COEF10_SET1_REG: SRC_COEF1 (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- APU_COEF32_SET1_REG ---------------------------- */ -#define APU_COEF32_SET1_REG_SRC_COEF2_Pos (0UL) /*!< APU COEF32_SET1_REG: SRC_COEF2 (Bit 0) */ -#define APU_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL) /*!< APU COEF32_SET1_REG: SRC_COEF2 (Bitfield-Mask: 0xffff) */ -#define APU_COEF32_SET1_REG_SRC_COEF3_Pos (16UL) /*!< APU COEF32_SET1_REG: SRC_COEF3 (Bit 16) */ -#define APU_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL) /*!< APU COEF32_SET1_REG: SRC_COEF3 (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- APU_COEF54_SET1_REG ---------------------------- */ -#define APU_COEF54_SET1_REG_SRC_COEF4_Pos (0UL) /*!< APU COEF54_SET1_REG: SRC_COEF4 (Bit 0) */ -#define APU_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL) /*!< APU COEF54_SET1_REG: SRC_COEF4 (Bitfield-Mask: 0xffff) */ -#define APU_COEF54_SET1_REG_SRC_COEF5_Pos (16UL) /*!< APU COEF54_SET1_REG: SRC_COEF5 (Bit 16) */ -#define APU_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL) /*!< APU COEF54_SET1_REG: SRC_COEF5 (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- APU_COEF76_SET1_REG ---------------------------- */ -#define APU_COEF76_SET1_REG_SRC_COEF6_Pos (0UL) /*!< APU COEF76_SET1_REG: SRC_COEF6 (Bit 0) */ -#define APU_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL) /*!< APU COEF76_SET1_REG: SRC_COEF6 (Bitfield-Mask: 0xffff) */ -#define APU_COEF76_SET1_REG_SRC_COEF7_Pos (16UL) /*!< APU COEF76_SET1_REG: SRC_COEF7 (Bit 16) */ -#define APU_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL) /*!< APU COEF76_SET1_REG: SRC_COEF7 (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- APU_COEF98_SET1_REG ---------------------------- */ -#define APU_COEF98_SET1_REG_SRC_COEF8_Pos (0UL) /*!< APU COEF98_SET1_REG: SRC_COEF8 (Bit 0) */ -#define APU_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL) /*!< APU COEF98_SET1_REG: SRC_COEF8 (Bitfield-Mask: 0xffff) */ -#define APU_COEF98_SET1_REG_SRC_COEF9_Pos (16UL) /*!< APU COEF98_SET1_REG: SRC_COEF9 (Bit 16) */ -#define APU_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL) /*!< APU COEF98_SET1_REG: SRC_COEF9 (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- APU_COEF0A_SET1_REG ---------------------------- */ -#define APU_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL) /*!< APU COEF0A_SET1_REG: SRC_COEF10 (Bit 0) */ -#define APU_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL) /*!< APU COEF0A_SET1_REG: SRC_COEF10 (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ APU_PCM1_CTRL_REG ----------------------------- */ -#define APU_PCM1_CTRL_REG_PCM_EN_Pos (0UL) /*!< APU PCM1_CTRL_REG: PCM_EN (Bit 0) */ -#define APU_PCM1_CTRL_REG_PCM_EN_Msk (0x1UL) /*!< APU PCM1_CTRL_REG: PCM_EN (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_MASTER_Pos (1UL) /*!< APU PCM1_CTRL_REG: PCM_MASTER (Bit 1) */ -#define APU_PCM1_CTRL_REG_PCM_MASTER_Msk (0x2UL) /*!< APU PCM1_CTRL_REG: PCM_MASTER (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos (2UL) /*!< APU PCM1_CTRL_REG: PCM_FSCLEN (Bit 2) */ -#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk (0x3cUL) /*!< APU PCM1_CTRL_REG: PCM_FSCLEN (Bitfield-Mask: 0x0f) */ -#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos (6UL) /*!< APU PCM1_CTRL_REG: PCM_FSCDEL (Bit 6) */ -#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk (0x40UL) /*!< APU PCM1_CTRL_REG: PCM_FSCDEL (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_PPOD_Pos (7UL) /*!< APU PCM1_CTRL_REG: PCM_PPOD (Bit 7) */ -#define APU_PCM1_CTRL_REG_PCM_PPOD_Msk (0x80UL) /*!< APU PCM1_CTRL_REG: PCM_PPOD (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_CLKINV_Pos (8UL) /*!< APU PCM1_CTRL_REG: PCM_CLKINV (Bit 8) */ -#define APU_PCM1_CTRL_REG_PCM_CLKINV_Msk (0x100UL) /*!< APU PCM1_CTRL_REG: PCM_CLKINV (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_FSCINV_Pos (9UL) /*!< APU PCM1_CTRL_REG: PCM_FSCINV (Bit 9) */ -#define APU_PCM1_CTRL_REG_PCM_FSCINV_Msk (0x200UL) /*!< APU PCM1_CTRL_REG: PCM_FSCINV (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos (10UL) /*!< APU PCM1_CTRL_REG: PCM_CLK_BIT (Bit 10) */ -#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk (0x400UL) /*!< APU PCM1_CTRL_REG: PCM_CLK_BIT (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos (11UL) /*!< APU PCM1_CTRL_REG: PCM_CH_DEL (Bit 11) */ -#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk (0xf800UL) /*!< APU PCM1_CTRL_REG: PCM_CH_DEL (Bitfield-Mask: 0x1f) */ -#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos (16UL) /*!< APU PCM1_CTRL_REG: PCM_FSC_EDGE (Bit 16) */ -#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk (0x10000UL) /*!< APU PCM1_CTRL_REG: PCM_FSC_EDGE (Bitfield-Mask: 0x01) */ -#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos (20UL) /*!< APU PCM1_CTRL_REG: PCM_FSC_DIV (Bit 20) */ -#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk (0xfff00000UL) /*!< APU PCM1_CTRL_REG: PCM_FSC_DIV (Bitfield-Mask: 0xfff) */ - -/* ------------------------------ APU_PCM1_IN1_REG ------------------------------ */ -#define APU_PCM1_IN1_REG_PCM_IN_Pos (0UL) /*!< APU PCM1_IN1_REG: PCM_IN (Bit 0) */ -#define APU_PCM1_IN1_REG_PCM_IN_Msk (0xffffffffUL) /*!< APU PCM1_IN1_REG: PCM_IN (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ APU_PCM1_IN2_REG ------------------------------ */ -#define APU_PCM1_IN2_REG_PCM_IN_Pos (0UL) /*!< APU PCM1_IN2_REG: PCM_IN (Bit 0) */ -#define APU_PCM1_IN2_REG_PCM_IN_Msk (0xffffffffUL) /*!< APU PCM1_IN2_REG: PCM_IN (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ APU_PCM1_OUT1_REG ----------------------------- */ -#define APU_PCM1_OUT1_REG_PCM_OUT_Pos (0UL) /*!< APU PCM1_OUT1_REG: PCM_OUT (Bit 0) */ -#define APU_PCM1_OUT1_REG_PCM_OUT_Msk (0xffffffffUL) /*!< APU PCM1_OUT1_REG: PCM_OUT (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------------ APU_PCM1_OUT2_REG ----------------------------- */ -#define APU_PCM1_OUT2_REG_PCM_OUT_Pos (0UL) /*!< APU PCM1_OUT2_REG: PCM_OUT (Bit 0) */ -#define APU_PCM1_OUT2_REG_PCM_OUT_Msk (0xffffffffUL) /*!< APU PCM1_OUT2_REG: PCM_OUT (Bitfield-Mask: 0xffffffff) */ - - -/* ================================================================================ */ -/* ================ struct 'BLE' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- BLE_BLE_RWBLECNTL_REG --------------------------- */ -#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Pos (0UL) /*!< BLE BLE_RWBLECNTL_REG: SYNCERR (Bit 0) */ -#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Msk (0x7UL) /*!< BLE BLE_RWBLECNTL_REG: SYNCERR (Bitfield-Mask: 0x07) */ -#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Pos (4UL) /*!< BLE BLE_RWBLECNTL_REG: RXWINSZDEF (Bit 4) */ -#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Msk (0xf0UL) /*!< BLE BLE_RWBLECNTL_REG: RXWINSZDEF (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Pos (8UL) /*!< BLE BLE_RWBLECNTL_REG: RWBLE_EN (Bit 8) */ -#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Msk (0x100UL) /*!< BLE BLE_RWBLECNTL_REG: RWBLE_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Pos (9UL) /*!< BLE BLE_RWBLECNTL_REG: ADVERTFILT_EN (Bit 9) */ -#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Msk (0x200UL) /*!< BLE BLE_RWBLECNTL_REG: ADVERTFILT_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Pos (12UL) /*!< BLE BLE_RWBLECNTL_REG: CORR_MODE (Bit 12) */ -#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Msk (0x3000UL) /*!< BLE BLE_RWBLECNTL_REG: CORR_MODE (Bitfield-Mask: 0x03) */ -#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Pos (16UL) /*!< BLE BLE_RWBLECNTL_REG: HOP_REMAP_DSB (Bit 16) */ -#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Msk (0x10000UL) /*!< BLE BLE_RWBLECNTL_REG: HOP_REMAP_DSB (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Pos (17UL) /*!< BLE BLE_RWBLECNTL_REG: CRC_DSB (Bit 17) */ -#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Msk (0x20000UL) /*!< BLE BLE_RWBLECNTL_REG: CRC_DSB (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Pos (18UL) /*!< BLE BLE_RWBLECNTL_REG: WHIT_DSB (Bit 18) */ -#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Msk (0x40000UL) /*!< BLE BLE_RWBLECNTL_REG: WHIT_DSB (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Pos (19UL) /*!< BLE BLE_RWBLECNTL_REG: CRYPT_DSB (Bit 19) */ -#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Msk (0x80000UL) /*!< BLE BLE_RWBLECNTL_REG: CRYPT_DSB (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Pos (20UL) /*!< BLE BLE_RWBLECNTL_REG: NESN_DSB (Bit 20) */ -#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Msk (0x100000UL) /*!< BLE BLE_RWBLECNTL_REG: NESN_DSB (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Pos (21UL) /*!< BLE BLE_RWBLECNTL_REG: SN_DSB (Bit 21) */ -#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Msk (0x200000UL) /*!< BLE BLE_RWBLECNTL_REG: SN_DSB (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Pos (22UL) /*!< BLE BLE_RWBLECNTL_REG: MD_DSB (Bit 22) */ -#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Msk (0x400000UL) /*!< BLE BLE_RWBLECNTL_REG: MD_DSB (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Pos (24UL) /*!< BLE BLE_RWBLECNTL_REG: SCAN_ABORT (Bit 24) */ -#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Msk (0x1000000UL) /*!< BLE BLE_RWBLECNTL_REG: SCAN_ABORT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Pos (25UL) /*!< BLE BLE_RWBLECNTL_REG: ADVERT_ABORT (Bit 25) */ -#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Msk (0x2000000UL) /*!< BLE BLE_RWBLECNTL_REG: ADVERT_ABORT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Pos (26UL) /*!< BLE BLE_RWBLECNTL_REG: RFTEST_ABORT (Bit 26) */ -#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Msk (0x4000000UL) /*!< BLE BLE_RWBLECNTL_REG: RFTEST_ABORT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Pos (28UL) /*!< BLE BLE_RWBLECNTL_REG: SWINT_REQ (Bit 28) */ -#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Msk (0x10000000UL) /*!< BLE BLE_RWBLECNTL_REG: SWINT_REQ (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Pos (29UL) /*!< BLE BLE_RWBLECNTL_REG: REG_SOFT_RST (Bit 29) */ -#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Msk (0x20000000UL) /*!< BLE BLE_RWBLECNTL_REG: REG_SOFT_RST (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Pos (30UL) /*!< BLE BLE_RWBLECNTL_REG: MASTER_TGSOFT_RST (Bit 30) */ -#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Msk (0x40000000UL) /*!< BLE BLE_RWBLECNTL_REG: MASTER_TGSOFT_RST (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Pos (31UL) /*!< BLE BLE_RWBLECNTL_REG: MASTER_SOFT_RST (Bit 31) */ -#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Msk (0x80000000UL) /*!< BLE BLE_RWBLECNTL_REG: MASTER_SOFT_RST (Bitfield-Mask: 0x01) */ - -/* ----------------------------- BLE_BLE_VERSION_REG ---------------------------- */ -#define BLE_BLE_VERSION_REG_BUILD_Pos (0UL) /*!< BLE BLE_VERSION_REG: BUILD (Bit 0) */ -#define BLE_BLE_VERSION_REG_BUILD_Msk (0xffUL) /*!< BLE BLE_VERSION_REG: BUILD (Bitfield-Mask: 0xff) */ -#define BLE_BLE_VERSION_REG_UPG_Pos (8UL) /*!< BLE BLE_VERSION_REG: UPG (Bit 8) */ -#define BLE_BLE_VERSION_REG_UPG_Msk (0xff00UL) /*!< BLE BLE_VERSION_REG: UPG (Bitfield-Mask: 0xff) */ -#define BLE_BLE_VERSION_REG_REL_Pos (16UL) /*!< BLE BLE_VERSION_REG: REL (Bit 16) */ -#define BLE_BLE_VERSION_REG_REL_Msk (0xff0000UL) /*!< BLE BLE_VERSION_REG: REL (Bitfield-Mask: 0xff) */ -#define BLE_BLE_VERSION_REG_TYP_Pos (24UL) /*!< BLE BLE_VERSION_REG: TYP (Bit 24) */ -#define BLE_BLE_VERSION_REG_TYP_Msk (0xff000000UL) /*!< BLE BLE_VERSION_REG: TYP (Bitfield-Mask: 0xff) */ - -/* ---------------------------- BLE_BLE_RWBLECONF_REG --------------------------- */ -#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Pos (0UL) /*!< BLE BLE_RWBLECONF_REG: BUSWIDTH (Bit 0) */ -#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Msk (0x1UL) /*!< BLE BLE_RWBLECONF_REG: BUSWIDTH (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECONF_REG_USECRYPT_Pos (1UL) /*!< BLE BLE_RWBLECONF_REG: USECRYPT (Bit 1) */ -#define BLE_BLE_RWBLECONF_REG_USECRYPT_Msk (0x2UL) /*!< BLE BLE_RWBLECONF_REG: USECRYPT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECONF_REG_USEDBG_Pos (2UL) /*!< BLE BLE_RWBLECONF_REG: USEDBG (Bit 2) */ -#define BLE_BLE_RWBLECONF_REG_USEDBG_Msk (0x4UL) /*!< BLE BLE_RWBLECONF_REG: USEDBG (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECONF_REG_COEX_Pos (3UL) /*!< BLE BLE_RWBLECONF_REG: COEX (Bit 3) */ -#define BLE_BLE_RWBLECONF_REG_COEX_Msk (0x8UL) /*!< BLE BLE_RWBLECONF_REG: COEX (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECONF_REG_INTMODE_Pos (4UL) /*!< BLE BLE_RWBLECONF_REG: INTMODE (Bit 4) */ -#define BLE_BLE_RWBLECONF_REG_INTMODE_Msk (0x10UL) /*!< BLE BLE_RWBLECONF_REG: INTMODE (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECONF_REG_DMMODE_Pos (5UL) /*!< BLE BLE_RWBLECONF_REG: DMMODE (Bit 5) */ -#define BLE_BLE_RWBLECONF_REG_DMMODE_Msk (0x20UL) /*!< BLE BLE_RWBLECONF_REG: DMMODE (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECONF_REG_DECIPHER_Pos (6UL) /*!< BLE BLE_RWBLECONF_REG: DECIPHER (Bit 6) */ -#define BLE_BLE_RWBLECONF_REG_DECIPHER_Msk (0x40UL) /*!< BLE BLE_RWBLECONF_REG: DECIPHER (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Pos (8UL) /*!< BLE BLE_RWBLECONF_REG: CLK_SEL (Bit 8) */ -#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Msk (0x3f00UL) /*!< BLE BLE_RWBLECONF_REG: CLK_SEL (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_RWBLECONF_REG_RFIF_Pos (16UL) /*!< BLE BLE_RWBLECONF_REG: RFIF (Bit 16) */ -#define BLE_BLE_RWBLECONF_REG_RFIF_Msk (0x7f0000UL) /*!< BLE BLE_RWBLECONF_REG: RFIF (Bitfield-Mask: 0x7f) */ -#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Pos (24UL) /*!< BLE BLE_RWBLECONF_REG: ADD_WIDTH (Bit 24) */ -#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Msk (0x3f000000UL) /*!< BLE BLE_RWBLECONF_REG: ADD_WIDTH (Bitfield-Mask: 0x3f) */ - -/* ----------------------------- BLE_BLE_INTCNTL_REG ---------------------------- */ -#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Pos (0UL) /*!< BLE BLE_INTCNTL_REG: CSCNTINTMSK (Bit 0) */ -#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Msk (0x1UL) /*!< BLE BLE_INTCNTL_REG: CSCNTINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_RXINTMSK_Pos (1UL) /*!< BLE BLE_INTCNTL_REG: RXINTMSK (Bit 1) */ -#define BLE_BLE_INTCNTL_REG_RXINTMSK_Msk (0x2UL) /*!< BLE BLE_INTCNTL_REG: RXINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Pos (2UL) /*!< BLE BLE_INTCNTL_REG: SLPINTMSK (Bit 2) */ -#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Msk (0x4UL) /*!< BLE BLE_INTCNTL_REG: SLPINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Pos (3UL) /*!< BLE BLE_INTCNTL_REG: EVENTINTMSK (Bit 3) */ -#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Msk (0x8UL) /*!< BLE BLE_INTCNTL_REG: EVENTINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Pos (4UL) /*!< BLE BLE_INTCNTL_REG: CRYPTINTMSK (Bit 4) */ -#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Msk (0x10UL) /*!< BLE BLE_INTCNTL_REG: CRYPTINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Pos (5UL) /*!< BLE BLE_INTCNTL_REG: ERRORINTMSK (Bit 5) */ -#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Msk (0x20UL) /*!< BLE BLE_INTCNTL_REG: ERRORINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Pos (6UL) /*!< BLE BLE_INTCNTL_REG: GROSSTGTIMINTMSK (Bit 6) */ -#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Msk (0x40UL) /*!< BLE BLE_INTCNTL_REG: GROSSTGTIMINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Pos (7UL) /*!< BLE BLE_INTCNTL_REG: FINETGTIMINTMSK (Bit 7) */ -#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Msk (0x80UL) /*!< BLE BLE_INTCNTL_REG: FINETGTIMINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Pos (8UL) /*!< BLE BLE_INTCNTL_REG: EVENTAPFAINTMSK (Bit 8) */ -#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Msk (0x100UL) /*!< BLE BLE_INTCNTL_REG: EVENTAPFAINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_SWINTMSK_Pos (9UL) /*!< BLE BLE_INTCNTL_REG: SWINTMSK (Bit 9) */ -#define BLE_BLE_INTCNTL_REG_SWINTMSK_Msk (0x200UL) /*!< BLE BLE_INTCNTL_REG: SWINTMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Pos (15UL) /*!< BLE BLE_INTCNTL_REG: CSCNTDEVMSK (Bit 15) */ -#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Msk (0x8000UL) /*!< BLE BLE_INTCNTL_REG: CSCNTDEVMSK (Bitfield-Mask: 0x01) */ - -/* ----------------------------- BLE_BLE_INTSTAT_REG ---------------------------- */ -#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Pos (0UL) /*!< BLE BLE_INTSTAT_REG: CSCNTINTSTAT (Bit 0) */ -#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Msk (0x1UL) /*!< BLE BLE_INTSTAT_REG: CSCNTINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Pos (1UL) /*!< BLE BLE_INTSTAT_REG: RXINTSTAT (Bit 1) */ -#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Msk (0x2UL) /*!< BLE BLE_INTSTAT_REG: RXINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Pos (2UL) /*!< BLE BLE_INTSTAT_REG: SLPINTSTAT (Bit 2) */ -#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Msk (0x4UL) /*!< BLE BLE_INTSTAT_REG: SLPINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Pos (3UL) /*!< BLE BLE_INTSTAT_REG: EVENTINTSTAT (Bit 3) */ -#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Msk (0x8UL) /*!< BLE BLE_INTSTAT_REG: EVENTINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Pos (4UL) /*!< BLE BLE_INTSTAT_REG: CRYPTINTSTAT (Bit 4) */ -#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Msk (0x10UL) /*!< BLE BLE_INTSTAT_REG: CRYPTINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Pos (5UL) /*!< BLE BLE_INTSTAT_REG: ERRORINTSTAT (Bit 5) */ -#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Msk (0x20UL) /*!< BLE BLE_INTSTAT_REG: ERRORINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Pos (6UL) /*!< BLE BLE_INTSTAT_REG: GROSSTGTIMINTSTAT (Bit 6) */ -#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Msk (0x40UL) /*!< BLE BLE_INTSTAT_REG: GROSSTGTIMINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Pos (7UL) /*!< BLE BLE_INTSTAT_REG: FINETGTIMINTSTAT (Bit 7) */ -#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Msk (0x80UL) /*!< BLE BLE_INTSTAT_REG: FINETGTIMINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Pos (8UL) /*!< BLE BLE_INTSTAT_REG: EVENTAPFAINTSTAT (Bit 8) */ -#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Msk (0x100UL) /*!< BLE BLE_INTSTAT_REG: EVENTAPFAINTSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Pos (9UL) /*!< BLE BLE_INTSTAT_REG: SWINTSTAT (Bit 9) */ -#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Msk (0x200UL) /*!< BLE BLE_INTSTAT_REG: SWINTSTAT (Bitfield-Mask: 0x01) */ - -/* --------------------------- BLE_BLE_INTRAWSTAT_REG --------------------------- */ -#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Pos (0UL) /*!< BLE BLE_INTRAWSTAT_REG: CSCNTINTRAWSTAT (Bit 0) */ -#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Msk (0x1UL) /*!< BLE BLE_INTRAWSTAT_REG: CSCNTINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Pos (1UL) /*!< BLE BLE_INTRAWSTAT_REG: RXINTRAWSTAT (Bit 1) */ -#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Msk (0x2UL) /*!< BLE BLE_INTRAWSTAT_REG: RXINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Pos (2UL) /*!< BLE BLE_INTRAWSTAT_REG: SLPINTRAWSTAT (Bit 2) */ -#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Msk (0x4UL) /*!< BLE BLE_INTRAWSTAT_REG: SLPINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Pos (3UL) /*!< BLE BLE_INTRAWSTAT_REG: EVENTINTRAWSTAT (Bit 3) */ -#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Msk (0x8UL) /*!< BLE BLE_INTRAWSTAT_REG: EVENTINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Pos (4UL) /*!< BLE BLE_INTRAWSTAT_REG: CRYPTINTRAWSTAT (Bit 4) */ -#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Msk (0x10UL) /*!< BLE BLE_INTRAWSTAT_REG: CRYPTINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Pos (5UL) /*!< BLE BLE_INTRAWSTAT_REG: ERRORINTRAWSTAT (Bit 5) */ -#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Msk (0x20UL) /*!< BLE BLE_INTRAWSTAT_REG: ERRORINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Pos (6UL) /*!< BLE BLE_INTRAWSTAT_REG: GROSSTGTIMINTRAWSTAT (Bit 6) */ -#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Msk (0x40UL) /*!< BLE BLE_INTRAWSTAT_REG: GROSSTGTIMINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Pos (7UL) /*!< BLE BLE_INTRAWSTAT_REG: FINETGTIMINTRAWSTAT (Bit 7) */ -#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Msk (0x80UL) /*!< BLE BLE_INTRAWSTAT_REG: FINETGTIMINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Pos (8UL) /*!< BLE BLE_INTRAWSTAT_REG: EVENTAPFAINTRAWSTAT (Bit 8) */ -#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Msk (0x100UL) /*!< BLE BLE_INTRAWSTAT_REG: EVENTAPFAINTRAWSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Pos (9UL) /*!< BLE BLE_INTRAWSTAT_REG: SWINTRAWSTAT (Bit 9) */ -#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Msk (0x200UL) /*!< BLE BLE_INTRAWSTAT_REG: SWINTRAWSTAT (Bitfield-Mask: 0x01) */ - -/* ----------------------------- BLE_BLE_INTACK_REG ----------------------------- */ -#define BLE_BLE_INTACK_REG_CSCNTINTACK_Pos (0UL) /*!< BLE BLE_INTACK_REG: CSCNTINTACK (Bit 0) */ -#define BLE_BLE_INTACK_REG_CSCNTINTACK_Msk (0x1UL) /*!< BLE BLE_INTACK_REG: CSCNTINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_RXINTACK_Pos (1UL) /*!< BLE BLE_INTACK_REG: RXINTACK (Bit 1) */ -#define BLE_BLE_INTACK_REG_RXINTACK_Msk (0x2UL) /*!< BLE BLE_INTACK_REG: RXINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_SLPINTACK_Pos (2UL) /*!< BLE BLE_INTACK_REG: SLPINTACK (Bit 2) */ -#define BLE_BLE_INTACK_REG_SLPINTACK_Msk (0x4UL) /*!< BLE BLE_INTACK_REG: SLPINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_EVENTINTACK_Pos (3UL) /*!< BLE BLE_INTACK_REG: EVENTINTACK (Bit 3) */ -#define BLE_BLE_INTACK_REG_EVENTINTACK_Msk (0x8UL) /*!< BLE BLE_INTACK_REG: EVENTINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_CRYPTINTACK_Pos (4UL) /*!< BLE BLE_INTACK_REG: CRYPTINTACK (Bit 4) */ -#define BLE_BLE_INTACK_REG_CRYPTINTACK_Msk (0x10UL) /*!< BLE BLE_INTACK_REG: CRYPTINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_ERRORINTACK_Pos (5UL) /*!< BLE BLE_INTACK_REG: ERRORINTACK (Bit 5) */ -#define BLE_BLE_INTACK_REG_ERRORINTACK_Msk (0x20UL) /*!< BLE BLE_INTACK_REG: ERRORINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Pos (6UL) /*!< BLE BLE_INTACK_REG: GROSSTGTIMINTACK (Bit 6) */ -#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Msk (0x40UL) /*!< BLE BLE_INTACK_REG: GROSSTGTIMINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Pos (7UL) /*!< BLE BLE_INTACK_REG: FINETGTIMINTACK (Bit 7) */ -#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Msk (0x80UL) /*!< BLE BLE_INTACK_REG: FINETGTIMINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Pos (8UL) /*!< BLE BLE_INTACK_REG: EVENTAPFAINTACK (Bit 8) */ -#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Msk (0x100UL) /*!< BLE BLE_INTACK_REG: EVENTAPFAINTACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_INTACK_REG_SWINTACK_Pos (9UL) /*!< BLE BLE_INTACK_REG: SWINTACK (Bit 9) */ -#define BLE_BLE_INTACK_REG_SWINTACK_Msk (0x200UL) /*!< BLE BLE_INTACK_REG: SWINTACK (Bitfield-Mask: 0x01) */ - -/* --------------------------- BLE_BLE_BASETIMECNT_REG -------------------------- */ -#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Pos (0UL) /*!< BLE BLE_BASETIMECNT_REG: BASETIMECNT (Bit 0) */ -#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Msk (0x7ffffffUL) /*!< BLE BLE_BASETIMECNT_REG: BASETIMECNT (Bitfield-Mask: 0x7ffffff) */ - -/* --------------------------- BLE_BLE_FINETIMECNT_REG -------------------------- */ -#define BLE_BLE_FINETIMECNT_REG_FINECNT_Pos (0UL) /*!< BLE BLE_FINETIMECNT_REG: FINECNT (Bit 0) */ -#define BLE_BLE_FINETIMECNT_REG_FINECNT_Msk (0x3ffUL) /*!< BLE BLE_FINETIMECNT_REG: FINECNT (Bitfield-Mask: 0x3ff) */ - -/* ----------------------------- BLE_BLE_BDADDRL_REG ---------------------------- */ -#define BLE_BLE_BDADDRL_REG_BDADDRL_Pos (0UL) /*!< BLE BLE_BDADDRL_REG: BDADDRL (Bit 0) */ -#define BLE_BLE_BDADDRL_REG_BDADDRL_Msk (0xffffffffUL) /*!< BLE BLE_BDADDRL_REG: BDADDRL (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- BLE_BLE_BDADDRU_REG ---------------------------- */ -#define BLE_BLE_BDADDRU_REG_BDADDRU_Pos (0UL) /*!< BLE BLE_BDADDRU_REG: BDADDRU (Bit 0) */ -#define BLE_BLE_BDADDRU_REG_BDADDRU_Msk (0xffffUL) /*!< BLE BLE_BDADDRU_REG: BDADDRU (Bitfield-Mask: 0xffff) */ -#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Pos (16UL) /*!< BLE BLE_BDADDRU_REG: PRIV_NPUB (Bit 16) */ -#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Msk (0x10000UL) /*!< BLE BLE_BDADDRU_REG: PRIV_NPUB (Bitfield-Mask: 0x01) */ - -/* ------------------------ BLE_BLE_CURRENTRXDESCPTR_REG ------------------------ */ -#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Pos (0UL) /*!< BLE BLE_CURRENTRXDESCPTR_REG: CURRENTRXDESCPTR (Bit 0) */ -#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Msk (0x7fffUL) /*!< BLE BLE_CURRENTRXDESCPTR_REG: CURRENTRXDESCPTR (Bitfield-Mask: 0x7fff) */ -#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Pos (16UL) /*!< BLE BLE_CURRENTRXDESCPTR_REG: ETPTR (Bit 16) */ -#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Msk (0xffff0000UL) /*!< BLE BLE_CURRENTRXDESCPTR_REG: ETPTR (Bitfield-Mask: 0xffff) */ - -/* --------------------------- BLE_BLE_DEEPSLCNTL_REG --------------------------- */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Pos (0UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_IRQ_EN (Bit 0) */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Msk (0x3UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_IRQ_EN (Bitfield-Mask: 0x03) */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Pos (2UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_ON (Bit 2) */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Msk (0x4UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_ON (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Pos (3UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_CORR_EN (Bit 3) */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Msk (0x8UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_CORR_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Pos (4UL) /*!< BLE BLE_DEEPSLCNTL_REG: SOFT_WAKEUP_REQ (Bit 4) */ -#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Msk (0x10UL) /*!< BLE BLE_DEEPSLCNTL_REG: SOFT_WAKEUP_REQ (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Pos (15UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_STAT (Bit 15) */ -#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Msk (0x8000UL) /*!< BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_STAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Pos (31UL) /*!< BLE BLE_DEEPSLCNTL_REG: EXTWKUPDSB (Bit 31) */ -#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Msk (0x80000000UL) /*!< BLE BLE_DEEPSLCNTL_REG: EXTWKUPDSB (Bitfield-Mask: 0x01) */ - -/* --------------------------- BLE_BLE_DEEPSLWKUP_REG --------------------------- */ -#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Pos (0UL) /*!< BLE BLE_DEEPSLWKUP_REG: DEEPSLTIME (Bit 0) */ -#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Msk (0xffffffffUL) /*!< BLE BLE_DEEPSLWKUP_REG: DEEPSLTIME (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- BLE_BLE_DEEPSLSTAT_REG --------------------------- */ -#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Pos (0UL) /*!< BLE BLE_DEEPSLSTAT_REG: DEEPSLDUR (Bit 0) */ -#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Msk (0xffffffffUL) /*!< BLE BLE_DEEPSLSTAT_REG: DEEPSLDUR (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- BLE_BLE_ENBPRESET_REG --------------------------- */ -#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Pos (0UL) /*!< BLE BLE_ENBPRESET_REG: TWIRQ_RESET (Bit 0) */ -#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Msk (0x3ffUL) /*!< BLE BLE_ENBPRESET_REG: TWIRQ_RESET (Bitfield-Mask: 0x3ff) */ -#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Pos (10UL) /*!< BLE BLE_ENBPRESET_REG: TWIRQ_SET (Bit 10) */ -#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Msk (0x1ffc00UL) /*!< BLE BLE_ENBPRESET_REG: TWIRQ_SET (Bitfield-Mask: 0x7ff) */ -#define BLE_BLE_ENBPRESET_REG_TWEXT_Pos (21UL) /*!< BLE BLE_ENBPRESET_REG: TWEXT (Bit 21) */ -#define BLE_BLE_ENBPRESET_REG_TWEXT_Msk (0xffe00000UL) /*!< BLE BLE_ENBPRESET_REG: TWEXT (Bitfield-Mask: 0x7ff) */ - -/* --------------------------- BLE_BLE_FINECNTCORR_REG -------------------------- */ -#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Pos (0UL) /*!< BLE BLE_FINECNTCORR_REG: FINECNTCORR (Bit 0) */ -#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Msk (0x3ffUL) /*!< BLE BLE_FINECNTCORR_REG: FINECNTCORR (Bitfield-Mask: 0x3ff) */ - -/* ------------------------- BLE_BLE_BASETIMECNTCORR_REG ------------------------ */ -#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Pos (0UL) /*!< BLE BLE_BASETIMECNTCORR_REG: BASETIMECNTCORR (Bit 0) */ -#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Msk (0x7ffffffUL) /*!< BLE BLE_BASETIMECNTCORR_REG: BASETIMECNTCORR (Bitfield-Mask: 0x7ffffff) */ - -/* ---------------------------- BLE_BLE_DIAGCNTL_REG ---------------------------- */ -#define BLE_BLE_DIAGCNTL_REG_DIAG0_Pos (0UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG0 (Bit 0) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG0_Msk (0x3fUL) /*!< BLE BLE_DIAGCNTL_REG: DIAG0 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Pos (7UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG0_EN (Bit 7) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Msk (0x80UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG0_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG1_Pos (8UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG1 (Bit 8) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG1_Msk (0x3f00UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG1 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Pos (15UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG1_EN (Bit 15) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Msk (0x8000UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG1_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG2_Pos (16UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG2 (Bit 16) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG2_Msk (0x3f0000UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG2 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Pos (23UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG2_EN (Bit 23) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Msk (0x800000UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG2_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG3_Pos (24UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG3 (Bit 24) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG3_Msk (0x3f000000UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG3 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Pos (31UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG3_EN (Bit 31) */ -#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Msk (0x80000000UL) /*!< BLE BLE_DIAGCNTL_REG: DIAG3_EN (Bitfield-Mask: 0x01) */ - -/* ---------------------------- BLE_BLE_DIAGSTAT_REG ---------------------------- */ -#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Pos (0UL) /*!< BLE BLE_DIAGSTAT_REG: DIAG0STAT (Bit 0) */ -#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Msk (0xffUL) /*!< BLE BLE_DIAGSTAT_REG: DIAG0STAT (Bitfield-Mask: 0xff) */ -#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Pos (8UL) /*!< BLE BLE_DIAGSTAT_REG: DIAG1STAT (Bit 8) */ -#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Msk (0xff00UL) /*!< BLE BLE_DIAGSTAT_REG: DIAG1STAT (Bitfield-Mask: 0xff) */ -#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Pos (16UL) /*!< BLE BLE_DIAGSTAT_REG: DIAG2STAT (Bit 16) */ -#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Msk (0xff0000UL) /*!< BLE BLE_DIAGSTAT_REG: DIAG2STAT (Bitfield-Mask: 0xff) */ -#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Pos (24UL) /*!< BLE BLE_DIAGSTAT_REG: DIAG3STAT (Bit 24) */ -#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Msk (0xff000000UL) /*!< BLE BLE_DIAGSTAT_REG: DIAG3STAT (Bitfield-Mask: 0xff) */ - -/* --------------------------- BLE_BLE_DEBUGADDMAX_REG -------------------------- */ -#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Pos (0UL) /*!< BLE BLE_DEBUGADDMAX_REG: EM_ADDMAX (Bit 0) */ -#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Msk (0xffffUL) /*!< BLE BLE_DEBUGADDMAX_REG: EM_ADDMAX (Bitfield-Mask: 0xffff) */ -#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Pos (16UL) /*!< BLE BLE_DEBUGADDMAX_REG: REG_ADDMAX (Bit 16) */ -#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Msk (0xffff0000UL) /*!< BLE BLE_DEBUGADDMAX_REG: REG_ADDMAX (Bitfield-Mask: 0xffff) */ - -/* --------------------------- BLE_BLE_DEBUGADDMIN_REG -------------------------- */ -#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Pos (0UL) /*!< BLE BLE_DEBUGADDMIN_REG: EM_ADDMIN (Bit 0) */ -#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Msk (0xffffUL) /*!< BLE BLE_DEBUGADDMIN_REG: EM_ADDMIN (Bitfield-Mask: 0xffff) */ -#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Pos (16UL) /*!< BLE BLE_DEBUGADDMIN_REG: REG_ADDMIN (Bit 16) */ -#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Msk (0xffff0000UL) /*!< BLE BLE_DEBUGADDMIN_REG: REG_ADDMIN (Bitfield-Mask: 0xffff) */ - -/* -------------------------- BLE_BLE_ERRORTYPESTAT_REG ------------------------- */ -#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Pos (0UL) /*!< BLE BLE_ERRORTYPESTAT_REG: TXCRYPT_ERROR (Bit 0) */ -#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Msk (0x1UL) /*!< BLE BLE_ERRORTYPESTAT_REG: TXCRYPT_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Pos (1UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RXCRYPT_ERROR (Bit 1) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Msk (0x2UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RXCRYPT_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Pos (2UL) /*!< BLE BLE_ERRORTYPESTAT_REG: PKTCNTL_EMACC_ERROR (Bit 2) */ -#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Msk (0x4UL) /*!< BLE BLE_ERRORTYPESTAT_REG: PKTCNTL_EMACC_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Pos (3UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RADIO_EMACC_ERROR (Bit 3) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Msk (0x8UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RADIO_EMACC_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Pos (4UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_EMACC_ERROR (Bit 4) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Msk (0x10UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_EMACC_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Pos (5UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_ENTRY_ERROR (Bit 5) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Msk (0x20UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_ENTRY_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Pos (6UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_APFM_ERROR (Bit 6) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Msk (0x40UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_APFM_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Pos (7UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_CNTL_APFM_ERROR (Bit 7) */ -#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Msk (0x80UL) /*!< BLE BLE_ERRORTYPESTAT_REG: EVT_CNTL_APFM_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Pos (8UL) /*!< BLE BLE_ERRORTYPESTAT_REG: WHITELIST_ERROR (Bit 8) */ -#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Msk (0x100UL) /*!< BLE BLE_ERRORTYPESTAT_REG: WHITELIST_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Pos (9UL) /*!< BLE BLE_ERRORTYPESTAT_REG: IFS_UNDERRUN (Bit 9) */ -#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Msk (0x200UL) /*!< BLE BLE_ERRORTYPESTAT_REG: IFS_UNDERRUN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Pos (10UL) /*!< BLE BLE_ERRORTYPESTAT_REG: ADV_UNDERRUN (Bit 10) */ -#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Msk (0x400UL) /*!< BLE BLE_ERRORTYPESTAT_REG: ADV_UNDERRUN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Pos (11UL) /*!< BLE BLE_ERRORTYPESTAT_REG: LLCHMAP_ERROR (Bit 11) */ -#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Msk (0x800UL) /*!< BLE BLE_ERRORTYPESTAT_REG: LLCHMAP_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Pos (12UL) /*!< BLE BLE_ERRORTYPESTAT_REG: CSFORMAT_ERROR (Bit 12) */ -#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Msk (0x1000UL) /*!< BLE BLE_ERRORTYPESTAT_REG: CSFORMAT_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Pos (13UL) /*!< BLE BLE_ERRORTYPESTAT_REG: TXDESC_EMPTY_ERROR (Bit 13) */ -#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Msk (0x2000UL) /*!< BLE BLE_ERRORTYPESTAT_REG: TXDESC_EMPTY_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Pos (14UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RXDESC_EMPTY_ERROR (Bit 14) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Msk (0x4000UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RXDESC_EMPTY_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Pos (15UL) /*!< BLE BLE_ERRORTYPESTAT_REG: TXDATA_PTR_ERROR (Bit 15) */ -#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Msk (0x8000UL) /*!< BLE BLE_ERRORTYPESTAT_REG: TXDATA_PTR_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Pos (16UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RXDATA_PTR_ERROR (Bit 16) */ -#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Msk (0x10000UL) /*!< BLE BLE_ERRORTYPESTAT_REG: RXDATA_PTR_ERROR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Pos (17UL) /*!< BLE BLE_ERRORTYPESTAT_REG: CONCEVTIRQ_ERROR (Bit 17) */ -#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Msk (0x20000UL) /*!< BLE BLE_ERRORTYPESTAT_REG: CONCEVTIRQ_ERROR (Bitfield-Mask: 0x01) */ - -/* --------------------------- BLE_BLE_SWPROFILING_REG -------------------------- */ -#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Pos (0UL) /*!< BLE BLE_SWPROFILING_REG: SWPROFVAL (Bit 0) */ -#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Msk (0xffffffffUL) /*!< BLE BLE_SWPROFILING_REG: SWPROFVAL (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- BLE_BLE_RADIOCNTL0_REG --------------------------- */ -#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Pos (2UL) /*!< BLE BLE_RADIOCNTL0_REG: field246rsv (Bit 2) */ -#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Msk (0x1cUL) /*!< BLE BLE_RADIOCNTL0_REG: field246rsv (Bitfield-Mask: 0x07) */ - -/* --------------------------- BLE_BLE_RADIOCNTL1_REG --------------------------- */ -#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Pos (16UL) /*!< BLE BLE_RADIOCNTL1_REG: XRFSEL (Bit 16) */ -#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Msk (0x1f0000UL) /*!< BLE BLE_RADIOCNTL1_REG: XRFSEL (Bitfield-Mask: 0x1f) */ - -/* -------------------------- BLE_BLE_RADIOPWRUPDN_REG -------------------------- */ -#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Pos (0UL) /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRUP (Bit 0) */ -#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Msk (0xffUL) /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRUP (Bitfield-Mask: 0xff) */ -#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Pos (8UL) /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRDN (Bit 8) */ -#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Msk (0xf00UL) /*!< BLE BLE_RADIOPWRUPDN_REG: TXPWRDN (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Pos (16UL) /*!< BLE BLE_RADIOPWRUPDN_REG: RXPWRUP (Bit 16) */ -#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Msk (0xff0000UL) /*!< BLE BLE_RADIOPWRUPDN_REG: RXPWRUP (Bitfield-Mask: 0xff) */ -#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Pos (24UL) /*!< BLE BLE_RADIOPWRUPDN_REG: RTRIP_DELAY (Bit 24) */ -#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Msk (0x7f000000UL) /*!< BLE BLE_RADIOPWRUPDN_REG: RTRIP_DELAY (Bitfield-Mask: 0x7f) */ - -/* ---------------------------- BLE_BLE_ADVCHMAP_REG ---------------------------- */ -#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Pos (0UL) /*!< BLE BLE_ADVCHMAP_REG: ADVCHMAP (Bit 0) */ -#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Msk (0x7UL) /*!< BLE BLE_ADVCHMAP_REG: ADVCHMAP (Bitfield-Mask: 0x07) */ - -/* ----------------------------- BLE_BLE_ADVTIM_REG ----------------------------- */ -#define BLE_BLE_ADVTIM_REG_ADVINT_Pos (0UL) /*!< BLE BLE_ADVTIM_REG: ADVINT (Bit 0) */ -#define BLE_BLE_ADVTIM_REG_ADVINT_Msk (0x3fffUL) /*!< BLE BLE_ADVTIM_REG: ADVINT (Bitfield-Mask: 0x3fff) */ - -/* --------------------------- BLE_BLE_ACTSCANSTAT_REG -------------------------- */ -#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Pos (0UL) /*!< BLE BLE_ACTSCANSTAT_REG: UPPERLIMIT (Bit 0) */ -#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Msk (0x1ffUL) /*!< BLE BLE_ACTSCANSTAT_REG: UPPERLIMIT (Bitfield-Mask: 0x1ff) */ -#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Pos (16UL) /*!< BLE BLE_ACTSCANSTAT_REG: BACKOFF (Bit 16) */ -#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Msk (0x1ff0000UL) /*!< BLE BLE_ACTSCANSTAT_REG: BACKOFF (Bitfield-Mask: 0x1ff) */ - -/* --------------------------- BLE_BLE_WLPUBADDPTR_REG -------------------------- */ -#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Pos (0UL) /*!< BLE BLE_WLPUBADDPTR_REG: WLPUBADDPTR (Bit 0) */ -#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Msk (0xffffUL) /*!< BLE BLE_WLPUBADDPTR_REG: WLPUBADDPTR (Bitfield-Mask: 0xffff) */ - -/* -------------------------- BLE_BLE_WLPRIVADDPTR_REG -------------------------- */ -#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Pos (0UL) /*!< BLE BLE_WLPRIVADDPTR_REG: WLPRIVADDPTR (Bit 0) */ -#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Msk (0xffffUL) /*!< BLE BLE_WLPRIVADDPTR_REG: WLPRIVADDPTR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- BLE_BLE_WLNBDEV_REG ---------------------------- */ -#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Pos (0UL) /*!< BLE BLE_WLNBDEV_REG: NBPUBDEV (Bit 0) */ -#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Msk (0xffUL) /*!< BLE BLE_WLNBDEV_REG: NBPUBDEV (Bitfield-Mask: 0xff) */ -#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Pos (8UL) /*!< BLE BLE_WLNBDEV_REG: NBPRIVDEV (Bit 8) */ -#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Msk (0xff00UL) /*!< BLE BLE_WLNBDEV_REG: NBPRIVDEV (Bitfield-Mask: 0xff) */ - -/* ----------------------------- BLE_BLE_AESCNTL_REG ---------------------------- */ -#define BLE_BLE_AESCNTL_REG_AES_START_Pos (0UL) /*!< BLE BLE_AESCNTL_REG: AES_START (Bit 0) */ -#define BLE_BLE_AESCNTL_REG_AES_START_Msk (0x1UL) /*!< BLE BLE_AESCNTL_REG: AES_START (Bitfield-Mask: 0x01) */ -#define BLE_BLE_AESCNTL_REG_AES_MODE_Pos (1UL) /*!< BLE BLE_AESCNTL_REG: AES_MODE (Bit 1) */ -#define BLE_BLE_AESCNTL_REG_AES_MODE_Msk (0x2UL) /*!< BLE BLE_AESCNTL_REG: AES_MODE (Bitfield-Mask: 0x01) */ - -/* --------------------------- BLE_BLE_AESKEY31_0_REG --------------------------- */ -#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Pos (0UL) /*!< BLE BLE_AESKEY31_0_REG: AESKEY31_0 (Bit 0) */ -#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Msk (0xffffffffUL) /*!< BLE BLE_AESKEY31_0_REG: AESKEY31_0 (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- BLE_BLE_AESKEY63_32_REG -------------------------- */ -#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Pos (0UL) /*!< BLE BLE_AESKEY63_32_REG: AESKEY63_32 (Bit 0) */ -#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Msk (0xffffffffUL) /*!< BLE BLE_AESKEY63_32_REG: AESKEY63_32 (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- BLE_BLE_AESKEY95_64_REG -------------------------- */ -#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Pos (0UL) /*!< BLE BLE_AESKEY95_64_REG: AESKEY95_64 (Bit 0) */ -#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Msk (0xffffffffUL) /*!< BLE BLE_AESKEY95_64_REG: AESKEY95_64 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- BLE_BLE_AESKEY127_96_REG -------------------------- */ -#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Pos (0UL) /*!< BLE BLE_AESKEY127_96_REG: AESKEY127_96 (Bit 0) */ -#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Msk (0xffffffffUL) /*!< BLE BLE_AESKEY127_96_REG: AESKEY127_96 (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- BLE_BLE_AESPTR_REG ----------------------------- */ -#define BLE_BLE_AESPTR_REG_AESPTR_Pos (0UL) /*!< BLE BLE_AESPTR_REG: AESPTR (Bit 0) */ -#define BLE_BLE_AESPTR_REG_AESPTR_Msk (0xffffUL) /*!< BLE BLE_AESPTR_REG: AESPTR (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- BLE_BLE_TXMICVAL_REG ---------------------------- */ -#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Pos (0UL) /*!< BLE BLE_TXMICVAL_REG: TXMICVAL (Bit 0) */ -#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Msk (0xffffffffUL) /*!< BLE BLE_TXMICVAL_REG: TXMICVAL (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- BLE_BLE_RXMICVAL_REG ---------------------------- */ -#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Pos (0UL) /*!< BLE BLE_RXMICVAL_REG: RXMICVAL (Bit 0) */ -#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Msk (0xffffffffUL) /*!< BLE BLE_RXMICVAL_REG: RXMICVAL (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- BLE_BLE_RFTESTCNTL_REG --------------------------- */ -#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Pos (0UL) /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTH (Bit 0) */ -#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Msk (0x1ffUL) /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTH (Bitfield-Mask: 0x1ff) */ -#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Pos (11UL) /*!< BLE BLE_RFTESTCNTL_REG: TXPKTCNTEN (Bit 11) */ -#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Msk (0x800UL) /*!< BLE BLE_RFTESTCNTL_REG: TXPKTCNTEN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Pos (12UL) /*!< BLE BLE_RFTESTCNTL_REG: TXPLDSRC (Bit 12) */ -#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Msk (0x1000UL) /*!< BLE BLE_RFTESTCNTL_REG: TXPLDSRC (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Pos (13UL) /*!< BLE BLE_RFTESTCNTL_REG: PRBSTYPE (Bit 13) */ -#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Msk (0x2000UL) /*!< BLE BLE_RFTESTCNTL_REG: PRBSTYPE (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Pos (14UL) /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTHSRC (Bit 14) */ -#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Msk (0x4000UL) /*!< BLE BLE_RFTESTCNTL_REG: TXLENGTHSRC (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Pos (15UL) /*!< BLE BLE_RFTESTCNTL_REG: INFINITETX (Bit 15) */ -#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Msk (0x8000UL) /*!< BLE BLE_RFTESTCNTL_REG: INFINITETX (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Pos (27UL) /*!< BLE BLE_RFTESTCNTL_REG: RXPKTCNTEN (Bit 27) */ -#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Msk (0x8000000UL) /*!< BLE BLE_RFTESTCNTL_REG: RXPKTCNTEN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Pos (31UL) /*!< BLE BLE_RFTESTCNTL_REG: INFINITERX (Bit 31) */ -#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Msk (0x80000000UL) /*!< BLE BLE_RFTESTCNTL_REG: INFINITERX (Bitfield-Mask: 0x01) */ - -/* -------------------------- BLE_BLE_RFTESTTXSTAT_REG -------------------------- */ -#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Pos (0UL) /*!< BLE BLE_RFTESTTXSTAT_REG: TXPKTCNT (Bit 0) */ -#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Msk (0xffffffffUL) /*!< BLE BLE_RFTESTTXSTAT_REG: TXPKTCNT (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- BLE_BLE_RFTESTRXSTAT_REG -------------------------- */ -#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Pos (0UL) /*!< BLE BLE_RFTESTRXSTAT_REG: RXPKTCNT (Bit 0) */ -#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Msk (0xffffffffUL) /*!< BLE BLE_RFTESTRXSTAT_REG: RXPKTCNT (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- BLE_BLE_TIMGENCNTL_REG --------------------------- */ -#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Pos (0UL) /*!< BLE BLE_TIMGENCNTL_REG: PREFETCH_TIME (Bit 0) */ -#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Msk (0x1ffUL) /*!< BLE BLE_TIMGENCNTL_REG: PREFETCH_TIME (Bitfield-Mask: 0x1ff) */ -#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Pos (16UL) /*!< BLE BLE_TIMGENCNTL_REG: PREFETCHABORT_TIME (Bit 16) */ -#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Msk (0x3ff0000UL) /*!< BLE BLE_TIMGENCNTL_REG: PREFETCHABORT_TIME (Bitfield-Mask: 0x3ff) */ -#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Pos (31UL) /*!< BLE BLE_TIMGENCNTL_REG: APFM_EN (Bit 31) */ -#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Msk (0x80000000UL) /*!< BLE BLE_TIMGENCNTL_REG: APFM_EN (Bitfield-Mask: 0x01) */ - -/* --------------------------- BLE_BLE_GROSSTIMTGT_REG -------------------------- */ -#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Pos (0UL) /*!< BLE BLE_GROSSTIMTGT_REG: GROSSTARGET (Bit 0) */ -#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Msk (0x7fffffUL) /*!< BLE BLE_GROSSTIMTGT_REG: GROSSTARGET (Bitfield-Mask: 0x7fffff) */ - -/* --------------------------- BLE_BLE_FINETIMTGT_REG --------------------------- */ -#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Pos (0UL) /*!< BLE BLE_FINETIMTGT_REG: FINETARGET (Bit 0) */ -#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Msk (0x7ffffffUL) /*!< BLE BLE_FINETIMTGT_REG: FINETARGET (Bitfield-Mask: 0x7ffffff) */ - -/* ---------------------------- BLE_BLE_SAMPLECLK_REG --------------------------- */ -#define BLE_BLE_SAMPLECLK_REG_SAMP_Pos (0UL) /*!< BLE BLE_SAMPLECLK_REG: SAMP (Bit 0) */ -#define BLE_BLE_SAMPLECLK_REG_SAMP_Msk (0x1UL) /*!< BLE BLE_SAMPLECLK_REG: SAMP (Bitfield-Mask: 0x01) */ - -/* --------------------------- BLE_BLE_COEXIFCNTL0_REG -------------------------- */ -#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Pos (0UL) /*!< BLE BLE_COEXIFCNTL0_REG: COEX_EN (Bit 0) */ -#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Msk (0x1UL) /*!< BLE BLE_COEXIFCNTL0_REG: COEX_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Pos (1UL) /*!< BLE BLE_COEXIFCNTL0_REG: SYNCGEN_EN (Bit 1) */ -#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Msk (0x2UL) /*!< BLE BLE_COEXIFCNTL0_REG: SYNCGEN_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Pos (4UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLANRXMSK (Bit 4) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Msk (0x30UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLANRXMSK (Bitfield-Mask: 0x03) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Pos (6UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLANTXMSK (Bit 6) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Msk (0xc0UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLANTXMSK (Bitfield-Mask: 0x03) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Pos (16UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLCTXPRIOMODE (Bit 16) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Msk (0x30000UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLCTXPRIOMODE (Bitfield-Mask: 0x03) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Pos (20UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLCRXPRIOMODE (Bit 20) */ -#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Msk (0x300000UL) /*!< BLE BLE_COEXIFCNTL0_REG: WLCRXPRIOMODE (Bitfield-Mask: 0x03) */ - -/* --------------------------- BLE_BLE_COEXIFCNTL1_REG -------------------------- */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Pos (0UL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDELAY (Bit 0) */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Msk (0x7fUL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDELAY (Bitfield-Mask: 0x7f) */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Pos (8UL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDURATION (Bit 8) */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Msk (0x7f00UL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPDURATION (Bitfield-Mask: 0x7f) */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Pos (16UL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPTXTHR (Bit 16) */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Msk (0x1f0000UL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPTXTHR (Bitfield-Mask: 0x1f) */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Pos (24UL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPRXTHR (Bit 24) */ -#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Msk (0x1f000000UL) /*!< BLE BLE_COEXIFCNTL1_REG: WLCPRXTHR (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- BLE_BLE_BLEMPRIO0_REG --------------------------- */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Pos (0UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM0 (Bit 0) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Msk (0xfUL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM0 (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Pos (4UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM1 (Bit 4) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Msk (0xf0UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM1 (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Pos (8UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM2 (Bit 8) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Msk (0xf00UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM2 (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Pos (12UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM3 (Bit 12) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Msk (0xf000UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM3 (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Pos (16UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM4 (Bit 16) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Msk (0xf0000UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM4 (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Pos (20UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM5 (Bit 20) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Msk (0xf00000UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM5 (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Pos (24UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM6 (Bit 24) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Msk (0xf000000UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM6 (Bitfield-Mask: 0x0f) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Pos (28UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM7 (Bit 28) */ -#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Msk (0xf0000000UL) /*!< BLE BLE_BLEMPRIO0_REG: BLEM7 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- BLE_BLE_BLEMPRIO1_REG --------------------------- */ -#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Pos (28UL) /*!< BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bit 28) */ -#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Msk (0xf0000000UL) /*!< BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bitfield-Mask: 0x0f) */ - -/* ------------------------------ BLE_BLE_CNTL2_REG ----------------------------- */ -#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Pos (0UL) /*!< BLE BLE_CNTL2_REG: EMACCERRSTAT (Bit 0) */ -#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Msk (0x1UL) /*!< BLE BLE_CNTL2_REG: EMACCERRSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_EMACCERRACK_Pos (1UL) /*!< BLE BLE_CNTL2_REG: EMACCERRACK (Bit 1) */ -#define BLE_BLE_CNTL2_REG_EMACCERRACK_Msk (0x2UL) /*!< BLE BLE_CNTL2_REG: EMACCERRACK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Pos (2UL) /*!< BLE BLE_CNTL2_REG: EMACCERRMSK (Bit 2) */ -#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Msk (0x4UL) /*!< BLE BLE_CNTL2_REG: EMACCERRMSK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Pos (3UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bit 3) */ -#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Msk (0x8UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Pos (4UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bit 4) */ -#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Msk (0x30UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bitfield-Mask: 0x03) */ -#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Pos (6UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bit 6) */ -#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Msk (0x40UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Pos (7UL) /*!< BLE BLE_CNTL2_REG: MON_LP_CLK (Bit 7) */ -#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Msk (0x80UL) /*!< BLE BLE_CNTL2_REG: MON_LP_CLK (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Pos (8UL) /*!< BLE BLE_CNTL2_REG: RADIO_PWRDN_ALLOW (Bit 8) */ -#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Msk (0x100UL) /*!< BLE BLE_CNTL2_REG: RADIO_PWRDN_ALLOW (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Pos (9UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bit 9) */ -#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Msk (0x7e00UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Pos (15UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bit 15) */ -#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Msk (0x8000UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Pos (16UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bit 16) */ -#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Msk (0x10000UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Pos (17UL) /*!< BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bit 17) */ -#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Msk (0x20000UL) /*!< BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BB_ONLY_Pos (18UL) /*!< BLE BLE_CNTL2_REG: BB_ONLY (Bit 18) */ -#define BLE_BLE_CNTL2_REG_BB_ONLY_Msk (0x40000UL) /*!< BLE BLE_CNTL2_REG: BB_ONLY (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Pos (19UL) /*!< BLE BLE_CNTL2_REG: SW_RPL_SPI (Bit 19) */ -#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Msk (0x80000UL) /*!< BLE BLE_CNTL2_REG: SW_RPL_SPI (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Pos (20UL) /*!< BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bit 20) */ -#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Msk (0x100000UL) /*!< BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Pos (21UL) /*!< BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bit 21) */ -#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Msk (0x200000UL) /*!< BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bitfield-Mask: 0x01) */ -#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Pos (22UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bit 22) */ -#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Msk (0xffc00000UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bitfield-Mask: 0x3ff) */ - -/* ----------------------------- BLE_BLE_EM_BASE_REG ---------------------------- */ -#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Pos (10UL) /*!< BLE BLE_EM_BASE_REG: BLE_EM_BASE_16_10 (Bit 10) */ -#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Msk (0x1fc00UL) /*!< BLE BLE_EM_BASE_REG: BLE_EM_BASE_16_10 (Bitfield-Mask: 0x7f) */ - -/* ---------------------------- BLE_BLE_DIAGCNTL2_REG --------------------------- */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Pos (0UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG4 (Bit 0) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Msk (0x3fUL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG4 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Pos (7UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG4_EN (Bit 7) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Msk (0x80UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG4_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Pos (8UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG5 (Bit 8) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Msk (0x3f00UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG5 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Pos (15UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG5_EN (Bit 15) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Msk (0x8000UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG5_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Pos (16UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG6 (Bit 16) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Msk (0x3f0000UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG6 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Pos (23UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG6_EN (Bit 23) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Msk (0x800000UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG6_EN (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Pos (24UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG7 (Bit 24) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Msk (0x3f000000UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG7 (Bitfield-Mask: 0x3f) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Pos (31UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG7_EN (Bit 31) */ -#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Msk (0x80000000UL) /*!< BLE BLE_DIAGCNTL2_REG: DIAG7_EN (Bitfield-Mask: 0x01) */ - -/* ---------------------------- BLE_BLE_DIAGCNTL3_REG --------------------------- */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Pos (0UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_BIT (Bit 0) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Msk (0x7UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Pos (3UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_INV (Bit 3) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Msk (0x8UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG0_INV (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Pos (4UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_BIT (Bit 4) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Msk (0x70UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Pos (7UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_INV (Bit 7) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Msk (0x80UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG1_INV (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Pos (8UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_BIT (Bit 8) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Msk (0x700UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Pos (11UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_INV (Bit 11) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Msk (0x800UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG2_INV (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Pos (12UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_BIT (Bit 12) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Msk (0x7000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Pos (15UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_INV (Bit 15) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Msk (0x8000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG3_INV (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Pos (16UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_BIT (Bit 16) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Msk (0x70000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Pos (19UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_INV (Bit 19) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Msk (0x80000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG4_INV (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Pos (20UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_BIT (Bit 20) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Msk (0x700000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Pos (23UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_INV (Bit 23) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Msk (0x800000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG5_INV (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Pos (24UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_BIT (Bit 24) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Msk (0x7000000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Pos (27UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_INV (Bit 27) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Msk (0x8000000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG6_INV (Bitfield-Mask: 0x01) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Pos (28UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_BIT (Bit 28) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Msk (0x70000000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_BIT (Bitfield-Mask: 0x07) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Pos (31UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_INV (Bit 31) */ -#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Msk (0x80000000UL) /*!< BLE BLE_DIAGCNTL3_REG: DIAG7_INV (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'CACHE' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- CACHE_CACHE_CTRL1_REG --------------------------- */ -#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos (0UL) /*!< CACHE CACHE_CTRL1_REG: CACHE_FLUSH (Bit 0) */ -#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk (0x1UL) /*!< CACHE CACHE_CTRL1_REG: CACHE_FLUSH (Bitfield-Mask: 0x01) */ -#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos (1UL) /*!< CACHE CACHE_CTRL1_REG: CACHE_RES1 (Bit 1) */ -#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk (0x2UL) /*!< CACHE CACHE_CTRL1_REG: CACHE_RES1 (Bitfield-Mask: 0x01) */ - -/* -------------------------- CACHE_CACHE_LNSIZECFG_REG ------------------------- */ -#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos (0UL) /*!< CACHE CACHE_LNSIZECFG_REG: CACHE_LINE (Bit 0) */ -#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk (0x3UL) /*!< CACHE CACHE_LNSIZECFG_REG: CACHE_LINE (Bitfield-Mask: 0x03) */ - -/* -------------------------- CACHE_CACHE_ASSOCCFG_REG -------------------------- */ -#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos (0UL) /*!< CACHE CACHE_ASSOCCFG_REG: CACHE_ASSOC (Bit 0) */ -#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk (0x3UL) /*!< CACHE CACHE_ASSOCCFG_REG: CACHE_ASSOC (Bitfield-Mask: 0x03) */ - -/* ---------------------------- CACHE_CACHE_CTRL2_REG --------------------------- */ -#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL) /*!< CACHE CACHE_CTRL2_REG: CACHE_LEN (Bit 0) */ -#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL) /*!< CACHE CACHE_CTRL2_REG: CACHE_LEN (Bitfield-Mask: 0x1ff) */ -#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL) /*!< CACHE CACHE_CTRL2_REG: CACHE_WEN (Bit 9) */ -#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL) /*!< CACHE CACHE_CTRL2_REG: CACHE_WEN (Bitfield-Mask: 0x01) */ -#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL) /*!< CACHE CACHE_CTRL2_REG: CACHE_CGEN (Bit 10) */ -#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL) /*!< CACHE CACHE_CTRL2_REG: CACHE_CGEN (Bitfield-Mask: 0x01) */ -#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Pos (11UL) /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_OTP_CACHED (Bit 11) */ -#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Msk (0x800UL) /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_OTP_CACHED (Bitfield-Mask: 0x01) */ -#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Pos (12UL) /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_QSPIFLASH_CACHED (Bit 12) */ -#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Msk (0x1000UL) /*!< CACHE CACHE_CTRL2_REG: ENABLE_ALSO_QSPIFLASH_CACHED (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CACHE_CACHE_CTRL3_REG --------------------------- */ -#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Pos (0UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_ASSOCIATIVITY_RESET_VALUE (Bit 0) */ -#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Msk (0x3UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_ASSOCIATIVITY_RESET_VALUE (Bitfield-Mask: 0x03) */ -#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Pos (2UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_LINE_SIZE_RESET_VALUE (Bit 2) */ -#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Msk (0xcUL) /*!< CACHE CACHE_CTRL3_REG: CACHE_LINE_SIZE_RESET_VALUE (Bitfield-Mask: 0x03) */ -#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Pos (4UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_RAM_SIZE_RESET_VALUE (Bit 4) */ -#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Msk (0x70UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_RAM_SIZE_RESET_VALUE (Bitfield-Mask: 0x07) */ -#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Pos (7UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_CONTROLLER_RESET (Bit 7) */ -#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Msk (0x80UL) /*!< CACHE CACHE_CTRL3_REG: CACHE_CONTROLLER_RESET (Bitfield-Mask: 0x01) */ - -/* -------------------------- CACHE_CACHE_MRM_HITS_REG -------------------------- */ -#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL) /*!< CACHE CACHE_MRM_HITS_REG: MRM_HITS (Bit 0) */ -#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0x7ffffUL) /*!< CACHE CACHE_MRM_HITS_REG: MRM_HITS (Bitfield-Mask: 0x7ffff) */ - -/* ------------------------- CACHE_CACHE_MRM_MISSES_REG ------------------------- */ -#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL) /*!< CACHE CACHE_MRM_MISSES_REG: MRM_MISSES (Bit 0) */ -#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0x3ffffUL) /*!< CACHE CACHE_MRM_MISSES_REG: MRM_MISSES (Bitfield-Mask: 0x3ffff) */ - -/* -------------------------- CACHE_CACHE_MRM_CTRL_REG -------------------------- */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_START (Bit 0) */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_START (Bitfield-Mask: 0x01) */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_MASK (Bit 1) */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_MASK (Bitfield-Mask: 0x01) */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_TINT_STATUS (Bit 2) */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01) */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Pos (3UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_THRES_STATUS (Bit 3) */ -#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Msk (0x8UL) /*!< CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_THRES_STATUS (Bitfield-Mask: 0x01) */ - -/* -------------------------- CACHE_CACHE_MRM_TINT_REG -------------------------- */ -#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL) /*!< CACHE CACHE_MRM_TINT_REG: MRM_TINT (Bit 0) */ -#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x3ffffUL) /*!< CACHE CACHE_MRM_TINT_REG: MRM_TINT (Bitfield-Mask: 0x3ffff) */ - -/* -------------------------- CACHE_CACHE_MRM_THRES_REG ------------------------- */ -#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Pos (0UL) /*!< CACHE CACHE_MRM_THRES_REG: MRM_THRES (Bit 0) */ -#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Msk (0x3ffffUL) /*!< CACHE CACHE_MRM_THRES_REG: MRM_THRES (Bitfield-Mask: 0x3ffff) */ - -/* ----------------------------- CACHE_SWD_RESET_REG ---------------------------- */ -#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL) /*!< CACHE SWD_RESET_REG: SWD_HW_RESET_REQ (Bit 0) */ -#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL) /*!< CACHE SWD_RESET_REG: SWD_HW_RESET_REQ (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'CHIP_VERSION' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- CHIP_VERSION_CHIP_ID1_REG ------------------------- */ -#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL) /*!< CHIP_VERSION CHIP_ID1_REG: CHIP_ID1 (Bit 0) */ -#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL) /*!< CHIP_VERSION CHIP_ID1_REG: CHIP_ID1 (Bitfield-Mask: 0xff) */ - -/* -------------------------- CHIP_VERSION_CHIP_ID2_REG ------------------------- */ -#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL) /*!< CHIP_VERSION CHIP_ID2_REG: CHIP_ID2 (Bit 0) */ -#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL) /*!< CHIP_VERSION CHIP_ID2_REG: CHIP_ID2 (Bitfield-Mask: 0xff) */ - -/* -------------------------- CHIP_VERSION_CHIP_ID3_REG ------------------------- */ -#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL) /*!< CHIP_VERSION CHIP_ID3_REG: CHIP_ID3 (Bit 0) */ -#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL) /*!< CHIP_VERSION CHIP_ID3_REG: CHIP_ID3 (Bitfield-Mask: 0xff) */ - -/* -------------------------- CHIP_VERSION_CHIP_SWC_REG ------------------------- */ -#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL) /*!< CHIP_VERSION CHIP_SWC_REG: CHIP_SWC (Bit 0) */ -#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL) /*!< CHIP_VERSION CHIP_SWC_REG: CHIP_SWC (Bitfield-Mask: 0x0f) */ - -/* ----------------------- CHIP_VERSION_CHIP_REVISION_REG ----------------------- */ -#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Pos (0UL) /*!< CHIP_VERSION CHIP_REVISION_REG: REVISION_ID (Bit 0) */ -#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Msk (0xffUL) /*!< CHIP_VERSION CHIP_REVISION_REG: REVISION_ID (Bitfield-Mask: 0xff) */ - -/* ------------------------ CHIP_VERSION_CHIP_CONFIG1_REG ----------------------- */ -#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Pos (0UL) /*!< CHIP_VERSION CHIP_CONFIG1_REG: CHIP_CONFIG1 (Bit 0) */ -#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Msk (0xffUL) /*!< CHIP_VERSION CHIP_CONFIG1_REG: CHIP_CONFIG1 (Bitfield-Mask: 0xff) */ - -/* ------------------------ CHIP_VERSION_CHIP_CONFIG2_REG ----------------------- */ -#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Pos (0UL) /*!< CHIP_VERSION CHIP_CONFIG2_REG: CHIP_CONFIG2 (Bit 0) */ -#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Msk (0xffUL) /*!< CHIP_VERSION CHIP_CONFIG2_REG: CHIP_CONFIG2 (Bitfield-Mask: 0xff) */ - -/* ------------------------ CHIP_VERSION_CHIP_CONFIG3_REG ----------------------- */ -#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Pos (0UL) /*!< CHIP_VERSION CHIP_CONFIG3_REG: CHIP_CONFIG3 (Bit 0) */ -#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Msk (0xffUL) /*!< CHIP_VERSION CHIP_CONFIG3_REG: CHIP_CONFIG3 (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'COEX' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- COEX_COEX_CTRL_REG ----------------------------- */ -#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Pos (0UL) /*!< COEX COEX_CTRL_REG: PRGING_ARBITER (Bit 0) */ -#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Msk (0x1UL) /*!< COEX COEX_CTRL_REG: PRGING_ARBITER (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Pos (1UL) /*!< COEX COEX_CTRL_REG: DECISION_SW_ALL (Bit 1) */ -#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Msk (0x2UL) /*!< COEX COEX_CTRL_REG: DECISION_SW_ALL (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Pos (2UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bit 2) */ -#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Msk (0x4UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Pos (3UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bit 3) */ -#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Msk (0x8UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Pos (4UL) /*!< COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bit 4) */ -#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Msk (0x10UL) /*!< COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Pos (5UL) /*!< COEX COEX_CTRL_REG: SEL_COEX_DIAG (Bit 5) */ -#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Msk (0x60UL) /*!< COEX COEX_CTRL_REG: SEL_COEX_DIAG (Bitfield-Mask: 0x03) */ -#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Pos (7UL) /*!< COEX COEX_CTRL_REG: SEL_FTDF_CCA (Bit 7) */ -#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Msk (0x80UL) /*!< COEX COEX_CTRL_REG: SEL_FTDF_CCA (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Pos (8UL) /*!< COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bit 8) */ -#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Msk (0x100UL) /*!< COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Pos (9UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_PTI (Bit 9) */ -#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Msk (0x200UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_PTI (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Pos (10UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bit 10) */ -#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Msk (0x400UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Pos (11UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_RADIO_BUSY (Bit 11) */ -#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Msk (0x1800UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_RADIO_BUSY (Bitfield-Mask: 0x03) */ -#define COEX_COEX_CTRL_REG_IGNORE_EXT_Pos (13UL) /*!< COEX COEX_CTRL_REG: IGNORE_EXT (Bit 13) */ -#define COEX_COEX_CTRL_REG_IGNORE_EXT_Msk (0x2000UL) /*!< COEX COEX_CTRL_REG: IGNORE_EXT (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Pos (14UL) /*!< COEX COEX_CTRL_REG: IGNORE_FTDF (Bit 14) */ -#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Msk (0x4000UL) /*!< COEX COEX_CTRL_REG: IGNORE_FTDF (Bitfield-Mask: 0x01) */ -#define COEX_COEX_CTRL_REG_IGNORE_BLE_Pos (15UL) /*!< COEX COEX_CTRL_REG: IGNORE_BLE (Bit 15) */ -#define COEX_COEX_CTRL_REG_IGNORE_BLE_Msk (0x8000UL) /*!< COEX COEX_CTRL_REG: IGNORE_BLE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- COEX_COEX_STAT_REG ----------------------------- */ -#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Pos (0UL) /*!< COEX COEX_STAT_REG: COEX_DECISION_PTR (Bit 0) */ -#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Msk (0xfUL) /*!< COEX COEX_STAT_REG: COEX_DECISION_PTR (Bitfield-Mask: 0x0f) */ -#define COEX_COEX_STAT_REG_COEX_DECISION_Pos (5UL) /*!< COEX COEX_STAT_REG: COEX_DECISION (Bit 5) */ -#define COEX_COEX_STAT_REG_COEX_DECISION_Msk (0x60UL) /*!< COEX COEX_STAT_REG: COEX_DECISION (Bitfield-Mask: 0x03) */ -#define COEX_COEX_STAT_REG_COEX_CLOSING_Pos (7UL) /*!< COEX COEX_STAT_REG: COEX_CLOSING (Bit 7) */ -#define COEX_COEX_STAT_REG_COEX_CLOSING_Msk (0x80UL) /*!< COEX COEX_STAT_REG: COEX_CLOSING (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_SMART_ACT_Pos (8UL) /*!< COEX COEX_STAT_REG: SMART_ACT (Bit 8) */ -#define COEX_COEX_STAT_REG_SMART_ACT_Msk (0x100UL) /*!< COEX COEX_STAT_REG: SMART_ACT (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_SMART_PRI_Pos (9UL) /*!< COEX COEX_STAT_REG: SMART_PRI (Bit 9) */ -#define COEX_COEX_STAT_REG_SMART_PRI_Msk (0x200UL) /*!< COEX COEX_STAT_REG: SMART_PRI (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_EXT_ACT0_Pos (10UL) /*!< COEX COEX_STAT_REG: EXT_ACT0 (Bit 10) */ -#define COEX_COEX_STAT_REG_EXT_ACT0_Msk (0x400UL) /*!< COEX COEX_STAT_REG: EXT_ACT0 (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_EXT_ACT1_Pos (11UL) /*!< COEX COEX_STAT_REG: EXT_ACT1 (Bit 11) */ -#define COEX_COEX_STAT_REG_EXT_ACT1_Msk (0x800UL) /*!< COEX COEX_STAT_REG: EXT_ACT1 (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Pos (12UL) /*!< COEX COEX_STAT_REG: COEX_RADIO_BUSY (Bit 12) */ -#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Msk (0x1000UL) /*!< COEX COEX_STAT_REG: COEX_RADIO_BUSY (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Pos (13UL) /*!< COEX COEX_STAT_REG: IGNORE_EXT_STAT (Bit 13) */ -#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Msk (0x2000UL) /*!< COEX COEX_STAT_REG: IGNORE_EXT_STAT (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Pos (14UL) /*!< COEX COEX_STAT_REG: IGNORE_FTDF_STAT (Bit 14) */ -#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Msk (0x4000UL) /*!< COEX COEX_STAT_REG: IGNORE_FTDF_STAT (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Pos (15UL) /*!< COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bit 15) */ -#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Msk (0x8000UL) /*!< COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bitfield-Mask: 0x01) */ - -/* ----------------------------- COEX_COEX_STAT2_REG ---------------------------- */ -#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Pos (0UL) /*!< COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bit 0) */ -#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Msk (0x7UL) /*!< COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bitfield-Mask: 0x07) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Pos (3UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bit 3) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Msk (0x8UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Pos (4UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bit 4) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Msk (0x10UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Pos (5UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bit 5) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Msk (0x20UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Pos (6UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bit 6) */ -#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Msk (0x1c0UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bitfield-Mask: 0x07) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Pos (9UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bit 9) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Msk (0x200UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Pos (10UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bit 10) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Msk (0x400UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Pos (11UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bit 11) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Msk (0x800UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bitfield-Mask: 0x01) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Pos (12UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bit 12) */ -#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Msk (0x7000UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bitfield-Mask: 0x07) */ -#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Pos (15UL) /*!< COEX COEX_STAT2_REG: COEX_EXT_ACT (Bit 15) */ -#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Msk (0x8000UL) /*!< COEX COEX_STAT2_REG: COEX_EXT_ACT (Bitfield-Mask: 0x01) */ - -/* --------------------------- COEX_COEX_INT_MASK_REG --------------------------- */ -#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Pos (8UL) /*!< COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bit 8) */ -#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Msk (0x100UL) /*!< COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Pos (9UL) /*!< COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bit 9) */ -#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Msk (0x200UL) /*!< COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01) */ - -/* --------------------------- COEX_COEX_INT_STAT_REG --------------------------- */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Pos (0UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bit 0) */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Msk (0xfUL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bitfield-Mask: 0x0f) */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Pos (5UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bit 5) */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Msk (0x20UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Pos (6UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bit 6) */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Msk (0x40UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Pos (7UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bit 7) */ -#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Msk (0x80UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Pos (8UL) /*!< COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bit 8) */ -#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Msk (0x100UL) /*!< COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Pos (9UL) /*!< COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bit 9) */ -#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Msk (0x200UL) /*!< COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01) */ - -/* ---------------------------- COEX_COEX_BLE_PTI_REG --------------------------- */ -#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Pos (0UL) /*!< COEX COEX_BLE_PTI_REG: COEX_BLE_PTI (Bit 0) */ -#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Msk (0x7UL) /*!< COEX COEX_BLE_PTI_REG: COEX_BLE_PTI (Bitfield-Mask: 0x07) */ - -/* --------------------------- COEX_COEX_FTDF_PTI_REG --------------------------- */ -#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Pos (0UL) /*!< COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bit 0) */ -#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Msk (0x7UL) /*!< COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bitfield-Mask: 0x07) */ - -/* ----------------------------- COEX_COEX_PRI1_REG ----------------------------- */ -#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI1_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI1_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI1_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI1_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI2_REG ----------------------------- */ -#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI2_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI2_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI2_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI2_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI3_REG ----------------------------- */ -#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI3_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI3_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI3_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI3_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI4_REG ----------------------------- */ -#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI4_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI4_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI4_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI4_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI5_REG ----------------------------- */ -#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI5_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI5_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI5_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI5_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI6_REG ----------------------------- */ -#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI6_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI6_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI6_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI6_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI7_REG ----------------------------- */ -#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI7_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI7_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI7_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI7_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI8_REG ----------------------------- */ -#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI8_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI8_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI8_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI8_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI9_REG ----------------------------- */ -#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI9_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI9_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI9_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI9_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI10_REG ---------------------------- */ -#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI10_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI10_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI10_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI10_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI11_REG ---------------------------- */ -#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI11_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI11_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI11_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI11_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI12_REG ---------------------------- */ -#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI12_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI12_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI12_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI12_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI13_REG ---------------------------- */ -#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI13_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI13_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI13_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI13_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI14_REG ---------------------------- */ -#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI14_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI14_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI14_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI14_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI15_REG ---------------------------- */ -#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI15_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI15_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI15_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI15_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - - -/* ================================================================================ */ -/* ================ struct 'CRG_PER' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- CRG_PER_CLK_PER_REG ---------------------------- */ -#define CRG_PER_CLK_PER_REG_UART_ENABLE_Pos (0UL) /*!< CRG_PER CLK_PER_REG: UART_ENABLE (Bit 0) */ -#define CRG_PER_CLK_PER_REG_UART_ENABLE_Msk (0x1UL) /*!< CRG_PER CLK_PER_REG: UART_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Pos (1UL) /*!< CRG_PER CLK_PER_REG: SPI_ENABLE (Bit 1) */ -#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Msk (0x2UL) /*!< CRG_PER CLK_PER_REG: SPI_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Pos (2UL) /*!< CRG_PER CLK_PER_REG: I2C_ENABLE (Bit 2) */ -#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Msk (0x4UL) /*!< CRG_PER CLK_PER_REG: I2C_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Pos (3UL) /*!< CRG_PER CLK_PER_REG: QUAD_ENABLE (Bit 3) */ -#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Msk (0x8UL) /*!< CRG_PER CLK_PER_REG: QUAD_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Pos (4UL) /*!< CRG_PER CLK_PER_REG: IR_CLK_ENABLE (Bit 4) */ -#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Msk (0x10UL) /*!< CRG_PER CLK_PER_REG: IR_CLK_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Pos (5UL) /*!< CRG_PER CLK_PER_REG: KBSCAN_ENABLE (Bit 5) */ -#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Msk (0x20UL) /*!< CRG_PER CLK_PER_REG: KBSCAN_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Pos (8UL) /*!< CRG_PER CLK_PER_REG: SPI_CLK_SEL (Bit 8) */ -#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Msk (0x100UL) /*!< CRG_PER CLK_PER_REG: SPI_CLK_SEL (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Pos (9UL) /*!< CRG_PER CLK_PER_REG: I2C_CLK_SEL (Bit 9) */ -#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Msk (0x200UL) /*!< CRG_PER CLK_PER_REG: I2C_CLK_SEL (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Pos (10UL) /*!< CRG_PER CLK_PER_REG: KBSCAN_CLK_SEL (Bit 10) */ -#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Msk (0x400UL) /*!< CRG_PER CLK_PER_REG: KBSCAN_CLK_SEL (Bitfield-Mask: 0x01) */ -#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Pos (11UL) /*!< CRG_PER CLK_PER_REG: ADC_CLK_SEL (Bit 11) */ -#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Msk (0x800UL) /*!< CRG_PER CLK_PER_REG: ADC_CLK_SEL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- CRG_PER_PCM_DIV_REG ---------------------------- */ -#define CRG_PER_PCM_DIV_REG_PCM_DIV_Pos (0UL) /*!< CRG_PER PCM_DIV_REG: PCM_DIV (Bit 0) */ -#define CRG_PER_PCM_DIV_REG_PCM_DIV_Msk (0xfffUL) /*!< CRG_PER PCM_DIV_REG: PCM_DIV (Bitfield-Mask: 0xfff) */ -#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos (12UL) /*!< CRG_PER PCM_DIV_REG: CLK_PCM_EN (Bit 12) */ -#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk (0x1000UL) /*!< CRG_PER PCM_DIV_REG: CLK_PCM_EN (Bitfield-Mask: 0x01) */ -#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos (13UL) /*!< CRG_PER PCM_DIV_REG: PCM_SRC_SEL (Bit 13) */ -#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk (0x2000UL) /*!< CRG_PER PCM_DIV_REG: PCM_SRC_SEL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_PER_PCM_FDIV_REG ---------------------------- */ -#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos (0UL) /*!< CRG_PER PCM_FDIV_REG: PCM_FDIV (Bit 0) */ -#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk (0xffffUL) /*!< CRG_PER PCM_FDIV_REG: PCM_FDIV (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- CRG_PER_PDM_DIV_REG ---------------------------- */ -#define CRG_PER_PDM_DIV_REG_PDM_DIV_Pos (0UL) /*!< CRG_PER PDM_DIV_REG: PDM_DIV (Bit 0) */ -#define CRG_PER_PDM_DIV_REG_PDM_DIV_Msk (0xffUL) /*!< CRG_PER PDM_DIV_REG: PDM_DIV (Bitfield-Mask: 0xff) */ -#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos (8UL) /*!< CRG_PER PDM_DIV_REG: CLK_PDM_EN (Bit 8) */ -#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk (0x100UL) /*!< CRG_PER PDM_DIV_REG: CLK_PDM_EN (Bitfield-Mask: 0x01) */ -#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL) /*!< CRG_PER PDM_DIV_REG: PDM_MASTER_MODE (Bit 9) */ -#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL) /*!< CRG_PER PDM_DIV_REG: PDM_MASTER_MODE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- CRG_PER_SRC_DIV_REG ---------------------------- */ -#define CRG_PER_SRC_DIV_REG_SRC_DIV_Pos (0UL) /*!< CRG_PER SRC_DIV_REG: SRC_DIV (Bit 0) */ -#define CRG_PER_SRC_DIV_REG_SRC_DIV_Msk (0xffUL) /*!< CRG_PER SRC_DIV_REG: SRC_DIV (Bitfield-Mask: 0xff) */ -#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos (8UL) /*!< CRG_PER SRC_DIV_REG: CLK_SRC_EN (Bit 8) */ -#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk (0x100UL) /*!< CRG_PER SRC_DIV_REG: CLK_SRC_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- CRG_PER_EH_REG ------------------------------- */ -#define CRG_PER_EH_REG_EH_EN_Pos (0UL) /*!< CRG_PER EH_REG: EH_EN (Bit 0) */ -#define CRG_PER_EH_REG_EH_EN_Msk (0x1UL) /*!< CRG_PER EH_REG: EH_EN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- CRG_PER_USBPAD_REG ----------------------------- */ -#define CRG_PER_USBPAD_REG_USBPAD_EN_Pos (0UL) /*!< CRG_PER USBPAD_REG: USBPAD_EN (Bit 0) */ -#define CRG_PER_USBPAD_REG_USBPAD_EN_Msk (0x1UL) /*!< CRG_PER USBPAD_REG: USBPAD_EN (Bitfield-Mask: 0x01) */ -#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos (1UL) /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW1_OFF (Bit 1) */ -#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk (0x2UL) /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW1_OFF (Bitfield-Mask: 0x01) */ -#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos (2UL) /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW2_ON (Bit 2) */ -#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk (0x4UL) /*!< CRG_PER USBPAD_REG: USBPHY_FORCE_SW2_ON (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'CRG_TOP' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- CRG_TOP_CLK_AMBA_REG ---------------------------- */ -#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL) /*!< CRG_TOP CLK_AMBA_REG: HCLK_DIV (Bit 0) */ -#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL) /*!< CRG_TOP CLK_AMBA_REG: HCLK_DIV (Bitfield-Mask: 0x07) */ -#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos (4UL) /*!< CRG_TOP CLK_AMBA_REG: PCLK_DIV (Bit 4) */ -#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk (0x30UL) /*!< CRG_TOP CLK_AMBA_REG: PCLK_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL) /*!< CRG_TOP CLK_AMBA_REG: AES_CLK_ENABLE (Bit 6) */ -#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL) /*!< CRG_TOP CLK_AMBA_REG: AES_CLK_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Pos (7UL) /*!< CRG_TOP CLK_AMBA_REG: ECC_CLK_ENABLE (Bit 7) */ -#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Msk (0x80UL) /*!< CRG_TOP CLK_AMBA_REG: ECC_CLK_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos (8UL) /*!< CRG_TOP CLK_AMBA_REG: TRNG_CLK_ENABLE (Bit 8) */ -#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk (0x100UL) /*!< CRG_TOP CLK_AMBA_REG: TRNG_CLK_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos (9UL) /*!< CRG_TOP CLK_AMBA_REG: OTP_ENABLE (Bit 9) */ -#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk (0x200UL) /*!< CRG_TOP CLK_AMBA_REG: OTP_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos (10UL) /*!< CRG_TOP CLK_AMBA_REG: QSPI_DIV (Bit 10) */ -#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk (0xc00UL) /*!< CRG_TOP CLK_AMBA_REG: QSPI_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos (12UL) /*!< CRG_TOP CLK_AMBA_REG: QSPI_ENABLE (Bit 12) */ -#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk (0x1000UL) /*!< CRG_TOP CLK_AMBA_REG: QSPI_ENABLE (Bitfield-Mask: 0x01) */ - -/* -------------------------- CRG_TOP_CLK_FREQ_TRIM_REG ------------------------- */ -#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Pos (0UL) /*!< CRG_TOP CLK_FREQ_TRIM_REG: FINE_ADJ (Bit 0) */ -#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Msk (0xffUL) /*!< CRG_TOP CLK_FREQ_TRIM_REG: FINE_ADJ (Bitfield-Mask: 0xff) */ -#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Pos (8UL) /*!< CRG_TOP CLK_FREQ_TRIM_REG: COARSE_ADJ (Bit 8) */ -#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Msk (0x700UL) /*!< CRG_TOP CLK_FREQ_TRIM_REG: COARSE_ADJ (Bitfield-Mask: 0x07) */ - -/* ---------------------------- CRG_TOP_CLK_RADIO_REG --------------------------- */ -#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Pos (0UL) /*!< CRG_TOP CLK_RADIO_REG: RFCU_DIV (Bit 0) */ -#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Msk (0x3UL) /*!< CRG_TOP CLK_RADIO_REG: RFCU_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (3UL) /*!< CRG_TOP CLK_RADIO_REG: RFCU_ENABLE (Bit 3) */ -#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x8UL) /*!< CRG_TOP CLK_RADIO_REG: RFCU_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Pos (4UL) /*!< CRG_TOP CLK_RADIO_REG: BLE_DIV (Bit 4) */ -#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Msk (0x30UL) /*!< CRG_TOP CLK_RADIO_REG: BLE_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Pos (6UL) /*!< CRG_TOP CLK_RADIO_REG: BLE_LP_RESET (Bit 6) */ -#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Msk (0x40UL) /*!< CRG_TOP CLK_RADIO_REG: BLE_LP_RESET (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Pos (7UL) /*!< CRG_TOP CLK_RADIO_REG: BLE_ENABLE (Bit 7) */ -#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Msk (0x80UL) /*!< CRG_TOP CLK_RADIO_REG: BLE_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Pos (8UL) /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_DIV (Bit 8) */ -#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Msk (0x300UL) /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Pos (11UL) /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_ENABLE (Bit 11) */ -#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Msk (0x800UL) /*!< CRG_TOP CLK_RADIO_REG: FTDF_MAC_ENABLE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_CLK_CTRL_REG ---------------------------- */ -#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL) /*!< CRG_TOP CLK_CTRL_REG: SYS_CLK_SEL (Bit 0) */ -#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL) /*!< CRG_TOP CLK_CTRL_REG: SYS_CLK_SEL (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Pos (2UL) /*!< CRG_TOP CLK_CTRL_REG: XTAL16M_DISABLE (Bit 2) */ -#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Msk (0x4UL) /*!< CRG_TOP CLK_CTRL_REG: XTAL16M_DISABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Pos (3UL) /*!< CRG_TOP CLK_CTRL_REG: XTAL32M_MODE (Bit 3) */ -#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Msk (0x8UL) /*!< CRG_TOP CLK_CTRL_REG: XTAL32M_MODE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos (4UL) /*!< CRG_TOP CLK_CTRL_REG: USB_CLK_SRC (Bit 4) */ -#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk (0x10UL) /*!< CRG_TOP CLK_CTRL_REG: USB_CLK_SRC (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Pos (5UL) /*!< CRG_TOP CLK_CTRL_REG: PLL_DIV2 (Bit 5) */ -#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Msk (0x20UL) /*!< CRG_TOP CLK_CTRL_REG: PLL_DIV2 (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Pos (6UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_XTAL32M_MODE (Bit 6) */ -#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Msk (0x40UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_XTAL32M_MODE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Pos (7UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_SYNC_LEVEL (Bit 7) */ -#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Msk (0x80UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_SYNC_LEVEL (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Pos (8UL) /*!< CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bit 8) */ -#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Msk (0x300UL) /*!< CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Pos (10UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bit 10) */ -#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Msk (0x400UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Pos (12UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bit 12) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Msk (0x1000UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Pos (13UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_RC16M (Bit 13) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Msk (0x2000UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_RC16M (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Pos (14UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_XTAL16M (Bit 14) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Msk (0x4000UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_XTAL16M (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos (15UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_PLL96M (Bit 15) */ -#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk (0x8000UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_PLL96M (Bitfield-Mask: 0x01) */ - -/* ----------------------------- CRG_TOP_CLK_TMR_REG ---------------------------- */ -#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Pos (0UL) /*!< CRG_TOP CLK_TMR_REG: TMR0_DIV (Bit 0) */ -#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk (0x3UL) /*!< CRG_TOP CLK_TMR_REG: TMR0_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Pos (2UL) /*!< CRG_TOP CLK_TMR_REG: TMR0_ENABLE (Bit 2) */ -#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk (0x4UL) /*!< CRG_TOP CLK_TMR_REG: TMR0_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Pos (3UL) /*!< CRG_TOP CLK_TMR_REG: TMR0_CLK_SEL (Bit 3) */ -#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk (0x8UL) /*!< CRG_TOP CLK_TMR_REG: TMR0_CLK_SEL (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Pos (4UL) /*!< CRG_TOP CLK_TMR_REG: TMR1_DIV (Bit 4) */ -#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Msk (0x30UL) /*!< CRG_TOP CLK_TMR_REG: TMR1_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Pos (6UL) /*!< CRG_TOP CLK_TMR_REG: TMR1_ENABLE (Bit 6) */ -#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Msk (0x40UL) /*!< CRG_TOP CLK_TMR_REG: TMR1_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Pos (7UL) /*!< CRG_TOP CLK_TMR_REG: TMR1_CLK_SEL (Bit 7) */ -#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Msk (0x80UL) /*!< CRG_TOP CLK_TMR_REG: TMR1_CLK_SEL (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Pos (8UL) /*!< CRG_TOP CLK_TMR_REG: TMR2_DIV (Bit 8) */ -#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Msk (0x300UL) /*!< CRG_TOP CLK_TMR_REG: TMR2_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Pos (10UL) /*!< CRG_TOP CLK_TMR_REG: TMR2_ENABLE (Bit 10) */ -#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Msk (0x400UL) /*!< CRG_TOP CLK_TMR_REG: TMR2_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Pos (11UL) /*!< CRG_TOP CLK_TMR_REG: TMR2_CLK_SEL (Bit 11) */ -#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Msk (0x800UL) /*!< CRG_TOP CLK_TMR_REG: TMR2_CLK_SEL (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Pos (12UL) /*!< CRG_TOP CLK_TMR_REG: BREATH_ENABLE (Bit 12) */ -#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Msk (0x1000UL) /*!< CRG_TOP CLK_TMR_REG: BREATH_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (13UL) /*!< CRG_TOP CLK_TMR_REG: WAKEUPCT_ENABLE (Bit 13) */ -#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x2000UL) /*!< CRG_TOP CLK_TMR_REG: WAKEUPCT_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Pos (14UL) /*!< CRG_TOP CLK_TMR_REG: P06_TMR1_PWM_MODE (Bit 14) */ -#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Msk (0x4000UL) /*!< CRG_TOP CLK_TMR_REG: P06_TMR1_PWM_MODE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_PMU_CTRL_REG ---------------------------- */ -#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL) /*!< CRG_TOP PMU_CTRL_REG: PERIPH_SLEEP (Bit 0) */ -#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL) /*!< CRG_TOP PMU_CTRL_REG: PERIPH_SLEEP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos (1UL) /*!< CRG_TOP PMU_CTRL_REG: RADIO_SLEEP (Bit 1) */ -#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk (0x2UL) /*!< CRG_TOP PMU_CTRL_REG: RADIO_SLEEP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos (2UL) /*!< CRG_TOP PMU_CTRL_REG: BLE_SLEEP (Bit 2) */ -#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Msk (0x4UL) /*!< CRG_TOP PMU_CTRL_REG: BLE_SLEEP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos (3UL) /*!< CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bit 3) */ -#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Msk (0x8UL) /*!< CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL) /*!< CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bit 4) */ -#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL) /*!< CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL) /*!< CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bit 5) */ -#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL) /*!< CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Pos (6UL) /*!< CRG_TOP PMU_CTRL_REG: OTP_COPY_DIV (Bit 6) */ -#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Msk (0xc0UL) /*!< CRG_TOP PMU_CTRL_REG: OTP_COPY_DIV (Bitfield-Mask: 0x03) */ -#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Pos (8UL) /*!< CRG_TOP PMU_CTRL_REG: RETAIN_RAM (Bit 8) */ -#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Msk (0x1f00UL) /*!< CRG_TOP PMU_CTRL_REG: RETAIN_RAM (Bitfield-Mask: 0x1f) */ -#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos (13UL) /*!< CRG_TOP PMU_CTRL_REG: ENABLE_CLKLESS (Bit 13) */ -#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk (0x2000UL) /*!< CRG_TOP PMU_CTRL_REG: ENABLE_CLKLESS (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (14UL) /*!< CRG_TOP PMU_CTRL_REG: RETAIN_CACHE (Bit 14) */ -#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x4000UL) /*!< CRG_TOP PMU_CTRL_REG: RETAIN_CACHE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Pos (15UL) /*!< CRG_TOP PMU_CTRL_REG: RETAIN_ECCRAM (Bit 15) */ -#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Msk (0x8000UL) /*!< CRG_TOP PMU_CTRL_REG: RETAIN_ECCRAM (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_SYS_CTRL_REG ---------------------------- */ -#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL) /*!< CRG_TOP SYS_CTRL_REG: REMAP_ADR0 (Bit 0) */ -#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL) /*!< CRG_TOP SYS_CTRL_REG: REMAP_ADR0 (Bitfield-Mask: 0x07) */ -#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Pos (3UL) /*!< CRG_TOP SYS_CTRL_REG: REMAP_RAMS (Bit 3) */ -#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Msk (0x18UL) /*!< CRG_TOP SYS_CTRL_REG: REMAP_RAMS (Bitfield-Mask: 0x03) */ -#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Pos (5UL) /*!< CRG_TOP SYS_CTRL_REG: PAD_LATCH_EN (Bit 5) */ -#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Msk (0x20UL) /*!< CRG_TOP SYS_CTRL_REG: PAD_LATCH_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Pos (6UL) /*!< CRG_TOP SYS_CTRL_REG: OTPC_RESET_REQ (Bit 6) */ -#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Msk (0x40UL) /*!< CRG_TOP SYS_CTRL_REG: OTPC_RESET_REQ (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL) /*!< CRG_TOP SYS_CTRL_REG: DEBUGGER_ENABLE (Bit 7) */ -#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL) /*!< CRG_TOP SYS_CTRL_REG: DEBUGGER_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Pos (8UL) /*!< CRG_TOP SYS_CTRL_REG: DRA_OFF (Bit 8) */ -#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Msk (0x100UL) /*!< CRG_TOP SYS_CTRL_REG: DRA_OFF (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos (9UL) /*!< CRG_TOP SYS_CTRL_REG: TIMEOUT_DISABLE (Bit 9) */ -#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk (0x200UL) /*!< CRG_TOP SYS_CTRL_REG: TIMEOUT_DISABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL) /*!< CRG_TOP SYS_CTRL_REG: CACHERAM_MUX (Bit 10) */ -#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL) /*!< CRG_TOP SYS_CTRL_REG: CACHERAM_MUX (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Pos (11UL) /*!< CRG_TOP SYS_CTRL_REG: DEV_PHASE (Bit 11) */ -#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Msk (0x800UL) /*!< CRG_TOP SYS_CTRL_REG: DEV_PHASE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos (12UL) /*!< CRG_TOP SYS_CTRL_REG: QSPI_INIT (Bit 12) */ -#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk (0x1000UL) /*!< CRG_TOP SYS_CTRL_REG: QSPI_INIT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Pos (13UL) /*!< CRG_TOP SYS_CTRL_REG: OTP_COPY (Bit 13) */ -#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Msk (0x2000UL) /*!< CRG_TOP SYS_CTRL_REG: OTP_COPY (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (14UL) /*!< CRG_TOP SYS_CTRL_REG: REMAP_INTVECT (Bit 14) */ -#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x4000UL) /*!< CRG_TOP SYS_CTRL_REG: REMAP_INTVECT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (15UL) /*!< CRG_TOP SYS_CTRL_REG: SW_RESET (Bit 15) */ -#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x8000UL) /*!< CRG_TOP SYS_CTRL_REG: SW_RESET (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_SYS_STAT_REG ---------------------------- */ -#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos (0UL) /*!< CRG_TOP SYS_STAT_REG: RAD_IS_DOWN (Bit 0) */ -#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk (0x1UL) /*!< CRG_TOP SYS_STAT_REG: RAD_IS_DOWN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos (1UL) /*!< CRG_TOP SYS_STAT_REG: RAD_IS_UP (Bit 1) */ -#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk (0x2UL) /*!< CRG_TOP SYS_STAT_REG: RAD_IS_UP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos (2UL) /*!< CRG_TOP SYS_STAT_REG: PER_IS_DOWN (Bit 2) */ -#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL) /*!< CRG_TOP SYS_STAT_REG: PER_IS_DOWN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL) /*!< CRG_TOP SYS_STAT_REG: PER_IS_UP (Bit 3) */ -#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL) /*!< CRG_TOP SYS_STAT_REG: PER_IS_UP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Pos (4UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bit 4) */ -#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Msk (0x10UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (5UL) /*!< CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bit 5) */ -#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x20UL) /*!< CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Pos (6UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bit 6) */ -#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Msk (0x40UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Pos (7UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bit 7) */ -#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Msk (0x80UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Pos (8UL) /*!< CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bit 8) */ -#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Msk (0x100UL) /*!< CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Pos (9UL) /*!< CRG_TOP SYS_STAT_REG: BLE_IS_UP (Bit 9) */ -#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Msk (0x200UL) /*!< CRG_TOP SYS_STAT_REG: BLE_IS_UP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Pos (10UL) /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_DOWN (Bit 10) */ -#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Msk (0x400UL) /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_DOWN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Pos (11UL) /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_UP (Bit 11) */ -#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Msk (0x800UL) /*!< CRG_TOP SYS_STAT_REG: FTDF_IS_UP (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_TRIM_CTRL_REG --------------------------- */ -#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Pos (0UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_COUNT_N (Bit 0) */ -#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Msk (0x3fUL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_COUNT_N (Bitfield-Mask: 0x3f) */ -#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos (6UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bit 6) */ -#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk (0xc0UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bitfield-Mask: 0x03) */ -#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos (8UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bit 8) */ -#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk (0x3f00UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bitfield-Mask: 0x3f) */ - -/* ----------------------------- CRG_TOP_CLK_32K_REG ---------------------------- */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Pos (0UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_ENABLE (Bit 0) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Msk (0x1UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Pos (1UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_RBIAS (Bit 1) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Msk (0x6UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_RBIAS (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Pos (3UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_CUR (Bit 3) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Msk (0x78UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_CUR (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Pos (7UL) /*!< CRG_TOP CLK_32K_REG: RC32K_ENABLE (Bit 7) */ -#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Msk (0x80UL) /*!< CRG_TOP CLK_32K_REG: RC32K_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Pos (8UL) /*!< CRG_TOP CLK_32K_REG: RC32K_TRIM (Bit 8) */ -#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Msk (0xf00UL) /*!< CRG_TOP CLK_32K_REG: RC32K_TRIM (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Pos (12UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bit 12) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x1000UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Pos (13UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bit 13) */ -#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Msk (0x2000UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- CRG_TOP_CLK_16M_REG ---------------------------- */ -#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Pos (0UL) /*!< CRG_TOP CLK_16M_REG: RC16M_ENABLE (Bit 0) */ -#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk (0x1UL) /*!< CRG_TOP CLK_16M_REG: RC16M_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Pos (1UL) /*!< CRG_TOP CLK_16M_REG: RC16M_TRIM (Bit 1) */ -#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Msk (0x1eUL) /*!< CRG_TOP CLK_16M_REG: RC16M_TRIM (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Pos (5UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_CUR_SET (Bit 5) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Msk (0xe0UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_CUR_SET (Bitfield-Mask: 0x07) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Pos (8UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_MAX_CURRENT (Bit 8) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Msk (0x100UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_MAX_CURRENT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Pos (9UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_EXT_CLK_ENABLE (Bit 9) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Msk (0x200UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_EXT_CLK_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Pos (10UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_AMP_TRIM (Bit 10) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Msk (0x1c00UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_AMP_TRIM (Bitfield-Mask: 0x07) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Pos (13UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_SPIKE_FLT_BYPASS (Bit 13) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Msk (0x2000UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_SPIKE_FLT_BYPASS (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Pos (14UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_HPASS_FLT_EN (Bit 14) */ -#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Msk (0x4000UL) /*!< CRG_TOP CLK_16M_REG: XTAL16_HPASS_FLT_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Pos (15UL) /*!< CRG_TOP CLK_16M_REG: RC16M_STARTUP_DISABLE (Bit 15) */ -#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Msk (0x8000UL) /*!< CRG_TOP CLK_16M_REG: RC16M_STARTUP_DISABLE (Bitfield-Mask: 0x01) */ - -/* --------------------------- CRG_TOP_CLK_RCX20K_REG --------------------------- */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Pos (0UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_TRIM (Bit 0) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Msk (0xfUL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_TRIM (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Pos (4UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_NTC (Bit 4) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Msk (0xf0UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_NTC (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Pos (8UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_BIAS (Bit 8) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Msk (0x300UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_BIAS (Bitfield-Mask: 0x03) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Pos (10UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_LOWF (Bit 10) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Msk (0x400UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_LOWF (Bitfield-Mask: 0x01) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Pos (11UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_ENABLE (Bit 11) */ -#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Msk (0x800UL) /*!< CRG_TOP CLK_RCX20K_REG: RCX20K_ENABLE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- CRG_TOP_BANDGAP_REG ---------------------------- */ -#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos (0UL) /*!< CRG_TOP BANDGAP_REG: BGR_TRIM (Bit 0) */ -#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk (0x1fUL) /*!< CRG_TOP BANDGAP_REG: BGR_TRIM (Bitfield-Mask: 0x1f) */ -#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos (5UL) /*!< CRG_TOP BANDGAP_REG: BGR_ITRIM (Bit 5) */ -#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0x3e0UL) /*!< CRG_TOP BANDGAP_REG: BGR_ITRIM (Bitfield-Mask: 0x1f) */ -#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Pos (10UL) /*!< CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bit 10) */ -#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Msk (0x3c00UL) /*!< CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Pos (14UL) /*!< CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bit 14) */ -#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Msk (0x4000UL) /*!< CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bitfield-Mask: 0x01) */ - -/* --------------------------- CRG_TOP_ANA_STATUS_REG --------------------------- */ -#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos (0UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_RADIO_OK (Bit 0) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk (0x1UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_RADIO_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Pos (1UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VBAT_OK (Bit 1) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Msk (0x2UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VBAT_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos (2UL) /*!< CRG_TOP ANA_STATUS_REG: VBUS_AVAILABLE (Bit 2) */ -#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk (0x4UL) /*!< CRG_TOP ANA_STATUS_REG: VBUS_AVAILABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Pos (3UL) /*!< CRG_TOP ANA_STATUS_REG: NEWBAT (Bit 3) */ -#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Msk (0x8UL) /*!< CRG_TOP ANA_STATUS_REG: NEWBAT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Pos (4UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_VBAT_OK (Bit 4) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Msk (0x10UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_VBAT_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Pos (5UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_USB_OK (Bit 5) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Msk (0x20UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_USB_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (6UL) /*!< CRG_TOP ANA_STATUS_REG: BANDGAP_OK (Bit 6) */ -#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x40UL) /*!< CRG_TOP ANA_STATUS_REG: BANDGAP_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Pos (7UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VDD_HIGH (Bit 7) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Msk (0x80UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VDD_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (8UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_CORE_OK (Bit 8) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x100UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_CORE_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Pos (9UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_PA_OK (Bit 9) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Msk (0x200UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_PA_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Pos (10UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_FLASH_OK (Bit 10) */ -#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Msk (0x400UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos (11UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_HIGH (Bit 11) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk (0x800UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos (12UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_LOW (Bit 12) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk (0x1000UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_VBUS_LOW (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Pos (13UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_V33_HIGH (Bit 13) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Msk (0x2000UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_V33_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Pos (14UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_FLASH_HIGH (Bit 14) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Msk (0x4000UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_FLASH_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Pos (15UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_PA_HIGH (Bit 15) */ -#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Msk (0x8000UL) /*!< CRG_TOP ANA_STATUS_REG: COMP_1V8_PA_HIGH (Bitfield-Mask: 0x01) */ - -/* ------------------------- CRG_TOP_STARTUP_STATUS_REG ------------------------- */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Pos (0UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bit 0) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Msk (0x1UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Pos (1UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bit 1) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Msk (0x2UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Pos (2UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bit 2) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Msk (0x4UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Pos (3UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LOD_SUPPLY_USB_OK (Bit 3) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Msk (0x8UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LOD_SUPPLY_USB_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Pos (4UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_CORE_OK (Bit 4) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Msk (0x10UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_CORE_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Pos (5UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_PA_OK (Bit 5) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Msk (0x20UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_PA_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Pos (6UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VDD_HIGH (Bit 6) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Msk (0x40UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VDD_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Pos (7UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_V33_HIGH (Bit 7) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Msk (0x80UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_V33_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Pos (8UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_HIGH (Bit 8) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Msk (0x100UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Pos (9UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_LOW (Bit 9) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Msk (0x200UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_LOW (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Pos (10UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_PA_HIGH (Bit 10) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Msk (0x400UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_PA_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Pos (11UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bit 11) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Msk (0x800UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Pos (12UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bit 12) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Msk (0x1000UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Pos (13UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bit 13) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Msk (0xe000UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bitfield-Mask: 0x07) */ - -/* -------------------------- CRG_TOP_VBUS_IRQ_MASK_REG ------------------------- */ -#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos (0UL) /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_FALL (Bit 0) */ -#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk (0x1UL) /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_FALL (Bitfield-Mask: 0x01) */ -#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos (1UL) /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_RISE (Bit 1) */ -#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk (0x2UL) /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_RISE (Bitfield-Mask: 0x01) */ - -/* ------------------------- CRG_TOP_VBUS_IRQ_CLEAR_REG ------------------------- */ -#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos (0UL) /*!< CRG_TOP VBUS_IRQ_CLEAR_REG: VBUS_IRQ_CLEAR (Bit 0) */ -#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk (0xffffUL) /*!< CRG_TOP VBUS_IRQ_CLEAR_REG: VBUS_IRQ_CLEAR (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- CRG_TOP_BOD_CTRL_REG ---------------------------- */ -#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Pos (0UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bit 0) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Msk (0x3UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bitfield-Mask: 0x03) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Pos (2UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bit 2) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Msk (0xcUL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bitfield-Mask: 0x03) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Pos (4UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bit 4) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Msk (0x30UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bitfield-Mask: 0x03) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Pos (6UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bit 6) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Msk (0xc0UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bitfield-Mask: 0x03) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Pos (8UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_LVL (Bit 8) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Msk (0x700UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_LVL (Bitfield-Mask: 0x07) */ - -/* ---------------------------- CRG_TOP_BOD_CTRL2_REG --------------------------- */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Pos (0UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_RESET_EN (Bit 0) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Msk (0x1UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_RESET_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Pos (1UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_VDD_EN (Bit 1) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Msk (0x2UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_VDD_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Pos (2UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_V33_EN (Bit 2) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Msk (0x4UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_V33_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Pos (3UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_PA_EN (Bit 3) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Msk (0x8UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_PA_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Pos (4UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_FLASH_EN (Bit 4) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Msk (0x10UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_FLASH_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Pos (5UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bit 5) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Msk (0x20UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Pos (6UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bit 6) */ -#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Msk (0x40UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bitfield-Mask: 0x01) */ - -/* --------------------------- CRG_TOP_BOD_STATUS_REG --------------------------- */ -#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Pos (0UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_VDD_LOW (Bit 0) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Msk (0x1UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_VDD_LOW (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Pos (1UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_PA_LOW (Bit 1) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Msk (0x2UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_PA_LOW (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Pos (2UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_FLASH_LOW (Bit 2) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Msk (0x4UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_1V8_FLASH_LOW (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Pos (3UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_V33_LOW (Bit 3) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Msk (0x8UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_V33_LOW (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Pos (4UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bit 4) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Msk (0x10UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bitfield-Mask: 0x01) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Pos (5UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bit 5) */ -#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Msk (0x20UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_LDO_CTRL1_REG --------------------------- */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Pos (0UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_CURLIM (Bit 0) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Msk (0x3UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_CURLIM (Bitfield-Mask: 0x03) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Pos (2UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_VBAT_RET_LEVEL (Bit 2) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Msk (0xcUL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_VBAT_RET_LEVEL (Bitfield-Mask: 0x03) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Pos (4UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_VBAT_LEVEL (Bit 4) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Msk (0x30UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_VBAT_LEVEL (Bitfield-Mask: 0x03) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Pos (6UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_USB_LEVEL (Bit 6) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Msk (0xc0UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_USB_LEVEL (Bitfield-Mask: 0x03) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Pos (8UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_SETVDD (Bit 8) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Msk (0x700UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_SETVDD (Bitfield-Mask: 0x07) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Pos (11UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_SETVDD (Bit 11) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Msk (0x3800UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_SETVDD (Bitfield-Mask: 0x07) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Pos (14UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_ENABLE (Bit 14) */ -#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Msk (0x4000UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_RADIO_ENABLE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_LDO_CTRL2_REG --------------------------- */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Pos (0UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V2_ON (Bit 0) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Msk (0x1UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V2_ON (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Pos (1UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_3V3_ON (Bit 1) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Msk (0x2UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_3V3_ON (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Pos (2UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_ON (Bit 2) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Msk (0x4UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_ON (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Pos (3UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_ON (Bit 3) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Msk (0x8UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_ON (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Pos (4UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_VBAT_RET_DISABLE (Bit 4) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Msk (0x10UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_VBAT_RET_DISABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Pos (5UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_RET_DISABLE (Bit 5) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Msk (0x20UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_RET_DISABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Pos (6UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_RET_DISABLE (Bit 6) */ -#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Msk (0x40UL) /*!< CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_RET_DISABLE (Bitfield-Mask: 0x01) */ - -/* --------------------------- CRG_TOP_SLEEP_TIMER_REG -------------------------- */ -#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Pos (0UL) /*!< CRG_TOP SLEEP_TIMER_REG: SLEEP_TIMER (Bit 0) */ -#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Msk (0xffffUL) /*!< CRG_TOP SLEEP_TIMER_REG: SLEEP_TIMER (Bitfield-Mask: 0xffff) */ - -/* --------------------------- CRG_TOP_POWER_CTRL_REG --------------------------- */ -#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Pos (0UL) /*!< CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bit 0) */ -#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Msk (0x7UL) /*!< CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bitfield-Mask: 0x07) */ - -/* -------------------------- CRG_TOP_POR_VBAT_CTRL_REG ------------------------- */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos (0UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bit 0) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk (0xfUL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos (4UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bit 4) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk (0xf0UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos (8UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bit 8) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk (0xf00UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos (12UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bit 12) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk (0x1000UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos (13UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bit 13) */ -#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk (0x2000UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bitfield-Mask: 0x01) */ - -/* -------------------------- CRG_TOP_XTALRDY_CTRL_REG -------------------------- */ -#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos (0UL) /*!< CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bit 0) */ -#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk (0xffUL) /*!< CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bitfield-Mask: 0xff) */ - -/* -------------------------- CRG_TOP_XTALRDY_STAT_REG -------------------------- */ -#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Pos (0UL) /*!< CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bit 0) */ -#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Msk (0xffUL) /*!< CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bitfield-Mask: 0xff) */ - -/* ---------------------------- CRG_TOP_LDO_CTRL3_REG --------------------------- */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Pos (0UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bit 0) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Msk (0x1UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Pos (1UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bit 1) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Msk (0x2UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Pos (2UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bit 2) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Msk (0x4UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Pos (3UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bit 3) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Msk (0x8UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Pos (4UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bit 4) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Msk (0x10UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos (5UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bit 5) */ -#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk (0x20UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bitfield-Mask: 0x01) */ - -/* -------------------------- CRG_TOP_XTAL16M_CTRL_REG -------------------------- */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_FREQ_TRIM_SW2_AMP_Pos (0UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_FREQ_TRIM_SW2_AMP (Bit 0) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_FREQ_TRIM_SW2_AMP_Msk (0x7UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_FREQ_TRIM_SW2_AMP (Bitfield-Mask: 0x07) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_AMP_REG_SIG_SEL_Pos (3UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_AMP_REG_SIG_SEL (Bit 3) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_AMP_REG_SIG_SEL_Msk (0x8UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_AMP_REG_SIG_SEL (Bitfield-Mask: 0x01) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_TST_AON_Pos (4UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_TST_AON (Bit 4) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_TST_AON_Msk (0x30UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_TST_AON (Bitfield-Mask: 0x03) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_SH_OVERRULE_Pos (6UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_SH_OVERRULE (Bit 6) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_SH_OVERRULE_Msk (0xc0UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_SH_OVERRULE (Bitfield-Mask: 0x03) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_ENABLE_ZERO_Pos (8UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_ENABLE_ZERO (Bit 8) */ -#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_ENABLE_ZERO_Msk (0x100UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_ENABLE_ZERO (Bitfield-Mask: 0x01) */ - -/* -------------------------- CRG_TOP_XTAL16M_START_REG ------------------------- */ -#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos (0UL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bit 0) */ -#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk (0xffUL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bitfield-Mask: 0xff) */ -#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Pos (8UL) /*!< CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bit 8) */ -#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Msk (0x700UL) /*!< CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bitfield-Mask: 0x07) */ - -/* -------------------------- CRG_TOP_XTAL16M_RAMP_REG -------------------------- */ -#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Pos (0UL) /*!< CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bit 0) */ -#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Msk (0xffUL) /*!< CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bitfield-Mask: 0xff) */ -#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Pos (8UL) /*!< CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bit 8) */ -#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Msk (0x700UL) /*!< CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bitfield-Mask: 0x07) */ - -/* ------------------------- CRG_TOP_XTAL16M_TRSTAT_REG ------------------------- */ -#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Pos (0UL) /*!< CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bit 0) */ -#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Msk (0x7fffUL) /*!< CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bitfield-Mask: 0x7fff) */ - -/* --------------------------- CRG_TOP_RESET_STAT_REG --------------------------- */ -#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL) /*!< CRG_TOP RESET_STAT_REG: PORESET_STAT (Bit 0) */ -#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL) /*!< CRG_TOP RESET_STAT_REG: PORESET_STAT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL) /*!< CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bit 1) */ -#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL) /*!< CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL) /*!< CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bit 2) */ -#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL) /*!< CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL) /*!< CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bit 3) */ -#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL) /*!< CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL) /*!< CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bit 4) */ -#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL) /*!< CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bitfield-Mask: 0x01) */ - -/* --------------------------- CRG_TOP_FORCE_SLEEP_REG -------------------------- */ -#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Pos (0UL) /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bit 0) */ -#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Msk (0x1UL) /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bitfield-Mask: 0x01) */ -#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Pos (1UL) /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_BLE_SLEEP (Bit 1) */ -#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Msk (0x2UL) /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_BLE_SLEEP (Bitfield-Mask: 0x01) */ - -/* -------------------------- CRG_TOP_LDOS_DISABLE_REG -------------------------- */ -#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Pos (0UL) /*!< CRG_TOP LDOS_DISABLE_REG: LDOS_DISABLE (Bit 0) */ -#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Msk (0x1UL) /*!< CRG_TOP LDOS_DISABLE_REG: LDOS_DISABLE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- CRG_TOP_AON_SPARE_REG --------------------------- */ -#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Pos (0UL) /*!< CRG_TOP AON_SPARE_REG: OSC16_HOLD_AMP_REG (Bit 0) */ -#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Msk (0x1UL) /*!< CRG_TOP AON_SPARE_REG: OSC16_HOLD_AMP_REG (Bitfield-Mask: 0x01) */ -#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Pos (1UL) /*!< CRG_TOP AON_SPARE_REG: OSC16_SH_DISABLE (Bit 1) */ -#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Msk (0x2UL) /*!< CRG_TOP AON_SPARE_REG: OSC16_SH_DISABLE (Bitfield-Mask: 0x01) */ -#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Pos (2UL) /*!< CRG_TOP AON_SPARE_REG: EN_BATSYS_RET (Bit 2) */ -#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Msk (0x4UL) /*!< CRG_TOP AON_SPARE_REG: EN_BATSYS_RET (Bitfield-Mask: 0x01) */ -#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Pos (3UL) /*!< CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bit 3) */ -#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Msk (0x8UL) /*!< CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bitfield-Mask: 0x01) */ - -/* --------------------------- CRG_TOP_SECURE_BOOT_REG -------------------------- */ -#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (0UL) /*!< CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bit 0) */ -#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x1UL) /*!< CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos (1UL) /*!< CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bit 1) */ -#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk (0x2UL) /*!< CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bitfield-Mask: 0x01) */ - -/* ------------------------- CRG_TOP_PMU_RESET_RAIL_REG ------------------------- */ -#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Pos (0UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bit 0) */ -#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Msk (0x1UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Pos (1UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bit 1) */ -#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Msk (0x2UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01) */ -#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Pos (2UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bit 2) */ -#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Msk (0x4UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01) */ - -/* ------------------------- CRG_TOP_DISCHARGE_RAIL_REG ------------------------- */ -#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos (0UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bit 0) */ -#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk (0x1UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01) */ -#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos (1UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bit 1) */ -#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk (0x2UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01) */ -#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos (2UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bit 2) */ -#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk (0x4UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'DCDC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- DCDC_DCDC_CTRL_0_REG ---------------------------- */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Pos (0UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_MODE (Bit 0) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Msk (0x3UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_MODE (Bitfield-Mask: 0x03) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Pos (2UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_FW_ENABLE (Bit 2) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Msk (0x4UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_FW_ENABLE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Pos (3UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_PRIORITY (Bit 3) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Msk (0x7f8UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_PRIORITY (Bitfield-Mask: 0xff) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Pos (11UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_IDLE_CLK_DIV (Bit 11) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Msk (0x1800UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_IDLE_CLK_DIV (Bitfield-Mask: 0x03) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Pos (13UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_BROWNOUT_LV_MODE (Bit 13) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Msk (0x2000UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_BROWNOUT_LV_MODE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Pos (14UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_FAST_STARTUP (Bit 14) */ -#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Msk (0x4000UL) /*!< DCDC DCDC_CTRL_0_REG: DCDC_FAST_STARTUP (Bitfield-Mask: 0x01) */ - -/* ---------------------------- DCDC_DCDC_CTRL_1_REG ---------------------------- */ -#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Pos (0UL) /*!< DCDC DCDC_CTRL_1_REG: DCDC_TIMEOUT (Bit 0) */ -#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Msk (0x1fUL) /*!< DCDC DCDC_CTRL_1_REG: DCDC_TIMEOUT (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Pos (5UL) /*!< DCDC DCDC_CTRL_1_REG: DCDC_GLOBAL_MAX_IDLE_TIME (Bit 5) */ -#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Msk (0x7e0UL) /*!< DCDC DCDC_CTRL_1_REG: DCDC_GLOBAL_MAX_IDLE_TIME (Bitfield-Mask: 0x3f) */ -#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Pos (11UL) /*!< DCDC DCDC_CTRL_1_REG: DCDC_STARTUP_DELAY (Bit 11) */ -#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Msk (0xf800UL) /*!< DCDC DCDC_CTRL_1_REG: DCDC_STARTUP_DELAY (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- DCDC_DCDC_CTRL_2_REG ---------------------------- */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Pos (0UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_HSGND_TRIM (Bit 0) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Msk (0x7UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_HSGND_TRIM (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Pos (3UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_LSSUP_TRIM (Bit 3) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Msk (0x38UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_LSSUP_TRIM (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Pos (6UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_TUNE (Bit 6) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Msk (0xc0UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_TUNE (Bitfield-Mask: 0x03) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Pos (8UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_RES (Bit 8) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Msk (0xf00UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_RES (Bitfield-Mask: 0x0f) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos (12UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_TRIG (Bit 12) */ -#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk (0xf000UL) /*!< DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_TRIG (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- DCDC_DCDC_V14_0_REG ---------------------------- */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Pos (0UL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MIN (Bit 0) */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Msk (0x1fUL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos (5UL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MAX_HV (Bit 5) */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk (0x3e0UL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Pos (10UL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_VOLTAGE (Bit 10) */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Msk (0x7c00UL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_VOLTAGE (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Pos (15UL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_FAST_RAMPING (Bit 15) */ -#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Msk (0x8000UL) /*!< DCDC DCDC_V14_0_REG: DCDC_V14_FAST_RAMPING (Bitfield-Mask: 0x01) */ - -/* ----------------------------- DCDC_DCDC_V14_1_REG ---------------------------- */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Pos (0UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_MIN (Bit 0) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Msk (0x1fUL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Pos (5UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_HYST (Bit 5) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Msk (0x3e0UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_HYST (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos (10UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_CUR_LIM_MAX_LV (Bit 10) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk (0x3c00UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Pos (14UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_LV (Bit 14) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Msk (0x4000UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_LV (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Pos (15UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_HV (Bit 15) */ -#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Msk (0x8000UL) /*!< DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_HV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- DCDC_DCDC_V18_0_REG ---------------------------- */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Pos (0UL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MIN (Bit 0) */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Msk (0x1fUL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos (5UL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MAX_HV (Bit 5) */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk (0x3e0UL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Pos (10UL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_VOLTAGE (Bit 10) */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Msk (0x7c00UL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_VOLTAGE (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Pos (15UL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_FAST_RAMPING (Bit 15) */ -#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Msk (0x8000UL) /*!< DCDC DCDC_V18_0_REG: DCDC_V18_FAST_RAMPING (Bitfield-Mask: 0x01) */ - -/* ----------------------------- DCDC_DCDC_V18_1_REG ---------------------------- */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Pos (0UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_MIN (Bit 0) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Msk (0x1fUL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Pos (5UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_HYST (Bit 5) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Msk (0x3e0UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_HYST (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos (10UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_CUR_LIM_MAX_LV (Bit 10) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk (0x3c00UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Pos (14UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_LV (Bit 14) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Msk (0x4000UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_LV (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Pos (15UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_HV (Bit 15) */ -#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Msk (0x8000UL) /*!< DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_HV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- DCDC_DCDC_VDD_0_REG ---------------------------- */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Pos (0UL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MIN (Bit 0) */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Msk (0x1fUL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos (5UL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MAX_HV (Bit 5) */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk (0x3e0UL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Pos (10UL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_VOLTAGE (Bit 10) */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Msk (0x7c00UL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_VOLTAGE (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Pos (15UL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_FAST_RAMPING (Bit 15) */ -#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Msk (0x8000UL) /*!< DCDC DCDC_VDD_0_REG: DCDC_VDD_FAST_RAMPING (Bitfield-Mask: 0x01) */ - -/* ----------------------------- DCDC_DCDC_VDD_1_REG ---------------------------- */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Pos (0UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_MIN (Bit 0) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Msk (0x1fUL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Pos (5UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_HYST (Bit 5) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Msk (0x3e0UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_HYST (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos (10UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_CUR_LIM_MAX_LV (Bit 10) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk (0x3c00UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Pos (14UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_LV (Bit 14) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Msk (0x4000UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_LV (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Pos (15UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_HV (Bit 15) */ -#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Msk (0x8000UL) /*!< DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_HV (Bitfield-Mask: 0x01) */ - -/* ---------------------------- DCDC_DCDC_V18P_0_REG ---------------------------- */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Pos (0UL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MIN (Bit 0) */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Msk (0x1fUL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos (5UL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MAX_HV (Bit 5) */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk (0x3e0UL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Pos (10UL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_VOLTAGE (Bit 10) */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Msk (0x7c00UL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_VOLTAGE (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Pos (15UL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_FAST_RAMPING (Bit 15) */ -#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Msk (0x8000UL) /*!< DCDC DCDC_V18P_0_REG: DCDC_V18P_FAST_RAMPING (Bitfield-Mask: 0x01) */ - -/* ---------------------------- DCDC_DCDC_V18P_1_REG ---------------------------- */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Pos (0UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_MIN (Bit 0) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Msk (0x1fUL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_MIN (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Pos (5UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_HYST (Bit 5) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Msk (0x3e0UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_HYST (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos (10UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_CUR_LIM_MAX_LV (Bit 10) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk (0x3c00UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Pos (14UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_LV (Bit 14) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Msk (0x4000UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_LV (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Pos (15UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_HV (Bit 15) */ -#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Msk (0x8000UL) /*!< DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_HV (Bitfield-Mask: 0x01) */ - -/* ----------------------------- DCDC_DCDC_RET_0_REG ---------------------------- */ -#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Pos (0UL) /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_CUR_LIM_RET (Bit 0) */ -#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Msk (0x1fUL) /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_CUR_LIM_RET (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Pos (5UL) /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_RET_CYCLES (Bit 5) */ -#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Msk (0xe0UL) /*!< DCDC DCDC_RET_0_REG: DCDC_VDD_RET_CYCLES (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Pos (8UL) /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_CUR_LIM_RET (Bit 8) */ -#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Msk (0x1f00UL) /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_CUR_LIM_RET (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Pos (13UL) /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_RET_CYCLES (Bit 13) */ -#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Msk (0xe000UL) /*!< DCDC DCDC_RET_0_REG: DCDC_V18P_RET_CYCLES (Bitfield-Mask: 0x07) */ - -/* ----------------------------- DCDC_DCDC_RET_1_REG ---------------------------- */ -#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Pos (0UL) /*!< DCDC DCDC_RET_1_REG: DCDC_V14_CUR_LIM_RET (Bit 0) */ -#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Msk (0x1fUL) /*!< DCDC DCDC_RET_1_REG: DCDC_V14_CUR_LIM_RET (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Pos (5UL) /*!< DCDC DCDC_RET_1_REG: DCDC_V14_RET_CYCLES (Bit 5) */ -#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Msk (0xe0UL) /*!< DCDC DCDC_RET_1_REG: DCDC_V14_RET_CYCLES (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Pos (8UL) /*!< DCDC DCDC_RET_1_REG: DCDC_V18_CUR_LIM_RET (Bit 8) */ -#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Msk (0x1f00UL) /*!< DCDC DCDC_RET_1_REG: DCDC_V18_CUR_LIM_RET (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Pos (13UL) /*!< DCDC DCDC_RET_1_REG: DCDC_V18_RET_CYCLES (Bit 13) */ -#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Msk (0xe000UL) /*!< DCDC DCDC_RET_1_REG: DCDC_V18_RET_CYCLES (Bitfield-Mask: 0x07) */ - -/* ----------------------------- DCDC_DCDC_TRIM_REG ----------------------------- */ -#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Pos (0UL) /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_TRIM (Bit 0) */ -#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Msk (0x3fUL) /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_TRIM (Bitfield-Mask: 0x3f) */ -#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Pos (6UL) /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_MAN_TRIM (Bit 6) */ -#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Msk (0x40UL) /*!< DCDC DCDC_TRIM_REG: DCDC_N_COMP_MAN_TRIM (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Pos (7UL) /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_TRIM (Bit 7) */ -#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Msk (0x1f80UL) /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_TRIM (Bitfield-Mask: 0x3f) */ -#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Pos (13UL) /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_MAN_TRIM (Bit 13) */ -#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Msk (0x2000UL) /*!< DCDC DCDC_TRIM_REG: DCDC_P_COMP_MAN_TRIM (Bitfield-Mask: 0x01) */ - -/* ---------------------------- DCDC_DCDC_TEST_0_REG ---------------------------- */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Pos (0UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_PSW (Bit 0) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Msk (0x1UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_PSW (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Pos (1UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_NSW (Bit 1) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Msk (0x2UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_NSW (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Pos (2UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_FW (Bit 2) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Msk (0x4UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_FW (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Pos (3UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V14 (Bit 3) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Msk (0x8UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V14 (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Pos (4UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18 (Bit 4) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Msk (0x10UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18 (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Pos (5UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_VDD (Bit 5) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Msk (0x20UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_VDD (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Pos (6UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18P (Bit 6) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Msk (0x40UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18P (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Pos (7UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_IDLE (Bit 7) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Msk (0x80UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_IDLE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Pos (8UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_ANA_TEST (Bit 8) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Msk (0x700UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_ANA_TEST (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Pos (11UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_OUTPUT_MONITOR (Bit 11) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Msk (0x3800UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_OUTPUT_MONITOR (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Pos (14UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_CURRENT (Bit 14) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Msk (0x4000UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_CURRENT (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Pos (15UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_COMP_CLK (Bit 15) */ -#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Msk (0x8000UL) /*!< DCDC DCDC_TEST_0_REG: DCDC_FORCE_COMP_CLK (Bitfield-Mask: 0x01) */ - -/* ---------------------------- DCDC_DCDC_TEST_1_REG ---------------------------- */ -#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Pos (0UL) /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_REG (Bit 0) */ -#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Msk (0xfUL) /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_REG (Bitfield-Mask: 0x0f) */ -#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Pos (4UL) /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_CURRENT (Bit 4) */ -#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Msk (0x1f0UL) /*!< DCDC DCDC_TEST_1_REG: DCDC_TEST_CURRENT (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Pos (9UL) /*!< DCDC DCDC_TEST_1_REG: DCDC_COMP_CLK (Bit 9) */ -#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Msk (0x1e00UL) /*!< DCDC DCDC_TEST_1_REG: DCDC_COMP_CLK (Bitfield-Mask: 0x0f) */ - -/* --------------------------- DCDC_DCDC_STATUS_0_REG --------------------------- */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Pos (0UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_0 (Bit 0) */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Msk (0x7UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_0 (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Pos (3UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_1 (Bit 3) */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Msk (0x38UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_1 (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Pos (6UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_2 (Bit 6) */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Msk (0x1c0UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_2 (Bitfield-Mask: 0x07) */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Pos (9UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_3 (Bit 9) */ -#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Msk (0xe00UL) /*!< DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_3 (Bitfield-Mask: 0x07) */ - -/* --------------------------- DCDC_DCDC_STATUS_1_REG --------------------------- */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Pos (0UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_NOK (Bit 0) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Msk (0x1UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_NOK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Pos (1UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_NOK (Bit 1) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Msk (0x2UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_NOK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Pos (2UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_NOK (Bit 2) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Msk (0x4UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_NOK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Pos (3UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_NOK (Bit 3) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Msk (0x8UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_NOK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Pos (4UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_OK (Bit 4) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Msk (0x10UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_OK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Pos (5UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_OK (Bit 5) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Msk (0x20UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_OK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Pos (6UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_OK (Bit 6) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Msk (0x40UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_OK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Pos (7UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_OK (Bit 7) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Msk (0x80UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_OK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Pos (8UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_AVAILABLE (Bit 8) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Msk (0x100UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V14_AVAILABLE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Pos (9UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_AVAILABLE (Bit 9) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Msk (0x200UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18_AVAILABLE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Pos (10UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_AVAILABLE (Bit 10) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Msk (0x400UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_VDD_AVAILABLE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Pos (11UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_AVAILABLE (Bit 11) */ -#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Msk (0x800UL) /*!< DCDC DCDC_STATUS_1_REG: DCDC_V18P_AVAILABLE (Bitfield-Mask: 0x01) */ - -/* --------------------------- DCDC_DCDC_STATUS_2_REG --------------------------- */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Pos (0UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP (Bit 0) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Msk (0x1UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Pos (1UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP (Bit 1) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Msk (0x2UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Pos (2UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_N (Bit 2) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Msk (0x4UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_N (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Pos (3UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_P (Bit 3) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Msk (0x8UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_P (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Pos (4UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_N (Bit 4) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Msk (0x10UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_N (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Pos (5UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_P (Bit 5) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Msk (0x20UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_P (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Pos (6UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_PSW_STATE (Bit 6) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Msk (0x40UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_PSW_STATE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Pos (7UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_NSW_STATE (Bit 7) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Msk (0x80UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_NSW_STATE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Pos (8UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_V14_SW_STATE (Bit 8) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Msk (0x100UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_V14_SW_STATE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Pos (9UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18_SW_STATE (Bit 9) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Msk (0x200UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18_SW_STATE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Pos (10UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_VDD_SW_STATE (Bit 10) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Msk (0x400UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_VDD_SW_STATE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Pos (11UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18P_SW_STATE (Bit 11) */ -#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Msk (0x800UL) /*!< DCDC DCDC_STATUS_2_REG: DCDC_V18P_SW_STATE (Bitfield-Mask: 0x01) */ - -/* --------------------------- DCDC_DCDC_STATUS_3_REG --------------------------- */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Pos (0UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_VDD (Bit 0) */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Msk (0x1fUL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_VDD (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Pos (5UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_V18P (Bit 5) */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Msk (0x3e0UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_V18P (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Pos (10UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bit 10) */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Msk (0x400UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Pos (11UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bit 11) */ -#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Msk (0x800UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bitfield-Mask: 0x01) */ - -/* --------------------------- DCDC_DCDC_STATUS_4_REG --------------------------- */ -#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Pos (0UL) /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V14 (Bit 0) */ -#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Msk (0x1fUL) /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V14 (Bitfield-Mask: 0x1f) */ -#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Pos (5UL) /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V18 (Bit 5) */ -#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Msk (0x3e0UL) /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V18 (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- DCDC_DCDC_TRIM_0_REG ---------------------------- */ -#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Pos (0UL) /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_N (Bit 0) */ -#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Msk (0x3fUL) /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_N (Bitfield-Mask: 0x3f) */ -#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Pos (6UL) /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_P (Bit 6) */ -#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Msk (0xfc0UL) /*!< DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_P (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- DCDC_DCDC_TRIM_1_REG ---------------------------- */ -#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Pos (0UL) /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_N (Bit 0) */ -#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Msk (0x3fUL) /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_N (Bitfield-Mask: 0x3f) */ -#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Pos (6UL) /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_P (Bit 6) */ -#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Msk (0xfc0UL) /*!< DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_P (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- DCDC_DCDC_TRIM_2_REG ---------------------------- */ -#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Pos (0UL) /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_N (Bit 0) */ -#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Msk (0x3fUL) /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_N (Bitfield-Mask: 0x3f) */ -#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Pos (6UL) /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_P (Bit 6) */ -#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Msk (0xfc0UL) /*!< DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_P (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- DCDC_DCDC_TRIM_3_REG ---------------------------- */ -#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Pos (0UL) /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_N (Bit 0) */ -#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Msk (0x3fUL) /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_N (Bitfield-Mask: 0x3f) */ -#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Pos (6UL) /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_P (Bit 6) */ -#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Msk (0xfc0UL) /*!< DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_P (Bitfield-Mask: 0x3f) */ - -/* -------------------------- DCDC_DCDC_IRQ_STATUS_REG -------------------------- */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos (0UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V14_TIMEOUT_IRQ_STATUS (Bit 0) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk (0x1UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V14_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos (1UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18_TIMEOUT_IRQ_STATUS (Bit 1) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk (0x2UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos (2UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_VDD_TIMEOUT_IRQ_STATUS (Bit 2) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk (0x4UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_VDD_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos (3UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18P_TIMEOUT_IRQ_STATUS (Bit 3) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk (0x8UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_V18P_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Pos (4UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_BROWN_OUT_IRQ_STATUS (Bit 4) */ -#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Msk (0x10UL) /*!< DCDC DCDC_IRQ_STATUS_REG: DCDC_BROWN_OUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ - -/* --------------------------- DCDC_DCDC_IRQ_CLEAR_REG -------------------------- */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos (0UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V14_TIMEOUT_IRQ_CLEAR (Bit 0) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk (0x1UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V14_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos (1UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18_TIMEOUT_IRQ_CLEAR (Bit 1) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk (0x2UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos (2UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bit 2) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk (0x4UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos (3UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bit 3) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk (0x8UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Pos (4UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_BROWN_OUT_IRQ_CLEAR (Bit 4) */ -#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Msk (0x10UL) /*!< DCDC DCDC_IRQ_CLEAR_REG: DCDC_BROWN_OUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ - -/* --------------------------- DCDC_DCDC_IRQ_MASK_REG --------------------------- */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos (0UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V14_TIMEOUT_IRQ_MASK (Bit 0) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk (0x1UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V14_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos (1UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18_TIMEOUT_IRQ_MASK (Bit 1) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk (0x2UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos (2UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_VDD_TIMEOUT_IRQ_MASK (Bit 2) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk (0x4UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_VDD_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos (3UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18P_TIMEOUT_IRQ_MASK (Bit 3) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk (0x8UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_V18P_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Pos (4UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_BROWN_OUT_IRQ_MASK (Bit 4) */ -#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Msk (0x10UL) /*!< DCDC DCDC_IRQ_MASK_REG: DCDC_BROWN_OUT_IRQ_MASK (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'DEM' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- DEM_RF_DEM_CTRL_REG ---------------------------- */ -#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Pos (0UL) /*!< DEM RF_DEM_CTRL_REG: RXDATA_INV (Bit 0) */ -#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Msk (0x1UL) /*!< DEM RF_DEM_CTRL_REG: RXDATA_INV (Bitfield-Mask: 0x01) */ -#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Pos (1UL) /*!< DEM RF_DEM_CTRL_REG: DEM_HSI_POL (Bit 1) */ -#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Msk (0x2UL) /*!< DEM RF_DEM_CTRL_REG: DEM_HSI_POL (Bitfield-Mask: 0x01) */ -#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Pos (2UL) /*!< DEM RF_DEM_CTRL_REG: MATCH0101_TH (Bit 2) */ -#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Msk (0x3cUL) /*!< DEM RF_DEM_CTRL_REG: MATCH0101_TH (Bitfield-Mask: 0x0f) */ -#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Pos (6UL) /*!< DEM RF_DEM_CTRL_REG: EQUAL_EN (Bit 6) */ -#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Msk (0x40UL) /*!< DEM RF_DEM_CTRL_REG: EQUAL_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Pos (7UL) /*!< DEM RF_DEM_CTRL_REG: BLE_DDC_EN (Bit 7) */ -#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Msk (0x80UL) /*!< DEM RF_DEM_CTRL_REG: BLE_DDC_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Pos (8UL) /*!< DEM RF_DEM_CTRL_REG: IQCORR_EN (Bit 8) */ -#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Msk (0x100UL) /*!< DEM RF_DEM_CTRL_REG: IQCORR_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Pos (9UL) /*!< DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bit 9) */ -#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Msk (0x200UL) /*!< DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Pos (10UL) /*!< DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bit 10) */ -#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Msk (0x400UL) /*!< DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Pos (11UL) /*!< DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bit 11) */ -#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Msk (0x3800UL) /*!< DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bitfield-Mask: 0x07) */ - -/* ---------------------------- DEM_RF_AGC_LUT_01_REG --------------------------- */ -#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Pos (0UL) /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN0 (Bit 0) */ -#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Msk (0x7UL) /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN0 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Pos (3UL) /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN0 (Bit 3) */ -#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Msk (0x38UL) /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN0 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Pos (6UL) /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN0 (Bit 6) */ -#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Msk (0xc0UL) /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN0 (Bitfield-Mask: 0x03) */ -#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Pos (8UL) /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN1 (Bit 8) */ -#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Msk (0x700UL) /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN1 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Pos (11UL) /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN1 (Bit 11) */ -#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Msk (0x3800UL) /*!< DEM RF_AGC_LUT_01_REG: VGA1_GAIN1 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Pos (14UL) /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN1 (Bit 14) */ -#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Msk (0xc000UL) /*!< DEM RF_AGC_LUT_01_REG: LNA_GAIN1 (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_AGC_LUT_23_REG --------------------------- */ -#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Pos (0UL) /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN2 (Bit 0) */ -#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Msk (0x7UL) /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN2 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Pos (3UL) /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN2 (Bit 3) */ -#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Msk (0x38UL) /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN2 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Pos (6UL) /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN2 (Bit 6) */ -#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Msk (0xc0UL) /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN2 (Bitfield-Mask: 0x03) */ -#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Pos (8UL) /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN3 (Bit 8) */ -#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Msk (0x700UL) /*!< DEM RF_AGC_LUT_23_REG: VGA2_GAIN3 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Pos (11UL) /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN3 (Bit 11) */ -#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Msk (0x3800UL) /*!< DEM RF_AGC_LUT_23_REG: VGA1_GAIN3 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Pos (14UL) /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN3 (Bit 14) */ -#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Msk (0xc000UL) /*!< DEM RF_AGC_LUT_23_REG: LNA_GAIN3 (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_AGC_LUT_45_REG --------------------------- */ -#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Pos (0UL) /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN4 (Bit 0) */ -#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Msk (0x7UL) /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN4 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Pos (3UL) /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN4 (Bit 3) */ -#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Msk (0x38UL) /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN4 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Pos (6UL) /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN4 (Bit 6) */ -#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Msk (0xc0UL) /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN4 (Bitfield-Mask: 0x03) */ -#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Pos (8UL) /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN5 (Bit 8) */ -#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Msk (0x700UL) /*!< DEM RF_AGC_LUT_45_REG: VGA2_GAIN5 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Pos (11UL) /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN5 (Bit 11) */ -#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Msk (0x3800UL) /*!< DEM RF_AGC_LUT_45_REG: VGA1_GAIN5 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Pos (14UL) /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN5 (Bit 14) */ -#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Msk (0xc000UL) /*!< DEM RF_AGC_LUT_45_REG: LNA_GAIN5 (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_AGC_LUT_67_REG --------------------------- */ -#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Pos (0UL) /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN6 (Bit 0) */ -#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Msk (0x7UL) /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN6 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Pos (3UL) /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN6 (Bit 3) */ -#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Msk (0x38UL) /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN6 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Pos (6UL) /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN6 (Bit 6) */ -#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Msk (0xc0UL) /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN6 (Bitfield-Mask: 0x03) */ -#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Pos (8UL) /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN7 (Bit 8) */ -#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Msk (0x700UL) /*!< DEM RF_AGC_LUT_67_REG: VGA2_GAIN7 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Pos (11UL) /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN7 (Bit 11) */ -#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Msk (0x3800UL) /*!< DEM RF_AGC_LUT_67_REG: VGA1_GAIN7 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Pos (14UL) /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN7 (Bit 14) */ -#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Msk (0xc000UL) /*!< DEM RF_AGC_LUT_67_REG: LNA_GAIN7 (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_AGC_LUT_89_REG --------------------------- */ -#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Pos (0UL) /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN8 (Bit 0) */ -#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Msk (0x7UL) /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN8 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Pos (3UL) /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN8 (Bit 3) */ -#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Msk (0x38UL) /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN8 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Pos (6UL) /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN8 (Bit 6) */ -#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Msk (0xc0UL) /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN8 (Bitfield-Mask: 0x03) */ -#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Pos (8UL) /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN9 (Bit 8) */ -#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Msk (0x700UL) /*!< DEM RF_AGC_LUT_89_REG: VGA2_GAIN9 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Pos (11UL) /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN9 (Bit 11) */ -#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Msk (0x3800UL) /*!< DEM RF_AGC_LUT_89_REG: VGA1_GAIN9 (Bitfield-Mask: 0x07) */ -#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Pos (14UL) /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN9 (Bit 14) */ -#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Msk (0xc000UL) /*!< DEM RF_AGC_LUT_89_REG: LNA_GAIN9 (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_AGC_CTRL1_REG ---------------------------- */ -#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Pos (0UL) /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_LOW (Bit 0) */ -#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Msk (0x7fUL) /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_LOW (Bitfield-Mask: 0x7f) */ -#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Pos (7UL) /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_HIGH (Bit 7) */ -#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Msk (0x3f80UL) /*!< DEM RF_AGC_CTRL1_REG: AGC_TH_HIGH (Bitfield-Mask: 0x7f) */ -#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Pos (14UL) /*!< DEM RF_AGC_CTRL1_REG: AGC_MODE (Bit 14) */ -#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Msk (0xc000UL) /*!< DEM RF_AGC_CTRL1_REG: AGC_MODE (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_AGC_CTRL2_REG ---------------------------- */ -#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Pos (0UL) /*!< DEM RF_AGC_CTRL2_REG: RSSI_TH (Bit 0) */ -#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Msk (0x3fUL) /*!< DEM RF_AGC_CTRL2_REG: RSSI_TH (Bitfield-Mask: 0x3f) */ -#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Pos (6UL) /*!< DEM RF_AGC_CTRL2_REG: EN_FRZ_GAIN (Bit 6) */ -#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Msk (0x40UL) /*!< DEM RF_AGC_CTRL2_REG: EN_FRZ_GAIN (Bitfield-Mask: 0x01) */ -#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Pos (7UL) /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_SEL (Bit 7) */ -#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Msk (0x80UL) /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_SEL (Bitfield-Mask: 0x01) */ -#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Pos (8UL) /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_WR (Bit 8) */ -#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Msk (0xf00UL) /*!< DEM RF_AGC_CTRL2_REG: AGCSETTING_WR (Bitfield-Mask: 0x0f) */ -#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Pos (12UL) /*!< DEM RF_AGC_CTRL2_REG: SLOW_AGC (Bit 12) */ -#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Msk (0x1000UL) /*!< DEM RF_AGC_CTRL2_REG: SLOW_AGC (Bitfield-Mask: 0x01) */ - -/* ----------------------------- DEM_RF_AFC_CTRL_REG ---------------------------- */ -#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Pos (0UL) /*!< DEM RF_AFC_CTRL_REG: AFC_MODE (Bit 0) */ -#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Msk (0xfUL) /*!< DEM RF_AFC_CTRL_REG: AFC_MODE (Bitfield-Mask: 0x0f) */ -#define DEM_RF_AFC_CTRL_REG_POLE1_Pos (4UL) /*!< DEM RF_AFC_CTRL_REG: POLE1 (Bit 4) */ -#define DEM_RF_AFC_CTRL_REG_POLE1_Msk (0x30UL) /*!< DEM RF_AFC_CTRL_REG: POLE1 (Bitfield-Mask: 0x03) */ -#define DEM_RF_AFC_CTRL_REG_POLE2_Pos (6UL) /*!< DEM RF_AFC_CTRL_REG: POLE2 (Bit 6) */ -#define DEM_RF_AFC_CTRL_REG_POLE2_Msk (0xc0UL) /*!< DEM RF_AFC_CTRL_REG: POLE2 (Bitfield-Mask: 0x03) */ -#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Pos (8UL) /*!< DEM RF_AFC_CTRL_REG: PAD_MODE (Bit 8) */ -#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Msk (0x300UL) /*!< DEM RF_AFC_CTRL_REG: PAD_MODE (Bitfield-Mask: 0x03) */ -#define DEM_RF_AFC_CTRL_REG_APD_MODE_Pos (10UL) /*!< DEM RF_AFC_CTRL_REG: APD_MODE (Bit 10) */ -#define DEM_RF_AFC_CTRL_REG_APD_MODE_Msk (0x1c00UL) /*!< DEM RF_AFC_CTRL_REG: APD_MODE (Bitfield-Mask: 0x07) */ - -/* ------------------------- DEM_RF_DC_OFFSET_CTRL1_REG ------------------------- */ -#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Pos (0UL) /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_I_WR (Bit 0) */ -#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Msk (0xffUL) /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_I_WR (Bitfield-Mask: 0xff) */ -#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Pos (8UL) /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_Q_WR (Bit 8) */ -#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Msk (0xff00UL) /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_Q_WR (Bitfield-Mask: 0xff) */ - -/* ------------------------- DEM_RF_DC_OFFSET_CTRL2_REG ------------------------- */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Pos (0UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCOFFSET_SEL (Bit 0) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Msk (0x1UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCOFFSET_SEL (Bitfield-Mask: 0x01) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Pos (1UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_EN (Bit 1) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Msk (0x2UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Pos (2UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPOLE (Bit 2) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Msk (0xcUL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPOLE (Bitfield-Mask: 0x03) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Pos (4UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNSTEP (Bit 4) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Msk (0x70UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNSTEP (Bitfield-Mask: 0x07) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Pos (7UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNGAIN (Bit 7) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Msk (0x180UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNGAIN (Bitfield-Mask: 0x03) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Pos (9UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bit 9) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Msk (0x200UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bitfield-Mask: 0x01) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Pos (10UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bit 10) */ -#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Msk (0x400UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------- DEM_RF_DC_OFFSET_CTRL3_REG ------------------------- */ -#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Pos (0UL) /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_I (Bit 0) */ -#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Msk (0xffUL) /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_I (Bitfield-Mask: 0xff) */ -#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Pos (8UL) /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_Q (Bit 8) */ -#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Msk (0xff00UL) /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_Q (Bitfield-Mask: 0xff) */ - -/* ------------------------- DEM_RF_DC_OFFSET_CTRL4_REG ------------------------- */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Pos (0UL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL0 (Bit 0) */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Msk (0xfUL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL0 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Pos (4UL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL1 (Bit 4) */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Msk (0xf0UL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL1 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Pos (8UL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL2 (Bit 8) */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Msk (0xf00UL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL2 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Pos (12UL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL3 (Bit 12) */ -#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Msk (0xf000UL) /*!< DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL3 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- DEM_RF_AGC_RESULT_REG --------------------------- */ -#define DEM_RF_AGC_RESULT_REG_AFC_RD_Pos (0UL) /*!< DEM RF_AGC_RESULT_REG: AFC_RD (Bit 0) */ -#define DEM_RF_AGC_RESULT_REG_AFC_RD_Msk (0xffUL) /*!< DEM RF_AGC_RESULT_REG: AFC_RD (Bitfield-Mask: 0xff) */ -#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Pos (8UL) /*!< DEM RF_AGC_RESULT_REG: AGCSETTING_RD (Bit 8) */ -#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Msk (0xf00UL) /*!< DEM RF_AGC_RESULT_REG: AGCSETTING_RD (Bitfield-Mask: 0x0f) */ - -/* --------------------------- DEM_RF_RSSI_RESULT_REG --------------------------- */ -#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Pos (0UL) /*!< DEM RF_RSSI_RESULT_REG: RSSI_PH_RD (Bit 0) */ -#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Msk (0x3fUL) /*!< DEM RF_RSSI_RESULT_REG: RSSI_PH_RD (Bitfield-Mask: 0x3f) */ -#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Pos (6UL) /*!< DEM RF_RSSI_RESULT_REG: RSSI_AVG_RD (Bit 6) */ -#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Msk (0xffc0UL) /*!< DEM RF_RSSI_RESULT_REG: RSSI_AVG_RD (Bitfield-Mask: 0x3ff) */ - -/* ------------------------- DEM_RF_DC_OFFSET_RESULT_REG ------------------------ */ -#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Pos (0UL) /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_I_RD (Bit 0) */ -#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Msk (0xffUL) /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_I_RD (Bitfield-Mask: 0xff) */ -#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Pos (8UL) /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_Q_RD (Bit 8) */ -#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Msk (0xff00UL) /*!< DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_Q_RD (Bitfield-Mask: 0xff) */ - -/* -------------------------- DEM_RF_RSSI_COMP_CTRL_REG ------------------------- */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Pos (0UL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP01 (Bit 0) */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Msk (0xfUL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP01 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Pos (4UL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP10 (Bit 4) */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Msk (0xf0UL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP10 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Pos (8UL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP11 (Bit 8) */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Msk (0xf00UL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP11 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Pos (12UL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP00 (Bit 12) */ -#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Msk (0xf000UL) /*!< DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP00 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- DEM_RF_FTDF_CTRL1_REG --------------------------- */ -#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Pos (0UL) /*!< DEM RF_FTDF_CTRL1_REG: CFE_BIAS (Bit 0) */ -#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Msk (0x3ffUL) /*!< DEM RF_FTDF_CTRL1_REG: CFE_BIAS (Bitfield-Mask: 0x3ff) */ -#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Pos (10UL) /*!< DEM RF_FTDF_CTRL1_REG: CFE_MODE (Bit 10) */ -#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Msk (0xc00UL) /*!< DEM RF_FTDF_CTRL1_REG: CFE_MODE (Bitfield-Mask: 0x03) */ -#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Pos (12UL) /*!< DEM RF_FTDF_CTRL1_REG: CFE_NSTEP (Bit 12) */ -#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Msk (0x3000UL) /*!< DEM RF_FTDF_CTRL1_REG: CFE_NSTEP (Bitfield-Mask: 0x03) */ -#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Pos (14UL) /*!< DEM RF_FTDF_CTRL1_REG: CHSEL_FILT_MODE2 (Bit 14) */ -#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Msk (0xc000UL) /*!< DEM RF_FTDF_CTRL1_REG: CHSEL_FILT_MODE2 (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_FTDF_CTRL2_REG --------------------------- */ -#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Pos (0UL) /*!< DEM RF_FTDF_CTRL2_REG: CORRTH (Bit 0) */ -#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Msk (0x3fUL) /*!< DEM RF_FTDF_CTRL2_REG: CORRTH (Bitfield-Mask: 0x3f) */ -#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Pos (6UL) /*!< DEM RF_FTDF_CTRL2_REG: NORM_EN (Bit 6) */ -#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Msk (0x40UL) /*!< DEM RF_FTDF_CTRL2_REG: NORM_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Pos (7UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_MODE (Bit 7) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Msk (0x80UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_MODE (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Pos (8UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_NPEAK (Bit 8) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Msk (0x700UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_NPEAK (Bitfield-Mask: 0x07) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Pos (11UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_NWIN (Bit 11) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Msk (0x3800UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_NWIN (Bitfield-Mask: 0x07) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Pos (14UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_OFFSET (Bit 14) */ -#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Msk (0xc000UL) /*!< DEM RF_FTDF_CTRL2_REG: PD_OFFSET (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_FTDF_CTRL3_REG --------------------------- */ -#define DEM_RF_FTDF_CTRL3_REG_FIF_Pos (0UL) /*!< DEM RF_FTDF_CTRL3_REG: FIF (Bit 0) */ -#define DEM_RF_FTDF_CTRL3_REG_FIF_Msk (0x1ffUL) /*!< DEM RF_FTDF_CTRL3_REG: FIF (Bitfield-Mask: 0x1ff) */ -#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Pos (9UL) /*!< DEM RF_FTDF_CTRL3_REG: FTDF_DDC_EN (Bit 9) */ -#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Msk (0x200UL) /*!< DEM RF_FTDF_CTRL3_REG: FTDF_DDC_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Pos (10UL) /*!< DEM RF_FTDF_CTRL3_REG: MATCH_FILT_EN (Bit 10) */ -#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Msk (0x400UL) /*!< DEM RF_FTDF_CTRL3_REG: MATCH_FILT_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Pos (11UL) /*!< DEM RF_FTDF_CTRL3_REG: TIMING_CORR_EN (Bit 11) */ -#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Msk (0x800UL) /*!< DEM RF_FTDF_CTRL3_REG: TIMING_CORR_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Pos (12UL) /*!< DEM RF_FTDF_CTRL3_REG: CHSEL_FILT_MODE1 (Bit 12) */ -#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Msk (0x3000UL) /*!< DEM RF_FTDF_CTRL3_REG: CHSEL_FILT_MODE1 (Bitfield-Mask: 0x03) */ -#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Pos (14UL) /*!< DEM RF_FTDF_CTRL3_REG: DS_OFFSET (Bit 14) */ -#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Msk (0xc000UL) /*!< DEM RF_FTDF_CTRL3_REG: DS_OFFSET (Bitfield-Mask: 0x03) */ - -/* ---------------------------- DEM_RF_FTDF_CTRL4_REG --------------------------- */ -#define DEM_RF_FTDF_CTRL4_REG_SFD0_Pos (0UL) /*!< DEM RF_FTDF_CTRL4_REG: SFD0 (Bit 0) */ -#define DEM_RF_FTDF_CTRL4_REG_SFD0_Msk (0xfUL) /*!< DEM RF_FTDF_CTRL4_REG: SFD0 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_FTDF_CTRL4_REG_SFD1_Pos (4UL) /*!< DEM RF_FTDF_CTRL4_REG: SFD1 (Bit 4) */ -#define DEM_RF_FTDF_CTRL4_REG_SFD1_Msk (0xf0UL) /*!< DEM RF_FTDF_CTRL4_REG: SFD1 (Bitfield-Mask: 0x0f) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Pos (8UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_PREAMBLE_EN (Bit 8) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Msk (0x100UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_PREAMBLE_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Pos (9UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_SYMBOL_EN (Bit 9) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Msk (0x200UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_SYMBOL_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Pos (10UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_CORRTH_EN (Bit 10) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Msk (0x400UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_CORRTH_EN (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Pos (11UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_SCALE (Bit 11) */ -#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Msk (0x1800UL) /*!< DEM RF_FTDF_CTRL4_REG: LQI_SCALE (Bitfield-Mask: 0x03) */ -#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Pos (13UL) /*!< DEM RF_FTDF_CTRL4_REG: FTDF_HSI_POL (Bit 13) */ -#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Msk (0x2000UL) /*!< DEM RF_FTDF_CTRL4_REG: FTDF_HSI_POL (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Pos (14UL) /*!< DEM RF_FTDF_CTRL4_REG: CCA_MODE (Bit 14) */ -#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Msk (0x4000UL) /*!< DEM RF_FTDF_CTRL4_REG: CCA_MODE (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Pos (15UL) /*!< DEM RF_FTDF_CTRL4_REG: SO_FTDF_SEL (Bit 15) */ -#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Msk (0x8000UL) /*!< DEM RF_FTDF_CTRL4_REG: SO_FTDF_SEL (Bitfield-Mask: 0x01) */ - -/* ------------------------ DEM_RF_FTDF_LOOP_GAIN_PD_REG ------------------------ */ -#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Pos (0UL) /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KP_LF_PD (Bit 0) */ -#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Msk (0xffUL) /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KP_LF_PD (Bitfield-Mask: 0xff) */ -#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Pos (8UL) /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KI_LF_PD (Bit 8) */ -#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Msk (0xff00UL) /*!< DEM RF_FTDF_LOOP_GAIN_PD_REG: KI_LF_PD (Bitfield-Mask: 0xff) */ - -/* ------------------------ DEM_RF_FTDF_LOOP_GAIN_DS_REG ------------------------ */ -#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Pos (0UL) /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KP_LF_DS (Bit 0) */ -#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Msk (0xffUL) /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KP_LF_DS (Bitfield-Mask: 0xff) */ -#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Pos (8UL) /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KI_LF_DS (Bit 8) */ -#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Msk (0xff00UL) /*!< DEM RF_FTDF_LOOP_GAIN_DS_REG: KI_LF_DS (Bitfield-Mask: 0xff) */ - -/* ---------------------------- DEM_RF_FTDF_CTRL5_REG --------------------------- */ -#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Pos (0UL) /*!< DEM RF_FTDF_CTRL5_REG: RSSITH (Bit 0) */ -#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Msk (0x1fffUL) /*!< DEM RF_FTDF_CTRL5_REG: RSSITH (Bitfield-Mask: 0x1fff) */ -#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Pos (13UL) /*!< DEM RF_FTDF_CTRL5_REG: FTDF_DDC_INV (Bit 13) */ -#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Msk (0x2000UL) /*!< DEM RF_FTDF_CTRL5_REG: FTDF_DDC_INV (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Pos (14UL) /*!< DEM RF_FTDF_CTRL5_REG: FSSS_CLEAR (Bit 14) */ -#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Msk (0x4000UL) /*!< DEM RF_FTDF_CTRL5_REG: FSSS_CLEAR (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Pos (15UL) /*!< DEM RF_FTDF_CTRL5_REG: DS_OFFSET_SEL (Bit 15) */ -#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Msk (0x8000UL) /*!< DEM RF_FTDF_CTRL5_REG: DS_OFFSET_SEL (Bitfield-Mask: 0x01) */ - -/* -------------------------- DEM_RF_FTDF_COBI_LOW_REG -------------------------- */ -#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Pos (0UL) /*!< DEM RF_FTDF_COBI_LOW_REG: COBI (Bit 0) */ -#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Msk (0xffffUL) /*!< DEM RF_FTDF_COBI_LOW_REG: COBI (Bitfield-Mask: 0xffff) */ - -/* -------------------------- DEM_RF_FTDF_COBI_HIGH_REG ------------------------- */ -#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Pos (0UL) /*!< DEM RF_FTDF_COBI_HIGH_REG: COBI (Bit 0) */ -#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Msk (0xffffUL) /*!< DEM RF_FTDF_COBI_HIGH_REG: COBI (Bitfield-Mask: 0xffff) */ - -/* --------------------------- DEM_RF_DEM_TESTMODE_REG -------------------------- */ -#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Pos (0UL) /*!< DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bit 0) */ -#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Msk (0x3ffUL) /*!< DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bitfield-Mask: 0x3ff) */ - -/* -------------------------- DEM_RF_DEM_IQCORRECT_REG -------------------------- */ -#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Pos (0UL) /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_BETA (Bit 0) */ -#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Msk (0xffUL) /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_BETA (Bitfield-Mask: 0xff) */ -#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Pos (8UL) /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_ALPHA (Bit 8) */ -#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Msk (0xff00UL) /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_ALPHA (Bitfield-Mask: 0xff) */ - -/* --------------------------- DEM_RF_PAD_CNT_CTRL_REG -------------------------- */ -#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Pos (0UL) /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_POS_LIMIT (Bit 0) */ -#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Msk (0x7fUL) /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_POS_LIMIT (Bitfield-Mask: 0x7f) */ -#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Pos (7UL) /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_NEG_LIMIT (Bit 7) */ -#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Msk (0x3f80UL) /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_NEG_LIMIT (Bitfield-Mask: 0x7f) */ -#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Pos (14UL) /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_CLEAR_COUNT (Bit 14) */ -#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Msk (0x4000UL) /*!< DEM RF_PAD_CNT_CTRL_REG: PAD_CLEAR_COUNT (Bitfield-Mask: 0x01) */ - -/* -------------------------- DEM_RF_PAD_CNT_RESULT_REG ------------------------- */ -#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Pos (0UL) /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_POS_CNT_RD (Bit 0) */ -#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Msk (0xffUL) /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_POS_CNT_RD (Bitfield-Mask: 0xff) */ -#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Pos (8UL) /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_NEG_CNT_RD (Bit 8) */ -#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Msk (0xff00UL) /*!< DEM RF_PAD_CNT_RESULT_REG: PAD_NEG_CNT_RD (Bitfield-Mask: 0xff) */ - -/* -------------------------- DEM_RF_FSSS_I_RESULT_REG -------------------------- */ -#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Pos (0UL) /*!< DEM RF_FSSS_I_RESULT_REG: FSSS_I_RD (Bit 0) */ -#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Msk (0xffffUL) /*!< DEM RF_FSSS_I_RESULT_REG: FSSS_I_RD (Bitfield-Mask: 0xffff) */ - -/* -------------------------- DEM_RF_FSSS_Q_RESULT_REG -------------------------- */ -#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Pos (0UL) /*!< DEM RF_FSSS_Q_RESULT_REG: FSSS_Q_RD (Bit 0) */ -#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Msk (0xffffUL) /*!< DEM RF_FSSS_Q_RESULT_REG: FSSS_Q_RD (Bitfield-Mask: 0xffff) */ - -/* ------------------------- DEM_RF_FSSS_MAG_RESULT_REG ------------------------- */ -#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Pos (0UL) /*!< DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bit 0) */ -#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Msk (0xffffUL) /*!< DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DEM_RF_CCA_RSSITH_REG --------------------------- */ -#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Pos (0UL) /*!< DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bit 0) */ -#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Msk (0x1fffUL) /*!< DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bitfield-Mask: 0x1fff) */ -#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Pos (13UL) /*!< DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bit 13) */ -#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Msk (0xe000UL) /*!< DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bitfield-Mask: 0x07) */ - -/* ------------------------- DEM_RF_FTDF_SIGDET_CTRL_REG ------------------------ */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Pos (0UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bit 0) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Msk (0x3UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bitfield-Mask: 0x03) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Pos (2UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bit 2) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Msk (0xfcUL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bitfield-Mask: 0x3f) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Pos (8UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bit 8) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Msk (0x100UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bitfield-Mask: 0x01) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Pos (9UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bit 9) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Msk (0x600UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bitfield-Mask: 0x03) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Pos (11UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bit 11) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Msk (0x1800UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bitfield-Mask: 0x03) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Pos (13UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bit 13) */ -#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Msk (0x6000UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bitfield-Mask: 0x03) */ - - -/* ================================================================================ */ -/* ================ struct 'DMA' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- DMA_DMA0_A_STARTL_REG --------------------------- */ -#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Pos (0UL) /*!< DMA DMA0_A_STARTL_REG: DMA0_A_STARTL (Bit 0) */ -#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Msk (0xffffUL) /*!< DMA DMA0_A_STARTL_REG: DMA0_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA0_A_STARTH_REG --------------------------- */ -#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Pos (0UL) /*!< DMA DMA0_A_STARTH_REG: DMA0_A_STARTH (Bit 0) */ -#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Msk (0xffffUL) /*!< DMA DMA0_A_STARTH_REG: DMA0_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA0_B_STARTL_REG --------------------------- */ -#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Pos (0UL) /*!< DMA DMA0_B_STARTL_REG: DMA0_B_STARTL (Bit 0) */ -#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Msk (0xffffUL) /*!< DMA DMA0_B_STARTL_REG: DMA0_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA0_B_STARTH_REG --------------------------- */ -#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Pos (0UL) /*!< DMA DMA0_B_STARTH_REG: DMA0_B_STARTH (Bit 0) */ -#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Msk (0xffffUL) /*!< DMA DMA0_B_STARTH_REG: DMA0_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA0_INT_REG ------------------------------ */ -#define DMA_DMA0_INT_REG_DMA0_INT_Pos (0UL) /*!< DMA DMA0_INT_REG: DMA0_INT (Bit 0) */ -#define DMA_DMA0_INT_REG_DMA0_INT_Msk (0xffffUL) /*!< DMA DMA0_INT_REG: DMA0_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA0_LEN_REG ------------------------------ */ -#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos (0UL) /*!< DMA DMA0_LEN_REG: DMA0_LEN (Bit 0) */ -#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk (0xffffUL) /*!< DMA DMA0_LEN_REG: DMA0_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA0_CTRL_REG ----------------------------- */ -#define DMA_DMA0_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA0_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA0_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA0_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA0_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA0_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA0_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA0_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA0_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA0_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA0_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA0_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA0_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA0_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA0_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA0_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA0_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA0_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA0_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA0_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA0_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA0_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA0_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA0_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA0_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA0_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA0_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA0_IDX_REG ------------------------------ */ -#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL) /*!< DMA DMA0_IDX_REG: DMA0_IDX (Bit 0) */ -#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk (0xffffUL) /*!< DMA DMA0_IDX_REG: DMA0_IDX (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA1_A_STARTL_REG --------------------------- */ -#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Pos (0UL) /*!< DMA DMA1_A_STARTL_REG: DMA1_A_STARTL (Bit 0) */ -#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Msk (0xffffUL) /*!< DMA DMA1_A_STARTL_REG: DMA1_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA1_A_STARTH_REG --------------------------- */ -#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Pos (0UL) /*!< DMA DMA1_A_STARTH_REG: DMA1_A_STARTH (Bit 0) */ -#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Msk (0xffffUL) /*!< DMA DMA1_A_STARTH_REG: DMA1_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA1_B_STARTL_REG --------------------------- */ -#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Pos (0UL) /*!< DMA DMA1_B_STARTL_REG: DMA1_B_STARTL (Bit 0) */ -#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Msk (0xffffUL) /*!< DMA DMA1_B_STARTL_REG: DMA1_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA1_B_STARTH_REG --------------------------- */ -#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Pos (0UL) /*!< DMA DMA1_B_STARTH_REG: DMA1_B_STARTH (Bit 0) */ -#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Msk (0xffffUL) /*!< DMA DMA1_B_STARTH_REG: DMA1_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA1_INT_REG ------------------------------ */ -#define DMA_DMA1_INT_REG_DMA1_INT_Pos (0UL) /*!< DMA DMA1_INT_REG: DMA1_INT (Bit 0) */ -#define DMA_DMA1_INT_REG_DMA1_INT_Msk (0xffffUL) /*!< DMA DMA1_INT_REG: DMA1_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA1_LEN_REG ------------------------------ */ -#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos (0UL) /*!< DMA DMA1_LEN_REG: DMA1_LEN (Bit 0) */ -#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk (0xffffUL) /*!< DMA DMA1_LEN_REG: DMA1_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA1_CTRL_REG ----------------------------- */ -#define DMA_DMA1_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA1_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA1_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA1_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA1_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA1_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA1_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA1_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA1_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA1_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA1_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA1_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA1_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA1_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA1_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA1_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA1_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA1_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA1_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA1_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA1_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA1_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA1_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA1_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA1_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA1_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA1_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA1_IDX_REG ------------------------------ */ -#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL) /*!< DMA DMA1_IDX_REG: DMA1_IDX (Bit 0) */ -#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk (0xffffUL) /*!< DMA DMA1_IDX_REG: DMA1_IDX (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA2_A_STARTL_REG --------------------------- */ -#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Pos (0UL) /*!< DMA DMA2_A_STARTL_REG: DMA2_A_STARTL (Bit 0) */ -#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Msk (0xffffUL) /*!< DMA DMA2_A_STARTL_REG: DMA2_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA2_A_STARTH_REG --------------------------- */ -#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Pos (0UL) /*!< DMA DMA2_A_STARTH_REG: DMA2_A_STARTH (Bit 0) */ -#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Msk (0xffffUL) /*!< DMA DMA2_A_STARTH_REG: DMA2_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA2_B_STARTL_REG --------------------------- */ -#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Pos (0UL) /*!< DMA DMA2_B_STARTL_REG: DMA2_B_STARTL (Bit 0) */ -#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Msk (0xffffUL) /*!< DMA DMA2_B_STARTL_REG: DMA2_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA2_B_STARTH_REG --------------------------- */ -#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Pos (0UL) /*!< DMA DMA2_B_STARTH_REG: DMA2_B_STARTH (Bit 0) */ -#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Msk (0xffffUL) /*!< DMA DMA2_B_STARTH_REG: DMA2_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA2_INT_REG ------------------------------ */ -#define DMA_DMA2_INT_REG_DMA2_INT_Pos (0UL) /*!< DMA DMA2_INT_REG: DMA2_INT (Bit 0) */ -#define DMA_DMA2_INT_REG_DMA2_INT_Msk (0xffffUL) /*!< DMA DMA2_INT_REG: DMA2_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA2_LEN_REG ------------------------------ */ -#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos (0UL) /*!< DMA DMA2_LEN_REG: DMA2_LEN (Bit 0) */ -#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk (0xffffUL) /*!< DMA DMA2_LEN_REG: DMA2_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA2_CTRL_REG ----------------------------- */ -#define DMA_DMA2_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA2_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA2_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA2_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA2_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA2_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA2_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA2_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA2_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA2_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA2_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA2_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA2_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA2_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA2_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA2_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA2_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA2_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA2_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA2_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA2_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA2_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA2_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA2_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA2_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA2_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA2_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA2_IDX_REG ------------------------------ */ -#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL) /*!< DMA DMA2_IDX_REG: DMA2_IDX (Bit 0) */ -#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk (0xffffUL) /*!< DMA DMA2_IDX_REG: DMA2_IDX (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA3_A_STARTL_REG --------------------------- */ -#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Pos (0UL) /*!< DMA DMA3_A_STARTL_REG: DMA3_A_STARTL (Bit 0) */ -#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Msk (0xffffUL) /*!< DMA DMA3_A_STARTL_REG: DMA3_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA3_A_STARTH_REG --------------------------- */ -#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Pos (0UL) /*!< DMA DMA3_A_STARTH_REG: DMA3_A_STARTH (Bit 0) */ -#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Msk (0xffffUL) /*!< DMA DMA3_A_STARTH_REG: DMA3_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA3_B_STARTL_REG --------------------------- */ -#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Pos (0UL) /*!< DMA DMA3_B_STARTL_REG: DMA3_B_STARTL (Bit 0) */ -#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Msk (0xffffUL) /*!< DMA DMA3_B_STARTL_REG: DMA3_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA3_B_STARTH_REG --------------------------- */ -#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Pos (0UL) /*!< DMA DMA3_B_STARTH_REG: DMA3_B_STARTH (Bit 0) */ -#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Msk (0xffffUL) /*!< DMA DMA3_B_STARTH_REG: DMA3_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA3_INT_REG ------------------------------ */ -#define DMA_DMA3_INT_REG_DMA3_INT_Pos (0UL) /*!< DMA DMA3_INT_REG: DMA3_INT (Bit 0) */ -#define DMA_DMA3_INT_REG_DMA3_INT_Msk (0xffffUL) /*!< DMA DMA3_INT_REG: DMA3_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA3_LEN_REG ------------------------------ */ -#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos (0UL) /*!< DMA DMA3_LEN_REG: DMA3_LEN (Bit 0) */ -#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk (0xffffUL) /*!< DMA DMA3_LEN_REG: DMA3_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA3_CTRL_REG ----------------------------- */ -#define DMA_DMA3_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA3_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA3_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA3_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA3_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA3_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA3_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA3_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA3_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA3_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA3_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA3_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA3_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA3_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA3_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA3_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA3_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA3_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA3_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA3_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA3_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA3_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA3_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA3_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA3_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA3_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA3_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA3_IDX_REG ------------------------------ */ -#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL) /*!< DMA DMA3_IDX_REG: DMA3_IDX (Bit 0) */ -#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk (0xffffUL) /*!< DMA DMA3_IDX_REG: DMA3_IDX (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA4_A_STARTL_REG --------------------------- */ -#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Pos (0UL) /*!< DMA DMA4_A_STARTL_REG: DMA4_A_STARTL (Bit 0) */ -#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Msk (0xffffUL) /*!< DMA DMA4_A_STARTL_REG: DMA4_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA4_A_STARTH_REG --------------------------- */ -#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Pos (0UL) /*!< DMA DMA4_A_STARTH_REG: DMA4_A_STARTH (Bit 0) */ -#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Msk (0xffffUL) /*!< DMA DMA4_A_STARTH_REG: DMA4_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA4_B_STARTL_REG --------------------------- */ -#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Pos (0UL) /*!< DMA DMA4_B_STARTL_REG: DMA4_B_STARTL (Bit 0) */ -#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Msk (0xffffUL) /*!< DMA DMA4_B_STARTL_REG: DMA4_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA4_B_STARTH_REG --------------------------- */ -#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Pos (0UL) /*!< DMA DMA4_B_STARTH_REG: DMA4_B_STARTH (Bit 0) */ -#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Msk (0xffffUL) /*!< DMA DMA4_B_STARTH_REG: DMA4_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA4_INT_REG ------------------------------ */ -#define DMA_DMA4_INT_REG_DMA4_INT_Pos (0UL) /*!< DMA DMA4_INT_REG: DMA4_INT (Bit 0) */ -#define DMA_DMA4_INT_REG_DMA4_INT_Msk (0xffffUL) /*!< DMA DMA4_INT_REG: DMA4_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA4_LEN_REG ------------------------------ */ -#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos (0UL) /*!< DMA DMA4_LEN_REG: DMA4_LEN (Bit 0) */ -#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk (0xffffUL) /*!< DMA DMA4_LEN_REG: DMA4_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA4_CTRL_REG ----------------------------- */ -#define DMA_DMA4_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA4_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA4_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA4_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA4_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA4_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA4_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA4_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA4_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA4_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA4_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA4_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA4_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA4_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA4_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA4_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA4_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA4_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA4_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA4_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA4_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA4_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA4_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA4_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA4_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA4_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA4_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA4_IDX_REG ------------------------------ */ -#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL) /*!< DMA DMA4_IDX_REG: DMA4_IDX (Bit 0) */ -#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk (0xffffUL) /*!< DMA DMA4_IDX_REG: DMA4_IDX (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA5_A_STARTL_REG --------------------------- */ -#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Pos (0UL) /*!< DMA DMA5_A_STARTL_REG: DMA5_A_STARTL (Bit 0) */ -#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Msk (0xffffUL) /*!< DMA DMA5_A_STARTL_REG: DMA5_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA5_A_STARTH_REG --------------------------- */ -#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Pos (0UL) /*!< DMA DMA5_A_STARTH_REG: DMA5_A_STARTH (Bit 0) */ -#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Msk (0xffffUL) /*!< DMA DMA5_A_STARTH_REG: DMA5_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA5_B_STARTL_REG --------------------------- */ -#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Pos (0UL) /*!< DMA DMA5_B_STARTL_REG: DMA5_B_STARTL (Bit 0) */ -#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Msk (0xffffUL) /*!< DMA DMA5_B_STARTL_REG: DMA5_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA5_B_STARTH_REG --------------------------- */ -#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Pos (0UL) /*!< DMA DMA5_B_STARTH_REG: DMA5_B_STARTH (Bit 0) */ -#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Msk (0xffffUL) /*!< DMA DMA5_B_STARTH_REG: DMA5_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA5_INT_REG ------------------------------ */ -#define DMA_DMA5_INT_REG_DMA5_INT_Pos (0UL) /*!< DMA DMA5_INT_REG: DMA5_INT (Bit 0) */ -#define DMA_DMA5_INT_REG_DMA5_INT_Msk (0xffffUL) /*!< DMA DMA5_INT_REG: DMA5_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA5_LEN_REG ------------------------------ */ -#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos (0UL) /*!< DMA DMA5_LEN_REG: DMA5_LEN (Bit 0) */ -#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk (0xffffUL) /*!< DMA DMA5_LEN_REG: DMA5_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA5_CTRL_REG ----------------------------- */ -#define DMA_DMA5_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA5_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA5_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA5_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA5_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA5_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA5_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA5_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA5_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA5_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA5_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA5_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA5_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA5_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA5_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA5_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA5_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA5_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA5_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA5_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA5_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA5_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA5_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA5_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA5_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA5_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA5_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA5_IDX_REG ------------------------------ */ -#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL) /*!< DMA DMA5_IDX_REG: DMA5_IDX (Bit 0) */ -#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk (0xffffUL) /*!< DMA DMA5_IDX_REG: DMA5_IDX (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA6_A_STARTL_REG --------------------------- */ -#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Pos (0UL) /*!< DMA DMA6_A_STARTL_REG: DMA6_A_STARTL (Bit 0) */ -#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Msk (0xffffUL) /*!< DMA DMA6_A_STARTL_REG: DMA6_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA6_A_STARTH_REG --------------------------- */ -#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Pos (0UL) /*!< DMA DMA6_A_STARTH_REG: DMA6_A_STARTH (Bit 0) */ -#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Msk (0xffffUL) /*!< DMA DMA6_A_STARTH_REG: DMA6_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA6_B_STARTL_REG --------------------------- */ -#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Pos (0UL) /*!< DMA DMA6_B_STARTL_REG: DMA6_B_STARTL (Bit 0) */ -#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Msk (0xffffUL) /*!< DMA DMA6_B_STARTL_REG: DMA6_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA6_B_STARTH_REG --------------------------- */ -#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Pos (0UL) /*!< DMA DMA6_B_STARTH_REG: DMA6_B_STARTH (Bit 0) */ -#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Msk (0xffffUL) /*!< DMA DMA6_B_STARTH_REG: DMA6_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA6_INT_REG ------------------------------ */ -#define DMA_DMA6_INT_REG_DMA6_INT_Pos (0UL) /*!< DMA DMA6_INT_REG: DMA6_INT (Bit 0) */ -#define DMA_DMA6_INT_REG_DMA6_INT_Msk (0xffffUL) /*!< DMA DMA6_INT_REG: DMA6_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA6_LEN_REG ------------------------------ */ -#define DMA_DMA6_LEN_REG_DMA6_LEN_Pos (0UL) /*!< DMA DMA6_LEN_REG: DMA6_LEN (Bit 0) */ -#define DMA_DMA6_LEN_REG_DMA6_LEN_Msk (0xffffUL) /*!< DMA DMA6_LEN_REG: DMA6_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA6_CTRL_REG ----------------------------- */ -#define DMA_DMA6_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA6_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA6_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA6_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA6_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA6_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA6_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA6_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA6_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA6_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA6_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA6_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA6_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA6_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA6_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA6_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA6_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA6_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA6_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA6_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA6_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA6_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA6_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA6_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA6_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA6_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA6_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA6_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA6_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA6_IDX_REG ------------------------------ */ -#define DMA_DMA6_IDX_REG_DMA6_IDX_Pos (0UL) /*!< DMA DMA6_IDX_REG: DMA6_IDX (Bit 0) */ -#define DMA_DMA6_IDX_REG_DMA6_IDX_Msk (0xffffUL) /*!< DMA DMA6_IDX_REG: DMA6_IDX (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA7_A_STARTL_REG --------------------------- */ -#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Pos (0UL) /*!< DMA DMA7_A_STARTL_REG: DMA7_A_STARTL (Bit 0) */ -#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Msk (0xffffUL) /*!< DMA DMA7_A_STARTL_REG: DMA7_A_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA7_A_STARTH_REG --------------------------- */ -#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Pos (0UL) /*!< DMA DMA7_A_STARTH_REG: DMA7_A_STARTH (Bit 0) */ -#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Msk (0xffffUL) /*!< DMA DMA7_A_STARTH_REG: DMA7_A_STARTH (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA7_B_STARTL_REG --------------------------- */ -#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Pos (0UL) /*!< DMA DMA7_B_STARTL_REG: DMA7_B_STARTL (Bit 0) */ -#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Msk (0xffffUL) /*!< DMA DMA7_B_STARTL_REG: DMA7_B_STARTL (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- DMA_DMA7_B_STARTH_REG --------------------------- */ -#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Pos (0UL) /*!< DMA DMA7_B_STARTH_REG: DMA7_B_STARTH (Bit 0) */ -#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Msk (0xffffUL) /*!< DMA DMA7_B_STARTH_REG: DMA7_B_STARTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA7_INT_REG ------------------------------ */ -#define DMA_DMA7_INT_REG_DMA7_INT_Pos (0UL) /*!< DMA DMA7_INT_REG: DMA7_INT (Bit 0) */ -#define DMA_DMA7_INT_REG_DMA7_INT_Msk (0xffffUL) /*!< DMA DMA7_INT_REG: DMA7_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA7_LEN_REG ------------------------------ */ -#define DMA_DMA7_LEN_REG_DMA7_LEN_Pos (0UL) /*!< DMA DMA7_LEN_REG: DMA7_LEN (Bit 0) */ -#define DMA_DMA7_LEN_REG_DMA7_LEN_Msk (0xffffUL) /*!< DMA DMA7_LEN_REG: DMA7_LEN (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ DMA_DMA7_CTRL_REG ----------------------------- */ -#define DMA_DMA7_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA DMA7_CTRL_REG: DMA_ON (Bit 0) */ -#define DMA_DMA7_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA DMA7_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_BW_Pos (1UL) /*!< DMA DMA7_CTRL_REG: BW (Bit 1) */ -#define DMA_DMA7_CTRL_REG_BW_Msk (0x6UL) /*!< DMA DMA7_CTRL_REG: BW (Bitfield-Mask: 0x03) */ -#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Pos (3UL) /*!< DMA DMA7_CTRL_REG: IRQ_ENABLE (Bit 3) */ -#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Msk (0x8UL) /*!< DMA DMA7_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos (4UL) /*!< DMA DMA7_CTRL_REG: DREQ_MODE (Bit 4) */ -#define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk (0x10UL) /*!< DMA DMA7_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_BINC_Pos (5UL) /*!< DMA DMA7_CTRL_REG: BINC (Bit 5) */ -#define DMA_DMA7_CTRL_REG_BINC_Msk (0x20UL) /*!< DMA DMA7_CTRL_REG: BINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_AINC_Pos (6UL) /*!< DMA DMA7_CTRL_REG: AINC (Bit 6) */ -#define DMA_DMA7_CTRL_REG_AINC_Msk (0x40UL) /*!< DMA DMA7_CTRL_REG: AINC (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_CIRCULAR_Pos (7UL) /*!< DMA DMA7_CTRL_REG: CIRCULAR (Bit 7) */ -#define DMA_DMA7_CTRL_REG_CIRCULAR_Msk (0x80UL) /*!< DMA DMA7_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos (8UL) /*!< DMA DMA7_CTRL_REG: DMA_PRIO (Bit 8) */ -#define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk (0x700UL) /*!< DMA DMA7_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07) */ -#define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos (11UL) /*!< DMA DMA7_CTRL_REG: DMA_IDLE (Bit 11) */ -#define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA7_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA7_CTRL_REG: DMA_INIT (Bit 12) */ -#define DMA_DMA7_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA7_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ -#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA7_CTRL_REG: REQ_SENSE (Bit 13) */ -#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA7_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ DMA_DMA7_IDX_REG ------------------------------ */ -#define DMA_DMA7_IDX_REG_DMA7_IDX_Pos (0UL) /*!< DMA DMA7_IDX_REG: DMA7_IDX (Bit 0) */ -#define DMA_DMA7_IDX_REG_DMA7_IDX_Msk (0xffffUL) /*!< DMA DMA7_IDX_REG: DMA7_IDX (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- DMA_DMA_REQ_MUX_REG ---------------------------- */ -#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos (0UL) /*!< DMA DMA_REQ_MUX_REG: DMA01_SEL (Bit 0) */ -#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk (0xfUL) /*!< DMA DMA_REQ_MUX_REG: DMA01_SEL (Bitfield-Mask: 0x0f) */ -#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos (4UL) /*!< DMA DMA_REQ_MUX_REG: DMA23_SEL (Bit 4) */ -#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk (0xf0UL) /*!< DMA DMA_REQ_MUX_REG: DMA23_SEL (Bitfield-Mask: 0x0f) */ -#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos (8UL) /*!< DMA DMA_REQ_MUX_REG: DMA45_SEL (Bit 8) */ -#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk (0xf00UL) /*!< DMA DMA_REQ_MUX_REG: DMA45_SEL (Bitfield-Mask: 0x0f) */ -#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos (12UL) /*!< DMA DMA_REQ_MUX_REG: DMA67_SEL (Bit 12) */ -#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk (0xf000UL) /*!< DMA DMA_REQ_MUX_REG: DMA67_SEL (Bitfield-Mask: 0x0f) */ - -/* --------------------------- DMA_DMA_INT_STATUS_REG --------------------------- */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH0 (Bit 0) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH0 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH1 (Bit 1) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH1 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH2 (Bit 2) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH2 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH3 (Bit 3) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH3 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH4 (Bit 4) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH4 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH5 (Bit 5) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH5 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos (6UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH6 (Bit 6) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk (0x40UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH6 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos (7UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH7 (Bit 7) */ -#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk (0x80UL) /*!< DMA DMA_INT_STATUS_REG: DMA_IRQ_CH7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- DMA_DMA_CLEAR_INT_REG --------------------------- */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH0 (Bit 0) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH1 (Bit 1) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH2 (Bit 2) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH3 (Bit 3) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH4 (Bit 4) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH5 (Bit 5) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos (6UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH6 (Bit 6) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk (0x40UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH6 (Bitfield-Mask: 0x01) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos (7UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH7 (Bit 7) */ -#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk (0x80UL) /*!< DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH7 (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'ECC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- ECC_ECC_CONFIG_REG ----------------------------- */ -#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Pos (0UL) /*!< ECC ECC_CONFIG_REG: ECC_OpPtrA (Bit 0) */ -#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Msk (0x1fUL) /*!< ECC ECC_CONFIG_REG: ECC_OpPtrA (Bitfield-Mask: 0x1f) */ -#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Pos (8UL) /*!< ECC ECC_CONFIG_REG: ECC_OpPtrB (Bit 8) */ -#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Msk (0x1f00UL) /*!< ECC ECC_CONFIG_REG: ECC_OpPtrB (Bitfield-Mask: 0x1f) */ -#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Pos (16UL) /*!< ECC ECC_CONFIG_REG: ECC_OpPtrC (Bit 16) */ -#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Msk (0x1f0000UL) /*!< ECC ECC_CONFIG_REG: ECC_OpPtrC (Bitfield-Mask: 0x1f) */ - -/* ----------------------------- ECC_ECC_COMMAND_REG ---------------------------- */ -#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Pos (0UL) /*!< ECC ECC_COMMAND_REG: ECC_TypeOperation (Bit 0) */ -#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Msk (0x7fUL) /*!< ECC ECC_COMMAND_REG: ECC_TypeOperation (Bitfield-Mask: 0x7f) */ -#define ECC_ECC_COMMAND_REG_ECC_Field_Pos (7UL) /*!< ECC ECC_COMMAND_REG: ECC_Field (Bit 7) */ -#define ECC_ECC_COMMAND_REG_ECC_Field_Msk (0x80UL) /*!< ECC ECC_COMMAND_REG: ECC_Field (Bitfield-Mask: 0x01) */ -#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Pos (8UL) /*!< ECC ECC_COMMAND_REG: ECC_SizeOfOperands (Bit 8) */ -#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Msk (0xff00UL) /*!< ECC ECC_COMMAND_REG: ECC_SizeOfOperands (Bitfield-Mask: 0xff) */ -#define ECC_ECC_COMMAND_REG_ECC_SignA_Pos (29UL) /*!< ECC ECC_COMMAND_REG: ECC_SignA (Bit 29) */ -#define ECC_ECC_COMMAND_REG_ECC_SignA_Msk (0x20000000UL) /*!< ECC ECC_COMMAND_REG: ECC_SignA (Bitfield-Mask: 0x01) */ -#define ECC_ECC_COMMAND_REG_ECC_SignB_Pos (30UL) /*!< ECC ECC_COMMAND_REG: ECC_SignB (Bit 30) */ -#define ECC_ECC_COMMAND_REG_ECC_SignB_Msk (0x40000000UL) /*!< ECC ECC_COMMAND_REG: ECC_SignB (Bitfield-Mask: 0x01) */ -#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Pos (31UL) /*!< ECC ECC_COMMAND_REG: ECC_CalcR2 (Bit 31) */ -#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Msk (0x80000000UL) /*!< ECC ECC_COMMAND_REG: ECC_CalcR2 (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ECC_ECC_CONTROL_REG ---------------------------- */ -#define ECC_ECC_CONTROL_REG_ECC_Start_Pos (0UL) /*!< ECC ECC_CONTROL_REG: ECC_Start (Bit 0) */ -#define ECC_ECC_CONTROL_REG_ECC_Start_Msk (0x1UL) /*!< ECC ECC_CONTROL_REG: ECC_Start (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ECC_ECC_STATUS_REG ----------------------------- */ -#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Pos (0UL) /*!< ECC ECC_STATUS_REG: ECC_Fail_Address (Bit 0) */ -#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Msk (0xfUL) /*!< ECC ECC_STATUS_REG: ECC_Fail_Address (Bitfield-Mask: 0x0f) */ -#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Pos (4UL) /*!< ECC ECC_STATUS_REG: ECC_Point_Px_NotOnCurve (Bit 4) */ -#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Msk (0x10UL) /*!< ECC ECC_STATUS_REG: ECC_Point_Px_NotOnCurve (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Pos (5UL) /*!< ECC ECC_STATUS_REG: ECC_Point_Px_AtInfinity (Bit 5) */ -#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Msk (0x20UL) /*!< ECC ECC_STATUS_REG: ECC_Point_Px_AtInfinity (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Pos (6UL) /*!< ECC ECC_STATUS_REG: ECC_Couple_NotValid (Bit 6) */ -#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Msk (0x40UL) /*!< ECC ECC_STATUS_REG: ECC_Couple_NotValid (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Pos (7UL) /*!< ECC ECC_STATUS_REG: ECC_Param_n_NotValid (Bit 7) */ -#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Msk (0x80UL) /*!< ECC ECC_STATUS_REG: ECC_Param_n_NotValid (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Pos (9UL) /*!< ECC ECC_STATUS_REG: ECC_Signature_NotValid (Bit 9) */ -#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Msk (0x200UL) /*!< ECC ECC_STATUS_REG: ECC_Signature_NotValid (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Pos (10UL) /*!< ECC ECC_STATUS_REG: ECC_Param_AB_NotValid (Bit 10) */ -#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Msk (0x400UL) /*!< ECC ECC_STATUS_REG: ECC_Param_AB_NotValid (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Pos (11UL) /*!< ECC ECC_STATUS_REG: ECC_NotInvertible (Bit 11) */ -#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Msk (0x800UL) /*!< ECC ECC_STATUS_REG: ECC_NotInvertible (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Pos (12UL) /*!< ECC ECC_STATUS_REG: ECC_PrimalityTestResult (Bit 12) */ -#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Msk (0x1000UL) /*!< ECC ECC_STATUS_REG: ECC_PrimalityTestResult (Bitfield-Mask: 0x01) */ -#define ECC_ECC_STATUS_REG_ECC_Busy_Pos (16UL) /*!< ECC ECC_STATUS_REG: ECC_Busy (Bit 16) */ -#define ECC_ECC_STATUS_REG_ECC_Busy_Msk (0x10000UL) /*!< ECC ECC_STATUS_REG: ECC_Busy (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ECC_ECC_VERSION_REG ---------------------------- */ -#define ECC_ECC_VERSION_REG_ECC_SVN_Pos (0UL) /*!< ECC ECC_VERSION_REG: ECC_SVN (Bit 0) */ -#define ECC_ECC_VERSION_REG_ECC_SVN_Msk (0xffUL) /*!< ECC ECC_VERSION_REG: ECC_SVN (Bitfield-Mask: 0xff) */ -#define ECC_ECC_VERSION_REG_ECC_HVN_Pos (8UL) /*!< ECC ECC_VERSION_REG: ECC_HVN (Bit 8) */ -#define ECC_ECC_VERSION_REG_ECC_HVN_Msk (0xff00UL) /*!< ECC ECC_VERSION_REG: ECC_HVN (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'FTDF' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- FTDF_FTDF_TX_FIFO_0_0_REG ------------------------- */ -#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Pos (0UL) /*!< FTDF FTDF_TX_FIFO_0_0_REG: TX_FIFO (Bit 0) */ -#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_FIFO_0_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_TX_FIFO_1_0_REG ------------------------- */ -#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Pos (0UL) /*!< FTDF FTDF_TX_FIFO_1_0_REG: TX_FIFO (Bit 0) */ -#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_FIFO_1_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_TX_FIFO_2_0_REG ------------------------- */ -#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Pos (0UL) /*!< FTDF FTDF_TX_FIFO_2_0_REG: TX_FIFO (Bit 0) */ -#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_FIFO_2_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_TX_FIFO_3_0_REG ------------------------- */ -#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Pos (0UL) /*!< FTDF FTDF_TX_FIFO_3_0_REG: TX_FIFO (Bit 0) */ -#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_FIFO_3_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_0_0_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAME_LENGTH (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Msk (0x7fUL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Pos (7UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_DEM_PTI (Bit 7) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Msk (0x780UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Pos (11UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CN (Bit 11) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Msk (0x7800UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Pos (15UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CALCAP (Bit 15) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Msk (0x78000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Pos (22UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_HSI (Bit 22) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Msk (0x400000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Pos (23UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAMETYPE (Bit 23) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Msk (0x3800000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: FRAMETYPE (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Pos (26UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CSMACA_ENA (Bit 26) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Msk (0x4000000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Pos (28UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: ACKREQUEST (Bit 28) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Msk (0x10000000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: ACKREQUEST (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Pos (30UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CRC16_ENA (Bit 30) */ -#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Msk (0x40000000UL) /*!< FTDF FTDF_TX_META_DATA_0_0_REG: CRC16_ENA (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_1_0_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_1_0_REG: MACSN (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Msk (0xffUL) /*!< FTDF FTDF_TX_META_DATA_1_0_REG: MACSN (Bitfield-Mask: 0xff) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_0_1_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAME_LENGTH (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Msk (0x7fUL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Pos (7UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_DEM_PTI (Bit 7) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Msk (0x780UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Pos (11UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CN (Bit 11) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Msk (0x7800UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Pos (15UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CALCAP (Bit 15) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Msk (0x78000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Pos (22UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_HSI (Bit 22) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Msk (0x400000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Pos (23UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAMETYPE (Bit 23) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Msk (0x3800000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: FRAMETYPE (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Pos (26UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CSMACA_ENA (Bit 26) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Msk (0x4000000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Pos (28UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: ACKREQUEST (Bit 28) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Msk (0x10000000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: ACKREQUEST (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Pos (30UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CRC16_ENA (Bit 30) */ -#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Msk (0x40000000UL) /*!< FTDF FTDF_TX_META_DATA_0_1_REG: CRC16_ENA (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_1_1_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_1_1_REG: MACSN (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Msk (0xffUL) /*!< FTDF FTDF_TX_META_DATA_1_1_REG: MACSN (Bitfield-Mask: 0xff) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_0_2_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAME_LENGTH (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Msk (0x7fUL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Pos (7UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_DEM_PTI (Bit 7) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Msk (0x780UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Pos (11UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CN (Bit 11) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Msk (0x7800UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Pos (15UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CALCAP (Bit 15) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Msk (0x78000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Pos (22UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_HSI (Bit 22) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Msk (0x400000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Pos (23UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAMETYPE (Bit 23) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Msk (0x3800000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: FRAMETYPE (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Pos (26UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CSMACA_ENA (Bit 26) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Msk (0x4000000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Pos (28UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: ACKREQUEST (Bit 28) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Msk (0x10000000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: ACKREQUEST (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Pos (30UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CRC16_ENA (Bit 30) */ -#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Msk (0x40000000UL) /*!< FTDF FTDF_TX_META_DATA_0_2_REG: CRC16_ENA (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_1_2_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_1_2_REG: MACSN (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Msk (0xffUL) /*!< FTDF FTDF_TX_META_DATA_1_2_REG: MACSN (Bitfield-Mask: 0xff) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_0_3_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAME_LENGTH (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Msk (0x7fUL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Pos (7UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_DEM_PTI (Bit 7) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Msk (0x780UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Pos (11UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CN (Bit 11) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Msk (0x7800UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Pos (15UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CALCAP (Bit 15) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Msk (0x78000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Pos (19UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_RF_GPIO_PINS (Bit 19) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Msk (0x380000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Pos (22UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_HSI (Bit 22) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Msk (0x400000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_HSI (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Pos (23UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAMETYPE (Bit 23) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Msk (0x3800000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: FRAMETYPE (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Pos (26UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CSMACA_ENA (Bit 26) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Msk (0x4000000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CSMACA_ENA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Pos (28UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: ACKREQUEST (Bit 28) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Msk (0x10000000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: ACKREQUEST (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Pos (30UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CRC16_ENA (Bit 30) */ -#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Msk (0x40000000UL) /*!< FTDF FTDF_TX_META_DATA_0_3_REG: CRC16_ENA (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_META_DATA_1_3_REG ----------------------- */ -#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Pos (0UL) /*!< FTDF FTDF_TX_META_DATA_1_3_REG: MACSN (Bit 0) */ -#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Msk (0xffUL) /*!< FTDF FTDF_TX_META_DATA_1_3_REG: MACSN (Bitfield-Mask: 0xff) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_0_0_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_0_REG: TXTIMESTAMP (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_0_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_1_0_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: ACKFAIL (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Msk (0x1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: ACKFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Pos (1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACAFAIL (Bit 1) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Msk (0x2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Pos (2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACANRRETRIES (Bit 2) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_0_1_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_1_REG: TXTIMESTAMP (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_1_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_1_1_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: ACKFAIL (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Msk (0x1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: ACKFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Pos (1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACAFAIL (Bit 1) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Msk (0x2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Pos (2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACANRRETRIES (Bit 2) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_0_2_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_2_REG: TXTIMESTAMP (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_2_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_1_2_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: ACKFAIL (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Msk (0x1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: ACKFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Pos (1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACAFAIL (Bit 1) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Msk (0x2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Pos (2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACANRRETRIES (Bit 2) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_0_3_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_3_REG: TXTIMESTAMP (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_TX_RETURN_STATUS_0_3_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- FTDF_FTDF_TX_RETURN_STATUS_1_3_REG --------------------- */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Pos (0UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: ACKFAIL (Bit 0) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Msk (0x1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: ACKFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Pos (1UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACAFAIL (Bit 1) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Msk (0x2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACAFAIL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Pos (2UL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACANRRETRIES (Bit 2) */ -#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Msk (0x1cUL) /*!< FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_0_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_0_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_0_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_0_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_0_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_0_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_0_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_0_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_0_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_0_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_0_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_0_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_0_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_0_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_0_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_0_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_0_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_1_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_1_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_1_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_1_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_1_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_1_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_1_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_1_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_1_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_1_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_1_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_1_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_1_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_1_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_1_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_1_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_1_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_2_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_2_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_2_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_2_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_2_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_2_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_2_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_2_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_2_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_2_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_2_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_2_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_2_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_2_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_2_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_2_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_2_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_3_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_3_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_3_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_3_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_3_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_3_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_3_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_3_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_3_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_3_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_3_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_3_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_3_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_3_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_3_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_3_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_3_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_4_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_4_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_4_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_4_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_4_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_4_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_4_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_4_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_4_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_4_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_4_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_4_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_4_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_4_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_4_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_4_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_4_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_5_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_5_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_5_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_5_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_5_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_5_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_5_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_5_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_5_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_5_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_5_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_5_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_5_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_5_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_5_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_5_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_5_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_6_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_6_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_6_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_6_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_6_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_6_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_6_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_6_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_6_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_6_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_6_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_6_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_6_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_6_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_6_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_6_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_6_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_META_0_7_REG ------------------------- */ -#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Pos (0UL) /*!< FTDF FTDF_RX_META_0_7_REG: RX_TIMESTAMP (Bit 0) */ -#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_META_0_7_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_META_1_7_REG ------------------------- */ -#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Pos (0UL) /*!< FTDF FTDF_RX_META_1_7_REG: CRC16_ERROR (Bit 0) */ -#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Msk (0x1UL) /*!< FTDF FTDF_RX_META_1_7_REG: CRC16_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Pos (2UL) /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_TYPE_ERROR (Bit 2) */ -#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Msk (0x4UL) /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Pos (3UL) /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_VERSION_ERROR (Bit 3) */ -#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Msk (0x8UL) /*!< FTDF FTDF_RX_META_1_7_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Pos (4UL) /*!< FTDF FTDF_RX_META_1_7_REG: DPANID_ERROR (Bit 4) */ -#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Msk (0x10UL) /*!< FTDF FTDF_RX_META_1_7_REG: DPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Pos (5UL) /*!< FTDF FTDF_RX_META_1_7_REG: DADDR_ERROR (Bit 5) */ -#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Msk (0x20UL) /*!< FTDF FTDF_RX_META_1_7_REG: DADDR_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Pos (6UL) /*!< FTDF FTDF_RX_META_1_7_REG: SPANID_ERROR (Bit 6) */ -#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Msk (0x40UL) /*!< FTDF FTDF_RX_META_1_7_REG: SPANID_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Pos (7UL) /*!< FTDF FTDF_RX_META_1_7_REG: ISPANID_COORD_ERROR (Bit 7) */ -#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Msk (0x80UL) /*!< FTDF FTDF_RX_META_1_7_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Pos (8UL) /*!< FTDF FTDF_RX_META_1_7_REG: QUALITY_INDICATOR (Bit 8) */ -#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Msk (0xff00UL) /*!< FTDF FTDF_RX_META_1_7_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_0_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_0_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_0_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_1_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_1_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_1_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_2_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_2_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_2_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_3_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_3_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_3_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_4_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_4_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_4_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_5_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_5_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_5_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_6_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_6_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_6_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_RX_FIFO_7_0_REG ------------------------- */ -#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Pos (0UL) /*!< FTDF FTDF_RX_FIFO_7_0_REG: RX_FIFO (Bit 0) */ -#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Msk (0xffffffffUL) /*!< FTDF FTDF_RX_FIFO_7_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_REL_NAME_0_REG -------------------------- */ -#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Pos (0UL) /*!< FTDF FTDF_REL_NAME_0_REG: REL_NAME (Bit 0) */ -#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Msk (0xffffffffUL) /*!< FTDF FTDF_REL_NAME_0_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_REL_NAME_1_REG -------------------------- */ -#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Pos (0UL) /*!< FTDF FTDF_REL_NAME_1_REG: REL_NAME (Bit 0) */ -#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Msk (0xffffffffUL) /*!< FTDF FTDF_REL_NAME_1_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_REL_NAME_2_REG -------------------------- */ -#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Pos (0UL) /*!< FTDF FTDF_REL_NAME_2_REG: REL_NAME (Bit 0) */ -#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Msk (0xffffffffUL) /*!< FTDF FTDF_REL_NAME_2_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_REL_NAME_3_REG -------------------------- */ -#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Pos (0UL) /*!< FTDF FTDF_REL_NAME_3_REG: REL_NAME (Bit 0) */ -#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Msk (0xffffffffUL) /*!< FTDF FTDF_REL_NAME_3_REG: REL_NAME (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_BUILDTIME_0_REG ------------------------- */ -#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Pos (0UL) /*!< FTDF FTDF_BUILDTIME_0_REG: BUILDTIME (Bit 0) */ -#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Msk (0xffffffffUL) /*!< FTDF FTDF_BUILDTIME_0_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_BUILDTIME_1_REG ------------------------- */ -#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Pos (0UL) /*!< FTDF FTDF_BUILDTIME_1_REG: BUILDTIME (Bit 0) */ -#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Msk (0xffffffffUL) /*!< FTDF FTDF_BUILDTIME_1_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_BUILDTIME_2_REG ------------------------- */ -#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Pos (0UL) /*!< FTDF FTDF_BUILDTIME_2_REG: BUILDTIME (Bit 0) */ -#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Msk (0xffffffffUL) /*!< FTDF FTDF_BUILDTIME_2_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_BUILDTIME_3_REG ------------------------- */ -#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Pos (0UL) /*!< FTDF FTDF_BUILDTIME_3_REG: BUILDTIME (Bit 0) */ -#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Msk (0xffffffffUL) /*!< FTDF FTDF_BUILDTIME_3_REG: BUILDTIME (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_GLOB_CONTROL_0_REG ------------------------ */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Pos (1UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: ISPANCOORDINATOR (Bit 1) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Msk (0x2UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: ISPANCOORDINATOR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Pos (2UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: RX_DMA_REQ (Bit 2) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Msk (0x4UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: RX_DMA_REQ (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Pos (3UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: TX_DMA_REQ (Bit 3) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Msk (0x8UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: TX_DMA_REQ (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Pos (8UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACSIMPLEADDRESS (Bit 8) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Msk (0xff00UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACSIMPLEADDRESS (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Pos (17UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACLEENABLED (Bit 17) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Msk (0x20000UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACLEENABLED (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Pos (18UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACTSCHENABLED (Bit 18) */ -#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Msk (0x40000UL) /*!< FTDF FTDF_GLOB_CONTROL_0_REG: MACTSCHENABLED (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_GLOB_CONTROL_1_REG ------------------------ */ -#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Pos (0UL) /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACPANID (Bit 0) */ -#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Msk (0xffffUL) /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACPANID (Bitfield-Mask: 0xffff) */ -#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Pos (16UL) /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACSHORTADDRESS (Bit 16) */ -#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Msk (0xffff0000UL) /*!< FTDF FTDF_GLOB_CONTROL_1_REG: MACSHORTADDRESS (Bitfield-Mask: 0xffff) */ - -/* ------------------------ FTDF_FTDF_GLOB_CONTROL_2_REG ------------------------ */ -#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Pos (0UL) /*!< FTDF FTDF_GLOB_CONTROL_2_REG: AEXTENDEDADDRESS_L (Bit 0) */ -#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Msk (0xffffffffUL) /*!< FTDF FTDF_GLOB_CONTROL_2_REG: AEXTENDEDADDRESS_L (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_GLOB_CONTROL_3_REG ------------------------ */ -#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Pos (0UL) /*!< FTDF FTDF_GLOB_CONTROL_3_REG: AEXTENDEDADDRESS_H (Bit 0) */ -#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Msk (0xffffffffUL) /*!< FTDF FTDF_GLOB_CONTROL_3_REG: AEXTENDEDADDRESS_H (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_0_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Pos (1UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXONDURATION (Bit 1) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Msk (0x1fffffeUL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXONDURATION (Bitfield-Mask: 0xffffff) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Pos (25UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bit 25) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Msk (0x2000000UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Pos (27UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bit 27) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Msk (0x78000000UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Pos (31UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bit 31) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Msk (0x80000000UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_TXPIPEPROPDELAY_REG ----------------------- */ -#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Pos (0UL) /*!< FTDF FTDF_TXPIPEPROPDELAY_REG: TXPIPEPROPDELAY (Bit 0) */ -#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Msk (0xffUL) /*!< FTDF FTDF_TXPIPEPROPDELAY_REG: TXPIPEPROPDELAY (Bitfield-Mask: 0xff) */ - -/* ---------------------- FTDF_FTDF_MACACKWAITDURATION_REG ---------------------- */ -#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Pos (0UL) /*!< FTDF FTDF_MACACKWAITDURATION_REG: MACACKWAITDURATION (Bit 0) */ -#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Msk (0xffUL) /*!< FTDF FTDF_MACACKWAITDURATION_REG: MACACKWAITDURATION (Bitfield-Mask: 0xff) */ - -/* --------------------- FTDF_FTDF_MACENHACKWAITDURATION_REG -------------------- */ -#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Pos (0UL) /*!< FTDF FTDF_MACENHACKWAITDURATION_REG: MACENHACKWAITDURATION (Bit 0) */ -#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Msk (0xffffUL) /*!< FTDF FTDF_MACENHACKWAITDURATION_REG: MACENHACKWAITDURATION (Bitfield-Mask: 0xffff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_1_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_DEM_PTI (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Msk (0xfUL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Pos (4UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CN (Bit 4) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Msk (0xf0UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Pos (8UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CALCAP (Bit 8) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Msk (0xf00UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Pos (12UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_RF_GPIO_PINS (Bit 12) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Msk (0x7000UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Pos (15UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_HSI (Bit 15) */ -#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Msk (0x8000UL) /*!< FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_HSI (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_2_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANENABLE (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Msk (0x1UL) /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANENABLE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Pos (8UL) /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANDURATION (Bit 8) */ -#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Msk (0xffffff00UL) /*!< FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANDURATION (Bitfield-Mask: 0xffffff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_3_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: MACMAXFRAMETOTALWAITTIME (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: MACMAXFRAMETOTALWAITTIME (Bitfield-Mask: 0xffff) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Msk (0xff0000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bit 24) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Msk (0x1000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Pos (25UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bit 25) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Msk (0x2000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Pos (26UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bit 26) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Msk (0x4000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Pos (27UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bit 27) */ -#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Msk (0x8000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_OS_REG ----------------------- */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: GETGENERATORVAL (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Msk (0x1UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: GETGENERATORVAL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Pos (1UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: RXENABLE (Bit 1) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Msk (0x2UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: RXENABLE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Pos (2UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bit 2) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Msk (0x4UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Pos (3UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bit 3) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Msk (0x8UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Pos (4UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bit 4) */ -#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Msk (0x10UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bitfield-Mask: 0x01) */ - -/* ---------------------- FTDF_FTDF_LMAC_CONTROL_STATUS_REG --------------------- */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Pos (1UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: LMACREADY4SLEEP (Bit 1) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Msk (0x2UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: LMACREADY4SLEEP (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Pos (2UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CCASTAT (Bit 2) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Msk (0x4UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CCASTAT (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Pos (6UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: WAKEUPTIMERENABLESTATUS (Bit 6) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Msk (0x40UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: WAKEUPTIMERENABLESTATUS (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Pos (8UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bit 8) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Msk (0xff00UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Msk (0x70000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Pos (19UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bit 19) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Msk (0x80000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bit 24) */ -#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Msk (0xff000000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bitfield-Mask: 0xff) */ - -/* ------------------------- FTDF_FTDF_EVENTCURRVAL_REG ------------------------- */ -#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Pos (0UL) /*!< FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bit 0) */ -#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Msk (0x1ffffffUL) /*!< FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bitfield-Mask: 0x1ffffff) */ - -/* ----------------------- FTDF_FTDF_TIMESTAMPCURRVAL_REG ----------------------- */ -#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Pos (0UL) /*!< FTDF FTDF_TIMESTAMPCURRVAL_REG: TIMESTAMPCURRVAL (Bit 0) */ -#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Msk (0xffffffffUL) /*!< FTDF FTDF_TIMESTAMPCURRVAL_REG: TIMESTAMPCURRVAL (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_4_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYSLEEPWAIT (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Msk (0xffUL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYSLEEPWAIT (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Pos (8UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: RXPIPEPROPDELAY (Bit 8) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Msk (0xff00UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: RXPIPEPROPDELAY (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_DEM_PTI (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Msk (0xf0000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Pos (20UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CN (Bit 20) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Msk (0xf00000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CALCAP (Bit 24) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Msk (0xf000000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Pos (28UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_RF_GPIO_PINS (Bit 28) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Msk (0x70000000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Pos (31UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_HSI (Bit 31) */ -#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Msk (0x80000000UL) /*!< FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_HSI (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_5_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: ACK_RESPONSE_DELAY (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Msk (0xffUL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: ACK_RESPONSE_DELAY (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Pos (8UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: CCASTATWAIT (Bit 8) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Msk (0xf00UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: CCASTATWAIT (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_DEM_PTI (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Msk (0xf0000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Pos (20UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CN (Bit 20) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Msk (0xf00000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CALCAP (Bit 24) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Msk (0xf000000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Pos (28UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_RF_GPIO_PINS (Bit 28) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Msk (0x70000000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Pos (31UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_HSI (Bit 31) */ -#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Msk (0x80000000UL) /*!< FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_HSI (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_6_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_6_REG: LIFSPERIOD (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Msk (0xffUL) /*!< FTDF FTDF_LMAC_CONTROL_6_REG: LIFSPERIOD (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Pos (8UL) /*!< FTDF FTDF_LMAC_CONTROL_6_REG: SIFSPERIOD (Bit 8) */ -#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Msk (0xff00UL) /*!< FTDF FTDF_LMAC_CONTROL_6_REG: SIFSPERIOD (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_6_REG: WUIFSPERIOD (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Msk (0xff0000UL) /*!< FTDF FTDF_LMAC_CONTROL_6_REG: WUIFSPERIOD (Bitfield-Mask: 0xff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_11_REG ----------------------- */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACRXTOTALCYCLETIME (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACRXTOTALCYCLETIME (Bitfield-Mask: 0xffff) */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Msk (0x10000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Pos (17UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bit 17) */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Msk (0xe0000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bit 24) */ -#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Msk (0xff000000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bitfield-Mask: 0xff) */ - -/* ---------------------- FTDF_FTDF_LMAC_CONTROL_DELTA_REG ---------------------- */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Pos (1UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: LMACREADY4SLEEP_D (Bit 1) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Msk (0x2UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: LMACREADY4SLEEP_D (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Pos (2UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYNCTIMESTAMP_E (Bit 2) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Msk (0x4UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYNCTIMESTAMP_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Pos (3UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIMETHR_E (Bit 3) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Msk (0x8UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIMETHR_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Pos (4UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIME2THR_E (Bit 4) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Msk (0x10UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIME2THR_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Pos (5UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: GETGENERATORVAL_E (Bit 5) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Msk (0x20UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: GETGENERATORVAL_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Pos (6UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: WAKEUPTIMERENABLESTATUS_D (Bit 6) */ -#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Msk (0x40UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: WAKEUPTIMERENABLESTATUS_D (Bitfield-Mask: 0x01) */ - -/* --------------------- FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG -------------------- */ -#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Pos (0UL) /*!< FTDF FTDF_TIMESTAMPCURRPHASEVAL_REG: TIMESTAMPCURRPHASEVAL (Bit 0) */ -#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Msk (0xffUL) /*!< FTDF FTDF_TIMESTAMPCURRPHASEVAL_REG: TIMESTAMPCURRPHASEVAL (Bitfield-Mask: 0xff) */ - -/* ---------------------- FTDF_FTDF_MACTSTXACKDELAYVAL_REG ---------------------- */ -#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Pos (0UL) /*!< FTDF FTDF_MACTSTXACKDELAYVAL_REG: MACTSTXACKDELAYVAL (Bit 0) */ -#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Msk (0xffffUL) /*!< FTDF FTDF_MACTSTXACKDELAYVAL_REG: MACTSTXACKDELAYVAL (Bitfield-Mask: 0xffff) */ - -/* ----------------------- FTDF_FTDF_LMAC_CONTROL_MASK_REG ---------------------- */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Pos (1UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: LMACREADY4SLEEP_M (Bit 1) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Msk (0x2UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: LMACREADY4SLEEP_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Pos (2UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYNCTIMESTAMP_M (Bit 2) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Msk (0x4UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYNCTIMESTAMP_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Pos (3UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIMETHR_M (Bit 3) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Msk (0x8UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIMETHR_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Pos (4UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIME2THR_M (Bit 4) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Msk (0x10UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIME2THR_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Pos (5UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: GETGENERATORVAL_M (Bit 5) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Msk (0x20UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: GETGENERATORVAL_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Pos (6UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: WAKEUPTIMERENABLESTATUS_M (Bit 6) */ -#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Msk (0x40UL) /*!< FTDF FTDF_LMAC_CONTROL_MASK_REG: WAKEUPTIMERENABLESTATUS_M (Bitfield-Mask: 0x01) */ - -/* -------------------------- FTDF_FTDF_LMAC_EVENT_REG -------------------------- */ -#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Pos (0UL) /*!< FTDF FTDF_LMAC_EVENT_REG: EDSCANREADY_E (Bit 0) */ -#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Msk (0x1UL) /*!< FTDF FTDF_LMAC_EVENT_REG: EDSCANREADY_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Pos (1UL) /*!< FTDF FTDF_LMAC_EVENT_REG: CCASTAT_E (Bit 1) */ -#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Msk (0x2UL) /*!< FTDF FTDF_LMAC_EVENT_REG: CCASTAT_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Pos (2UL) /*!< FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bit 2) */ -#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Msk (0x4UL) /*!< FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Pos (3UL) /*!< FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bit 3) */ -#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Msk (0x8UL) /*!< FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bitfield-Mask: 0x01) */ - -/* --------------------------- FTDF_FTDF_LMAC_MASK_REG -------------------------- */ -#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Pos (0UL) /*!< FTDF FTDF_LMAC_MASK_REG: EDSCANREADY_M (Bit 0) */ -#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Msk (0x1UL) /*!< FTDF FTDF_LMAC_MASK_REG: EDSCANREADY_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Pos (1UL) /*!< FTDF FTDF_LMAC_MASK_REG: CCASTAT_M (Bit 1) */ -#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Msk (0x2UL) /*!< FTDF FTDF_LMAC_MASK_REG: CCASTAT_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Pos (2UL) /*!< FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bit 2) */ -#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Msk (0x4UL) /*!< FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Pos (3UL) /*!< FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bit 3) */ -#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Msk (0x8UL) /*!< FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_LMAC_MANUAL_1_REG ------------------------ */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Pos (0UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_MODE (Bit 0) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Msk (0x1UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_MODE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Pos (1UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_EN (Bit 1) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Msk (0x2UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_EN (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Pos (2UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_EN (Bit 2) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Msk (0x4UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_EN (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Pos (3UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_EN (Bit 3) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Msk (0x8UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_EN (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Pos (4UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_PIPE_EN (Bit 4) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Msk (0x10UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_PIPE_EN (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Pos (5UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_ED_REQUEST (Bit 5) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Msk (0x20UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_ED_REQUEST (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Pos (6UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_FRM_NR (Bit 6) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Msk (0xc0UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_FRM_NR (Bitfield-Mask: 0x03) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Pos (8UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PTI (Bit 8) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Msk (0xf00UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Pos (16UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_DEM_PTI (Bit 16) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Msk (0xf0000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_DEM_PTI (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Pos (20UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CN (Bit 20) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Msk (0xf00000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CN (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Pos (24UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CALCAP (Bit 24) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Msk (0xf000000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CALCAP (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Pos (28UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS (Bit 28) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Msk (0x70000000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Pos (31UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_HSI (Bit 31) */ -#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Msk (0x80000000UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_HSI (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_LMAC_MANUAL_OS_REG ------------------------ */ -#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Pos (0UL) /*!< FTDF FTDF_LMAC_MANUAL_OS_REG: LMAC_MANUAL_TX_START (Bit 0) */ -#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Msk (0x1UL) /*!< FTDF FTDF_LMAC_MANUAL_OS_REG: LMAC_MANUAL_TX_START (Bitfield-Mask: 0x01) */ - -/* ---------------------- FTDF_FTDF_LMAC_MANUAL_STATUS_REG ---------------------- */ -#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Pos (0UL) /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_CCA_STAT (Bit 0) */ -#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Msk (0x1UL) /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_CCA_STAT (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Pos (8UL) /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_ED_STAT (Bit 8) */ -#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Msk (0xff00UL) /*!< FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_ED_STAT (Bitfield-Mask: 0xff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_7_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACWUPERIOD (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACWUPERIOD (Bitfield-Mask: 0xffff) */ -#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACCSLSAMPLEPERIOD (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Msk (0xffff0000UL) /*!< FTDF FTDF_LMAC_CONTROL_7_REG: MACCSLSAMPLEPERIOD (Bitfield-Mask: 0xffff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_8_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_8_REG: MACCSLSTARTSAMPLETIME (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Msk (0xffffffffUL) /*!< FTDF FTDF_LMAC_CONTROL_8_REG: MACCSLSTARTSAMPLETIME (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_9_REG ------------------------ */ -#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLDATAPERIOD (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLDATAPERIOD (Bitfield-Mask: 0xffff) */ -#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLFRAMEPENDINGWAITT (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Msk (0xffff0000UL) /*!< FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLFRAMEPENDINGWAITT (Bitfield-Mask: 0xffff) */ - -/* ------------------------ FTDF_FTDF_LMAC_CONTROL_10_REG ----------------------- */ -#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACWURZCORRECTION (Bit 0) */ -#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Msk (0xffUL) /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACWURZCORRECTION (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACCSLMARGINRZ (Bit 16) */ -#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Msk (0xf0000UL) /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACCSLMARGINRZ (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Pos (28UL) /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACRZZEROVAL (Bit 28) */ -#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Msk (0xf0000000UL) /*!< FTDF FTDF_LMAC_CONTROL_10_REG: MACRZZEROVAL (Bitfield-Mask: 0x0f) */ - -/* -------------------------- FTDF_FTDF_SECURITY_0_REG -------------------------- */ -#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Pos (1UL) /*!< FTDF FTDF_SECURITY_0_REG: SECTXRXN (Bit 1) */ -#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Msk (0x2UL) /*!< FTDF FTDF_SECURITY_0_REG: SECTXRXN (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Pos (8UL) /*!< FTDF FTDF_SECURITY_0_REG: SECENTRY (Bit 8) */ -#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Msk (0xf00UL) /*!< FTDF FTDF_SECURITY_0_REG: SECENTRY (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Pos (16UL) /*!< FTDF FTDF_SECURITY_0_REG: SECALENGTH (Bit 16) */ -#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Msk (0x7f0000UL) /*!< FTDF FTDF_SECURITY_0_REG: SECALENGTH (Bitfield-Mask: 0x7f) */ -#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Pos (24UL) /*!< FTDF FTDF_SECURITY_0_REG: SECMLENGTH (Bit 24) */ -#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Msk (0x7f000000UL) /*!< FTDF FTDF_SECURITY_0_REG: SECMLENGTH (Bitfield-Mask: 0x7f) */ -#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Pos (31UL) /*!< FTDF FTDF_SECURITY_0_REG: SECENCDECN (Bit 31) */ -#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Msk (0x80000000UL) /*!< FTDF FTDF_SECURITY_0_REG: SECENCDECN (Bitfield-Mask: 0x01) */ - -/* -------------------------- FTDF_FTDF_SECURITY_1_REG -------------------------- */ -#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Pos (0UL) /*!< FTDF FTDF_SECURITY_1_REG: SECAUTHFLAGS (Bit 0) */ -#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Msk (0xffUL) /*!< FTDF FTDF_SECURITY_1_REG: SECAUTHFLAGS (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Pos (8UL) /*!< FTDF FTDF_SECURITY_1_REG: SECENCRFLAGS (Bit 8) */ -#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Msk (0xff00UL) /*!< FTDF FTDF_SECURITY_1_REG: SECENCRFLAGS (Bitfield-Mask: 0xff) */ - -/* --------------------------- FTDF_FTDF_SECKEY_0_REG --------------------------- */ -#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Pos (0UL) /*!< FTDF FTDF_SECKEY_0_REG: SECKEY_0 (Bit 0) */ -#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Msk (0xffffffffUL) /*!< FTDF FTDF_SECKEY_0_REG: SECKEY_0 (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- FTDF_FTDF_SECKEY_1_REG --------------------------- */ -#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Pos (0UL) /*!< FTDF FTDF_SECKEY_1_REG: SECKEY_1 (Bit 0) */ -#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Msk (0xffffffffUL) /*!< FTDF FTDF_SECKEY_1_REG: SECKEY_1 (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- FTDF_FTDF_SECKEY_2_REG --------------------------- */ -#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Pos (0UL) /*!< FTDF FTDF_SECKEY_2_REG: SECKEY_2 (Bit 0) */ -#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Msk (0xffffffffUL) /*!< FTDF FTDF_SECKEY_2_REG: SECKEY_2 (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- FTDF_FTDF_SECKEY_3_REG --------------------------- */ -#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Pos (0UL) /*!< FTDF FTDF_SECKEY_3_REG: SECKEY_3 (Bit 0) */ -#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Msk (0xffffffffUL) /*!< FTDF FTDF_SECKEY_3_REG: SECKEY_3 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_SECNONCE_0_REG -------------------------- */ -#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Pos (0UL) /*!< FTDF FTDF_SECNONCE_0_REG: SECNONCE_0 (Bit 0) */ -#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Msk (0xffffffffUL) /*!< FTDF FTDF_SECNONCE_0_REG: SECNONCE_0 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_SECNONCE_1_REG -------------------------- */ -#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Pos (0UL) /*!< FTDF FTDF_SECNONCE_1_REG: SECNONCE_1 (Bit 0) */ -#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Msk (0xffffffffUL) /*!< FTDF FTDF_SECNONCE_1_REG: SECNONCE_1 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_SECNONCE_2_REG -------------------------- */ -#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Pos (0UL) /*!< FTDF FTDF_SECNONCE_2_REG: SECNONCE_2 (Bit 0) */ -#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Msk (0xffffffffUL) /*!< FTDF FTDF_SECNONCE_2_REG: SECNONCE_2 (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- FTDF_FTDF_SECNONCE_3_REG -------------------------- */ -#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Pos (0UL) /*!< FTDF FTDF_SECNONCE_3_REG: SECNONCE_3 (Bit 0) */ -#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Msk (0xffUL) /*!< FTDF FTDF_SECNONCE_3_REG: SECNONCE_3 (Bitfield-Mask: 0xff) */ - -/* -------------------------- FTDF_FTDF_SECURITY_OS_REG ------------------------- */ -#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Pos (0UL) /*!< FTDF FTDF_SECURITY_OS_REG: SECABORT (Bit 0) */ -#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Msk (0x1UL) /*!< FTDF FTDF_SECURITY_OS_REG: SECABORT (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Pos (1UL) /*!< FTDF FTDF_SECURITY_OS_REG: SECSTART (Bit 1) */ -#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Msk (0x2UL) /*!< FTDF FTDF_SECURITY_OS_REG: SECSTART (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_SECURITY_STATUS_REG ----------------------- */ -#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Pos (0UL) /*!< FTDF FTDF_SECURITY_STATUS_REG: SECBUSY (Bit 0) */ -#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Msk (0x1UL) /*!< FTDF FTDF_SECURITY_STATUS_REG: SECBUSY (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Pos (1UL) /*!< FTDF FTDF_SECURITY_STATUS_REG: SECAUTHFAIL (Bit 1) */ -#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Msk (0x2UL) /*!< FTDF FTDF_SECURITY_STATUS_REG: SECAUTHFAIL (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_SECURITY_EVENT_REG ------------------------ */ -#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Pos (0UL) /*!< FTDF FTDF_SECURITY_EVENT_REG: SECREADY_E (Bit 0) */ -#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Msk (0x1UL) /*!< FTDF FTDF_SECURITY_EVENT_REG: SECREADY_E (Bitfield-Mask: 0x01) */ - -/* ---------------------- FTDF_FTDF_SECURITY_EVENTMASK_REG ---------------------- */ -#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Pos (0UL) /*!< FTDF FTDF_SECURITY_EVENTMASK_REG: SECREADY_M (Bit 0) */ -#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Msk (0x1UL) /*!< FTDF FTDF_SECURITY_EVENTMASK_REG: SECREADY_M (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_TSCH_CONTROL_0_REG ------------------------ */ -#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Pos (0UL) /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSTXACKDELAY (Bit 0) */ -#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Msk (0xffffUL) /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSTXACKDELAY (Bitfield-Mask: 0xffff) */ -#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Pos (16UL) /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSRXWAIT (Bit 16) */ -#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Msk (0xffff0000UL) /*!< FTDF FTDF_TSCH_CONTROL_0_REG: MACTSRXWAIT (Bitfield-Mask: 0xffff) */ - -/* ------------------------ FTDF_FTDF_TSCH_CONTROL_1_REG ------------------------ */ -#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Pos (0UL) /*!< FTDF FTDF_TSCH_CONTROL_1_REG: MACTSRXTX (Bit 0) */ -#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Msk (0xffffUL) /*!< FTDF FTDF_TSCH_CONTROL_1_REG: MACTSRXTX (Bitfield-Mask: 0xffff) */ - -/* ------------------------ FTDF_FTDF_TSCH_CONTROL_2_REG ------------------------ */ -#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Pos (0UL) /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSRXACKDELAY (Bit 0) */ -#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Msk (0xffffUL) /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSRXACKDELAY (Bitfield-Mask: 0xffff) */ -#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Pos (16UL) /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSACKWAIT (Bit 16) */ -#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Msk (0xffff0000UL) /*!< FTDF FTDF_TSCH_CONTROL_2_REG: MACTSACKWAIT (Bitfield-Mask: 0xffff) */ - -/* ----------------------- FTDF_FTDF_PHY_PARAMETERS_0_REG ----------------------- */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Pos (0UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_0 (Bit 0) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Msk (0x7UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_0 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Pos (4UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_1 (Bit 4) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Msk (0x70UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_1 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Pos (8UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_2 (Bit 8) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Msk (0x700UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_2 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Pos (12UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_3 (Bit 12) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Msk (0x7000UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_3 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Pos (16UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_4 (Bit 16) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Msk (0x70000UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_4 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Pos (20UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_5 (Bit 20) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Msk (0x700000UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_5 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Pos (24UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_6 (Bit 24) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Msk (0x7000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_6 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Pos (28UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_7 (Bit 28) */ -#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Msk (0x70000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_7 (Bitfield-Mask: 0x07) */ - -/* ----------------------- FTDF_FTDF_PHY_PARAMETERS_1_REG ----------------------- */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Pos (0UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_0 (Bit 0) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Msk (0x7UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_0 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Pos (4UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_1 (Bit 4) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Msk (0x70UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_1 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Pos (8UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_2 (Bit 8) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Msk (0x700UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_2 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Pos (12UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_3 (Bit 12) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Msk (0x7000UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_3 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Pos (16UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_4 (Bit 16) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Msk (0x70000UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_4 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Pos (20UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_5 (Bit 20) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Msk (0x700000UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_5 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Pos (24UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_6 (Bit 24) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Msk (0x7000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_6 (Bitfield-Mask: 0x07) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Pos (28UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_7 (Bit 28) */ -#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Msk (0x70000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_7 (Bitfield-Mask: 0x07) */ - -/* ----------------------- FTDF_FTDF_PHY_PARAMETERS_2_REG ----------------------- */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Pos (0UL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXSTARTUP (Bit 0) */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Msk (0xffUL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXSTARTUP (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Pos (8UL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXLATENCY (Bit 8) */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Msk (0xff00UL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXLATENCY (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Pos (16UL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXFINISH (Bit 16) */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Msk (0xff0000UL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXFINISH (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Pos (24UL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTRXWAIT (Bit 24) */ -#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Msk (0xff000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTRXWAIT (Bitfield-Mask: 0xff) */ - -/* ----------------------- FTDF_FTDF_PHY_PARAMETERS_3_REG ----------------------- */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Pos (0UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXSTARTUP (Bit 0) */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Msk (0xffUL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXSTARTUP (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Pos (8UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXLATENCY (Bit 8) */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Msk (0xff00UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXLATENCY (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Pos (16UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bit 16) */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Msk (0xff0000UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Pos (24UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bit 24) */ -#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Msk (0x1000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_RX_CONTROL_0_REG ------------------------- */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Pos (0UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DBGRXTRANSPARENTMODE (Bit 0) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Msk (0x1UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DBGRXTRANSPARENTMODE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Pos (1UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: RXBEACONONLY (Bit 1) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Msk (0x2UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: RXBEACONONLY (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Pos (2UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: RXCOORDREALIGNONLY (Bit 2) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Msk (0x4UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: RXCOORDREALIGNONLY (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Pos (3UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: RX_READ_BUF_PTR (Bit 3) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Msk (0x78UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: RX_READ_BUF_PTR (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Pos (7UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXFRMPENDINGCA (Bit 7) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Msk (0x80UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXFRMPENDINGCA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Pos (8UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKREQUESTCA (Bit 8) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Msk (0x100UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKREQUESTCA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Pos (9UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSCRCERROR (Bit 9) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Msk (0x200UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSCRCERROR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Pos (10UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISDATAREQUESTCA (Bit 10) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Msk (0x400UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISDATAREQUESTCA (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Pos (11UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSRESFRAMEVERSION (Bit 11) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Msk (0x800UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSRESFRAMEVERSION (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Pos (12UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDPANID (Bit 12) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Msk (0x1000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDPANID (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Pos (13UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDADDR (Bit 13) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Msk (0x2000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDADDR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Pos (14UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSBEACONWRONGPANID (Bit 14) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Msk (0x4000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSBEACONWRONGPANID (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Pos (15UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSTOPANCOORDINATOR (Bit 15) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Msk (0x8000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSTOPANCOORDINATOR (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Pos (16UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSFRMTYPE (Bit 16) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Msk (0xff0000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSFRMTYPE (Bitfield-Mask: 0xff) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Pos (24UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWAKEUP (Bit 24) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Msk (0x1000000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWAKEUP (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Pos (25UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACPASSWAKEUP (Bit 25) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Msk (0x2000000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACPASSWAKEUP (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Pos (26UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACIMPLICITBROADCAST (Bit 26) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Msk (0x4000000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: MACIMPLICITBROADCAST (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Pos (27UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKRECEIVEDCA (Bit 27) */ -#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Msk (0x8000000UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DISRXACKRECEIVEDCA (Bitfield-Mask: 0x01) */ - -/* --------------------------- FTDF_FTDF_RX_EVENT_REG --------------------------- */ -#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Pos (0UL) /*!< FTDF FTDF_RX_EVENT_REG: RXSOF_E (Bit 0) */ -#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Msk (0x1UL) /*!< FTDF FTDF_RX_EVENT_REG: RXSOF_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Pos (1UL) /*!< FTDF FTDF_RX_EVENT_REG: RX_OVERFLOW_E (Bit 1) */ -#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Msk (0x2UL) /*!< FTDF FTDF_RX_EVENT_REG: RX_OVERFLOW_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Pos (2UL) /*!< FTDF FTDF_RX_EVENT_REG: RX_BUF_AVAIL_E (Bit 2) */ -#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Msk (0x4UL) /*!< FTDF FTDF_RX_EVENT_REG: RX_BUF_AVAIL_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Pos (3UL) /*!< FTDF FTDF_RX_EVENT_REG: RXBYTE_E (Bit 3) */ -#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Msk (0x8UL) /*!< FTDF FTDF_RX_EVENT_REG: RXBYTE_E (Bitfield-Mask: 0x01) */ - -/* ---------------------------- FTDF_FTDF_RX_MASK_REG --------------------------- */ -#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Pos (0UL) /*!< FTDF FTDF_RX_MASK_REG: RXSOF_M (Bit 0) */ -#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Msk (0x1UL) /*!< FTDF FTDF_RX_MASK_REG: RXSOF_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Pos (1UL) /*!< FTDF FTDF_RX_MASK_REG: RX_OVERFLOW_M (Bit 1) */ -#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Msk (0x2UL) /*!< FTDF FTDF_RX_MASK_REG: RX_OVERFLOW_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Pos (2UL) /*!< FTDF FTDF_RX_MASK_REG: RX_BUF_AVAIL_M (Bit 2) */ -#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Msk (0x4UL) /*!< FTDF FTDF_RX_MASK_REG: RX_BUF_AVAIL_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Pos (3UL) /*!< FTDF FTDF_RX_MASK_REG: RXBYTE_M (Bit 3) */ -#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Msk (0x8UL) /*!< FTDF FTDF_RX_MASK_REG: RXBYTE_M (Bitfield-Mask: 0x01) */ - -/* --------------------------- FTDF_FTDF_RX_STATUS_REG -------------------------- */ -#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Pos (0UL) /*!< FTDF FTDF_RX_STATUS_REG: RX_BUFF_IS_FULL (Bit 0) */ -#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Msk (0x1UL) /*!< FTDF FTDF_RX_STATUS_REG: RX_BUFF_IS_FULL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Pos (1UL) /*!< FTDF FTDF_RX_STATUS_REG: RX_WRITE_BUF_PTR (Bit 1) */ -#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Msk (0x1eUL) /*!< FTDF FTDF_RX_STATUS_REG: RX_WRITE_BUF_PTR (Bitfield-Mask: 0x0f) */ - -/* --------------------- FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG -------------------- */ -#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Pos (0UL) /*!< FTDF FTDF_SYMBOLTIMESNAPSHOTVAL_REG: SYMBOLTIMESNAPSHOTVAL (Bit 0) */ -#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Msk (0xffffffffUL) /*!< FTDF FTDF_SYMBOLTIMESNAPSHOTVAL_REG: SYMBOLTIMESNAPSHOTVAL (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_RX_STATUS_DELTA_REG ----------------------- */ -#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Pos (0UL) /*!< FTDF FTDF_RX_STATUS_DELTA_REG: RX_BUFF_IS_FULL_D (Bit 0) */ -#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Msk (0x1UL) /*!< FTDF FTDF_RX_STATUS_DELTA_REG: RX_BUFF_IS_FULL_D (Bitfield-Mask: 0x01) */ - -/* ------------------------ FTDF_FTDF_RX_STATUS_MASK_REG ------------------------ */ -#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Pos (0UL) /*!< FTDF FTDF_RX_STATUS_MASK_REG: RX_BUFF_IS_FULL_M (Bit 0) */ -#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Msk (0x1UL) /*!< FTDF FTDF_RX_STATUS_MASK_REG: RX_BUFF_IS_FULL_M (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_TX_CONTROL_0_REG ------------------------- */ -#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Pos (0UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: DBGTXTRANSPARENTMODE (Bit 0) */ -#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Msk (0x1UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: DBGTXTRANSPARENTMODE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Pos (4UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXBE (Bit 4) */ -#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Msk (0xf0UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXBE (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Pos (8UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMINBE (Bit 8) */ -#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Msk (0xf00UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMINBE (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Pos (12UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXCSMABACKOFFS (Bit 12) */ -#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Msk (0x7000UL) /*!< FTDF FTDF_TX_CONTROL_0_REG: MACMAXCSMABACKOFFS (Bitfield-Mask: 0x07) */ - -/* ---------------------------- FTDF_FTDF_FTDF_CE_REG --------------------------- */ -#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Pos (0UL) /*!< FTDF FTDF_FTDF_CE_REG: FTDF_CE (Bit 0) */ -#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Msk (0x3fUL) /*!< FTDF FTDF_FTDF_CE_REG: FTDF_CE (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- FTDF_FTDF_FTDF_CM_REG --------------------------- */ -#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Pos (0UL) /*!< FTDF FTDF_FTDF_CM_REG: FTDF_CM (Bit 0) */ -#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Msk (0x3fUL) /*!< FTDF FTDF_FTDF_CM_REG: FTDF_CM (Bitfield-Mask: 0x3f) */ - -/* ----------------------- FTDF_FTDF_SYNCTIMESTAMPTHR_REG ----------------------- */ -#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Pos (0UL) /*!< FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bit 0) */ -#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Msk (0x1ffffffUL) /*!< FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bitfield-Mask: 0x1ffffff) */ - -/* ----------------------- FTDF_FTDF_SYNCTIMESTAMPVAL_REG ----------------------- */ -#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Pos (0UL) /*!< FTDF FTDF_SYNCTIMESTAMPVAL_REG: SYNCTIMESTAMPVAL (Bit 0) */ -#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Msk (0xffffffffUL) /*!< FTDF FTDF_SYNCTIMESTAMPVAL_REG: SYNCTIMESTAMPVAL (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_TIMER_CONTROL_1_REG ----------------------- */ -#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Pos (1UL) /*!< FTDF FTDF_TIMER_CONTROL_1_REG: SYNCTIMESTAMPENA (Bit 1) */ -#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Msk (0x2UL) /*!< FTDF FTDF_TIMER_CONTROL_1_REG: SYNCTIMESTAMPENA (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_MACTXSTDACKFRMCNT_REG ---------------------- */ -#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Pos (0UL) /*!< FTDF FTDF_MACTXSTDACKFRMCNT_REG: MACTXSTDACKFRMCNT (Bit 0) */ -#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACTXSTDACKFRMCNT_REG: MACTXSTDACKFRMCNT (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------- FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG --------------------- */ -#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Pos (0UL) /*!< FTDF FTDF_MACRXSTDACKFRMOKCNT_REG: MACRXSTDACKFRMOKCNT (Bit 0) */ -#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACRXSTDACKFRMOKCNT_REG: MACRXSTDACKFRMOKCNT (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------- FTDF_FTDF_MACRXADDRFAILFRMCNT_REG --------------------- */ -#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Pos (0UL) /*!< FTDF FTDF_MACRXADDRFAILFRMCNT_REG: MACRXADDRFAILFRMCNT (Bit 0) */ -#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACRXADDRFAILFRMCNT_REG: MACRXADDRFAILFRMCNT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------- FTDF_FTDF_MACRXUNSUPFRMCNT_REG ----------------------- */ -#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Pos (0UL) /*!< FTDF FTDF_MACRXUNSUPFRMCNT_REG: MACRXUNSUPFRMCNT (Bit 0) */ -#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACRXUNSUPFRMCNT_REG: MACRXUNSUPFRMCNT (Bitfield-Mask: 0xffffffff) */ - -/* --------------------- FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG -------------------- */ -#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Pos (0UL) /*!< FTDF FTDF_SYNCTIMESTAMPPHASEVAL_REG: SYNCTIMESTAMPPHASEVAL (Bit 0) */ -#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Msk (0xffUL) /*!< FTDF FTDF_SYNCTIMESTAMPPHASEVAL_REG: SYNCTIMESTAMPPHASEVAL (Bitfield-Mask: 0xff) */ - -/* ----------------------- FTDF_FTDF_MACFCSERRORCOUNT_REG ----------------------- */ -#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Pos (0UL) /*!< FTDF FTDF_MACFCSERRORCOUNT_REG: MACFCSERRORCOUNT (Bit 0) */ -#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Msk (0xffffffffUL) /*!< FTDF FTDF_MACFCSERRORCOUNT_REG: MACFCSERRORCOUNT (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- FTDF_FTDF_LMACRESET_REG -------------------------- */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Pos (0UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_CONTROL (Bit 0) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Msk (0x1UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_CONTROL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Pos (1UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_RX (Bit 1) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Msk (0x2UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_RX (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Pos (2UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TX (Bit 2) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Msk (0x4UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TX (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Pos (3UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_AHB (Bit 3) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Msk (0x8UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_AHB (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Pos (4UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_OREG (Bit 4) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Msk (0x10UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_OREG (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Pos (6UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TSTIM (Bit 6) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Msk (0x40UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TSTIM (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Pos (7UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_SEC (Bit 7) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Msk (0x80UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_SEC (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Pos (9UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_COUNT (Bit 9) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Msk (0x200UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_COUNT (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Pos (10UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TIMCTRL (Bit 10) */ -#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Msk (0x400UL) /*!< FTDF FTDF_LMACRESET_REG: LMACRESET_TIMCTRL (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Pos (16UL) /*!< FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bit 16) */ -#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Msk (0x10000UL) /*!< FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_WAKEUP_CONTROL_OS_REG ---------------------- */ -#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Pos (0UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bit 0) */ -#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Msk (0x1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Pos (1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bit 1) */ -#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Msk (0x2UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_SYMBOLTIMETHR_REG ------------------------ */ -#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Pos (0UL) /*!< FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bit 0) */ -#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Msk (0xffffffffUL) /*!< FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_SYMBOLTIME2THR_REG ------------------------ */ -#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Pos (0UL) /*!< FTDF FTDF_SYMBOLTIME2THR_REG: SYMBOLTIME2THR (Bit 0) */ -#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Msk (0xffffffffUL) /*!< FTDF FTDF_SYMBOLTIME2THR_REG: SYMBOLTIME2THR (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- FTDF_FTDF_DEBUGCONTROL_REG ------------------------- */ -#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Pos (8UL) /*!< FTDF FTDF_DEBUGCONTROL_REG: DBG_RX_INPUT (Bit 8) */ -#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Msk (0x100UL) /*!< FTDF FTDF_DEBUGCONTROL_REG: DBG_RX_INPUT (Bitfield-Mask: 0x01) */ - -/* --------------------------- FTDF_FTDF_TXBYTE_E_REG --------------------------- */ -#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Pos (0UL) /*!< FTDF FTDF_TXBYTE_E_REG: TXBYTE_E (Bit 0) */ -#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Msk (0x1UL) /*!< FTDF FTDF_TXBYTE_E_REG: TXBYTE_E (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Pos (1UL) /*!< FTDF FTDF_TXBYTE_E_REG: TX_LAST_SYMBOL_E (Bit 1) */ -#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Msk (0x2UL) /*!< FTDF FTDF_TXBYTE_E_REG: TX_LAST_SYMBOL_E (Bitfield-Mask: 0x01) */ - -/* --------------------------- FTDF_FTDF_TXBYTE_M_REG --------------------------- */ -#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Pos (0UL) /*!< FTDF FTDF_TXBYTE_M_REG: TXBYTE_M (Bit 0) */ -#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Msk (0x1UL) /*!< FTDF FTDF_TXBYTE_M_REG: TXBYTE_M (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Pos (1UL) /*!< FTDF FTDF_TXBYTE_M_REG: TX_LAST_SYMBOL_M (Bit 1) */ -#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Msk (0x2UL) /*!< FTDF FTDF_TXBYTE_M_REG: TX_LAST_SYMBOL_M (Bitfield-Mask: 0x01) */ - -/* -------------------------- FTDF_FTDF_TX_FLAG_S_0_REG ------------------------- */ -#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_S_0_REG: TX_FLAG_STAT (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_S_0_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_0_REG: TX_FLAG_CLEAR_E (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_0_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_0_REG: TX_FLAG_CLEAR_M (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_0_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_TX_PRIORITY_0_REG ------------------------ */ -#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Pos (0UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: TX_PRIORITY (Bit 0) */ -#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bit 4) */ -#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bit 8) */ -#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bitfield-Mask: 0x0f) */ - -/* -------------------------- FTDF_FTDF_TX_FLAG_S_1_REG ------------------------- */ -#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_S_1_REG: TX_FLAG_STAT (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_S_1_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_1_REG: TX_FLAG_CLEAR_E (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_1_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_1_REG: TX_FLAG_CLEAR_M (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_1_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_TX_PRIORITY_1_REG ------------------------ */ -#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Pos (0UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: TX_PRIORITY (Bit 0) */ -#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bit 4) */ -#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bit 8) */ -#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bitfield-Mask: 0x0f) */ - -/* -------------------------- FTDF_FTDF_TX_FLAG_S_2_REG ------------------------- */ -#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_S_2_REG: TX_FLAG_STAT (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_S_2_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_2_REG: TX_FLAG_CLEAR_E (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_2_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_2_REG: TX_FLAG_CLEAR_M (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_2_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_TX_PRIORITY_2_REG ------------------------ */ -#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Pos (0UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: TX_PRIORITY (Bit 0) */ -#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bit 4) */ -#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bit 8) */ -#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bitfield-Mask: 0x0f) */ - -/* -------------------------- FTDF_FTDF_TX_FLAG_S_3_REG ------------------------- */ -#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_S_3_REG: TX_FLAG_STAT (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_S_3_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_3_REG: TX_FLAG_CLEAR_E (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_E_3_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01) */ - -/* ----------------------- FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG ---------------------- */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_3_REG: TX_FLAG_CLEAR_M (Bit 0) */ -#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Msk (0x1UL) /*!< FTDF FTDF_TX_FLAG_CLEAR_M_3_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01) */ - -/* ------------------------- FTDF_FTDF_TX_PRIORITY_3_REG ------------------------ */ -#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Pos (0UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: TX_PRIORITY (Bit 0) */ -#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bit 4) */ -#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bit 8) */ -#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bitfield-Mask: 0x0f) */ - -/* --------------------------- FTDF_FTDF_TX_SET_OS_REG -------------------------- */ -#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Pos (0UL) /*!< FTDF FTDF_TX_SET_OS_REG: TX_FLAG_SET (Bit 0) */ -#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Msk (0xfUL) /*!< FTDF FTDF_TX_SET_OS_REG: TX_FLAG_SET (Bitfield-Mask: 0x0f) */ - -/* -------------------------- FTDF_FTDF_TX_CLEAR_OS_REG ------------------------- */ -#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Pos (0UL) /*!< FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bit 0) */ -#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Msk (0xfUL) /*!< FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bitfield-Mask: 0x0f) */ - -/* ------------------------ FTDF_FTDF_WAKEUP_CONTROL_REG ------------------------ */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Pos (0UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bit 0) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Msk (0x1ffffffUL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bitfield-Mask: 0x1ffffff) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Pos (29UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bit 29) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Msk (0x20000000UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Pos (30UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bit 30) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Msk (0xc0000000UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bitfield-Mask: 0x03) */ - -/* ------------------------- FTDF_FTDF_LONG_ADDR_0_0_REG ------------------------ */ -#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Pos (0UL) /*!< FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bit 0) */ -#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Msk (0xffffffffUL) /*!< FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------- FTDF_FTDF_LONG_ADDR_1_0_REG ------------------------ */ -#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Pos (0UL) /*!< FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bit 0) */ -#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Msk (0xffffffffUL) /*!< FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bitfield-Mask: 0xffffffff) */ - -/* ------------------------ FTDF_FTDF_SIZE_AND_VAL_0_REG ------------------------ */ -#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Pos (0UL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bit 0) */ -#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Msk (0xfUL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bitfield-Mask: 0x0f) */ -#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Pos (4UL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bit 4) */ -#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Msk (0x10UL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'GP_TIMERS' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- GP_TIMERS_TIMER0_CTRL_REG ------------------------- */ -#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Pos (0UL) /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CTRL (Bit 0) */ -#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Msk (0x1UL) /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CTRL (Bitfield-Mask: 0x01) */ -#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Pos (1UL) /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_SEL (Bit 1) */ -#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Msk (0x2UL) /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_SEL (Bitfield-Mask: 0x01) */ -#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Pos (2UL) /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_DIV (Bit 2) */ -#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Msk (0x4UL) /*!< GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_DIV (Bitfield-Mask: 0x01) */ -#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Pos (3UL) /*!< GP_TIMERS TIMER0_CTRL_REG: PWM_MODE (Bit 3) */ -#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Msk (0x8UL) /*!< GP_TIMERS TIMER0_CTRL_REG: PWM_MODE (Bitfield-Mask: 0x01) */ - -/* --------------------------- GP_TIMERS_TIMER0_ON_REG -------------------------- */ -#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Pos (0UL) /*!< GP_TIMERS TIMER0_ON_REG: TIM0_ON (Bit 0) */ -#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Msk (0xffffUL) /*!< GP_TIMERS TIMER0_ON_REG: TIM0_ON (Bitfield-Mask: 0xffff) */ - -/* ------------------------ GP_TIMERS_TIMER0_RELOAD_M_REG ----------------------- */ -#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Pos (0UL) /*!< GP_TIMERS TIMER0_RELOAD_M_REG: TIM0_M (Bit 0) */ -#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Msk (0xffffUL) /*!< GP_TIMERS TIMER0_RELOAD_M_REG: TIM0_M (Bitfield-Mask: 0xffff) */ - -/* ------------------------ GP_TIMERS_TIMER0_RELOAD_N_REG ----------------------- */ -#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Pos (0UL) /*!< GP_TIMERS TIMER0_RELOAD_N_REG: TIM0_N (Bit 0) */ -#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Msk (0xffffUL) /*!< GP_TIMERS TIMER0_RELOAD_N_REG: TIM0_N (Bitfield-Mask: 0xffff) */ - -/* ------------------------- GP_TIMERS_PWM2_START_CYCLE ------------------------- */ -#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Pos (0UL) /*!< GP_TIMERS PWM2_START_CYCLE: START_CYCLE (Bit 0) */ -#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Msk (0x3fffUL) /*!< GP_TIMERS PWM2_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff) */ - -/* ------------------------- GP_TIMERS_PWM3_START_CYCLE ------------------------- */ -#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Pos (0UL) /*!< GP_TIMERS PWM3_START_CYCLE: START_CYCLE (Bit 0) */ -#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Msk (0x3fffUL) /*!< GP_TIMERS PWM3_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff) */ - -/* ------------------------- GP_TIMERS_PWM4_START_CYCLE ------------------------- */ -#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Pos (0UL) /*!< GP_TIMERS PWM4_START_CYCLE: START_CYCLE (Bit 0) */ -#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Msk (0x3fffUL) /*!< GP_TIMERS PWM4_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff) */ - -/* -------------------------- GP_TIMERS_PWM2_END_CYCLE -------------------------- */ -#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Pos (0UL) /*!< GP_TIMERS PWM2_END_CYCLE: END_CYCLE (Bit 0) */ -#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Msk (0x3fffUL) /*!< GP_TIMERS PWM2_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff) */ - -/* -------------------------- GP_TIMERS_PWM3_END_CYCLE -------------------------- */ -#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Pos (0UL) /*!< GP_TIMERS PWM3_END_CYCLE: END_CYCLE (Bit 0) */ -#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Msk (0x3fffUL) /*!< GP_TIMERS PWM3_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff) */ - -/* -------------------------- GP_TIMERS_PWM4_END_CYCLE -------------------------- */ -#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Pos (0UL) /*!< GP_TIMERS PWM4_END_CYCLE: END_CYCLE (Bit 0) */ -#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Msk (0x3fffUL) /*!< GP_TIMERS PWM4_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff) */ - -/* ----------------------- GP_TIMERS_TRIPLE_PWM_FREQUENCY ----------------------- */ -#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Pos (0UL) /*!< GP_TIMERS TRIPLE_PWM_FREQUENCY: FREQ (Bit 0) */ -#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Msk (0x3fffUL) /*!< GP_TIMERS TRIPLE_PWM_FREQUENCY: FREQ (Bitfield-Mask: 0x3fff) */ - -/* ------------------------ GP_TIMERS_TRIPLE_PWM_CTRL_REG ----------------------- */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Pos (0UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_ENABLE (Bit 0) */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Msk (0x1UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_ENABLE (Bitfield-Mask: 0x01) */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Pos (1UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: SW_PAUSE_EN (Bit 1) */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Msk (0x2UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: SW_PAUSE_EN (Bitfield-Mask: 0x01) */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Pos (2UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bit 2) */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Msk (0x4UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bitfield-Mask: 0x01) */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Pos (3UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bit 3) */ -#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Msk (0x8UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bitfield-Mask: 0x01) */ - -/* -------------------------- GP_TIMERS_BREATH_CFG_REG -------------------------- */ -#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Pos (0UL) /*!< GP_TIMERS BREATH_CFG_REG: BRTH_DIV (Bit 0) */ -#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Msk (0xffUL) /*!< GP_TIMERS BREATH_CFG_REG: BRTH_DIV (Bitfield-Mask: 0xff) */ -#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Pos (8UL) /*!< GP_TIMERS BREATH_CFG_REG: BRTH_STEP (Bit 8) */ -#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Msk (0xff00UL) /*!< GP_TIMERS BREATH_CFG_REG: BRTH_STEP (Bitfield-Mask: 0xff) */ - -/* ------------------------ GP_TIMERS_BREATH_DUTY_MAX_REG ----------------------- */ -#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Pos (0UL) /*!< GP_TIMERS BREATH_DUTY_MAX_REG: BRTH_DUTY_MAX (Bit 0) */ -#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Msk (0xffUL) /*!< GP_TIMERS BREATH_DUTY_MAX_REG: BRTH_DUTY_MAX (Bitfield-Mask: 0xff) */ - -/* ------------------------ GP_TIMERS_BREATH_DUTY_MIN_REG ----------------------- */ -#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Pos (0UL) /*!< GP_TIMERS BREATH_DUTY_MIN_REG: BRTH_DUTY_MIN (Bit 0) */ -#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Msk (0xffUL) /*!< GP_TIMERS BREATH_DUTY_MIN_REG: BRTH_DUTY_MIN (Bitfield-Mask: 0xff) */ - -/* -------------------------- GP_TIMERS_BREATH_CTRL_REG ------------------------- */ -#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Pos (0UL) /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_EN (Bit 0) */ -#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Msk (0x1UL) /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_EN (Bitfield-Mask: 0x01) */ -#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Pos (1UL) /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_PWM_POL (Bit 1) */ -#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Msk (0x2UL) /*!< GP_TIMERS BREATH_CTRL_REG: BRTH_PWM_POL (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'GPADC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- GPADC_GP_ADC_CTRL_REG --------------------------- */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos (0UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_EN (Bit 0) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk (0x1UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_EN (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_START (Bit 1) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_START (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CONT (Bit 2) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CONT (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos (3UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CLK_SEL (Bit 3) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk (0x8UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CLK_SEL (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos (4UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_INT (Bit 4) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk (0x10UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_INT (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MINT (Bit 5) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MINT (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos (6UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SE (Bit 6) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk (0x40UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SE (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MUTE (Bit 7) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_MUTE (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos (8UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SEL (Bit 8) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk (0x1f00UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SEL (Bitfield-Mask: 0x1f) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (13UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SIGN (Bit 13) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x2000UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_SIGN (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (14UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CHOP (Bit 14) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x4000UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_CHOP (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos (15UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_LDO_ZERO (Bit 15) */ -#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk (0x8000UL) /*!< GPADC GP_ADC_CTRL_REG: GP_ADC_LDO_ZERO (Bitfield-Mask: 0x01) */ - -/* --------------------------- GPADC_GP_ADC_CTRL2_REG --------------------------- */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos (0UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_ATTN3X (Bit 0) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk (0x1UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_ATTN3X (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos (1UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_IDYN (Bit 1) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk (0x2UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_IDYN (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_I20U (Bit 2) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_I20U (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos (3UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_DMA_EN (Bit 3) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk (0x8UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_DMA_EN (Bitfield-Mask: 0x01) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (5UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_CONV_NRS (Bit 5) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0xe0UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_CONV_NRS (Bitfield-Mask: 0x07) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (8UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_SMPL_TIME (Bit 8) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0xf00UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_SMPL_TIME (Bitfield-Mask: 0x0f) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (12UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_STORE_DEL (Bit 12) */ -#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xf000UL) /*!< GPADC GP_ADC_CTRL2_REG: GP_ADC_STORE_DEL (Bitfield-Mask: 0x0f) */ - -/* --------------------------- GPADC_GP_ADC_CTRL3_REG --------------------------- */ -#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL) /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_EN_DEL (Bit 0) */ -#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL) /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_EN_DEL (Bitfield-Mask: 0xff) */ -#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL) /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_INTERVAL (Bit 8) */ -#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL) /*!< GPADC GP_ADC_CTRL3_REG: GP_ADC_INTERVAL (Bitfield-Mask: 0xff) */ - -/* ---------------------------- GPADC_GP_ADC_OFFP_REG --------------------------- */ -#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL) /*!< GPADC GP_ADC_OFFP_REG: GP_ADC_OFFP (Bit 0) */ -#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL) /*!< GPADC GP_ADC_OFFP_REG: GP_ADC_OFFP (Bitfield-Mask: 0x3ff) */ - -/* ---------------------------- GPADC_GP_ADC_OFFN_REG --------------------------- */ -#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL) /*!< GPADC GP_ADC_OFFN_REG: GP_ADC_OFFN (Bit 0) */ -#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL) /*!< GPADC GP_ADC_OFFN_REG: GP_ADC_OFFN (Bitfield-Mask: 0x3ff) */ - -/* ------------------------- GPADC_GP_ADC_CLEAR_INT_REG ------------------------- */ -#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL) /*!< GPADC GP_ADC_CLEAR_INT_REG: GP_ADC_CLR_INT (Bit 0) */ -#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL) /*!< GPADC GP_ADC_CLEAR_INT_REG: GP_ADC_CLR_INT (Bitfield-Mask: 0xffff) */ - -/* --------------------------- GPADC_GP_ADC_RESULT_REG -------------------------- */ -#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL) /*!< GPADC GP_ADC_RESULT_REG: GP_ADC_VAL (Bit 0) */ -#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL) /*!< GPADC GP_ADC_RESULT_REG: GP_ADC_VAL (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'GPIO' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------ GPIO_P0_DATA_REG ------------------------------ */ -#define GPIO_P0_DATA_REG_P0_DATA_Pos (0UL) /*!< GPIO P0_DATA_REG: P0_DATA (Bit 0) */ -#define GPIO_P0_DATA_REG_P0_DATA_Msk (0xffUL) /*!< GPIO P0_DATA_REG: P0_DATA (Bitfield-Mask: 0xff) */ - -/* ------------------------------ GPIO_P1_DATA_REG ------------------------------ */ -#define GPIO_P1_DATA_REG_P1_DATA_Pos (0UL) /*!< GPIO P1_DATA_REG: P1_DATA (Bit 0) */ -#define GPIO_P1_DATA_REG_P1_DATA_Msk (0xffUL) /*!< GPIO P1_DATA_REG: P1_DATA (Bitfield-Mask: 0xff) */ - -/* ------------------------------ GPIO_P2_DATA_REG ------------------------------ */ -#define GPIO_P2_DATA_REG_P2_DATA_Pos (0UL) /*!< GPIO P2_DATA_REG: P2_DATA (Bit 0) */ -#define GPIO_P2_DATA_REG_P2_DATA_Msk (0x1fUL) /*!< GPIO P2_DATA_REG: P2_DATA (Bitfield-Mask: 0x1f) */ - -/* ------------------------------ GPIO_P3_DATA_REG ------------------------------ */ -#define GPIO_P3_DATA_REG_P3_DATA_Pos (0UL) /*!< GPIO P3_DATA_REG: P3_DATA (Bit 0) */ -#define GPIO_P3_DATA_REG_P3_DATA_Msk (0xffUL) /*!< GPIO P3_DATA_REG: P3_DATA (Bitfield-Mask: 0xff) */ - -/* ------------------------------ GPIO_P4_DATA_REG ------------------------------ */ -#define GPIO_P4_DATA_REG_P4_DATA_Pos (0UL) /*!< GPIO P4_DATA_REG: P4_DATA (Bit 0) */ -#define GPIO_P4_DATA_REG_P4_DATA_Msk (0xffUL) /*!< GPIO P4_DATA_REG: P4_DATA (Bitfield-Mask: 0xff) */ - -/* ---------------------------- GPIO_P0_SET_DATA_REG ---------------------------- */ -#define GPIO_P0_SET_DATA_REG_P0_SET_Pos (0UL) /*!< GPIO P0_SET_DATA_REG: P0_SET (Bit 0) */ -#define GPIO_P0_SET_DATA_REG_P0_SET_Msk (0xffUL) /*!< GPIO P0_SET_DATA_REG: P0_SET (Bitfield-Mask: 0xff) */ - -/* ---------------------------- GPIO_P1_SET_DATA_REG ---------------------------- */ -#define GPIO_P1_SET_DATA_REG_P1_SET_Pos (0UL) /*!< GPIO P1_SET_DATA_REG: P1_SET (Bit 0) */ -#define GPIO_P1_SET_DATA_REG_P1_SET_Msk (0xffUL) /*!< GPIO P1_SET_DATA_REG: P1_SET (Bitfield-Mask: 0xff) */ - -/* ---------------------------- GPIO_P2_SET_DATA_REG ---------------------------- */ -#define GPIO_P2_SET_DATA_REG_P2_SET_Pos (0UL) /*!< GPIO P2_SET_DATA_REG: P2_SET (Bit 0) */ -#define GPIO_P2_SET_DATA_REG_P2_SET_Msk (0x1fUL) /*!< GPIO P2_SET_DATA_REG: P2_SET (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- GPIO_P3_SET_DATA_REG ---------------------------- */ -#define GPIO_P3_SET_DATA_REG_P3_SET_Pos (0UL) /*!< GPIO P3_SET_DATA_REG: P3_SET (Bit 0) */ -#define GPIO_P3_SET_DATA_REG_P3_SET_Msk (0xffUL) /*!< GPIO P3_SET_DATA_REG: P3_SET (Bitfield-Mask: 0xff) */ - -/* ---------------------------- GPIO_P4_SET_DATA_REG ---------------------------- */ -#define GPIO_P4_SET_DATA_REG_P4_SET_Pos (0UL) /*!< GPIO P4_SET_DATA_REG: P4_SET (Bit 0) */ -#define GPIO_P4_SET_DATA_REG_P4_SET_Msk (0xffUL) /*!< GPIO P4_SET_DATA_REG: P4_SET (Bitfield-Mask: 0xff) */ - -/* --------------------------- GPIO_P0_RESET_DATA_REG --------------------------- */ -#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL) /*!< GPIO P0_RESET_DATA_REG: P0_RESET (Bit 0) */ -#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0xffUL) /*!< GPIO P0_RESET_DATA_REG: P0_RESET (Bitfield-Mask: 0xff) */ - -/* --------------------------- GPIO_P1_RESET_DATA_REG --------------------------- */ -#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL) /*!< GPIO P1_RESET_DATA_REG: P1_RESET (Bit 0) */ -#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0xffUL) /*!< GPIO P1_RESET_DATA_REG: P1_RESET (Bitfield-Mask: 0xff) */ - -/* --------------------------- GPIO_P2_RESET_DATA_REG --------------------------- */ -#define GPIO_P2_RESET_DATA_REG_P2_RESET_Pos (0UL) /*!< GPIO P2_RESET_DATA_REG: P2_RESET (Bit 0) */ -#define GPIO_P2_RESET_DATA_REG_P2_RESET_Msk (0x1fUL) /*!< GPIO P2_RESET_DATA_REG: P2_RESET (Bitfield-Mask: 0x1f) */ - -/* --------------------------- GPIO_P3_RESET_DATA_REG --------------------------- */ -#define GPIO_P3_RESET_DATA_REG_P3_RESET_Pos (0UL) /*!< GPIO P3_RESET_DATA_REG: P3_RESET (Bit 0) */ -#define GPIO_P3_RESET_DATA_REG_P3_RESET_Msk (0xffUL) /*!< GPIO P3_RESET_DATA_REG: P3_RESET (Bitfield-Mask: 0xff) */ - -/* --------------------------- GPIO_P4_RESET_DATA_REG --------------------------- */ -#define GPIO_P4_RESET_DATA_REG_P4_RESET_Pos (0UL) /*!< GPIO P4_RESET_DATA_REG: P4_RESET (Bit 0) */ -#define GPIO_P4_RESET_DATA_REG_P4_RESET_Msk (0xffUL) /*!< GPIO P4_RESET_DATA_REG: P4_RESET (Bitfield-Mask: 0xff) */ - -/* ------------------------------ GPIO_P00_MODE_REG ----------------------------- */ -#define GPIO_P00_MODE_REG_PID_Pos (0UL) /*!< GPIO P00_MODE_REG: PID (Bit 0) */ -#define GPIO_P00_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P00_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P00_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P00_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P00_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P00_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P00_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P00_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P00_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P00_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P01_MODE_REG ----------------------------- */ -#define GPIO_P01_MODE_REG_PID_Pos (0UL) /*!< GPIO P01_MODE_REG: PID (Bit 0) */ -#define GPIO_P01_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P01_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P01_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P01_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P01_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P01_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P01_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P01_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P01_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P01_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P02_MODE_REG ----------------------------- */ -#define GPIO_P02_MODE_REG_PID_Pos (0UL) /*!< GPIO P02_MODE_REG: PID (Bit 0) */ -#define GPIO_P02_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P02_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P02_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P02_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P02_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P02_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P02_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P02_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P02_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P02_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P03_MODE_REG ----------------------------- */ -#define GPIO_P03_MODE_REG_PID_Pos (0UL) /*!< GPIO P03_MODE_REG: PID (Bit 0) */ -#define GPIO_P03_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P03_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P03_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P03_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P03_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P03_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P03_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P03_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P03_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P03_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P04_MODE_REG ----------------------------- */ -#define GPIO_P04_MODE_REG_PID_Pos (0UL) /*!< GPIO P04_MODE_REG: PID (Bit 0) */ -#define GPIO_P04_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P04_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P04_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P04_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P04_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P04_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P04_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P04_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P04_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P04_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P05_MODE_REG ----------------------------- */ -#define GPIO_P05_MODE_REG_PID_Pos (0UL) /*!< GPIO P05_MODE_REG: PID (Bit 0) */ -#define GPIO_P05_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P05_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P05_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P05_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P05_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P05_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P05_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P05_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P05_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P05_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P06_MODE_REG ----------------------------- */ -#define GPIO_P06_MODE_REG_PID_Pos (0UL) /*!< GPIO P06_MODE_REG: PID (Bit 0) */ -#define GPIO_P06_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P06_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P06_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P06_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P06_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P06_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P06_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P06_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P06_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P06_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P07_MODE_REG ----------------------------- */ -#define GPIO_P07_MODE_REG_PID_Pos (0UL) /*!< GPIO P07_MODE_REG: PID (Bit 0) */ -#define GPIO_P07_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P07_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P07_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P07_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P07_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P07_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P07_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P07_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P07_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P07_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P10_MODE_REG ----------------------------- */ -#define GPIO_P10_MODE_REG_PID_Pos (0UL) /*!< GPIO P10_MODE_REG: PID (Bit 0) */ -#define GPIO_P10_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P10_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P10_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P10_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P10_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P10_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P10_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P10_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P10_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P10_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P11_MODE_REG ----------------------------- */ -#define GPIO_P11_MODE_REG_PID_Pos (0UL) /*!< GPIO P11_MODE_REG: PID (Bit 0) */ -#define GPIO_P11_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P11_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P11_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P11_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P11_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P11_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P11_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P11_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P11_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P11_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P12_MODE_REG ----------------------------- */ -#define GPIO_P12_MODE_REG_PID_Pos (0UL) /*!< GPIO P12_MODE_REG: PID (Bit 0) */ -#define GPIO_P12_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P12_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P12_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P12_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P12_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P12_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P12_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P12_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P12_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P12_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P13_MODE_REG ----------------------------- */ -#define GPIO_P13_MODE_REG_PID_Pos (0UL) /*!< GPIO P13_MODE_REG: PID (Bit 0) */ -#define GPIO_P13_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P13_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P13_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P13_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P13_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P13_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P13_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P13_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P13_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P13_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P14_MODE_REG ----------------------------- */ -#define GPIO_P14_MODE_REG_PID_Pos (0UL) /*!< GPIO P14_MODE_REG: PID (Bit 0) */ -#define GPIO_P14_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P14_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P14_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P14_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P14_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P14_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P14_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P14_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P14_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P14_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P15_MODE_REG ----------------------------- */ -#define GPIO_P15_MODE_REG_PID_Pos (0UL) /*!< GPIO P15_MODE_REG: PID (Bit 0) */ -#define GPIO_P15_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P15_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P15_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P15_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P15_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P15_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P15_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P15_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P15_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P15_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P16_MODE_REG ----------------------------- */ -#define GPIO_P16_MODE_REG_PID_Pos (0UL) /*!< GPIO P16_MODE_REG: PID (Bit 0) */ -#define GPIO_P16_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P16_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P16_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P16_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P16_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P16_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P16_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P16_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P16_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P16_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P17_MODE_REG ----------------------------- */ -#define GPIO_P17_MODE_REG_PID_Pos (0UL) /*!< GPIO P17_MODE_REG: PID (Bit 0) */ -#define GPIO_P17_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P17_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P17_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P17_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P17_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P17_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P17_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P17_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P17_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P17_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P20_MODE_REG ----------------------------- */ -#define GPIO_P20_MODE_REG_PID_Pos (0UL) /*!< GPIO P20_MODE_REG: PID (Bit 0) */ -#define GPIO_P20_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P20_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P20_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P20_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P20_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P20_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P20_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P20_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P20_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P20_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P21_MODE_REG ----------------------------- */ -#define GPIO_P21_MODE_REG_PID_Pos (0UL) /*!< GPIO P21_MODE_REG: PID (Bit 0) */ -#define GPIO_P21_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P21_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P21_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P21_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P21_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P21_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P21_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P21_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P21_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P21_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P22_MODE_REG ----------------------------- */ -#define GPIO_P22_MODE_REG_PID_Pos (0UL) /*!< GPIO P22_MODE_REG: PID (Bit 0) */ -#define GPIO_P22_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P22_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P22_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P22_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P22_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P22_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P22_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P22_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P22_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P22_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P23_MODE_REG ----------------------------- */ -#define GPIO_P23_MODE_REG_PID_Pos (0UL) /*!< GPIO P23_MODE_REG: PID (Bit 0) */ -#define GPIO_P23_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P23_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P23_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P23_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P23_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P23_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P23_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P23_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P23_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P23_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P24_MODE_REG ----------------------------- */ -#define GPIO_P24_MODE_REG_PID_Pos (0UL) /*!< GPIO P24_MODE_REG: PID (Bit 0) */ -#define GPIO_P24_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P24_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P24_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P24_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P24_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P24_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P24_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P24_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P24_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P24_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P30_MODE_REG ----------------------------- */ -#define GPIO_P30_MODE_REG_PID_Pos (0UL) /*!< GPIO P30_MODE_REG: PID (Bit 0) */ -#define GPIO_P30_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P30_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P30_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P30_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P30_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P30_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P30_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P30_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P30_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P30_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P31_MODE_REG ----------------------------- */ -#define GPIO_P31_MODE_REG_PID_Pos (0UL) /*!< GPIO P31_MODE_REG: PID (Bit 0) */ -#define GPIO_P31_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P31_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P31_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P31_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P31_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P31_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P31_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P31_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P31_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P31_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P32_MODE_REG ----------------------------- */ -#define GPIO_P32_MODE_REG_PID_Pos (0UL) /*!< GPIO P32_MODE_REG: PID (Bit 0) */ -#define GPIO_P32_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P32_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P32_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P32_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P32_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P32_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P32_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P32_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P32_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P32_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P33_MODE_REG ----------------------------- */ -#define GPIO_P33_MODE_REG_PID_Pos (0UL) /*!< GPIO P33_MODE_REG: PID (Bit 0) */ -#define GPIO_P33_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P33_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P33_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P33_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P33_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P33_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P33_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P33_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P33_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P33_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P34_MODE_REG ----------------------------- */ -#define GPIO_P34_MODE_REG_PID_Pos (0UL) /*!< GPIO P34_MODE_REG: PID (Bit 0) */ -#define GPIO_P34_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P34_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P34_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P34_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P34_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P34_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P34_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P34_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P34_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P34_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P35_MODE_REG ----------------------------- */ -#define GPIO_P35_MODE_REG_PID_Pos (0UL) /*!< GPIO P35_MODE_REG: PID (Bit 0) */ -#define GPIO_P35_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P35_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P35_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P35_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P35_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P35_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P35_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P35_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P35_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P35_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P36_MODE_REG ----------------------------- */ -#define GPIO_P36_MODE_REG_PID_Pos (0UL) /*!< GPIO P36_MODE_REG: PID (Bit 0) */ -#define GPIO_P36_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P36_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P36_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P36_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P36_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P36_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P36_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P36_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P36_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P36_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P37_MODE_REG ----------------------------- */ -#define GPIO_P37_MODE_REG_PID_Pos (0UL) /*!< GPIO P37_MODE_REG: PID (Bit 0) */ -#define GPIO_P37_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P37_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P37_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P37_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P37_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P37_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P37_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P37_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P37_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P37_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P40_MODE_REG ----------------------------- */ -#define GPIO_P40_MODE_REG_PID_Pos (0UL) /*!< GPIO P40_MODE_REG: PID (Bit 0) */ -#define GPIO_P40_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P40_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P40_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P40_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P40_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P40_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P40_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P40_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P40_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P40_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P41_MODE_REG ----------------------------- */ -#define GPIO_P41_MODE_REG_PID_Pos (0UL) /*!< GPIO P41_MODE_REG: PID (Bit 0) */ -#define GPIO_P41_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P41_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P41_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P41_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P41_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P41_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P41_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P41_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P41_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P41_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P42_MODE_REG ----------------------------- */ -#define GPIO_P42_MODE_REG_PID_Pos (0UL) /*!< GPIO P42_MODE_REG: PID (Bit 0) */ -#define GPIO_P42_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P42_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P42_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P42_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P42_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P42_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P42_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P42_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P42_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P42_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P43_MODE_REG ----------------------------- */ -#define GPIO_P43_MODE_REG_PID_Pos (0UL) /*!< GPIO P43_MODE_REG: PID (Bit 0) */ -#define GPIO_P43_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P43_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P43_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P43_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P43_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P43_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P43_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P43_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P43_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P43_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P44_MODE_REG ----------------------------- */ -#define GPIO_P44_MODE_REG_PID_Pos (0UL) /*!< GPIO P44_MODE_REG: PID (Bit 0) */ -#define GPIO_P44_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P44_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P44_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P44_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P44_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P44_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P44_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P44_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P44_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P44_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P45_MODE_REG ----------------------------- */ -#define GPIO_P45_MODE_REG_PID_Pos (0UL) /*!< GPIO P45_MODE_REG: PID (Bit 0) */ -#define GPIO_P45_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P45_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P45_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P45_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P45_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P45_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P45_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P45_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P45_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P45_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P46_MODE_REG ----------------------------- */ -#define GPIO_P46_MODE_REG_PID_Pos (0UL) /*!< GPIO P46_MODE_REG: PID (Bit 0) */ -#define GPIO_P46_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P46_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P46_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P46_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P46_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P46_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P46_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P46_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P46_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P46_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* ------------------------------ GPIO_P47_MODE_REG ----------------------------- */ -#define GPIO_P47_MODE_REG_PID_Pos (0UL) /*!< GPIO P47_MODE_REG: PID (Bit 0) */ -#define GPIO_P47_MODE_REG_PID_Msk (0x3fUL) /*!< GPIO P47_MODE_REG: PID (Bitfield-Mask: 0x3f) */ -#define GPIO_P47_MODE_REG_PUPD_Pos (8UL) /*!< GPIO P47_MODE_REG: PUPD (Bit 8) */ -#define GPIO_P47_MODE_REG_PUPD_Msk (0x300UL) /*!< GPIO P47_MODE_REG: PUPD (Bitfield-Mask: 0x03) */ -#define GPIO_P47_MODE_REG_PPOD_Pos (10UL) /*!< GPIO P47_MODE_REG: PPOD (Bit 10) */ -#define GPIO_P47_MODE_REG_PPOD_Msk (0x400UL) /*!< GPIO P47_MODE_REG: PPOD (Bitfield-Mask: 0x01) */ - -/* --------------------------- GPIO_P0_PADPWR_CTRL_REG -------------------------- */ -#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos (6UL) /*!< GPIO P0_PADPWR_CTRL_REG: P0_OUT_CTRL (Bit 6) */ -#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk (0xc0UL) /*!< GPIO P0_PADPWR_CTRL_REG: P0_OUT_CTRL (Bitfield-Mask: 0x03) */ - -/* --------------------------- GPIO_P1_PADPWR_CTRL_REG -------------------------- */ -#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos (0UL) /*!< GPIO P1_PADPWR_CTRL_REG: P1_OUT_CTRL (Bit 0) */ -#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk (0xffUL) /*!< GPIO P1_PADPWR_CTRL_REG: P1_OUT_CTRL (Bitfield-Mask: 0xff) */ - -/* --------------------------- GPIO_P2_PADPWR_CTRL_REG -------------------------- */ -#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Pos (0UL) /*!< GPIO P2_PADPWR_CTRL_REG: P2_OUT_CTRL (Bit 0) */ -#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Msk (0x1fUL) /*!< GPIO P2_PADPWR_CTRL_REG: P2_OUT_CTRL (Bitfield-Mask: 0x1f) */ - -/* --------------------------- GPIO_P3_PADPWR_CTRL_REG -------------------------- */ -#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Pos (0UL) /*!< GPIO P3_PADPWR_CTRL_REG: P3_OUT_CTRL (Bit 0) */ -#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Msk (0xffUL) /*!< GPIO P3_PADPWR_CTRL_REG: P3_OUT_CTRL (Bitfield-Mask: 0xff) */ - -/* --------------------------- GPIO_P4_PADPWR_CTRL_REG -------------------------- */ -#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Pos (0UL) /*!< GPIO P4_PADPWR_CTRL_REG: P4_OUT_CTRL (Bit 0) */ -#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Msk (0xffUL) /*!< GPIO P4_PADPWR_CTRL_REG: P4_OUT_CTRL (Bitfield-Mask: 0xff) */ - -/* ------------------------------ GPIO_GPIO_CLK_SEL ----------------------------- */ -#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Pos (0UL) /*!< GPIO GPIO_CLK_SEL: FUNC_CLOCK_SEL (Bit 0) */ -#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Msk (0x7UL) /*!< GPIO GPIO_CLK_SEL: FUNC_CLOCK_SEL (Bitfield-Mask: 0x07) */ - -/* ----------------------------- GPIO_BIST_CTRL_REG ----------------------------- */ -#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Pos (0UL) /*!< GPIO BIST_CTRL_REG: RAM_BIST_CONFIG (Bit 0) */ -#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Msk (0x3UL) /*!< GPIO BIST_CTRL_REG: RAM_BIST_CONFIG (Bitfield-Mask: 0x03) */ -#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Pos (2UL) /*!< GPIO BIST_CTRL_REG: RAM_BIST_PATTERN (Bit 2) */ -#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Msk (0xcUL) /*!< GPIO BIST_CTRL_REG: RAM_BIST_PATTERN (Bitfield-Mask: 0x03) */ -#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Pos (4UL) /*!< GPIO BIST_CTRL_REG: ROMBIST_ENABLE (Bit 4) */ -#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Msk (0x10UL) /*!< GPIO BIST_CTRL_REG: ROMBIST_ENABLE (Bitfield-Mask: 0x01) */ -#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Pos (5UL) /*!< GPIO BIST_CTRL_REG: RAMBIST_ENABLE (Bit 5) */ -#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Msk (0x20UL) /*!< GPIO BIST_CTRL_REG: RAMBIST_ENABLE (Bitfield-Mask: 0x01) */ -#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Pos (6UL) /*!< GPIO BIST_CTRL_REG: SYSRAMBIST_ENABLE (Bit 6) */ -#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Msk (0x40UL) /*!< GPIO BIST_CTRL_REG: SYSRAMBIST_ENABLE (Bitfield-Mask: 0x01) */ -#define GPIO_BIST_CTRL_REG_SHOW_BIST_Pos (7UL) /*!< GPIO BIST_CTRL_REG: SHOW_BIST (Bit 7) */ -#define GPIO_BIST_CTRL_REG_SHOW_BIST_Msk (0x80UL) /*!< GPIO BIST_CTRL_REG: SHOW_BIST (Bitfield-Mask: 0x01) */ - -/* -------------------------- GPIO_RAMBIST_STATUS1_REG -------------------------- */ -#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Pos (0UL) /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_LINE_FAIL (Bit 0) */ -#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Msk (0x1UL) /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Pos (1UL) /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_FAIL (Bit 1) */ -#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Msk (0x2UL) /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Pos (2UL) /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_BUSY (Bit 2) */ -#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Msk (0x4UL) /*!< GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Pos (3UL) /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_LINE_FAIL (Bit 3) */ -#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Msk (0x8UL) /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Pos (4UL) /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_FAIL (Bit 4) */ -#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Msk (0x10UL) /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Pos (5UL) /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_BUSY (Bit 5) */ -#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Msk (0x20UL) /*!< GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Pos (6UL) /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_LINE_FAIL (Bit 6) */ -#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Msk (0x40UL) /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Pos (7UL) /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_FAIL (Bit 7) */ -#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Msk (0x80UL) /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Pos (8UL) /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_BUSY (Bit 8) */ -#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Msk (0x100UL) /*!< GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Pos (9UL) /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_LINE_FAIL (Bit 9) */ -#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Msk (0x200UL) /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Pos (10UL) /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_FAIL (Bit 10) */ -#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Msk (0x400UL) /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Pos (11UL) /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_BUSY (Bit 11) */ -#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Msk (0x800UL) /*!< GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Pos (12UL) /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_LINE_FAIL (Bit 12) */ -#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Msk (0x1000UL) /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Pos (13UL) /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_FAIL (Bit 13) */ -#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Msk (0x2000UL) /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Pos (14UL) /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_BUSY (Bit 14) */ -#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Msk (0x4000UL) /*!< GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Pos (15UL) /*!< GPIO RAMBIST_STATUS1_REG: ROM_BIST_BUSY (Bit 15) */ -#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Msk (0x8000UL) /*!< GPIO RAMBIST_STATUS1_REG: ROM_BIST_BUSY (Bitfield-Mask: 0x01) */ - -/* -------------------------- GPIO_RAMBIST_STATUS2_REG -------------------------- */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Pos (0UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_LINE_FAIL (Bit 0) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Msk (0x1UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Pos (1UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_FAIL (Bit 1) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Msk (0x2UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Pos (2UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_BUSY (Bit 2) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Msk (0x4UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Pos (3UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_LINE_FAIL (Bit 3) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Msk (0x8UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Pos (4UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_FAIL (Bit 4) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Msk (0x10UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Pos (5UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_BUSY (Bit 5) */ -#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Msk (0x20UL) /*!< GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Pos (6UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_LINE_FAIL (Bit 6) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Msk (0x40UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Pos (7UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_FAIL (Bit 7) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Msk (0x80UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Pos (8UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_BUSY (Bit 8) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Msk (0x100UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Pos (9UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_LINE_FAIL (Bit 9) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Msk (0x200UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Pos (10UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_FAIL (Bit 10) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Msk (0x400UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Pos (11UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_BUSY (Bit 11) */ -#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Msk (0x800UL) /*!< GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Pos (12UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_LINE_FAIL (Bit 12) */ -#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Msk (0x1000UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Pos (13UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_FAIL (Bit 13) */ -#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Msk (0x2000UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Pos (14UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bit 14) */ -#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Msk (0x4000UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bitfield-Mask: 0x01) */ - -/* -------------------------- GPIO_RAMBIST_STATUS3_REG -------------------------- */ -#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Pos (0UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bit 0) */ -#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Msk (0x1UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Pos (1UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bit 1) */ -#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Msk (0x2UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ -#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Pos (2UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bit 2) */ -#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Msk (0x4UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ - -/* -------------------------- GPIO_ROMBIST_RESULTL_REG -------------------------- */ -#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Pos (0UL) /*!< GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bit 0) */ -#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Msk (0xffffUL) /*!< GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bitfield-Mask: 0xffff) */ - -/* -------------------------- GPIO_ROMBIST_RESULTH_REG -------------------------- */ -#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Pos (0UL) /*!< GPIO ROMBIST_RESULTH_REG: ROMBIST_RESULTH (Bit 0) */ -#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Msk (0xffffUL) /*!< GPIO ROMBIST_RESULTH_REG: ROMBIST_RESULTH (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- GPIO_TEST_CTRL_REG ----------------------------- */ -#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Pos (0UL) /*!< GPIO TEST_CTRL_REG: SHOW_CLOCKS (Bit 0) */ -#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Msk (0x1UL) /*!< GPIO TEST_CTRL_REG: SHOW_CLOCKS (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Pos (1UL) /*!< GPIO TEST_CTRL_REG: ENABLE_RFPT (Bit 1) */ -#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Msk (0x2UL) /*!< GPIO TEST_CTRL_REG: ENABLE_RFPT (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Pos (2UL) /*!< GPIO TEST_CTRL_REG: SHOW_PLL_TEST_OUT (Bit 2) */ -#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Msk (0x4UL) /*!< GPIO TEST_CTRL_REG: SHOW_PLL_TEST_OUT (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Pos (3UL) /*!< GPIO TEST_CTRL_REG: SHOW_DCDC_TESTBUS (Bit 3) */ -#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Msk (0x8UL) /*!< GPIO TEST_CTRL_REG: SHOW_DCDC_TESTBUS (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Pos (4UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_CAP_TEST_EN (Bit 4) */ -#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Msk (0x10UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_CAP_TEST_EN (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Pos (5UL) /*!< GPIO TEST_CTRL_REG: SHOW_IF_RO (Bit 5) */ -#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Msk (0x20UL) /*!< GPIO TEST_CTRL_REG: SHOW_IF_RO (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Pos (6UL) /*!< GPIO TEST_CTRL_REG: PLL_TST_MODE (Bit 6) */ -#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Msk (0x40UL) /*!< GPIO TEST_CTRL_REG: PLL_TST_MODE (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Pos (7UL) /*!< GPIO TEST_CTRL_REG: SHOW_TXDAC_MOD (Bit 7) */ -#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Msk (0x80UL) /*!< GPIO TEST_CTRL_REG: SHOW_TXDAC_MOD (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Pos (8UL) /*!< GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bit 8) */ -#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Msk (0x700UL) /*!< GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bitfield-Mask: 0x07) */ -#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Pos (12UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bit 12) */ -#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Msk (0x3000UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bitfield-Mask: 0x03) */ -#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Pos (14UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bit 14) */ -#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Msk (0x4000UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPIO_TEST_CTRL2_REG ---------------------------- */ -#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Pos (0UL) /*!< GPIO TEST_CTRL2_REG: ANA_TESTMUX_CTRL (Bit 0) */ -#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Msk (0xfUL) /*!< GPIO TEST_CTRL2_REG: ANA_TESTMUX_CTRL (Bitfield-Mask: 0x0f) */ -#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Pos (8UL) /*!< GPIO TEST_CTRL2_REG: RF_IN_TESTMUX_CTRL (Bit 8) */ -#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Msk (0x300UL) /*!< GPIO TEST_CTRL2_REG: RF_IN_TESTMUX_CTRL (Bitfield-Mask: 0x03) */ - -/* ----------------------------- GPIO_TEST_CTRL3_REG ---------------------------- */ -#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Pos (0UL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bit 0) */ -#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Msk (0x3fUL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bitfield-Mask: 0x3f) */ -#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Pos (6UL) /*!< GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bit 6) */ -#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Msk (0x40UL) /*!< GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Pos (8UL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bit 8) */ -#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Msk (0xff00UL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bitfield-Mask: 0xff) */ - -/* ----------------------------- GPIO_TEST_CTRL4_REG ---------------------------- */ -#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Pos (0UL) /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_SEL (Bit 0) */ -#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Msk (0x7UL) /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_SEL (Bitfield-Mask: 0x07) */ -#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Pos (8UL) /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_PARAM (Bit 8) */ -#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Msk (0xff00UL) /*!< GPIO TEST_CTRL4_REG: RF_TEST_IN_PARAM (Bitfield-Mask: 0xff) */ - -/* ----------------------------- GPIO_TEST_CTRL5_REG ---------------------------- */ -#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Pos (0UL) /*!< GPIO TEST_CTRL5_REG: TEST_BUS_TO_AVS (Bit 0) */ -#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Msk (0x1UL) /*!< GPIO TEST_CTRL5_REG: TEST_BUS_TO_AVS (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Pos (1UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V4 (Bit 1) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Msk (0x2UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V4 (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Pos (2UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_FLASH (Bit 2) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Msk (0x4UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_FLASH (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Pos (3UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_CORE (Bit 3) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Msk (0x8UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_CORE (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Pos (4UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_PA (Bit 4) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Msk (0x10UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_1V8_PA (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Pos (5UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_ADC (Bit 5) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Msk (0x20UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_ADC (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Pos (6UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_PLL (Bit 6) */ -#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Msk (0x40UL) /*!< GPIO TEST_CTRL5_REG: TEST_LDO_PLL (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Pos (7UL) /*!< GPIO TEST_CTRL5_REG: TEST_BANDGAP_I_TEST (Bit 7) */ -#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Msk (0x80UL) /*!< GPIO TEST_CTRL5_REG: TEST_BANDGAP_I_TEST (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Pos (8UL) /*!< GPIO TEST_CTRL5_REG: TEST_SIMO_BUCK (Bit 8) */ -#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Msk (0x100UL) /*!< GPIO TEST_CTRL5_REG: TEST_SIMO_BUCK (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Pos (9UL) /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_OUT (Bit 9) */ -#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Msk (0x200UL) /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_OUT (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Pos (10UL) /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_IN (Bit 10) */ -#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Msk (0x400UL) /*!< GPIO TEST_CTRL5_REG: TEST_BOD_VREF_IN (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Pos (11UL) /*!< GPIO TEST_CTRL5_REG: TEST_I_DCDC_FILT (Bit 11) */ -#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Msk (0x800UL) /*!< GPIO TEST_CTRL5_REG: TEST_I_DCDC_FILT (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Pos (12UL) /*!< GPIO TEST_CTRL5_REG: TEST_VCONT_A (Bit 12) */ -#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Msk (0x1000UL) /*!< GPIO TEST_CTRL5_REG: TEST_VCONT_A (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Pos (13UL) /*!< GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bit 13) */ -#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Msk (0x2000UL) /*!< GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bitfield-Mask: 0x01) */ -#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Pos (14UL) /*!< GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bit 14) */ -#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Msk (0x4000UL) /*!< GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'GPREG' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- GPREG_SET_FREEZE_REG ---------------------------- */ -#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< GPREG SET_FREEZE_REG: FRZ_WKUPTIM (Bit 0) */ -#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< GPREG SET_FREEZE_REG: FRZ_WKUPTIM (Bitfield-Mask: 0x01) */ -#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Pos (1UL) /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM0 (Bit 1) */ -#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Msk (0x2UL) /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM0 (Bitfield-Mask: 0x01) */ -#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Pos (2UL) /*!< GPREG SET_FREEZE_REG: FRZ_BLETIM (Bit 2) */ -#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Msk (0x4UL) /*!< GPREG SET_FREEZE_REG: FRZ_BLETIM (Bitfield-Mask: 0x01) */ -#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Pos (3UL) /*!< GPREG SET_FREEZE_REG: FRZ_WDOG (Bit 3) */ -#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk (0x8UL) /*!< GPREG SET_FREEZE_REG: FRZ_WDOG (Bitfield-Mask: 0x01) */ -#define GPREG_SET_FREEZE_REG_FRZ_USB_Pos (4UL) /*!< GPREG SET_FREEZE_REG: FRZ_USB (Bit 4) */ -#define GPREG_SET_FREEZE_REG_FRZ_USB_Msk (0x10UL) /*!< GPREG SET_FREEZE_REG: FRZ_USB (Bitfield-Mask: 0x01) */ -#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos (5UL) /*!< GPREG SET_FREEZE_REG: FRZ_DMA (Bit 5) */ -#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk (0x20UL) /*!< GPREG SET_FREEZE_REG: FRZ_DMA (Bitfield-Mask: 0x01) */ -#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Pos (6UL) /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM1 (Bit 6) */ -#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk (0x40UL) /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM1 (Bitfield-Mask: 0x01) */ -#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos (7UL) /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM2 (Bit 7) */ -#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x80UL) /*!< GPREG SET_FREEZE_REG: FRZ_SWTIM2 (Bitfield-Mask: 0x01) */ - -/* --------------------------- GPREG_RESET_FREEZE_REG --------------------------- */ -#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< GPREG RESET_FREEZE_REG: FRZ_WKUPTIM (Bit 0) */ -#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< GPREG RESET_FREEZE_REG: FRZ_WKUPTIM (Bitfield-Mask: 0x01) */ -#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Pos (1UL) /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM0 (Bit 1) */ -#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Msk (0x2UL) /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM0 (Bitfield-Mask: 0x01) */ -#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Pos (2UL) /*!< GPREG RESET_FREEZE_REG: FRZ_BLETIM (Bit 2) */ -#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Msk (0x4UL) /*!< GPREG RESET_FREEZE_REG: FRZ_BLETIM (Bitfield-Mask: 0x01) */ -#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Pos (3UL) /*!< GPREG RESET_FREEZE_REG: FRZ_WDOG (Bit 3) */ -#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk (0x8UL) /*!< GPREG RESET_FREEZE_REG: FRZ_WDOG (Bitfield-Mask: 0x01) */ -#define GPREG_RESET_FREEZE_REG_FRZ_USB_Pos (4UL) /*!< GPREG RESET_FREEZE_REG: FRZ_USB (Bit 4) */ -#define GPREG_RESET_FREEZE_REG_FRZ_USB_Msk (0x10UL) /*!< GPREG RESET_FREEZE_REG: FRZ_USB (Bitfield-Mask: 0x01) */ -#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos (5UL) /*!< GPREG RESET_FREEZE_REG: FRZ_DMA (Bit 5) */ -#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk (0x20UL) /*!< GPREG RESET_FREEZE_REG: FRZ_DMA (Bitfield-Mask: 0x01) */ -#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Pos (6UL) /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM1 (Bit 6) */ -#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Msk (0x40UL) /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM1 (Bitfield-Mask: 0x01) */ -#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (7UL) /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM2 (Bit 7) */ -#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x80UL) /*!< GPREG RESET_FREEZE_REG: FRZ_SWTIM2 (Bitfield-Mask: 0x01) */ - -/* ------------------------------- GPREG_DEBUG_REG ------------------------------ */ -#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Pos (0UL) /*!< GPREG DEBUG_REG: DEBUGS_FREEZE_EN (Bit 0) */ -#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Msk (0x1UL) /*!< GPREG DEBUG_REG: DEBUGS_FREEZE_EN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- GPREG_GP_STATUS_REG ---------------------------- */ -#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL) /*!< GPREG GP_STATUS_REG: CAL_PHASE (Bit 0) */ -#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL) /*!< GPREG GP_STATUS_REG: CAL_PHASE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- GPREG_GP_CONTROL_REG ---------------------------- */ -#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Pos (0UL) /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_REQ (Bit 0) */ -#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Msk (0x1UL) /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_REQ (Bitfield-Mask: 0x01) */ -#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Pos (1UL) /*!< GPREG GP_CONTROL_REG: BLE_H2H_BRIDGE_BYPASS (Bit 1) */ -#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Msk (0x2UL) /*!< GPREG GP_CONTROL_REG: BLE_H2H_BRIDGE_BYPASS (Bitfield-Mask: 0x01) */ -#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Pos (2UL) /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bit 2) */ -#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Msk (0x4UL) /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bitfield-Mask: 0x01) */ - -/* --------------------------- GPREG_ECC_BASE_ADDR_REG -------------------------- */ -#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Pos (0UL) /*!< GPREG ECC_BASE_ADDR_REG: ECC_BASE_ADDR (Bit 0) */ -#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Msk (0x7fUL) /*!< GPREG ECC_BASE_ADDR_REG: ECC_BASE_ADDR (Bitfield-Mask: 0x7f) */ - -/* ---------------------------- GPREG_LED_CONTROL_REG --------------------------- */ -#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Pos (0UL) /*!< GPREG LED_CONTROL_REG: LED1_SRC_SEL (Bit 0) */ -#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Msk (0x1UL) /*!< GPREG LED_CONTROL_REG: LED1_SRC_SEL (Bitfield-Mask: 0x01) */ -#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Pos (1UL) /*!< GPREG LED_CONTROL_REG: LED2_SRC_SEL (Bit 1) */ -#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Msk (0x2UL) /*!< GPREG LED_CONTROL_REG: LED2_SRC_SEL (Bitfield-Mask: 0x01) */ -#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Pos (2UL) /*!< GPREG LED_CONTROL_REG: LED3_SRC_SEL (Bit 2) */ -#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Msk (0x4UL) /*!< GPREG LED_CONTROL_REG: LED3_SRC_SEL (Bitfield-Mask: 0x01) */ -#define GPREG_LED_CONTROL_REG_LED1_EN_Pos (3UL) /*!< GPREG LED_CONTROL_REG: LED1_EN (Bit 3) */ -#define GPREG_LED_CONTROL_REG_LED1_EN_Msk (0x8UL) /*!< GPREG LED_CONTROL_REG: LED1_EN (Bitfield-Mask: 0x01) */ -#define GPREG_LED_CONTROL_REG_LED2_EN_Pos (4UL) /*!< GPREG LED_CONTROL_REG: LED2_EN (Bit 4) */ -#define GPREG_LED_CONTROL_REG_LED2_EN_Msk (0x10UL) /*!< GPREG LED_CONTROL_REG: LED2_EN (Bitfield-Mask: 0x01) */ -#define GPREG_LED_CONTROL_REG_LED3_EN_Pos (5UL) /*!< GPREG LED_CONTROL_REG: LED3_EN (Bit 5) */ -#define GPREG_LED_CONTROL_REG_LED3_EN_Msk (0x20UL) /*!< GPREG LED_CONTROL_REG: LED3_EN (Bitfield-Mask: 0x01) */ -#define GPREG_LED_CONTROL_REG_LED_TRIM_Pos (6UL) /*!< GPREG LED_CONTROL_REG: LED_TRIM (Bit 6) */ -#define GPREG_LED_CONTROL_REG_LED_TRIM_Msk (0x3c0UL) /*!< GPREG LED_CONTROL_REG: LED_TRIM (Bitfield-Mask: 0x0f) */ - -/* ------------------------- GPREG_BLE_FINECNT_SAMP_REG ------------------------- */ -#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Pos (0UL) /*!< GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bit 0) */ -#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Msk (0x3ffUL) /*!< GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bitfield-Mask: 0x3ff) */ - -/* --------------------------- GPREG_PLL_SYS_CTRL1_REG -------------------------- */ -#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Pos (0UL) /*!< GPREG PLL_SYS_CTRL1_REG: PLL_EN (Bit 0) */ -#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Msk (0x1UL) /*!< GPREG PLL_SYS_CTRL1_REG: PLL_EN (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos (1UL) /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_ENABLE (Bit 1) */ -#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk (0x2UL) /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_ENABLE (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos (2UL) /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_VREF_HOLD (Bit 2) */ -#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk (0x4UL) /*!< GPREG PLL_SYS_CTRL1_REG: LDO_PLL_VREF_HOLD (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Pos (8UL) /*!< GPREG PLL_SYS_CTRL1_REG: PLL_R_DIV (Bit 8) */ -#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Msk (0x7f00UL) /*!< GPREG PLL_SYS_CTRL1_REG: PLL_R_DIV (Bitfield-Mask: 0x7f) */ - -/* --------------------------- GPREG_PLL_SYS_CTRL2_REG -------------------------- */ -#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Pos (0UL) /*!< GPREG PLL_SYS_CTRL2_REG: PLL_N_DIV (Bit 0) */ -#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Msk (0x7fUL) /*!< GPREG PLL_SYS_CTRL2_REG: PLL_N_DIV (Bitfield-Mask: 0x7f) */ -#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Pos (12UL) /*!< GPREG PLL_SYS_CTRL2_REG: PLL_DEL_SEL (Bit 12) */ -#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Msk (0x3000UL) /*!< GPREG PLL_SYS_CTRL2_REG: PLL_DEL_SEL (Bitfield-Mask: 0x03) */ -#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Pos (14UL) /*!< GPREG PLL_SYS_CTRL2_REG: PLL_SEL_MIN_CUR_INT (Bit 14) */ -#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Msk (0x4000UL) /*!< GPREG PLL_SYS_CTRL2_REG: PLL_SEL_MIN_CUR_INT (Bitfield-Mask: 0x01) */ - -/* --------------------------- GPREG_PLL_SYS_CTRL3_REG -------------------------- */ -#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Pos (0UL) /*!< GPREG PLL_SYS_CTRL3_REG: PLL_ICP_SEL (Bit 0) */ -#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Msk (0x1fUL) /*!< GPREG PLL_SYS_CTRL3_REG: PLL_ICP_SEL (Bitfield-Mask: 0x1f) */ -#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Pos (10UL) /*!< GPREG PLL_SYS_CTRL3_REG: PLL_START_DEL (Bit 10) */ -#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Msk (0x7c00UL) /*!< GPREG PLL_SYS_CTRL3_REG: PLL_START_DEL (Bitfield-Mask: 0x1f) */ -#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Pos (15UL) /*!< GPREG PLL_SYS_CTRL3_REG: PLL_RECALIB (Bit 15) */ -#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Msk (0x8000UL) /*!< GPREG PLL_SYS_CTRL3_REG: PLL_RECALIB (Bitfield-Mask: 0x01) */ - -/* -------------------------- GPREG_PLL_SYS_STATUS_REG -------------------------- */ -#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos (0UL) /*!< GPREG PLL_SYS_STATUS_REG: PLL_LOCK_FINE (Bit 0) */ -#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk (0x1UL) /*!< GPREG PLL_SYS_STATUS_REG: PLL_LOCK_FINE (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos (1UL) /*!< GPREG PLL_SYS_STATUS_REG: LDO_PLL_OK (Bit 1) */ -#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk (0x2UL) /*!< GPREG PLL_SYS_STATUS_REG: LDO_PLL_OK (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Pos (5UL) /*!< GPREG PLL_SYS_STATUS_REG: PLL_PLL_BEST_MIN_CUR (Bit 5) */ -#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Msk (0x7e0UL) /*!< GPREG PLL_SYS_STATUS_REG: PLL_PLL_BEST_MIN_CUR (Bitfield-Mask: 0x3f) */ -#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Pos (11UL) /*!< GPREG PLL_SYS_STATUS_REG: PLL_CALIBR_END (Bit 11) */ -#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Msk (0x800UL) /*!< GPREG PLL_SYS_STATUS_REG: PLL_CALIBR_END (Bitfield-Mask: 0x01) */ - -/* --------------------------- GPREG_PLL_SYS_TEST_REG --------------------------- */ -#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Pos (0UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_DIS_LOOPFILT (Bit 0) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Msk (0x1UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_DIS_LOOPFILT (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Pos (1UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_MIN_CURRENT (Bit 1) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Msk (0x7eUL) /*!< GPREG PLL_SYS_TEST_REG: PLL_MIN_CURRENT (Bitfield-Mask: 0x3f) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Pos (7UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_TEST_VCTR (Bit 7) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Msk (0x80UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_TEST_VCTR (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Pos (8UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_OPEN_LOOP (Bit 8) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Msk (0x100UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_OPEN_LOOP (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Pos (9UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_CHANGE (Bit 9) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Msk (0x200UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_CHANGE (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Pos (10UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_N_DIV_TEST (Bit 10) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Msk (0x400UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_N_DIV_TEST (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Pos (11UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_R_DIV_TEST (Bit 11) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Msk (0x800UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_SEL_R_DIV_TEST (Bitfield-Mask: 0x01) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Pos (13UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_LOCK_DET_RES_CNT (Bit 13) */ -#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Msk (0xe000UL) /*!< GPREG PLL_SYS_TEST_REG: PLL_LOCK_DET_RES_CNT (Bitfield-Mask: 0x07) */ - - -/* ================================================================================ */ -/* ================ struct 'I2C' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- I2C_I2C_CON_REG ------------------------------ */ -#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C I2C_CON_REG: I2C_MASTER_MODE (Bit 0) */ -#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C I2C_CON_REG: I2C_MASTER_MODE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C I2C_CON_REG: I2C_SPEED (Bit 1) */ -#define I2C_I2C_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C I2C_CON_REG: I2C_SPEED (Bitfield-Mask: 0x03) */ -#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C I2C_CON_REG: I2C_10BITADDR_SLAVE (Bit 3) */ -#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C I2C_CON_REG: I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C I2C_CON_REG: I2C_10BITADDR_MASTER (Bit 4) */ -#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C I2C_CON_REG: I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C I2C_CON_REG: I2C_RESTART_EN (Bit 5) */ -#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C I2C_CON_REG: I2C_RESTART_EN (Bitfield-Mask: 0x01) */ -#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C I2C_CON_REG: I2C_SLAVE_DISABLE (Bit 6) */ -#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C I2C_CON_REG: I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- I2C_I2C_TAR_REG ------------------------------ */ -#define I2C_I2C_TAR_REG_IC_TAR_Pos (0UL) /*!< I2C I2C_TAR_REG: IC_TAR (Bit 0) */ -#define I2C_I2C_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< I2C I2C_TAR_REG: IC_TAR (Bitfield-Mask: 0x3ff) */ -#define I2C_I2C_TAR_REG_GC_OR_START_Pos (10UL) /*!< I2C I2C_TAR_REG: GC_OR_START (Bit 10) */ -#define I2C_I2C_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< I2C I2C_TAR_REG: GC_OR_START (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TAR_REG_SPECIAL_Pos (11UL) /*!< I2C I2C_TAR_REG: SPECIAL (Bit 11) */ -#define I2C_I2C_TAR_REG_SPECIAL_Msk (0x800UL) /*!< I2C I2C_TAR_REG: SPECIAL (Bitfield-Mask: 0x01) */ - -/* ------------------------------- I2C_I2C_SAR_REG ------------------------------ */ -#define I2C_I2C_SAR_REG_IC_SAR_Pos (0UL) /*!< I2C I2C_SAR_REG: IC_SAR (Bit 0) */ -#define I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< I2C I2C_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff) */ - -/* ---------------------------- I2C_I2C_DATA_CMD_REG ---------------------------- */ -#define I2C_I2C_DATA_CMD_REG_DAT_Pos (0UL) /*!< I2C I2C_DATA_CMD_REG: DAT (Bit 0) */ -#define I2C_I2C_DATA_CMD_REG_DAT_Msk (0xffUL) /*!< I2C I2C_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff) */ -#define I2C_I2C_DATA_CMD_REG_CMD_Pos (8UL) /*!< I2C I2C_DATA_CMD_REG: CMD (Bit 8) */ -#define I2C_I2C_DATA_CMD_REG_CMD_Msk (0x100UL) /*!< I2C I2C_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01) */ -#define I2C_I2C_DATA_CMD_REG_STOP_Pos (9UL) /*!< I2C I2C_DATA_CMD_REG: STOP (Bit 9) */ -#define I2C_I2C_DATA_CMD_REG_STOP_Msk (0x200UL) /*!< I2C I2C_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01) */ -#define I2C_I2C_DATA_CMD_REG_RESTART_Pos (10UL) /*!< I2C I2C_DATA_CMD_REG: RESTART (Bit 10) */ -#define I2C_I2C_DATA_CMD_REG_RESTART_Msk (0x400UL) /*!< I2C I2C_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C_I2C_SS_SCL_HCNT_REG -------------------------- */ -#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< I2C I2C_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0) */ -#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< I2C I2C_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C_I2C_SS_SCL_LCNT_REG -------------------------- */ -#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< I2C I2C_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bit 0) */ -#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< I2C I2C_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C_I2C_FS_SCL_HCNT_REG -------------------------- */ -#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< I2C I2C_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bit 0) */ -#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< I2C I2C_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C_I2C_FS_SCL_LCNT_REG -------------------------- */ -#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< I2C I2C_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bit 0) */ -#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< I2C I2C_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- I2C_I2C_INTR_STAT_REG --------------------------- */ -#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_UNDER (Bit 0) */ -#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_UNDER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_OVER (Bit 1) */ -#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_OVER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_FULL (Bit 2) */ -#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_FULL (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< I2C I2C_INTR_STAT_REG: R_TX_OVER (Bit 3) */ -#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< I2C I2C_INTR_STAT_REG: R_TX_OVER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< I2C I2C_INTR_STAT_REG: R_TX_EMPTY (Bit 4) */ -#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< I2C I2C_INTR_STAT_REG: R_TX_EMPTY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< I2C I2C_INTR_STAT_REG: R_RD_REQ (Bit 5) */ -#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< I2C I2C_INTR_STAT_REG: R_RD_REQ (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< I2C I2C_INTR_STAT_REG: R_TX_ABRT (Bit 6) */ -#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< I2C I2C_INTR_STAT_REG: R_TX_ABRT (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_DONE (Bit 7) */ -#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< I2C I2C_INTR_STAT_REG: R_RX_DONE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< I2C I2C_INTR_STAT_REG: R_ACTIVITY (Bit 8) */ -#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< I2C I2C_INTR_STAT_REG: R_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< I2C I2C_INTR_STAT_REG: R_STOP_DET (Bit 9) */ -#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< I2C I2C_INTR_STAT_REG: R_STOP_DET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< I2C I2C_INTR_STAT_REG: R_START_DET (Bit 10) */ -#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< I2C I2C_INTR_STAT_REG: R_START_DET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< I2C I2C_INTR_STAT_REG: R_GEN_CALL (Bit 11) */ -#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< I2C I2C_INTR_STAT_REG: R_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- I2C_I2C_INTR_MASK_REG --------------------------- */ -#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_UNDER (Bit 0) */ -#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_UNDER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_OVER (Bit 1) */ -#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_OVER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_FULL (Bit 2) */ -#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_FULL (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< I2C I2C_INTR_MASK_REG: M_TX_OVER (Bit 3) */ -#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< I2C I2C_INTR_MASK_REG: M_TX_OVER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< I2C I2C_INTR_MASK_REG: M_TX_EMPTY (Bit 4) */ -#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< I2C I2C_INTR_MASK_REG: M_TX_EMPTY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< I2C I2C_INTR_MASK_REG: M_RD_REQ (Bit 5) */ -#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< I2C I2C_INTR_MASK_REG: M_RD_REQ (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< I2C I2C_INTR_MASK_REG: M_TX_ABRT (Bit 6) */ -#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< I2C I2C_INTR_MASK_REG: M_TX_ABRT (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_DONE (Bit 7) */ -#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< I2C I2C_INTR_MASK_REG: M_RX_DONE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< I2C I2C_INTR_MASK_REG: M_ACTIVITY (Bit 8) */ -#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< I2C I2C_INTR_MASK_REG: M_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< I2C I2C_INTR_MASK_REG: M_STOP_DET (Bit 9) */ -#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< I2C I2C_INTR_MASK_REG: M_STOP_DET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< I2C I2C_INTR_MASK_REG: M_START_DET (Bit 10) */ -#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< I2C I2C_INTR_MASK_REG: M_START_DET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< I2C I2C_INTR_MASK_REG: M_GEN_CALL (Bit 11) */ -#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< I2C I2C_INTR_MASK_REG: M_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_RAW_INTR_STAT_REG ------------------------- */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_UNDER (Bit 0) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_UNDER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_OVER (Bit 1) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_OVER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_FULL (Bit 2) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_FULL (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< I2C I2C_RAW_INTR_STAT_REG: TX_OVER (Bit 3) */ -#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< I2C I2C_RAW_INTR_STAT_REG: TX_OVER (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< I2C I2C_RAW_INTR_STAT_REG: TX_EMPTY (Bit 4) */ -#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< I2C I2C_RAW_INTR_STAT_REG: TX_EMPTY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RD_REQ (Bit 5) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RD_REQ (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< I2C I2C_RAW_INTR_STAT_REG: TX_ABRT (Bit 6) */ -#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< I2C I2C_RAW_INTR_STAT_REG: TX_ABRT (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_DONE (Bit 7) */ -#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< I2C I2C_RAW_INTR_STAT_REG: RX_DONE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< I2C I2C_RAW_INTR_STAT_REG: ACTIVITY (Bit 8) */ -#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< I2C I2C_RAW_INTR_STAT_REG: ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< I2C I2C_RAW_INTR_STAT_REG: STOP_DET (Bit 9) */ -#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< I2C I2C_RAW_INTR_STAT_REG: STOP_DET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< I2C I2C_RAW_INTR_STAT_REG: START_DET (Bit 10) */ -#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< I2C I2C_RAW_INTR_STAT_REG: START_DET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< I2C I2C_RAW_INTR_STAT_REG: GEN_CALL (Bit 11) */ -#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< I2C I2C_RAW_INTR_STAT_REG: GEN_CALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ I2C_I2C_RX_TL_REG ----------------------------- */ -#define I2C_I2C_RX_TL_REG_RX_TL_Pos (0UL) /*!< I2C I2C_RX_TL_REG: RX_TL (Bit 0) */ -#define I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< I2C I2C_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f) */ - -/* ------------------------------ I2C_I2C_TX_TL_REG ----------------------------- */ -#define I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL) /*!< I2C I2C_TX_TL_REG: TX_TL (Bit 0) */ -#define I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< I2C I2C_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- I2C_I2C_CLR_INTR_REG ---------------------------- */ -#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< I2C I2C_CLR_INTR_REG: CLR_INTR (Bit 0) */ -#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< I2C I2C_CLR_INTR_REG: CLR_INTR (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_CLR_RX_UNDER_REG -------------------------- */ -#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< I2C I2C_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bit 0) */ -#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< I2C I2C_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C_I2C_CLR_RX_OVER_REG -------------------------- */ -#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< I2C I2C_CLR_RX_OVER_REG: CLR_RX_OVER (Bit 0) */ -#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< I2C I2C_CLR_RX_OVER_REG: CLR_RX_OVER (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C_I2C_CLR_TX_OVER_REG -------------------------- */ -#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< I2C I2C_CLR_TX_OVER_REG: CLR_TX_OVER (Bit 0) */ -#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< I2C I2C_CLR_TX_OVER_REG: CLR_TX_OVER (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C_I2C_CLR_RD_REQ_REG --------------------------- */ -#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< I2C I2C_CLR_RD_REQ_REG: CLR_RD_REQ (Bit 0) */ -#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< I2C I2C_CLR_RD_REQ_REG: CLR_RD_REQ (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C_I2C_CLR_TX_ABRT_REG -------------------------- */ -#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< I2C I2C_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bit 0) */ -#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< I2C I2C_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C_I2C_CLR_RX_DONE_REG -------------------------- */ -#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< I2C I2C_CLR_RX_DONE_REG: CLR_RX_DONE (Bit 0) */ -#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< I2C I2C_CLR_RX_DONE_REG: CLR_RX_DONE (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_CLR_ACTIVITY_REG -------------------------- */ -#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< I2C I2C_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bit 0) */ -#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< I2C I2C_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_CLR_STOP_DET_REG -------------------------- */ -#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos (0UL) /*!< I2C I2C_CLR_STOP_DET_REG: CLR_ACTIVITY (Bit 0) */ -#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< I2C I2C_CLR_STOP_DET_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_CLR_START_DET_REG ------------------------- */ -#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< I2C I2C_CLR_START_DET_REG: CLR_START_DET (Bit 0) */ -#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< I2C I2C_CLR_START_DET_REG: CLR_START_DET (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_CLR_GEN_CALL_REG -------------------------- */ -#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< I2C I2C_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bit 0) */ -#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< I2C I2C_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- I2C_I2C_ENABLE_REG ----------------------------- */ -#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Pos (0UL) /*!< I2C I2C_ENABLE_REG: CTRL_ENABLE (Bit 0) */ -#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Msk (0x1UL) /*!< I2C I2C_ENABLE_REG: CTRL_ENABLE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- I2C_I2C_STATUS_REG ----------------------------- */ -#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C I2C_STATUS_REG: I2C_ACTIVITY (Bit 0) */ -#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C I2C_STATUS_REG: I2C_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_STATUS_REG_TFNF_Pos (1UL) /*!< I2C I2C_STATUS_REG: TFNF (Bit 1) */ -#define I2C_I2C_STATUS_REG_TFNF_Msk (0x2UL) /*!< I2C I2C_STATUS_REG: TFNF (Bitfield-Mask: 0x01) */ -#define I2C_I2C_STATUS_REG_TFE_Pos (2UL) /*!< I2C I2C_STATUS_REG: TFE (Bit 2) */ -#define I2C_I2C_STATUS_REG_TFE_Msk (0x4UL) /*!< I2C I2C_STATUS_REG: TFE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_STATUS_REG_RFNE_Pos (3UL) /*!< I2C I2C_STATUS_REG: RFNE (Bit 3) */ -#define I2C_I2C_STATUS_REG_RFNE_Msk (0x8UL) /*!< I2C I2C_STATUS_REG: RFNE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_STATUS_REG_RFF_Pos (4UL) /*!< I2C I2C_STATUS_REG: RFF (Bit 4) */ -#define I2C_I2C_STATUS_REG_RFF_Msk (0x10UL) /*!< I2C I2C_STATUS_REG: RFF (Bitfield-Mask: 0x01) */ -#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< I2C I2C_STATUS_REG: MST_ACTIVITY (Bit 5) */ -#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< I2C I2C_STATUS_REG: MST_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< I2C I2C_STATUS_REG: SLV_ACTIVITY (Bit 6) */ -#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< I2C I2C_STATUS_REG: SLV_ACTIVITY (Bitfield-Mask: 0x01) */ - -/* ------------------------------ I2C_I2C_TXFLR_REG ----------------------------- */ -#define I2C_I2C_TXFLR_REG_TXFLR_Pos (0UL) /*!< I2C I2C_TXFLR_REG: TXFLR (Bit 0) */ -#define I2C_I2C_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< I2C I2C_TXFLR_REG: TXFLR (Bitfield-Mask: 0x3f) */ - -/* ------------------------------ I2C_I2C_RXFLR_REG ----------------------------- */ -#define I2C_I2C_RXFLR_REG_RXFLR_Pos (0UL) /*!< I2C I2C_RXFLR_REG: RXFLR (Bit 0) */ -#define I2C_I2C_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< I2C I2C_RXFLR_REG: RXFLR (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- I2C_I2C_SDA_HOLD_REG ---------------------------- */ -#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Pos (0UL) /*!< I2C I2C_SDA_HOLD_REG: IC_SDA_HOLD (Bit 0) */ -#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Msk (0xffffUL) /*!< I2C I2C_SDA_HOLD_REG: IC_SDA_HOLD (Bitfield-Mask: 0xffff) */ - -/* ------------------------- I2C_I2C_TX_ABRT_SOURCE_REG ------------------------- */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bit 0) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bit 1) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bit 2) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bit 3) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bit 4) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bit 5) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bit 6) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bit 7) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bit 8) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bit 9) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bit 10) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bit 11) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ARB_LOST (Bit 12) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ARB_LOST (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bit 13) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bit 14) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bit 15) */ -#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */ - -/* ----------------------------- I2C_I2C_DMA_CR_REG ----------------------------- */ -#define I2C_I2C_DMA_CR_REG_RDMAE_Pos (0UL) /*!< I2C I2C_DMA_CR_REG: RDMAE (Bit 0) */ -#define I2C_I2C_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< I2C I2C_DMA_CR_REG: RDMAE (Bitfield-Mask: 0x01) */ -#define I2C_I2C_DMA_CR_REG_TDMAE_Pos (1UL) /*!< I2C I2C_DMA_CR_REG: TDMAE (Bit 1) */ -#define I2C_I2C_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< I2C I2C_DMA_CR_REG: TDMAE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- I2C_I2C_DMA_TDLR_REG ---------------------------- */ -#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< I2C I2C_DMA_TDLR_REG: DMATDL (Bit 0) */ -#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< I2C I2C_DMA_TDLR_REG: DMATDL (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- I2C_I2C_DMA_RDLR_REG ---------------------------- */ -#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< I2C I2C_DMA_RDLR_REG: DMARDL (Bit 0) */ -#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< I2C I2C_DMA_RDLR_REG: DMARDL (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- I2C_I2C_SDA_SETUP_REG --------------------------- */ -#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< I2C I2C_SDA_SETUP_REG: SDA_SETUP (Bit 0) */ -#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< I2C I2C_SDA_SETUP_REG: SDA_SETUP (Bitfield-Mask: 0xff) */ - -/* ------------------------ I2C_I2C_ACK_GENERAL_CALL_REG ------------------------ */ -#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< I2C I2C_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bit 0) */ -#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< I2C I2C_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_ENABLE_STATUS_REG ------------------------- */ -#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< I2C I2C_ENABLE_STATUS_REG: IC_EN (Bit 0) */ -#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< I2C I2C_ENABLE_STATUS_REG: IC_EN (Bitfield-Mask: 0x01) */ -#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< I2C I2C_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bit 1) */ -#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< I2C I2C_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */ -#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< I2C I2C_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bit 2) */ -#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< I2C I2C_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C_I2C_IC_FS_SPKLEN_REG -------------------------- */ -#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos (0UL) /*!< I2C I2C_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bit 0) */ -#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk (0xffUL) /*!< I2C I2C_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bitfield-Mask: 0xff) */ - -/* --------------------------- I2C_I2C_COMP_PARAM1_REG -------------------------- */ -#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos (0UL) /*!< I2C I2C_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bit 0) */ -#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk (0xffffUL) /*!< I2C I2C_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C_I2C_COMP_PARAM2_REG -------------------------- */ -#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos (0UL) /*!< I2C I2C_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bit 0) */ -#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk (0xffffUL) /*!< I2C I2C_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bitfield-Mask: 0xffff) */ - -/* -------------------------- I2C_I2C_COMP_VERSION_REG -------------------------- */ -#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Pos (0UL) /*!< I2C I2C_COMP_VERSION_REG: IC_COMP_VERSION (Bit 0) */ -#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Msk (0xffffUL) /*!< I2C I2C_COMP_VERSION_REG: IC_COMP_VERSION (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- I2C_I2C_COMP2_VERSION --------------------------- */ -#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Pos (0UL) /*!< I2C I2C_COMP2_VERSION: IC_COMP2_VERSION (Bit 0) */ -#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Msk (0xffffUL) /*!< I2C I2C_COMP2_VERSION: IC_COMP2_VERSION (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- I2C_I2C_COMP_TYPE_REG --------------------------- */ -#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Pos (0UL) /*!< I2C I2C_COMP_TYPE_REG: IC_COMP_TYPE (Bit 0) */ -#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Msk (0xffffUL) /*!< I2C I2C_COMP_TYPE_REG: IC_COMP_TYPE (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C_I2C_COMP_TYPE2_REG --------------------------- */ -#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos (0UL) /*!< I2C I2C_COMP_TYPE2_REG: IC_COMP2_TYPE (Bit 0) */ -#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk (0xffffUL) /*!< I2C I2C_COMP_TYPE2_REG: IC_COMP2_TYPE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'I2C2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------ I2C2_I2C2_CON_REG ----------------------------- */ -#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C2 I2C2_CON_REG: I2C_MASTER_MODE (Bit 0) */ -#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C2 I2C2_CON_REG: I2C_MASTER_MODE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C2 I2C2_CON_REG: I2C_SPEED (Bit 1) */ -#define I2C2_I2C2_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C2 I2C2_CON_REG: I2C_SPEED (Bitfield-Mask: 0x03) */ -#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_SLAVE (Bit 3) */ -#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_MASTER (Bit 4) */ -#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C2 I2C2_CON_REG: I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C2 I2C2_CON_REG: I2C_RESTART_EN (Bit 5) */ -#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C2 I2C2_CON_REG: I2C_RESTART_EN (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C2 I2C2_CON_REG: I2C_SLAVE_DISABLE (Bit 6) */ -#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C2 I2C2_CON_REG: I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ I2C2_I2C2_TAR_REG ----------------------------- */ -#define I2C2_I2C2_TAR_REG_IC_TAR_Pos (0UL) /*!< I2C2 I2C2_TAR_REG: IC_TAR (Bit 0) */ -#define I2C2_I2C2_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< I2C2 I2C2_TAR_REG: IC_TAR (Bitfield-Mask: 0x3ff) */ -#define I2C2_I2C2_TAR_REG_GC_OR_START_Pos (10UL) /*!< I2C2 I2C2_TAR_REG: GC_OR_START (Bit 10) */ -#define I2C2_I2C2_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< I2C2 I2C2_TAR_REG: GC_OR_START (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TAR_REG_SPECIAL_Pos (11UL) /*!< I2C2 I2C2_TAR_REG: SPECIAL (Bit 11) */ -#define I2C2_I2C2_TAR_REG_SPECIAL_Msk (0x800UL) /*!< I2C2 I2C2_TAR_REG: SPECIAL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ I2C2_I2C2_SAR_REG ----------------------------- */ -#define I2C2_I2C2_SAR_REG_IC_SAR_Pos (0UL) /*!< I2C2 I2C2_SAR_REG: IC_SAR (Bit 0) */ -#define I2C2_I2C2_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< I2C2 I2C2_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff) */ - -/* --------------------------- I2C2_I2C2_DATA_CMD_REG --------------------------- */ -#define I2C2_I2C2_DATA_CMD_REG_DAT_Pos (0UL) /*!< I2C2 I2C2_DATA_CMD_REG: DAT (Bit 0) */ -#define I2C2_I2C2_DATA_CMD_REG_DAT_Msk (0xffUL) /*!< I2C2 I2C2_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff) */ -#define I2C2_I2C2_DATA_CMD_REG_CMD_Pos (8UL) /*!< I2C2 I2C2_DATA_CMD_REG: CMD (Bit 8) */ -#define I2C2_I2C2_DATA_CMD_REG_CMD_Msk (0x100UL) /*!< I2C2 I2C2_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_DATA_CMD_REG_STOP_Pos (9UL) /*!< I2C2 I2C2_DATA_CMD_REG: STOP (Bit 9) */ -#define I2C2_I2C2_DATA_CMD_REG_STOP_Msk (0x200UL) /*!< I2C2 I2C2_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_DATA_CMD_REG_RESTART_Pos (10UL) /*!< I2C2 I2C2_DATA_CMD_REG: RESTART (Bit 10) */ -#define I2C2_I2C2_DATA_CMD_REG_RESTART_Msk (0x400UL) /*!< I2C2 I2C2_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C2_I2C2_SS_SCL_HCNT_REG ------------------------- */ -#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< I2C2 I2C2_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0) */ -#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< I2C2 I2C2_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */ - -/* -------------------------- I2C2_I2C2_SS_SCL_LCNT_REG ------------------------- */ -#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< I2C2 I2C2_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bit 0) */ -#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< I2C2 I2C2_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */ - -/* -------------------------- I2C2_I2C2_FS_SCL_HCNT_REG ------------------------- */ -#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< I2C2 I2C2_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bit 0) */ -#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< I2C2 I2C2_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */ - -/* -------------------------- I2C2_I2C2_FS_SCL_LCNT_REG ------------------------- */ -#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< I2C2 I2C2_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bit 0) */ -#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< I2C2 I2C2_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C2_I2C2_INTR_STAT_REG -------------------------- */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_UNDER (Bit 0) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_UNDER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_OVER (Bit 1) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_OVER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_FULL (Bit 2) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_FULL (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_OVER (Bit 3) */ -#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_OVER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_EMPTY (Bit 4) */ -#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_EMPTY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RD_REQ (Bit 5) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RD_REQ (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_ABRT (Bit 6) */ -#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_TX_ABRT (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_DONE (Bit 7) */ -#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_RX_DONE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_ACTIVITY (Bit 8) */ -#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_STOP_DET (Bit 9) */ -#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_STOP_DET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_START_DET (Bit 10) */ -#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_START_DET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_GEN_CALL (Bit 11) */ -#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< I2C2 I2C2_INTR_STAT_REG: R_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C2_I2C2_INTR_MASK_REG -------------------------- */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_UNDER (Bit 0) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_UNDER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_OVER (Bit 1) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_OVER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_FULL (Bit 2) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_FULL (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_OVER (Bit 3) */ -#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_OVER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_EMPTY (Bit 4) */ -#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_EMPTY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RD_REQ (Bit 5) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RD_REQ (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_ABRT (Bit 6) */ -#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_TX_ABRT (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_DONE (Bit 7) */ -#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_RX_DONE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_ACTIVITY (Bit 8) */ -#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_STOP_DET (Bit 9) */ -#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_STOP_DET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_START_DET (Bit 10) */ -#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_START_DET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_GEN_CALL (Bit 11) */ -#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< I2C2 I2C2_INTR_MASK_REG: M_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_RAW_INTR_STAT_REG ------------------------ */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_UNDER (Bit 0) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_UNDER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_OVER (Bit 1) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_OVER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_FULL (Bit 2) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_FULL (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_OVER (Bit 3) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_OVER (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_EMPTY (Bit 4) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_EMPTY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RD_REQ (Bit 5) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RD_REQ (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_ABRT (Bit 6) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: TX_ABRT (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_DONE (Bit 7) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: RX_DONE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: ACTIVITY (Bit 8) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: STOP_DET (Bit 9) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: STOP_DET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: START_DET (Bit 10) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: START_DET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: GEN_CALL (Bit 11) */ -#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< I2C2 I2C2_RAW_INTR_STAT_REG: GEN_CALL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- I2C2_I2C2_RX_TL_REG ---------------------------- */ -#define I2C2_I2C2_RX_TL_REG_RX_TL_Pos (0UL) /*!< I2C2 I2C2_RX_TL_REG: RX_TL (Bit 0) */ -#define I2C2_I2C2_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< I2C2 I2C2_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f) */ - -/* ----------------------------- I2C2_I2C2_TX_TL_REG ---------------------------- */ -#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos (0UL) /*!< I2C2 I2C2_TX_TL_REG: TX_TL (Bit 0) */ -#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< I2C2 I2C2_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f) */ - -/* --------------------------- I2C2_I2C2_CLR_INTR_REG --------------------------- */ -#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< I2C2 I2C2_CLR_INTR_REG: CLR_INTR (Bit 0) */ -#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< I2C2 I2C2_CLR_INTR_REG: CLR_INTR (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_CLR_RX_UNDER_REG ------------------------- */ -#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< I2C2 I2C2_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bit 0) */ -#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< I2C2 I2C2_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C2_I2C2_CLR_RX_OVER_REG ------------------------- */ -#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< I2C2 I2C2_CLR_RX_OVER_REG: CLR_RX_OVER (Bit 0) */ -#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< I2C2 I2C2_CLR_RX_OVER_REG: CLR_RX_OVER (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C2_I2C2_CLR_TX_OVER_REG ------------------------- */ -#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< I2C2 I2C2_CLR_TX_OVER_REG: CLR_TX_OVER (Bit 0) */ -#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< I2C2 I2C2_CLR_TX_OVER_REG: CLR_TX_OVER (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C2_I2C2_CLR_RD_REQ_REG -------------------------- */ -#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< I2C2 I2C2_CLR_RD_REQ_REG: CLR_RD_REQ (Bit 0) */ -#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< I2C2 I2C2_CLR_RD_REQ_REG: CLR_RD_REQ (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C2_I2C2_CLR_TX_ABRT_REG ------------------------- */ -#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< I2C2 I2C2_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bit 0) */ -#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< I2C2 I2C2_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bitfield-Mask: 0x01) */ - -/* -------------------------- I2C2_I2C2_CLR_RX_DONE_REG ------------------------- */ -#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< I2C2 I2C2_CLR_RX_DONE_REG: CLR_RX_DONE (Bit 0) */ -#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< I2C2 I2C2_CLR_RX_DONE_REG: CLR_RX_DONE (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_CLR_ACTIVITY_REG ------------------------- */ -#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< I2C2 I2C2_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bit 0) */ -#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< I2C2 I2C2_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_CLR_STOP_DET_REG ------------------------- */ -#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos (0UL) /*!< I2C2 I2C2_CLR_STOP_DET_REG: CLR_ACTIVITY (Bit 0) */ -#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< I2C2 I2C2_CLR_STOP_DET_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_CLR_START_DET_REG ------------------------ */ -#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< I2C2 I2C2_CLR_START_DET_REG: CLR_START_DET (Bit 0) */ -#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< I2C2 I2C2_CLR_START_DET_REG: CLR_START_DET (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_CLR_GEN_CALL_REG ------------------------- */ -#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< I2C2 I2C2_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bit 0) */ -#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< I2C2 I2C2_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- I2C2_I2C2_ENABLE_REG ---------------------------- */ -#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Pos (0UL) /*!< I2C2 I2C2_ENABLE_REG: CTRL_ENABLE (Bit 0) */ -#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Msk (0x1UL) /*!< I2C2 I2C2_ENABLE_REG: CTRL_ENABLE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- I2C2_I2C2_STATUS_REG ---------------------------- */ -#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C2 I2C2_STATUS_REG: I2C_ACTIVITY (Bit 0) */ -#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C2 I2C2_STATUS_REG: I2C_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_STATUS_REG_TFNF_Pos (1UL) /*!< I2C2 I2C2_STATUS_REG: TFNF (Bit 1) */ -#define I2C2_I2C2_STATUS_REG_TFNF_Msk (0x2UL) /*!< I2C2 I2C2_STATUS_REG: TFNF (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_STATUS_REG_TFE_Pos (2UL) /*!< I2C2 I2C2_STATUS_REG: TFE (Bit 2) */ -#define I2C2_I2C2_STATUS_REG_TFE_Msk (0x4UL) /*!< I2C2 I2C2_STATUS_REG: TFE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_STATUS_REG_RFNE_Pos (3UL) /*!< I2C2 I2C2_STATUS_REG: RFNE (Bit 3) */ -#define I2C2_I2C2_STATUS_REG_RFNE_Msk (0x8UL) /*!< I2C2 I2C2_STATUS_REG: RFNE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_STATUS_REG_RFF_Pos (4UL) /*!< I2C2 I2C2_STATUS_REG: RFF (Bit 4) */ -#define I2C2_I2C2_STATUS_REG_RFF_Msk (0x10UL) /*!< I2C2 I2C2_STATUS_REG: RFF (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< I2C2 I2C2_STATUS_REG: MST_ACTIVITY (Bit 5) */ -#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< I2C2 I2C2_STATUS_REG: MST_ACTIVITY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< I2C2 I2C2_STATUS_REG: SLV_ACTIVITY (Bit 6) */ -#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< I2C2 I2C2_STATUS_REG: SLV_ACTIVITY (Bitfield-Mask: 0x01) */ - -/* ----------------------------- I2C2_I2C2_TXFLR_REG ---------------------------- */ -#define I2C2_I2C2_TXFLR_REG_TXFLR_Pos (0UL) /*!< I2C2 I2C2_TXFLR_REG: TXFLR (Bit 0) */ -#define I2C2_I2C2_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< I2C2 I2C2_TXFLR_REG: TXFLR (Bitfield-Mask: 0x3f) */ - -/* ----------------------------- I2C2_I2C2_RXFLR_REG ---------------------------- */ -#define I2C2_I2C2_RXFLR_REG_RXFLR_Pos (0UL) /*!< I2C2 I2C2_RXFLR_REG: RXFLR (Bit 0) */ -#define I2C2_I2C2_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< I2C2 I2C2_RXFLR_REG: RXFLR (Bitfield-Mask: 0x3f) */ - -/* --------------------------- I2C2_I2C2_SDA_HOLD_REG --------------------------- */ -#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Pos (0UL) /*!< I2C2 I2C2_SDA_HOLD_REG: IC_SDA_HOLD (Bit 0) */ -#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Msk (0xffffUL) /*!< I2C2 I2C2_SDA_HOLD_REG: IC_SDA_HOLD (Bitfield-Mask: 0xffff) */ - -/* ------------------------ I2C2_I2C2_TX_ABRT_SOURCE_REG ------------------------ */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bit 0) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bit 1) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bit 2) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bit 3) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bit 4) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bit 5) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bit 6) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bit 7) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bit 8) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bit 9) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bit 10) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bit 11) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ARB_LOST (Bit 12) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ARB_LOST (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bit 13) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bit 14) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bit 15) */ -#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */ - -/* ---------------------------- I2C2_I2C2_DMA_CR_REG ---------------------------- */ -#define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos (0UL) /*!< I2C2 I2C2_DMA_CR_REG: RDMAE (Bit 0) */ -#define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< I2C2 I2C2_DMA_CR_REG: RDMAE (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos (1UL) /*!< I2C2 I2C2_DMA_CR_REG: TDMAE (Bit 1) */ -#define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< I2C2 I2C2_DMA_CR_REG: TDMAE (Bitfield-Mask: 0x01) */ - -/* --------------------------- I2C2_I2C2_DMA_TDLR_REG --------------------------- */ -#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< I2C2 I2C2_DMA_TDLR_REG: DMATDL (Bit 0) */ -#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< I2C2 I2C2_DMA_TDLR_REG: DMATDL (Bitfield-Mask: 0x1f) */ - -/* --------------------------- I2C2_I2C2_DMA_RDLR_REG --------------------------- */ -#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< I2C2 I2C2_DMA_RDLR_REG: DMARDL (Bit 0) */ -#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< I2C2 I2C2_DMA_RDLR_REG: DMARDL (Bitfield-Mask: 0x1f) */ - -/* --------------------------- I2C2_I2C2_SDA_SETUP_REG -------------------------- */ -#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< I2C2 I2C2_SDA_SETUP_REG: SDA_SETUP (Bit 0) */ -#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< I2C2 I2C2_SDA_SETUP_REG: SDA_SETUP (Bitfield-Mask: 0xff) */ - -/* ----------------------- I2C2_I2C2_ACK_GENERAL_CALL_REG ----------------------- */ -#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< I2C2 I2C2_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bit 0) */ -#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< I2C2 I2C2_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_ENABLE_STATUS_REG ------------------------ */ -#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< I2C2 I2C2_ENABLE_STATUS_REG: IC_EN (Bit 0) */ -#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< I2C2 I2C2_ENABLE_STATUS_REG: IC_EN (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bit 1) */ -#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */ -#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bit 2) */ -#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< I2C2 I2C2_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */ - -/* ------------------------- I2C2_I2C2_IC_FS_SPKLEN_REG ------------------------- */ -#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos (0UL) /*!< I2C2 I2C2_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bit 0) */ -#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk (0xffUL) /*!< I2C2 I2C2_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bitfield-Mask: 0xff) */ - -/* -------------------------- I2C2_I2C2_COMP_PARAM1_REG ------------------------- */ -#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos (0UL) /*!< I2C2 I2C2_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bit 0) */ -#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk (0xffffUL) /*!< I2C2 I2C2_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bitfield-Mask: 0xffff) */ - -/* -------------------------- I2C2_I2C2_COMP_PARAM2_REG ------------------------- */ -#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos (0UL) /*!< I2C2 I2C2_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bit 0) */ -#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk (0xffffUL) /*!< I2C2 I2C2_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bitfield-Mask: 0xffff) */ - -/* ------------------------- I2C2_I2C2_COMP_VERSION_REG ------------------------- */ -#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Pos (0UL) /*!< I2C2 I2C2_COMP_VERSION_REG: IC_COMP_VERSION (Bit 0) */ -#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Msk (0xffffUL) /*!< I2C2 I2C2_COMP_VERSION_REG: IC_COMP_VERSION (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C2_I2C2_COMP2_VERSION -------------------------- */ -#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Pos (0UL) /*!< I2C2 I2C2_COMP2_VERSION: IC_COMP2_VERSION (Bit 0) */ -#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Msk (0xffffUL) /*!< I2C2 I2C2_COMP2_VERSION: IC_COMP2_VERSION (Bitfield-Mask: 0xffff) */ - -/* --------------------------- I2C2_I2C2_COMP_TYPE_REG -------------------------- */ -#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Pos (0UL) /*!< I2C2 I2C2_COMP_TYPE_REG: IC_COMP_TYPE (Bit 0) */ -#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Msk (0xffffUL) /*!< I2C2 I2C2_COMP_TYPE_REG: IC_COMP_TYPE (Bitfield-Mask: 0xffff) */ - -/* -------------------------- I2C2_I2C2_COMP_TYPE2_REG -------------------------- */ -#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos (0UL) /*!< I2C2 I2C2_COMP_TYPE2_REG: IC_COMP2_TYPE (Bit 0) */ -#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk (0xffffUL) /*!< I2C2 I2C2_COMP_TYPE2_REG: IC_COMP2_TYPE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'IR' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- IR_IR_FREQ_CARRIER_ON_REG ------------------------- */ -#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Pos (0UL) /*!< IR IR_FREQ_CARRIER_ON_REG: IR_FREQ_CARRIER_ON (Bit 0) */ -#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Msk (0x3ffUL) /*!< IR IR_FREQ_CARRIER_ON_REG: IR_FREQ_CARRIER_ON (Bitfield-Mask: 0x3ff) */ - -/* ------------------------- IR_IR_FREQ_CARRIER_OFF_REG ------------------------- */ -#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Pos (0UL) /*!< IR IR_FREQ_CARRIER_OFF_REG: IR_FREQ_CARRIER_OFF (Bit 0) */ -#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Msk (0x3ffUL) /*!< IR IR_FREQ_CARRIER_OFF_REG: IR_FREQ_CARRIER_OFF (Bitfield-Mask: 0x3ff) */ - -/* -------------------------- IR_IR_LOGIC_ONE_TIME_REG -------------------------- */ -#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Pos (0UL) /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_SPACE (Bit 0) */ -#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Msk (0xffUL) /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_SPACE (Bitfield-Mask: 0xff) */ -#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Pos (8UL) /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_MARK (Bit 8) */ -#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Msk (0xff00UL) /*!< IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_MARK (Bitfield-Mask: 0xff) */ - -/* -------------------------- IR_IR_LOGIC_ZERO_TIME_REG ------------------------- */ -#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Pos (0UL) /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_SPACE (Bit 0) */ -#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Msk (0xffUL) /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_SPACE (Bitfield-Mask: 0xff) */ -#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Pos (8UL) /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_MARK (Bit 8) */ -#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Msk (0xff00UL) /*!< IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_MARK (Bitfield-Mask: 0xff) */ - -/* ------------------------------- IR_IR_CTRL_REG ------------------------------- */ -#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Pos (0UL) /*!< IR IR_CTRL_REG: IR_CODE_FIFO_RESET (Bit 0) */ -#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Msk (0x1UL) /*!< IR IR_CTRL_REG: IR_CODE_FIFO_RESET (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Pos (1UL) /*!< IR IR_CTRL_REG: IR_REP_FIFO_RESET (Bit 1) */ -#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Msk (0x2UL) /*!< IR IR_CTRL_REG: IR_REP_FIFO_RESET (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_ENABLE_Pos (2UL) /*!< IR IR_CTRL_REG: IR_ENABLE (Bit 2) */ -#define IR_IR_CTRL_REG_IR_ENABLE_Msk (0x4UL) /*!< IR IR_CTRL_REG: IR_ENABLE (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_TX_START_Pos (3UL) /*!< IR IR_CTRL_REG: IR_TX_START (Bit 3) */ -#define IR_IR_CTRL_REG_IR_TX_START_Msk (0x8UL) /*!< IR IR_CTRL_REG: IR_TX_START (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Pos (4UL) /*!< IR IR_CTRL_REG: IR_REPEAT_TYPE (Bit 4) */ -#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Msk (0x10UL) /*!< IR IR_CTRL_REG: IR_REPEAT_TYPE (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Pos (5UL) /*!< IR IR_CTRL_REG: IR_INVERT_OUTPUT (Bit 5) */ -#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Msk (0x20UL) /*!< IR IR_CTRL_REG: IR_INVERT_OUTPUT (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Pos (6UL) /*!< IR IR_CTRL_REG: IR_LOGIC_ZERO_FORMAT (Bit 6) */ -#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Msk (0x40UL) /*!< IR IR_CTRL_REG: IR_LOGIC_ZERO_FORMAT (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Pos (7UL) /*!< IR IR_CTRL_REG: IR_LOGIC_ONE_FORMAT (Bit 7) */ -#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Msk (0x80UL) /*!< IR IR_CTRL_REG: IR_LOGIC_ONE_FORMAT (Bitfield-Mask: 0x01) */ -#define IR_IR_CTRL_REG_IR_IRQ_EN_Pos (8UL) /*!< IR IR_CTRL_REG: IR_IRQ_EN (Bit 8) */ -#define IR_IR_CTRL_REG_IR_IRQ_EN_Msk (0x100UL) /*!< IR IR_CTRL_REG: IR_IRQ_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ IR_IR_STATUS_REG ------------------------------ */ -#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Pos (0UL) /*!< IR IR_STATUS_REG: IR_CODE_FIFO_WRDS (Bit 0) */ -#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Msk (0x3fUL) /*!< IR IR_STATUS_REG: IR_CODE_FIFO_WRDS (Bitfield-Mask: 0x3f) */ -#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Pos (6UL) /*!< IR IR_STATUS_REG: IR_REP_FIFO_WRDS (Bit 6) */ -#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Msk (0x3c0UL) /*!< IR IR_STATUS_REG: IR_REP_FIFO_WRDS (Bitfield-Mask: 0x0f) */ -#define IR_IR_STATUS_REG_IR_BUSY_Pos (10UL) /*!< IR IR_STATUS_REG: IR_BUSY (Bit 10) */ -#define IR_IR_STATUS_REG_IR_BUSY_Msk (0x400UL) /*!< IR IR_STATUS_REG: IR_BUSY (Bitfield-Mask: 0x01) */ - -/* ---------------------------- IR_IR_REPEAT_TIME_REG --------------------------- */ -#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Pos (0UL) /*!< IR IR_REPEAT_TIME_REG: IR_REPEAT_TIME (Bit 0) */ -#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Msk (0xffffUL) /*!< IR IR_REPEAT_TIME_REG: IR_REPEAT_TIME (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- IR_IR_MAIN_FIFO_REG ---------------------------- */ -#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Pos (0UL) /*!< IR IR_MAIN_FIFO_REG: IR_CODE_FIFO_DATA (Bit 0) */ -#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Msk (0xffffUL) /*!< IR IR_MAIN_FIFO_REG: IR_CODE_FIFO_DATA (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- IR_IR_REPEAT_FIFO_REG --------------------------- */ -#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Pos (0UL) /*!< IR IR_REPEAT_FIFO_REG: IR_REPEAT_FIFO_DATA (Bit 0) */ -#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Msk (0xffffUL) /*!< IR IR_REPEAT_FIFO_REG: IR_REPEAT_FIFO_DATA (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- IR_IR_IRQ_STATUS_REG ---------------------------- */ -#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Pos (0UL) /*!< IR IR_IRQ_STATUS_REG: IR_IRQ_ACK (Bit 0) */ -#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Msk (0x1UL) /*!< IR IR_IRQ_STATUS_REG: IR_IRQ_ACK (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'KBSCAN' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- KBSCAN_KBSCN_CTRL_REG --------------------------- */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Pos (0UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_EN (Bit 0) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Msk (0x1UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_EN (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Pos (1UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_MESSAGE_MASK (Bit 1) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Msk (0x2UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_MESSAGE_MASK (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Pos (2UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_INACTIVE_MASK (Bit 2) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Msk (0x4UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_INACTIVE_MASK (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Pos (3UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_FIFO_MASK (Bit 3) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Msk (0x8UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_FIFO_MASK (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Pos (4UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_TIME (Bit 4) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Msk (0x7f0UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_TIME (Bitfield-Mask: 0x7f) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Pos (11UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_EN (Bit 11) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Msk (0x800UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_EN (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Pos (12UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_CLKDIV (Bit 12) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Msk (0x3000UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_CLKDIV (Bitfield-Mask: 0x03) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Pos (14UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_RESET_FIFO (Bit 14) */ -#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Msk (0x4000UL) /*!< KBSCAN KBSCN_CTRL_REG: KBSCN_RESET_FIFO (Bitfield-Mask: 0x01) */ - -/* --------------------------- KBSCAN_KBSCN_CTRL2_REG --------------------------- */ -#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Pos (0UL) /*!< KBSCAN KBSCN_CTRL2_REG: KBSCN_ROW_ACTIVE_TIME (Bit 0) */ -#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Msk (0xffffUL) /*!< KBSCAN KBSCN_CTRL2_REG: KBSCN_ROW_ACTIVE_TIME (Bitfield-Mask: 0xffff) */ - -/* ------------------------ KBSCAN_KBSCN_MATRIX_SIZE_REG ------------------------ */ -#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Pos (0UL) /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_ROW (Bit 0) */ -#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Msk (0xfUL) /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_ROW (Bitfield-Mask: 0x0f) */ -#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Pos (4UL) /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_COLUMN (Bit 4) */ -#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Msk (0x1f0UL) /*!< KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_COLUMN (Bitfield-Mask: 0x1f) */ - -/* -------------------------- KBSCAN_KBSCN_DEBOUNCE_REG ------------------------- */ -#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Pos (0UL) /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_RELEASE_TIME (Bit 0) */ -#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Msk (0x3fUL) /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_RELEASE_TIME (Bitfield-Mask: 0x3f) */ -#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Pos (6UL) /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_PRESS_TIME (Bit 6) */ -#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Msk (0xfc0UL) /*!< KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_PRESS_TIME (Bitfield-Mask: 0x3f) */ - -/* --------------------------- KBSCAN_KBSCN_STATUS_REG -------------------------- */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Pos (0UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_MES_IRQ_STATUS (Bit 0) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Msk (0x1UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_MES_IRQ_STATUS (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Pos (1UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_INACTIVE_IRQ_STATUS (Bit 1) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Msk (0x2UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_INACTIVE_IRQ_STATUS (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Pos (2UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_NUM_MESSAGE (Bit 2) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Msk (0x7cUL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_NUM_MESSAGE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Pos (7UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_OVERFL (Bit 7) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Msk (0x80UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_OVERFL (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Pos (8UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_UNDERFL (Bit 8) */ -#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Msk (0x100UL) /*!< KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_UNDERFL (Bitfield-Mask: 0x01) */ - -/* ------------------------ KBSCAN_KBSCN_MESSAGE_KEY_REG ------------------------ */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Pos (0UL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_ROW (Bit 0) */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Msk (0xfUL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_ROW (Bitfield-Mask: 0x0f) */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Pos (4UL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_COLUMN (Bit 4) */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Msk (0x1f0UL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_COLUMN (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Pos (9UL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEY_STATE (Bit 9) */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Msk (0x200UL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEY_STATE (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Pos (10UL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_LAST_ENTRY (Bit 10) */ -#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Msk (0x400UL) /*!< KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_LAST_ENTRY (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P00_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P00_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P01_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P01_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P02_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P02_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P03_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P03_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P04_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P04_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P05_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P05_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P06_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P06_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P07_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P07_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P10_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P10_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P11_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P11_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P12_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P12_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P13_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P13_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P14_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P14_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P15_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P15_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P16_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P16_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P17_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P17_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P20_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P20_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P21_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P21_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P22_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P22_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P23_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P23_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P24_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P24_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P30_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P30_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P31_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P31_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P32_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P32_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P33_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P33_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P34_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P34_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P35_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P35_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P36_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P36_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P37_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P37_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P40_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P40_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P41_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P41_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P42_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P42_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P43_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P43_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P44_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P44_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P45_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P45_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P46_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P46_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- KBSCAN_KBSCN_P47_MODE_REG ------------------------- */ -#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Pos (0UL) /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_MODE (Bit 0) */ -#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Msk (0x1fUL) /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f) */ -#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Pos (5UL) /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_ROW (Bit 5) */ -#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Msk (0x20UL) /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01) */ -#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Pos (6UL) /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_GPIO_EN (Bit 6) */ -#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Msk (0x40UL) /*!< KBSCAN KBSCN_P47_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'OTPC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- OTPC_OTPC_MODE_REG ----------------------------- */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos (0UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_MODE (Bit 0) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk (0x7UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_MODE (Bitfield-Mask: 0x07) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Pos (4UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_DMA (Bit 4) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Msk (0x10UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_DMA (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Pos (5UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_FIFO_FLUSH (Bit 5) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Msk (0x20UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_FIFO_FLUSH (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Pos (6UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_ERR_RESP_DIS (Bit 6) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Msk (0x40UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_ERR_RESP_DIS (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Pos (8UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_SP_ROWS (Bit 8) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Msk (0x100UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_USE_SP_ROWS (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Pos (9UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_RLD_RR_REQ (Bit 9) */ -#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Msk (0x200UL) /*!< OTPC OTPC_MODE_REG: OTPC_MODE_RLD_RR_REQ (Bitfield-Mask: 0x01) */ - -/* ----------------------------- OTPC_OTPC_PCTRL_REG ---------------------------- */ -#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Pos (0UL) /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_WADDR (Bit 0) */ -#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Msk (0x1fffUL) /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_WADDR (Bitfield-Mask: 0x1fff) */ -#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Pos (14UL) /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PRETRY (Bit 14) */ -#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Msk (0x4000UL) /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PRETRY (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Pos (15UL) /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PSTART (Bit 15) */ -#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Msk (0x8000UL) /*!< OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PSTART (Bitfield-Mask: 0x01) */ - -/* ----------------------------- OTPC_OTPC_STAT_REG ----------------------------- */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos (0UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PRDY (Bit 0) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk (0x1UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PRDY (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Pos (1UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_UNC (Bit 1) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Msk (0x2UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_UNC (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Pos (2UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_COR (Bit 2) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Msk (0x4UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PERR_COR (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Pos (3UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PZERO (Bit 3) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Msk (0x8UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_PZERO (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Pos (4UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TRDY (Bit 4) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Msk (0x10UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TRDY (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Pos (5UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TERROR (Bit 5) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Msk (0x20UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_TERROR (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Pos (6UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_ARDY (Bit 6) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Msk (0x40UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_ARDY (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Pos (7UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_RERROR (Bit 7) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Msk (0x80UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_RERROR (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Pos (8UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_FWORDS (Bit 8) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Msk (0xf00UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_FWORDS (Bitfield-Mask: 0x0f) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Pos (16UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_NWORDS (Bit 16) */ -#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Msk (0x3fff0000UL) /*!< OTPC OTPC_STAT_REG: OTPC_STAT_NWORDS (Bitfield-Mask: 0x3fff) */ - -/* ---------------------------- OTPC_OTPC_AHBADR_REG ---------------------------- */ -#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Pos (2UL) /*!< OTPC OTPC_AHBADR_REG: OTPC_AHBADR (Bit 2) */ -#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Msk (0xfffffffcUL) /*!< OTPC OTPC_AHBADR_REG: OTPC_AHBADR (Bitfield-Mask: 0x3fffffff) */ - -/* ---------------------------- OTPC_OTPC_CELADR_REG ---------------------------- */ -#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Pos (0UL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR (Bit 0) */ -#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Msk (0x3fffUL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR (Bitfield-Mask: 0x3fff) */ -#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Pos (16UL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bit 16) */ -#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Msk (0x3fff0000UL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bitfield-Mask: 0x3fff) */ - -/* ---------------------------- OTPC_OTPC_NWORDS_REG ---------------------------- */ -#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Pos (0UL) /*!< OTPC OTPC_NWORDS_REG: OTPC_NWORDS (Bit 0) */ -#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Msk (0x3fffUL) /*!< OTPC OTPC_NWORDS_REG: OTPC_NWORDS (Bitfield-Mask: 0x3fff) */ - -/* ----------------------------- OTPC_OTPC_FFPRT_REG ---------------------------- */ -#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Pos (0UL) /*!< OTPC OTPC_FFPRT_REG: OTPC_FFPRT (Bit 0) */ -#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Msk (0xffffffffUL) /*!< OTPC OTPC_FFPRT_REG: OTPC_FFPRT (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- OTPC_OTPC_FFRD_REG ----------------------------- */ -#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Pos (0UL) /*!< OTPC OTPC_FFRD_REG: OTPC_FFRD (Bit 0) */ -#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Msk (0xffffffffUL) /*!< OTPC OTPC_FFRD_REG: OTPC_FFRD (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- OTPC_OTPC_PWORDL_REG ---------------------------- */ -#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Pos (0UL) /*!< OTPC OTPC_PWORDL_REG: OTPC_PWORDL (Bit 0) */ -#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Msk (0xffffffffUL) /*!< OTPC OTPC_PWORDL_REG: OTPC_PWORDL (Bitfield-Mask: 0xffffffff) */ - -/* ---------------------------- OTPC_OTPC_PWORDH_REG ---------------------------- */ -#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Pos (0UL) /*!< OTPC OTPC_PWORDH_REG: OTPC_PWORDH (Bit 0) */ -#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Msk (0xffffffffUL) /*!< OTPC OTPC_PWORDH_REG: OTPC_PWORDH (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- OTPC_OTPC_TIM1_REG ----------------------------- */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos (0UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_CADX (Bit 0) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Msk (0xffUL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_CADX (Bitfield-Mask: 0xff) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos (8UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_PW (Bit 8) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Msk (0xff00UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_PW (Bitfield-Mask: 0xff) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos (16UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_1US (Bit 16) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk (0x3f0000UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_1US (Bitfield-Mask: 0x3f) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos (22UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_500NS (Bit 22) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Msk (0x7c00000UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_500NS (Bitfield-Mask: 0x1f) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos (27UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_200NS (Bit 27) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Msk (0x78000000UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_200NS (Bitfield-Mask: 0x0f) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos (31UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_25NS (Bit 31) */ -#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Msk (0x80000000UL) /*!< OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_25NS (Bitfield-Mask: 0x01) */ - -/* ----------------------------- OTPC_OTPC_TIM2_REG ----------------------------- */ -#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Pos (0UL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_STBY_THR (Bit 0) */ -#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Msk (0x3ffUL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_STBY_THR (Bitfield-Mask: 0x3ff) */ -#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Pos (16UL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_T_BCHK (Bit 16) */ -#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Msk (0x7f0000UL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_T_BCHK (Bitfield-Mask: 0x7f) */ -#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Pos (23UL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bit 23) */ -#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Msk (0x800000UL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bitfield-Mask: 0x01) */ - -/* ----------------------------- OTPC_OTPC_TEST_REG ----------------------------- */ -#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Pos (0UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bit 0) */ -#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Msk (0x1UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bitfield-Mask: 0x01) */ -#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Pos (16UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bit 16) */ -#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Msk (0xff0000UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bitfield-Mask: 0xff) */ -#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Pos (24UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bit 24) */ -#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Msk (0x3000000UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bitfield-Mask: 0x03) */ -#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Pos (26UL) /*!< OTPC OTPC_TEST_REG: OTPC_USED_RR (Bit 26) */ -#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Msk (0x4000000UL) /*!< OTPC OTPC_TEST_REG: OTPC_USED_RR (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'PATCH' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- PATCH_PATCH_VALID_REG --------------------------- */ -#define PATCH_PATCH_VALID_REG_PATCH_VALID_Pos (0UL) /*!< PATCH PATCH_VALID_REG: PATCH_VALID (Bit 0) */ -#define PATCH_PATCH_VALID_REG_PATCH_VALID_Msk (0xfffffffUL) /*!< PATCH PATCH_VALID_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff) */ - -/* -------------------------- PATCH_PATCH_VALID_SET_REG ------------------------- */ -#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Pos (0UL) /*!< PATCH PATCH_VALID_SET_REG: PATCH_VALID (Bit 0) */ -#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Msk (0xfffffffUL) /*!< PATCH PATCH_VALID_SET_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff) */ - -/* ------------------------- PATCH_PATCH_VALID_RESET_REG ------------------------ */ -#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Pos (0UL) /*!< PATCH PATCH_VALID_RESET_REG: PATCH_VALID (Bit 0) */ -#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Msk (0xfffffffUL) /*!< PATCH PATCH_VALID_RESET_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff) */ - -/* ---------------------------- PATCH_PATCH_ADDR0_REG --------------------------- */ -#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR0_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR1_REG --------------------------- */ -#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR1_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR2_REG --------------------------- */ -#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR2_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR3_REG --------------------------- */ -#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR3_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR4_REG --------------------------- */ -#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR4_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR5_REG --------------------------- */ -#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR5_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR6_REG --------------------------- */ -#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR6_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR7_REG --------------------------- */ -#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR7_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR8_REG --------------------------- */ -#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR8_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PATCH_PATCH_ADDR9_REG --------------------------- */ -#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR9_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR10_REG --------------------------- */ -#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR10_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR11_REG --------------------------- */ -#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR11_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR12_REG --------------------------- */ -#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR12_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR13_REG --------------------------- */ -#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR13_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR14_REG --------------------------- */ -#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR14_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR15_REG --------------------------- */ -#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR15_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR16_REG --------------------------- */ -#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR16_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR17_REG --------------------------- */ -#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR17_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR18_REG --------------------------- */ -#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR18_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR19_REG --------------------------- */ -#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Pos (1UL) /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_C (Bit 1) */ -#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Msk (0x1fffeUL) /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff) */ -#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR19_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_ADDR20_REG --------------------------- */ -#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR20_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA20_REG --------------------------- */ -#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA20_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA20_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- PATCH_PATCH_ADDR21_REG --------------------------- */ -#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR21_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA21_REG --------------------------- */ -#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA21_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA21_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- PATCH_PATCH_ADDR22_REG --------------------------- */ -#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR22_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA22_REG --------------------------- */ -#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA22_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA22_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- PATCH_PATCH_ADDR23_REG --------------------------- */ -#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR23_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA23_REG --------------------------- */ -#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA23_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA23_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- PATCH_PATCH_ADDR24_REG --------------------------- */ -#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR24_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA24_REG --------------------------- */ -#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA24_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA24_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- PATCH_PATCH_ADDR25_REG --------------------------- */ -#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR25_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA25_REG --------------------------- */ -#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA25_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA25_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- PATCH_PATCH_ADDR26_REG --------------------------- */ -#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR26_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA26_REG --------------------------- */ -#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA26_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA26_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - -/* --------------------------- PATCH_PATCH_ADDR27_REG --------------------------- */ -#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Pos (2UL) /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_D (Bit 2) */ -#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Msk (0x1fffcUL) /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff) */ -#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Pos (19UL) /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_19 (Bit 19) */ -#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Msk (0x80000UL) /*!< PATCH PATCH_ADDR27_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01) */ - -/* --------------------------- PATCH_PATCH_DATA27_REG --------------------------- */ -#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Pos (0UL) /*!< PATCH PATCH_DATA27_REG: PATCH_DATA (Bit 0) */ -#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Msk (0xffffffffUL) /*!< PATCH PATCH_DATA27_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff) */ - - -/* ================================================================================ */ -/* ================ struct 'PLLDIG' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------ PLLDIG_RF_SYNTH_CTRL1_BLE_REG ----------------------- */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Pos (0UL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CHANNEL_ZERO (Bit 0) */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Msk (0xfffUL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CHANNEL_ZERO (Bitfield-Mask: 0xfff) */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Pos (12UL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: SGN (Bit 12) */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Msk (0x1000UL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: SGN (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Pos (13UL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CS (Bit 13) */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Msk (0x2000UL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: CS (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Pos (14UL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: PLL_HSI_POL (Bit 14) */ -#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Msk (0x4000UL) /*!< PLLDIG RF_SYNTH_CTRL1_BLE_REG: PLL_HSI_POL (Bitfield-Mask: 0x01) */ - -/* ----------------------- PLLDIG_RF_SYNTH_CTRL1_FTDF_REG ----------------------- */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Pos (0UL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CHANNEL_ZERO (Bit 0) */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Msk (0xfffUL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CHANNEL_ZERO (Bitfield-Mask: 0xfff) */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Pos (12UL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: SGN (Bit 12) */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Msk (0x1000UL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: SGN (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Pos (13UL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CS (Bit 13) */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Msk (0x2000UL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CS (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Pos (14UL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: PLL_HSI_POL (Bit 14) */ -#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Msk (0x4000UL) /*!< PLLDIG RF_SYNTH_CTRL1_FTDF_REG: PLL_HSI_POL (Bitfield-Mask: 0x01) */ - -/* ------------------------ PLLDIG_RF_SYNTH_CTRL2_BLE_REG ----------------------- */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Pos (0UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_RX (Bit 0) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Msk (0x3UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_RX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Pos (2UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_TX (Bit 2) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Msk (0xcUL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_TX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Pos (4UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bit 4) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Msk (0x30UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Pos (6UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bit 6) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Msk (0xc0UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Pos (8UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bit 8) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Msk (0x100UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Pos (9UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_86 (Bit 9) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Msk (0x200UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_86 (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Pos (10UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: TXDATA_INV (Bit 10) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Msk (0x400UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: TXDATA_INV (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Pos (11UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: EO_PACKET_DIS (Bit 11) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Msk (0x800UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: EO_PACKET_DIS (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Pos (12UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bit 12) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Msk (0x1000UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Pos (13UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bit 13) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Msk (0x2000UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bitfield-Mask: 0x01) */ - -/* ----------------------- PLLDIG_RF_SYNTH_CTRL2_FTDF_REG ----------------------- */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Pos (0UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bit 0) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Msk (0x3UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Pos (2UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bit 2) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Msk (0xcUL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Pos (4UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bit 4) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Msk (0x30UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Pos (6UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bit 6) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Msk (0x40UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Pos (8UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bit 8) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Msk (0x100UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Pos (10UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bit 10) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Msk (0x400UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bitfield-Mask: 0x01) */ - -/* -------------------------- PLLDIG_RF_SYNTH_CTRL3_REG ------------------------- */ -#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Pos (0UL) /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_WR (Bit 0) */ -#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Msk (0x3fffUL) /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_WR (Bitfield-Mask: 0x3fff) */ -#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Pos (14UL) /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_SEL (Bit 14) */ -#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Msk (0x4000UL) /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Pos (15UL) /*!< PLLDIG RF_SYNTH_CTRL3_REG: ZIF_MODE_EN (Bit 15) */ -#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Msk (0x8000UL) /*!< PLLDIG RF_SYNTH_CTRL3_REG: ZIF_MODE_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- PLLDIG_RF_VCOCAL_CTRL_REG ------------------------- */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Pos (0UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_WR (Bit 0) */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Msk (0xfUL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_WR (Bitfield-Mask: 0x0f) */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Pos (4UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_SEL (Bit 4) */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Msk (0x30UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_SEL (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Pos (6UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bit 6) */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Msk (0xc0UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Pos (8UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bit 8) */ -#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Msk (0x100UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bitfield-Mask: 0x01) */ - -/* ------------------------ PLLDIG_RF_MGAIN_CTRL_BLE_REG ------------------------ */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_WR (Bit 0) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Msk (0xffUL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_WR (Bitfield-Mask: 0xff) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Pos (8UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_SEL (Bit 8) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Msk (0x100UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Pos (9UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: BLE_TESTPAT_GEN (Bit 9) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Msk (0x200UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: BLE_TESTPAT_GEN (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Pos (10UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_CMP_INV (Bit 10) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Msk (0x400UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_CMP_INV (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Pos (11UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_AVER (Bit 11) */ -#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Msk (0x1800UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_AVER (Bitfield-Mask: 0x03) */ - -/* ------------------------ PLLDIG_RF_MGAIN_CTRL_FTDF_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bit 0) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Msk (0x7fUL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bitfield-Mask: 0x7f) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Pos (7UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bit 7) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Msk (0x80UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Pos (8UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bit 8) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Msk (0xff00UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bitfield-Mask: 0xff) */ - -/* -------------------------- PLLDIG_RF_MGAIN_CTRL2_REG ------------------------- */ -#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bit 0) */ -#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Msk (0x7fUL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bitfield-Mask: 0x7f) */ -#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Pos (7UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bit 7) */ -#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Msk (0x80UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Pos (8UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bit 8) */ -#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Msk (0x100UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bitfield-Mask: 0x01) */ - -/* ----------------------- PLLDIG_RF_VCO_CALCAP_BIT14_REG ----------------------- */ -#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Pos (0UL) /*!< PLLDIG RF_VCO_CALCAP_BIT14_REG: VCO_CALCAP_BIT14 (Bit 0) */ -#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Msk (0xffffUL) /*!< PLLDIG RF_VCO_CALCAP_BIT14_REG: VCO_CALCAP_BIT14 (Bitfield-Mask: 0xffff) */ - -/* ----------------------- PLLDIG_RF_VCO_CALCAP_BIT15_REG ----------------------- */ -#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Pos (0UL) /*!< PLLDIG RF_VCO_CALCAP_BIT15_REG: VCO_CALCAP_BIT15 (Bit 0) */ -#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Msk (0xffffUL) /*!< PLLDIG RF_VCO_CALCAP_BIT15_REG: VCO_CALCAP_BIT15 (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- PLLDIG_RF_BMCW_REG ----------------------------- */ -#define PLLDIG_RF_BMCW_REG_CN_WR_Pos (0UL) /*!< PLLDIG RF_BMCW_REG: CN_WR (Bit 0) */ -#define PLLDIG_RF_BMCW_REG_CN_WR_Msk (0x3fUL) /*!< PLLDIG RF_BMCW_REG: CN_WR (Bitfield-Mask: 0x3f) */ -#define PLLDIG_RF_BMCW_REG_HSI_WR_Pos (6UL) /*!< PLLDIG RF_BMCW_REG: HSI_WR (Bit 6) */ -#define PLLDIG_RF_BMCW_REG_HSI_WR_Msk (0x40UL) /*!< PLLDIG RF_BMCW_REG: HSI_WR (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_BMCW_REG_CN_SEL_Pos (7UL) /*!< PLLDIG RF_BMCW_REG: CN_SEL (Bit 7) */ -#define PLLDIG_RF_BMCW_REG_CN_SEL_Msk (0x80UL) /*!< PLLDIG RF_BMCW_REG: CN_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_BMCW_REG_HSI_SEL_Pos (8UL) /*!< PLLDIG RF_BMCW_REG: HSI_SEL (Bit 8) */ -#define PLLDIG_RF_BMCW_REG_HSI_SEL_Msk (0x100UL) /*!< PLLDIG RF_BMCW_REG: HSI_SEL (Bitfield-Mask: 0x01) */ - -/* ------------------------ PLLDIG_RF_KMOD_ALPHA_BLE_REG ------------------------ */ -#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Pos (0UL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bit 0) */ -#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Msk (0x3fUL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bitfield-Mask: 0x3f) */ -#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Pos (6UL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bit 6) */ -#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Msk (0xfc0UL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bitfield-Mask: 0x3f) */ - -/* ------------------------ PLLDIG_RF_KMOD_ALPHA_FTDF_REG ----------------------- */ -#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Pos (0UL) /*!< PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bit 0) */ -#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Msk (0x3fUL) /*!< PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bitfield-Mask: 0x3f) */ - -/* ----------------------- PLLDIG_RF_SYNTH_RESULT_BLE_REG ----------------------- */ -#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: GAUSS_GAIN_CAL_RD (Bit 0) */ -#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Msk (0xffUL) /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: GAUSS_GAIN_CAL_RD (Bitfield-Mask: 0xff) */ -#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Pos (8UL) /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: VCO_FREQTRIM_RD (Bit 8) */ -#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Msk (0xf00UL) /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: VCO_FREQTRIM_RD (Bitfield-Mask: 0x0f) */ - -/* ----------------------- PLLDIG_RF_SYNTH_RESULT_FTDF_REG ---------------------- */ -#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bit 0) */ -#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Msk (0x7fUL) /*!< PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bitfield-Mask: 0x7f) */ - -/* ----------------------- PLLDIG_RF_SYNTH_RESULT2_BLE_REG ---------------------- */ -#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: GAUSS_GAIN_RD (Bit 0) */ -#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Msk (0xffUL) /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: GAUSS_GAIN_RD (Bitfield-Mask: 0xff) */ -#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Pos (8UL) /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: CN_CAL_RD (Bit 8) */ -#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Msk (0x3f00UL) /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: CN_CAL_RD (Bitfield-Mask: 0x3f) */ - -/* ---------------------- PLLDIG_RF_SYNTH_RESULT2_FTDF_REG ---------------------- */ -#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bit 0) */ -#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Msk (0xffUL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bitfield-Mask: 0xff) */ - -/* ---------------------- PLLDIG_RF_SYNTH_RESULT3_FTDF_REG ---------------------- */ -#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT3_FTDF_REG: CN_CAL_FTDF_RD (Bit 0) */ -#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Msk (0x3fUL) /*!< PLLDIG RF_SYNTH_RESULT3_FTDF_REG: CN_CAL_FTDF_RD (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- PLLDIG_RF_CALCAP1_REG --------------------------- */ -#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Pos (0UL) /*!< PLLDIG RF_CALCAP1_REG: VCO_CALCAP_LOW (Bit 0) */ -#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Msk (0xffffUL) /*!< PLLDIG RF_CALCAP1_REG: VCO_CALCAP_LOW (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- PLLDIG_RF_CALCAP2_REG --------------------------- */ -#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Pos (0UL) /*!< PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bit 0) */ -#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Msk (0x3UL) /*!< PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bitfield-Mask: 0x03) */ - -/* -------------------------- PLLDIG_RF_NMD_OFFSET_REG -------------------------- */ -#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Pos (0UL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bit 0) */ -#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Msk (0xffUL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bitfield-Mask: 0xff) */ -#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Pos (8UL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bit 8) */ -#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Msk (0xff00UL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bitfield-Mask: 0xff) */ - -/* ------------------------- PLLDIG_RF_FTDF_PHYATTR_REG ------------------------- */ -#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Pos (0UL) /*!< PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bit 0) */ -#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Msk (0xffffUL) /*!< PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bitfield-Mask: 0xffff) */ - -/* ------------------------- PLLDIG_RF_CALTRIM_STEP1_REG ------------------------ */ -#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Pos (0UL) /*!< PLLDIG RF_CALTRIM_STEP1_REG: MDSTATE_RD (Bit 0) */ -#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Msk (0xffffUL) /*!< PLLDIG RF_CALTRIM_STEP1_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */ - -/* ------------------------- PLLDIG_RF_CALTRIM_STEP2_REG ------------------------ */ -#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Pos (0UL) /*!< PLLDIG RF_CALTRIM_STEP2_REG: MDSTATE_RD (Bit 0) */ -#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Msk (0xffffUL) /*!< PLLDIG RF_CALTRIM_STEP2_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */ - -/* ------------------------- PLLDIG_RF_CALTRIM_STEP3_REG ------------------------ */ -#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Pos (0UL) /*!< PLLDIG RF_CALTRIM_STEP3_REG: MDSTATE_RD (Bit 0) */ -#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Msk (0xffffUL) /*!< PLLDIG RF_CALTRIM_STEP3_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */ - -/* ------------------------- PLLDIG_RF_CALTRIM_STEP4_REG ------------------------ */ -#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Pos (0UL) /*!< PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bit 0) */ -#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Msk (0xffffUL) /*!< PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */ - -/* -------------------------- PLLDIG_RF_MGAIN_CTRL3_REG ------------------------- */ -#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bit 0) */ -#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Msk (0xffUL) /*!< PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bitfield-Mask: 0xff) */ - -/* ------------------------- PLLDIG_RF_VCO_FREQ_EST_REG ------------------------- */ -#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Pos (0UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bit 0) */ -#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Msk (0x1UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Pos (1UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bit 1) */ -#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Msk (0xfeUL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bitfield-Mask: 0x7f) */ -#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Pos (8UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bit 8) */ -#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Msk (0x700UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bitfield-Mask: 0x07) */ - -/* -------------------------- PLLDIG_RF_SYNTH_SPARE_REG ------------------------- */ -#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Pos (0UL) /*!< PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bit 0) */ -#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Msk (0xffUL) /*!< PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bitfield-Mask: 0xff) */ - -/* ------------------------- PLLDIG_RF_MSKMOD_CTRL1_REG ------------------------- */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bit 0) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Msk (0xfUL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bitfield-Mask: 0x0f) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Pos (4UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bit 4) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Msk (0x10UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Pos (5UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bit 5) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Msk (0x20UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Pos (6UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bit 6) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Msk (0x40UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Pos (7UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bit 7) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Msk (0x80UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Pos (8UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bit 8) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Msk (0x100UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bitfield-Mask: 0x01) */ - -/* ------------------------- PLLDIG_RF_MSKMOD_CHIPL_REG ------------------------- */ -#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CHIPL_REG: MSK_CHIPL (Bit 0) */ -#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Msk (0xffffUL) /*!< PLLDIG RF_MSKMOD_CHIPL_REG: MSK_CHIPL (Bitfield-Mask: 0xffff) */ - -/* ------------------------- PLLDIG_RF_MSKMOD_CHIPH_REG ------------------------- */ -#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bit 0) */ -#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Msk (0xffffUL) /*!< PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bitfield-Mask: 0xffff) */ - -/* -------------------------- PLLDIG_RF_TXDAC_TEST_REG -------------------------- */ -#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Pos (0UL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bit 0) */ -#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Msk (0xffUL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bitfield-Mask: 0xff) */ -#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Pos (8UL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bit 8) */ -#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Msk (0x100UL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bitfield-Mask: 0x01) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL0_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL1_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL1_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL1_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL2_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL2_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL2_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL3_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL3_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL3_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL4_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL4_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL4_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL5_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL5_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL5_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL6_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL7_REG ----------------------- */ -#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bit 0) */ -#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_0_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_1_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_2_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_3_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_4_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_5_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_6_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_TBL_7_REG ------------------------- */ -#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bit 0) */ -#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ - -/* -------------------------- PLLDIG_RF_PULSE_CTRL_REG -------------------------- */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Pos (0UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bit 0) */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Msk (0x1UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Pos (1UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bit 1) */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Msk (0x6UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Pos (3UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bit 3) */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Msk (0x8UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Pos (4UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bit 4) */ -#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Msk (0xf0UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'QSPIC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------- QSPIC_QSPIC_CTRLBUS_REG -------------------------- */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_SINGLE (Bit 0) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_DUAL (Bit 1) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_DUAL (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_QUAD (Bit 2) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_QUAD (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_EN_CS (Bit 3) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_EN_CS (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_DIS_CS (Bit 4) */ -#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL) /*!< QSPIC QSPIC_CTRLBUS_REG: QSPIC_DIS_CS (Bitfield-Mask: 0x01) */ - -/* -------------------------- QSPIC_QSPIC_CTRLMODE_REG -------------------------- */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_AUTO_MD (Bit 0) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_AUTO_MD (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_CLK_MD (Bit 1) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_CLK_MD (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_OEN (Bit 2) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_OEN (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_OEN (Bit 3) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_OEN (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_DAT (Bit 4) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_DAT (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_DAT (Bit 5) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_DAT (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_HRDY_MD (Bit 6) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_HRDY_MD (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RXD_NEG (Bit 7) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RXD_NEG (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RPIPE_EN (Bit 8) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_PCLK_MD (Bit 9) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_PCLK_MD (Bitfield-Mask: 0x07) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_FORCENSEQ_EN (Bit 12) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_USE_32BA (Bit 13) */ -#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL) /*!< QSPIC QSPIC_CTRLMODE_REG: QSPIC_USE_32BA (Bitfield-Mask: 0x01) */ - -/* -------------------------- QSPIC_QSPIC_RECVDATA_REG -------------------------- */ -#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL) /*!< QSPIC QSPIC_RECVDATA_REG: QSPIC_RECVDATA (Bit 0) */ -#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL) /*!< QSPIC QSPIC_RECVDATA_REG: QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- QSPIC_QSPIC_BURSTCMDA_REG ------------------------- */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST (Bit 0) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST (Bitfield-Mask: 0xff) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_WB (Bit 8) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_WB (Bitfield-Mask: 0xff) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_BYTE (Bit 16) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_TX_MD (Bit 24) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_ADR_TX_MD (Bit 26) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_TX_MD (Bit 28) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_DMY_TX_MD (Bit 30) */ -#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC QSPIC_BURSTCMDA_REG: QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */ - -/* -------------------------- QSPIC_QSPIC_BURSTCMDB_REG ------------------------- */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DAT_RX_MD (Bit 0) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_BYTE_EN (Bit 2) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_HF_DS (Bit 3) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_NUM (Bit 4) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_NUM (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_INST_MD (Bit 6) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_INST_MD (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_MD (Bit 7) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_MD (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_LEN (Bit 8) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_SIZE (Bit 10) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_CS_HIGH_MIN (Bit 12) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_FORCE (Bit 15) */ -#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL) /*!< QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_FORCE (Bitfield-Mask: 0x01) */ - -/* --------------------------- QSPIC_QSPIC_STATUS_REG --------------------------- */ -#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL) /*!< QSPIC QSPIC_STATUS_REG: QSPIC_BUSY (Bit 0) */ -#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL) /*!< QSPIC QSPIC_STATUS_REG: QSPIC_BUSY (Bitfield-Mask: 0x01) */ - -/* -------------------------- QSPIC_QSPIC_WRITEDATA_REG ------------------------- */ -#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL) /*!< QSPIC QSPIC_WRITEDATA_REG: QSPIC_WRITEDATA (Bit 0) */ -#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC QSPIC_WRITEDATA_REG: QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- QSPIC_QSPIC_READDATA_REG -------------------------- */ -#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL) /*!< QSPIC QSPIC_READDATA_REG: QSPIC_READDATA (Bit 0) */ -#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL) /*!< QSPIC QSPIC_READDATA_REG: QSPIC_READDATA (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- QSPIC_QSPIC_DUMMYDATA_REG ------------------------- */ -#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL) /*!< QSPIC QSPIC_DUMMYDATA_REG: QSPIC_DUMMYDATA (Bit 0) */ -#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC QSPIC_DUMMYDATA_REG: QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */ - -/* -------------------------- QSPIC_QSPIC_ERASECTRL_REG ------------------------- */ -#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL) /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_ADDR (Bit 4) */ -#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */ -#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL) /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERASE_EN (Bit 24) */ -#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL) /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERASE_EN (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL) /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_STATE (Bit 25) */ -#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_STATE (Bitfield-Mask: 0x07) */ - -/* -------------------------- QSPIC_QSPIC_ERASECMDA_REG ------------------------- */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_ERS_INST (Bit 0) */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_ERS_INST (Bitfield-Mask: 0xff) */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_WEN_INST (Bit 8) */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_WEN_INST (Bitfield-Mask: 0xff) */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_SUS_INST (Bit 16) */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_SUS_INST (Bitfield-Mask: 0xff) */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_RES_INST (Bit 24) */ -#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC QSPIC_ERASECMDA_REG: QSPIC_RES_INST (Bitfield-Mask: 0xff) */ - -/* -------------------------- QSPIC_QSPIC_ERASECMDB_REG ------------------------- */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_TX_MD (Bit 0) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_WEN_TX_MD (Bit 2) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_SUS_TX_MD (Bit 4) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RES_TX_MD (Bit 6) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_EAD_TX_MD (Bit 8) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_CS_HI (Bit 10) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERSRES_HLD (Bit 16) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RESSUS_DLY (Bit 24) */ -#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC QSPIC_ERASECMDB_REG: QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f) */ - -/* -------------------------- QSPIC_QSPIC_BURSTBRK_REG -------------------------- */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_WRD (Bit 0) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_EN (Bit 16) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_EN (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_SZ (Bit 17) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_SZ (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_TX_MD (Bit 18) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_SEC_HF_DS (Bit 20) */ -#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL) /*!< QSPIC QSPIC_BURSTBRK_REG: QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */ - -/* -------------------------- QSPIC_QSPIC_STATUSCMD_REG ------------------------- */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_INST (Bit 0) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_TX_MD (Bit 8) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_RX_MD (Bit 10) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_POS (Bit 12) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_POS (Bitfield-Mask: 0x07) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_VAL (Bit 15) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RESSTS_DLY (Bit 16) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_STSDLY_SEL (Bit 22) */ -#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC QSPIC_STATUSCMD_REG: QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */ - -/* -------------------------- QSPIC_QSPIC_CHCKERASE_REG ------------------------- */ -#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL) /*!< QSPIC QSPIC_CHCKERASE_REG: QSPIC_CHCKERASE (Bit 0) */ -#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC QSPIC_CHCKERASE_REG: QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */ - -/* ----------------------------- QSPIC_QSPIC_GP_REG ----------------------------- */ -#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL) /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_DRV (Bit 1) */ -#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL) /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_DRV (Bitfield-Mask: 0x03) */ -#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL) /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_SLEW (Bit 3) */ -#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL) /*!< QSPIC QSPIC_GP_REG: QSPIC_PADS_SLEW (Bitfield-Mask: 0x03) */ - -/* --------------------------- QSPIC_QSPIC_UCODE_START -------------------------- */ -#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos (0UL) /*!< QSPIC QSPIC_UCODE_START: QSPIC_UCODE_X (Bit 0) */ -#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk (0xffffffffUL) /*!< QSPIC QSPIC_UCODE_START: QSPIC_UCODE_X (Bitfield-Mask: 0xffffffff) */ - - -/* ================================================================================ */ -/* ================ struct 'QUAD' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- QUAD_QDEC_CTRL_REG ----------------------------- */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Pos (0UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_MASK (Bit 0) */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Msk (0x1UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_MASK (Bitfield-Mask: 0x01) */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Pos (1UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_CLR (Bit 1) */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Msk (0x2UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_CLR (Bitfield-Mask: 0x01) */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Pos (2UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_STATUS (Bit 2) */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Msk (0x4UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_STATUS (Bitfield-Mask: 0x01) */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Pos (3UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_THRES (Bit 3) */ -#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Msk (0x3f8UL) /*!< QUAD QDEC_CTRL_REG: QD_IRQ_THRES (Bitfield-Mask: 0x7f) */ -#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Pos (10UL) /*!< QUAD QDEC_CTRL_REG: CHX_PORT_EN (Bit 10) */ -#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Msk (0x400UL) /*!< QUAD QDEC_CTRL_REG: CHX_PORT_EN (Bitfield-Mask: 0x01) */ -#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Pos (11UL) /*!< QUAD QDEC_CTRL_REG: CHY_PORT_EN (Bit 11) */ -#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Msk (0x800UL) /*!< QUAD QDEC_CTRL_REG: CHY_PORT_EN (Bitfield-Mask: 0x01) */ -#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Pos (12UL) /*!< QUAD QDEC_CTRL_REG: CHZ_PORT_EN (Bit 12) */ -#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Msk (0x1000UL) /*!< QUAD QDEC_CTRL_REG: CHZ_PORT_EN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- QUAD_QDEC_XCNT_REG ----------------------------- */ -#define QUAD_QDEC_XCNT_REG_X_counter_Pos (0UL) /*!< QUAD QDEC_XCNT_REG: X_counter (Bit 0) */ -#define QUAD_QDEC_XCNT_REG_X_counter_Msk (0xffffUL) /*!< QUAD QDEC_XCNT_REG: X_counter (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- QUAD_QDEC_YCNT_REG ----------------------------- */ -#define QUAD_QDEC_YCNT_REG_Y_counter_Pos (0UL) /*!< QUAD QDEC_YCNT_REG: Y_counter (Bit 0) */ -#define QUAD_QDEC_YCNT_REG_Y_counter_Msk (0xffffUL) /*!< QUAD QDEC_YCNT_REG: Y_counter (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- QUAD_QDEC_ZCNT_REG ----------------------------- */ -#define QUAD_QDEC_ZCNT_REG_Z_counter_Pos (0UL) /*!< QUAD QDEC_ZCNT_REG: Z_counter (Bit 0) */ -#define QUAD_QDEC_ZCNT_REG_Z_counter_Msk (0xffffUL) /*!< QUAD QDEC_ZCNT_REG: Z_counter (Bitfield-Mask: 0xffff) */ - -/* --------------------------- QUAD_QDEC_CLOCKDIV_REG --------------------------- */ -#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Pos (0UL) /*!< QUAD QDEC_CLOCKDIV_REG: clock_divider (Bit 0) */ -#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Msk (0x3ffUL) /*!< QUAD QDEC_CLOCKDIV_REG: clock_divider (Bitfield-Mask: 0x3ff) */ - - -/* ================================================================================ */ -/* ================ struct 'RFCU' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- RFCU_RF_OVERRULE_REG ---------------------------- */ -#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Pos (0UL) /*!< RFCU RF_OVERRULE_REG: TX_EN_OVR (Bit 0) */ -#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Msk (0x3UL) /*!< RFCU RF_OVERRULE_REG: TX_EN_OVR (Bitfield-Mask: 0x03) */ -#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Pos (2UL) /*!< RFCU RF_OVERRULE_REG: RX_EN_OVR (Bit 2) */ -#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Msk (0xcUL) /*!< RFCU RF_OVERRULE_REG: RX_EN_OVR (Bitfield-Mask: 0x03) */ -#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Pos (4UL) /*!< RFCU RF_OVERRULE_REG: RF_MODE_OVR (Bit 4) */ -#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Msk (0x30UL) /*!< RFCU RF_OVERRULE_REG: RF_MODE_OVR (Bitfield-Mask: 0x03) */ -#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Pos (6UL) /*!< RFCU RF_OVERRULE_REG: IFF_FTDF_OVR (Bit 6) */ -#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Msk (0xc0UL) /*!< RFCU RF_OVERRULE_REG: IFF_FTDF_OVR (Bitfield-Mask: 0x03) */ -#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Pos (8UL) /*!< RFCU RF_OVERRULE_REG: MIX_FTDF_OVR (Bit 8) */ -#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Msk (0x300UL) /*!< RFCU RF_OVERRULE_REG: MIX_FTDF_OVR (Bitfield-Mask: 0x03) */ -#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Pos (10UL) /*!< RFCU RF_OVERRULE_REG: TXDAC_SEL (Bit 10) */ -#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Msk (0xc00UL) /*!< RFCU RF_OVERRULE_REG: TXDAC_SEL (Bitfield-Mask: 0x03) */ -#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Pos (12UL) /*!< RFCU RF_OVERRULE_REG: GAUSS_DAC_SEL (Bit 12) */ -#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Msk (0x3000UL) /*!< RFCU RF_OVERRULE_REG: GAUSS_DAC_SEL (Bitfield-Mask: 0x03) */ -#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Pos (14UL) /*!< RFCU RF_OVERRULE_REG: CN_FTDF_TIMES2 (Bit 14) */ -#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Msk (0x4000UL) /*!< RFCU RF_OVERRULE_REG: CN_FTDF_TIMES2 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- RFCU_RF_DIAGIRQ01_REG --------------------------- */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Pos (0UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_0 (Bit 0) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Msk (0x1UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_0 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Pos (1UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_0 (Bit 1) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Msk (0x6UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_0 (Bitfield-Mask: 0x03) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Pos (3UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_0 (Bit 3) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Msk (0x38UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_0 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Pos (6UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_0 (Bit 6) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Msk (0x40UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_0 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Pos (8UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_1 (Bit 8) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Msk (0x100UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_1 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Pos (9UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_1 (Bit 9) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Msk (0x600UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_1 (Bitfield-Mask: 0x03) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Pos (11UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_1 (Bit 11) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Msk (0x3800UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_1 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Pos (14UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_1 (Bit 14) */ -#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Msk (0x4000UL) /*!< RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_1 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- RFCU_RF_DIAGIRQ23_REG --------------------------- */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Pos (0UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_2 (Bit 0) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Msk (0x1UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_2 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Pos (1UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_2 (Bit 1) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Msk (0x6UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_2 (Bitfield-Mask: 0x03) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Pos (3UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_2 (Bit 3) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Msk (0x38UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_2 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Pos (6UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_2 (Bit 6) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Msk (0x40UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_2 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Pos (8UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_3 (Bit 8) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Msk (0x100UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_3 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Pos (9UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_3 (Bit 9) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Msk (0x600UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_3 (Bitfield-Mask: 0x03) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Pos (11UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_3 (Bit 11) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Msk (0x3800UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_3 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Pos (14UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_3 (Bit 14) */ -#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Msk (0x4000UL) /*!< RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_3 (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_DIAGIRQ_STAT_REG -------------------------- */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Pos (0UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_0 (Bit 0) */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Msk (0x1UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_0 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Pos (1UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_1 (Bit 1) */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Msk (0x2UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_1 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Pos (2UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_2 (Bit 2) */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Msk (0x4UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_2 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Pos (3UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bit 3) */ -#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Msk (0x8UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_AGC_EXT1_LUT_REG -------------------------- */ -#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Pos (0UL) /*!< RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bit 0) */ -#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Msk (0x3ffUL) /*!< RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bitfield-Mask: 0x3ff) */ - -/* ---------------------------- RFCU_RF_CALSTATE_REG ---------------------------- */ -#define RFCU_RF_CALSTATE_REG_CALSTATE_Pos (0UL) /*!< RFCU RF_CALSTATE_REG: CALSTATE (Bit 0) */ -#define RFCU_RF_CALSTATE_REG_CALSTATE_Msk (0xfUL) /*!< RFCU RF_CALSTATE_REG: CALSTATE (Bitfield-Mask: 0x0f) */ - -/* -------------------------- RFCU_RF_SCAN_FEEDBACK_REG ------------------------- */ -#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Pos (0UL) /*!< RFCU RF_SCAN_FEEDBACK_REG: LF_RES (Bit 0) */ -#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Msk (0xfUL) /*!< RFCU RF_SCAN_FEEDBACK_REG: LF_RES (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Pos (4UL) /*!< RFCU RF_SCAN_FEEDBACK_REG: CP_CUR (Bit 4) */ -#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Msk (0xf0UL) /*!< RFCU RF_SCAN_FEEDBACK_REG: CP_CUR (Bitfield-Mask: 0x0f) */ - -/* --------------------------- RFCU_RF_REF_OSC_BLE_REG -------------------------- */ -#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Pos (0UL) /*!< RFCU RF_REF_OSC_BLE_REG: CNT_RO (Bit 0) */ -#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Msk (0x3fUL) /*!< RFCU RF_REF_OSC_BLE_REG: CNT_RO (Bitfield-Mask: 0x3f) */ -#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Pos (6UL) /*!< RFCU RF_REF_OSC_BLE_REG: CNT_CLK (Bit 6) */ -#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Msk (0x7fc0UL) /*!< RFCU RF_REF_OSC_BLE_REG: CNT_CLK (Bitfield-Mask: 0x1ff) */ - -/* -------------------------- RFCU_RF_REF_OSC_FTDF_REG -------------------------- */ -#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Pos (0UL) /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_RO (Bit 0) */ -#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Msk (0x3fUL) /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_RO (Bitfield-Mask: 0x3f) */ -#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Pos (6UL) /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_CLK (Bit 6) */ -#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Msk (0x7fc0UL) /*!< RFCU RF_REF_OSC_FTDF_REG: CNT_CLK (Bitfield-Mask: 0x1ff) */ - -/* ---------------------------- RFCU_RF_CAL_CTRL_REG ---------------------------- */ -#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Pos (0UL) /*!< RFCU RF_CAL_CTRL_REG: SO_CAL (Bit 0) */ -#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Msk (0x1UL) /*!< RFCU RF_CAL_CTRL_REG: SO_CAL (Bitfield-Mask: 0x01) */ -#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Pos (1UL) /*!< RFCU RF_CAL_CTRL_REG: EO_CAL (Bit 1) */ -#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Msk (0x2UL) /*!< RFCU RF_CAL_CTRL_REG: EO_CAL (Bitfield-Mask: 0x01) */ -#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Pos (2UL) /*!< RFCU RF_CAL_CTRL_REG: MGAIN_CAL_DIS (Bit 2) */ -#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Msk (0x4UL) /*!< RFCU RF_CAL_CTRL_REG: MGAIN_CAL_DIS (Bitfield-Mask: 0x01) */ -#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Pos (3UL) /*!< RFCU RF_CAL_CTRL_REG: IFF_CAL_DIS (Bit 3) */ -#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Msk (0x8UL) /*!< RFCU RF_CAL_CTRL_REG: IFF_CAL_DIS (Bitfield-Mask: 0x01) */ -#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Pos (4UL) /*!< RFCU RF_CAL_CTRL_REG: DC_OFFSET_CAL_DIS (Bit 4) */ -#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Msk (0x10UL) /*!< RFCU RF_CAL_CTRL_REG: DC_OFFSET_CAL_DIS (Bitfield-Mask: 0x01) */ -#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Pos (5UL) /*!< RFCU RF_CAL_CTRL_REG: VCO_CAL_DIS (Bit 5) */ -#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Msk (0x20UL) /*!< RFCU RF_CAL_CTRL_REG: VCO_CAL_DIS (Bitfield-Mask: 0x01) */ - -/* ---------------------------- RFCU_RF_IRQ_CTRL_REG ---------------------------- */ -#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Pos (0UL) /*!< RFCU RF_IRQ_CTRL_REG: EO_CAL_CLEAR (Bit 0) */ -#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Msk (0x1UL) /*!< RFCU RF_IRQ_CTRL_REG: EO_CAL_CLEAR (Bitfield-Mask: 0x01) */ - -/* ------------------------- RFCU_RF_ADCI_DC_OFFSET_REG ------------------------- */ -#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Pos (0UL) /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFP_I_RD (Bit 0) */ -#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Msk (0xffUL) /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFP_I_RD (Bitfield-Mask: 0xff) */ -#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Pos (8UL) /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFN_I_RD (Bit 8) */ -#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Msk (0xff00UL) /*!< RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFN_I_RD (Bitfield-Mask: 0xff) */ - -/* ------------------------- RFCU_RF_ADCQ_DC_OFFSET_REG ------------------------- */ -#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Pos (0UL) /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFP_Q_RD (Bit 0) */ -#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Msk (0xffUL) /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFP_Q_RD (Bitfield-Mask: 0xff) */ -#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Pos (8UL) /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFN_Q_RD (Bit 8) */ -#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Msk (0xff00UL) /*!< RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFN_Q_RD (Bitfield-Mask: 0xff) */ - -/* --------------------------- RFCU_RF_SPARE1_BLE_REG --------------------------- */ -#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Pos (0UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_RFCLK_TEST (Bit 0) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Msk (0x1UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_RFCLK_TEST (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos (1UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_PLL_DXTAL16_TEST (Bit 1) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk (0x2UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos (2UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk (0x4UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Pos (3UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bit 3) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Msk (0x8UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Pos (4UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bit 4) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Msk (0x30UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Pos (6UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bit 6) */ -#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Msk (0xffc0UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff) */ - -/* --------------------------- RFCU_RF_SPARE1_FTDF_REG -------------------------- */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Pos (0UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_RFCLK_TEST (Bit 0) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Msk (0x1UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_RFCLK_TEST (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos (1UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_PLL_DXTAL16_TEST (Bit 1) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk (0x2UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos (2UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk (0x4UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Pos (3UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bit 3) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Msk (0x8UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Pos (4UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bit 4) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Msk (0x30UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Pos (6UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bit 6) */ -#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Msk (0xffc0UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff) */ - -/* ------------------------- RFCU_RF_BIAS_CTRL1_BLE_REG ------------------------- */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Pos (0UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: MIX_BIAS_BLE_SET (Bit 0) */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Msk (0xfUL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: MIX_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Pos (4UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: CP_BIAS_BLE_SET (Bit 4) */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Msk (0xf0UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: CP_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Pos (8UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: VCO_BIAS_BLE_SET (Bit 8) */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Msk (0xf00UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: VCO_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Pos (12UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: IFF_BIAS_BLE_SET (Bit 12) */ -#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Msk (0xf000UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: IFF_BIAS_BLE_SET (Bitfield-Mask: 0x0f) */ - -/* ------------------------- RFCU_RF_BIAS_CTRL1_FTDF_REG ------------------------ */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Pos (0UL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: MIX_BIAS_FTDF_SET (Bit 0) */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Msk (0xfUL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: MIX_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Pos (4UL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: CP_BIAS_FTDF_SET (Bit 4) */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Msk (0xf0UL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: CP_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Pos (8UL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: VCO_BIAS_FTDF_SET (Bit 8) */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Msk (0xf00UL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: VCO_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Pos (12UL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: IFF_BIAS_FTDF_SET (Bit 12) */ -#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Msk (0xf000UL) /*!< RFCU RF_BIAS_CTRL1_FTDF_REG: IFF_BIAS_FTDF_SET (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- RFCU_RF_IFF_CTRL1_REG --------------------------- */ -#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Pos (0UL) /*!< RFCU RF_IFF_CTRL1_REG: IF_CAL_CAP (Bit 0) */ -#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Msk (0x1fUL) /*!< RFCU RF_IFF_CTRL1_REG: IF_CAL_CAP (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Pos (5UL) /*!< RFCU RF_IFF_CTRL1_REG: IF_MUTE (Bit 5) */ -#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Msk (0x20UL) /*!< RFCU RF_IFF_CTRL1_REG: IF_MUTE (Bitfield-Mask: 0x01) */ -#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Pos (6UL) /*!< RFCU RF_IFF_CTRL1_REG: IFF_DCOC_DAC_DIS (Bit 6) */ -#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Msk (0x40UL) /*!< RFCU RF_IFF_CTRL1_REG: IFF_DCOC_DAC_DIS (Bitfield-Mask: 0x01) */ -#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Pos (7UL) /*!< RFCU RF_IFF_CTRL1_REG: RO_TO_PINS (Bit 7) */ -#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Msk (0x80UL) /*!< RFCU RF_IFF_CTRL1_REG: RO_TO_PINS (Bitfield-Mask: 0x01) */ -#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Pos (8UL) /*!< RFCU RF_IFF_CTRL1_REG: IF_SEL_SET2_GT (Bit 8) */ -#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Msk (0xf00UL) /*!< RFCU RF_IFF_CTRL1_REG: IF_SEL_SET2_GT (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Pos (12UL) /*!< RFCU RF_IFF_CTRL1_REG: IF_SELECT_FSM (Bit 12) */ -#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Msk (0x1000UL) /*!< RFCU RF_IFF_CTRL1_REG: IF_SELECT_FSM (Bitfield-Mask: 0x01) */ -#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Pos (13UL) /*!< RFCU RF_IFF_CTRL1_REG: IFF_COMPLEX_DIS (Bit 13) */ -#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Msk (0x2000UL) /*!< RFCU RF_IFF_CTRL1_REG: IFF_COMPLEX_DIS (Bitfield-Mask: 0x01) */ - -/* ---------------------------- RFCU_RF_ADC_CTRL1_REG --------------------------- */ -#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Pos (0UL) /*!< RFCU RF_ADC_CTRL1_REG: ADC_DC_OFFSET_SEL (Bit 0) */ -#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Msk (0x1UL) /*!< RFCU RF_ADC_CTRL1_REG: ADC_DC_OFFSET_SEL (Bitfield-Mask: 0x01) */ -#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Pos (13UL) /*!< RFCU RF_ADC_CTRL1_REG: ADC_MUTE (Bit 13) */ -#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Msk (0x2000UL) /*!< RFCU RF_ADC_CTRL1_REG: ADC_MUTE (Bitfield-Mask: 0x01) */ -#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Pos (14UL) /*!< RFCU RF_ADC_CTRL1_REG: ADC_SIGN (Bit 14) */ -#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Msk (0x4000UL) /*!< RFCU RF_ADC_CTRL1_REG: ADC_SIGN (Bitfield-Mask: 0x01) */ - -/* ---------------------------- RFCU_RF_ADC_CTRL2_REG --------------------------- */ -#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Pos (0UL) /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFP_I_WR (Bit 0) */ -#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Msk (0xffUL) /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFP_I_WR (Bitfield-Mask: 0xff) */ -#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Pos (8UL) /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFN_I_WR (Bit 8) */ -#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Msk (0xff00UL) /*!< RFCU RF_ADC_CTRL2_REG: ADC_OFFN_I_WR (Bitfield-Mask: 0xff) */ - -/* ---------------------------- RFCU_RF_ADC_CTRL3_REG --------------------------- */ -#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Pos (0UL) /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFP_Q_WR (Bit 0) */ -#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Msk (0xffUL) /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFP_Q_WR (Bitfield-Mask: 0xff) */ -#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Pos (8UL) /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFN_Q_WR (Bit 8) */ -#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Msk (0xff00UL) /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFN_Q_WR (Bitfield-Mask: 0xff) */ - -/* ----------------------------- RFCU_RF_PA_CTRL_REG ---------------------------- */ -#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Pos (5UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bit 5) */ -#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Msk (0x60UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bitfield-Mask: 0x03) */ -#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Pos (7UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bit 7) */ -#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Msk (0x180UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bitfield-Mask: 0x03) */ -#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Pos (9UL) /*!< RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bit 9) */ -#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Msk (0x200UL) /*!< RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bitfield-Mask: 0x01) */ -#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Pos (11UL) /*!< RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bit 11) */ -#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Msk (0x7800UL) /*!< RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- RFCU_RF_MGC_CTRL_REG ---------------------------- */ -#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Pos (0UL) /*!< RFCU RF_MGC_CTRL_REG: MGC_GAIN_SET (Bit 0) */ -#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Msk (0x1UL) /*!< RFCU RF_MGC_CTRL_REG: MGC_GAIN_SET (Bitfield-Mask: 0x01) */ -#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Pos (1UL) /*!< RFCU RF_MGC_CTRL_REG: MGC_POLE_SW (Bit 1) */ -#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Msk (0x2UL) /*!< RFCU RF_MGC_CTRL_REG: MGC_POLE_SW (Bitfield-Mask: 0x01) */ -#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Pos (2UL) /*!< RFCU RF_MGC_CTRL_REG: GAUSS_DAC_CTRL (Bit 2) */ -#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Msk (0xcUL) /*!< RFCU RF_MGC_CTRL_REG: GAUSS_DAC_CTRL (Bitfield-Mask: 0x03) */ - -/* --------------------------- RFCU_RF_VCOVAR_CTRL_REG -------------------------- */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Pos (0UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V0 (Bit 0) */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Msk (0x7UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V0 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Pos (3UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V1 (Bit 3) */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Msk (0x38UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V1 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Pos (6UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V2 (Bit 6) */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Msk (0x1c0UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V2 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Pos (9UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V3 (Bit 9) */ -#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Msk (0xe00UL) /*!< RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V3 (Bitfield-Mask: 0x07) */ -#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Pos (12UL) /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V0 (Bit 12) */ -#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Msk (0x3000UL) /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V0 (Bitfield-Mask: 0x03) */ -#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Pos (14UL) /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V1 (Bit 14) */ -#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Msk (0xc000UL) /*!< RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V1 (Bitfield-Mask: 0x03) */ - -/* ---------------------------- RFCU_RF_PFD_CTRL_REG ---------------------------- */ -#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Pos (0UL) /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_SET (Bit 0) */ -#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Msk (0x3UL) /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_SET (Bitfield-Mask: 0x03) */ -#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Pos (2UL) /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_EN (Bit 2) */ -#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Msk (0x4UL) /*!< RFCU RF_PFD_CTRL_REG: FIXED_CUR_EN (Bitfield-Mask: 0x01) */ -#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Pos (3UL) /*!< RFCU RF_PFD_CTRL_REG: PFD_POLARITY (Bit 3) */ -#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Msk (0x8UL) /*!< RFCU RF_PFD_CTRL_REG: PFD_POLARITY (Bitfield-Mask: 0x01) */ - -/* --------------------------- RFCU_RF_CP_CTRL_BLE_REG -------------------------- */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Pos (0UL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_RX (Bit 0) */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Msk (0xfUL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Pos (4UL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_TX (Bit 4) */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Msk (0xf0UL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_TX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Pos (8UL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_RX (Bit 8) */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Msk (0xf00UL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Pos (12UL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_TX (Bit 12) */ -#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Msk (0xf000UL) /*!< RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_TX (Bitfield-Mask: 0x0f) */ - -/* -------------------------- RFCU_RF_CP_CTRL_FTDF_REG -------------------------- */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Pos (0UL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_RX (Bit 0) */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Msk (0xfUL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Pos (4UL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_TX (Bit 4) */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Msk (0xf0UL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_TX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Pos (8UL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_RX (Bit 8) */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Msk (0xf00UL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Pos (12UL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_TX (Bit 12) */ -#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Msk (0xf000UL) /*!< RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_TX (Bitfield-Mask: 0x0f) */ - -/* ------------------------- RFCU_RF_LF_RES_CTRL_BLE_REG ------------------------ */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Pos (0UL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_RX (Bit 0) */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Msk (0xfUL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Pos (4UL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_TX (Bit 4) */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Msk (0xf0UL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_TX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Pos (8UL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_RX (Bit 8) */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Msk (0xf00UL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Pos (12UL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_TX (Bit 12) */ -#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Msk (0xf000UL) /*!< RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_TX (Bitfield-Mask: 0x0f) */ - -/* ------------------------ RFCU_RF_LF_RES_CTRL_FTDF_REG ------------------------ */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Pos (0UL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_RX (Bit 0) */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Msk (0xfUL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Pos (4UL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_TX (Bit 4) */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Msk (0xf0UL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_TX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Pos (8UL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_RX (Bit 8) */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Msk (0xf00UL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Pos (12UL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_TX (Bit 12) */ -#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Msk (0xf000UL) /*!< RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_TX (Bitfield-Mask: 0x0f) */ - -/* ------------------------- RFCU_RF_MIXER_CTRL1_BLE_REG ------------------------ */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Pos (0UL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_GMBIAS_BLE (Bit 0) */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Msk (0xfUL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_GMBIAS_BLE (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Pos (4UL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_IBIAS_BLE (Bit 4) */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Msk (0xf0UL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_IBIAS_BLE (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Pos (8UL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_VCM_BLE (Bit 8) */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Msk (0xf00UL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_VCM_BLE (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Pos (12UL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_SPARE_BLE (Bit 12) */ -#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Msk (0xf000UL) /*!< RFCU RF_MIXER_CTRL1_BLE_REG: MIX_SPARE_BLE (Bitfield-Mask: 0x0f) */ - -/* ------------------------ RFCU_RF_MIXER_CTRL1_FTDF_REG ------------------------ */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Pos (0UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_GMBIAS_FTDF (Bit 0) */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Msk (0xfUL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_GMBIAS_FTDF (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Pos (4UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_IBIAS_FTDF (Bit 4) */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Msk (0xf0UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_IBIAS_FTDF (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Pos (8UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_VCM_FTDF (Bit 8) */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Msk (0xf00UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_VCM_FTDF (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Pos (12UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_SPARE (Bit 12) */ -#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Msk (0xf000UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_SPARE (Bitfield-Mask: 0x0f) */ - -/* --------------------------- RFCU_RF_MIXER_CTRL2_REG -------------------------- */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Pos (0UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bit 0) */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Msk (0x1fUL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Pos (5UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bit 5) */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Msk (0x20UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bitfield-Mask: 0x01) */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Pos (6UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bit 6) */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Msk (0x7c0UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */ - -/* ----------------------------- RFCU_RF_LF_CTRL_REG ---------------------------- */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Pos (0UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bit 0) */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Msk (0x1fUL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Pos (5UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bit 5) */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Msk (0x20UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bitfield-Mask: 0x01) */ -#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Pos (6UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bit 6) */ -#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Msk (0x40UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bitfield-Mask: 0x01) */ -#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Pos (7UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bit 7) */ -#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Msk (0x80UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bitfield-Mask: 0x01) */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Pos (8UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bit 8) */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Msk (0x1f00UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */ - -/* ---------------------------- RFCU_RF_TDC_CTRL_REG ---------------------------- */ -#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Pos (0UL) /*!< RFCU RF_TDC_CTRL_REG: CTRL_FAST (Bit 0) */ -#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Msk (0xfUL) /*!< RFCU RF_TDC_CTRL_REG: CTRL_FAST (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Pos (4UL) /*!< RFCU RF_TDC_CTRL_REG: CTRL_SLOW (Bit 4) */ -#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Msk (0xf0UL) /*!< RFCU RF_TDC_CTRL_REG: CTRL_SLOW (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Pos (8UL) /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_1 (Bit 8) */ -#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Msk (0x100UL) /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_1 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Pos (9UL) /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_2 (Bit 9) */ -#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Msk (0x200UL) /*!< RFCU RF_TDC_CTRL_REG: CAL_PH_2 (Bitfield-Mask: 0x01) */ -#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Pos (10UL) /*!< RFCU RF_TDC_CTRL_REG: REF_CTRL (Bit 10) */ -#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Msk (0xc00UL) /*!< RFCU RF_TDC_CTRL_REG: REF_CTRL (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Pos (12UL) /*!< RFCU RF_TDC_CTRL_REG: TDC_CONNECT (Bit 12) */ -#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Msk (0x1000UL) /*!< RFCU RF_TDC_CTRL_REG: TDC_CONNECT (Bitfield-Mask: 0x01) */ - -/* ---------------------------- RFCU_RF_IO_CTRL1_REG ---------------------------- */ -#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Pos (0UL) /*!< RFCU RF_IO_CTRL1_REG: RFIO_TRIM1_CAP (Bit 0) */ -#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Msk (0xffUL) /*!< RFCU RF_IO_CTRL1_REG: RFIO_TRIM1_CAP (Bitfield-Mask: 0xff) */ - -/* ---------------------------- RFCU_RF_LNA_CTRL1_REG --------------------------- */ -#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Pos (0UL) /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_LF (Bit 0) */ -#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Msk (0x3fUL) /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_LF (Bitfield-Mask: 0x3f) */ -#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Pos (6UL) /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_HF (Bit 6) */ -#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Msk (0xfc0UL) /*!< RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_HF (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- RFCU_RF_LNA_CTRL2_REG --------------------------- */ -#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Pos (0UL) /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_HI (Bit 0) */ -#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Msk (0x3fUL) /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_HI (Bitfield-Mask: 0x3f) */ -#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Pos (6UL) /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_LO (Bit 6) */ -#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Msk (0xfc0UL) /*!< RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_LO (Bitfield-Mask: 0x3f) */ - -/* ---------------------------- RFCU_RF_LNA_CTRL3_REG --------------------------- */ -#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Pos (0UL) /*!< RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bit 0) */ -#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Msk (0x1fUL) /*!< RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bitfield-Mask: 0x1f) */ - -/* -------------------------- RFCU_RF_VCO_AMP_CTRL1_REG ------------------------- */ -#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Pos (0UL) /*!< RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bit 0) */ -#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Msk (0x7fUL) /*!< RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bitfield-Mask: 0x7f) */ - -/* -------------------------- RFCU_RF_VCO_AMP_CTRL2_REG ------------------------- */ -#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Pos (0UL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bit 0) */ -#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Msk (0xffUL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bitfield-Mask: 0xff) */ -#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Pos (8UL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bit 8) */ -#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Msk (0xff00UL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bitfield-Mask: 0xff) */ - -/* --------------------------- RFCU_RF_TX_PWR_BLE_REG --------------------------- */ -#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Pos (0UL) /*!< RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bit 0) */ -#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Msk (0x7UL) /*!< RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bitfield-Mask: 0x07) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_1_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ -#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_2_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ -#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_3_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ -#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_4_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ -#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_5_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ -#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_6_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ -#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_7_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ - -/* --------------------------- RFCU_RF_TX_PWR_FTDF_REG -------------------------- */ -#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Pos (0UL) /*!< RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bit 0) */ -#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Msk (0x7UL) /*!< RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bitfield-Mask: 0x07) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_RD_REG ------------------------- */ -#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Msk (0xfffUL) /*!< RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bitfield-Mask: 0xfff) */ - -/* ---------------------------- RFCU_RF_DIV_IQ_RX_REG --------------------------- */ -#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Pos (0UL) /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFN_TRIM_RX (Bit 0) */ -#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Msk (0xfUL) /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFN_TRIM_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Pos (4UL) /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFP_TRIM_RX (Bit 4) */ -#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Msk (0xf0UL) /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFP_TRIM_RX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Pos (8UL) /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_IQ_TRIM_RX_SPARE (Bit 8) */ -#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Msk (0x100UL) /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_IQ_TRIM_RX_SPARE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- RFCU_RF_DIV_IQ_TX_REG --------------------------- */ -#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Pos (0UL) /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFN_TRIM_TX (Bit 0) */ -#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Msk (0xfUL) /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFN_TRIM_TX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Pos (4UL) /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFP_TRIM_TX (Bit 4) */ -#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Msk (0xf0UL) /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_OFFP_TRIM_TX (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Pos (8UL) /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_IQ_TRIM_TX_SPARE (Bit 8) */ -#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Msk (0x100UL) /*!< RFCU RF_DIV_IQ_TX_REG: DIV2_IQ_TRIM_TX_SPARE (Bitfield-Mask: 0x01) */ - -/* --------------------------- RFCU_RF_LO_IQ_TRIM_REG --------------------------- */ -#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Pos (0UL) /*!< RFCU RF_LO_IQ_TRIM_REG: RF_LO_IQ_TRIM (Bit 0) */ -#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Msk (0xffffUL) /*!< RFCU RF_LO_IQ_TRIM_REG: RF_LO_IQ_TRIM (Bitfield-Mask: 0xffff) */ - -/* --------------------------- RFCU_RF_TXDAC_CTRL_REG --------------------------- */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Pos (0UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bit 0) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Msk (0x1fUL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Pos (5UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bit 5) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Msk (0x20UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bitfield-Mask: 0x01) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Pos (6UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bit 6) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Msk (0x40UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bitfield-Mask: 0x01) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Pos (7UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bit 7) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Msk (0xf80UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */ - -/* ----------------------- RFCU_RF_TXDAC_CAL_CAP_STAT_REG ----------------------- */ -#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Pos (0UL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bit 0) */ -#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Msk (0x1fUL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Pos (5UL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bit 5) */ -#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Msk (0x20UL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bitfield-Mask: 0x01) */ - -/* --------------------------- RFCU_RF_IFF_RESULT_REG --------------------------- */ -#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Pos (0UL) /*!< RFCU RF_IFF_RESULT_REG: IF_CAL_CAP_RD (Bit 0) */ -#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Msk (0x1fUL) /*!< RFCU RF_IFF_RESULT_REG: IF_CAL_CAP_RD (Bitfield-Mask: 0x1f) */ - -/* ------------------------- RFCU_RF_IFF_CC_BLE_SET1_REG ------------------------ */ -#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Pos (0UL) /*!< RFCU RF_IFF_CC_BLE_SET1_REG: IF_CAL_CAP_WR (Bit 0) */ -#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Msk (0x1fUL) /*!< RFCU RF_IFF_CC_BLE_SET1_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */ - -/* ------------------------- RFCU_RF_IFF_CC_BLE_SET2_REG ------------------------ */ -#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Pos (0UL) /*!< RFCU RF_IFF_CC_BLE_SET2_REG: IF_CAL_CAP_WR (Bit 0) */ -#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Msk (0x1fUL) /*!< RFCU RF_IFF_CC_BLE_SET2_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */ - -/* ------------------------ RFCU_RF_IFF_CC_FTDF_SET1_REG ------------------------ */ -#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Pos (0UL) /*!< RFCU RF_IFF_CC_FTDF_SET1_REG: IF_CAL_CAP_WR (Bit 0) */ -#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Msk (0x1fUL) /*!< RFCU RF_IFF_CC_FTDF_SET1_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */ - -/* ------------------------ RFCU_RF_IFF_CC_FTDF_SET2_REG ------------------------ */ -#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Pos (0UL) /*!< RFCU RF_IFF_CC_FTDF_SET2_REG: IF_CAL_CAP_WR (Bit 0) */ -#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Msk (0x1fUL) /*!< RFCU RF_IFF_CC_FTDF_SET2_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */ - -/* ------------------------ RFCU_RF_IFF_CAL_CAP_STAT_REG ------------------------ */ -#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Pos (0UL) /*!< RFCU RF_IFF_CAL_CAP_STAT_REG: IF_CAL_CAP_RD (Bit 0) */ -#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Msk (0x1fUL) /*!< RFCU RF_IFF_CAL_CAP_STAT_REG: IF_CAL_CAP_RD (Bitfield-Mask: 0x1f) */ - -/* ------------------------ RFCU_RF_MIX_CAL_CAP_STAT_REG ------------------------ */ -#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Pos (0UL) /*!< RFCU RF_MIX_CAL_CAP_STAT_REG: MIX_CAL_CAP_RD (Bit 0) */ -#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Msk (0x1fUL) /*!< RFCU RF_MIX_CAL_CAP_STAT_REG: MIX_CAL_CAP_RD (Bitfield-Mask: 0x1f) */ - -/* ------------------------- RFCU_RF_LF_CAL_CAP_STAT_REG ------------------------ */ -#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Pos (0UL) /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_CAL_CAP_RD (Bit 0) */ -#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Msk (0x1fUL) /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_CAL_CAP_RD (Bitfield-Mask: 0x1f) */ -#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Pos (5UL) /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_SHORT_R4_RD (Bit 5) */ -#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Msk (0x20UL) /*!< RFCU RF_LF_CAL_CAP_STAT_REG: LF_SHORT_R4_RD (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'RFCU_POWER' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG0_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG1_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG2_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG3_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG4_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG5_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG6_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG7_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG8_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG9_REG ---------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG10_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG11_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG12_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG13_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG14_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG15_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG16_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG17_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG18_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG19_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG20_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG21_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG22_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG25_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG26_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG27_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG28_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG29_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG30_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG32_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG33_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG34_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG36_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG39_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG40_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG41_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG42_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG43_REG --------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_1_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_1_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_2_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_2_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_3_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_3_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_4_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_4_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_5_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_5_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_6_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_6_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_7_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_7_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_8_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_8_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ----------------------- RFCU_POWER_RF_CNTRL_TIMER_9_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_9_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_10_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_10_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_11_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_11_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_12_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_12_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_13_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_13_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_14_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_14_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_15_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_15_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_16_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_16_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_17_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_17_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_18_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_18_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_19_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_19_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_20_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_20_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_21_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_21_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_22_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_22_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_23_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_23_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_24_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_24_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_25_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_25_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_26_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_26_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_27_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_27_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_28_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_28_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_29_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_29_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_30_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_30_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ---------------------- RFCU_POWER_RF_CNTRL_TIMER_31_REG ---------------------- */ -#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Pos (0UL) /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: SET_OFFSET (Bit 0) */ -#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Msk (0xffUL) /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: SET_OFFSET (Bitfield-Mask: 0xff) */ -#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Pos (8UL) /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: RESET_OFFSET (Bit 8) */ -#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Msk (0xff00UL) /*!< RFCU_POWER RF_CNTRL_TIMER_31_REG: RESET_OFFSET (Bitfield-Mask: 0xff) */ - -/* ------------------------ RFCU_POWER_RF_ALWAYS_EN1_REG ------------------------ */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Pos (0UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_EN (Bit 0) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Msk (0x1UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Pos (1UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CORE_EN (Bit 1) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Msk (0x2UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CORE_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Pos (2UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CGM_EN (Bit 2) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Msk (0x4UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CGM_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Pos (3UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MIX_LDO_EN (Bit 3) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Msk (0x8UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MIX_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Pos (4UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFF_LDO_EN (Bit 4) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Msk (0x10UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFF_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Pos (5UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFFADC_LDO_EN (Bit 5) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Msk (0x20UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFFADC_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Pos (6UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_LDO_EN (Bit 6) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Msk (0x40UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Pos (7UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MD_LDO_EN (Bit 7) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Msk (0x80UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MD_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Pos (8UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PFD_LDO_EN (Bit 8) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Msk (0x100UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PFD_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Pos (9UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_LDO_EN (Bit 9) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Msk (0x200UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_LDO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Pos (10UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_SWITCH_EN (Bit 10) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Msk (0x400UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_SWITCH_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Pos (11UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_BIAS_EN (Bit 11) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Msk (0x800UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_BIAS_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Pos (12UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_BIAS_EN (Bit 12) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Msk (0x1000UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_BIAS_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Pos (13UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_ZERO (Bit 13) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Msk (0x2000UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_ZERO (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Pos (14UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_RAMP_EN (Bit 14) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Msk (0x4000UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_RAMP_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Pos (15UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_EN (Bit 15) */ -#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Msk (0x8000UL) /*!< RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------ RFCU_POWER_RF_ALWAYS_EN2_REG ------------------------ */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Pos (0UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_MIX_EN (Bit 0) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Msk (0x1UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_MIX_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Pos (1UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFF_EN (Bit 1) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Msk (0x2UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFF_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Pos (2UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_ADC_EN (Bit 2) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Msk (0x4UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_ADC_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Pos (3UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_EN (Bit 3) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Msk (0x8UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Pos (4UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_MD_EN (Bit 4) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Msk (0x10UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_MD_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Pos (5UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_EN (Bit 5) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Msk (0x20UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Pos (6UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_PDF_EN (Bit 6) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Msk (0x40UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_PDF_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Pos (7UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_EN (Bit 7) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Msk (0x80UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Pos (8UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RFIO_TXRX (Bit 8) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Msk (0x100UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RFIO_TXRX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Pos (9UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_PA_EN (Bit 9) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Msk (0x200UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_PA_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Pos (10UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RXIQ_EN (Bit 10) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Msk (0x400UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RXIQ_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Pos (11UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_DIV2_EN (Bit 11) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Msk (0x800UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_DIV2_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Pos (12UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_BIAS_SH_OPEN (Bit 12) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Msk (0x1000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_BIAS_SH_OPEN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Pos (13UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_BIAS_SH_OPEN (Bit 13) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Msk (0x2000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_BIAS_SH_OPEN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Pos (14UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFFMIX_BIAS_SH_OPEN (Bit 14) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Msk (0x4000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFFMIX_BIAS_SH_OPEN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Pos (15UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_BIAS_SH (Bit 15) */ -#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Msk (0x8000UL) /*!< RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_BIAS_SH (Bitfield-Mask: 0x01) */ - -/* ------------------------ RFCU_POWER_RF_ALWAYS_EN3_REG ------------------------ */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Pos (0UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_MIX_BIAS_SH (Bit 0) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Msk (0x1UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_MIX_BIAS_SH (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Pos (1UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLL_DIG_EN (Bit 1) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Msk (0x2UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLL_DIG_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Pos (2UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLLCLOSED_EN (Bit 2) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Msk (0x4UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLLCLOSED_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Pos (3UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_DEM_EN (Bit 3) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Msk (0x8UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_DEM_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Pos (4UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_ZERO_EN (Bit 4) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Msk (0x10UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_ZERO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Pos (5UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_CAL_EN (Bit 5) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Msk (0x20UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_CAL_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Pos (6UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TDC_EN (Bit 6) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Msk (0x40UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TDC_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Pos (7UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RFIO_EN (Bit 7) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Msk (0x80UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RFIO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Pos (8UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_EN (Bit 8) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Msk (0x100UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Pos (9UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_SH (Bit 9) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Msk (0x200UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_SH (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Pos (10UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RADIO_EN (Bit 10) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Msk (0x400UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RADIO_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Pos (11UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_ADC_CLK_EN (Bit 11) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Msk (0x800UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_ADC_CLK_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Pos (12UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TR_PWRM_OFF_EN (Bit 12) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Msk (0x1000UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TR_PWRM_OFF_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Pos (13UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TXDAC_EN (Bit 13) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Msk (0x2000UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TXDAC_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Pos (14UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE2_EN (Bit 14) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Msk (0x4000UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE2_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Pos (15UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE3_EN (Bit 15) */ -#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Msk (0x8000UL) /*!< RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE3_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------ RFCU_POWER_RF_ALWAYS_EN4_REG ------------------------ */ -#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Pos (0UL) /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_SPARE4_EN (Bit 0) */ -#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Msk (0x1UL) /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_SPARE4_EN (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Pos (1UL) /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bit 1) */ -#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Msk (0x2UL) /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------ RFCU_POWER_RF_PORT_EN_BLE_REG ----------------------- */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Pos (0UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bit 0) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Msk (0x1UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Pos (1UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bit 1) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Msk (0x2UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Pos (2UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bit 2) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Msk (0x4UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Pos (3UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bit 3) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Msk (0x8UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Pos (4UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bit 4) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Msk (0x10UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Pos (5UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bit 5) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Msk (0x20UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Pos (6UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bit 6) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk (0x40UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Pos (7UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bit 7) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk (0x80UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Pos (8UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bit 8) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Msk (0x100UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Pos (9UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bit 9) */ -#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Msk (0x200UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bitfield-Mask: 0x01) */ - -/* ----------------------- RFCU_POWER_RF_PORT_EN_FTDF_REG ----------------------- */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Pos (0UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bit 0) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Msk (0x1UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Pos (1UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bit 1) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Msk (0x2UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Pos (2UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bit 2) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Msk (0x4UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Pos (3UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bit 3) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Msk (0x8UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Pos (4UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bit 4) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Msk (0x10UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Pos (5UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bit 5) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Msk (0x20UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Pos (6UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bit 6) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk (0x40UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Pos (7UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bit 7) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk (0x80UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Pos (8UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bit 8) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Msk (0x100UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Pos (9UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bit 9) */ -#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Msk (0x200UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bitfield-Mask: 0x01) */ - -/* ------------------------- RFCU_POWER_RF_PORT_POL_REG ------------------------- */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Pos (0UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT0_POL (Bit 0) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Msk (0x1UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT0_POL (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Pos (1UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT1_POL (Bit 1) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Msk (0x2UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT1_POL (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Pos (2UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT2_POL (Bit 2) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Msk (0x4UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT2_POL (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Pos (3UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT3_POL (Bit 3) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Msk (0x8UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT3_POL (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Pos (4UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT4_POL (Bit 4) */ -#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Msk (0x10UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT4_POL (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'RFPT' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- RFPT_RFPT_CTRL_REG ----------------------------- */ -#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Pos (0UL) /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_EN (Bit 0) */ -#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Msk (0x1UL) /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_EN (Bitfield-Mask: 0x01) */ -#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Pos (1UL) /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_SEL (Bit 1) */ -#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Msk (0x6UL) /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_SEL (Bitfield-Mask: 0x03) */ -#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Pos (3UL) /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_ADC_TYPE (Bit 3) */ -#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Msk (0x8UL) /*!< RFPT RFPT_CTRL_REG: RFPT_PACK_ADC_TYPE (Bitfield-Mask: 0x01) */ -#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Pos (4UL) /*!< RFPT RFPT_CTRL_REG: RFPT_CIRC_EN (Bit 4) */ -#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Msk (0x10UL) /*!< RFPT RFPT_CTRL_REG: RFPT_CIRC_EN (Bitfield-Mask: 0x01) */ -#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Pos (5UL) /*!< RFPT RFPT_CTRL_REG: RFPT_BREQ_FORCE (Bit 5) */ -#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Msk (0x20UL) /*!< RFPT RFPT_CTRL_REG: RFPT_BREQ_FORCE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- RFPT_RFPT_ADDRL_REG ---------------------------- */ -#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Pos (2UL) /*!< RFPT RFPT_ADDRL_REG: RFPT_ADDRL (Bit 2) */ -#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Msk (0xfffcUL) /*!< RFPT RFPT_ADDRL_REG: RFPT_ADDRL (Bitfield-Mask: 0x3fff) */ - -/* ----------------------------- RFPT_RFPT_ADDRH_REG ---------------------------- */ -#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Pos (0UL) /*!< RFPT RFPT_ADDRH_REG: RFPT_ADDRH (Bit 0) */ -#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Msk (0x3UL) /*!< RFPT RFPT_ADDRH_REG: RFPT_ADDRH (Bitfield-Mask: 0x03) */ - -/* ------------------------------ RFPT_RFPT_LEN_REG ----------------------------- */ -#define RFPT_RFPT_LEN_REG_RFPT_LEN_Pos (0UL) /*!< RFPT RFPT_LEN_REG: RFPT_LEN (Bit 0) */ -#define RFPT_RFPT_LEN_REG_RFPT_LEN_Msk (0x7fffUL) /*!< RFPT RFPT_LEN_REG: RFPT_LEN (Bitfield-Mask: 0x7fff) */ - -/* ----------------------------- RFPT_RFPT_STAT_REG ----------------------------- */ -#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Pos (0UL) /*!< RFPT RFPT_STAT_REG: RFPT_ACTIVE (Bit 0) */ -#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Msk (0x1UL) /*!< RFPT RFPT_STAT_REG: RFPT_ACTIVE (Bitfield-Mask: 0x01) */ -#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Pos (1UL) /*!< RFPT RFPT_STAT_REG: RFPT_OFLOW_STK (Bit 1) */ -#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Msk (0x2UL) /*!< RFPT RFPT_STAT_REG: RFPT_OFLOW_STK (Bitfield-Mask: 0x01) */ - -/* --------------------------- RFPT_RFPT_CRV_ADDRL_REG -------------------------- */ -#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Pos (2UL) /*!< RFPT RFPT_CRV_ADDRL_REG: RFPT_CRV_ADDRL (Bit 2) */ -#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Msk (0xfffcUL) /*!< RFPT RFPT_CRV_ADDRL_REG: RFPT_CRV_ADDRL (Bitfield-Mask: 0x3fff) */ - -/* --------------------------- RFPT_RFPT_CRV_ADDRH_REG -------------------------- */ -#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Pos (0UL) /*!< RFPT RFPT_CRV_ADDRH_REG: RFPT_CRV_ADDRH (Bit 0) */ -#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Msk (0x3UL) /*!< RFPT RFPT_CRV_ADDRH_REG: RFPT_CRV_ADDRH (Bitfield-Mask: 0x03) */ - -/* ---------------------------- RFPT_RFPT_CRV_LEN_REG --------------------------- */ -#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Pos (0UL) /*!< RFPT RFPT_CRV_LEN_REG: RFPT_CRV_LEN (Bit 0) */ -#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Msk (0x7fffUL) /*!< RFPT RFPT_CRV_LEN_REG: RFPT_CRV_LEN (Bitfield-Mask: 0x7fff) */ - - -/* ================================================================================ */ -/* ================ struct 'SPI' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------ SPI_SPI_CTRL_REG ------------------------------ */ -#define SPI_SPI_CTRL_REG_SPI_ON_Pos (0UL) /*!< SPI SPI_CTRL_REG: SPI_ON (Bit 0) */ -#define SPI_SPI_CTRL_REG_SPI_ON_Msk (0x1UL) /*!< SPI SPI_CTRL_REG: SPI_ON (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_PHA_Pos (1UL) /*!< SPI SPI_CTRL_REG: SPI_PHA (Bit 1) */ -#define SPI_SPI_CTRL_REG_SPI_PHA_Msk (0x2UL) /*!< SPI SPI_CTRL_REG: SPI_PHA (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_POL_Pos (2UL) /*!< SPI SPI_CTRL_REG: SPI_POL (Bit 2) */ -#define SPI_SPI_CTRL_REG_SPI_POL_Msk (0x4UL) /*!< SPI SPI_CTRL_REG: SPI_POL (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_CLK_Pos (3UL) /*!< SPI SPI_CTRL_REG: SPI_CLK (Bit 3) */ -#define SPI_SPI_CTRL_REG_SPI_CLK_Msk (0x18UL) /*!< SPI SPI_CTRL_REG: SPI_CLK (Bitfield-Mask: 0x03) */ -#define SPI_SPI_CTRL_REG_SPI_DO_Pos (5UL) /*!< SPI SPI_CTRL_REG: SPI_DO (Bit 5) */ -#define SPI_SPI_CTRL_REG_SPI_DO_Msk (0x20UL) /*!< SPI SPI_CTRL_REG: SPI_DO (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_SMN_Pos (6UL) /*!< SPI SPI_CTRL_REG: SPI_SMN (Bit 6) */ -#define SPI_SPI_CTRL_REG_SPI_SMN_Msk (0x40UL) /*!< SPI SPI_CTRL_REG: SPI_SMN (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_WORD_Pos (7UL) /*!< SPI SPI_CTRL_REG: SPI_WORD (Bit 7) */ -#define SPI_SPI_CTRL_REG_SPI_WORD_Msk (0x180UL) /*!< SPI SPI_CTRL_REG: SPI_WORD (Bitfield-Mask: 0x03) */ -#define SPI_SPI_CTRL_REG_SPI_RST_Pos (9UL) /*!< SPI SPI_CTRL_REG: SPI_RST (Bit 9) */ -#define SPI_SPI_CTRL_REG_SPI_RST_Msk (0x200UL) /*!< SPI SPI_CTRL_REG: SPI_RST (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos (10UL) /*!< SPI SPI_CTRL_REG: SPI_FORCE_DO (Bit 10) */ -#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL) /*!< SPI SPI_CTRL_REG: SPI_FORCE_DO (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_TXH_Pos (11UL) /*!< SPI SPI_CTRL_REG: SPI_TXH (Bit 11) */ -#define SPI_SPI_CTRL_REG_SPI_TXH_Msk (0x800UL) /*!< SPI SPI_CTRL_REG: SPI_TXH (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_DI_Pos (12UL) /*!< SPI SPI_CTRL_REG: SPI_DI (Bit 12) */ -#define SPI_SPI_CTRL_REG_SPI_DI_Msk (0x1000UL) /*!< SPI SPI_CTRL_REG: SPI_DI (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos (13UL) /*!< SPI SPI_CTRL_REG: SPI_INT_BIT (Bit 13) */ -#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk (0x2000UL) /*!< SPI SPI_CTRL_REG: SPI_INT_BIT (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_MINT_Pos (14UL) /*!< SPI SPI_CTRL_REG: SPI_MINT (Bit 14) */ -#define SPI_SPI_CTRL_REG_SPI_MINT_Msk (0x4000UL) /*!< SPI SPI_CTRL_REG: SPI_MINT (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos (15UL) /*!< SPI SPI_CTRL_REG: SPI_EN_CTRL (Bit 15) */ -#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk (0x8000UL) /*!< SPI SPI_CTRL_REG: SPI_EN_CTRL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SPI_SPI_RX_TX_REG0 ----------------------------- */ -#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Pos (0UL) /*!< SPI SPI_RX_TX_REG0: SPI_DATA0 (Bit 0) */ -#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Msk (0xffffUL) /*!< SPI SPI_RX_TX_REG0: SPI_DATA0 (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- SPI_SPI_RX_TX_REG1 ----------------------------- */ -#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Pos (0UL) /*!< SPI SPI_RX_TX_REG1: SPI_DATA1 (Bit 0) */ -#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Msk (0xffffUL) /*!< SPI SPI_RX_TX_REG1: SPI_DATA1 (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- SPI_SPI_CLEAR_INT_REG --------------------------- */ -#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL) /*!< SPI SPI_CLEAR_INT_REG: SPI_CLEAR_INT (Bit 0) */ -#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffUL) /*!< SPI SPI_CLEAR_INT_REG: SPI_CLEAR_INT (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ SPI_SPI_CTRL_REG1 ----------------------------- */ -#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Pos (0UL) /*!< SPI SPI_CTRL_REG1: SPI_FIFO_MODE (Bit 0) */ -#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Msk (0x3UL) /*!< SPI SPI_CTRL_REG1: SPI_FIFO_MODE (Bitfield-Mask: 0x03) */ -#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Pos (2UL) /*!< SPI SPI_CTRL_REG1: SPI_PRIORITY (Bit 2) */ -#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Msk (0x4UL) /*!< SPI SPI_CTRL_REG1: SPI_PRIORITY (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG1_SPI_BUSY_Pos (3UL) /*!< SPI SPI_CTRL_REG1: SPI_BUSY (Bit 3) */ -#define SPI_SPI_CTRL_REG1_SPI_BUSY_Msk (0x8UL) /*!< SPI SPI_CTRL_REG1: SPI_BUSY (Bitfield-Mask: 0x01) */ -#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Pos (4UL) /*!< SPI SPI_CTRL_REG1: SPI_9BIT_VAL (Bit 4) */ -#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Msk (0x10UL) /*!< SPI SPI_CTRL_REG1: SPI_9BIT_VAL (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'SPI2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- SPI2_SPI2_CTRL_REG ----------------------------- */ -#define SPI2_SPI2_CTRL_REG_SPI_ON_Pos (0UL) /*!< SPI2 SPI2_CTRL_REG: SPI_ON (Bit 0) */ -#define SPI2_SPI2_CTRL_REG_SPI_ON_Msk (0x1UL) /*!< SPI2 SPI2_CTRL_REG: SPI_ON (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_PHA_Pos (1UL) /*!< SPI2 SPI2_CTRL_REG: SPI_PHA (Bit 1) */ -#define SPI2_SPI2_CTRL_REG_SPI_PHA_Msk (0x2UL) /*!< SPI2 SPI2_CTRL_REG: SPI_PHA (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_POL_Pos (2UL) /*!< SPI2 SPI2_CTRL_REG: SPI_POL (Bit 2) */ -#define SPI2_SPI2_CTRL_REG_SPI_POL_Msk (0x4UL) /*!< SPI2 SPI2_CTRL_REG: SPI_POL (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_CLK_Pos (3UL) /*!< SPI2 SPI2_CTRL_REG: SPI_CLK (Bit 3) */ -#define SPI2_SPI2_CTRL_REG_SPI_CLK_Msk (0x18UL) /*!< SPI2 SPI2_CTRL_REG: SPI_CLK (Bitfield-Mask: 0x03) */ -#define SPI2_SPI2_CTRL_REG_SPI_DO_Pos (5UL) /*!< SPI2 SPI2_CTRL_REG: SPI_DO (Bit 5) */ -#define SPI2_SPI2_CTRL_REG_SPI_DO_Msk (0x20UL) /*!< SPI2 SPI2_CTRL_REG: SPI_DO (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_SMN_Pos (6UL) /*!< SPI2 SPI2_CTRL_REG: SPI_SMN (Bit 6) */ -#define SPI2_SPI2_CTRL_REG_SPI_SMN_Msk (0x40UL) /*!< SPI2 SPI2_CTRL_REG: SPI_SMN (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_WORD_Pos (7UL) /*!< SPI2 SPI2_CTRL_REG: SPI_WORD (Bit 7) */ -#define SPI2_SPI2_CTRL_REG_SPI_WORD_Msk (0x180UL) /*!< SPI2 SPI2_CTRL_REG: SPI_WORD (Bitfield-Mask: 0x03) */ -#define SPI2_SPI2_CTRL_REG_SPI_RST_Pos (9UL) /*!< SPI2 SPI2_CTRL_REG: SPI_RST (Bit 9) */ -#define SPI2_SPI2_CTRL_REG_SPI_RST_Msk (0x200UL) /*!< SPI2 SPI2_CTRL_REG: SPI_RST (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos (10UL) /*!< SPI2 SPI2_CTRL_REG: SPI_FORCE_DO (Bit 10) */ -#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL) /*!< SPI2 SPI2_CTRL_REG: SPI_FORCE_DO (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_TXH_Pos (11UL) /*!< SPI2 SPI2_CTRL_REG: SPI_TXH (Bit 11) */ -#define SPI2_SPI2_CTRL_REG_SPI_TXH_Msk (0x800UL) /*!< SPI2 SPI2_CTRL_REG: SPI_TXH (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_DI_Pos (12UL) /*!< SPI2 SPI2_CTRL_REG: SPI_DI (Bit 12) */ -#define SPI2_SPI2_CTRL_REG_SPI_DI_Msk (0x1000UL) /*!< SPI2 SPI2_CTRL_REG: SPI_DI (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos (13UL) /*!< SPI2 SPI2_CTRL_REG: SPI_INT_BIT (Bit 13) */ -#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk (0x2000UL) /*!< SPI2 SPI2_CTRL_REG: SPI_INT_BIT (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_MINT_Pos (14UL) /*!< SPI2 SPI2_CTRL_REG: SPI_MINT (Bit 14) */ -#define SPI2_SPI2_CTRL_REG_SPI_MINT_Msk (0x4000UL) /*!< SPI2 SPI2_CTRL_REG: SPI_MINT (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos (15UL) /*!< SPI2 SPI2_CTRL_REG: SPI_EN_CTRL (Bit 15) */ -#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk (0x8000UL) /*!< SPI2 SPI2_CTRL_REG: SPI_EN_CTRL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- SPI2_SPI2_RX_TX_REG0 ---------------------------- */ -#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Pos (0UL) /*!< SPI2 SPI2_RX_TX_REG0: SPI_DATA0 (Bit 0) */ -#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Msk (0xffffUL) /*!< SPI2 SPI2_RX_TX_REG0: SPI_DATA0 (Bitfield-Mask: 0xffff) */ - -/* ---------------------------- SPI2_SPI2_RX_TX_REG1 ---------------------------- */ -#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Pos (0UL) /*!< SPI2 SPI2_RX_TX_REG1: SPI_DATA1 (Bit 0) */ -#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Msk (0xffffUL) /*!< SPI2 SPI2_RX_TX_REG1: SPI_DATA1 (Bitfield-Mask: 0xffff) */ - -/* --------------------------- SPI2_SPI2_CLEAR_INT_REG -------------------------- */ -#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL) /*!< SPI2 SPI2_CLEAR_INT_REG: SPI_CLEAR_INT (Bit 0) */ -#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffUL) /*!< SPI2 SPI2_CLEAR_INT_REG: SPI_CLEAR_INT (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- SPI2_SPI2_CTRL_REG1 ---------------------------- */ -#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Pos (0UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_FIFO_MODE (Bit 0) */ -#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Msk (0x3UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_FIFO_MODE (Bitfield-Mask: 0x03) */ -#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Pos (2UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_PRIORITY (Bit 2) */ -#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Msk (0x4UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_PRIORITY (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Pos (3UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_BUSY (Bit 3) */ -#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Msk (0x8UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_BUSY (Bitfield-Mask: 0x01) */ -#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Pos (4UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_9BIT_VAL (Bit 4) */ -#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Msk (0x10UL) /*!< SPI2 SPI2_CTRL_REG1: SPI_9BIT_VAL (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'TIMER1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------- TIMER1_CAPTIM_CTRL_REG --------------------------- */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Pos (0UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_EN (Bit 0) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Msk (0x1UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_EN (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_ONESHOT_MODE_EN (Bit 1) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_COUNT_DOWN_EN (Bit 2) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN1_EVENT_FALL_EN (Bit 3) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN2_EVENT_FALL_EN (Bit 4) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Pos (5UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IRQ_EN (Bit 5) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk (0x20UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_IRQ_EN (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_FREE_RUN_MODE_EN (Bit 6) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Pos (7UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_SYS_CLK_EN (Bit 7) */ -#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIMER1 CAPTIM_CTRL_REG: CAPTIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------- TIMER1_CAPTIM_TIMER_VAL_REG ------------------------ */ -#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Pos (0UL) /*!< TIMER1 CAPTIM_TIMER_VAL_REG: CAPTIM_TIMER_VALUE (Bit 0) */ -#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Msk (0xffffUL) /*!< TIMER1 CAPTIM_TIMER_VAL_REG: CAPTIM_TIMER_VALUE (Bitfield-Mask: 0xffff) */ - -/* -------------------------- TIMER1_CAPTIM_STATUS_REG -------------------------- */ -#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Pos (0UL) /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN1_STATE (Bit 0) */ -#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Msk (0x1UL) /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN1_STATE (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Pos (1UL) /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN2_STATE (Bit 1) */ -#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Msk (0x2UL) /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN2_STATE (Bitfield-Mask: 0x01) */ -#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Pos (2UL) /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_ONESHOT_PHASE (Bit 2) */ -#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIMER1 CAPTIM_STATUS_REG: CAPTIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ - -/* ------------------------ TIMER1_CAPTIM_GPIO1_CONF_REG ------------------------ */ -#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Pos (0UL) /*!< TIMER1 CAPTIM_GPIO1_CONF_REG: CAPTIM_GPIO1_CONF (Bit 0) */ -#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIMER1 CAPTIM_GPIO1_CONF_REG: CAPTIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ - -/* ------------------------ TIMER1_CAPTIM_GPIO2_CONF_REG ------------------------ */ -#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Pos (0UL) /*!< TIMER1 CAPTIM_GPIO2_CONF_REG: CAPTIM_GPIO2_CONF (Bit 0) */ -#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIMER1 CAPTIM_GPIO2_CONF_REG: CAPTIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ - -/* -------------------------- TIMER1_CAPTIM_RELOAD_REG -------------------------- */ -#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Pos (0UL) /*!< TIMER1 CAPTIM_RELOAD_REG: CAPTIM_RELOAD (Bit 0) */ -#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Msk (0xffffUL) /*!< TIMER1 CAPTIM_RELOAD_REG: CAPTIM_RELOAD (Bitfield-Mask: 0xffff) */ - -/* ------------------------- TIMER1_CAPTIM_SHOTWIDTH_REG ------------------------ */ -#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Pos (0UL) /*!< TIMER1 CAPTIM_SHOTWIDTH_REG: CAPTIM_SHOTWIDTH (Bit 0) */ -#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Msk (0xffffUL) /*!< TIMER1 CAPTIM_SHOTWIDTH_REG: CAPTIM_SHOTWIDTH (Bitfield-Mask: 0xffff) */ - -/* ------------------------- TIMER1_CAPTIM_PRESCALER_REG ------------------------ */ -#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Pos (0UL) /*!< TIMER1 CAPTIM_PRESCALER_REG: CAPTIM_PRESCALER (Bit 0) */ -#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Msk (0xffffUL) /*!< TIMER1 CAPTIM_PRESCALER_REG: CAPTIM_PRESCALER (Bitfield-Mask: 0xffff) */ - -/* ----------------------- TIMER1_CAPTIM_CAPTURE_GPIO1_REG ---------------------- */ -#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_GPIO1_REG: CAPTIM_CAPTURE_GPIO1 (Bit 0) */ -#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_GPIO1_REG: CAPTIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffff) */ - -/* ----------------------- TIMER1_CAPTIM_CAPTURE_GPIO2_REG ---------------------- */ -#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_GPIO2_REG: CAPTIM_CAPTURE_GPIO2 (Bit 0) */ -#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_GPIO2_REG: CAPTIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffff) */ - -/* ----------------------- TIMER1_CAPTIM_PRESCALER_VAL_REG ---------------------- */ -#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Pos (0UL) /*!< TIMER1 CAPTIM_PRESCALER_VAL_REG: CAPTIM_PRESCALER_VAL (Bit 0) */ -#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Msk (0xffffUL) /*!< TIMER1 CAPTIM_PRESCALER_VAL_REG: CAPTIM_PRESCALER_VAL (Bitfield-Mask: 0xffff) */ - -/* ------------------------- TIMER1_CAPTIM_PWM_FREQ_REG ------------------------- */ -#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Pos (0UL) /*!< TIMER1 CAPTIM_PWM_FREQ_REG: CAPTIM_PWM_FREQ (Bit 0) */ -#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Msk (0xffffUL) /*!< TIMER1 CAPTIM_PWM_FREQ_REG: CAPTIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ - -/* -------------------------- TIMER1_CAPTIM_PWM_DC_REG -------------------------- */ -#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Pos (0UL) /*!< TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bit 0) */ -#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Msk (0xffffUL) /*!< TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bitfield-Mask: 0xffff) */ - -/* ------------------------ TIMER1_CAPTIM_TIMER_HVAL_REG ------------------------ */ -#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Pos (0UL) /*!< TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bit 0) */ -#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Msk (0xffffUL) /*!< TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bitfield-Mask: 0xffff) */ - -/* ------------------------ TIMER1_CAPTIM_RELOAD_HIGH_REG ----------------------- */ -#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Pos (0UL) /*!< TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bit 0) */ -#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Msk (0xffffUL) /*!< TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bitfield-Mask: 0xffff) */ - -/* -------------------- TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG -------------------- */ -#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bit 0) */ -#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bitfield-Mask: 0xffff) */ - -/* -------------------- TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG -------------------- */ -#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bit 0) */ -#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bitfield-Mask: 0xffff) */ - -/* ---------------------- TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG ---------------------- */ -#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Pos (0UL) /*!< TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bit 0) */ -#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Msk (0xffffUL) /*!< TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'TRNG' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- TRNG_TRNG_CTRL_REG ----------------------------- */ -#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos (0UL) /*!< TRNG TRNG_CTRL_REG: TRNG_ENABLE (Bit 0) */ -#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk (0x1UL) /*!< TRNG TRNG_CTRL_REG: TRNG_ENABLE (Bitfield-Mask: 0x01) */ -#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Pos (1UL) /*!< TRNG TRNG_CTRL_REG: TRNG_MODE (Bit 1) */ -#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Msk (0x2UL) /*!< TRNG TRNG_CTRL_REG: TRNG_MODE (Bitfield-Mask: 0x01) */ - -/* ---------------------------- TRNG_TRNG_FIFOLVL_REG --------------------------- */ -#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos (0UL) /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOLVL (Bit 0) */ -#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk (0x1fUL) /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOLVL (Bitfield-Mask: 0x1f) */ -#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos (5UL) /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOFULL (Bit 5) */ -#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk (0x20UL) /*!< TRNG TRNG_FIFOLVL_REG: TRNG_FIFOFULL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ TRNG_TRNG_VER_REG ----------------------------- */ -#define TRNG_TRNG_VER_REG_TRNG_SVN_Pos (0UL) /*!< TRNG TRNG_VER_REG: TRNG_SVN (Bit 0) */ -#define TRNG_TRNG_VER_REG_TRNG_SVN_Msk (0xffffUL) /*!< TRNG TRNG_VER_REG: TRNG_SVN (Bitfield-Mask: 0xffff) */ -#define TRNG_TRNG_VER_REG_TRNG_MIN_Pos (16UL) /*!< TRNG TRNG_VER_REG: TRNG_MIN (Bit 16) */ -#define TRNG_TRNG_VER_REG_TRNG_MIN_Msk (0xff0000UL) /*!< TRNG TRNG_VER_REG: TRNG_MIN (Bitfield-Mask: 0xff) */ -#define TRNG_TRNG_VER_REG_TRNG_MAJ_Pos (24UL) /*!< TRNG TRNG_VER_REG: TRNG_MAJ (Bit 24) */ -#define TRNG_TRNG_VER_REG_TRNG_MAJ_Msk (0xff000000UL) /*!< TRNG TRNG_VER_REG: TRNG_MAJ (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'UART' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- UART_UART_RBR_THR_DLL_REG ------------------------- */ -#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< UART UART_RBR_THR_DLL_REG: RBR_THR_DLL (Bit 0) */ -#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< UART UART_RBR_THR_DLL_REG: RBR_THR_DLL (Bitfield-Mask: 0xff) */ - -/* ---------------------------- UART_UART_IER_DLH_REG --------------------------- */ -#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Pos (0UL) /*!< UART UART_IER_DLH_REG: ERBFI_dlh0 (Bit 0) */ -#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Msk (0x1UL) /*!< UART UART_IER_DLH_REG: ERBFI_dlh0 (Bitfield-Mask: 0x01) */ -#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos (1UL) /*!< UART UART_IER_DLH_REG: ETBEI_dlh1 (Bit 1) */ -#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Msk (0x2UL) /*!< UART UART_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01) */ -#define UART_UART_IER_DLH_REG_ELSI_dhl2_Pos (2UL) /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bit 2) */ -#define UART_UART_IER_DLH_REG_ELSI_dhl2_Msk (0x4UL) /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01) */ -#define UART_UART_IER_DLH_REG_EDSSI_dlh3_Pos (3UL) /*!< UART UART_IER_DLH_REG: EDSSI_dlh3 (Bit 3) */ -#define UART_UART_IER_DLH_REG_EDSSI_dlh3_Msk (0x8UL) /*!< UART UART_IER_DLH_REG: EDSSI_dlh3 (Bitfield-Mask: 0x01) */ -#define UART_UART_IER_DLH_REG_dlh6_4_Pos (4UL) /*!< UART UART_IER_DLH_REG: dlh6_4 (Bit 4) */ -#define UART_UART_IER_DLH_REG_dlh6_4_Msk (0x70UL) /*!< UART UART_IER_DLH_REG: dlh6_4 (Bitfield-Mask: 0x07) */ -#define UART_UART_IER_DLH_REG_PTIME_dlh7_Pos (7UL) /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bit 7) */ -#define UART_UART_IER_DLH_REG_PTIME_dlh7_Msk (0x80UL) /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01) */ - -/* ---------------------------- UART_UART_IIR_FCR_REG --------------------------- */ -#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< UART UART_IIR_FCR_REG: IIR_FCR (Bit 0) */ -#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk (0xffffUL) /*!< UART UART_IIR_FCR_REG: IIR_FCR (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ UART_UART_LCR_REG ----------------------------- */ -#define UART_UART_LCR_REG_UART_DLS_Pos (0UL) /*!< UART UART_LCR_REG: UART_DLS (Bit 0) */ -#define UART_UART_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART UART_LCR_REG: UART_DLS (Bitfield-Mask: 0x03) */ -#define UART_UART_LCR_REG_UART_STOP_Pos (2UL) /*!< UART UART_LCR_REG: UART_STOP (Bit 2) */ -#define UART_UART_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART UART_LCR_REG: UART_STOP (Bitfield-Mask: 0x01) */ -#define UART_UART_LCR_REG_UART_PEN_Pos (3UL) /*!< UART UART_LCR_REG: UART_PEN (Bit 3) */ -#define UART_UART_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART UART_LCR_REG: UART_PEN (Bitfield-Mask: 0x01) */ -#define UART_UART_LCR_REG_UART_EPS_Pos (4UL) /*!< UART UART_LCR_REG: UART_EPS (Bit 4) */ -#define UART_UART_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART UART_LCR_REG: UART_EPS (Bitfield-Mask: 0x01) */ -#define UART_UART_LCR_REG_UART_BC_Pos (6UL) /*!< UART UART_LCR_REG: UART_BC (Bit 6) */ -#define UART_UART_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART UART_LCR_REG: UART_BC (Bitfield-Mask: 0x01) */ -#define UART_UART_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART UART_LCR_REG: UART_DLAB (Bit 7) */ -#define UART_UART_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART UART_LCR_REG: UART_DLAB (Bitfield-Mask: 0x01) */ - -/* ------------------------------ UART_UART_MCR_REG ----------------------------- */ -#define UART_UART_MCR_REG_UART_OUT1_Pos (2UL) /*!< UART UART_MCR_REG: UART_OUT1 (Bit 2) */ -#define UART_UART_MCR_REG_UART_OUT1_Msk (0x4UL) /*!< UART UART_MCR_REG: UART_OUT1 (Bitfield-Mask: 0x01) */ -#define UART_UART_MCR_REG_UART_OUT2_Pos (3UL) /*!< UART UART_MCR_REG: UART_OUT2 (Bit 3) */ -#define UART_UART_MCR_REG_UART_OUT2_Msk (0x8UL) /*!< UART UART_MCR_REG: UART_OUT2 (Bitfield-Mask: 0x01) */ -#define UART_UART_MCR_REG_UART_LB_Pos (4UL) /*!< UART UART_MCR_REG: UART_LB (Bit 4) */ -#define UART_UART_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART UART_MCR_REG: UART_LB (Bitfield-Mask: 0x01) */ -#define UART_UART_MCR_REG_UART_SIRE_Pos (6UL) /*!< UART UART_MCR_REG: UART_SIRE (Bit 6) */ -#define UART_UART_MCR_REG_UART_SIRE_Msk (0x40UL) /*!< UART UART_MCR_REG: UART_SIRE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ UART_UART_LSR_REG ----------------------------- */ -#define UART_UART_LSR_REG_UART_DR_Pos (0UL) /*!< UART UART_LSR_REG: UART_DR (Bit 0) */ -#define UART_UART_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART UART_LSR_REG: UART_DR (Bitfield-Mask: 0x01) */ -#define UART_UART_LSR_REG_UART_OE_Pos (1UL) /*!< UART UART_LSR_REG: UART_OE (Bit 1) */ -#define UART_UART_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART UART_LSR_REG: UART_OE (Bitfield-Mask: 0x01) */ -#define UART_UART_LSR_REG_UART_PE_Pos (2UL) /*!< UART UART_LSR_REG: UART_PE (Bit 2) */ -#define UART_UART_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART UART_LSR_REG: UART_PE (Bitfield-Mask: 0x01) */ -#define UART_UART_LSR_REG_UART_FE_Pos (3UL) /*!< UART UART_LSR_REG: UART_FE (Bit 3) */ -#define UART_UART_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART UART_LSR_REG: UART_FE (Bitfield-Mask: 0x01) */ -#define UART_UART_LSR_REG_UART_BI_Pos (4UL) /*!< UART UART_LSR_REG: UART_BI (Bit 4) */ -#define UART_UART_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART UART_LSR_REG: UART_BI (Bitfield-Mask: 0x01) */ -#define UART_UART_LSR_REG_UART_THRE_Pos (5UL) /*!< UART UART_LSR_REG: UART_THRE (Bit 5) */ -#define UART_UART_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART UART_LSR_REG: UART_THRE (Bitfield-Mask: 0x01) */ -#define UART_UART_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART UART_LSR_REG: UART_TEMT (Bit 6) */ -#define UART_UART_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART UART_LSR_REG: UART_TEMT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ UART_UART_SCR_REG ----------------------------- */ -#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL) /*!< UART UART_SCR_REG: UART_SCRATCH_PAD (Bit 0) */ -#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL) /*!< UART UART_SCR_REG: UART_SCRATCH_PAD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ UART_UART_USR_REG ----------------------------- */ -#define UART_UART_USR_REG_UART_BUSY_Pos (0UL) /*!< UART UART_USR_REG: UART_BUSY (Bit 0) */ -#define UART_UART_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART UART_USR_REG: UART_BUSY (Bitfield-Mask: 0x01) */ - -/* ------------------------------ UART_UART_SRR_REG ----------------------------- */ -#define UART_UART_SRR_REG_UART_UR_Pos (0UL) /*!< UART UART_SRR_REG: UART_UR (Bit 0) */ -#define UART_UART_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART UART_SRR_REG: UART_UR (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART_UART_SBCR_REG ----------------------------- */ -#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART UART_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bit 0) */ -#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART UART_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART_UART_DMASA_REG ---------------------------- */ -#define UART_UART_DMASA_REG_DMASA_Pos (0UL) /*!< UART UART_DMASA_REG: DMASA (Bit 0) */ -#define UART_UART_DMASA_REG_DMASA_Msk (0x1UL) /*!< UART UART_DMASA_REG: DMASA (Bitfield-Mask: 0x01) */ - -/* ------------------------------ UART_UART_DLF_REG ----------------------------- */ -#define UART_UART_DLF_REG_UART_DLF_Pos (0UL) /*!< UART UART_DLF_REG: UART_DLF (Bit 0) */ -#define UART_UART_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART UART_DLF_REG: UART_DLF (Bitfield-Mask: 0x0f) */ - -/* ------------------------------ UART_UART_CPR_REG ----------------------------- */ -#define UART_UART_CPR_REG_CPR_Pos (0UL) /*!< UART UART_CPR_REG: CPR (Bit 0) */ -#define UART_UART_CPR_REG_CPR_Msk (0xffffUL) /*!< UART UART_CPR_REG: CPR (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ UART_UART_UCV_REG ----------------------------- */ -#define UART_UART_UCV_REG_UCV_Pos (0UL) /*!< UART UART_UCV_REG: UCV (Bit 0) */ -#define UART_UART_UCV_REG_UCV_Msk (0xffffUL) /*!< UART UART_UCV_REG: UCV (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ UART_UART_CTR_REG ----------------------------- */ -#define UART_UART_CTR_REG_CTR_Pos (0UL) /*!< UART UART_CTR_REG: CTR (Bit 0) */ -#define UART_UART_CTR_REG_CTR_Msk (0xffffUL) /*!< UART UART_CTR_REG: CTR (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'UART2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------- UART2_UART2_RBR_THR_DLL_REG ------------------------ */ -#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< UART2 UART2_RBR_THR_DLL_REG: RBR_THR_DLL (Bit 0) */ -#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< UART2 UART2_RBR_THR_DLL_REG: RBR_THR_DLL (Bitfield-Mask: 0xff) */ - -/* --------------------------- UART2_UART2_IER_DLH_REG -------------------------- */ -#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Pos (0UL) /*!< UART2 UART2_IER_DLH_REG: ERBFI_dlh0 (Bit 0) */ -#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Msk (0x1UL) /*!< UART2 UART2_IER_DLH_REG: ERBFI_dlh0 (Bitfield-Mask: 0x01) */ -#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Pos (1UL) /*!< UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bit 1) */ -#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Msk (0x2UL) /*!< UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01) */ -#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Pos (2UL) /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bit 2) */ -#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Msk (0x4UL) /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01) */ -#define UART2_UART2_IER_DLH_REG_EDSSI_dlh3_Pos (3UL) /*!< UART2 UART2_IER_DLH_REG: EDSSI_dlh3 (Bit 3) */ -#define UART2_UART2_IER_DLH_REG_EDSSI_dlh3_Msk (0x8UL) /*!< UART2 UART2_IER_DLH_REG: EDSSI_dlh3 (Bitfield-Mask: 0x01) */ -#define UART2_UART2_IER_DLH_REG_dlh6_4_Pos (4UL) /*!< UART2 UART2_IER_DLH_REG: dlh6_4 (Bit 4) */ -#define UART2_UART2_IER_DLH_REG_dlh6_4_Msk (0x70UL) /*!< UART2 UART2_IER_DLH_REG: dlh6_4 (Bitfield-Mask: 0x07) */ -#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Pos (7UL) /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bit 7) */ -#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Msk (0x80UL) /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01) */ - -/* --------------------------- UART2_UART2_IIR_FCR_REG -------------------------- */ -#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< UART2 UART2_IIR_FCR_REG: IIR_FCR (Bit 0) */ -#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk (0xffffUL) /*!< UART2 UART2_IIR_FCR_REG: IIR_FCR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- UART2_UART2_LCR_REG ---------------------------- */ -#define UART2_UART2_LCR_REG_UART_DLS_Pos (0UL) /*!< UART2 UART2_LCR_REG: UART_DLS (Bit 0) */ -#define UART2_UART2_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART2 UART2_LCR_REG: UART_DLS (Bitfield-Mask: 0x03) */ -#define UART2_UART2_LCR_REG_UART_STOP_Pos (2UL) /*!< UART2 UART2_LCR_REG: UART_STOP (Bit 2) */ -#define UART2_UART2_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART2 UART2_LCR_REG: UART_STOP (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LCR_REG_UART_PEN_Pos (3UL) /*!< UART2 UART2_LCR_REG: UART_PEN (Bit 3) */ -#define UART2_UART2_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART2 UART2_LCR_REG: UART_PEN (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LCR_REG_UART_EPS_Pos (4UL) /*!< UART2 UART2_LCR_REG: UART_EPS (Bit 4) */ -#define UART2_UART2_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART2 UART2_LCR_REG: UART_EPS (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LCR_REG_UART_BC_Pos (6UL) /*!< UART2 UART2_LCR_REG: UART_BC (Bit 6) */ -#define UART2_UART2_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART2 UART2_LCR_REG: UART_BC (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART2 UART2_LCR_REG: UART_DLAB (Bit 7) */ -#define UART2_UART2_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART2 UART2_LCR_REG: UART_DLAB (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_MCR_REG ---------------------------- */ -#define UART2_UART2_MCR_REG_UART_RTS_Pos (1UL) /*!< UART2 UART2_MCR_REG: UART_RTS (Bit 1) */ -#define UART2_UART2_MCR_REG_UART_RTS_Msk (0x2UL) /*!< UART2 UART2_MCR_REG: UART_RTS (Bitfield-Mask: 0x01) */ -#define UART2_UART2_MCR_REG_UART_OUT1_Pos (2UL) /*!< UART2 UART2_MCR_REG: UART_OUT1 (Bit 2) */ -#define UART2_UART2_MCR_REG_UART_OUT1_Msk (0x4UL) /*!< UART2 UART2_MCR_REG: UART_OUT1 (Bitfield-Mask: 0x01) */ -#define UART2_UART2_MCR_REG_UART_OUT2_Pos (3UL) /*!< UART2 UART2_MCR_REG: UART_OUT2 (Bit 3) */ -#define UART2_UART2_MCR_REG_UART_OUT2_Msk (0x8UL) /*!< UART2 UART2_MCR_REG: UART_OUT2 (Bitfield-Mask: 0x01) */ -#define UART2_UART2_MCR_REG_UART_LB_Pos (4UL) /*!< UART2 UART2_MCR_REG: UART_LB (Bit 4) */ -#define UART2_UART2_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART2 UART2_MCR_REG: UART_LB (Bitfield-Mask: 0x01) */ -#define UART2_UART2_MCR_REG_UART_AFCE_Pos (5UL) /*!< UART2 UART2_MCR_REG: UART_AFCE (Bit 5) */ -#define UART2_UART2_MCR_REG_UART_AFCE_Msk (0x20UL) /*!< UART2 UART2_MCR_REG: UART_AFCE (Bitfield-Mask: 0x01) */ -#define UART2_UART2_MCR_REG_UART_SIRE_Pos (6UL) /*!< UART2 UART2_MCR_REG: UART_SIRE (Bit 6) */ -#define UART2_UART2_MCR_REG_UART_SIRE_Msk (0x40UL) /*!< UART2 UART2_MCR_REG: UART_SIRE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_LSR_REG ---------------------------- */ -#define UART2_UART2_LSR_REG_UART_DR_Pos (0UL) /*!< UART2 UART2_LSR_REG: UART_DR (Bit 0) */ -#define UART2_UART2_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART2 UART2_LSR_REG: UART_DR (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LSR_REG_UART_OE_Pos (1UL) /*!< UART2 UART2_LSR_REG: UART_OE (Bit 1) */ -#define UART2_UART2_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART2 UART2_LSR_REG: UART_OE (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LSR_REG_UART_PE_Pos (2UL) /*!< UART2 UART2_LSR_REG: UART_PE (Bit 2) */ -#define UART2_UART2_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART2 UART2_LSR_REG: UART_PE (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LSR_REG_UART_FE_Pos (3UL) /*!< UART2 UART2_LSR_REG: UART_FE (Bit 3) */ -#define UART2_UART2_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART2 UART2_LSR_REG: UART_FE (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LSR_REG_UART_BI_Pos (4UL) /*!< UART2 UART2_LSR_REG: UART_BI (Bit 4) */ -#define UART2_UART2_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART2 UART2_LSR_REG: UART_BI (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LSR_REG_UART_THRE_Pos (5UL) /*!< UART2 UART2_LSR_REG: UART_THRE (Bit 5) */ -#define UART2_UART2_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART2 UART2_LSR_REG: UART_THRE (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART2 UART2_LSR_REG: UART_TEMT (Bit 6) */ -#define UART2_UART2_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART2 UART2_LSR_REG: UART_TEMT (Bitfield-Mask: 0x01) */ -#define UART2_UART2_LSR_REG_UART_RFE_Pos (7UL) /*!< UART2 UART2_LSR_REG: UART_RFE (Bit 7) */ -#define UART2_UART2_LSR_REG_UART_RFE_Msk (0x80UL) /*!< UART2 UART2_LSR_REG: UART_RFE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_MSR_REG ---------------------------- */ -#define UART2_UART2_MSR_REG_UART_DCTS_Pos (0UL) /*!< UART2 UART2_MSR_REG: UART_DCTS (Bit 0) */ -#define UART2_UART2_MSR_REG_UART_DCTS_Msk (0x1UL) /*!< UART2 UART2_MSR_REG: UART_DCTS (Bitfield-Mask: 0x01) */ -#define UART2_UART2_MSR_REG_UART_CTS_Pos (4UL) /*!< UART2 UART2_MSR_REG: UART_CTS (Bit 4) */ -#define UART2_UART2_MSR_REG_UART_CTS_Msk (0x10UL) /*!< UART2 UART2_MSR_REG: UART_CTS (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_SCR_REG ---------------------------- */ -#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos (0UL) /*!< UART2 UART2_SCR_REG: UART_SCRATCH_PAD (Bit 0) */ -#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL) /*!< UART2 UART2_SCR_REG: UART_SCRATCH_PAD (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR0_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR0_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR0_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR1_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR1_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR1_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR2_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR2_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR2_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR3_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR3_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR3_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR4_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR4_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR4_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR5_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR5_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR5_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR6_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR6_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR6_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR7_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR7_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR7_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR8_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR8_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR8_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR9_REG ------------------------- */ -#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR9_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR9_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR10_REG ------------------------ */ -#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR10_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR10_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR11_REG ------------------------ */ -#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR11_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR11_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR12_REG ------------------------ */ -#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR12_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR12_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR13_REG ------------------------ */ -#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR13_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR13_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR14_REG ------------------------ */ -#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR14_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR14_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ------------------------- UART2_UART2_SRBR_STHR15_REG ------------------------ */ -#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL) /*!< UART2 UART2_SRBR_STHR15_REG: SRBR_STHRx (Bit 0) */ -#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL) /*!< UART2 UART2_SRBR_STHR15_REG: SRBR_STHRx (Bitfield-Mask: 0xff) */ - -/* ----------------------------- UART2_UART2_FAR_REG ---------------------------- */ -#define UART2_UART2_FAR_REG_UART_FAR_Pos (0UL) /*!< UART2 UART2_FAR_REG: UART_FAR (Bit 0) */ -#define UART2_UART2_FAR_REG_UART_FAR_Msk (0x1UL) /*!< UART2 UART2_FAR_REG: UART_FAR (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_USR_REG ---------------------------- */ -#define UART2_UART2_USR_REG_UART_BUSY_Pos (0UL) /*!< UART2 UART2_USR_REG: UART_BUSY (Bit 0) */ -#define UART2_UART2_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART2 UART2_USR_REG: UART_BUSY (Bitfield-Mask: 0x01) */ -#define UART2_UART2_USR_REG_UART_TFNF_Pos (1UL) /*!< UART2 UART2_USR_REG: UART_TFNF (Bit 1) */ -#define UART2_UART2_USR_REG_UART_TFNF_Msk (0x2UL) /*!< UART2 UART2_USR_REG: UART_TFNF (Bitfield-Mask: 0x01) */ -#define UART2_UART2_USR_REG_UART_TFE_Pos (2UL) /*!< UART2 UART2_USR_REG: UART_TFE (Bit 2) */ -#define UART2_UART2_USR_REG_UART_TFE_Msk (0x4UL) /*!< UART2 UART2_USR_REG: UART_TFE (Bitfield-Mask: 0x01) */ -#define UART2_UART2_USR_REG_UART_RFNE_Pos (3UL) /*!< UART2 UART2_USR_REG: UART_RFNE (Bit 3) */ -#define UART2_UART2_USR_REG_UART_RFNE_Msk (0x8UL) /*!< UART2 UART2_USR_REG: UART_RFNE (Bitfield-Mask: 0x01) */ -#define UART2_UART2_USR_REG_UART_RFF_Pos (4UL) /*!< UART2 UART2_USR_REG: UART_RFF (Bit 4) */ -#define UART2_UART2_USR_REG_UART_RFF_Msk (0x10UL) /*!< UART2 UART2_USR_REG: UART_RFF (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_TFL_REG ---------------------------- */ -#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL) /*!< UART2 UART2_TFL_REG: UART_TRANSMIT_FIFO_LEVEL (Bit 0) */ -#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0xffffUL) /*!< UART2 UART2_TFL_REG: UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- UART2_UART2_RFL_REG ---------------------------- */ -#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL) /*!< UART2 UART2_RFL_REG: UART_RECEIVE_FIFO_LEVEL (Bit 0) */ -#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0xffffUL) /*!< UART2 UART2_RFL_REG: UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- UART2_UART2_SRR_REG ---------------------------- */ -#define UART2_UART2_SRR_REG_UART_UR_Pos (0UL) /*!< UART2 UART2_SRR_REG: UART_UR (Bit 0) */ -#define UART2_UART2_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART2 UART2_SRR_REG: UART_UR (Bitfield-Mask: 0x01) */ -#define UART2_UART2_SRR_REG_UART_RFR_Pos (1UL) /*!< UART2 UART2_SRR_REG: UART_RFR (Bit 1) */ -#define UART2_UART2_SRR_REG_UART_RFR_Msk (0x2UL) /*!< UART2 UART2_SRR_REG: UART_RFR (Bitfield-Mask: 0x01) */ -#define UART2_UART2_SRR_REG_UART_XFR_Pos (2UL) /*!< UART2 UART2_SRR_REG: UART_XFR (Bit 2) */ -#define UART2_UART2_SRR_REG_UART_XFR_Msk (0x4UL) /*!< UART2 UART2_SRR_REG: UART_XFR (Bitfield-Mask: 0x01) */ - -/* ---------------------------- UART2_UART2_SRTS_REG ---------------------------- */ -#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL) /*!< UART2 UART2_SRTS_REG: UART_SHADOW_REQUEST_TO_SEND (Bit 0) */ -#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL) /*!< UART2 UART2_SRTS_REG: UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01) */ - -/* ---------------------------- UART2_UART2_SBCR_REG ---------------------------- */ -#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART2 UART2_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bit 0) */ -#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART2 UART2_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */ - -/* ---------------------------- UART2_UART2_SDMAM_REG --------------------------- */ -#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL) /*!< UART2 UART2_SDMAM_REG: UART_SHADOW_DMA_MODE (Bit 0) */ -#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL) /*!< UART2 UART2_SDMAM_REG: UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_SFE_REG ---------------------------- */ -#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL) /*!< UART2 UART2_SFE_REG: UART_SHADOW_FIFO_ENABLE (Bit 0) */ -#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL) /*!< UART2 UART2_SFE_REG: UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_SRT_REG ---------------------------- */ -#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL) /*!< UART2 UART2_SRT_REG: UART_SHADOW_RCVR_TRIGGER (Bit 0) */ -#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL) /*!< UART2 UART2_SRT_REG: UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */ - -/* ---------------------------- UART2_UART2_STET_REG ---------------------------- */ -#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART2 UART2_STET_REG: UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0) */ -#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART2 UART2_STET_REG: UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */ - -/* ----------------------------- UART2_UART2_HTX_REG ---------------------------- */ -#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos (0UL) /*!< UART2 UART2_HTX_REG: UART_HALT_TX (Bit 0) */ -#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk (0x1UL) /*!< UART2 UART2_HTX_REG: UART_HALT_TX (Bitfield-Mask: 0x01) */ - -/* ---------------------------- UART2_UART2_DMASA_REG --------------------------- */ -#define UART2_UART2_DMASA_REG_DMASA_Pos (0UL) /*!< UART2 UART2_DMASA_REG: DMASA (Bit 0) */ -#define UART2_UART2_DMASA_REG_DMASA_Msk (0x1UL) /*!< UART2 UART2_DMASA_REG: DMASA (Bitfield-Mask: 0x01) */ - -/* ----------------------------- UART2_UART2_DLF_REG ---------------------------- */ -#define UART2_UART2_DLF_REG_UART_DLF_Pos (0UL) /*!< UART2 UART2_DLF_REG: UART_DLF (Bit 0) */ -#define UART2_UART2_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART2 UART2_DLF_REG: UART_DLF (Bitfield-Mask: 0x0f) */ - -/* ----------------------------- UART2_UART2_CPR_REG ---------------------------- */ -#define UART2_UART2_CPR_REG_CPR_Pos (0UL) /*!< UART2 UART2_CPR_REG: CPR (Bit 0) */ -#define UART2_UART2_CPR_REG_CPR_Msk (0xffffUL) /*!< UART2 UART2_CPR_REG: CPR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- UART2_UART2_UCV_REG ---------------------------- */ -#define UART2_UART2_UCV_REG_UCV_Pos (0UL) /*!< UART2 UART2_UCV_REG: UCV (Bit 0) */ -#define UART2_UART2_UCV_REG_UCV_Msk (0xffffUL) /*!< UART2 UART2_UCV_REG: UCV (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- UART2_UART2_CTR_REG ---------------------------- */ -#define UART2_UART2_CTR_REG_CTR_Pos (0UL) /*!< UART2 UART2_CTR_REG: CTR (Bit 0) */ -#define UART2_UART2_CTR_REG_CTR_Msk (0xffffUL) /*!< UART2 UART2_CTR_REG: CTR (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'USB' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------ USB_USB_MCTRL_REG ----------------------------- */ -#define USB_USB_MCTRL_REG_USBEN_Pos (0UL) /*!< USB USB_MCTRL_REG: USBEN (Bit 0) */ -#define USB_USB_MCTRL_REG_USBEN_Msk (0x1UL) /*!< USB USB_MCTRL_REG: USBEN (Bitfield-Mask: 0x01) */ -#define USB_USB_MCTRL_REG_USB_DBG_Pos (1UL) /*!< USB USB_MCTRL_REG: USB_DBG (Bit 1) */ -#define USB_USB_MCTRL_REG_USB_DBG_Msk (0x2UL) /*!< USB USB_MCTRL_REG: USB_DBG (Bitfield-Mask: 0x01) */ -#define USB_USB_MCTRL_REG_USB_NAT_Pos (3UL) /*!< USB USB_MCTRL_REG: USB_NAT (Bit 3) */ -#define USB_USB_MCTRL_REG_USB_NAT_Msk (0x8UL) /*!< USB USB_MCTRL_REG: USB_NAT (Bitfield-Mask: 0x01) */ -#define USB_USB_MCTRL_REG_LSMODE_Pos (4UL) /*!< USB USB_MCTRL_REG: LSMODE (Bit 4) */ -#define USB_USB_MCTRL_REG_LSMODE_Msk (0x10UL) /*!< USB USB_MCTRL_REG: LSMODE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_USB_XCVDIAG_REG ---------------------------- */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos (0UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TEST (Bit 0) */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk (0x1UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TEST (Bitfield-Mask: 0x01) */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos (1UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TXp (Bit 1) */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk (0x2UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TXp (Bitfield-Mask: 0x01) */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos (2UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TXn (Bit 2) */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk (0x4UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TXn (Bitfield-Mask: 0x01) */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos (3UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TXEN (Bit 3) */ -#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk (0x8UL) /*!< USB USB_XCVDIAG_REG: USB_XCV_TXEN (Bitfield-Mask: 0x01) */ -#define USB_USB_XCVDIAG_REG_USB_RCV_Pos (5UL) /*!< USB USB_XCVDIAG_REG: USB_RCV (Bit 5) */ -#define USB_USB_XCVDIAG_REG_USB_RCV_Msk (0x20UL) /*!< USB USB_XCVDIAG_REG: USB_RCV (Bitfield-Mask: 0x01) */ -#define USB_USB_XCVDIAG_REG_USB_VMIN_Pos (6UL) /*!< USB USB_XCVDIAG_REG: USB_VMIN (Bit 6) */ -#define USB_USB_XCVDIAG_REG_USB_VMIN_Msk (0x40UL) /*!< USB USB_XCVDIAG_REG: USB_VMIN (Bitfield-Mask: 0x01) */ -#define USB_USB_XCVDIAG_REG_USB_VPIN_Pos (7UL) /*!< USB USB_XCVDIAG_REG: USB_VPIN (Bit 7) */ -#define USB_USB_XCVDIAG_REG_USB_VPIN_Msk (0x80UL) /*!< USB USB_XCVDIAG_REG: USB_VPIN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_USB_TCR_REG ------------------------------ */ -#define USB_USB_TCR_REG_USB_CADJ_Pos (0UL) /*!< USB USB_TCR_REG: USB_CADJ (Bit 0) */ -#define USB_USB_TCR_REG_USB_CADJ_Msk (0x1fUL) /*!< USB USB_TCR_REG: USB_CADJ (Bitfield-Mask: 0x1f) */ -#define USB_USB_TCR_REG_USB_VADJ_Pos (5UL) /*!< USB USB_TCR_REG: USB_VADJ (Bit 5) */ -#define USB_USB_TCR_REG_USB_VADJ_Msk (0xe0UL) /*!< USB USB_TCR_REG: USB_VADJ (Bitfield-Mask: 0x07) */ - -/* ------------------------------- USB_USB_UTR_REG ------------------------------ */ -#define USB_USB_UTR_REG_USB_UTR_RES_Pos (0UL) /*!< USB USB_UTR_REG: USB_UTR_RES (Bit 0) */ -#define USB_USB_UTR_REG_USB_UTR_RES_Msk (0x1fUL) /*!< USB USB_UTR_REG: USB_UTR_RES (Bitfield-Mask: 0x1f) */ -#define USB_USB_UTR_REG_USB_SF_Pos (5UL) /*!< USB USB_UTR_REG: USB_SF (Bit 5) */ -#define USB_USB_UTR_REG_USB_SF_Msk (0x20UL) /*!< USB USB_UTR_REG: USB_SF (Bitfield-Mask: 0x01) */ -#define USB_USB_UTR_REG_USB_NCRC_Pos (6UL) /*!< USB USB_UTR_REG: USB_NCRC (Bit 6) */ -#define USB_USB_UTR_REG_USB_NCRC_Msk (0x40UL) /*!< USB USB_UTR_REG: USB_NCRC (Bitfield-Mask: 0x01) */ -#define USB_USB_UTR_REG_USB_DIAG_Pos (7UL) /*!< USB USB_UTR_REG: USB_DIAG (Bit 7) */ -#define USB_USB_UTR_REG_USB_DIAG_Msk (0x80UL) /*!< USB USB_UTR_REG: USB_DIAG (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_USB_FAR_REG ------------------------------ */ -#define USB_USB_FAR_REG_USB_AD_Pos (0UL) /*!< USB USB_FAR_REG: USB_AD (Bit 0) */ -#define USB_USB_FAR_REG_USB_AD_Msk (0x7fUL) /*!< USB USB_FAR_REG: USB_AD (Bitfield-Mask: 0x7f) */ -#define USB_USB_FAR_REG_USB_AD_EN_Pos (7UL) /*!< USB USB_FAR_REG: USB_AD_EN (Bit 7) */ -#define USB_USB_FAR_REG_USB_AD_EN_Msk (0x80UL) /*!< USB USB_FAR_REG: USB_AD_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_NFSR_REG ------------------------------ */ -#define USB_USB_NFSR_REG_USB_NFS_Pos (0UL) /*!< USB USB_NFSR_REG: USB_NFS (Bit 0) */ -#define USB_USB_NFSR_REG_USB_NFS_Msk (0x3UL) /*!< USB USB_NFSR_REG: USB_NFS (Bitfield-Mask: 0x03) */ - -/* ------------------------------ USB_USB_MAEV_REG ------------------------------ */ -#define USB_USB_MAEV_REG_USB_WARN_Pos (0UL) /*!< USB USB_MAEV_REG: USB_WARN (Bit 0) */ -#define USB_USB_MAEV_REG_USB_WARN_Msk (0x1UL) /*!< USB USB_MAEV_REG: USB_WARN (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_ALT_Pos (1UL) /*!< USB USB_MAEV_REG: USB_ALT (Bit 1) */ -#define USB_USB_MAEV_REG_USB_ALT_Msk (0x2UL) /*!< USB USB_MAEV_REG: USB_ALT (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_TX_EV_Pos (2UL) /*!< USB USB_MAEV_REG: USB_TX_EV (Bit 2) */ -#define USB_USB_MAEV_REG_USB_TX_EV_Msk (0x4UL) /*!< USB USB_MAEV_REG: USB_TX_EV (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_FRAME_Pos (3UL) /*!< USB USB_MAEV_REG: USB_FRAME (Bit 3) */ -#define USB_USB_MAEV_REG_USB_FRAME_Msk (0x8UL) /*!< USB USB_MAEV_REG: USB_FRAME (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_NAK_Pos (4UL) /*!< USB USB_MAEV_REG: USB_NAK (Bit 4) */ -#define USB_USB_MAEV_REG_USB_NAK_Msk (0x10UL) /*!< USB USB_MAEV_REG: USB_NAK (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_ULD_Pos (5UL) /*!< USB USB_MAEV_REG: USB_ULD (Bit 5) */ -#define USB_USB_MAEV_REG_USB_ULD_Msk (0x20UL) /*!< USB USB_MAEV_REG: USB_ULD (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_RX_EV_Pos (6UL) /*!< USB USB_MAEV_REG: USB_RX_EV (Bit 6) */ -#define USB_USB_MAEV_REG_USB_RX_EV_Msk (0x40UL) /*!< USB USB_MAEV_REG: USB_RX_EV (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_INTR_Pos (7UL) /*!< USB USB_MAEV_REG: USB_INTR (Bit 7) */ -#define USB_USB_MAEV_REG_USB_INTR_Msk (0x80UL) /*!< USB USB_MAEV_REG: USB_INTR (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_EP0_TX_Pos (8UL) /*!< USB USB_MAEV_REG: USB_EP0_TX (Bit 8) */ -#define USB_USB_MAEV_REG_USB_EP0_TX_Msk (0x100UL) /*!< USB USB_MAEV_REG: USB_EP0_TX (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_EP0_RX_Pos (9UL) /*!< USB USB_MAEV_REG: USB_EP0_RX (Bit 9) */ -#define USB_USB_MAEV_REG_USB_EP0_RX_Msk (0x200UL) /*!< USB USB_MAEV_REG: USB_EP0_RX (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_EP0_NAK_Pos (10UL) /*!< USB USB_MAEV_REG: USB_EP0_NAK (Bit 10) */ -#define USB_USB_MAEV_REG_USB_EP0_NAK_Msk (0x400UL) /*!< USB USB_MAEV_REG: USB_EP0_NAK (Bitfield-Mask: 0x01) */ -#define USB_USB_MAEV_REG_USB_CH_EV_Pos (11UL) /*!< USB USB_MAEV_REG: USB_CH_EV (Bit 11) */ -#define USB_USB_MAEV_REG_USB_CH_EV_Msk (0x800UL) /*!< USB USB_MAEV_REG: USB_CH_EV (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_MAMSK_REG ----------------------------- */ -#define USB_USB_MAMSK_REG_USB_M_WARN_Pos (0UL) /*!< USB USB_MAMSK_REG: USB_M_WARN (Bit 0) */ -#define USB_USB_MAMSK_REG_USB_M_WARN_Msk (0x1UL) /*!< USB USB_MAMSK_REG: USB_M_WARN (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_ALT_Pos (1UL) /*!< USB USB_MAMSK_REG: USB_M_ALT (Bit 1) */ -#define USB_USB_MAMSK_REG_USB_M_ALT_Msk (0x2UL) /*!< USB USB_MAMSK_REG: USB_M_ALT (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_TX_EV_Pos (2UL) /*!< USB USB_MAMSK_REG: USB_M_TX_EV (Bit 2) */ -#define USB_USB_MAMSK_REG_USB_M_TX_EV_Msk (0x4UL) /*!< USB USB_MAMSK_REG: USB_M_TX_EV (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_FRAME_Pos (3UL) /*!< USB USB_MAMSK_REG: USB_M_FRAME (Bit 3) */ -#define USB_USB_MAMSK_REG_USB_M_FRAME_Msk (0x8UL) /*!< USB USB_MAMSK_REG: USB_M_FRAME (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_NAK_Pos (4UL) /*!< USB USB_MAMSK_REG: USB_M_NAK (Bit 4) */ -#define USB_USB_MAMSK_REG_USB_M_NAK_Msk (0x10UL) /*!< USB USB_MAMSK_REG: USB_M_NAK (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_ULD_Pos (5UL) /*!< USB USB_MAMSK_REG: USB_M_ULD (Bit 5) */ -#define USB_USB_MAMSK_REG_USB_M_ULD_Msk (0x20UL) /*!< USB USB_MAMSK_REG: USB_M_ULD (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_RX_EV_Pos (6UL) /*!< USB USB_MAMSK_REG: USB_M_RX_EV (Bit 6) */ -#define USB_USB_MAMSK_REG_USB_M_RX_EV_Msk (0x40UL) /*!< USB USB_MAMSK_REG: USB_M_RX_EV (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_INTR_Pos (7UL) /*!< USB USB_MAMSK_REG: USB_M_INTR (Bit 7) */ -#define USB_USB_MAMSK_REG_USB_M_INTR_Msk (0x80UL) /*!< USB USB_MAMSK_REG: USB_M_INTR (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos (8UL) /*!< USB USB_MAMSK_REG: USB_M_EP0_TX (Bit 8) */ -#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk (0x100UL) /*!< USB USB_MAMSK_REG: USB_M_EP0_TX (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos (9UL) /*!< USB USB_MAMSK_REG: USB_M_EP0_RX (Bit 9) */ -#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk (0x200UL) /*!< USB USB_MAMSK_REG: USB_M_EP0_RX (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos (10UL) /*!< USB USB_MAMSK_REG: USB_M_EP0_NAK (Bit 10) */ -#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk (0x400UL) /*!< USB USB_MAMSK_REG: USB_M_EP0_NAK (Bitfield-Mask: 0x01) */ -#define USB_USB_MAMSK_REG_USB_M_CH_EV_Pos (11UL) /*!< USB USB_MAMSK_REG: USB_M_CH_EV (Bit 11) */ -#define USB_USB_MAMSK_REG_USB_M_CH_EV_Msk (0x800UL) /*!< USB USB_MAMSK_REG: USB_M_CH_EV (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_ALTEV_REG ----------------------------- */ -#define USB_USB_ALTEV_REG_USB_EOP_Pos (3UL) /*!< USB USB_ALTEV_REG: USB_EOP (Bit 3) */ -#define USB_USB_ALTEV_REG_USB_EOP_Msk (0x8UL) /*!< USB USB_ALTEV_REG: USB_EOP (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTEV_REG_USB_SD3_Pos (4UL) /*!< USB USB_ALTEV_REG: USB_SD3 (Bit 4) */ -#define USB_USB_ALTEV_REG_USB_SD3_Msk (0x10UL) /*!< USB USB_ALTEV_REG: USB_SD3 (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTEV_REG_USB_SD5_Pos (5UL) /*!< USB USB_ALTEV_REG: USB_SD5 (Bit 5) */ -#define USB_USB_ALTEV_REG_USB_SD5_Msk (0x20UL) /*!< USB USB_ALTEV_REG: USB_SD5 (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTEV_REG_USB_RESET_Pos (6UL) /*!< USB USB_ALTEV_REG: USB_RESET (Bit 6) */ -#define USB_USB_ALTEV_REG_USB_RESET_Msk (0x40UL) /*!< USB USB_ALTEV_REG: USB_RESET (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTEV_REG_USB_RESUME_Pos (7UL) /*!< USB USB_ALTEV_REG: USB_RESUME (Bit 7) */ -#define USB_USB_ALTEV_REG_USB_RESUME_Msk (0x80UL) /*!< USB USB_ALTEV_REG: USB_RESUME (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_USB_ALTMSK_REG ----------------------------- */ -#define USB_USB_ALTMSK_REG_USB_M_EOP_Pos (3UL) /*!< USB USB_ALTMSK_REG: USB_M_EOP (Bit 3) */ -#define USB_USB_ALTMSK_REG_USB_M_EOP_Msk (0x8UL) /*!< USB USB_ALTMSK_REG: USB_M_EOP (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTMSK_REG_USB_M_SD3_Pos (4UL) /*!< USB USB_ALTMSK_REG: USB_M_SD3 (Bit 4) */ -#define USB_USB_ALTMSK_REG_USB_M_SD3_Msk (0x10UL) /*!< USB USB_ALTMSK_REG: USB_M_SD3 (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTMSK_REG_USB_M_SD5_Pos (5UL) /*!< USB USB_ALTMSK_REG: USB_M_SD5 (Bit 5) */ -#define USB_USB_ALTMSK_REG_USB_M_SD5_Msk (0x20UL) /*!< USB USB_ALTMSK_REG: USB_M_SD5 (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTMSK_REG_USB_M_RESET_Pos (6UL) /*!< USB USB_ALTMSK_REG: USB_M_RESET (Bit 6) */ -#define USB_USB_ALTMSK_REG_USB_M_RESET_Msk (0x40UL) /*!< USB USB_ALTMSK_REG: USB_M_RESET (Bitfield-Mask: 0x01) */ -#define USB_USB_ALTMSK_REG_USB_M_RESUME_Pos (7UL) /*!< USB USB_ALTMSK_REG: USB_M_RESUME (Bit 7) */ -#define USB_USB_ALTMSK_REG_USB_M_RESUME_Msk (0x80UL) /*!< USB USB_ALTMSK_REG: USB_M_RESUME (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXEV_REG ------------------------------ */ -#define USB_USB_TXEV_REG_USB_TXFIFO31_Pos (0UL) /*!< USB USB_TXEV_REG: USB_TXFIFO31 (Bit 0) */ -#define USB_USB_TXEV_REG_USB_TXFIFO31_Msk (0x7UL) /*!< USB USB_TXEV_REG: USB_TXFIFO31 (Bitfield-Mask: 0x07) */ -#define USB_USB_TXEV_REG_USB_TXUDRRN31_Pos (4UL) /*!< USB USB_TXEV_REG: USB_TXUDRRN31 (Bit 4) */ -#define USB_USB_TXEV_REG_USB_TXUDRRN31_Msk (0x70UL) /*!< USB USB_TXEV_REG: USB_TXUDRRN31 (Bitfield-Mask: 0x07) */ - -/* ------------------------------ USB_USB_TXMSK_REG ----------------------------- */ -#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos (0UL) /*!< USB USB_TXMSK_REG: USB_M_TXFIFO31 (Bit 0) */ -#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk (0x7UL) /*!< USB USB_TXMSK_REG: USB_M_TXFIFO31 (Bitfield-Mask: 0x07) */ -#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos (4UL) /*!< USB USB_TXMSK_REG: USB_M_TXUDRRN31 (Bit 4) */ -#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk (0x70UL) /*!< USB USB_TXMSK_REG: USB_M_TXUDRRN31 (Bitfield-Mask: 0x07) */ - -/* ------------------------------ USB_USB_RXEV_REG ------------------------------ */ -#define USB_USB_RXEV_REG_USB_RXFIFO31_Pos (0UL) /*!< USB USB_RXEV_REG: USB_RXFIFO31 (Bit 0) */ -#define USB_USB_RXEV_REG_USB_RXFIFO31_Msk (0x7UL) /*!< USB USB_RXEV_REG: USB_RXFIFO31 (Bitfield-Mask: 0x07) */ -#define USB_USB_RXEV_REG_USB_RXOVRRN31_Pos (4UL) /*!< USB USB_RXEV_REG: USB_RXOVRRN31 (Bit 4) */ -#define USB_USB_RXEV_REG_USB_RXOVRRN31_Msk (0x70UL) /*!< USB USB_RXEV_REG: USB_RXOVRRN31 (Bitfield-Mask: 0x07) */ - -/* ------------------------------ USB_USB_RXMSK_REG ----------------------------- */ -#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos (0UL) /*!< USB USB_RXMSK_REG: USB_M_RXFIFO31 (Bit 0) */ -#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk (0x7UL) /*!< USB USB_RXMSK_REG: USB_M_RXFIFO31 (Bitfield-Mask: 0x07) */ -#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos (4UL) /*!< USB USB_RXMSK_REG: USB_M_RXOVRRN31 (Bit 4) */ -#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk (0x70UL) /*!< USB USB_RXMSK_REG: USB_M_RXOVRRN31 (Bitfield-Mask: 0x07) */ - -/* ------------------------------ USB_USB_NAKEV_REG ----------------------------- */ -#define USB_USB_NAKEV_REG_USB_IN31_Pos (0UL) /*!< USB USB_NAKEV_REG: USB_IN31 (Bit 0) */ -#define USB_USB_NAKEV_REG_USB_IN31_Msk (0x7UL) /*!< USB USB_NAKEV_REG: USB_IN31 (Bitfield-Mask: 0x07) */ -#define USB_USB_NAKEV_REG_USB_OUT31_Pos (4UL) /*!< USB USB_NAKEV_REG: USB_OUT31 (Bit 4) */ -#define USB_USB_NAKEV_REG_USB_OUT31_Msk (0x70UL) /*!< USB USB_NAKEV_REG: USB_OUT31 (Bitfield-Mask: 0x07) */ - -/* ----------------------------- USB_USB_NAKMSK_REG ----------------------------- */ -#define USB_USB_NAKMSK_REG_USB_M_IN31_Pos (0UL) /*!< USB USB_NAKMSK_REG: USB_M_IN31 (Bit 0) */ -#define USB_USB_NAKMSK_REG_USB_M_IN31_Msk (0x7UL) /*!< USB USB_NAKMSK_REG: USB_M_IN31 (Bitfield-Mask: 0x07) */ -#define USB_USB_NAKMSK_REG_USB_M_OUT31_Pos (4UL) /*!< USB USB_NAKMSK_REG: USB_M_OUT31 (Bit 4) */ -#define USB_USB_NAKMSK_REG_USB_M_OUT31_Msk (0x70UL) /*!< USB USB_NAKMSK_REG: USB_M_OUT31 (Bitfield-Mask: 0x07) */ - -/* ------------------------------ USB_USB_FWEV_REG ------------------------------ */ -#define USB_USB_FWEV_REG_USB_TXWARN31_Pos (0UL) /*!< USB USB_FWEV_REG: USB_TXWARN31 (Bit 0) */ -#define USB_USB_FWEV_REG_USB_TXWARN31_Msk (0x7UL) /*!< USB USB_FWEV_REG: USB_TXWARN31 (Bitfield-Mask: 0x07) */ -#define USB_USB_FWEV_REG_USB_RXWARN31_Pos (4UL) /*!< USB USB_FWEV_REG: USB_RXWARN31 (Bit 4) */ -#define USB_USB_FWEV_REG_USB_RXWARN31_Msk (0x70UL) /*!< USB USB_FWEV_REG: USB_RXWARN31 (Bitfield-Mask: 0x07) */ - -/* ------------------------------ USB_USB_FWMSK_REG ----------------------------- */ -#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos (0UL) /*!< USB USB_FWMSK_REG: USB_M_TXWARN31 (Bit 0) */ -#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk (0x7UL) /*!< USB USB_FWMSK_REG: USB_M_TXWARN31 (Bitfield-Mask: 0x07) */ -#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos (4UL) /*!< USB USB_FWMSK_REG: USB_M_RXWARN31 (Bit 4) */ -#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk (0x70UL) /*!< USB USB_FWMSK_REG: USB_M_RXWARN31 (Bitfield-Mask: 0x07) */ - -/* ------------------------------- USB_USB_FNH_REG ------------------------------ */ -#define USB_USB_FNH_REG_USB_FN_10_8_Pos (0UL) /*!< USB USB_FNH_REG: USB_FN_10_8 (Bit 0) */ -#define USB_USB_FNH_REG_USB_FN_10_8_Msk (0x7UL) /*!< USB USB_FNH_REG: USB_FN_10_8 (Bitfield-Mask: 0x07) */ -#define USB_USB_FNH_REG_USB_RFC_Pos (5UL) /*!< USB USB_FNH_REG: USB_RFC (Bit 5) */ -#define USB_USB_FNH_REG_USB_RFC_Msk (0x20UL) /*!< USB USB_FNH_REG: USB_RFC (Bitfield-Mask: 0x01) */ -#define USB_USB_FNH_REG_USB_UL_Pos (6UL) /*!< USB USB_FNH_REG: USB_UL (Bit 6) */ -#define USB_USB_FNH_REG_USB_UL_Msk (0x40UL) /*!< USB USB_FNH_REG: USB_UL (Bitfield-Mask: 0x01) */ -#define USB_USB_FNH_REG_USB_MF_Pos (7UL) /*!< USB USB_FNH_REG: USB_MF (Bit 7) */ -#define USB_USB_FNH_REG_USB_MF_Msk (0x80UL) /*!< USB USB_FNH_REG: USB_MF (Bitfield-Mask: 0x01) */ - -/* ------------------------------- USB_USB_FNL_REG ------------------------------ */ -#define USB_USB_FNL_REG_USB_FN_Pos (0UL) /*!< USB USB_FNL_REG: USB_FN (Bit 0) */ -#define USB_USB_FNL_REG_USB_FN_Msk (0xffUL) /*!< USB USB_FNL_REG: USB_FN (Bitfield-Mask: 0xff) */ - -/* ----------------------------- USB_USB_UX20CDR_REG ---------------------------- */ -#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos (0UL) /*!< USB USB_UX20CDR_REG: RPU_SSPROTEN (Bit 0) */ -#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk (0x1UL) /*!< USB USB_UX20CDR_REG: RPU_SSPROTEN (Bitfield-Mask: 0x01) */ -#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos (1UL) /*!< USB USB_UX20CDR_REG: RPU_RCDELAY (Bit 1) */ -#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk (0x2UL) /*!< USB USB_UX20CDR_REG: RPU_RCDELAY (Bitfield-Mask: 0x01) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos (2UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1DM (Bit 2) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk (0x4UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1DM (Bitfield-Mask: 0x01) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos (4UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_EN (Bit 4) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk (0x10UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos (5UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1 (Bit 5) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk (0x20UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_SW1 (Bitfield-Mask: 0x01) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos (6UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_SW2 (Bit 6) */ -#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk (0x40UL) /*!< USB USB_UX20CDR_REG: RPU_TEST_SW2 (Bitfield-Mask: 0x01) */ -#define USB_USB_UX20CDR_REG_RPU_TEST7_Pos (7UL) /*!< USB USB_UX20CDR_REG: RPU_TEST7 (Bit 7) */ -#define USB_USB_UX20CDR_REG_RPU_TEST7_Msk (0x80UL) /*!< USB USB_UX20CDR_REG: RPU_TEST7 (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_EPC0_REG ------------------------------ */ -#define USB_USB_EPC0_REG_USB_EP_Pos (0UL) /*!< USB USB_EPC0_REG: USB_EP (Bit 0) */ -#define USB_USB_EPC0_REG_USB_EP_Msk (0xfUL) /*!< USB USB_EPC0_REG: USB_EP (Bitfield-Mask: 0x0f) */ -#define USB_USB_EPC0_REG_USB_DEF_Pos (6UL) /*!< USB USB_EPC0_REG: USB_DEF (Bit 6) */ -#define USB_USB_EPC0_REG_USB_DEF_Msk (0x40UL) /*!< USB USB_EPC0_REG: USB_DEF (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC0_REG_USB_STALL_Pos (7UL) /*!< USB USB_EPC0_REG: USB_STALL (Bit 7) */ -#define USB_USB_EPC0_REG_USB_STALL_Msk (0x80UL) /*!< USB USB_EPC0_REG: USB_STALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXD0_REG ------------------------------ */ -#define USB_USB_TXD0_REG_USB_TXFD_Pos (0UL) /*!< USB USB_TXD0_REG: USB_TXFD (Bit 0) */ -#define USB_USB_TXD0_REG_USB_TXFD_Msk (0xffUL) /*!< USB USB_TXD0_REG: USB_TXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_TXS0_REG ------------------------------ */ -#define USB_USB_TXS0_REG_USB_TCOUNT_Pos (0UL) /*!< USB USB_TXS0_REG: USB_TCOUNT (Bit 0) */ -#define USB_USB_TXS0_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB USB_TXS0_REG: USB_TCOUNT (Bitfield-Mask: 0x1f) */ -#define USB_USB_TXS0_REG_USB_TX_DONE_Pos (5UL) /*!< USB USB_TXS0_REG: USB_TX_DONE (Bit 5) */ -#define USB_USB_TXS0_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB USB_TXS0_REG: USB_TX_DONE (Bitfield-Mask: 0x01) */ -#define USB_USB_TXS0_REG_USB_ACK_STAT_Pos (6UL) /*!< USB USB_TXS0_REG: USB_ACK_STAT (Bit 6) */ -#define USB_USB_TXS0_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB USB_TXS0_REG: USB_ACK_STAT (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXC0_REG ------------------------------ */ -#define USB_USB_TXC0_REG_USB_TX_EN_Pos (0UL) /*!< USB USB_TXC0_REG: USB_TX_EN (Bit 0) */ -#define USB_USB_TXC0_REG_USB_TX_EN_Msk (0x1UL) /*!< USB USB_TXC0_REG: USB_TX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos (2UL) /*!< USB USB_TXC0_REG: USB_TOGGLE_TX0 (Bit 2) */ -#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk (0x4UL) /*!< USB USB_TXC0_REG: USB_TOGGLE_TX0 (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC0_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_TXC0_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_TXC0_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_TXC0_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC0_REG_USB_IGN_IN_Pos (4UL) /*!< USB USB_TXC0_REG: USB_IGN_IN (Bit 4) */ -#define USB_USB_TXC0_REG_USB_IGN_IN_Msk (0x10UL) /*!< USB USB_TXC0_REG: USB_IGN_IN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- USB_USB_EP0_NAK_REG ---------------------------- */ -#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos (0UL) /*!< USB USB_EP0_NAK_REG: USB_EP0_INNAK (Bit 0) */ -#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk (0x1UL) /*!< USB USB_EP0_NAK_REG: USB_EP0_INNAK (Bitfield-Mask: 0x01) */ -#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos (1UL) /*!< USB USB_EP0_NAK_REG: USB_EP0_OUTNAK (Bit 1) */ -#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk (0x2UL) /*!< USB USB_EP0_NAK_REG: USB_EP0_OUTNAK (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXD0_REG ------------------------------ */ -#define USB_USB_RXD0_REG_USB_RXFD_Pos (0UL) /*!< USB USB_RXD0_REG: USB_RXFD (Bit 0) */ -#define USB_USB_RXD0_REG_USB_RXFD_Msk (0xffUL) /*!< USB USB_RXD0_REG: USB_RXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_RXS0_REG ------------------------------ */ -#define USB_USB_RXS0_REG_USB_RCOUNT_Pos (0UL) /*!< USB USB_RXS0_REG: USB_RCOUNT (Bit 0) */ -#define USB_USB_RXS0_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB USB_RXS0_REG: USB_RCOUNT (Bitfield-Mask: 0x0f) */ -#define USB_USB_RXS0_REG_USB_RX_LAST_Pos (4UL) /*!< USB USB_RXS0_REG: USB_RX_LAST (Bit 4) */ -#define USB_USB_RXS0_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB USB_RXS0_REG: USB_RX_LAST (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos (5UL) /*!< USB USB_RXS0_REG: USB_TOGGLE_RX0 (Bit 5) */ -#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk (0x20UL) /*!< USB USB_RXS0_REG: USB_TOGGLE_RX0 (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS0_REG_USB_SETUP_Pos (6UL) /*!< USB USB_RXS0_REG: USB_SETUP (Bit 6) */ -#define USB_USB_RXS0_REG_USB_SETUP_Msk (0x40UL) /*!< USB USB_RXS0_REG: USB_SETUP (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXC0_REG ------------------------------ */ -#define USB_USB_RXC0_REG_USB_RX_EN_Pos (0UL) /*!< USB USB_RXC0_REG: USB_RX_EN (Bit 0) */ -#define USB_USB_RXC0_REG_USB_RX_EN_Msk (0x1UL) /*!< USB USB_RXC0_REG: USB_RX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC0_REG_USB_IGN_OUT_Pos (1UL) /*!< USB USB_RXC0_REG: USB_IGN_OUT (Bit 1) */ -#define USB_USB_RXC0_REG_USB_IGN_OUT_Msk (0x2UL) /*!< USB USB_RXC0_REG: USB_IGN_OUT (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC0_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB USB_RXC0_REG: USB_IGN_SETUP (Bit 2) */ -#define USB_USB_RXC0_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB USB_RXC0_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC0_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_RXC0_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_RXC0_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_RXC0_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_EPC1_REG ------------------------------ */ -#define USB_USB_EPC1_REG_USB_EP_Pos (0UL) /*!< USB USB_EPC1_REG: USB_EP (Bit 0) */ -#define USB_USB_EPC1_REG_USB_EP_Msk (0xfUL) /*!< USB USB_EPC1_REG: USB_EP (Bitfield-Mask: 0x0f) */ -#define USB_USB_EPC1_REG_USB_EP_EN_Pos (4UL) /*!< USB USB_EPC1_REG: USB_EP_EN (Bit 4) */ -#define USB_USB_EPC1_REG_USB_EP_EN_Msk (0x10UL) /*!< USB USB_EPC1_REG: USB_EP_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC1_REG_USB_ISO_Pos (5UL) /*!< USB USB_EPC1_REG: USB_ISO (Bit 5) */ -#define USB_USB_EPC1_REG_USB_ISO_Msk (0x20UL) /*!< USB USB_EPC1_REG: USB_ISO (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC1_REG_USB_STALL_Pos (7UL) /*!< USB USB_EPC1_REG: USB_STALL (Bit 7) */ -#define USB_USB_EPC1_REG_USB_STALL_Msk (0x80UL) /*!< USB USB_EPC1_REG: USB_STALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXD1_REG ------------------------------ */ -#define USB_USB_TXD1_REG_USB_TXFD_Pos (0UL) /*!< USB USB_TXD1_REG: USB_TXFD (Bit 0) */ -#define USB_USB_TXD1_REG_USB_TXFD_Msk (0xffUL) /*!< USB USB_TXD1_REG: USB_TXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_TXS1_REG ------------------------------ */ -#define USB_USB_TXS1_REG_USB_TCOUNT_Pos (0UL) /*!< USB USB_TXS1_REG: USB_TCOUNT (Bit 0) */ -#define USB_USB_TXS1_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB USB_TXS1_REG: USB_TCOUNT (Bitfield-Mask: 0x1f) */ -#define USB_USB_TXS1_REG_USB_TX_DONE_Pos (5UL) /*!< USB USB_TXS1_REG: USB_TX_DONE (Bit 5) */ -#define USB_USB_TXS1_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB USB_TXS1_REG: USB_TX_DONE (Bitfield-Mask: 0x01) */ -#define USB_USB_TXS1_REG_USB_ACK_STAT_Pos (6UL) /*!< USB USB_TXS1_REG: USB_ACK_STAT (Bit 6) */ -#define USB_USB_TXS1_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB USB_TXS1_REG: USB_ACK_STAT (Bitfield-Mask: 0x01) */ -#define USB_USB_TXS1_REG_USB_TX_URUN_Pos (7UL) /*!< USB USB_TXS1_REG: USB_TX_URUN (Bit 7) */ -#define USB_USB_TXS1_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB USB_TXS1_REG: USB_TX_URUN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXC1_REG ------------------------------ */ -#define USB_USB_TXC1_REG_USB_TX_EN_Pos (0UL) /*!< USB USB_TXC1_REG: USB_TX_EN (Bit 0) */ -#define USB_USB_TXC1_REG_USB_TX_EN_Msk (0x1UL) /*!< USB USB_TXC1_REG: USB_TX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC1_REG_USB_LAST_Pos (1UL) /*!< USB USB_TXC1_REG: USB_LAST (Bit 1) */ -#define USB_USB_TXC1_REG_USB_LAST_Msk (0x2UL) /*!< USB USB_TXC1_REG: USB_LAST (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB USB_TXC1_REG: USB_TOGGLE_TX (Bit 2) */ -#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB USB_TXC1_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC1_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_TXC1_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_TXC1_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_TXC1_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC1_REG_USB_RFF_Pos (4UL) /*!< USB USB_TXC1_REG: USB_RFF (Bit 4) */ -#define USB_USB_TXC1_REG_USB_RFF_Msk (0x10UL) /*!< USB USB_TXC1_REG: USB_RFF (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC1_REG_USB_TFWL_Pos (5UL) /*!< USB USB_TXC1_REG: USB_TFWL (Bit 5) */ -#define USB_USB_TXC1_REG_USB_TFWL_Msk (0x60UL) /*!< USB USB_TXC1_REG: USB_TFWL (Bitfield-Mask: 0x03) */ -#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB USB_TXC1_REG: USB_IGN_ISOMSK (Bit 7) */ -#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB USB_TXC1_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_EPC2_REG ------------------------------ */ -#define USB_USB_EPC2_REG_USB_EP_Pos (0UL) /*!< USB USB_EPC2_REG: USB_EP (Bit 0) */ -#define USB_USB_EPC2_REG_USB_EP_Msk (0xfUL) /*!< USB USB_EPC2_REG: USB_EP (Bitfield-Mask: 0x0f) */ -#define USB_USB_EPC2_REG_USB_EP_EN_Pos (4UL) /*!< USB USB_EPC2_REG: USB_EP_EN (Bit 4) */ -#define USB_USB_EPC2_REG_USB_EP_EN_Msk (0x10UL) /*!< USB USB_EPC2_REG: USB_EP_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC2_REG_USB_ISO_Pos (5UL) /*!< USB USB_EPC2_REG: USB_ISO (Bit 5) */ -#define USB_USB_EPC2_REG_USB_ISO_Msk (0x20UL) /*!< USB USB_EPC2_REG: USB_ISO (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC2_REG_USB_STALL_Pos (7UL) /*!< USB USB_EPC2_REG: USB_STALL (Bit 7) */ -#define USB_USB_EPC2_REG_USB_STALL_Msk (0x80UL) /*!< USB USB_EPC2_REG: USB_STALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXD1_REG ------------------------------ */ -#define USB_USB_RXD1_REG_USB_RXFD_Pos (0UL) /*!< USB USB_RXD1_REG: USB_RXFD (Bit 0) */ -#define USB_USB_RXD1_REG_USB_RXFD_Msk (0xffUL) /*!< USB USB_RXD1_REG: USB_RXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_RXS1_REG ------------------------------ */ -#define USB_USB_RXS1_REG_USB_RCOUNT_Pos (0UL) /*!< USB USB_RXS1_REG: USB_RCOUNT (Bit 0) */ -#define USB_USB_RXS1_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB USB_RXS1_REG: USB_RCOUNT (Bitfield-Mask: 0x0f) */ -#define USB_USB_RXS1_REG_USB_RX_LAST_Pos (4UL) /*!< USB USB_RXS1_REG: USB_RX_LAST (Bit 4) */ -#define USB_USB_RXS1_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB USB_RXS1_REG: USB_RX_LAST (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB USB_RXS1_REG: USB_TOGGLE_RX (Bit 5) */ -#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB USB_RXS1_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS1_REG_USB_SETUP_Pos (6UL) /*!< USB USB_RXS1_REG: USB_SETUP (Bit 6) */ -#define USB_USB_RXS1_REG_USB_SETUP_Msk (0x40UL) /*!< USB USB_RXS1_REG: USB_SETUP (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS1_REG_USB_RX_ERR_Pos (7UL) /*!< USB USB_RXS1_REG: USB_RX_ERR (Bit 7) */ -#define USB_USB_RXS1_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB USB_RXS1_REG: USB_RX_ERR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXC1_REG ------------------------------ */ -#define USB_USB_RXC1_REG_USB_RX_EN_Pos (0UL) /*!< USB USB_RXC1_REG: USB_RX_EN (Bit 0) */ -#define USB_USB_RXC1_REG_USB_RX_EN_Msk (0x1UL) /*!< USB USB_RXC1_REG: USB_RX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC1_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB USB_RXC1_REG: USB_IGN_SETUP (Bit 2) */ -#define USB_USB_RXC1_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB USB_RXC1_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC1_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_RXC1_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_RXC1_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_RXC1_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC1_REG_USB_RFWL_Pos (5UL) /*!< USB USB_RXC1_REG: USB_RFWL (Bit 5) */ -#define USB_USB_RXC1_REG_USB_RFWL_Msk (0x60UL) /*!< USB USB_RXC1_REG: USB_RFWL (Bitfield-Mask: 0x03) */ - -/* ------------------------------ USB_USB_EPC3_REG ------------------------------ */ -#define USB_USB_EPC3_REG_USB_EP_Pos (0UL) /*!< USB USB_EPC3_REG: USB_EP (Bit 0) */ -#define USB_USB_EPC3_REG_USB_EP_Msk (0xfUL) /*!< USB USB_EPC3_REG: USB_EP (Bitfield-Mask: 0x0f) */ -#define USB_USB_EPC3_REG_USB_EP_EN_Pos (4UL) /*!< USB USB_EPC3_REG: USB_EP_EN (Bit 4) */ -#define USB_USB_EPC3_REG_USB_EP_EN_Msk (0x10UL) /*!< USB USB_EPC3_REG: USB_EP_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC3_REG_USB_ISO_Pos (5UL) /*!< USB USB_EPC3_REG: USB_ISO (Bit 5) */ -#define USB_USB_EPC3_REG_USB_ISO_Msk (0x20UL) /*!< USB USB_EPC3_REG: USB_ISO (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC3_REG_USB_STALL_Pos (7UL) /*!< USB USB_EPC3_REG: USB_STALL (Bit 7) */ -#define USB_USB_EPC3_REG_USB_STALL_Msk (0x80UL) /*!< USB USB_EPC3_REG: USB_STALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXD2_REG ------------------------------ */ -#define USB_USB_TXD2_REG_USB_TXFD_Pos (0UL) /*!< USB USB_TXD2_REG: USB_TXFD (Bit 0) */ -#define USB_USB_TXD2_REG_USB_TXFD_Msk (0xffUL) /*!< USB USB_TXD2_REG: USB_TXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_TXS2_REG ------------------------------ */ -#define USB_USB_TXS2_REG_USB_TCOUNT_Pos (0UL) /*!< USB USB_TXS2_REG: USB_TCOUNT (Bit 0) */ -#define USB_USB_TXS2_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB USB_TXS2_REG: USB_TCOUNT (Bitfield-Mask: 0x1f) */ -#define USB_USB_TXS2_REG_USB_TX_DONE_Pos (5UL) /*!< USB USB_TXS2_REG: USB_TX_DONE (Bit 5) */ -#define USB_USB_TXS2_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB USB_TXS2_REG: USB_TX_DONE (Bitfield-Mask: 0x01) */ -#define USB_USB_TXS2_REG_USB_ACK_STAT_Pos (6UL) /*!< USB USB_TXS2_REG: USB_ACK_STAT (Bit 6) */ -#define USB_USB_TXS2_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB USB_TXS2_REG: USB_ACK_STAT (Bitfield-Mask: 0x01) */ -#define USB_USB_TXS2_REG_USB_TX_URUN_Pos (7UL) /*!< USB USB_TXS2_REG: USB_TX_URUN (Bit 7) */ -#define USB_USB_TXS2_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB USB_TXS2_REG: USB_TX_URUN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXC2_REG ------------------------------ */ -#define USB_USB_TXC2_REG_USB_TX_EN_Pos (0UL) /*!< USB USB_TXC2_REG: USB_TX_EN (Bit 0) */ -#define USB_USB_TXC2_REG_USB_TX_EN_Msk (0x1UL) /*!< USB USB_TXC2_REG: USB_TX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC2_REG_USB_LAST_Pos (1UL) /*!< USB USB_TXC2_REG: USB_LAST (Bit 1) */ -#define USB_USB_TXC2_REG_USB_LAST_Msk (0x2UL) /*!< USB USB_TXC2_REG: USB_LAST (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB USB_TXC2_REG: USB_TOGGLE_TX (Bit 2) */ -#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB USB_TXC2_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC2_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_TXC2_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_TXC2_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_TXC2_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC2_REG_USB_RFF_Pos (4UL) /*!< USB USB_TXC2_REG: USB_RFF (Bit 4) */ -#define USB_USB_TXC2_REG_USB_RFF_Msk (0x10UL) /*!< USB USB_TXC2_REG: USB_RFF (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC2_REG_USB_TFWL_Pos (5UL) /*!< USB USB_TXC2_REG: USB_TFWL (Bit 5) */ -#define USB_USB_TXC2_REG_USB_TFWL_Msk (0x60UL) /*!< USB USB_TXC2_REG: USB_TFWL (Bitfield-Mask: 0x03) */ -#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB USB_TXC2_REG: USB_IGN_ISOMSK (Bit 7) */ -#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB USB_TXC2_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_EPC4_REG ------------------------------ */ -#define USB_USB_EPC4_REG_USB_EP_Pos (0UL) /*!< USB USB_EPC4_REG: USB_EP (Bit 0) */ -#define USB_USB_EPC4_REG_USB_EP_Msk (0xfUL) /*!< USB USB_EPC4_REG: USB_EP (Bitfield-Mask: 0x0f) */ -#define USB_USB_EPC4_REG_USB_EP_EN_Pos (4UL) /*!< USB USB_EPC4_REG: USB_EP_EN (Bit 4) */ -#define USB_USB_EPC4_REG_USB_EP_EN_Msk (0x10UL) /*!< USB USB_EPC4_REG: USB_EP_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC4_REG_USB_ISO_Pos (5UL) /*!< USB USB_EPC4_REG: USB_ISO (Bit 5) */ -#define USB_USB_EPC4_REG_USB_ISO_Msk (0x20UL) /*!< USB USB_EPC4_REG: USB_ISO (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC4_REG_USB_STALL_Pos (7UL) /*!< USB USB_EPC4_REG: USB_STALL (Bit 7) */ -#define USB_USB_EPC4_REG_USB_STALL_Msk (0x80UL) /*!< USB USB_EPC4_REG: USB_STALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXD2_REG ------------------------------ */ -#define USB_USB_RXD2_REG_USB_RXFD_Pos (0UL) /*!< USB USB_RXD2_REG: USB_RXFD (Bit 0) */ -#define USB_USB_RXD2_REG_USB_RXFD_Msk (0xffUL) /*!< USB USB_RXD2_REG: USB_RXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_RXS2_REG ------------------------------ */ -#define USB_USB_RXS2_REG_USB_RCOUNT_Pos (0UL) /*!< USB USB_RXS2_REG: USB_RCOUNT (Bit 0) */ -#define USB_USB_RXS2_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB USB_RXS2_REG: USB_RCOUNT (Bitfield-Mask: 0x0f) */ -#define USB_USB_RXS2_REG_USB_RX_LAST_Pos (4UL) /*!< USB USB_RXS2_REG: USB_RX_LAST (Bit 4) */ -#define USB_USB_RXS2_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB USB_RXS2_REG: USB_RX_LAST (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB USB_RXS2_REG: USB_TOGGLE_RX (Bit 5) */ -#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB USB_RXS2_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS2_REG_USB_SETUP_Pos (6UL) /*!< USB USB_RXS2_REG: USB_SETUP (Bit 6) */ -#define USB_USB_RXS2_REG_USB_SETUP_Msk (0x40UL) /*!< USB USB_RXS2_REG: USB_SETUP (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS2_REG_USB_RX_ERR_Pos (7UL) /*!< USB USB_RXS2_REG: USB_RX_ERR (Bit 7) */ -#define USB_USB_RXS2_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB USB_RXS2_REG: USB_RX_ERR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXC2_REG ------------------------------ */ -#define USB_USB_RXC2_REG_USB_RX_EN_Pos (0UL) /*!< USB USB_RXC2_REG: USB_RX_EN (Bit 0) */ -#define USB_USB_RXC2_REG_USB_RX_EN_Msk (0x1UL) /*!< USB USB_RXC2_REG: USB_RX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC2_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB USB_RXC2_REG: USB_IGN_SETUP (Bit 2) */ -#define USB_USB_RXC2_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB USB_RXC2_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC2_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_RXC2_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_RXC2_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_RXC2_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC2_REG_USB_RFWL_Pos (5UL) /*!< USB USB_RXC2_REG: USB_RFWL (Bit 5) */ -#define USB_USB_RXC2_REG_USB_RFWL_Msk (0x60UL) /*!< USB USB_RXC2_REG: USB_RFWL (Bitfield-Mask: 0x03) */ - -/* ------------------------------ USB_USB_EPC5_REG ------------------------------ */ -#define USB_USB_EPC5_REG_USB_EP_Pos (0UL) /*!< USB USB_EPC5_REG: USB_EP (Bit 0) */ -#define USB_USB_EPC5_REG_USB_EP_Msk (0xfUL) /*!< USB USB_EPC5_REG: USB_EP (Bitfield-Mask: 0x0f) */ -#define USB_USB_EPC5_REG_USB_EP_EN_Pos (4UL) /*!< USB USB_EPC5_REG: USB_EP_EN (Bit 4) */ -#define USB_USB_EPC5_REG_USB_EP_EN_Msk (0x10UL) /*!< USB USB_EPC5_REG: USB_EP_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC5_REG_USB_ISO_Pos (5UL) /*!< USB USB_EPC5_REG: USB_ISO (Bit 5) */ -#define USB_USB_EPC5_REG_USB_ISO_Msk (0x20UL) /*!< USB USB_EPC5_REG: USB_ISO (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC5_REG_USB_STALL_Pos (7UL) /*!< USB USB_EPC5_REG: USB_STALL (Bit 7) */ -#define USB_USB_EPC5_REG_USB_STALL_Msk (0x80UL) /*!< USB USB_EPC5_REG: USB_STALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXD3_REG ------------------------------ */ -#define USB_USB_TXD3_REG_USB_TXFD_Pos (0UL) /*!< USB USB_TXD3_REG: USB_TXFD (Bit 0) */ -#define USB_USB_TXD3_REG_USB_TXFD_Msk (0xffUL) /*!< USB USB_TXD3_REG: USB_TXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_TXS3_REG ------------------------------ */ -#define USB_USB_TXS3_REG_USB_TCOUNT_Pos (0UL) /*!< USB USB_TXS3_REG: USB_TCOUNT (Bit 0) */ -#define USB_USB_TXS3_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB USB_TXS3_REG: USB_TCOUNT (Bitfield-Mask: 0x1f) */ -#define USB_USB_TXS3_REG_USB_TX_DONE_Pos (5UL) /*!< USB USB_TXS3_REG: USB_TX_DONE (Bit 5) */ -#define USB_USB_TXS3_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB USB_TXS3_REG: USB_TX_DONE (Bitfield-Mask: 0x01) */ -#define USB_USB_TXS3_REG_USB_ACK_STAT_Pos (6UL) /*!< USB USB_TXS3_REG: USB_ACK_STAT (Bit 6) */ -#define USB_USB_TXS3_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB USB_TXS3_REG: USB_ACK_STAT (Bitfield-Mask: 0x01) */ -#define USB_USB_TXS3_REG_USB_TX_URUN_Pos (7UL) /*!< USB USB_TXS3_REG: USB_TX_URUN (Bit 7) */ -#define USB_USB_TXS3_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB USB_TXS3_REG: USB_TX_URUN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_TXC3_REG ------------------------------ */ -#define USB_USB_TXC3_REG_USB_TX_EN_Pos (0UL) /*!< USB USB_TXC3_REG: USB_TX_EN (Bit 0) */ -#define USB_USB_TXC3_REG_USB_TX_EN_Msk (0x1UL) /*!< USB USB_TXC3_REG: USB_TX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC3_REG_USB_LAST_Pos (1UL) /*!< USB USB_TXC3_REG: USB_LAST (Bit 1) */ -#define USB_USB_TXC3_REG_USB_LAST_Msk (0x2UL) /*!< USB USB_TXC3_REG: USB_LAST (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB USB_TXC3_REG: USB_TOGGLE_TX (Bit 2) */ -#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB USB_TXC3_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC3_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_TXC3_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_TXC3_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_TXC3_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC3_REG_USB_RFF_Pos (4UL) /*!< USB USB_TXC3_REG: USB_RFF (Bit 4) */ -#define USB_USB_TXC3_REG_USB_RFF_Msk (0x10UL) /*!< USB USB_TXC3_REG: USB_RFF (Bitfield-Mask: 0x01) */ -#define USB_USB_TXC3_REG_USB_TFWL_Pos (5UL) /*!< USB USB_TXC3_REG: USB_TFWL (Bit 5) */ -#define USB_USB_TXC3_REG_USB_TFWL_Msk (0x60UL) /*!< USB USB_TXC3_REG: USB_TFWL (Bitfield-Mask: 0x03) */ -#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB USB_TXC3_REG: USB_IGN_ISOMSK (Bit 7) */ -#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB USB_TXC3_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_EPC6_REG ------------------------------ */ -#define USB_USB_EPC6_REG_USB_EP_Pos (0UL) /*!< USB USB_EPC6_REG: USB_EP (Bit 0) */ -#define USB_USB_EPC6_REG_USB_EP_Msk (0xfUL) /*!< USB USB_EPC6_REG: USB_EP (Bitfield-Mask: 0x0f) */ -#define USB_USB_EPC6_REG_USB_EP_EN_Pos (4UL) /*!< USB USB_EPC6_REG: USB_EP_EN (Bit 4) */ -#define USB_USB_EPC6_REG_USB_EP_EN_Msk (0x10UL) /*!< USB USB_EPC6_REG: USB_EP_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC6_REG_USB_ISO_Pos (5UL) /*!< USB USB_EPC6_REG: USB_ISO (Bit 5) */ -#define USB_USB_EPC6_REG_USB_ISO_Msk (0x20UL) /*!< USB USB_EPC6_REG: USB_ISO (Bitfield-Mask: 0x01) */ -#define USB_USB_EPC6_REG_USB_STALL_Pos (7UL) /*!< USB USB_EPC6_REG: USB_STALL (Bit 7) */ -#define USB_USB_EPC6_REG_USB_STALL_Msk (0x80UL) /*!< USB USB_EPC6_REG: USB_STALL (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXD3_REG ------------------------------ */ -#define USB_USB_RXD3_REG_USB_RXFD_Pos (0UL) /*!< USB USB_RXD3_REG: USB_RXFD (Bit 0) */ -#define USB_USB_RXD3_REG_USB_RXFD_Msk (0xffUL) /*!< USB USB_RXD3_REG: USB_RXFD (Bitfield-Mask: 0xff) */ - -/* ------------------------------ USB_USB_RXS3_REG ------------------------------ */ -#define USB_USB_RXS3_REG_USB_RCOUNT_Pos (0UL) /*!< USB USB_RXS3_REG: USB_RCOUNT (Bit 0) */ -#define USB_USB_RXS3_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB USB_RXS3_REG: USB_RCOUNT (Bitfield-Mask: 0x0f) */ -#define USB_USB_RXS3_REG_USB_RX_LAST_Pos (4UL) /*!< USB USB_RXS3_REG: USB_RX_LAST (Bit 4) */ -#define USB_USB_RXS3_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB USB_RXS3_REG: USB_RX_LAST (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB USB_RXS3_REG: USB_TOGGLE_RX (Bit 5) */ -#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB USB_RXS3_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS3_REG_USB_SETUP_Pos (6UL) /*!< USB USB_RXS3_REG: USB_SETUP (Bit 6) */ -#define USB_USB_RXS3_REG_USB_SETUP_Msk (0x40UL) /*!< USB USB_RXS3_REG: USB_SETUP (Bitfield-Mask: 0x01) */ -#define USB_USB_RXS3_REG_USB_RX_ERR_Pos (7UL) /*!< USB USB_RXS3_REG: USB_RX_ERR (Bit 7) */ -#define USB_USB_RXS3_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB USB_RXS3_REG: USB_RX_ERR (Bitfield-Mask: 0x01) */ - -/* ------------------------------ USB_USB_RXC3_REG ------------------------------ */ -#define USB_USB_RXC3_REG_USB_RX_EN_Pos (0UL) /*!< USB USB_RXC3_REG: USB_RX_EN (Bit 0) */ -#define USB_USB_RXC3_REG_USB_RX_EN_Msk (0x1UL) /*!< USB USB_RXC3_REG: USB_RX_EN (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC3_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB USB_RXC3_REG: USB_IGN_SETUP (Bit 2) */ -#define USB_USB_RXC3_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB USB_RXC3_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC3_REG_USB_FLUSH_Pos (3UL) /*!< USB USB_RXC3_REG: USB_FLUSH (Bit 3) */ -#define USB_USB_RXC3_REG_USB_FLUSH_Msk (0x8UL) /*!< USB USB_RXC3_REG: USB_FLUSH (Bitfield-Mask: 0x01) */ -#define USB_USB_RXC3_REG_USB_RFWL_Pos (5UL) /*!< USB USB_RXC3_REG: USB_RFWL (Bit 5) */ -#define USB_USB_RXC3_REG_USB_RFWL_Msk (0x60UL) /*!< USB USB_RXC3_REG: USB_RFWL (Bitfield-Mask: 0x03) */ - -/* ---------------------------- USB_USB_DMA_CTRL_REG ---------------------------- */ -#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos (0UL) /*!< USB USB_DMA_CTRL_REG: USB_DMA_RX (Bit 0) */ -#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk (0x7UL) /*!< USB USB_DMA_CTRL_REG: USB_DMA_RX (Bitfield-Mask: 0x07) */ -#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos (3UL) /*!< USB USB_DMA_CTRL_REG: USB_DMA_TX (Bit 3) */ -#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk (0x38UL) /*!< USB USB_DMA_CTRL_REG: USB_DMA_TX (Bitfield-Mask: 0x07) */ -#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos (6UL) /*!< USB USB_DMA_CTRL_REG: USB_DMA_EN (Bit 6) */ -#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk (0x40UL) /*!< USB USB_DMA_CTRL_REG: USB_DMA_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------- USB_USB_CHARGER_CTRL_REG -------------------------- */ -#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos (0UL) /*!< USB USB_CHARGER_CTRL_REG: USB_CHARGE_ON (Bit 0) */ -#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk (0x1UL) /*!< USB USB_CHARGER_CTRL_REG: USB_CHARGE_ON (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos (1UL) /*!< USB USB_CHARGER_CTRL_REG: IDP_SRC_ON (Bit 1) */ -#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk (0x2UL) /*!< USB USB_CHARGER_CTRL_REG: IDP_SRC_ON (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos (2UL) /*!< USB USB_CHARGER_CTRL_REG: VDP_SRC_ON (Bit 2) */ -#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk (0x4UL) /*!< USB USB_CHARGER_CTRL_REG: VDP_SRC_ON (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos (3UL) /*!< USB USB_CHARGER_CTRL_REG: VDM_SRC_ON (Bit 3) */ -#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk (0x8UL) /*!< USB USB_CHARGER_CTRL_REG: VDM_SRC_ON (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos (4UL) /*!< USB USB_CHARGER_CTRL_REG: IDP_SINK_ON (Bit 4) */ -#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk (0x10UL) /*!< USB USB_CHARGER_CTRL_REG: IDP_SINK_ON (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos (5UL) /*!< USB USB_CHARGER_CTRL_REG: IDM_SINK_ON (Bit 5) */ -#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk (0x20UL) /*!< USB USB_CHARGER_CTRL_REG: IDM_SINK_ON (Bitfield-Mask: 0x01) */ - -/* -------------------------- USB_USB_CHARGER_STAT_REG -------------------------- */ -#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos (0UL) /*!< USB USB_CHARGER_STAT_REG: USB_DCP_DET (Bit 0) */ -#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk (0x1UL) /*!< USB USB_CHARGER_STAT_REG: USB_DCP_DET (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos (1UL) /*!< USB USB_CHARGER_STAT_REG: USB_CHG_DET (Bit 1) */ -#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk (0x2UL) /*!< USB USB_CHARGER_STAT_REG: USB_CHG_DET (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos (2UL) /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL (Bit 2) */ -#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk (0x4UL) /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos (3UL) /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL (Bit 3) */ -#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk (0x8UL) /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos (4UL) /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL2 (Bit 4) */ -#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk (0x10UL) /*!< USB USB_CHARGER_STAT_REG: USB_DP_VAL2 (Bitfield-Mask: 0x01) */ -#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos (5UL) /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL2 (Bit 5) */ -#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk (0x20UL) /*!< USB USB_CHARGER_STAT_REG: USB_DM_VAL2 (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'WAKEUP' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- WAKEUP_WKUP_CTRL_REG ---------------------------- */ -#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_DEB_VALUE (Bit 0) */ -#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_DEB_VALUE (Bitfield-Mask: 0x3f) */ -#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_SFT_KEYHIT (Bit 6) */ -#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_SFT_KEYHIT (Bitfield-Mask: 0x01) */ -#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bit 7) */ -#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01) */ - -/* -------------------------- WAKEUP_WKUP_RESET_IRQ_REG ------------------------- */ -#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL) /*!< WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bit 0) */ -#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL) /*!< WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bitfield-Mask: 0xffff) */ - -/* -------------------------- WAKEUP_WKUP_SELECT_P0_REG ------------------------- */ -#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL) /*!< WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bit 0) */ -#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffUL) /*!< WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bitfield-Mask: 0xff) */ - -/* -------------------------- WAKEUP_WKUP_SELECT_P1_REG ------------------------- */ -#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL) /*!< WAKEUP WKUP_SELECT_P1_REG: WKUP_SELECT_P1 (Bit 0) */ -#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0xffUL) /*!< WAKEUP WKUP_SELECT_P1_REG: WKUP_SELECT_P1 (Bitfield-Mask: 0xff) */ - -/* -------------------------- WAKEUP_WKUP_SELECT_P2_REG ------------------------- */ -#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Pos (0UL) /*!< WAKEUP WKUP_SELECT_P2_REG: WKUP_SELECT_P2 (Bit 0) */ -#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_SELECT_P2_REG: WKUP_SELECT_P2 (Bitfield-Mask: 0x1f) */ - -/* -------------------------- WAKEUP_WKUP_SELECT_P3_REG ------------------------- */ -#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Pos (0UL) /*!< WAKEUP WKUP_SELECT_P3_REG: WKUP_SELECT_P3 (Bit 0) */ -#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Msk (0xffUL) /*!< WAKEUP WKUP_SELECT_P3_REG: WKUP_SELECT_P3 (Bitfield-Mask: 0xff) */ - -/* -------------------------- WAKEUP_WKUP_SELECT_P4_REG ------------------------- */ -#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Pos (0UL) /*!< WAKEUP WKUP_SELECT_P4_REG: WKUP_SELECT_P4 (Bit 0) */ -#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Msk (0xffUL) /*!< WAKEUP WKUP_SELECT_P4_REG: WKUP_SELECT_P4 (Bitfield-Mask: 0xff) */ - -/* --------------------------- WAKEUP_WKUP_POL_P0_REG --------------------------- */ -#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL) /*!< WAKEUP WKUP_POL_P0_REG: WKUP_POL_P0 (Bit 0) */ -#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffUL) /*!< WAKEUP WKUP_POL_P0_REG: WKUP_POL_P0 (Bitfield-Mask: 0xff) */ - -/* --------------------------- WAKEUP_WKUP_POL_P1_REG --------------------------- */ -#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL) /*!< WAKEUP WKUP_POL_P1_REG: WKUP_POL_P1 (Bit 0) */ -#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0xffUL) /*!< WAKEUP WKUP_POL_P1_REG: WKUP_POL_P1 (Bitfield-Mask: 0xff) */ - -/* --------------------------- WAKEUP_WKUP_POL_P2_REG --------------------------- */ -#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Pos (0UL) /*!< WAKEUP WKUP_POL_P2_REG: WKUP_POL_P2 (Bit 0) */ -#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_POL_P2_REG: WKUP_POL_P2 (Bitfield-Mask: 0x1f) */ - -/* --------------------------- WAKEUP_WKUP_POL_P3_REG --------------------------- */ -#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Pos (0UL) /*!< WAKEUP WKUP_POL_P3_REG: WKUP_POL_P3 (Bit 0) */ -#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Msk (0xffUL) /*!< WAKEUP WKUP_POL_P3_REG: WKUP_POL_P3 (Bitfield-Mask: 0xff) */ - -/* --------------------------- WAKEUP_WKUP_POL_P4_REG --------------------------- */ -#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Pos (0UL) /*!< WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bit 0) */ -#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Msk (0xffUL) /*!< WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bitfield-Mask: 0xff) */ - -/* -------------------------- WAKEUP_WKUP_STATUS_0_REG -------------------------- */ -#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Pos (0UL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bit 0) */ -#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Msk (0xffUL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bitfield-Mask: 0xff) */ -#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Pos (8UL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bit 8) */ -#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Msk (0xff00UL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bitfield-Mask: 0xff) */ - -/* -------------------------- WAKEUP_WKUP_STATUS_1_REG -------------------------- */ -#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Pos (0UL) /*!< WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bit 0) */ -#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bitfield-Mask: 0x1f) */ - -/* -------------------------- WAKEUP_WKUP_STATUS_2_REG -------------------------- */ -#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Pos (0UL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bit 0) */ -#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Msk (0xffUL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bitfield-Mask: 0xff) */ -#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Pos (8UL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bit 8) */ -#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Msk (0xff00UL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bitfield-Mask: 0xff) */ - -/* --------------------------- WAKEUP_WKUP_CLEAR_0_REG -------------------------- */ -#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Pos (0UL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bit 0) */ -#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Msk (0xffUL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bitfield-Mask: 0xff) */ -#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Pos (8UL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bit 8) */ -#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Msk (0xff00UL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bitfield-Mask: 0xff) */ - -/* --------------------------- WAKEUP_WKUP_CLEAR_1_REG -------------------------- */ -#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Pos (0UL) /*!< WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bit 0) */ -#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bitfield-Mask: 0x1f) */ - -/* --------------------------- WAKEUP_WKUP_CLEAR_2_REG -------------------------- */ -#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Pos (0UL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bit 0) */ -#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Msk (0xffUL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bitfield-Mask: 0xff) */ -#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Pos (8UL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bit 8) */ -#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Msk (0xff00UL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bitfield-Mask: 0xff) */ - -/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P0_REG ------------------------ */ -#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bit 0) */ -#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xff) */ - -/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P1_REG ------------------------ */ -#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bit 0) */ -#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0xff) */ - -/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P2_REG ------------------------ */ -#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bit 0) */ -#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bitfield-Mask: 0x1f) */ - -/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P3_REG ------------------------ */ -#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bit 0) */ -#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bitfield-Mask: 0xff) */ - -/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P4_REG ------------------------ */ -#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bit 0) */ -#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'WDOG' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------ WDOG_WATCHDOG_REG ----------------------------- */ -#define WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL) /*!< WDOG WATCHDOG_REG: WDOG_VAL (Bit 0) */ -#define WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0xffUL) /*!< WDOG WATCHDOG_REG: WDOG_VAL (Bitfield-Mask: 0xff) */ -#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (8UL) /*!< WDOG WATCHDOG_REG: WDOG_VAL_NEG (Bit 8) */ -#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x100UL) /*!< WDOG WATCHDOG_REG: WDOG_VAL_NEG (Bitfield-Mask: 0x01) */ -#define WDOG_WATCHDOG_REG_WDOG_WEN_Pos (9UL) /*!< WDOG WATCHDOG_REG: WDOG_WEN (Bit 9) */ -#define WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xfe00UL) /*!< WDOG WATCHDOG_REG: WDOG_WEN (Bitfield-Mask: 0x7f) */ - -/* --------------------------- WDOG_WATCHDOG_CTRL_REG --------------------------- */ -#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL) /*!< WDOG WATCHDOG_CTRL_REG: NMI_RST (Bit 0) */ -#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL) /*!< WDOG WATCHDOG_CTRL_REG: NMI_RST (Bitfield-Mask: 0x01) */ - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define AES_HASH_BASE 0x40020000UL -#define ANAMISC_BASE 0x50001B00UL -#define APU_BASE 0x50004000UL -#define BLE_BASE 0x40000000UL -#define CACHE_BASE 0x400C3000UL -#define CHIP_VERSION_BASE 0x50003200UL -#define COEX_BASE 0x50002F00UL -#define CRG_PER_BASE 0x50001C00UL -#define CRG_TOP_BASE 0x50000000UL -#define DCDC_BASE 0x50000080UL -#define DEM_BASE 0x50002E00UL -#define DMA_BASE 0x50003500UL -#define ECC_BASE 0x50006000UL -#define FTDF_BASE 0x40080000UL -#define GP_TIMERS_BASE 0x50003400UL -#define GPADC_BASE 0x50001900UL -#define GPIO_BASE 0x50003000UL -#define GPREG_BASE 0x50003300UL -#define I2C_BASE 0x50001400UL -#define I2C2_BASE 0x50001500UL -#define IR_BASE 0x50001700UL -#define KBSCAN_BASE 0x50001600UL -#define OTPC_BASE 0x07F40000UL -#define PATCH_BASE 0x40050000UL -#define PLLDIG_BASE 0x50002D00UL -#define QSPIC_BASE 0x0C000000UL -#define QUAD_BASE 0x50001A00UL -#define RFCU_BASE 0x50002000UL -#define RFCU_POWER_BASE 0x50002200UL -#define RFPT_BASE 0x50003600UL -#define SPI_BASE 0x50001200UL -#define SPI2_BASE 0x50001300UL -#define TIMER1_BASE 0x50000200UL -#define TRNG_BASE 0x50005000UL -#define UART_BASE 0x50001000UL -#define UART2_BASE 0x50001100UL -#define USB_BASE 0x50001800UL -#define WAKEUP_BASE 0x50000100UL -#define WDOG_BASE 0x50003100UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define AES_HASH ((AES_HASH_Type *) AES_HASH_BASE) -#define ANAMISC ((ANAMISC_Type *) ANAMISC_BASE) -#define APU ((APU_Type *) APU_BASE) -#define BLE ((BLE_Type *) BLE_BASE) -#define CACHE ((CACHE_Type *) CACHE_BASE) -#define CHIP_VERSION ((CHIP_VERSION_Type *) CHIP_VERSION_BASE) -#define COEX ((COEX_Type *) COEX_BASE) -#define CRG_PER ((CRG_PER_Type *) CRG_PER_BASE) -#define CRG_TOP ((CRG_TOP_Type *) CRG_TOP_BASE) -#define DCDC ((DCDC_Type *) DCDC_BASE) -#define DEM ((DEM_Type *) DEM_BASE) -#define DMA ((DMA_Type *) DMA_BASE) -#define ECC ((ECC_Type *) ECC_BASE) -#define FTDF ((FTDF_Type *) FTDF_BASE) -#define GP_TIMERS ((GP_TIMERS_Type *) GP_TIMERS_BASE) -#define GPADC ((GPADC_Type *) GPADC_BASE) -#define GPIO ((GPIO_Type *) GPIO_BASE) -#define GPREG ((GPREG_Type *) GPREG_BASE) -#define I2C ((I2C_Type *) I2C_BASE) -#define I2C2 ((I2C2_Type *) I2C2_BASE) -#define IR ((IR_Type *) IR_BASE) -#define KBSCAN ((KBSCAN_Type *) KBSCAN_BASE) -#define OTPC ((OTPC_Type *) OTPC_BASE) -#define PATCH ((PATCH_Type *) PATCH_BASE) -#define PLLDIG ((PLLDIG_Type *) PLLDIG_BASE) -#define QSPIC ((QSPIC_Type *) QSPIC_BASE) -#define QUAD ((QUAD_Type *) QUAD_BASE) -#define RFCU ((RFCU_Type *) RFCU_BASE) -#define RFCU_POWER ((RFCU_POWER_Type *) RFCU_POWER_BASE) -#define RFPT ((RFPT_Type *) RFPT_BASE) -#define SPI ((SPI_Type *) SPI_BASE) -#define SPI2 ((SPI2_Type *) SPI2_BASE) -#define TIMER1 ((TIMER1_Type *) TIMER1_BASE) -#define TRNG ((TRNG_Type *) TRNG_BASE) -#define UART ((UART_Type *) UART_BASE) -#define UART2 ((UART2_Type *) UART2_BASE) -#define USB ((USB_Type *) USB_BASE) -#define WAKEUP ((WAKEUP_Type *) WAKEUP_BASE) -#define WDOG ((WDOG_Type *) WDOG_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group DA14680BB */ -/** @} */ /* End of group Dialog */ - -#ifdef __cplusplus -} -#endif - - -#endif /* DA14680BB_H */ - diff --git a/third_party/dialog/DialogSDK/bsp/include/cmsis_gcc.h b/third_party/dialog/DialogSDK/bsp/include/cmsis_gcc.h deleted file mode 100644 index bb89fbba9..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/core_cm0.h b/third_party/dialog/DialogSDK/bsp/include/core_cm0.h deleted file mode 100644 index 21ae4f9ba..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ -#include "sdk_defs.h" /* Declares IRQn_Type */ -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/third_party/dialog/DialogSDK/bsp/include/core_cmFunc.h b/third_party/dialog/DialogSDK/bsp/include/core_cmFunc.h deleted file mode 100644 index 652a48af0..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/core_cmInstr.h b/third_party/dialog/DialogSDK/bsp/include/core_cmInstr.h deleted file mode 100644 index f474b0e6f..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/interrupts.h b/third_party/dialog/DialogSDK/bsp/include/interrupts.h deleted file mode 100644 index af902cce2..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/interrupts.h +++ /dev/null @@ -1,151 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup INTERRUPTS - * - * \brief Interrupt priority configuration - * - * \{ - */ - -/** - ***************************************************************************************** - * - * @file interrupts.h - * - * @brief Interrupt priority configuration - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef INTERRUPTS_H_ -#define INTERRUPTS_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Setup interrupt priorities - * - * When CPU is reset all interrupts have some priority setup. - * Reset -3 - * NMI -2 - * HardFault -1 - * All other interrupts have configurable priority that is set to 0. - * If some interrupts should have priority other then default, this function should be called. - * Argument \p prios can specify only those interrupts that need to have value other than default. - * For memory efficiency table with priorities for each interrupt consist of interrupt priority - * tag PRIORITY_x followed by interrupts that should have this priority, interrupts names are from - * enum IRQn_Type. - * - * \note If interrupt priorities do not need to be changed dynamically at runtime, best way to - * specify static configuration is to create table named __dialog_interrupt_priorities that will - * be used automatically at startup. - * - * Most convenient way to prepare such table is to use macros like in example below: - * - * \code{.c} - * INTERRUPT_PRIORITY_CONFIG_START(__dialog_interrupt_priorities) - * PRIORITY_0, // Start interrupts with priority 0 (highest) - * SVCall_IRQn, - * PendSV_IRQn, - * SysTick_IRQn, - * PRIORITY_1, // Start interrupts with priority 1 - * BLE_WAKEUP_LP_IRQn, - * BLE_GEN_IRQn, - * FTDF_WAKEUP_IRQn, - * FTDF_GEN_IRQn, - * PRIORITY_2, - * SRC_IN_IRQn, - * SRC_OUT_IRQn, - * PRIORITY_3, - * UART_IRQn, - * UART2_IRQn, - * INTERRUPT_PRIORITY_CONFIG_END - * \endcode - * - * Table __dialog_interrupt_priorities can now be used to call this function. - * Table can specify all interrupts or only those that need to be changed. - * - * \param [in] prios table with interrupts and priorities to setup - * - */ -void set_interrupt_priorities(const int8_t prios[]); - -/** - * \brief Check whether running in interrupt context. - * - * \return true if the CPU is serving an interrupt. - */ -static inline bool in_interrupt(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0; -} - - -/** - * \brief Default interrupt priorities table. - * - */ -extern const int8_t __dialog_interrupt_priorities[]; - - -#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && (dg_configUSE_AUTO_CHIP_DETECTION != 1) - #define LAST_IRQn PLL_LOCK_IRQn -#else - #define LAST_IRQn RESERVED31_IRQn -#endif - -/* - * Following macros allow easy way to build table with interrupt priorities. - * See example in set_interrupt_priorities function description. - */ -#define INTERRUPT_PRIORITY_CONFIG_START(name) const int8_t name[] = { -#define PRIORITY_0 (LAST_IRQn + 1) -#define PRIORITY_1 (LAST_IRQn + 2) -#define PRIORITY_2 (LAST_IRQn + 3) -#define PRIORITY_3 (LAST_IRQn + 4) -#define PRIORITY_TABLE_END (LAST_IRQn + 5) -#define INTERRUPT_PRIORITY_CONFIG_END PRIORITY_TABLE_END }; - -#ifdef __cplusplus -} -#endif - -#endif /* INTERRUPTS_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h b/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h deleted file mode 100644 index 587ed989b..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h +++ /dev/null @@ -1,812 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup PLATFORM - * - * \brief Platform definitions - * - * \{ - */ - -/** - ***************************************************************************************** - * - * @file sdk_defs.h - * - * @brief Central include header file with platform definitions. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef __SDK_DEFS_H__ -#define __SDK_DEFS_H__ - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#ifdef __GNUC__ -# define GCC_VERSION (__GNUC__ * 10000 \ - + __GNUC_MINOR__ * 100 \ - + __GNUC_PATCHLEVEL__) -/* assert gcc version is at least 4.9.3 */ -# if GCC_VERSION < 40903 -# error "Please use gcc version 4.9.3 or newer!" -# endif -#endif - -#if (dg_configUSE_AUTO_CHIP_DETECTION == 1) - - /* use a register description that is generic enough for our needs */ -# include "DA14680AE.h" - -#else - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_E -# include "DA14680AE.h" -# else -# error "Unknown chip stepping for revision A -- check the value of dg_configBLACK_ORCA_IC_STEP" -# endif -#elif dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B -# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_B -# include "DA14680BB.h" -# else -# error "Unknown chip stepping for revision B -- check the value of dg_configBLACK_ORCA_IC_STEP" -# endif -#else -# error "Unknown chip revision -- check the value of dg_configBLACK_ORCA_IC_REV" -#endif - -#endif - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_DA14680.h" /* DA14680AA System */ - -/************************ - * Memory map - ************************/ - -/** - * \brief Remapped device base address. - */ -#define MEMORY_REMAPPED_BASE 0x00000000UL -#define MEMORY_REMAPPED_END 0x04000000UL - -/** - * \brief Remapped device memory size (64MiB). - */ -#define MEMORY_REMAPPED_SIZE (MEMORY_REMAPPED_END - MEMORY_REMAPPED_BASE) - -/** - * \brief ROM base address. - */ -#define MEMORY_ROM_BASE 0x07F00000UL -#define MEMORY_ROM_END 0x07F40000UL - -/** - * \brief ROM memory size (256KiB). - */ -#define MEMORY_ROM_SIZE (MEMORY_ROM_END - MEMORY_ROM_BASE) - -/** - * \brief OTP Controller base address. - */ -#define MEMORY_OTPC_BASE 0x07F40000UL -#define MEMORY_OTPC_END 0x07F80000UL - -/** - * \brief OTP memory base address. - */ -#define MEMORY_OTP_BASE 0x07F80000UL -#define MEMORY_OTP_END 0x07FC0000UL - -/** - * \brief OTP memory size (256KiB). - */ -#define MEMORY_OTP_SIZE (MEMORY_OTP_END - MEMORY_OTP_BASE) - -/** - * \brief SYSTEM RAM base address. - */ -#define MEMORY_SYSRAM_BASE 0x07FC0000UL -#define MEMORY_SYSRAM_END 0x07FE0000UL - -/** - * \brief SYSTEM RAM size (128KiB). - */ -#define MEMORY_SYSRAM_SIZE (MEMORY_SYSRAM_END - MEMORY_SYSRAM_BASE) - -/** - * \brief CACHE RAM base address. - */ -#define MEMORY_CACHERAM_BASE 0x07FE0000UL -#define MEMORY_CACHERAM_END 0x08000000UL - -/** - * \brief CACHE RAM size (128KiB). - */ -#define MEMORY_CACHERAM_SIZE (MEMORY_CACHERAM_END - MEMORY_CACHERAM_BASE) - -/** - * \brief QSPI Flash base address. - */ -#define MEMORY_QSPIF_BASE 0x08000000UL -#define MEMORY_QSPIF_END 0x0BF00000UL - -/** - * \brief QSPI Flash memory size (63MiB). - */ -#define MEMORY_QSPIF_SIZE (MEMORY_QSPIF_END - MEMORY_QSPIF_BASE) - -/** - * \brief QSPI Controller base address. - */ -#define MEMORY_QSPIC_BASE 0x0C000000UL -#define MEMORY_QSPIC_END 0x0C100000UL - -/** - * \brief ECC engine microcode base address. - */ -#define MEMORY_ECC_UCODE_BASE 0x40030000UL - -/** - * \brief TRNG FIFO address - */ -#define MEMORY_TRNG_FIFO 0x40040000UL - -#define WITHIN_RANGE(_a, _s, _e) (((uint32_t)(_a) >= (uint32_t)(_s)) && ((uint32_t)(_a) < (uint32_t)(_e))) - -/** - * \brief Address is in the remapped memory region - */ -#define IS_REMAPPED_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_REMAPPED_BASE, MEMORY_REMAPPED_END) - -/** - * \brief Address is in the ROM region - */ -#define IS_ROM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_ROM_BASE, MEMORY_ROM_END) - -/** - * \brief Address is in the OTP memory region - */ -#define IS_OTP_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OTP_BASE, MEMORY_OTP_END) - -/** - * \brief Address is in the OTP Controller memory region - */ -#define IS_OTPC_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OTPC_BASE, MEMORY_OTPC_END) - -/** - * \brief Address is in the SYSTEM RAM region - */ -#define IS_SYSRAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_SYSRAM_BASE, MEMORY_SYSRAM_END) - -/** - * \brief Address is in the CACHE RAM region - */ -#define IS_CACHERAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_CACHERAM_BASE, MEMORY_CACHERAM_END) - -/** - * \brief Address is in the QSPI Flash memory region - */ -#define IS_QSPIF_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_QSPIF_BASE, MEMORY_QSPIF_END) - -/** - * \brief Address is in the QSPI Controller memory region - */ -#define IS_QSPIC_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_QSPIC_BASE, MEMORY_QSPIC_END) - -#define _BLACK_ORCA_IC_VERSION(revision, stepping) \ - (((revision) << 8) | (stepping)) - -/** - * \brief Convenience macro to create the full chip version from revision and stepping. - * It takes letters as arguments. - */ -#define BLACK_ORCA_IC_VERSION(revision, stepping) \ - _BLACK_ORCA_IC_VERSION(BLACK_ORCA_IC_REV_##revision, \ - BLACK_ORCA_IC_STEP_##stepping) - -/** - * \brief The chip version that we compile for. - */ -#define BLACK_ORCA_TARGET_IC \ - _BLACK_ORCA_IC_VERSION(dg_configBLACK_ORCA_IC_REV, dg_configBLACK_ORCA_IC_STEP) - - -/** - * \brief Zero-initialized data retained memory attribute - */ -#define __RETAINED __attribute__((section("retention_mem_zi"))) // RetRAM0 -#define __RETAINED_1 __attribute__((section("retention_mem_1_zi"))) // RetRAM1 - -/** - * \brief Initialized data retained memory attribute - */ -#define __RETAINED_RW __attribute__((section("retention_mem_init"))) - -/** - * \brief Uninitialized data retained memory attribute - */ -#define __RETAINED_UNINIT __attribute__((section("retention_mem_uninit"))) - - /** - * \brief Constant data retained memory attribute - */ - #define __RETAINED_CONST_INIT __attribute__((section("retention_mem_const"))) - -/** - * \brief Text retained memory attribute - */ -#if ((dg_configCODE_LOCATION == NON_VOLATILE_IS_FLASH) && (dg_configEXEC_MODE == MODE_IS_CACHED)) -#define __RETAINED_CODE __attribute__((section("text_retained"))) __attribute__((noinline)) __attribute__((optimize ("no-tree-switch-conversion"))) -#else -#define __RETAINED_CODE -#endif - -/** - * \brief Attribute to tell the compiler to consider a symbol as used - */ -#define __USED __attribute__((used)) - -/** - * \brief Attribute to tell the compiler to consider a symbol as externally visible (for LTO) - */ -#define __LTO_EXT __attribute__((externally_visible)) - -extern uint32_t black_orca_chip_version; - -#define CHIP_IS_AE (black_orca_chip_version == BLACK_ORCA_IC_VERSION(A, E)) -#define CHIP_IS_BB (black_orca_chip_version == BLACK_ORCA_IC_VERSION(B, B)) - -/** - * \brief Get the chip version of the system, at runtime. - */ -__STATIC_INLINE uint32_t black_orca_get_chip_version(void) -{ - uint32_t rev = CHIP_VERSION->CHIP_REVISION_REG - 'A'; - uint32_t step = CHIP_VERSION->CHIP_TEST1_REG; - - return _BLACK_ORCA_IC_VERSION(rev, step); -} - -// Forward declaration -__RETAINED_CODE void hw_cpm_assert_trigger_gpio(void); - -/** - * \brief Assert as warning macro - * - * \note Active only while in development mode - */ -#define ASSERT_WARNING(a) \ - { \ - if (!(a)) { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - __asm volatile ( " cpsid i " ); \ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ - hw_cpm_assert_trigger_gpio(); \ - do {} while(1); \ - } \ - } \ - } - -/** - * \brief Assert as error macro - * - */ -#define ASSERT_ERROR(a) \ - { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - if (!(a)) { \ - __asm volatile ( " cpsid i " ); \ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ - hw_cpm_assert_trigger_gpio(); \ - do {} while(1); \ - } \ - } \ - else { \ - if (!(a)) { \ - __asm volatile ( " cpsid i " ); \ - __asm volatile ( " bkpt 2 " ); \ - } \ - } \ - } - -/** - * \brief Assert as warning macro when the system is still uninitialized - * - * \note Active only while in development mode. The SW cursor is not activated. - */ -#define ASSERT_WARNING_UNINIT(a) \ - { \ - if (!(a)) { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - __asm volatile ( " cpsid i " ); \ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ - do {} while(1); \ - } \ - } \ - } - -/** - * \brief Assert as error macro when the system is still uninitialized - * - * \note The SW cursor is not activated. - */ -#define ASSERT_ERROR_UNINIT(a) \ - { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - if (!(a)) { \ - __asm volatile ( " cpsid i " ); \ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ - do {} while(1); \ - } \ - } \ - else { \ - if (!(a)) { \ - __asm volatile ( " cpsid i " ); \ - __asm volatile ( " bkpt 2 " ); \ - } \ - } \ - } - -/** - * \brief Macro to disable all interrupts - * - * This macro must always be used with GLOBAL_INT_RESTORE(). E.g. - * - * \code{.c} - * GLOBAL_INT_DISABLE(); - * ... code to be executed with interrupts disabled ... - * GLOBAL_INT_RESTORE(); - * \endcode - * - * \sa GLOBAL_INT_RESTORE - */ -#define GLOBAL_INT_DISABLE() \ - do { \ - unsigned int __l_irq_rest; \ - __asm volatile ("mrs %0, primask \n\t" \ - "mov r1, $1 \n\t" \ - "msr primask, r1 \n\t" \ - : "=r" (__l_irq_rest) \ - : \ - : "r1" \ - ); \ - DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); - -/** - * \brief Macro to restore all interrupts - * - * This macro must always be used after GLOBAL_INT_DISABLE(). E.g. - * - * \code{.c} - * GLOBAL_INT_DISABLE(); - * ... code to be executed with interrupts disabled ... - * GLOBAL_INT_RESTORE(); - * \endcode - * - * \sa GLOBAL_INT_DISABLE - */ -#define GLOBAL_INT_RESTORE() \ - if (__l_irq_rest == 0) { \ - DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \ - } \ - __asm volatile ("msr primask, %0 \n\t" \ - : \ - : "r" (__l_irq_rest) \ - : \ - ); \ - } while(0) - -#define containingoffset(address, type, field) ((type*)((uint8*)(address)-(size_t)(&((type*)0)->field))) - -/** - * \brief Macro the minimum of two values - * - * \param[in] a First value - * \param[in] b Second value - */ -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -/** - * \brief Macro the maximum of two values - * - * \param[in] a First value - * \param[in] b Second value - */ -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) - -/** - * \brief Macro to swap the bytes of a 16-bit variable - * - * \param[in] a The 16-bit variable - */ -#if defined(__GNUC__) -#define SWAP16(a) __builtin_bswap16(a) -#else -#define SWAP16(a) ((a<<8) | (a>>8)) -#endif - -/** - * \brief Macro to swap the bytes of a 32-bit variable - * - * \param[in] a The 32-bit variable - */ -#if defined(__GNUC__) -#define SWAP32(a) __builtin_bswap32(a) -#else -#define SWAP32(a) ((a>>24 & 0xff) | (a>>8 & 0xff00) | (a<<8 & 0xff0000) | (a<<24 & 0xff000000)) -#endif - -#if defined(__GNUC__) -#define DEPRECATED __attribute__ ((deprecated)) -#else -#warning Deprecated macro must be implemented for this compiler -#define DEPRECATED -#endif - -#if defined(__GNUC__) -#define DEPRECATED_MSG(msg) __attribute__ ((deprecated(msg))) -#else -#warning Deprecated macro must be implemented for this compiler -#define DEPRECATED_MSG(msg) -#endif - -/* The following exist in ROM code */ -void __aeabi_memcpy(void *dest, const void *src, size_t n); -void __aeabi_memmove(void *dest, const void *src, size_t n); -void __aeabi_memset(void *dest, size_t n, int c); - -/** - * \brief Optimized memcpy - */ -#define OPT_MEMCPY __aeabi_memcpy - -/** - * \brief Optimized memmove - */ -#define OPT_MEMMOVE __aeabi_memmove - -/** - * \brief Optimized memset - */ -#define OPT_MEMSET(s, c, n) __aeabi_memset(s, n, c) - -/** - * \brief Access register field mask. - * - * Returns a register field mask (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * - * tmp = CRG_TOP->SYS_STAT_REG; - * - * if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY)) { - * ... - * \endcode - */ -#define REG_MSK(base, reg, field) \ - (base ## _ ## reg ## _ ## field ## _Msk) - -/** - * \brief Access register field position. - * - * Returns a register field position (aimed to be used with local variables). - */ -#define REG_POS(base, reg, field) \ - (base ## _ ## reg ## _ ## field ## _Pos) - -/** - * \brief Access register field value. - * - * Returns a register field value (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * int counter; - * tmp = CRG_TOP->TRIM_CTRL_REG; - * counter = REG_GET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); - * ... - * \endcode - */ -#define REG_GET_FIELD(base, reg, field, var) \ - ((var & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ - (base ## _ ## reg ## _ ## field ## _Pos)) - -/** - * \brief Set register field value. - * - * Sets a register field value (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * - * tmp = CRG_TOP->TRIM_CTRL_REG; - * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp, 10); - * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp, 2); - * CRG_TOP->TRIM_CTRL_REG = tmp; - * ... - * \endcode - */ -#define REG_SET_FIELD(base, reg, field, var, val) \ - var = ((var & ~((base ## _ ## reg ## _ ## field ## _Msk))) | \ - (((val) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ - (base ## _ ## reg ## _ ## field ## _Msk))) - -/** - * \brief Clear register field value. - * - * Clears a register field value (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * - * tmp = CRG_TOP->TRIM_CTRL_REG; - * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); - * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp); - * CRG_TOP->TRIM_CTRL_REG = tmp; - * ... - * \endcode - */ -#define REG_CLR_FIELD(base, reg, field, var) \ - var &= ~(base ## _ ## reg ## _ ## field ## _Msk) - -/** - * \brief Get the address of a register value by index (provided a register interval) - * - * \note The register interval should be an exact multiple of the register's base size. For example, - * if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result - * will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by - * the interval value (in bytes) to find the actual offset of the register. - * - * Returns a register address value by index - */ -#define REG_GET_ADDR_INDEXED(base, reg, interval, index) \ - ((&base->reg) + (((intptr_t) index) * ((interval) / sizeof(base->reg)))) - -/** - * \brief Return the value of a register field by index (provided a register interval). - * - * e.g. - * \code - * uint16_t val; - * uint16_t index = 2 - * - * val = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, REG_EXP_SA_L, 0x10, index) - * - * ... - * \endcode - * - * \note The register interval should be an exact multiple of the register's base size. For example, - * if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result - * will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by - * the interval value (in bytes) to find the actual offset of the register. - * - */ -#define REG_GETF_INDEXED(base, reg, field, interval, index) \ - (((*REG_GET_ADDR_INDEXED(base, reg, interval, index)) & \ - (base ## _ ## reg ## _ ## field ## _Msk)) >> (base ## _ ## reg ## _ ## field ## _Pos)) - -/** - * \brief Return the value of a register field. - * - * e.g. - * \code - * uint16_t val; - * - * val = REG_GETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N); - * ... - * \endcode - */ -#define REG_GETF(base, reg, field) \ - (((base->reg) & (base##_##reg##_##field##_Msk)) >> (base##_##reg##_##field##_Pos)) - -/** - * \brief Set the value of a register field. - * - * e.g. - * \code - * - * REG_SETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, new_value); - * ... - * \endcode - */ -#define REG_SETF(base, reg, field, new_val) \ - base->reg = ((base->reg & ~(base##_##reg##_##field##_Msk)) | \ - ((base##_##reg##_##field##_Msk) & ((new_val) << (base##_##reg##_##field##_Pos)))) - -/** - * \brief Set a bit of a register. - * - * e.g. - * \code - * - * REG_SET_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); - * ... - * \endcode - */ -#define REG_SET_BIT(base, reg, field) \ - do { \ - base->reg |= (1 << (base##_##reg##_##field##_Pos)); \ - } while (0) - -/** - * \brief Clear a bit of a register. - * - * e.g. - * \code - * - * REG_CLR_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); - * ... - * \endcode - */ -#define REG_CLR_BIT(base, reg, field) \ - do { \ - base->reg &= ~(base##_##reg##_##field##_Msk); \ - } while (0) - -/** - * \brief Sets register bits, indicated by the mask, to a value. - * - * e.g. - * \code - * REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); - * \endcode - */ -#define REG_SET_MASKED(base, reg, mask, value) \ - do { \ - base->reg = (base->reg & ~(mask)) | ((value) & (mask)); \ - } while (0) - -/** - * \brief Sets 16-bit wide register bits, indicated by the field, to a value v. - */ -#define BITS16(base, reg, field, v) \ - ((uint16) (((uint16) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ - (base ## _ ## reg ## _ ## field ## _Msk))) - -/** - * \brief Sets 32-bit wide register bits, indicated by the field, to a value v. - */ -#define BITS32(base, reg, field, v) \ - ((uint32) (((uint32) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ - (base ## _ ## reg ## _ ## field ## _Msk))) - -/** - * \brief Reads 16-bit wide register bits, indicated by the field, to a variable v. - */ -#define GETBITS16(base, reg, v, field) \ - ((uint16) (((uint16) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ - (base ## _ ## reg ## _ ## field ## _Pos)) - -/** - * \brief Reads 32-bit wide register bits, indicated by the field, to a variable v. - */ -#define GETBITS32(base, reg, v, field) \ - ((uint32) (((uint32) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ - (base ## _ ## reg ## _ ## field ## _Pos)) - -/** - * \brief Macro to enable the debugger - * - */ -#define ENABLE_DEBUGGER \ - do { \ - REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ - } while(0) - -/** - * \brief Macro to disable the debugger - * - */ -#define DISABLE_DEBUGGER \ - do { \ - REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ - } while(0) - - -/** - * \brief Macro to cause a software reset - * - */ -#define SWRESET \ - do { \ - REG_SET_BIT(GPREG, DEBUG_REG, SW_RESET); \ - } while (0) - -#define BIT0 0x01 -#define BIT1 0x02 -#define BIT2 0x04 -#define BIT3 0x08 -#define BIT4 0x10 -#define BIT5 0x20 -#define BIT6 0x40 -#define BIT7 0x80 - -#define BIT8 0x0100 -#define BIT9 0x0200 -#define BIT10 0x0400 -#define BIT11 0x0800 -#define BIT12 0x1000 -#define BIT13 0x2000 -#define BIT14 0x4000 -#define BIT15 0x8000 - -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 - -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -typedef unsigned char uint8; // 8 bits -typedef char int8; // 8 bits -typedef unsigned short uint16; // 16 bits -typedef short int16; // 16 bits -typedef unsigned long uint32; // 32 bits -typedef long int32; // 32 bits -typedef unsigned long long uint64; // 64 bits -typedef long long int64; // 64 bits - -/* See also "Data Types" on pag. 21 of the (Doulos) Cortex-M0 / SoC 1.0 training documentation. */ -typedef unsigned char BYTE; // 8 bits = Byte -typedef unsigned short HWORD; // 16 bits = Halfword -typedef unsigned long WORD; // 32 bits = Word -typedef long long DWORD; // 64 bits = Doubleword - - -#ifdef __cplusplus -} -#endif - -#endif /* __SDK_DEFS_H__ */ - -/** - * \} - * \} - * \} - */ - diff --git a/third_party/dialog/DialogSDK/bsp/include/suota.h b/third_party/dialog/DialogSDK/bsp/include/suota.h deleted file mode 100644 index 7862f4229..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/suota.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup SUOTA - * - * \brief SUOTA structure definitions - * - * \{ - */ - -/** - ***************************************************************************************** - * - * @file suota.h - * - * @brief SUOTA structure definitions - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef SUOTA_H_ -#define SUOTA_H_ - -#include - -#define SUOTA_VERSION_1_1 11 -#define SUOTA_VERSION_1_2 12 -#define SUOTA_VERSION_1_3 13 - -#ifndef SUOTA_VERSION -#define SUOTA_VERSION SUOTA_VERSION_1_3 -#endif - -#if SUOTA_PSM && (SUOTA_VERSION < SUOTA_VERSION_1_2) -# error "SUOTA_PSM is only applicable to SUOTA_VERSION >= 1.2" -#endif - -/** - * \struct suota_1_1_product_header_t; - * - * \brief SUOTA 1.1 product header as defined by Dialog SUOTA specification. - * - * \note the same header is used for any SUOTA version newer than 1.1 - * - */ -typedef struct { - uint8_t signature[2]; - uint16_t flags; - uint32_t current_image_location; - uint32_t update_image_location; - uint8_t reserved[8]; -} __attribute__((packed)) suota_1_1_product_header_t; - -#define SUOTA_1_1_PRODUCT_HEADER_SIGNATURE_B1 0x70 -#define SUOTA_1_1_PRODUCT_HEADER_SIGNATURE_B2 0x62 - -/** - * \struct suota_1_1_image_header_t - * - * \brief SUOTA 1.1 image header as defined by Dialog SUOTA specification. - * - * \note the same header is used for any SUOTA version newer than 1.1 - * - */ -typedef struct { - uint8_t signature[2]; - uint16_t flags; - uint32_t code_size; - uint32_t crc; - uint8_t version[16]; - uint32_t timestamp; - uint32_t exec_location; -} __attribute__((packed)) suota_1_1_image_header_t; - -#define SUOTA_1_1_IMAGE_HEADER_SIGNATURE_B1 0x70 -#define SUOTA_1_1_IMAGE_HEADER_SIGNATURE_B2 0x61 - -#define SUOTA_1_1_IMAGE_FLAG_FORCE_CRC 0x01 -#define SUOTA_1_1_IMAGE_FLAG_VALID 0x02 -#define SUOTA_1_1_IMAGE_FLAG_RETRY1 0x04 -#define SUOTA_1_1_IMAGE_FLAG_RETRY2 0x08 - -typedef suota_1_1_image_header_t suota_image_header_t; - -#endif /* SUOTA_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/include/system_ARMCM0.h b/third_party/dialog/DialogSDK/bsp/include/system_ARMCM0.h deleted file mode 100755 index 9b8d11ba1..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/system_ARMCM0.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM0.h - * @brief CMSIS Device System Header File for - * ARMCM0 Device Series - * @version V2.00 - * @date 18. August 2015 - ******************************************************************************/ -/* Copyright (c) 2011 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef SYSTEM_ARMCM0_H -#define SYSTEM_ARMCM0_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** @brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock - retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM0_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/system_DA14680.h b/third_party/dialog/DialogSDK/bsp/include/system_DA14680.h deleted file mode 100755 index 1d2e4dbf4..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/system_DA14680.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************//** - * @file system_DA14680.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for - * Device DA14680 - * @version V3.10 - * @date 23. November 2012 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef SYSTEM_DA14680_H -#define SYSTEM_DA14680_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - - -/** - * \brief Convert a CPU address to a physical address - * - * To calculate the physical address, the current remapping (SYS_CTRL_REG.REMAP_ADR0) - * is used. - * - * \param [in] addr address seen by CPU - * - * \return physical address (for DMA, AES/HASH etc.) -- can be same or different as addr - * - */ -extern uint32_t DA15000_phy_addr(uint32_t addr); - - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_DA14680_H */ diff --git a/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld b/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld deleted file mode 100755 index a8105d7c1..000000000 --- a/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld +++ /dev/null @@ -1,237 +0,0 @@ -/** - **************************************************************************************** - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -MEMORY -{ - ROM (rx) : ORIGIN = (0x8000000 + (0)), LENGTH = (512 * 1024) - RetRAM0 (rwx): ORIGIN = (0x7FC0000) + (( 64 * 1024) + ( 0 * 1024)), LENGTH = (( 24 * 1024)) - RetRAM1 (rwx): ORIGIN = (0), LENGTH = 0 - RAM (rw) : ORIGIN = (0x7FC0000) + ((0x200)), LENGTH = (( 64 * 1024) - (0x200)) -} - -ENTRY(Reset_Handler) -SECTIONS -{ - .init_text : - { - KEEP(*(.isr_vector)) - . = 0xC0; - KEEP(*(.patch_table)) - . = 0x100; - KEEP(*(.patch_table_flash)) - . = 0x130; - KEEP(*(.default_patch_code_handler_section)) - . = 0x200; - *(text_reset*) - } > ROM - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext + (__data_end__ - __data_start__)) - LONG (__RetRAM0_code_start__) - LONG (__RetRAM0_code_end__ - __RetRAM0_code_start__) - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - __copy_table_end__ = .; - . = ALIGN(16); - } > ROM - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__RetRAM0_data_start) - LONG (__RetRAM0_size) - LONG (__RetRAM1_start__) - LONG (__RetRAM1_end__ - __RetRAM1_start__) - __zero_table_end__ = .; - . = ALIGN(16); - } > ROM - PROVIDE_HIDDEN (__stext = .); - .text : - { - *(EXCLUDE_FILE(*libnosys.a:sbrk.o - *libgcc.a:_aeabi_uldivmod.o - *libgcc.a:_muldi3.o - *libgcc.a:_dvmd_tls.o - *libgcc.a:bpabi.o - *libgcc.a:_udivdi3.o - *libgcc.a:_clzdi2.o - *libgcc.a:_clzsi2.o) .text*) - . = ALIGN(4); - __start_adapter_init_section = .; - *(adapter_init_section) - __stop_adapter_init_section = .; - __start_bus_init_section = .; - *(bus_init_section) - __stop_bus_init_section = .; - __start_device_init_section = .; - *(device_init_section) - __stop_device_init_section = .; - KEEP(*(.init)) - KEEP(*(.fini)) - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - *(.rodata*) - KEEP(*(.eh_frame*)) - } > ROM - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - .align_s : - { - . = ALIGN(16); - } > ROM - __etext = .; - .data : AT (__etext) - { - . = ALIGN(16); - __data_start__ = .; - *(vtable) - *(EXCLUDE_FILE(*\libg_nano.a:* *\libnosys.a:*) .data*) - . = ALIGN(4); - KEEP(*(.jcr*)) - . = ALIGN(16); - __data_end__ = .; - } > RAM - .bss : - { - . = ALIGN(32); - __bss_start__ = .; - *(.bss.ecc_buffer) - *(EXCLUDE_FILE(*\libg_nano.a:* *\libnosys.a:*) .bss*) - *(COMMON) - . = ALIGN(32); - __bss_end__ = .; - } > RAM - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - __HeapLimit = .; - } > RAM - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - RETENTION_INIT0 : AT (__etext + (__data_end__ - __data_start__)) - { - . = ALIGN(16); - __RetRAM0_code_start__ = .; - *(text_retained) - *libgcc.a:_aeabi_uldivmod.o (.text*) - *libgcc.a:_muldi3.o (.text*) - *libgcc.a:_dvmd_tls.o (.text*) - *libgcc.a:bpabi.o (.text*) - *libgcc.a:_udivdi3.o (.text*) - *libgcc.a:_clzdi2.o (.text*) - *libgcc.a:_clzsi2.o (.text*) - . = ALIGN(4); - *(retention_mem_init) - *(retention_mem_const) - *(privileged_data_init) - *(.retention) - *\libg_nano.a:* (.data*) - *\libnosys.a:* (.data*) - . = ALIGN(16); - __RetRAM0_code_end__ = .; - . = ALIGN(4); - } > RetRAM0 - RETENTION_RAM0 (COPY) : - { - . = ALIGN(4); - __RetRAM0_start = .; - *(nmi_info) - *(hard_fault_info) - *(retention_mem_uninit) - . = ALIGN(32); - __RetRAM0_data_start = .; - *\libg_nano.a:* (.bss*) - *\libnosys.a:* (.bss*) - *(privileged_data_zi) - *(retention_mem_zi) - *(os_heap) - . = ALIGN(32); - __RetRAM0_data_end__ = .; - } > RetRAM0 - RETENTION_RAM1 (COPY) : - { - . = ALIGN(32); - __RetRAM1_start__ = .; - *(privileged_data_1_zi) - *(retention_mem_1_zi) - . = ALIGN(32); - __RetRAM1_end__ = .; - } > RetRAM1 - __RetRAM0_size = (__RetRAM0_data_end__ - __RetRAM0_data_start); - __image_size = __etext + (__data_end__ - __data_start__) - + (__RetRAM0_code_end__ - __RetRAM0_code_start__) - - ORIGIN(ROM); - __mirrored_image_size = __etext + (__data_end__ - __data_start__) - ORIGIN(ROM); -} - diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h deleted file mode 100644 index c6d21aaf1..000000000 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h +++ /dev/null @@ -1,305 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup MEMORY - * - * \{ - */ - -/** - **************************************************************************************** - * - * @file qspi_automode.h - * - * @brief Access QSPI flash when running in auto mode - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef QSPI_AUTOMODE_H_ -#define QSPI_AUTOMODE_H_ - -#include -#include -#include -#include -#include -#include "hw_cpm.h" -/* - * Debug options - */ -#if __DBG_QSPI_ENABLED -#define __DBG_QSPI_VOLATILE__ volatile -#pragma message "Automode: Debugging is on!" -#else -#define __DBG_QSPI_VOLATILE__ -#endif - -/* - * Defines (generic) - */ - -/* Macros to put functions that need to be copied to ram in one section (retained) */ -typedef struct qspi_ucode_s { - const uint32_t *code; - uint8_t size; -} qspi_ucode_t; - -/* - * Flash specific defines - */ - -/** - * \brief SUS bit delay after SUSPEND command (in μsec) - * - */ -#define FLASH_SUS_DELAY (20) - - -/** - * \brief Get size of RAM buffer needed for code to modify QSPI flash. - * - * Called must allocate buffer at least of this size and pass it qspi_set_code_buffer() to allow - * flash modification. - * - * \return size of buffer needed - * - */ -DEPRECATED -uint32_t qspi_automode_get_code_buffer_size(void); - -/** - * \brief Set buffer that will be used for code that modifies flash. - * - * This function should be called with buffer allocated for flash manipulation code. - * Size of this buffer should be at least the value returned from qspi_get_code_buffer_size(). - * If function is called with NULL all further calls to qspi_write_flash_page() or - * qspi_erase_flash_sector() will crash. - * To preserve memory it is quite wise to allocate buffer before erase/write, update flash and - * then call this function with NULL and free memory. - * - * \param [in] ram buffer for code that will be used for erase and write. - * - */ -DEPRECATED_MSG("Function does not need to be called") -void qspi_automode_set_code_buffer(void *ram); - -/** - * \brief Write flash memory - * - * This function allows to write up to page size of data to flash. - * If size is greater than page size, flash can wrap data and overwrite content of page. - * It's possible to write less then page size. - * Memory should be erased before. - * - * \note: Do not pass buf pointing to QSPI mapped memory. - * - * \param [in] addr offset in flash to write data to - * \param [in] buf pointer to data to write - * \param [in] size number of bytes to write - * - * return number of bytes written - * - */ -size_t qspi_automode_write_flash_page(uint32_t addr, const uint8_t *buf, size_t size); - -/** - * \brief Erase flash sector - * - * \param [in] addr starting offset of sector - */ -void qspi_automode_erase_flash_sector(uint32_t addr); - -/** - * \brief Erase whole chip - */ -void qspi_automode_erase_chip(void); - -/** - * \brief Read flash memory - * - * \param [in] addr starting offset - * \param [out] buf buffer to read data to - * \param [in] len number of bytes to read - * - * \returns number of bytes read - */ -size_t qspi_automode_read(uint32_t addr, uint8_t *buf, size_t len); - -/** - * \brief Get address of flash - * - * \param [in] addr starting offset - * - * \returns address in CPU address space where data is located - */ -static inline const void *qspi_automode_addr(uint32_t addr) __attribute__((always_inline)); - -static inline const void *qspi_automode_addr(uint32_t addr) -{ - return (const void *) (MEMORY_QSPIF_BASE + addr); -} - -/** - * \brief Power up flash - */ -__RETAINED_CODE void qspi_automode_flash_power_up(void); - -/** - * \brief Set QSPI Flash into power down mode - */ -__RETAINED_CODE void qspi_automode_flash_power_down(void); - -/** - * \brief Init QSPI controller - */ -__RETAINED_CODE bool qspi_automode_init(void); - -#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) -/** - * \brief Check if a program or sector erase operation is in progress - * - * \return bool True if the BUSY bit is set else false. - * - * \warning This function checks the value of the BUSY bit in the Status Register 1 of the Flash. It - * is the responsibility of the caller to call the function in the right context. The - * function must be called with interrupts disabled. - * - */ -__RETAINED_CODE bool qspi_check_program_erase_in_progress(void); - -/** - * \brief Suspend a Flash program or erase operation - * - * \details This function will try to suspend an ongoing program or erase procedure. The SUS bit is - * checked and the actual status is returned to the caller. Note that the program or erase - * procedure may have been completed before the suspend command is processed by the Flash. In - * this case the SUS bit will be left to 0. - * - * \return bool True if the procedure has been suspended. False if the procedure was not suspended - * successfully or had finished before the suspend command was processed by the Flash. - * - * \warning After the call to this function, the QSPI controller is set to auto mode and the Flash - * access to quad mode (if QUAD_MODE is 1). The function must be called with interrupts - * disabled. - * - */ -__RETAINED_CODE bool qspi_check_and_suspend(void); - -/** - * \brief Resume a Flash program or sector erase operation - * - * \warning After the call to this function, the QSPI controller is set to manual mode and the Flash - * access to single mode. The function must be called with interrupts disabled. - * - */ -__RETAINED_CODE void qspi_resume(void); - -/** - * \brief Erase a sector of the Flash in manual mode - * - * \param[in] addr The address of the sector to be erased. - * - * \warning This function does not block until the Flash has processed the command! The QSPI - * controller is left to manual mode after the call to this function. The function must be - * called with interrupts disabled. - * - */ -__RETAINED_CODE void flash_erase_sector_manual_mode(uint32_t addr); - -/** - * \brief Program data into a page of the Flash in manual mode - * - * \param[in] addr The address of the Flash where the data will be written. It may be anywhere in a - * page. - * \param[in] buf Pointer to the beginning of the buffer that contains the data to be written. - * \param[in] len The number of bytes to be written. - * - * \return size_t The number of bytes written. - * - * \warning The boundary of the page where addr belongs to, will not be crossed! The caller should - * issue another flash_program_page_manual_mode() call in order to write the remaining data - * to the next page. The QSPI controller is left to manual mode after the call to this - * function. The function must be called with interrupts disabled. - * - */ -__RETAINED_CODE size_t flash_program_page_manual_mode(uint32_t addr, const uint8_t *buf, - uint16_t len); -#endif - -/** - * \brief Activate Flash command entry mode - * - * \note After the call to this function, the QSPI controller is set to manual mode and the Flash - * access to single mode. - * - * \warning The function must be called with interrupts disabled. - * - */ -__RETAINED_CODE void flash_activate_command_entry_mode(void); - -/** - * \brief Deactivate Flash command entry mode - * - * \note After the call to this function, the QSPI controller is set to auto mode and the Flash - * access to quad mode (if QUAD_MODE is 1). - * - * \warning The function must be called with interrupts disabled. - * - */ -__RETAINED_CODE void flash_deactivate_command_entry_mode(void); - -/** - * \brief Configure Flash and QSPI controller for system clock frequency - * - * This function is used to change the Flash configuration of the QSPI controller - * to work with the system clock frequency defined in sys_clk. Dummy clock - * cycles could be changed here to support higher clock frequencies. - * QSPI controller clock divider could also be changed if the Flash - * maximum frequency is smaller than the system clock frequency. - * This function must be called before changing system clock frequency. - * - * \param [in] sys_clk System clock frequency - * - */ -__RETAINED_CODE void qspi_automode_sys_clock_cfg(sys_clk_t sys_clk); - -/** - * \brief Get ucode required for wake-up sequence - * \return qspi_ucode_t Pointer to the structure containing the ucode and ucode size - */ -const qspi_ucode_t *qspi_automode_get_ucode(void); - -#endif /* QSPI_AUTOMODE_H_ */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h deleted file mode 100644 index e964e5027..000000000 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h +++ /dev/null @@ -1,174 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup MEMORY - * - * \brief QSPI flash driver framework - * \{ - */ - -/** - **************************************************************************************** - * - * @file qspi_common.h - * - * @brief QSPI flash driver common definitions - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef _QSPI_COMMON_H_ -#define _QSPI_COMMON_H_ - -#include "qspi_automode.h" - -/* - * Flash Commands - * - * Note: Default command issuing mode is single mode! If commands specific to other modes have to be - * issued then the mode must be changed! - */ -#define CMD_WRITE_STATUS_REGISTER 0x01 -#define CMD_WRITE_DISABLE 0x04 -#define CMD_READ_STATUS_REGISTER 0x05 -#define CMD_WRITE_ENABLE 0x06 -#define CMD_SECTOR_ERASE 0x20 -#define CMD_QUAD_PAGE_PROGRAM 0x32 -#define CMD_QUAD_IO_PAGE_PROGRAM 0x38 -#define CMD_BLOCK_ERASE 0x52 -#define CMD_CHIP_ERASE 0xC7 -#define CMD_FAST_READ_QUAD 0xEB -#define CMD_READ_JEDEC_ID 0x9F -#define CMD_EXIT_CONTINUOUS_MODE 0xFF -#define CMD_RELEASE_POWER_DOWN 0xAB -#define CMD_ENTER_POWER_DOWN 0xB9 - -#define CMD_FAST_READ_QUAD_4B 0xEC -#define CMD_SECTOR_ERASE_4B 0x21 -#define CMD_QUAD_PAGE_PROGRAM_4B 0x34 -#define CMD_QUAD_IO_PAGE_PROGRAM_4B 0x3E - -/* Erase/Write in progress */ -#define FLASH_STATUS_BUSY_BIT 0 -#define FLASH_STATUS_BUSY_MASK (1 << FLASH_STATUS_BUSY_BIT) - -/* WE Latch bit */ -#define FLASH_STATUS_WEL_BIT 1 -#define FLASH_STATUS_WEL_MASK (1 << FLASH_STATUS_WEL_BIT) - -typedef bool (*is_suspended_cb_t)(void); -typedef void (*initialize_cb_t)(uint8_t device_type, uint8_t device_density); -typedef void (*deactivate_command_entry_mode_cb_t)(void); -typedef void (*sys_clk_cfg_cb_t)(sys_clk_t type); -typedef uint8_t (*get_dummy_bytes_cb_t)(void); - -/** - * \brief QSPI Flash configuration structure - * - * This struct is used to define a driver for a specific QSPI flash. - * - * \note The struct instance must be declared as static const for this to work - */ -typedef struct qspi_flash_config { - // Function pointers - initialize_cb_t initialize; /**< Flash-specific initialization */ - is_suspended_cb_t is_suspended; /**< Check if flash is in erase/program - suspend state */ - deactivate_command_entry_mode_cb_t - deactivate_command_entry_mode; /**< Perform extra steps needed when command - entry mode is deactivated */ - sys_clk_cfg_cb_t sys_clk_cfg; /**< Perform Flash configuration when system clock - is changed (e.g. change dummy bytes or QSPIC - clock divider */ - get_dummy_bytes_cb_t get_dummy_bytes; /**< Return the number of dummy bytes currently - needed (they may e.g. change when the clock - changes) */ - uint8_t manufacturer_id; /**< The Flash JEDEC vendor ID (Cmd 0x9F, 1st byte) - This (and the device_type/device_density) - are needed for flash autodetection */ - uint8_t device_type; /**< The Flash JEDEC device type (Cmd 0x9F, 2nd byte) */ - uint8_t device_density; /**< The Flash JEDEC device type (Cmd 0x9F, 3rd byte) */ - uint8_t erase_opcode; /**< The Flash erase opcode to use */ - uint8_t erase_suspend_opcode; /**< The Flash erase suspend opcode to use */ - uint8_t erase_resume_opcode; /**< The Flash erase resume opcode to use */ - uint8_t page_program_opcode; /**< The Flash page program opcode to use */ - bool quad_page_program_address; /**< If true, the address will be transmitted in - QUAD mode when writing a page. Otherwise, it - will be transmitted in single mode */ - uint8_t read_erase_progress_opcode; /**< The opcode to use to check if erase is in progress - (Usually the Read Status Reg opcode (0x5)) */ - - uint8_t erase_in_progress_bit; /**< The bit to check when reading the erase progress */ - bool erase_in_progress_bit_high_level; /**< The active state (true: high, false: low) of the bit - above */ - uint8_t send_once; /**< If set to 1, the "Performance mode" (or burst, or - continuous; differs per vendor) will be used for read - accesses. In this mode, the read opcode is only sent - once, and subsequent accesses only transfer the address */ - uint8_t extra_byte; /**< The extra byte to transmit, when in "Performance mode" - (send once is 1), that tells the flash that it should - stay in this continuous, performance mode */ - HW_QSPI_ADDR_SIZE address_size; /**< Whether the flash works in 24- or 32-bit addressing mode */ - HW_QSPI_BREAK_SEQ_SIZE break_seq_size; /**< Whether the break sequence, that puts flash out of the - continuous mode, is one or two bytes long (the break byte is - 0xFF) */ - qspi_ucode_t ucode_wakeup; /**< The QSPIC microcode to use to setup the flash on wakeup. This - is automatically used by the QSPI Controller after wakeup, and - before CPU starts code execution. This is different based on - whether flash was active, in deep power down or completely off - while the system was sleeping */ - uint16_t power_down_delay; /**< This is the time, in usec, needed for the flash to go to power - down, after the Power Down command is issued */ - uint16_t release_power_down_delay; /**< This is the time, in usec, needed for the flash to exit the power - down mode, after the Release Power Down command is issued */ -} qspi_flash_config_t; - -extern const qspi_flash_config_t* flash_config_init; -#if (FLASH_AUTODETECT == 1) -extern qspi_flash_config_t *flash_config; -#else -extern const qspi_flash_config_t * const flash_config; -#endif - -static void qspi_write(const uint8_t *wbuf, size_t wlen); -static void qspi_transact(const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, size_t rlen); -static uint8_t flash_read_status_register(void); -static void flash_write_status_register(uint8_t value); -static void flash_write_enable(void); -static void qspi_automode_set_dummy_bytes_count(uint8_t count); -static inline bool flash_erase_program_in_progress(void) __attribute__((always_inline)); -static inline bool flash_is_busy(void) __attribute__((always_inline)); - -#endif /* _QSPI_COMMON_H_ */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h deleted file mode 100644 index 774da1618..000000000 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup MEMORY - * - * \{ - */ - -/** - **************************************************************************************** - * - * @file qspi_w25q80ew.h - * - * @brief QSPI flash driver for the Winbond W25Q80EW - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************** - */ - -#ifndef _QSPI_W32Q80EW_H_ -#define _QSPI_W32Q80EW_H_ - -#ifndef WINBOND_ID -#define WINBOND_ID 0xEF -#endif - -// Device type using command 0x9F -#define W25Q80EW 0x60 - -#ifndef W25Q_8Mb_SIZE -#define W25Q_8Mb_SIZE 0x14 -#endif - -#if (FLASH_AUTODETECT == 1) || (dg_configFLASH_MANUFACTURER_ID == WINBOND_ID && \ - dg_configFLASH_DEVICE_TYPE == W25Q80EW && dg_configFLASH_DENSITY == W25Q_8Mb_SIZE) - -#include "qspi_common.h" - -#include "qspi_winbond.h" - -static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk); -static uint8_t flash_w25q80ew_get_dummy_bytes(void); - -static const qspi_flash_config_t flash_w25q80ew_config = { - .manufacturer_id = WINBOND_ID, - .device_type = W25Q80EW, - .device_density = W25Q_8Mb_SIZE, - .is_suspended = flash_w25q_is_suspended, - .initialize = flash_w25q_initialize, - .deactivate_command_entry_mode = flash_w25q_deactivate_command_entry_mode, - .sys_clk_cfg = flash_w25q80ew_sys_clock_cfg, - .get_dummy_bytes = flash_w25q80ew_get_dummy_bytes, - .break_seq_size = HW_QSPI_BREAK_SEQ_SIZE_1B, - .address_size = HW_QSPI_ADDR_SIZE_24, - .page_program_opcode = CMD_QUAD_PAGE_PROGRAM, - .quad_page_program_address = false, - .erase_opcode = CMD_SECTOR_ERASE, - .erase_suspend_opcode = W25Q_ERASE_PROGRAM_SUSPEND, - .erase_resume_opcode = W25Q_ERASE_PROGRAM_RESUME, - .read_erase_progress_opcode = CMD_READ_STATUS_REGISTER, - .erase_in_progress_bit = FLASH_STATUS_BUSY_BIT, - .erase_in_progress_bit_high_level = true, - .send_once = 1, - .extra_byte = 0xA0, - .ucode_wakeup = {w25q_ucode_wakeup, sizeof(w25q_ucode_wakeup)}, - .power_down_delay = W25Q_POWER_DOWN_DELAY_US, - .release_power_down_delay = W25Q_RELEASE_POWER_DOWN_DELAY_US, -}; - -#if (FLASH_AUTODETECT == 0) - const qspi_flash_config_t* const flash_config = &flash_w25q80ew_config; -#endif - -__RETAINED_CODE static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk) -{ - -} - -__RETAINED_CODE static uint8_t flash_w25q80ew_get_dummy_bytes(void) -{ - return 2; -} -#endif - -#endif /* _QSPI_W32Q80EW_H_ */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h deleted file mode 100644 index 0c183ac75..000000000 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h +++ /dev/null @@ -1,241 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup MEMORY - * - * \{ - */ - -/** - **************************************************************************************** - * - * @file qspi_winbond.h - * - * @brief QSPI flash driver for Winbond flashes - common code - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef _QSPI_WINBOND_H_ -#define _QSPI_WINBOND_H_ - -#define WINBOND_ID 0xEF - -#if (FLASH_AUTODETECT == 1) || (dg_configFLASH_MANUFACTURER_ID == WINBOND_ID) -#include "qspi_common.h" - -#define W25Q_ERASE_PROGRAM_SUSPEND 0x75 -#define W25Q_ERASE_PROGRAM_RESUME 0x7A - -#define W25Q_WRITE_STATUS_REGISTER2 0x31 -#define W25Q_PAGE_PROGRAM 0x02 -#define W25Q_WRITE_ENABLE_NON_VOL 0x50 -#define W25Q_READ_STATUS_REGISTER2 0x35 -#define W25Q_BLOCK_ERASE_64K 0xD8 -#define W25Q_FAST_READ_QPI 0x0B -#define W25Q_READ_DEVICE_ID_SINGLE 0x90 // Requires single mode for the command entry! -#define W25Q_READ_DEVICE_ID_DUAL 0x92 // Requires dual mode for the command entry! -#define W25Q_READ_DEVICE_ID_QUAD 0x94 -#define W25Q_READ_UNIQUE_ID 0x4B // Requires single mode for the command entry! -#define W25Q_READ_SFDP_REG 0x5A // Requires single mode for the command entry! -#define W25Q_ERASE_SECURITY_REGS 0x44 // Requires single mode for the command entry! -#define W25Q_PROGR_SECURITY_REGS 0x42 // Requires single mode for the command entry! -#define W25Q_READ_SECURITY_REGS 0x48 // Requires single mode for the command entry! -#define W25Q_ENTER_QPI_MODE 0x38 // Requires single mode for the command entry! -#define W25Q_EXIT_QPI_MODE 0xFF // Requires quad mode for the command entry! - -/* Suspend */ -#define W25Q_STATUS2_SUS_BIT 7 -#define W25Q_STATUS2_SUS_MASK (1 << W25Q_STATUS2_SUS_BIT) - -/* QPI Enable */ -#define W25Q_STATUS2_QE_BIT 1 -#define W25Q_STATUS2_QE_MASK (1 << W25Q_STATUS2_QE_BIT) - -// Flash power up/down timings -#define W25Q_POWER_DOWN_DELAY_US 3 -#define W25Q_RELEASE_POWER_DOWN_DELAY_US 3 -#define W25Q_POWER_UP_DELAY_US 10 - -#if (dg_configFLASH_POWER_OFF == 1) -/** - * \brief uCode for handling the QSPI FLASH activation from power off. - */ - /* - * Should work with all Winbond flashes -- verified with W25Q80EW. - * - * Delay 10usec - * 0x01 // CMD_NBYTES = 0, CMD_TX_MD = 0 (Single), CMD_VALID = 1 - * 0xA0 // CMD_WT_CNT_LS = 160 --> 10000 / 62.5 = 160 = 10usec - * 0x00 // CMD_WT_CNT_MS = 0 - * Exit from Fast Read mode - * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 - * 0x00 // CMD_WT_CNT_LS = 0 - * 0x00 // CMD_WT_CNT_MS = 0 - * 0xFF // Enable Reset - * (up to 16 words) - */ - const uint32_t w25q_ucode_wakeup[] = { - 0x09000001 | (((uint16_t)(W25Q_POWER_UP_DELAY_US*1000/62.5) & 0xFFFF) << 8), - 0x00FF0000, - }; -#elif (dg_configFLASH_POWER_DOWN == 1) -/** - * \brief uCode for handling the QSPI FLASH release from power-down. - */ - /* - * Should work with all Winbond flashes -- verified with W25Q80EW. - * - * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 - * 0x30 // CMD_WT_CNT_LS = 3000 / 62.5 = 48 // 3usec - * 0x00 // CMD_WT_CNT_MS = 0 - * 0xAB // Release Power Down - * (up to 16 words) - */ - const uint32_t w25q_ucode_wakeup[] = { - 0xAB000009 | (((uint16_t)(W25Q_RELEASE_POWER_DOWN_DELAY_US*1000/62.5) & 0xFFFF) << 8), - }; -#else -/** - * \brief uCode for handling the QSPI FLASH exit from the "Continuous Read Mode". - */ - /* - * Should work with all Winbond flashes -- verified with W25Q80EW. - * - * 0x25 // CMD_NBYTES = 4, CMD_TX_MD = 2 (Quad), CMD_VALID = 1 - * 0x00 // CMD_WT_CNT_LS = 0 - * 0x00 // CMD_WT_CNT_MS = 0 - * 0x55 // Clocks 0-1 (A23-16) - * 0x55 // Clocks 2-3 (A15-8) - * 0x55 // Clocks 4-5 (A7-0) - * 0x55 // Clocks 6-7 (M7-0) : M5-4 != '10' ==> Disable "Continuous Read Mode" - * (up to 16 words) - */ - const uint32_t w25q_ucode_wakeup[] = { - 0x55000025, - 0x00555555, - }; -#endif - -static bool flash_w25q_is_suspended(void); -static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density); -static void flash_w25q_deactivate_command_entry_mode(void); - -/** - * \brief Enable volatile writes to Status Register bits - * \details When this command is issued, any writes to any of the Status Registers of the Flash are - * done as volatile writes. This command is valid only when the Write Status Register command - * follows. - * - * \note This function blocks until the Flash has processed the command. - */ -static inline void flash_w25q_wre_volatile(void) __attribute__((always_inline)) __attribute__((unused)); -static inline void flash_w25q_wre_volatile(void) -{ - uint8_t cmd[] = { W25Q_WRITE_ENABLE_NON_VOL }; - - qspi_write(cmd, 1); - - /* Verify */ - while (flash_is_busy()); -} - -static inline uint8_t flash_w25q_read_status_register_2(void) __attribute__((always_inline)); -static inline uint8_t flash_w25q_read_status_register_2(void) -{ - __DBG_QSPI_VOLATILE__ uint8_t status; - uint8_t cmd[] = { W25Q_READ_STATUS_REGISTER2 }; - - qspi_transact(cmd, 1, &status, 1); - - return status; -} - -/** - * \brief Write the Status Register 2 of the Flash - * - * \param[in] value The value to be written. - * - * \note This function blocks until the Flash has processed the command. No verification that the - * value has been actually written is done though. It is up to the caller to decide whether - * such verification is needed or not and execute it on its own. - */ -static inline void flash_w25q_write_status_register_2(uint8_t value) __attribute__((always_inline)); -static inline void flash_w25q_write_status_register_2(uint8_t value) -{ - uint8_t cmd[] = { W25Q_WRITE_STATUS_REGISTER2, value }; - - qspi_write(cmd, 2); - - /* Wait for the Flash to process the command */ - while (flash_is_busy()); -} - -static inline void flash_w25q_enable_quad_mode(void) __attribute__((always_inline)); -static inline void flash_w25q_enable_quad_mode(void) -{ - uint8_t status; - - status = flash_w25q_read_status_register_2(); - if (!(status & W25Q_STATUS2_QE_MASK)) { - flash_write_enable(); - flash_w25q_write_status_register_2(status | W25Q_STATUS2_QE_MASK); - } -} - -__RETAINED_CODE static bool flash_w25q_is_suspended(void) -{ - __DBG_QSPI_VOLATILE__ uint8_t status; - - status = flash_w25q_read_status_register_2(); - return (status & W25Q_STATUS2_SUS_MASK) != 0; -} - -__RETAINED_CODE static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density) -{ - flash_activate_command_entry_mode(); - - flash_w25q_enable_quad_mode(); - - flash_deactivate_command_entry_mode(); -} - -__RETAINED_CODE static void flash_w25q_deactivate_command_entry_mode(void) -{ -} - -#endif - -#endif /* _QSPI_WINBOND_H_ */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c b/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c deleted file mode 100644 index b0f2f2c8c..000000000 --- a/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c +++ /dev/null @@ -1,1179 +0,0 @@ -/** - **************************************************************************************** - * - * @file qspi_automode.c - * - * @brief Access QSPI flash when running in auto mode - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#include -#include -#include -#include "sdk_defs.h" - -#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) -#include "osal.h" -#include "sys_power_mgr.h" -#endif - -#include "hw_cpm.h" - -#include "hw_qspi.h" -#include "qspi_automode.h" - -/* - * QSPI controller allows to execute code directly from QSPI flash. - * When code is executing from flash there is no possibility to reprogram it. - * To be able to modify flash memory while it is used for code execution it must me assured that - * during the time needed for erase/write no code is running from flash. - */ - -/* - * Flash specific defines - */ - -/* SUS bit delay after SUSPEND command */ -#define FLASH_SUS_DELAY (20) // in usec - -/* Flash page size */ -#define FLASH_MAX_WRITE_SIZE dg_configFLASH_MAX_WRITE_SIZE - -/* - * Use QUAD mode for page write. - * - * Note: If the flash does not support QUAD mode or it is not connected for QUAD mode set it to 0 - * (single mode). - */ -#ifndef QUAD_MODE -#define QUAD_MODE 1 -#endif - -#ifndef ERASE_IN_AUTOMODE -#define ERASE_IN_AUTOMODE 1 -#endif - -#ifndef FLASH_FORCE_24BIT_ADDRESSING -#define FLASH_FORCE_24BIT_ADDRESSING 0 // Force 24 bit addressing for devices > 128Mbits -#endif - -/* - * WARNING: The Autodetect mode will greatly increase both the code and the used RetRAM size!!!! - * Use with extreme caution!! - */ -#if dg_configFLASH_AUTODETECT == 1 - #define FLASH_AUTODETECT 1 // Enable Flash auto-detection -#else - #if !defined(dg_configFLASH_MANUFACTURER_ID) - #error Please define dg_configFLASH_MANUFACTURER_ID !!! - #endif - #if !defined(dg_configFLASH_DEVICE_TYPE) - #error Please define dg_configFLASH_DEVICE_TYPE !!! - #endif - #if !defined(dg_configFLASH_DENSITY) - #error Please define dg_configFLASH_DENSITY !!! - #endif - #define FLASH_AUTODETECT 0 -#endif - -#if FLASH_AUTODETECT == 1 -#include "qspi_w25q80ew.h" -#include "qspi_mx25u51245.h" -#include "qspi_gd25lq80b.h" -#else -#ifndef dg_configFLASH_HEADER_FILE -#error Please define macro dg_configFLASH_HEADER_FILE to the header file name that contains the respective implementation -#endif -#include dg_configFLASH_HEADER_FILE -#endif - -#if (FLASH_AUTODETECT == 1) - -static const qspi_flash_config_t* flash_config_table[] = { - &flash_w25q80ew_config, // This is the default one - &flash_mx25u51245_config, - &flash_gd25lq80b_config, -}; - -__RETAINED static qspi_flash_config_t flash_autodetect_config; - -__RETAINED qspi_flash_config_t * flash_config; - -#endif - - - -/* - * Function definitions - */ - -/** - * \brief Set bus mode to single or QUAD mode. - * - * \param[in] mode Can be single (HW_QSPI_BUS_MODE_SINGLE) or quad (HW_QSPI_BUS_MODE_QUAD) mode. - * - * \note DUAL mode page program so is not supported by this function. - */ -static inline void qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) __attribute__((always_inline)); - -static inline void qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) -{ - if (mode == HW_QSPI_BUS_MODE_SINGLE) { - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE); - QSPIC->QSPIC_CTRLMODE_REG |= - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_DAT, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_DAT, 1); - } else { -#if QUAD_MODE - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD); - QSPIC->QSPIC_CTRLMODE_REG &= - ~(BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | - BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1)); -#endif - } -} - -/** - * \brief Set the mode of the QSPI controller (manual or auto) - * - * \param[in] automode True for auto and false for manual mode setting. - */ -static inline void qspi_set_automode(bool automode) __attribute__((always_inline)); - -static inline void qspi_set_automode(bool automode) -{ - REG_SETF(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_AUTO_MD, automode); -} - -/** - * \brief Write to the Flash the contents of a buffer - * - * \param[in] wbuf Pointer to the beginning of the buffer - * \param[in] wlen The number of bytes to be written - * - * \note The data are transferred as bytes (8 bits wide). No optimization is done in trying to use - * faster access methods (i.e. transfer words instead of bytes whenever it is possible). - */ -__RETAINED_CODE static void qspi_write(const uint8_t *wbuf, size_t wlen) -{ - size_t i; - - hw_qspi_cs_enable(); - - for (i = 0; i < wlen; ++i) { - hw_qspi_write8(wbuf[i]); - } - - hw_qspi_cs_disable(); -} - -/** - * \brief Write an arbitrary number of bytes to the Flash and then read an arbitrary number of bytes - * from the Flash in one transaction - * - * \param[in] wbuf Pointer to the beginning of the buffer that contains the data to be written - * \param[in] wlen The number of bytes to be written - * \param[in] rbuf Pointer to the beginning of the buffer than the read data are stored - * \param[in] rlen The number of bytes to be read - * - * \note The data are transferred as bytes (8 bits wide). No optimization is done in trying to use - * faster access methods (i.e. transfer words instead of bytes whenever it is possible). - */ -__RETAINED_CODE static void qspi_transact(const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, size_t rlen) -{ - size_t i; - - hw_qspi_cs_enable(); - - for (i = 0; i < wlen; ++i) { - hw_qspi_write8(wbuf[i]); - } - - for (i = 0; i < rlen; ++i) { - rbuf[i] = hw_qspi_read8(); - } - - hw_qspi_cs_disable(); -} - - -static inline bool flash_erase_program_in_progress(void) -{ - __DBG_QSPI_VOLATILE__ uint8_t status; - uint8_t cmd[] = { flash_config->read_erase_progress_opcode }; - - qspi_transact(cmd, 1, &status, 1); - - return ((status & (1 << flash_config->erase_in_progress_bit)) != 0) == flash_config->erase_in_progress_bit_high_level; -} - - -static inline bool flash_is_busy(void) -{ - return (flash_read_status_register() & FLASH_STATUS_BUSY_MASK) != 0; -} - -/** - * \brief Exit from continuous mode. - */ -__RETAINED_CODE static void flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE break_seq_size) -{ - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_EXIT_CONTINUOUS_MODE); - if (break_seq_size == HW_QSPI_BREAK_SEQ_SIZE_2B) { - hw_qspi_write8(CMD_EXIT_CONTINUOUS_MODE); - } - hw_qspi_cs_disable(); - - while (flash_is_busy()); -} - -/** - * \brief Get Device ID when Flash is not in Power Down mode - * - * \return uint8_t The Device ID of the Flash - * - * \note The function blocks until the Flash executes the command. - */ -__RETAINED_CODE __attribute__((unused)) static uint8_t flash_get_id(void) -{ - uint8_t id; - - hw_qspi_cs_enable(); - hw_qspi_write32(CMD_RELEASE_POWER_DOWN); - id = hw_qspi_read8(); - hw_qspi_cs_disable(); - - while (flash_is_busy()); - - return id; -} - -/** - * \brief Set WEL (Write Enable Latch) bit of the Status Register of the Flash - * \details The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, - * Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers - * instruction. In the case of Write Status Register command, any status bits will be written - * as non-volatile bits. - * - * \note This function blocks until the Flash has processed the command and it will be repeated if, - * for any reason, the command was not successfully executed by the Flash. - */ -__RETAINED_CODE static void flash_write_enable(void) -{ - __DBG_QSPI_VOLATILE__ uint8_t status; - uint8_t cmd[] = { CMD_WRITE_ENABLE }; - - do { - qspi_write(cmd, 1); - /* Verify */ - do { - status = flash_read_status_register(); - } while (status & FLASH_STATUS_BUSY_MASK); - } while (!(status & FLASH_STATUS_WEL_MASK)); -} - -/** - * \brief Read the Status Register 1 of the Flash - * - * \return uint8_t The value of the Status Register 1 of the Flash. - */ -__RETAINED_CODE static uint8_t flash_read_status_register(void) -{ - __DBG_QSPI_VOLATILE__ uint8_t status; - uint8_t cmd[] = { CMD_READ_STATUS_REGISTER }; - - qspi_transact(cmd, 1, &status, 1); - - return status; -} - -/** - * \brief Write the Status Register 1 of the Flash - * - * \param[in] value The value to be written. - * - * \note This function blocks until the Flash has processed the command. No verification that the - * value has been actually written is done though. It is up to the caller to decide whether - * such verification is needed or not and execute it on its own. - */ -__RETAINED_CODE __attribute__((unused)) static void flash_write_status_register(uint8_t value) -{ - uint8_t cmd[2] = { CMD_WRITE_STATUS_REGISTER, value }; - - qspi_write(cmd, 2); - - /* Wait for the Flash to process the command */ - while (flash_is_busy()); -} - -/** - * \brief Fast copy of a buffer to a FIFO - * \details Implementation of a fast copy of the contents of a buffer to a FIFO in assembly. All - * addresses are word aligned. - * - * \param[in] start Pointer to the beginning of the buffer - * \param[in] end Pointer to the end of the buffer - * \param[in] Pointer to the FIFO - * - * \warning No validity checks are made! It is the responsibility of the caller to make sure that - * sane values are passed to this function. - */ -static inline -void fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t dest) __attribute__((always_inline)); - -static inline void fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t dest) -{ - __asm volatile( "copy: \n" - " ldmia %[start]!, {r3} \n" - " str r3, [%[dest]] \n" - " cmp %[start], %[end] \n" - " blt copy \n" - : - : /* output */ - [start] "l" (start), [end] "r" (end), [dest] "l" (dest) : /* inputs (%0, %1, %2) */ - "r3"); /* registers that are destroyed */ -} - -/** - * \brief Write data (up to 1 page) to Flash - * - * \param[in] addr The address of the Flash where the data will be written. It may be anywhere in a - * page. - * \param[in] buf Pointer to the beginning of the buffer that contains the data to be written. - * \param[in] size The number of bytes to be written. - * - * \return size_t The number of bytes written. - * - * \warning The boundary of the page where addr belongs to, will not be crossed! The caller should - * issue another flash_write_page() call in order to write the remaining data to the next - * page. - */ -__RETAINED_CODE static size_t flash_write_page(uint32_t addr, const uint8_t *buf, uint16_t size) -{ - size_t i = 0; - size_t odd = ((uint32_t) buf) & 3; - size_t size_aligned32; - size_t tmp; - - DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_PAGE_PROG); - - flash_write_enable(); - - /* Reduce max write size, that can reduce interrupt latency time */ - if (size > FLASH_MAX_WRITE_SIZE) { - size = FLASH_MAX_WRITE_SIZE; - } - - /* Make sure write will not cross page boundary */ - tmp = 256 - (addr & 0xFF); - if (size > tmp) { - size = tmp; - } - - hw_qspi_cs_enable(); - - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { - hw_qspi_write8(flash_config->page_program_opcode); -#if QUAD_MODE - if (flash_config->quad_page_program_address == true) { - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); - } -#endif - hw_qspi_write32((addr >> 24) | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); -#if QUAD_MODE - if (flash_config->quad_page_program_address == false) { - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); - } -#endif - } - else { - if (flash_config->quad_page_program_address == true) { - hw_qspi_write8(flash_config->page_program_opcode); -#if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); -#endif - hw_qspi_write16(((addr >> 16) & 0xFF) | (addr & 0xFF00)); - hw_qspi_write8(addr & 0xFF); - } - else { - hw_qspi_write32(CMD_QUAD_PAGE_PROGRAM | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); -#if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); -#endif - } - } - - if (odd) { - odd = 4 - odd; - for (i = 0; i < odd && i < size; ++i) { - hw_qspi_write8(buf[i]); - } - } - - size_aligned32 = ((size - i) & ~0x3); - - if (size_aligned32) { - fast_write_to_fifo32((uint32_t)(buf + i), (uint32_t)(buf + i + size_aligned32), - (uint32_t)&(QSPIC->QSPIC_WRITEDATA_REG)); - i += size_aligned32; - } - - for (; i < size; i++) { - hw_qspi_write8(buf[i]); - } - - hw_qspi_cs_disable(); - - DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_PAGE_PROG); - -#if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); -#endif - - return i; -} - -/** - * \brief Erase a sector of the Flash - * - * \param[in] addr The address of the sector to be erased. - * - * \note This function blocks until the Flash has processed the command. - */ -__RETAINED_CODE __attribute__((unused)) static void flash_erase_sector(uint32_t addr) -{ - flash_write_enable(); - - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { - uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 5); - } - else { - uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 4); - } - - - /* Wait for the Flash to process the command */ - while (flash_erase_program_in_progress()); -} - -/** - * \brief Check if the Flash can accept commands - * - * \return bool True if the Flash is not busy else false. - * - */ -__RETAINED_CODE static bool qspi_writable(void) -{ - bool writable; - - /* - * From now on QSPI may not be available, turn off interrupts. - */ - GLOBAL_INT_DISABLE(); - - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); - - /* - * Check if flash is ready. - */ - writable = !(flash_is_busy()); - - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); - - /* - * Let other code to be executed including QSPI one. - */ - GLOBAL_INT_RESTORE(); - - return writable; -} - -/** - * \brief Get the status of an Erase when it is done automatically by the QSPI controller - * - * \return uint8_t The status of the Erase - * 0: No Erase - * 1: Pending erase request - * 2: Erase procedure is running - * 3: Suspended Erase procedure - * 4: Finishing the Erase procedure - */ -__RETAINED_CODE __attribute__((unused)) static uint8_t qspi_get_erase_status(void) -{ - QSPIC->QSPIC_CHCKERASE_REG = 0; - - return HW_QSPIC_REG_GETF(ERASECTRL, ERS_STATE); -} - -/** - * \brief Get the address size used by the QSPI controller - * - * \return The address size used (HW_QSPI_ADDR_SIZE_24 or HW_QSPI_ADDR_SIZE_32). - */ -static inline HW_QSPI_ADDR_SIZE qspi_get_address_size(void) __attribute__((always_inline)); - -static inline HW_QSPI_ADDR_SIZE qspi_get_address_size(void) -{ - return (HW_QSPI_ADDR_SIZE)HW_QSPIC_REG_GETF(CTRLMODE, USE_32BA); -} - -__RETAINED_CODE void flash_activate_command_entry_mode(void) -{ - /* - * Turn off auto mode to allow write. - */ - qspi_set_automode(false); - - /* - * Switch to single mode for command entry. - */ - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - - /* - * Exit continuous mode (QPI mode), after this the flash will interpret commands again. - */ - if (flash_config->send_once != 0) { - flash_reset_continuous_mode(flash_config->break_seq_size); - } -} - - -__RETAINED_CODE void flash_deactivate_command_entry_mode(void) -{ - flash_config->deactivate_command_entry_mode(); - -#if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); -#endif - qspi_set_automode(true); -} - -#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) -__RETAINED_CODE void flash_erase_sector_manual_mode(uint32_t addr) -{ - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); - - /* - * Issue the erase sector command. - */ - flash_write_enable(); - - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { - uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 5); - } - else { - uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; - qspi_write(cmd, 4); - } - - /* - * Flash stays in manual mode. - */ -} - -__RETAINED_CODE size_t flash_program_page_manual_mode(uint32_t addr, const uint8_t *buf, uint16_t size) -{ - size_t written = flash_write_page(addr, buf, size); - - /* - * Flash stays in manual mode. - */ - - return written; -} - -__RETAINED_CODE bool qspi_check_program_erase_in_progress(void) -{ - return flash_is_busy(); -} - -__RETAINED_CODE bool qspi_check_and_suspend(void) -{ - uint8_t cmd[] = { flash_config->erase_suspend_opcode }; - bool am = hw_qspi_get_automode(); - bool ret = true; - - if (am) { - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); - } - - /* - * Suspend action. - */ - DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); - - /* - * Check if an operation is ongoing. - */ - while (flash_erase_program_in_progress()) { - qspi_write(cmd, 1); - } - - hw_cpm_delay_usec(FLASH_SUS_DELAY); // Wait for SUS bit to be updated - - DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); - - if (flash_config->is_suspended() == false) { - ret = false; - } - - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); - - return ret; -} - -__RETAINED_CODE void qspi_resume(void) -{ - uint8_t cmd[] = { flash_config->erase_resume_opcode }; - - do { - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); - - /* - * Check if suspended. - */ - if (flash_config->is_suspended() == false) { - break; - } - - /* - * Wait for flash to become ready again. - */ - do { - /* - * Resume action. - */ - qspi_write(cmd, 1); - - /* - * Check if SUS bit is cleared. - */ - } while (flash_config->is_suspended()); - } while (0); - - /* - * Flash stays in manual mode. - */ -} -#endif - -#if (ERASE_IN_AUTOMODE == 1) -/** - * \brief Erase sector (via CPM background processing or using the QSPI controller) - * - * \details This function will execute a Flash sector erase operation. The operation will either be - * carried out immediately (dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 1) or it will be - * deferred to be executed by the CPM when the system becomes idle (when - * dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 0, default value). In the latter case, the - * caller will block until the CPM completes the registered erase operation. - * - * \param[in] addr The address of the sector to be erased. - */ -__RETAINED_CODE static void qspi_erase_sector(uint32_t addr) -{ -#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) - OS_TASK handle; - void *op; - - handle = OS_GET_CURRENT_TASK(); - - /* Instruct CPM to erase this sector */ - if (pm_register_qspi_operation(handle, addr, NULL, 0, &op)) { - /* Block until erase is completed */ - OS_TASK_SUSPEND(handle); - OS_FREE(op); - } - else { - /* The PM has not started yet... */ - -#endif - /* Wait for previous erase to end */ - while (qspi_get_erase_status() != 0) { - } - - if (qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32) { - addr >>= 12; - } else { - addr >>= 4; - } - - /* Setup erase block page */ - HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr); - - /* Fire erase */ - HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); -#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) - } -#endif -} -#endif /* (ERASE_IN_AUTOMODE == 1) */ - -/** - * \brief Write data to a page in the Flash (via CPM background processing or using the QSPI - * controller) - * - * \details This function will execute a Flash program page operation. The operation will either be - * carried out immediately (dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 1) or it will be - * deferred to be executed by the CPM when the system becomes idle (when - * dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 0, default value). In the latter case, the - * caller will block until the CPM completes the registered page program operation. - * - * \param[in] addr The address of the Flash where the data will be written. It may be anywhere in a - * page. - * \param[in] buf Pointer to the beginning of the buffer that contains the data to be written. - * \param[in] size The number of bytes to be written. - * - * \return size_t The number of bytes written. - * - * \warning The caller should ensure that buf does not point to QSPI mapped memory. - */ -__RETAINED_CODE static size_t write_page(uint32_t addr, const uint8_t *buf, uint16_t size) -{ - size_t written; - -#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) - OS_TASK handle; - void *op; - - handle = OS_GET_CURRENT_TASK(); - - /* Instruct CPM to program this sector */ - if (pm_register_qspi_operation(handle, addr, buf, &size, &op)) { - /* Block until program is completed */ - OS_TASK_SUSPEND(handle); - OS_FREE(op); - written = size; - } - else { -#endif - /* - * From now on QSPI may not be available, turn of interrupts. - */ - GLOBAL_INT_DISABLE(); - - /* - * Turn on command entry mode. - */ - flash_activate_command_entry_mode(); - - /* - * Write data into the page of the Flash. - */ - written = flash_write_page(addr, buf, size); - - /* Wait for the Flash to process the command */ - while (flash_erase_program_in_progress()); - - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); - - /* - * Let other code to be executed including QSPI one. - */ - GLOBAL_INT_RESTORE(); -#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) - } -#endif - - return written; -} - -/** - * \brief Erase a sector of the Flash - * - * \details The time and the way that the operation will be carried out depends on the following - * settings: - * ERASE_IN_AUTOMODE = 0: the command is issued immediately in manual mode - * ERASE_IN_AUTOMODE = 1: - * dg_configDISABLE_BACKGROUND_FLASH_OPS = 0: the operation is executed manually by the - * CPM when the system becomes idle - * dg_configDISABLE_BACKGROUND_FLASH_OPS = 1: the operation is executed automatically - * by the QSPI controller. - * - * \param[in] addr The address of the sector to be erased. - */ -__RETAINED_CODE static void erase_sector(uint32_t addr) -{ -#if ERASE_IN_AUTOMODE - /* - * Erase sector in automode - */ - qspi_erase_sector(addr); - - /* - * Wait for erase to finish - */ - while (qspi_get_erase_status()) { - } -#else - /* - * From now on QSPI may not be available, turn of interrupts. - */ - GLOBAL_INT_DISABLE(); - - /* - * Turn off auto mode to allow write. - */ - qspi_set_automode(false); - - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - - /* - * Exit continuous mode, after this the flash will interpret commands again. - */ - flash_reset_continuous_mode(flash_config->break_seq_size); - - /* - * Execute erase command. - */ - flash_erase_sector(addr); - - /* - * Restore auto mode. - */ - flash_deactivate_command_entry_mode(); - - /* - * Let other code to be executed including QSPI one. - */ - GLOBAL_INT_RESTORE(); -#endif -} - -uint32_t qspi_automode_get_code_buffer_size(void) -{ - /* Return 1 in case some code will pass this value to memory allocation function */ - return 1; -} - -void qspi_automode_set_code_buffer(void *ram) -{ - (void) ram; /* Unused */ -} - -bool qspi_automode_writable(void) -{ - return qspi_writable(); -} - -size_t qspi_automode_write_flash_page(uint32_t addr, const uint8_t *buf, size_t size) -{ - while (!qspi_automode_writable()) { - } - - return write_page(addr, buf, size); -} - -void qspi_automode_erase_flash_sector(uint32_t addr) -{ - while (!qspi_automode_writable()) { - } - - erase_sector(addr); -} - -void qspi_automode_erase_chip(void) -{ - flash_activate_command_entry_mode(); - - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_WRITE_ENABLE); - hw_qspi_cs_disable(); - - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_CHIP_ERASE); - hw_qspi_cs_disable(); - - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_READ_STATUS_REGISTER); - while (hw_qspi_read8() & FLASH_STATUS_BUSY_MASK); - hw_qspi_cs_disable(); - - flash_deactivate_command_entry_mode(); -} - -size_t qspi_automode_read(uint32_t addr, uint8_t *buf, size_t len) -{ - memcpy(buf, (void *)(MEMORY_QSPIF_BASE + addr), len); - - return len; -} - -__RETAINED_CODE void qspi_automode_flash_power_up(void) -{ - hw_cpm_delay_usec(flash_config->power_down_delay); - - /* Interrupts must be turned off since the flash goes in manual mode, and - * code (e.g. for an ISR) cannot be fetched from flash during this time - */ - GLOBAL_INT_DISABLE(); - - // Do not call flash_activate_command_entry_mode(). This function will call - // flash_reset_continuous_mode which will try to send break sequence to the QSPI Flash - // which is in power-down mode. - qspi_set_automode(false); - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_RELEASE_POWER_DOWN); - hw_qspi_cs_disable(); - - flash_deactivate_command_entry_mode(); - - /* - * The flash is in auto mode again. Re-enable the interrupts - */ - GLOBAL_INT_RESTORE(); - - hw_cpm_delay_usec(flash_config->release_power_down_delay); -} - -__RETAINED_CODE void qspi_automode_flash_power_down(void) -{ - flash_activate_command_entry_mode(); - - hw_qspi_cs_enable(); - hw_qspi_write8(CMD_ENTER_POWER_DOWN); - hw_qspi_cs_disable(); - -// Do not call flash_deactivate_command_entry_mode(). This function will call -// flash_config->deactivate_command_entry_mode() which will try to send commands to the QSPI Flash -// which has already been set in power-down mode. - -// flash_deactivate_command_entry_mode(); - -#if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); -#endif - qspi_set_automode(true); -} - -static qspi_config qspi_cfg = { - HW_QSPI_ADDR_SIZE_24, HW_QSPI_POL_HIGH, HW_QSPI_SAMPLING_EDGE_NEGATIVE -}; - -/** - * \brief Read the JEDEC manufacturer ID, device type and device density using command 0x9F - * - * \param[in] manufacturer_id Pointer to the variable where the manufacturer ID will be returned - * \param[in] device_type Pointer to the variable where the device type will be returned - * \param[in] density Pointer to the variable where the device density will be returned - */ -#if FLASH_AUTODETECT -__RETAINED_CODE static void flash_read_jedec_id(uint8_t *manufacturer_id, uint8_t *device_type, uint8_t *density) -{ - uint8_t cmd[] = { CMD_READ_JEDEC_ID }; - uint8_t buffer[3]; - - qspi_set_automode(false); - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - - // reset continuous mode using both one and two break bytes to cover all cases - flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_2B); - flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_1B); - - qspi_transact(cmd, 1, buffer, 3); - *manufacturer_id = buffer[0]; - *device_type = buffer[1]; - *density = buffer[2]; - -#if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); -#endif - qspi_set_automode(true); -} -#endif - -/** - * \brief Configure dummy bytes in QSPI controller - * - * \param[in] count Number of dummy bytes (not including extra byte) - */ -__RETAINED_CODE __attribute__((unused)) static void qspi_automode_set_dummy_bytes_count(uint8_t count) -{ - if (count == 3) { - HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1); - } else { - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, - dummy_num[count]); - } -} - -__RETAINED_CODE bool qspi_automode_init(void) -{ - uint8_t device_type; - uint8_t device_density; - - hw_qspi_enable_clock(); - - -#if __DBG_QSPI_ENABLED - REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, 3); -#endif - -#if FLASH_AUTODETECT - uint8_t manufacturer_id; - uint8_t i; - - - flash_read_jedec_id(&manufacturer_id, &device_type, &device_density); - - const qspi_flash_config_t* flash_config_init = flash_config_table[0]; // default to first entry. - - for (i=0; i< sizeof(flash_config_table)/sizeof(qspi_flash_config_t*); i++) { - if ( (flash_config_table[i]->manufacturer_id == manufacturer_id) && - (flash_config_table[i]->device_type == device_type) && - (flash_config_table[i]->device_density == device_density)) { - flash_config_init = flash_config_table[i]; - break; - } - } - flash_autodetect_config = *flash_config_init; - flash_config = &flash_autodetect_config; -#else - device_type = dg_configFLASH_DEVICE_TYPE; - device_density = dg_configFLASH_DENSITY; -#endif - - /* - * Copy the selected flash struct from flash into retram - */ - flash_config->initialize(device_type, device_density); - - uint8_t read_opcode; - - if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) { - read_opcode = CMD_FAST_READ_QUAD_4B; - qspi_cfg.address_size = HW_QSPI_ADDR_SIZE_32; // It will be set when hw_qspi_init() is called - } - else { - read_opcode = CMD_FAST_READ_QUAD; - } - /* - * Setup erase instruction that will be sent by QSPI controller to erase sector in automode. - */ - hw_qspi_set_erase_instruction(flash_config->erase_opcode, HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_SINGLE, 15, 5); - /* - * Setup instruction pair that will temporarily suspend erase operation to allow read. - */ - hw_qspi_set_suspend_resume_instructions(flash_config->erase_suspend_opcode, HW_QSPI_BUS_MODE_SINGLE, - flash_config->erase_resume_opcode, HW_QSPI_BUS_MODE_SINGLE, 7); - - /* - * QSPI controller must send write enable before erase, this sets it up. - */ - hw_qspi_set_write_enable_instruction(CMD_WRITE_ENABLE, HW_QSPI_BUS_MODE_SINGLE); - - /* - * Setup instruction that will be used to periodically check erase operation status. - * Check LSB which is 1 when erase is in progress. - */ - hw_qspi_set_read_status_instruction(flash_config->read_erase_progress_opcode, HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_SINGLE, flash_config->erase_in_progress_bit, flash_config->erase_in_progress_bit_high_level?1:0, 20, 0); - - /* - * This sequence is necessary if flash is working in continuous read mode, when instruction - * is not sent on every read access just address. Sending 0xFFFF will exit this mode. - * This sequence is sent only when QSPI is working in automode and decides to send one of - * instructions above. - * If flash is working in DUAL bus mode sequence should be 0xFFFF and size should be - * HW_QSPI_BREAK_SEQ_SIZE_2B. - */ - hw_qspi_set_break_sequence(0xFFFF, HW_QSPI_BUS_MODE_SINGLE, flash_config->break_seq_size, 0); - - /* - * If application starts from FLASH then bootloader must have set read instruction. - */ - if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) { - hw_qspi_init(&qspi_cfg); - hw_qspi_set_div(HW_QSPI_DIV_1); - } - flash_activate_command_entry_mode(); - - hw_qspi_set_read_instruction(read_opcode, flash_config->send_once, flash_config->get_dummy_bytes(), HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_QUAD, HW_QSPI_BUS_MODE_QUAD, - HW_QSPI_BUS_MODE_QUAD); - hw_qspi_set_extra_byte(flash_config->extra_byte, HW_QSPI_BUS_MODE_QUAD, 0); - hw_qspi_set_address_size(flash_config->address_size); - - flash_deactivate_command_entry_mode(); - - HW_QSPIC_REG_SETF(BURSTCMDB, CS_HIGH_MIN, 0); - - return true; -} - -__RETAINED_CODE void qspi_automode_sys_clock_cfg(sys_clk_t sys_clk) -{ - if ((CRG_TOP->CLK_AMBA_REG & (1 << REG_POS(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE))) != 0) { // If clock is enabled - /* Some of the sys_clk_cfg() implementations put the flash in command entry mode, where the flash is - * not available for code execution. We must make sure that no interrupt (that may cause a cache miss) - * hits during this time. - */ - GLOBAL_INT_DISABLE(); - flash_config->sys_clk_cfg(sys_clk); - GLOBAL_INT_RESTORE(); - } -} - -const qspi_ucode_t *qspi_automode_get_ucode(void) -{ - return &flash_config->ucode_wakeup; -} diff --git a/third_party/dialog/DialogSDK/bsp/osal/osal.h b/third_party/dialog/DialogSDK/bsp/osal/osal.h deleted file mode 100644 index 5a88a8ea1..000000000 --- a/third_party/dialog/DialogSDK/bsp/osal/osal.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup OSAL - * - * \brief OS Abstraction Layer - * - * \{ - */ - -/** - **************************************************************************************** - * - * @file osal.h - * - * @brief OS abstraction layer API - * - * @brief Access QSPI flash when running in auto mode - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef OSAL_H_ -#define OSAL_H_ - -#if defined OS_BAREMETAL - -#include - -/* - * Basic set of macros that can be used in non OS environment. - */ -# define PRIVILEGED_DATA -# define OS_MALLOC malloc -# define OS_FREE free -# ifndef RELEASE_BUILD -# define OS_ASSERT(a) do { if (!(a)) {__BKPT(0);} } while (0) -# else -# define OS_ASSERT(a) ((void) (a)) -# endif - -#endif - -/** - * \brief Cast any pointer to unsigned int value - */ -#define OS_PTR_TO_UINT(p) ((unsigned) (void *) (p)) - -/** - * \brief Cast any pointer to signed int value - */ -#define OS_PTR_TO_INT(p) ((int) (void *) (p)) - -/** - * \brief Cast any unsigned int value to pointer - */ -#define OS_UINT_TO_PTR(u) ((void *) (unsigned) (u)) - -/** - * \brief Cast any signed int value to pointer - */ -#define OS_INT_TO_PTR(i) ((void *) (int) (i)) - -#endif /* OSAL_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h deleted file mode 100644 index e98faa2a2..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h +++ /dev/null @@ -1,767 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup AES_HASH - * \{ - * \brief AES/Hash Engine - */ - -/** - **************************************************************************************** - * - * @file hw_aes_hash.h - * - * @brief Definition of API for the AES/HASH Engine Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef HW_AES_HASH_H_ -#define HW_AES_HASH_H_ - -#if dg_configUSE_HW_AES_HASH - -#include -#include "sdk_defs.h" - -/** - * \brief AES/Hash callback - * - * This function is called by the AES/Hash driver when the interrupt is fired. - * - */ -typedef void (*hw_aes_hash_cb)(void); - -/** - * \brief AES key sizes. Possible values: HW_AES_128, HW_AES_192, HW_AES_256. - */ -typedef enum { - HW_AES_128 = 0, - HW_AES_192 = 1, - HW_AES_256 = 2 -} hw_aes_key_size; - -/** - * \brief AES direction. Possible values: HW_AES_DECRYPT, HW_AES_ENCRYPT. - */ -typedef enum { - HW_AES_DECRYPT = 0, - HW_AES_ENCRYPT = 1 -} hw_aes_direction; - -/** - * \brief AES/Hash modes. Possible values: HW_AES_ECB, HW_AES_CBC, HW_AES_CTR, HW_HASH_MD5, - * HW_AES_SHA_1, HW_AES_SHA_256_224, HW_AES_SHA_256, HW_AES_SHA_384, HW_AES_SHA_512, - * HW_AES_SHA_512_224, HW_AES_SHA_512_256. - */ -typedef enum { - HW_AES_ECB, - HW_AES_CBC, - HW_AES_CTR, - HW_HASH_MD5, - HW_HASH_SHA_1, - HW_HASH_SHA_256_224, - HW_HASH_SHA_256, - HW_HASH_SHA_384, - HW_HASH_SHA_512, - HW_HASH_SHA_512_224, - HW_HASH_SHA_512_256 -} hw_aes_hash_mode; - -/** - * \brief Key expansion modes. - * Possible values HW_AES_PERFORM_KEY_EXPANSION, HW_AES_DO_NOT_PERFORM_KEY_EXPANSION - */ -typedef enum { - HW_AES_PERFORM_KEY_EXPANSION = 0, /**< Key expansion is performed by the engine */ - HW_AES_DO_NOT_PERFORM_KEY_EXPANSION /**< Key expansion is performed by the software */ -} hw_aes_hash_key_exp_t; - -/** - \brief AES/Hash setup structure. - */ -typedef struct { - hw_aes_hash_mode mode; /**< AES/Hash mode. */ - hw_aes_direction aesDirection; /**< AES direction. Only used when the mode is an AES mode.*/ - hw_aes_key_size aesKeySize; /**< AES key size. Only used when the mode is an AES mode. */ - bool aesKeyExpand; /**< When true the key expansion process is execute. When false the key - expansion process is not executed. The user should write the AES keys in CRYPTO_RAM. - Only used when the mode is an AES mode. */ - uint32 aesKeys; /**< The start address of the buffer containing the AES key. */ - uint32 aesIvCtrblk_0_31; /**< In CBC mode IV[31:0] and in CTR mode the initial value of the - 32 bits counter. Only used when the mode is an AES CBC/CTR mode. */ - uint32 aesIvCtrblk_32_63; /**< In CBC mode IV[63:32] and in CTR[63:32]. - Only used when the mode is an AES CBC/CTR mode. */ - uint32 aesIvCtrblk_64_95; /**< In CBC mode IV[95:64] and in CTR[95:64]. - Only used when the mode is an AES CBC/CTR mode. */ - uint32 aesIvCtrblk_96_127; /**< In CBC mode IV[127:96] and in CTR[127:96]. - Only used when the mode is an AES CBC/CTR mode. */ - bool aesWriteBackAll; /**< When true all the AES resulting data is written to memory. - When false only the final block of the AES resulting data is written to memory. - Only used when the mode is an AES mode. */ - uint8 hashOutLength; /**< The number of bytes of the hash result to be saved to memory. - Only used when mode is a Hash mode. */ - bool moreDataToCome; /**< When false this is the last data block. When true more data is to - come. */ - uint32 sourceAddress; /**< The physical address of the input data that needs to be processed. */ - uint32 destinationAddress; /**< The physical address (RAM only) where the resulting data needs - to be written. If NULL the register is not written.*/ - uint32 dataSize; /**< The number of bytes that need to be processed. If this number is not - a multiple of a block size, the data is automatically extended with zeros. */ - bool enableInterrupt; /**< When true the callback function is called after the operation - has ended. */ - hw_aes_hash_cb callback; /**< The callback function that is called when enable interrupt - is true. */ -} hw_aes_hash_setup; - -/** - * \brief Enable AES/HASH engine clock - * - * This function enables the AES/HASH engine clock. - */ -__STATIC_INLINE void hw_aes_hash_enable_clock(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, AES_CLK_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Disable AES/HASH engine clock - * - * This function disables the AES/HASH engine clock. - */ -__STATIC_INLINE void hw_aes_hash_disable_clock(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, AES_CLK_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Check if AES/HASH engine clock is enabled - * - * \return Non-zero value if enabled, 0 otherwise - */ -__STATIC_INLINE int hw_aes_hash_clock_is_enabled(void) -{ - return (CRG_TOP->CLK_AMBA_REG) & (CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk); -} - -/** - * \brief AES/Hash enable. - * - * This function sets up and starts a AES/HASH engine operation. All the - * configuration details are included in the setup input structure. - * - * \param [in] setup The setup structure with setup values. - * - * \deprecated You can use hw_aes_hash_init with hw_aes_hash_start instead. - * - * \sa hw_aes_hash_init - * \sa hw_aes_hash_start - * - */ -void hw_aes_hash_enable(const hw_aes_hash_setup setup) DEPRECATED; - -/** - * \brief AES/Hash initialize. - * - * This function sets up a AES/HASH engine operation. All the configuration details - * are included in the setup input structure. The operation can then start by calling - * hw_aes_hash_start - * - * \param [in] setup The setup structure with setup values. - * - * \note There are some restrictions in the value of dataSize of the setup structure depending on - * the mode. This function will do appropriate checking using assertions. The following - * table shows what the value of dataSize should be: - * - * mode | moreDataToCome = true | moreDataToCome = false - * ------------------- | --------------------- | ---------------------- - * HW_AES_ECB | multiple of 16 | multiple of 16 - * HW_AES_CBC | multiple of 16 | no restrictions - * HW_AES_CTR | multiple of 16 | no restrictions - * HW_HASH_MD5 | multiple of 8 | no restrictions - * HW_HASH_SHA_1 | multiple of 8 | no restrictions - * HW_HASH_SHA_256_224 | multiple of 8 | no restrictions - * HW_HASH_SHA_256 | multiple of 8 | no restrictions - * HW_HASH_SHA_384 | multiple of 8 | no restrictions - * HW_HASH_SHA_512 | multiple of 8 | no restrictions - * HW_HASH_SHA_512_224 | multiple of 8 | no restrictions - * HW_HASH_SHA_512_256 | multiple of 8 | no restrictions - * - * \sa hw_aes_hash_start - * - */ -void hw_aes_hash_init(hw_aes_hash_setup *setup); - -/** - * \brief AES/Hash restart. - * - * This function restarts the AES/Hash engine. This function can be used when the engine waits for - * more input data. - * - * \param [in] sourceAddress The start address of the data that needs to be processed. - * \param [in] dataSize The number of bytes that need to be processed. If this number is not - * a multiple of a block size, the data is automatically extended with zeros. - * \param [in] moreDataToCome When false this is the last data block. When true more data is to - * come. - * - */ -void hw_aes_hash_restart(const uint32 sourceAddress, const uint32 dataSize, - const bool moreDataToCome); - -/** - * \brief AES/Hash is active. - * - * This function tells if the AES/Hash engine is active or not. - * - * \return True if the AES/Hash engine is active and false when it is inactive. - * - */ -bool hw_aes_hash_is_active(); - -/** - * \brief AES/Hash is waiting for more data. - * - * This function tells if the AES/Hash engine is waiting for more data or not. - * - * \return True if the AES/Hash engine is waiting more data and false when it is not. - * - */ -bool hw_aes_hash_wait_for_in(); - -/** - * \brief AES/Hash disable. - * - * This function disables the AES/HASH engine and its interrupt request signal. - * - * \param [in] waitTillInactive When true the AES/HASH engine is disabled after any pending operation - * finishes. When false the AES/Hash is disabled immediately. - * - */ -void hw_aes_hash_disable(const bool waitTillInactive); - -/** - * \brief Mark next input block as being last - * - * This function is used to configure the engine so as to consider the next input block - * as the last of the operation. When the operation finishes, the engine's status - * becomes "inactive". - */ -__STATIC_INLINE void hw_aes_hash_mark_input_block_as_last(void) -{ - REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN); -} - -/** - * \brief Mark next input block as not being last - * - * This function is used to configure the engine so as to expect more input blocks - * after the operation. When the operation finishes, the engine's status - * becomes "waiting for input". - */ -__STATIC_INLINE void hw_aes_hash_mark_input_block_as_not_last(void) -{ - REG_SET_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN); -} - -/** - * \brief Configure engine for AES ECB encryption/decryption - * - * This function configures the engine for AES ECB encryption/decryption - * - * \param[in] key_size The size of the key used in the encryption/decryption - * - * \warning AES ECB is not recommended for use in cryptographic protocols. - */ -__STATIC_INLINE void hw_aes_hash_cfg_aes_ecb(hw_aes_key_size key_size) -{ - uint32 crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEY_SZ, crypto_ctrl_reg, key_size); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for AES CTR encryption/decryption - * - * This function configures the engine for AES CTR encryption/decryption - * - * \param[in] key_size The size of the key used in the encryption/decryption - */ -__STATIC_INLINE void hw_aes_hash_cfg_aes_ctr(hw_aes_key_size key_size) -{ - uint32 crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 2); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEY_SZ, crypto_ctrl_reg, key_size); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for AES CBC encryption/decryption - * - * This function configures the engine for AES CBC encryption/decryption - * - * \param[in] key_size The size of the key used in the encryption/decryption - */ -__STATIC_INLINE void hw_aes_hash_cfg_aes_cbc(hw_aes_key_size key_size) -{ - uint32 crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 3); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEY_SZ, crypto_ctrl_reg, key_size); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for MD5 hash - * - * This function configures the engine to perform MD5 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 16. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_md5(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 16)? 15: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 0); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for SHA1 hash - * - * This function configures the engine to perform SHA1 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 20. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_sha1(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 20)? 19: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 1); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for SHA-224 hash - * - * This function configures the engine to perform SHA-224 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 28. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_sha_224(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 28)? 27: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 2); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for SHA-256 hash - * - * This function configures the engine to perform SHA-256 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 32. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_sha_256(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 32)? 31: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 3); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for SHA-384 hash - * - * This function configures the engine to perform SHA-384 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 48. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_sha_384(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 48)? 47: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 0); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for SHA-512 hash - * - * This function configures the engine to perform SHA-512 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 64. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_sha_512(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 64)? 63: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 1); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for SHA-512/224 hash - * - * This function configures the engine to perform SHA-512/224 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 28. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_sha_512_224(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 28)? 27: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 2); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Configure engine for SHA-512/256 hash - * - * This function configures the engine to perform SHA-512/256 hashing - * - * \param[in] result_size The size in bytes of the result that the engine will write - * to the output memory. Accepted values are 1 to 32. Out of - * range values are adjusted to the closest limit. - */ -__STATIC_INLINE void hw_aes_hash_cfg_sha_512_256(unsigned int result_size) -{ - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (result_size > 32)? 31: (result_size == 0)? 0 : (result_size - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypto_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypto_ctrl_reg, 3); - - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; -} - -/** - * \brief Store initialization vector in AES/HASH engine memory - * - * This function stores the initialization vector (IV) that is necessary for AES CBC - * mode. - * - * - * \sa hw_aes_store_ic - * - * \param[in] iv The address of the buffer containing the initialization vector - */ -void hw_aes_hash_store_iv(const uint8 *iv); - -/** - * \brief Store counter initialization in AES/HASH engine memory - * - * This function stores the counter initialization that is necessary for AES CTR - * mode. - * - * - * \sa hw_aes_store_iv - * - * \param[in] ic The address of the buffer containing the counter initialization - */ -void hw_aes_hash_store_ic(const uint8 *ic); - -/** - * \brief Store AES keys in AES/HASH engine memory - * - * This function stores the keys used for AES encryption/decryption in AES/HASH engine memory. - * If key expansion is performed by the engine, then aes_keys should contain only the base - * key. Otherwise it should contain all the expanded keys. - * - * \note - * After an AES operation with a certain key, further operations using the same key do not - * need storing it to the AES/HASH memory again. - * - * \param[in] key_size The size of the key used in the encryption/decryption - * \param[in] aes_keys The address of the buffer containing the keys - * \param[in] key_exp Define if key expansion will be performed by hw or sw - */ -void hw_aes_hash_store_keys(hw_aes_key_size key_size, const uint8 *aes_keys, hw_aes_hash_key_exp_t key_exp); - -/** - * \brief Configure DMA for data manipulation - * - * This function configures the DMA machine with the source and destination buffers. - * - * \param[in] src The physical address of the buffer containing the input data for the operation - * \param[in] dst The physical address (RAM or Cache RAM only) of the buffer where the output of the - * operation will be stored. The dst address must be NULL when configuring the DMA - * while the engine is waiting for more input data. - * \param[in] len The length of the input data - */ -void hw_aes_hash_cfg_dma(const uint8 *src, uint8 *dst, unsigned int len); - -/** - * \brief Start AES/HASH engine operation - * - * This function starts a AES/HASH operation. The operation depends on the configuration that - * has been applied before calling this function - * - * \sa hw_aes_hash_init - * - */ -__STATIC_INLINE void hw_aes_hash_start(void) -{ - AES_HASH->CRYPTO_START_REG = 1; -} - -/** - * \brief Start AES encryption - * - * This function starts an AES encryption. AES mode, key and input/output data should be configured - * before calling this function. - * - * \sa hw_aes_hash_init - * \sa hw_aes_hash_cfg_aes_ecb - * \sa hw_aes_hash_cfg_aes_ctr - * \sa hw_aes_hash_cfg_aes_cbc - * \sa hw_aes_hash_store_keys - * \sa hw_aes_hash_cfg_dma - */ -__STATIC_INLINE void hw_aes_hash_encrypt(void) -{ - REG_SET_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ENCDEC); - - AES_HASH->CRYPTO_START_REG = 1; -} - -/** - * \brief Start AES decryption - * - * This function starts an AES decryption. AES mode, key and input/output data should be configured - * before calling this function. - * - * \sa hw_aes_hash_init - * \sa hw_aes_hash_cfg_aes_ecb - * \sa hw_aes_hash_cfg_aes_ctr - * \sa hw_aes_hash_cfg_aes_cbc - * \sa hw_aes_hash_store_keys - * \sa hw_aes_hash_cfg_dma - */ -__STATIC_INLINE void hw_aes_hash_decrypt(void) -{ - REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ENCDEC); - - AES_HASH->CRYPTO_START_REG = 1; -} - -/** - * \brief Enable AES/HASH engine interrupt - * - * This function enables the AES/HASH engine interrupt and sets a callback function - * to be called when the interrupt occurs. - * - * \param[in] cb The callback function for the interrupt - * - * \deprecated Consider using hw_crypto API along with hw_aes_hash_enable_interrupt_source() - */ -DEPRECATED_MSG("consider using hw_crypto API along with hw_aes_hash_enable_interrupt_source") -void hw_aes_hash_enable_interrupt(hw_aes_hash_cb cb); - -/** - * \brief Disable AES/HASH engine interrupt - * - * This function disables the AES/HASH engine interrupt. - * - * \deprecated Consider using hw_crypto API along with hw_aes_hash_disable_interrupt_source() - */ -DEPRECATED_MSG("consider using hw_crypto API along with hw_aes_hash_disable_interrupt_source") -void hw_aes_hash_disable_interrupt(void); - -/** - * \brief Enable AES/HASH engine interrupt source - * - * This function enables AES/HASH engine interrupt source. - * - * \note AES/HASH engine and ECC engine are common sources of CRYPTO system interrupt. This - * function does not enable the CRYPTO interrupt itself. Use hw_crypto_enable_aes_hash_interrupt() - * in addition, in order to enable the CRYPTO interrupt. - */ -static inline void hw_aes_hash_enable_interrupt_source(void) -{ - REG_SET_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_IRQ_EN); -} - -/** - * \brief Disable AES/HASH engine interrupt source - * - * This function disables AES/HASH engine interrupt source. - * - * \note AES/HASH engine and ECC engine are common sources of CRYPTO system interrupt. This - * function does not disable the CRYPTO interrupt itself. Use hw_crypto_disable_aes_hash_interrupt() - * in order to disable the CRYPTO interrupt. - */ -static inline void hw_aes_hash_disable_interrupt_source(void) -{ - REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_IRQ_EN); -} - -/** - * \brief Clear AES/HASH engine pending interrupt - * - * This function clears AES/HASH engine pending interrupt request. - * - * \note AES/HASH engine and ECC engine are common sources of CRYPTO system interrupt. This - * function does not clear pending CRYPTO interrupt. Use hw_crypto_clear_pending_interrupt() - * in order to clear pending CRYPTO interrupt. - */ -static inline void hw_aes_hash_clear_interrupt_req(void) -{ - AES_HASH->CRYPTO_CLRIRQ_REG = 0x1; -} - -/** - * \brief Set output mode to write all - * - * This function configures the AES/HASH engine to write back to memory all the - * resulting data. - * - * \note - * Only applicable to AES operations. - */ -__STATIC_INLINE void hw_aes_hash_output_mode_write_all(void) -{ - REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_OUT_MD); -} - -/** - * \brief Set output mode to write final - * - * This function configures the AES/HASH engine to write back to memory only the - * the last block of the resulting data. - * - * \note - * Only applicable to AES operations. - */ -__STATIC_INLINE void hw_aes_hash_output_mode_write_final(void) -{ - REG_SET_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_OUT_MD); -} - -/** - * \brief Check input data size restriction - * - * This function checks the restrictions of input data length. It returns 0 if the restrictions are not - * violated, -1 otherwise. It checks the configured values at the time it is called so it should be - * used just before starting an operation. The function can be useful for debugging. The following - * table summarizes the restrictions for the input data length. - * - * ALGORITHM | NOT LAST DATA BLOCK | LAST DATA BLOCK - * ------------------- | --------------------- | ---------------- - * HW_AES_ECB | multiple of 16 | multiple of 16 - * HW_AES_CBC | multiple of 16 | no restrictions - * HW_AES_CTR | multiple of 16 | no restrictions - * HW_HASH_MD5 | multiple of 8 | no restrictions - * HW_HASH_SHA_1 | multiple of 8 | no restrictions - * HW_HASH_SHA_256_224 | multiple of 8 | no restrictions - * HW_HASH_SHA_256 | multiple of 8 | no restrictions - * HW_HASH_SHA_384 | multiple of 8 | no restrictions - * HW_HASH_SHA_512 | multiple of 8 | no restrictions - * HW_HASH_SHA_512_224 | multiple of 8 | no restrictions - * HW_HASH_SHA_512_256 | multiple of 8 | no restrictions - * - */ -int hw_aes_hash_check_restrictions(void); - -#endif /* dg_configUSE_HW_AES_HASH */ - -#endif /* HW_AES_HASH_H_ */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h deleted file mode 100644 index b99d16825..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h +++ /dev/null @@ -1,1463 +0,0 @@ -/** -\addtogroup BSP -\{ -\addtogroup DEVICES -\{ -\addtogroup CPM -\{ -\brief Clock and Power Manager -*/ - -/** - **************************************************************************************** - * - * @file hw_cpm.h - * - * @brief Clock and Power Manager header file. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef CPM_H_ -#define CPM_H_ - -#if dg_configUSE_HW_CPM - -#include "sdk_defs.h" - - -/** - * \addtogroup CLOCK_TYPES - * \brief Clock types - * \note These macros must only be used with hw_cpm_set_sysclk(). - * \{ - */ - -/** - * \brief System crystal oscillator 16 MHz - */ -#define SYS_CLK_IS_XTAL16M (0) -/** - * \brief System RC oscillator 16 MHz - */ -#define SYS_CLK_IS_RC16 (1) -/** - * \brief System Low Power clock - */ -#define SYS_CLK_IS_LP (2) -/** - * \brief System PLL - */ -#define SYS_CLK_IS_PLL (3) -/** - * \brief Low Power RC oscillator 32 kHz - */ -#define LP_CLK_IS_RC32K (0) -/** - * \brief Low Power RC oscillator 11.7 kHz - */ -#define LP_CLK_IS_RCX (1) -/** - * \brief Low Power crystal oscillator 32 kHz - */ -#define LP_CLK_IS_XTAL32K (2) -/** - * \brief Low Power external clock - */ -#define LP_CLK_IS_EXTERNAL (3) -/** - * \} - */ - -#define DCDC_IS_READY \ - (REG_MSK(DCDC, DCDC_STATUS_1_REG, DCDC_VDD_AVAILABLE)) -// (DCDC_V18P_AVAILABLE | DCDC_VDD_AVAILABLE | DCDC_V18_AVAILABLE | DCDC_V14_AVAILABLE) - -#define DCDC_IS_READY_TO_SLEEP (DCDC_VDD_AVAILABLE | DCDC_V14_AVAILABLE) - -typedef enum cal_clk_cel_type { - CALIBRATE_RC32K = 0, - CALIBRATE_RC16M, - CALIBRATE_XTAL32K, - CALIBRATE_RCX, -} cal_clk_t; - -/** - * \brief The system clock type - * \note Must only be used with functions cm_sys_clk_init/set() - * - */ -typedef enum sysclk_type { - sysclk_RC16 = 0, //!< RC16 - sysclk_XTAL16M = 1, //!< 1 x 16M - sysclk_XTAL32M = 2, //!< 2 x 16M - sysclk_PLL48 = 3, //!< 3 x 16M - sysclk_PLL96 = 6, //!< 6 x 16M - sysclk_LP = 255, //!< not applicable -} sys_clk_t; - -/** - * \brief The AMBA High-Performance Bus (AHB) clock divider - * - */ -typedef enum ahbdiv_type { - ahb_div1 = 0, //!< Divide by 1 - ahb_div2, //!< Divide by 2 - ahb_div4, //!< Divide by 4 - ahb_div8, //!< Divide by 8 - ahb_div16, //!< Divide by 16 -} ahb_div_t; - -ahb_div_t cm_ahbclk; -sys_clk_t cm_sysclk; - -/** - * \brief The AMBA Peripheral Bus (APB) clock divider - * - */ -typedef enum apbdiv_type { - apb_div1 = 0, //!< Divide by 1 - apb_div2, //!< Divide by 2 - apb_div4, //!< Divide by 4 - apb_div8, //!< Divide by 8 -} apb_div_t; - -/** - * \brief The CPU clock type (speed) - * - */ -typedef enum cpu_clk_type { - cpuclk_1M = 1, //!< 1 MHz - cpuclk_2M = 2, //!< 2 MHz - cpuclk_3M = 3, //!< 3 MHz - cpuclk_4M = 4, //!< 4 MHz - cpuclk_6M = 6, //!< 6 MHz - cpuclk_8M = 8, //!< 8 MHz - cpuclk_12M = 12, //!< 12 MHz - cpuclk_16M = 16, //!< 16 MHz - cpuclk_24M = 24, //!< 24 MHz - cpuclk_32M = 32, //!< 32 MHz - cpuclk_48M = 48, //!< 48 MHz - cpuclk_96M = 96 //!< 96 MHz -} cpu_clk_t; - - -/** - * \brief The TCS setting for the BOD control. - * \details If it is zero then the hard-coded SDK code for the BOD setup is used. It it is not zero, - * this is the value that is written to the BOD_CTRL2_REG. - */ -extern uint16_t hw_cpm_bod_enabled_in_tcs; - - -/** - * \brief Turn on the 1.2V LDO. - * - */ -__STATIC_INLINE void hw_cpm_turn_1_2V_on(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_turn_1_2V_on(void) -{ - REG_SET_BIT(CRG_TOP, LDO_CTRL2_REG, LDO_1V2_ON); -} - -/** - * \brief Turn off the 1.2V LDO. - * - */ -__STATIC_INLINE void hw_cpm_turn_1_2V_off(void) -{ - REG_CLR_BIT(CRG_TOP, LDO_CTRL2_REG, LDO_1V2_ON); -} - -/** - * \brief Enable Cache retainability. - * - */ -__STATIC_INLINE void hw_cpm_set_cache_retained(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Enable ECC microcode RAM retainment. - * - */ -__STATIC_INLINE void hw_cpm_set_eccram_retained(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_ECCRAM); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Enable QSPI initialization after wake-up. - * - */ -__STATIC_INLINE void hw_cpm_enable_qspi_init(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, QSPI_INIT); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Setup the Retention Memory configuration. - * - */ -__STATIC_INLINE void hw_cpm_setup_retmem(void) -{ - GLOBAL_INT_DISABLE(); - REG_SETF(CRG_TOP, PMU_CTRL_REG, RETAIN_RAM, dg_configMEM_RETENTION_MODE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Disable memory retention. - * - */ -__STATIC_INLINE void hw_cpm_no_retmem(void) -{ - GLOBAL_INT_DISABLE(); - CRG_TOP->PMU_CTRL_REG &= ~(REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_RAM) | - REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE) | - REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_ECCRAM)); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Enable the clock-less sleep mode. - * - */ -__STATIC_INLINE void hw_cpm_enable_clockless(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, ENABLE_CLKLESS); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Disable the clock-less sleep mode. - * - */ -__STATIC_INLINE void hw_cpm_disable_clockless(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, ENABLE_CLKLESS); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Activate the "Reset on wake-up" functionality. - * - */ -__STATIC_INLINE void hw_cpm_enable_reset_on_wup(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RESET_ON_WAKEUP); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Activate BOD protection. - * - */ -__RETAINED_CODE void hw_cpm_activate_bod_protection(void); - -/** - * \brief Activate BOD protection (non retained version). - * - */ -void hw_cpm_activate_bod_protection_at_init(void); - -/** - * \brief Configure BOD protection. - * - * \note Not applicable for DA14680/1-00 chips. - * - */ -void hw_cpm_configure_bod_protection(void); - -/** - * \brief Deactivate BOD protection. - * - */ -__STATIC_INLINE void hw_cpm_deactivate_bod_protection(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_deactivate_bod_protection(void) -{ - CRG_TOP->BOD_CTRL2_REG = 0; -} - -/** - * \brief Activate BOD protection for 1V4 rail (only for DA14682/3-00, DA15XXX-00 chips!). - * - */ -__STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void) -{ -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_V14_EN); -#endif -} - -/** - * \brief Deactivate BOD protection for 1V4 rail (only for DA14682/3-00, DA15XXX-00 chips!). - * - */ -__STATIC_INLINE void hw_cpm_deactivate_1v4_bod_protection(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_deactivate_1v4_bod_protection(void) -{ -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_V14_EN); -#endif -} - -/** - * \brief Power down the Radio Power Domain. - * - */ -__STATIC_INLINE void hw_cpm_power_down_radio(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Power down the Peripheral Power Domain. - * - */ -__STATIC_INLINE void hw_cpm_power_down_periph_pd(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_power_down_periph_pd(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, PERIPH_SLEEP); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Wait for Radio Power Domain Power down. - * - */ -__STATIC_INLINE void hw_cpm_wait_rad_power_down(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_wait_rad_power_down(void) -{ - while ((CRG_TOP->SYS_STAT_REG & REG_MSK(CRG_TOP, SYS_STAT_REG, RAD_IS_DOWN)) == 0); -} - -/** - * \brief Wait for Peripheral Power Domain Power down. - * - */ -__STATIC_INLINE void hw_cpm_wait_per_power_down(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_wait_per_power_down(void) -{ - while ((CRG_TOP->SYS_STAT_REG & REG_MSK(CRG_TOP, SYS_STAT_REG, PER_IS_DOWN)) == 0); -} - -/** - * \brief Power up the Peripherals Power Domain. - * - */ -__STATIC_INLINE void hw_cpm_power_up_per_pd(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_power_up_per_pd(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, PERIPH_SLEEP); - GLOBAL_INT_RESTORE(); - while ((CRG_TOP->SYS_STAT_REG & REG_MSK(CRG_TOP, SYS_STAT_REG, PER_IS_UP)) == 0); -} - -#if defined(CONFIG_USE_FTDF) -/** - * \brief Check the status of FTDF Power Domain. - * - * \return 0, if it is powered down and 1 if it is powered up. - * - */ -__STATIC_INLINE uint32_t hw_cpm_check_ftdf_pd_status(void) -{ - return REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP); -} -#endif - -#if defined(CONFIG_USE_BLE) -/** - * \brief Check the status of BLE Power Domain. - * - * \return 0, if it is powered down and 1 if it is powered up. - * - */ -__STATIC_INLINE uint32_t hw_cpm_check_ble_pd_status(void) -{ - return REG_GETF(CRG_TOP, SYS_STAT_REG, BLE_IS_UP); -} -#endif - -/** - * \brief Check the status of Peripherals Power Domain. - * - * \return 0, if it is powered down and 1 if it is powered up. - * - */ -__STATIC_INLINE uint32_t hw_cpm_check_per_pd_status(void) -{ - return REG_GETF(CRG_TOP, SYS_STAT_REG, PER_IS_UP); -} - -/** - * \brief Check the status of Radio Power Domain. - * - * \return 0, if it is powered down and 1 if it is powered up. - * - */ -__STATIC_INLINE uint32_t hw_cpm_check_rad_pd_status(void) -{ - return REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_UP); -} - -/** - * \brief Activate Pad latches. - * - */ -__STATIC_INLINE void hw_cpm_activate_pad_latches(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_activate_pad_latches(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, PAD_LATCH_EN); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Deactivate Pad latches. - * - */ -__STATIC_INLINE void hw_cpm_deactivate_pad_latches(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_deactivate_pad_latches(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, PAD_LATCH_EN); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Check if the RC16M is enabled. - * - * \return 0 if the RC16M is disabled, else 1. - * - */ -__STATIC_INLINE uint32_t hw_cpm_check_rc16_status(void) -{ - return REG_GETF(CRG_TOP, CLK_16M_REG, RC16M_ENABLE); -} - -/** - * \brief Activate the RC16M. - * - */ -__STATIC_INLINE void hw_cpm_enable_rc16(void) -{ - REG_SET_BIT(CRG_TOP, CLK_16M_REG, RC16M_ENABLE); -} - -/** - * \brief Deactivate the RC16M. - * - */ -__STATIC_INLINE void hw_cpm_disable_rc16(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_disable_rc16(void) -{ - REG_CLR_BIT(CRG_TOP, CLK_16M_REG, RC16M_ENABLE); -} - -/** - * \brief Set the XTAL16M settling time. - * - */ -__STATIC_INLINE void hw_cpm_set_xtal16m_settling_time(uint8_t cycles) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_set_xtal16m_settling_time(uint8_t cycles) -{ - CRG_TOP->XTALRDY_CTRL_REG = cycles; -} - -/** - * \brief Check if the XTAL16M has started ticking - * - */ -__STATIC_INLINE bool hw_cpm_is_xtal16m_started(void) __attribute__((always_inline)); - -__STATIC_INLINE bool hw_cpm_is_xtal16m_started(void) -{ - return (REG_GETF(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY) == 1); -} - -/** - * \brief Check if the XTAL16M is enabled. - * - * \return 0 if the XTAL16M is disabled, not 0 else. - * - */ -__STATIC_INLINE uint32_t hw_cpm_check_xtal16m_status(void) -{ - uint32_t ret; - - ret = REG_GETF(CRG_TOP, CLK_CTRL_REG, XTAL16M_DISABLE); - - return !ret; -} - -/** - * \brief Activate the XTAL16M. - * - */ -__STATIC_INLINE void hw_cpm_enable_xtal16m(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, CLK_CTRL_REG, XTAL16M_DISABLE); - GLOBAL_INT_RESTORE(); - -} - -/** - * \brief Deactivate the XTAL16M. - * - */ -__STATIC_INLINE void hw_cpm_disable_xtal16m(void) -{ - REG_SET_BIT(CRG_TOP, CLK_CTRL_REG, XTAL16M_DISABLE); -} - -/** - * \brief Enable the high-pass filter of the XTAL16M. - * - */ -__STATIC_INLINE void hw_cpm_enable_xtal16m_hpf(void) -{ - REG_SET_BIT(CRG_TOP, CLK_16M_REG, XTAL16_HPASS_FLT_EN); // Last review date: Feb 15, 2016 - 12:25:47 -} - -/** - * \brief Set a flag before sleeping that will check after the code execution is resumed after the - * WFI() to determine whether the system actually entered into sleep or not. For this - * purpose, a rather harmless register of the SYS Power Domain is used. - * - */ -__STATIC_INLINE void hw_cpm_set_sleep_flag(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_set_sleep_flag(void) -{ - GPIO->GPIO_CLK_SEL = 1; -} - -/** - * \brief Prepare RESET type tracking. - */ -__STATIC_INLINE void hw_cpm_track_reset_type(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_track_reset_type(void) -{ -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) - CRG_TOP->RESET_STAT_REG = 0; -#endif -} - -/** - * \brief Check if the system entered sleep. - * - * \return True, if the system slept, else false. - * - */ -__STATIC_INLINE bool hw_cpm_check_sleep_flag(void) -{ - return (GPIO->GPIO_CLK_SEL == 0); -} - -/** - * \brief Check if the XTAL16M has settled. - * - * \return 1 if the XTAL16M has settled, else 0. - * - */ -__STATIC_INLINE uint32_t hw_cpm_is_xtal16m_trimmed(void) -{ - return REG_GETF(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY); -} - -/** - * \brief Check if the PLL is on and has locked. - * - * \return 1 if the PLL has locked, else 0. - * - */ -__STATIC_INLINE uint32_t hw_cpm_is_pll_locked(void) -{ - return REG_GETF(GPREG, PLL_SYS_STATUS_REG, PLL_LOCK_FINE); -} - -/** - * \brief Enable the PLL divider. The output frequency is set to 48MHz. - * - */ -__STATIC_INLINE void hw_cpm_enable_pll_divider(void) -{ - REG_SET_BIT(CRG_TOP, CLK_CTRL_REG, PLL_DIV2); -} - -/** - * \brief Disable the PLL divider. The output frequency is set to 96MHz. - * - */ -__STATIC_INLINE void hw_cpm_disable_pll_divider(void) -{ - REG_CLR_BIT(CRG_TOP, CLK_CTRL_REG, PLL_DIV2); -} - -/** - * \brief Get the status of the PLL divider. - * - * \return 0 if the divider is disabled, 1 if the divider is enabled. - * - */ -__STATIC_INLINE uint32_t hw_cpm_get_pll_divider_status(void) -{ - return REG_GETF(CRG_TOP, CLK_CTRL_REG, PLL_DIV2); -} - -/** - * \brief Return the clock used as the system clock. - * - * \retval SYS_CLK_IS_XTAL16M Crystal oscillator - * \retval SYS_CLK_IS_RC16 RC oscillator - * \retval SYS_CLK_IS_LP Low Power clock - * \retval SYS_CLK_IS_PLL PLL - * - */ -__STATIC_INLINE uint32_t hw_cpm_get_sysclk(void) -{ - return REG_GETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL); -} - -/** - * \brief Return the divider of the AMBA High Speed Bus. - * - * \retval 0 Divide by 1 - * \retval 1 Divide by 2 - * \retval 2 Divide by 4 - * \retval 3 Divide by 8 - * \retval 3 Divide by 16 - * - */ -__STATIC_INLINE uint32_t hw_cpm_get_hclk_div(void) __attribute__((always_inline)); - -__STATIC_INLINE uint32_t hw_cpm_get_hclk_div(void) -{ - return REG_GETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV); -} - -/** - * \brief Set the divider of the AMBA High Speed Bus. - * - */ -__STATIC_INLINE void hw_cpm_set_hclk_div(uint32_t div) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_set_hclk_div(uint32_t div) -{ - GLOBAL_INT_DISABLE(); - REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, div); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Return the divider of the AMBA Peripheral Bus. - * - * \retval 0 Divide by 1 - * \retval 1 Divide by 2 - * \retval 2 Divide by 4 - * \retval 3 Divide by 8 - * - */ -__STATIC_INLINE uint32_t hw_cpm_get_pclk_div(void) -{ - return REG_GETF(CRG_TOP, CLK_AMBA_REG, PCLK_DIV); -} - -/** - * \brief Set the divider of the AMBA Peripheral Bus. - * - */ -__STATIC_INLINE void hw_cpm_set_pclk_div(uint32_t div) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_set_pclk_div(uint32_t div) -{ - GLOBAL_INT_DISABLE(); - REG_SETF(CRG_TOP, CLK_AMBA_REG, PCLK_DIV, div); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Check whether any of the Timer0 and 2 is active and uses the system clock. - * - * \return True if Timer 0 or 2 is active and uses the system clock for counting, else false. - * - */ -__STATIC_INLINE bool hw_cpm_timer02_uses_sysclk(void) -{ - uint32_t regval; - bool ret = true; - - do { - regval = CRG_TOP->CLK_TMR_REG; - - // Check Timer0 clock - if ((regval & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_ENABLE)) && - (regval & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_CLK_SEL))) { - break; - } - - // Check Timer2 clock - if ((regval & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_ENABLE)) && - (regval & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_CLK_SEL))) { - break; - } - - ret = false; - } while (0); - - return ret; -} - -/** - * \brief Check whether a MAC is active. - * - * \return True if MAC is active, else false. - * - */ -__STATIC_INLINE bool hw_cpm_mac_is_active(void) -{ -#ifdef CONFIG_USE_FTDF - if (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP)) { - return true; - } -#endif - -#ifdef CONFIG_USE_BLE - if (REG_GETF(CRG_TOP, SYS_STAT_REG, BLE_IS_UP)) { - return true; - } -#endif - - return false; -} - -/** - * \brief Check whether the RC32K is the Low Power clock. - * - * \return True if RC32K is the LP clock, else false. - * - */ -__STATIC_INLINE bool hw_cpm_lp_is_rc32k(void) -{ - return REG_GETF(CRG_TOP, CLK_32K_REG, RC32K_ENABLE) && - (REG_GETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE) == LP_CLK_IS_RC32K); -} - -/** - * \brief Set RCX as the Low Power clock. - * - * \warning The RCX must have been enabled before calling this function! - */ -__STATIC_INLINE void hw_cpm_lp_set_rcx(void) -{ - ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_RCX20K_REG, RCX20K_ENABLE) == 1); - - REG_SETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE, LP_CLK_IS_RCX); -} - -/** - * \brief Set XTAL32K as the Low Power clock. - * - * \warning The XTAL32K must have been enabled before calling this function! - * Interrupts must have been disabled before calling this function! - */ -__STATIC_INLINE void hw_cpm_lp_set_xtal32k(void) -{ - ASSERT_WARNING(__get_PRIMASK() == 1); - ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_32K_REG, XTAL32K_ENABLE) == 1); - - REG_SETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE, LP_CLK_IS_XTAL32K); -} - -/** - * \brief Configure pin to connect an external digital clock. - * - */ -void hw_cpm_configure_ext32k_pins(void); - -/** - * \brief Set an external digital clock as the Low Power clock. - * - * \warning Interrupts must have been disabled before calling this function! - */ -__STATIC_INLINE void hw_cpm_lp_set_ext32k(void) -{ - ASSERT_WARNING(__get_PRIMASK() == 1); - - REG_SETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE, LP_CLK_IS_EXTERNAL); -} - -/** - * \brief Enable RC32K. - * - */ -__STATIC_INLINE void hw_cpm_enable_rc32k(void) -{ - REG_SET_BIT(CRG_TOP, CLK_32K_REG, RC32K_ENABLE); -} - -/** - * \brief Disable RC32K. - * - * \warning RC32K must not be the LP clock. - * - */ -__STATIC_INLINE void hw_cpm_disable_rc32k(void) -{ - ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE) != LP_CLK_IS_RC32K); - - REG_CLR_BIT(CRG_TOP, CLK_32K_REG, RC32K_ENABLE); -} - -/** - * \brief Set RC32K as the Low Power clock. - * - * \warning The RC32K must have been enabled before calling this function! - */ -__STATIC_INLINE void hw_cpm_lp_set_rc32k(void) -{ - ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_32K_REG, RC32K_ENABLE) == 1); - - REG_SETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE, LP_CLK_IS_RC32K); -} - -/** - * \brief Configure RCX. This must be done only once since the register is retained. - * - */ -__STATIC_INLINE void hw_cpm_configure_rcx(void) -{ - uint32_t reg; - - reg = CRG_TOP->CLK_RCX20K_REG; - - REG_SET_FIELD(CRG_TOP, CLK_RCX20K_REG, RCX20K_NTC, reg, 0xC); // 0x4C2 - REG_SET_FIELD(CRG_TOP, CLK_RCX20K_REG, RCX20K_BIAS, reg, 0); // Last review date: Feb 15, 2016 - 12:25:47 - REG_SET_FIELD(CRG_TOP, CLK_RCX20K_REG, RCX20K_TRIM, reg, 2); - REG_SET_FIELD(CRG_TOP, CLK_RCX20K_REG, RCX20K_LOWF, reg, 1); - - CRG_TOP->CLK_RCX20K_REG = reg; -} - -/** - * \brief Enable RCX but does not set it as the LP clock. - * - */ -__STATIC_INLINE void hw_cpm_enable_rcx(void) -{ - REG_SET_BIT(CRG_TOP, CLK_RCX20K_REG, RCX20K_ENABLE); -} - -/** - * \brief Disable RCX. - * - * \warning RCX must not be the LP clock - * - */ -__STATIC_INLINE void hw_cpm_disable_rcx(void) -{ - ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE) != LP_CLK_IS_RCX); - - REG_CLR_BIT(CRG_TOP, CLK_RCX20K_REG, RCX20K_ENABLE); -} - -/** - * \brief Configure XTAL32KX pins. - * - */ -void hw_cpm_configure_xtal32k_pins(void); - -/** - * \brief Configure XTAL32KX. This must be done only once since the register is retained. - * - */ -__STATIC_INLINE void hw_cpm_configure_xtal32k(void) -{ - uint32_t reg; - - // Configure xtal. - reg = CRG_TOP->CLK_32K_REG; - REG_SET_FIELD(CRG_TOP, CLK_32K_REG, XTAL32K_CUR, reg, 5); // Last review date: Feb 15, 2016 - 12:25:47 - REG_SET_FIELD(CRG_TOP, CLK_32K_REG, XTAL32K_RBIAS, reg, 3); // Last review date: Feb 15, 2016 - 12:25:47 - - if (dg_configEXT_LP_IS_DIGITAL) { - REG_SET_FIELD(CRG_TOP, CLK_32K_REG, XTAL32K_DISABLE_AMPREG, reg, 1); - } - else { - REG_SET_FIELD(CRG_TOP, CLK_32K_REG, XTAL32K_DISABLE_AMPREG, reg, 0); - } - - CRG_TOP->CLK_32K_REG = reg; -} - -/** - * \brief Enable XTAL32K but does not set it as the LP clock. - * - */ -__STATIC_INLINE void hw_cpm_enable_xtal32k(void) -{ - REG_SET_BIT(CRG_TOP, CLK_32K_REG, XTAL32K_ENABLE); -} - -/** - * \brief Disable XTAL32K. - * - * \warning XTAL32K must not be the LP clock. - * - */ -__STATIC_INLINE void hw_cpm_disable_xtal32k(void) -{ - ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE) != LP_CLK_IS_XTAL32K); - - REG_CLR_BIT(CRG_TOP, CLK_32K_REG, XTAL32K_ENABLE); -} - -/** - * \brief Check the status of a requested calibration. - * - * \return true if the calibration has finished (or never run) else false. - * - */ -__STATIC_INLINE bool hw_cpm_calibration_finished(void) -{ - return REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 0; -} - -/** - * \brief Start calibration of a clock. - * - * \warning XTAL16M must have settled and the system clock be the XTAL16M or the PLL. - * - */ -void hw_cpm_start_calibration(cal_clk_t clk_type, uint32_t cycles); - -/** - * \brief Return the calibration results. - * - * \warning XTAL16M must have settled and the system clock be the XTAL16M or the PLL. - * - */ -uint32_t hw_cpm_get_calibration_data(void); - -/** - * \brief Check if the RC16M is the System Clock. - * - * \return 1 if the RC16M is the System Clock else 0. - * - */ -uint32_t hw_cpm_sysclk_is_rc16(void); - -/** - * \brief Check if the XTAL16M is the System Clock. - * - * \return 1 if the XTAL16M is the System Clock else 0. - * - */ -uint32_t hw_cpm_sysclk_is_xtal16m(void); - -/** - * \brief Setup system for a 32MHz / 16MHz external crystal. - * - * \param[in] freq true if 32MHz crystal is connected, false if 16MHz crystal is used - * - * \return void - * - */ -void hw_cpm_set_divn(bool freq); - -/** - * \brief Check if the system clock can be switched to the RC16. - * - * \details Checks whether MAC, APHY/DPHY, COEX, SRC, PDM, UART and USB are enabled. If any of - * these blocks is enabled then the switching is not allowed. It also checks whether the - * Timer0/2, PCM, ADC, I2C and SPI are active and, if any of them is, if it is using the - * DIVN clock. In this case the switching is not allowed. - * - * \return true if it is allowed to switch to RC16 else false. - * - */ -bool hw_cpm_is_rc16_allowed(void); - -/** - * \brief Set System clock. - * - * \param[in] mode The new system clock. - * - */ -void hw_cpm_set_sysclk(uint32_t mode); - -/** - * \brief Add a short delay loop. - * - */ -void hw_cpm_short_delay(void); - -/** - * \brief Enable the PLL. - * - */ -void hw_cpm_pll_sys_on(void); - -/** - * \brief Disable the PLL. - * - * \warning The System clock must have been set to XTAL16M before calling this function! - * - */ -void hw_cpm_pll_sys_off(void); - -/** - * \brief Enable the 3V3 clamp. - * - */ -__STATIC_INLINE void hw_cpm_3v3_clamp_on(void) -{ - REG_SET_BIT(CRG_TOP, AON_SPARE_REG, EN_BATSYS_RET); -} - -/** - * \brief Disable the 3V3 clamp. - * - */ -__STATIC_INLINE void hw_cpm_3v3_clamp_off(void) -{ - REG_CLR_BIT(CRG_TOP, AON_SPARE_REG, EN_BATSYS_RET); -} - -/** - * \brief Enable OSC16M amplitude regulation - */ -__STATIC_INLINE void hw_cpm_enable_osc16m_amp_reg(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_enable_osc16m_amp_reg(void) -{ - REG_CLR_BIT(CRG_TOP, AON_SPARE_REG, OSC16_HOLD_AMP_REG); -} - -/** - * \brief Disable OSC16M amplitude regulation - */ -__STATIC_INLINE void hw_cpm_disable_osc16m_amp_reg(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_disable_osc16m_amp_reg(void) -{ - REG_SET_BIT(CRG_TOP, AON_SPARE_REG, OSC16_HOLD_AMP_REG); -} - -/** - * \brief Sets the state of the 1v8 rail. - * - * \param[in] state true, the 1v8 rail is controlled via dg_config macros - * false, the 1v8 rail is off - * - */ -void hw_cpm_set_1v8_state(bool state); - -/** - * \brief Returns the state of the 1v8 rail. - * - * \return false if the 1v8 rail is off, true if it is controlled via dg_config macros - * - */ -__RETAINED_CODE bool hw_cpm_get_1v8_state(void); - -/** - * \brief Enable the LDO_VBAT_RET. - * - */ -__STATIC_INLINE void hw_cpm_ldo_vbat_ret_on(void) -{ - REG_CLR_BIT(CRG_TOP, LDO_CTRL2_REG, LDO_VBAT_RET_DISABLE); -} - -/** - * \brief Disable the LDO_VBAT_RET. - * - */ -__STATIC_INLINE void hw_cpm_ldo_vbat_ret_off(void) -{ - REG_SET_BIT(CRG_TOP, LDO_CTRL2_REG, LDO_VBAT_RET_DISABLE); -} - -/** - * \brief Disable the LDO_IO_RET and the LDO_IO2_RET. - * - */ -__STATIC_INLINE void hw_cpm_ldo_io_ret_off(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_ldo_io_ret_off(void) -{ - uint32_t reg = CRG_TOP->LDO_CTRL2_REG; - - if (dg_configPOWER_1V8_SLEEP == 1) { - if (dg_configUSE_BOD == 1) { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); - } - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, reg, 1); - } - - if (dg_configPOWER_1V8P == 1) { - if (dg_configUSE_BOD == 1) { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); - } - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_RET_DISABLE, reg, 1); - } - - CRG_TOP->LDO_CTRL2_REG = reg; -} - -/* - * \brief Set the LDO_RADIO_SETVDD to the proper level (0x2 = 1.40V) - */ -__STATIC_INLINE void hw_cpm_reset_radio_vdd(void) -{ - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_SETVDD, 0x2); -} - -/** - * \brief Enable the LDOs. - * - */ -__STATIC_INLINE void hw_cpm_start_ldos(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_start_ldos(void) -{ - uint32_t reg = CRG_TOP->LDO_CTRL2_REG; - if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) && - (dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_A)) { - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_VBAT_RET_LEVEL, 0); - } - REG_SET_BIT(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_ENABLE); - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V2_ON, reg, 1); - - if ((dg_configPOWER_1V8_ACTIVE == 1) && hw_cpm_get_1v8_state()) { - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, reg, 1); - if (dg_configPOWER_1V8_SLEEP == 0) { - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, reg, 1); - } - else { - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, reg); - } - } - else { - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, reg); - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, reg, 1); - } - - if (dg_configPOWER_1V8P == 1) { - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_ON, reg, 1); - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_RET_DISABLE, reg); - } - else { - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_ON, reg); - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_RET_DISABLE, reg, 1); - } - - CRG_TOP->LDO_CTRL2_REG = reg; -} - -/** - * \brief Configure the DCDC. - * - */ -void hw_cpm_dcdc_config(void); - -/** - * \brief Enable the DCDC. - * - */ -void hw_cpm_dcdc_on(void); - -/** - * \brief Prepare the DCDC for sleep. - * - */ -__STATIC_INLINE void hw_cpm_dcdc_sleep(void) __attribute__((always_inline)); - -void hw_cpm_dcdc_sleep(void) -{ - // Deactivate DCDC 1V4 output rail - DCDC->DCDC_V14_1_REG &= ~(REG_MSK(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_HV) | - REG_MSK(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_LV)); - - // Set DCDC to sleep mode - REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 2); - - // Disable Retention LDOs for 1V8 and 1V8P - CRG_TOP->LDO_CTRL2_REG |= ((1 << REG_POS(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_RET_DISABLE)) | - (1 << REG_POS(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE))); - - // Enable LDO_CORE before going to sleep - hw_cpm_turn_1_2V_on(); -} - -/** - * \brief Disable the DCDC. - * - */ -__STATIC_INLINE void hw_cpm_dcdc_off(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_dcdc_off(void) -{ - // Enable the LDOs - hw_cpm_start_ldos(); - - // Turn off DCDC - DCDC->DCDC_CTRL_0_REG &= ~REG_MSK(DCDC, DCDC_CTRL_0_REG, DCDC_MODE); -} - -/** - * \brief Check if DCDC is active. - * - * \return True, if the DCDC is active else false. - * - */ -__STATIC_INLINE bool hw_cpm_dcdc_is_active(void) __attribute__((always_inline)); - -__STATIC_INLINE bool hw_cpm_dcdc_is_active(void) -{ - return (REG_GETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE) == 1); -} - -/** - * \brief Disable the DCDC and switch to LDOs without turning off the LDO_RADIO. - * - */ -__STATIC_INLINE void hw_cpm_switch_to_ldos(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_switch_to_ldos(void) -{ - // Enable the LDOs - hw_cpm_start_ldos(); - - // Turn off DCDC - DCDC->DCDC_CTRL_0_REG &= ~REG_MSK(DCDC, DCDC_CTRL_0_REG, DCDC_MODE); -} - - -/** - * \brief Set the configured time for the re-charging of the retention LDOs and the DCDC rails. - * - */ -__STATIC_INLINE void hw_cpm_set_recharge_period(uint16_t period) -{ - CRG_TOP->SLEEP_TIMER_REG = period; -} - -/** - * \brief Reset the time for the re-charging of the retention LDOs and the DCDC rails to zero. - * - */ -__STATIC_INLINE void hw_cpm_reset_recharge_period(void) -{ - // Set the DCDC charge period - CRG_TOP->SLEEP_TIMER_REG = 0; -} - -/** - * \brief Set (part of) the preferred settings. - * - */ -void hw_cpm_set_preferred_values(void); - -/** - * \brief Set the GPIO used for the SW cursor to High-Z. - * - */ -__STATIC_INLINE void hw_cpm_setup_sw_cursor(void) -{ - if (dg_configUSE_SW_CURSOR == 1) { - SW_CURSOR_GPIO = 0x000; - } -} - -/** - * \brief Triggers the GPIO used for the SW cursor. - * - */ -void hw_cpm_trigger_sw_cursor(void); - -/** - * \brief Stop the clock to the RF unit. - * - */ -__STATIC_INLINE void hw_cpm_rfcu_clk_off(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_rfcu_clk_off(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, CLK_RADIO_REG, RFCU_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Enable the debugger. - * - */ -__STATIC_INLINE void hw_cpm_enable_debugger(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_enable_debugger(void) -{ - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Disable the debugger. - * - */ -__STATIC_INLINE void hw_cpm_disable_debugger(void) __attribute__((always_inline)); - -__STATIC_INLINE void hw_cpm_disable_debugger(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Check if the debugger is attached. - * - * \return true, if the debugger is attached, else false. - * - */ -__STATIC_INLINE bool hw_cpm_is_debugger_attached(void) __attribute__((always_inline)); - -__STATIC_INLINE bool hw_cpm_is_debugger_attached(void) -{ - return (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE) != 0); -} - - -/** - * \brief Check if any DMA channel is active. - * - * \return true if a channel is active, false if all channels are inactive. - * - */ -__STATIC_INLINE bool hw_cpm_check_dma(void) -{ - bool ret = false; - - if (((DMA->DMA0_CTRL_REG & REG_MSK(DMA, DMA0_CTRL_REG, DMA_ON)) == 1) || - ((DMA->DMA1_CTRL_REG & REG_MSK(DMA, DMA1_CTRL_REG, DMA_ON)) == 1) || - ((DMA->DMA2_CTRL_REG & REG_MSK(DMA, DMA2_CTRL_REG, DMA_ON)) == 1) || - ((DMA->DMA3_CTRL_REG & REG_MSK(DMA, DMA3_CTRL_REG, DMA_ON)) == 1) || - ((DMA->DMA4_CTRL_REG & REG_MSK(DMA, DMA4_CTRL_REG, DMA_ON)) == 1) || - ((DMA->DMA5_CTRL_REG & REG_MSK(DMA, DMA5_CTRL_REG, DMA_ON)) == 1) || - ((DMA->DMA6_CTRL_REG & REG_MSK(DMA, DMA6_CTRL_REG, DMA_ON)) == 1) || - ((DMA->DMA7_CTRL_REG & REG_MSK(DMA, DMA7_CTRL_REG, DMA_ON))== 1) ){ - ret = true; - } - - return ret; -} - -/** - * \brief Issue a HW reset (due to a fault condition). - * - * \details A HW reset (WDOG) will be generated. The NMI Handler will be called and "status" will be - * stored in the Retention RAM. - * - */ -__RETAINED_CODE void hw_cpm_reset_system(void); - -/** - * \brief Issue a HW reset (intentionally, i.e. after a SW upgrade). - * - * \details A HW reset (WDOG) will be generated. The NMI Handler is bypassed. Thus, no "status" is - * stored in the Retention RAM. - * - */ -__RETAINED_CODE void hw_cpm_reboot_system(void); - -/** - * \brief Add delay of N usecs. - * - * \param[in] usec The number of usecs to wait for. - * - * \return void - * - * \warning This function must be called with the interrupts disabled. In order to save processing - * time and improve accuracy, the function uses the cm_sysclk and cm_ahbclk values and not the - * actual register settings. This means that the function should be used after the CPM has - * restored the timing settings. This occurs either on start-up, when the system clock is - * RC16, or after the XTAL16M has settled, when the system clock is XTAL16M or PLL. - * Therefore, it is important that the platform (either the CPM or some other entity) has - * configured values sys_clk_t cm_sysclk and ahb_div_t cm_ahbclk - * - */ -__RETAINED_CODE void hw_cpm_delay_usec(uint32_t usec); - -/** - * \brief Trigger a GPIO when ASSERT_WARNING() or ASSERT_ERROR() hits. - * - */ -__RETAINED_CODE void hw_cpm_assert_trigger_gpio(void); - -#endif /* dg_configUSE_HW_CPM */ - -#endif /* CPM_H_ */ - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h deleted file mode 100644 index ef05b5991..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup CRYPTO - * \{ - * \brief Interrupt handling for the crypto engines (AES/HASH, ECC) - */ - -/** - **************************************************************************************** - * - * @file hw_crypto.h - * - * @brief Interrupt handling API for the AES/Hash and ECC Engines. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC) - -#include "sdk_defs.h" - -/** - * \brief Crypto engines callback - * - * This function type is used for callbacks called when the crypto engines (AES/HASH, ECC) - * generate an interrupt. - * - * \param [in] status The status register (either AES/HASH or ECC) at the time of the interrupt. - * - */ -typedef void (*hw_crypto_cb)(unsigned int status); - -/** - * \brief Enable interrupt for AES/HASH crypto engine. - * - * \param [in] cb A callback to be called when interrupt occurs. It must always be provided. - * - * \note AES/HASH engine and ECC engine are common sources of CRYPTO system interrupt. This - * function only enables CRYPTO interrupt itself and registers a callback for AES/HASH - * related CRYPTO interrupts. In order to fully enable AES/HASH interrupts - * hw_aes_hash_enable_interrupt_source() must also be called - */ -void hw_crypto_enable_aes_hash_interrupt(hw_crypto_cb cb); - -/** - * \brief Enable interrupt for ECC crypto engine. - * - * \param [in] cb A callback to be called when interrupt occurs. It must always be provided. - */ -void hw_crypto_enable_ecc_interrupt(hw_crypto_cb cb); - -/** - * \brief Disable interrupt for AES/HASH crypto engine. - */ -void hw_crypto_disable_aes_hash_interrupt(void); - -/** - * \brief Disable interrupt for ECC crypto engine. - */ -void hw_crypto_disable_ecc_interrupt(void); - -/** - * \brief Clear pending interrupt from AES/HASH and ECC crypto engines. - * - * \note This function clears the pending CRYPTO interrupt only on the NVI Controller. - * Use hw_aes_hash_clear_interrupt_req() and hw_ecc_clear_interrupt_source() to clear the - * source of CRYPTO interrupt on the AES/HASH and ECC engines respectively. - */ -static inline void hw_crypto_clear_pending_interrupt(void) -{ - NVIC_ClearPendingIRQ(CRYPTO_IRQn); -} - -#endif /* (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC) */ -/** - * \} - * \} - * \} - */ - diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_dma.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_dma.h deleted file mode 100644 index 01fc6344c..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_dma.h +++ /dev/null @@ -1,382 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup DMA - * \{ - * \brief DMA Controller - */ - -/** - **************************************************************************************** - * - * @file hw_dma.h - * - * @brief Definition of API for the DMA Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef HW_DMA_H_ -#define HW_DMA_H_ - -#if dg_configUSE_HW_DMA - -#include -#include - -/* -* ENUMERATION DEFINITIONS -***************************************************************************************** -*/ - -/** - * \brief DMA channel number - * - */ -typedef enum { - HW_DMA_CHANNEL_0 = 0, /**< Channel number 0 */ - HW_DMA_CHANNEL_1 = 1, /**< Channel number 1 */ - HW_DMA_CHANNEL_2 = 2, /**< Channel number 2 */ - HW_DMA_CHANNEL_3 = 3, /**< Channel number 3 */ - HW_DMA_CHANNEL_4 = 4, /**< Channel number 4 */ - HW_DMA_CHANNEL_5 = 5, /**< Channel number 5 */ - HW_DMA_CHANNEL_6 = 6, /**< Channel number 6 */ - HW_DMA_CHANNEL_7 = 7, /**< Channel number 7 */ - HW_DMA_CHANNEL_INVALID = 8 /**< Invalid Channel number */ -} HW_DMA_CHANNEL; - -/** - * \brief DMA channel enable/disable - * - */ -typedef enum { - HW_DMA_STATE_DISABLED = 0x0, /**< DMA disabled */ - HW_DMA_STATE_ENABLED = 0x1 /**< DMA enabled */ -} HW_DMA_STATE; - -/** - * \brief DMA channel bus width transfer - * - */ -typedef enum { - HW_DMA_BW_BYTE = 0x0, /**< Byte */ - HW_DMA_BW_HALFWORD = 0x2, /**< Halfword */ - HW_DMA_BW_WORD = 0x4 /**< Word */ -} HW_DMA_BW; - -/** - * \brief DMA channel interrupt enable/disable - * - */ -typedef enum { - HW_DMA_IRQ_STATE_DISABLED = 0x0, /**< Disable interrupt on this channel */ - HW_DMA_IRQ_STATE_ENABLED = 0x8 /**< Enable interrupt on this channel */ -} HW_DMA_IRQ_STATE; - -/** - * \brief DMA request input multiplexer controlled - * - */ -typedef enum { - HW_DMA_DREQ_START = 0x0, /**< DMA channel starts immediately */ - HW_DMA_DREQ_TRIGGERED = 0x10 /**< DMA channel must be triggered by peripheral DMA request */ -} HW_DMA_DREQ; - -/** - * \brief Increment destination address mode - * - */ -typedef enum { - HW_DMA_BINC_FALSE = 0x0, /**< Do not increment */ - HW_DMA_BINC_TRUE = 0x20 /**< Increment according value of BW */ -} HW_DMA_BINC; - -/** - * \brief Increment of source address mode - * - */ -typedef enum { - HW_DMA_AINC_FALSE = 0x0, /**< Do not increment */ - HW_DMA_AINC_TRUE = 0x40 /**< Increment according value of BW */ -} HW_DMA_AINC; - -/** - * \brief Channel mode - * - * In normal mode the DMA transfer stops the transfer after - * length DMAx_LEN_REG. - * In circular mode the DMA channel repeats the transfer - * after length DMAx_LEN_REG with the initial register values - * DMAx_A_START_REG, DMAx_B_START_REG, DMAx_LEN_REG, DMAx_INT_REG. - * - * \note only works if DREQ_MODE = 1 - * - */ -typedef enum { - HW_DMA_MODE_NORMAL = 0x0, /**< Normal mode */ - HW_DMA_MODE_CIRCULAR = 0x80 /**< Circular mode */ -} HW_DMA_MODE; - -/** - * \brief Channel priority - * - * Set priority level of DMA channel to determine which DMA - * channel will be activated in case more than one DMA channel - * requests DMA. - * - */ -typedef enum { - HW_DMA_PRIO_0 = 0x000, /**< Lowest priority */ - HW_DMA_PRIO_1 = 0x100, /**< .. */ - HW_DMA_PRIO_2 = 0x200, /**< .. */ - HW_DMA_PRIO_3 = 0x300, /**< .. */ - HW_DMA_PRIO_4 = 0x400, /**< .. */ - HW_DMA_PRIO_5 = 0x500, /**< .. */ - HW_DMA_PRIO_6 = 0x600, /**< .. */ - HW_DMA_PRIO_7 = 0x700 /**< Highest priority */ -} HW_DMA_PRIO; - -/** - * \brief DMA idle mode - * - * In blocking mode the DMA performs a fast back-to-back - * copy, disabling bus access for any bus master with lower priority. - * In interrupting mode the DMA inserts a wait cycle after each - * store allowing the CR16 to steal cycles or cache to perform a - * burst read. - * - * \note if DREQ_MODE = 1, DMA_IDLE does not have any effect - * - */ -typedef enum { - HW_DMA_IDLE_BLOCKING_MODE = 0x000, /**< Blocking mode */ - HW_DMA_IDLE_INTERRUPTING_MODE = 0x800 /**< Interrupting mode */ -} HW_DMA_IDLE; - -/** - * \brief DMA init mode - * - */ -typedef enum { - HW_DMA_INIT_AX_BX_AY_BY = 0x0000, /**< DMA performs copy A1 to B1, A2 to B2 */ - HW_DMA_INIT_AX_BX_BY = 0x1000 /**< DMA performs copy A1 to B1, B2 */ -} HW_DMA_INIT; - -/** - * \brief Channel request trigger - * - */ -typedef enum { - HW_DMA_TRIG_SPI_RXTX = 0x0, - HW_DMA_TRIG_SPI2_RXTX = 0x1, - HW_DMA_TRIG_UART_RXTX = 0x2, - HW_DMA_TRIG_UART2_RXTX = 0x3, - HW_DMA_TRIG_I2C_RXTX = 0x4, - HW_DMA_TRIG_I2C2_RXTX = 0x5, - HW_DMA_TRIG_USB_RXTX = 0x6, - HW_DMA_TRIG_I2S_LEFTRIGHT = 0x8, - HW_DMA_TRIG_PDM_LEFTRIGHT = 0x9, - HW_DMA_TRIG_FTDF_RXTX = 0xA, - HW_DMA_TRIG_ECC_RXTX = 0xB, - HW_DMA_TRIG_ADC = 0xC, - HW_DMA_TRIG_NONE = 0xF -} HW_DMA_TRIG; - -/** - * \brief DMA channel transfer callback - * - * This function is called by the DMA driver when the - * interrupt is fired. - * - * \param [in] user_data transfered data - * \param [in] len length of transfered data - * - */ -typedef void (*hw_dma_transfer_cb)(void *user_data, uint16_t len); - -/** - * \brief DMA parameters structure - * - */ -typedef struct { - HW_DMA_CHANNEL channel_number; /**< DMA Channel Number to be used */ - HW_DMA_BW bus_width; /**< Transfer Bus width: 8, 16 or 32 bits */ - HW_DMA_IRQ_STATE irq_enable; /**< Enable or disable IRQ generation */ - uint16 irq_nr_of_trans; /**< Number of transfers before IRQ generation - set to 0 to fire IRQ after transfer ends */ - HW_DMA_DREQ dreq_mode; /**< Start DMA immediately or triggered by peripheral */ - HW_DMA_AINC a_inc; /**< Increment of source address */ - HW_DMA_BINC b_inc; /**< Increment of destination address */ - HW_DMA_MODE circular; /**< Select normal or circular operation */ - HW_DMA_PRIO dma_prio; /**< Channel priority from 0 to 7 */ - HW_DMA_IDLE dma_idle; /**< Idle mode: blocking or interrupting */ - HW_DMA_INIT dma_init; /**< Copy mode: block copy or mem init */ - HW_DMA_TRIG dma_req_mux; /**< DMA trigger */ - uint32 src_address; /**< Source address */ - uint32 dest_address; /**< Destination address */ - uint16 length; /**< Number of DMA transfers */ - hw_dma_transfer_cb callback; /**< Function to call after irq_nr_of_trans transfers */ - void *user_data; /**< Data to pass to Callback */ -} DMA_setup; - -/* -* API FUNCTIONS DEFINITIONS -***************************************************************************************** -*/ - -/** - * \brief Initialize DMA Channel - * - * \param [in] channel_setup pointer to struct of type DMA_Setup - * - */ -void hw_dma_channel_initialization(DMA_setup *channel_setup); - -/** - * \brief Update DMA source address and length - * - * When DMA is configured for some peripheral, it could be enough to setup only source address - * and data length. Other parameters most likely do not change for same type of transmission - * for values that ware specified in \p hw_dma_channel_initialization(). - * This function should speed up DMA start time when only address and size changes from previous - * transmission. - * - * \param [in] channel DMA channel number to modify - * \param [in] addr new source address - * \param [in] length new data transfer length - * \param [in] cb function to call after transmission finishes - * - */ -void hw_dma_channel_update_source(HW_DMA_CHANNEL channel, void* addr, uint16_t length, - hw_dma_transfer_cb cb); - -/** - * \brief Update DMA destination address and length - * - * When DMA is configured for some peripheral, it could be enough to setup only destination address - * and data length. Other parameters most likely do not change for same type of transmission - * for values that ware specified in \p hw_dma_channel_initialization(). - * This function should speed up DMA start time when only address and size changes from previous - * transmission. - * - * \param [in] channel DMA channel number to modify - * \param [in] addr new source address - * \param [in] length new data transfer length - * \param [in] cb function to call after transmission finishes - * - */ -void hw_dma_channel_update_destination(HW_DMA_CHANNEL channel, void *addr, uint16_t length, - hw_dma_transfer_cb cb); - -/** - * \brief Update DMA interrupt trigger index - * - * DMA channel can trigger an interrupt after arbitrary transfer has finished. - * Usually interrupt is triggered after transmission finishes but for cyclic mode, - * where DMA never stops, it is convenient trigger interrupt at other times. - * This function allows to specify the number of transfers after which the interrupt is triggered. - * - * \param [in] channel DMA channel number to modify - * \param [in] int_ix Number of transfers until the interrupt is triggered - * - */ -void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix); - -/** - * \brief Enable or disable a DMA channel - * - * \param [in] channel_number DMA Channel Number to start/stop - * \param [in] dma_on enable/disable DMA channel - * - */ -void hw_dma_channel_enable(HW_DMA_CHANNEL channel_number, HW_DMA_STATE dma_on); - -/** - * \brief Stop DMA channel if operation is in progress - * - * If no transfer is in progress nothing happens. - * If there is outstanding DMA transfer it will be stopped and - * callback will be called with count of data already transfered - * - * \param [in] channel_number DMA channel number to stop - * - */ -void hw_dma_channel_stop(HW_DMA_CHANNEL channel_number); - -/** - * \brief Read number of transmitted bytes so far - * - * Use this function to see how many bytes were transfered - * via DMA channel so far. This number can changed very soon. - * - * \param [in] channel_number DMA channel number - * - * \return number of bytes already transfered (when transfer is in progress), - * 0 - if transfer is already finished, - * undefined if called or not started channel - * - */ -uint16_t hw_dma_transfered_bytes(HW_DMA_CHANNEL channel_number); - -/** - * \brief Freeze DMA - * - */ -static inline void hw_dma_freeze(void) -{ - GPREG->SET_FREEZE_REG = REG_MSK(GPREG, SET_FREEZE_REG, FRZ_DMA); -} - -/** - * \brief Unfreeze DMA - * - */ -static inline void hw_dma_unfreeze(void) -{ - GPREG->RESET_FREEZE_REG = REG_MSK(GPREG, RESET_FREEZE_REG, FRZ_DMA); -} - -/** - * \brief Check if any DMA channel is active. - * - * \return true, if a channel is active else false. - */ -bool hw_dma_channel_active(void); - -#endif /* dg_configUSE_HW_DMA */ - -#endif /* HW_DMA_H_ */ - -/** - * \} - * \} - * \} - */ - diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpadc.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpadc.h deleted file mode 100644 index fd918e33b..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpadc.h +++ /dev/null @@ -1,767 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup GPADC - * \{ - * \brief General Purpose ADC - */ - -/** - ***************************************************************************************** - * - * @file hw_gpadc.h - * - * @brief Definition of API for the GPADC Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_GPADC_H -#define HW_GPADC_H - -#if dg_configUSE_HW_GPADC - -#include -#include -#include - -extern int16_t hw_gpadc_differential_gain_error; -extern int16_t hw_gpadc_single_ended_gain_error; - -/** - * \brief ADC input mode - * - */ -typedef enum { - HW_GPADC_INPUT_MODE_DIFFERENTIAL = 0, /**< differential mode (default) */ - HW_GPADC_INPUT_MODE_SINGLE_ENDED = 1 /**< single ended mode */ -} HW_GPADC_INPUT_MODE; - -/** - * \brief ADC clock source - * - */ -typedef enum { - HW_GPADC_CLOCK_INTERNAL = 0, /**< internal high-speed clock (default) */ - HW_GPADC_CLOCK_DIGITAL = 1 /**< digital clock (16/96MHz) */ -} HW_GPADC_CLOCK; - -/** - * \brief ADC input - * - * \p GPADC_INPUT_SE_* values should be used only in single ended mode - * \p GPADC_INPUT_DIFF_* values should be used only in differential mode - * - */ -typedef enum { - HW_GPADC_INPUT_SE_P12 = 0, /**< GPIO 1.2 */ - HW_GPADC_INPUT_SE_P14 = 1, /**< GPIO 1.4 */ - HW_GPADC_INPUT_SE_P13 = 2, /**< GPIO 1.3 */ - HW_GPADC_INPUT_SE_P07 = 3, /**< GPIO 0.7 */ - HW_GPADC_INPUT_SE_AVS = 4, /**< analog ground level */ - HW_GPADC_INPUT_SE_VDD = 5, - HW_GPADC_INPUT_SE_VDCDC = 6, - HW_GPADC_INPUT_SE_V33 = 7, - HW_GPADC_INPUT_SE_VBAT = 9, /**< battery */ - HW_GPADC_INPUT_SE_TEMPSENS = 14, /**< temperature sensor */ - HW_GPADC_INPUT_SE_P06 = 16, /**< GPIO 0.6 */ - HW_GPADC_INPUT_SE_P10 = 17, /**< GPIO 1.0 */ - HW_GPADC_INPUT_SE_P15 = 18, /**< GPIO 1.5 */ - HW_GPADC_INPUT_SE_P24 = 19, /**< GPIO 2.4 */ - HW_GPADC_INPUT_DIFF_P12_P14 = 0, /**< GPIO 1.2 vs 1.4 */ - HW_GPADC_INPUT_DIFF_P13_P07 = 1, /**< GPIO 1.3 vs 0.7 */ -} HW_GPADC_INPUT; - -/** - * \brief ADC interrupt handler - * - */ -typedef void (*hw_gpadc_interrupt_cb)(void); - -/** - * \brief ADC configuration - * - */ -typedef struct { - HW_GPADC_CLOCK clock; /**< clock source */ - HW_GPADC_INPUT_MODE input_mode; /**< input mode */ - HW_GPADC_INPUT input; /**< ADC input */ - - uint8_t sample_time; /**< sample time */ - bool continous; /**< continous mode state */ - uint8_t interval; /**< interval between conversions in continous mode */ - - bool input_attenuator; /**< input attenuator state */ - bool chopping; /**< chopping state */ - uint8_t oversampling; /**< oversampling value */ -} gpadc_config; - -/** - * \brief Initialize ADC - * - * \p cfg can be NULL - no configuration is performed in such case. - * - * \param [in] cfg configuration - * - */ -void hw_gpadc_init(const gpadc_config *cfg); - -/** - * \brief Configure ADC - * - * Shortcut to call appropriate configuration function. If \p cfg is NULL, this function does - * nothing. - * - * \param [in] cfg configuration - * - */ -void hw_gpadc_configure(const gpadc_config *cfg); - -/** - * \brief Reset ADC to its default values without disabling the LDO. - * - */ -void hw_gpadc_reset(void); - -/** - * \brief Register interrupt handler - * - * Interrupt is enabled after calling this function. Application is responsible for clearing - * interrupt using hw_gpadc_clear_interrupt(). If no callback is specified interrupt is cleared by - * driver. - * - * \param [in] cb callback fired on interrupt - * - * \sa hw_gpadc_clear_interrupt - * - */ -void hw_gpadc_register_interrupt(hw_gpadc_interrupt_cb cb); - -/** - * \brief Unregister interrupt handler - * - * Interrupt is disabled after calling this function. - * - */ -void hw_gpadc_unregister_interrupt(void); - -/** - * \brief Clear interrupt - * - * Application should call this in interrupt handler to clear interrupt. - * - * \sa hw_gpadc_register_interrupt - * - */ -static inline void hw_gpadc_clear_interrupt(void) -{ - GPADC->GP_ADC_CLEAR_INT_REG = 1; -} - -/** - * \brief Enable ADC - * - * Sampling is started after calling this function, to start conversion application should call - * hw_gpadc_start(). - * - * \sa hw_gpadc_start - * - */ -static inline void hw_gpadc_enable(void) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_EN, 1); -} - -/** - * \brief Disable ADC - * - * Application should wait for conversion to be completed before disabling ADC. In case of - * continuous mode, application should disable continuous mode and then wait for conversion to be - * completed in order to have ADC in defined state. - * - * \sa hw_gpadc_in_progress - * \sa hw_gpadc_set_continuous - * - */ -static inline void hw_gpadc_disable(void) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_EN, 0); -} - -/** - * \brief Set the delay required to enable the ADC_LDO. - * - * param [in] LDO enable delay - * - */ -static inline void hw_gpadc_set_ldo_delay(uint32_t delay) -{ - REG_SETF(GPADC, GP_ADC_CTRL3_REG, GP_ADC_EN_DEL, delay); -} - -/** \brief Perform ADC calibration - * - * Calibration is performed. The input mode must be HW_GPADC_INPUT_SE_VDD (1.2V). - * LDO constant and dynamic currents may be on. The input mode must be Single Ended. The calibration - * is performed only once. - * - * \sa hw_gpadc_set_input_mode - * - */ -void hw_gpadc_calibrate(void); - -/** - * \brief Start conversion - * - * Application should not call this function while conversion is still in progress. - * - * \sa hw_gpadc_in_progress - * - */ -static inline void hw_gpadc_start(void) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_START, 1); -} - -/** - * \brief Check if conversion is in progress - * - * \return conversion state - * - */ -static inline bool hw_gpadc_in_progress(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_START); -} - -/** - * \brief Set continuous mode - * - * With continuous mode enabled ADC will automatically restart conversion once completed. It's still - * required to start 1st conversion using hw_gpadc_start(). Interval between subsequent conversions - * can be adjusted using hw_gpadc_set_interval(). - * - * \param [in] enabled continuous mode state - * - * \sa hw_gpadc_start - * \sa hw_gpadc_set_interval - * - */ -static inline void hw_gpadc_set_continuous(bool enabled) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CONT, !!enabled); -} - -/** - * \brief Get continuous mode state - * - * \return continuous mode state - * - */ -static inline bool hw_gpadc_get_continuous(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CONT); -} - -/** - * \brief Set input channel - * - * Application is responsible for using proper input symbols depending on whether single ended or - * differential mode is used. - * - * \param [in] input input channel - * - * \sa hw_gpadc_set_input_mode - * \sa GPADC_INPUT_MODE - * - */ -static inline void hw_gpadc_set_input(HW_GPADC_INPUT input) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SEL, input); -} - -/** - * \brief Get current input channel - * - * \return input channel - * - */ -static inline HW_GPADC_INPUT hw_gpadc_get_input(void) -{ - return (HW_GPADC_INPUT) REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SEL); -} - -/** - * \brief Set input mode - * - * \param [in] mode input mode - * - */ -static inline void hw_gpadc_set_input_mode(HW_GPADC_INPUT_MODE mode) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SE, mode); -} - -/** - * \brief Get current input mode - * - * return input mode - * - */ -static inline HW_GPADC_INPUT_MODE hw_gpadc_get_input_mode(void) -{ - return (HW_GPADC_INPUT_MODE) REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SE); -} - -/** - * \brief Set clock source - * - * \param [in] clock clock source - * - */ -static inline void hw_gpadc_set_clock(HW_GPADC_CLOCK clock) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CLK_SEL, clock); -} - -/** - * \brief Get current clock source - * - * \return clock source - * - */ -static inline HW_GPADC_CLOCK hw_gpadc_get_clock(void) -{ - return (HW_GPADC_CLOCK) REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CLK_SEL); -} - -/** - * \brief Set oversampling - * - * With oversampling enabled multiple successive conversions will be executed and results are added - * together to increase effective number of bits in result. - * - * Number of samples taken is 2\p n_samples. Valid values for \p n_samples are 0-7 thus - * at most 128 samples can be taken. In this case 17bits of result are generated with the least - * significant bit being discarded. - * - * \param [in] n_samples number of samples to be taken - * - * \sa hw_gpadc_get_raw_value - * - */ -static inline void hw_gpadc_set_oversampling(uint8_t n_samples) -{ - REG_SETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_CONV_NRS, n_samples); -} - -/** - * \brief Get current oversampling - * - * \return number of samples to be taken - * - * \sa hw_gpadc_set_oversampling - * - */ -static inline uint8_t hw_gpadc_get_oversampling(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_CONV_NRS); -} - -/** - * \brief Set sample time - * - * Sample time is \p mult x 32 clock cycles or 1 clock cycle when \p mult is 0. Valid values are - * 0-15. - * - * \param [in] mult multiplier - * - */ -static inline void hw_gpadc_set_sample_time(uint8_t mult) -{ - REG_SETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_SMPL_TIME, mult); -} - -/** - * \brief Get current sample time - * - * \return multiplier - * - * \sa hw_gpadc_set_sample_time - * - */ -static inline uint8_t hw_gpadc_get_sample_time(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_SMPL_TIME); -} - -/** - * \brief Set state of input attenuator - * - * Enabling internal attenuator scales input voltage by factor of 3 thus increasing effective input - * scale from 0-1.2V to 0-3.6V in single ended mode or from -1.2-1.2V to -3.6-3.6V in differential - * mode. - * - * \param [in] enabled attenuator state - * - */ -static inline void hw_gpadc_set_input_attenuator_state(bool enabled) -{ - REG_SETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_ATTN3X, !!enabled); -} - -/** - * \brief Get current state of input attenuator - * - * \return attenuator state - * - */ -static inline bool hw_gpadc_get_input_attenuator_state(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_ATTN3X); -} - -/** - * \brief Set input mute state - * - * Once enabled, samples are taken at mid-scale to determine internal offset and/or notice of the - * ADC with regards to VDD_REF. - * - * \param [in] enabled mute state - * - * \sa hw_gpadc_calibrate - * - */ -static inline void hw_gpadc_set_mute(bool enabled) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_MUTE, !!enabled); -} - -/** - * \brief Get current input mute state - * - * \return mute state - * - * \sa hw_gpadc_set_mute - * - */ -static inline bool hw_gpadc_get_mute(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_MUTE); -} - -/** - * \brief Set input and output sign change - * - * Once enabled, sign of ADC input and output is changed. - * - * \param [in] enabled sign change state - * - */ -static inline void hw_gpadc_set_sign_change(bool enabled) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SIGN, !!enabled); -} - -/** - * \brief Set input and output sign change - * - * \return sign change state - * - */ -static inline bool hw_gpadc_get_sign_change(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SIGN); -} - -/** - * \brief Set chopping state - * - * Once enabled, two samples with opposite polarity are taken to cancel offset. - * - * \param [in] enabled chopping state - * - */ -static inline void hw_gpadc_set_chopping(bool enabled) -{ - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CHOP, !!enabled); -} - -/** - * \brief Get current chopping state - * - * \return chopping state - * - */ -static inline bool hw_gpadc_get_chopping(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CHOP); -} - -/** - * \brief Set state of constant 20uA load current on ADC LDO output - * - * Constant 20uA load current on LDO output can be enabled so that the current will not drop to 0. - * - * \param [in] enabled load current state - * - */ -static inline void hw_gpadc_set_ldo_constant_current(bool enabled) -{ - REG_SETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_I20U, !!enabled); -} - -/** - * \brief Get current state of constant 20uA load current on ADC LDO output - * - * \return load current current state - * - * \sa hw_gpadc_set_ldo_constant_current - * - */ -static inline bool hw_gpadc_get_ldo_constant_current(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_I20U); -} - -/** - * \brief Set state of dynamic 10uA load current on ADC LDO output - * - * 10uA load current on LDO output can be enabled during sample phase so that the load current - * during sampling and conversion phase becomes approximately the same. - * - * \param [in] enabled load current state - * - */ -static inline void hw_gpadc_set_ldo_dynamic_current(bool enabled) -{ - REG_SETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_IDYN, !!enabled); -} - -/** - * \brief Get current state of dynamic 10uA load current on ADC LDO output - * - * \return load current current state - * - * \sa hw_gpadc_set_ldo_dynamic_current - * - */ -static inline bool hw_gpadc_get_ldo_dynamic_current(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL2_REG, GP_ADC_IDYN); -} - -/** - * \brief Set interval between conversions in continuous mode - * - * Interval time is \p mult x 1.024ms. Valid values are 0-255. - * - * \param [in] mult multiplier - * - * \sa hw_gpadc_set_continuous - * - */ -static inline void hw_gpadc_set_interval(uint8_t mult) -{ - REG_SETF(GPADC, GP_ADC_CTRL3_REG, GP_ADC_INTERVAL, mult); -} - -/** - * \brief Get current interval between conversions in continuous mode - * - * \return multiplier - * - * \sa hw_gpadc_set_interval - * - */ -static inline uint8_t hw_gpadc_get_interval(void) -{ - return REG_GETF(GPADC, GP_ADC_CTRL3_REG, GP_ADC_INTERVAL); -} - -/** - * \brief Set offset adjustment for positive ADC array - * - * \param [in] offset offset value - * - * \sa hw_gpadc_calibrate - * \sa hw_gpadc_set_negative_offset - * - */ -static inline void hw_gpadc_set_offset_positive(uint16_t offset) -{ - GPADC->GP_ADC_OFFP_REG = offset & REG_MSK(GPADC, GP_ADC_OFFP_REG, GP_ADC_OFFP); -} - -/** - * \brief Get current offset adjustment for positive ADC array - * - * \return offset value - * - */ -static inline uint16_t hw_gpadc_get_offset_positive(void) -{ - return GPADC->GP_ADC_OFFP_REG & REG_MSK(GPADC, GP_ADC_OFFP_REG, GP_ADC_OFFP); -} - -/** - * \brief Set offset adjustment for negative ADC array - * - * \param [in] offset offset value - * - * \sa hw_gpadc_calibrate - * \sa hw_gpadc_set_positive_offset - * - */ -static inline void hw_gpadc_set_offset_negative(uint16_t offset) -{ - GPADC->GP_ADC_OFFN_REG = offset & REG_MSK(GPADC, GP_ADC_OFFN_REG, GP_ADC_OFFN); -} - - -/** - * \brief Get current offset adjustment for negative ADC array - * - * \return offset value - * - */ -static inline uint16_t hw_gpadc_get_offset_negative(void) -{ - return GPADC->GP_ADC_OFFN_REG & REG_MSK(GPADC, GP_ADC_OFFN_REG, GP_ADC_OFFN); -} - -/** - * \brief Store Single Ended ADC Gain Error - * - * \param [in] single ADC Single Ended Gain Error - * - */ -static inline void hw_gpadc_store_se_gain_error(int16_t single) -{ - hw_gpadc_single_ended_gain_error = single; -} - -/** - * \brief Store Differential ADC Gain Error - * - * \param [in] diff ADC Differential Gain Error - * - */ -static inline void hw_gpadc_store_diff_gain_error(int16_t diff) -{ - hw_gpadc_differential_gain_error = diff; -} - -/** - * \brief Check the availability of ADC Gain Error - * - * \return ADC Gain Error availability - * - */ -static inline bool hw_gpadc_pre_check_for_gain_error(void) -{ - if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) { - return (hw_gpadc_single_ended_gain_error && hw_gpadc_differential_gain_error); - } - - return false; -} - -/** - * \brief Get raw conversion result value - * - * Upper 10 bits are always valid, lower 6 bits are only valid in case oversampling is enabled. - * - * \return conversion result value - * - * \sa hw_gpadc_start - * \sa hw_gpadc_set_oversampling - * \sa hw_gpadc_get_value - * - */ -uint16_t hw_gpadc_get_raw_value(void); - -/** - * \brief Get conversion result value - * - * Invalid bits are discarded from result, i.e. oversampling is taken into account when calculating - * value. - * - * \return conversion result value - * - * \sa hw_gpadc_set_oversampling - * \sa hw_gpadc_get_raw_value - * - */ -static inline uint16_t hw_gpadc_get_value(void) -{ - return hw_gpadc_get_raw_value() >> (6 - MIN(6, hw_gpadc_get_oversampling())); -} - -/** - * \brief Get conversion result value without gain compensation and over sampling. - * - * \return conversion result value - * - */ -static inline uint16_t hw_gpadc_get_value_without_gain(void) -{ - uint16_t adc_raw_res = GPADC->GP_ADC_RESULT_REG; - return adc_raw_res; -} - -/** - * \brief Start a measurement and wait for the result. - * - * \sa hw_gpadc_start - * \sa hw_gpadc_in_progress - * \sa hw_gpadc_clear_interrupt - * - */ -void hw_gpadc_adc_measure(void); - -/** - * \brief Take measurements using the ADC and evaluate the results. - * - * \sa hw_gpadc_adc_measure - * \sa hw_gpadc_get_raw_value - * - */ -void hw_gpadc_test_measurements(void); - -#endif /* dg_configUSE_HW_GPADC */ - -#endif /* HW_GPADC_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpio.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpio.h deleted file mode 100644 index 862193ea3..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpio.h +++ /dev/null @@ -1,495 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup GPIO - * \{ - * \brief GPIO Control - */ - -/** - ***************************************************************************************** - * - * @file hw_gpio.h - * - * @brief Definition of API for the GPIO Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_GPIO_H_ -#define HW_GPIO_H_ - -#if dg_configUSE_HW_GPIO - -#include -#include -#include - -/* GPIO layout definitions */ - -/** Number of GPIO ports available */ -#define HW_GPIO_NUM_PORTS (5) -/** Number of GPIO pins available (cumulative) */ -#define HW_GPIO_NUM_PINS (HW_GPIO_PORT_0_NUM_PINS + HW_GPIO_PORT_1_NUM_PINS + \ - HW_GPIO_PORT_2_NUM_PINS + HW_GPIO_PORT_3_NUM_PINS + \ - HW_GPIO_PORT_4_NUM_PINS) -/** Number of GPIO pins available in port 0 */ -#define HW_GPIO_PORT_0_NUM_PINS (8) -/** Number of GPIO pins available in port 1 */ -#define HW_GPIO_PORT_1_NUM_PINS (8) -/** Number of GPIO pins available in port 2 */ -#define HW_GPIO_PORT_2_NUM_PINS (5) -/** Number of GPIO pins available in port 3 */ -#define HW_GPIO_PORT_3_NUM_PINS (8) -/** Number of GPIO pins available in port 4 */ -#define HW_GPIO_PORT_4_NUM_PINS (8) -/** Number of pins in each GPIO port */ -extern const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS]; - - -/** - * \brief GPIO input/output mode - * - */ -typedef enum { - HW_GPIO_MODE_INPUT = 0, /**< GPIO as an input */ - HW_GPIO_MODE_INPUT_PULLUP = 0x100, /**< GPIO as an input with pull-up */ - HW_GPIO_MODE_INPUT_PULLDOWN = 0x200, /**< GPIO as an input with pull-down */ - HW_GPIO_MODE_OUTPUT = 0x300, /**< GPIO as an (implicitly push-pull) output */ - HW_GPIO_MODE_OUTPUT_PUSH_PULL = 0x300, /**< GPIO as an (explicitly push-pull) output */ - HW_GPIO_MODE_OUTPUT_OPEN_DRAIN = 0x700, /**< GPIO as an open-drain output */ -} HW_GPIO_MODE; - -/** - * \brief GPIO power source - * - */ -typedef enum { - HW_GPIO_POWER_V33 = 0, /**< V33 (3.3 V) power rail */ - HW_GPIO_POWER_VDD1V8P = 1, /**< VDD1V8P (1.8 V) power rail */ -} HW_GPIO_POWER; - -/** - * \brief GPIO port number - * - */ -typedef enum { - HW_GPIO_PORT_0 = 0, /**< GPIO Port 0 */ - HW_GPIO_PORT_1 = 1, /**< GPIO Port 1 */ - HW_GPIO_PORT_2 = 2, /**< GPIO Port 2 */ - HW_GPIO_PORT_3 = 3, /**< GPIO Port 3 */ - HW_GPIO_PORT_4 = 4 /**< GPIO Port 4 */ -} HW_GPIO_PORT; - -/** - * \brief GPIO pin number - * - */ -typedef enum { - HW_GPIO_PIN_0 = 0, /**< GPIO Pin 0 */ - HW_GPIO_PIN_1 = 1, /**< GPIO Pin 1 */ - HW_GPIO_PIN_2 = 2, /**< GPIO Pin 2 */ - HW_GPIO_PIN_3 = 3, /**< GPIO Pin 3 */ - HW_GPIO_PIN_4 = 4, /**< GPIO Pin 4 */ - HW_GPIO_PIN_5 = 5, /**< GPIO Pin 5 */ - HW_GPIO_PIN_6 = 6, /**< GPIO Pin 6 */ - HW_GPIO_PIN_7 = 7, /**< GPIO Pin 7 */ -} HW_GPIO_PIN; - -/** - * \brief GPIO function - * - */ -typedef enum { - HW_GPIO_FUNC_GPIO = 0, /**< GPIO */ - HW_GPIO_FUNC_UART_RX = 1, /**< GPIO as UART RX */ - HW_GPIO_FUNC_UART_TX = 2, /**< GPIO as UART TX */ - HW_GPIO_FUNC_UART_IRDA_RX = 3, /**< GPIO as UART IRDA RX */ - HW_GPIO_FUNC_UART_IRDA_TX = 4, /**< GPIO as UART IRDA TX */ - HW_GPIO_FUNC_UART2_RX = 5, /**< GPIO as UART2 RX */ - HW_GPIO_FUNC_UART2_TX = 6, /**< GPIO as UART2 TX */ - HW_GPIO_FUNC_UART2_IRDA_RX = 7, /**< GPIO as UART2 IRDA RX */ - HW_GPIO_FUNC_UART2_IRDA_TX = 8, /**< GPIO as UART2 IRDA TX */ - HW_GPIO_FUNC_UART2_CTSN = 9, /**< GPIO as UART2 CTSN */ - HW_GPIO_FUNC_UART2_RTSN = 10, /**< GPIO as UART2 RTSN */ - HW_GPIO_FUNC_SPI_DI = 11, /**< GPIO as SPI DI */ - HW_GPIO_FUNC_SPI_DO = 12, /**< GPIO as SPI DO */ - HW_GPIO_FUNC_SPI_CLK = 13, /**< GPIO as SPI CLK */ - HW_GPIO_FUNC_SPI_EN = 14, /**< GPIO as SPI EN */ - HW_GPIO_FUNC_SPI2_DI = 15, /**< GPIO as SPI2 DI */ - HW_GPIO_FUNC_SPI2_DO = 16, /**< GPIO as SPI2 DO */ - HW_GPIO_FUNC_SPI2_CLK = 17, /**< GPIO as SPI2 CLK */ - HW_GPIO_FUNC_SPI2_EN = 18, /**< GPIO as SPI2 EN */ - HW_GPIO_FUNC_I2C_SCL = 19, /**< GPIO as I2C SCL */ - HW_GPIO_FUNC_I2C_SDA = 20, /**< GPIO as I2C SDA */ - HW_GPIO_FUNC_I2C2_SCL = 21, /**< GPIO as I2C2 SCL */ - HW_GPIO_FUNC_I2C2_SDA = 22, /**< GPIO as I2C2 SDA */ - HW_GPIO_FUNC_PWM0 = 23, /**< GPIO as PWM0 */ - HW_GPIO_FUNC_PWM1 = 24, /**< GPIO as PWM1 */ - HW_GPIO_FUNC_PWM2 = 25, /**< GPIO as PWM2 */ - HW_GPIO_FUNC_PWM3 = 26, /**< GPIO as PWM3 */ - HW_GPIO_FUNC_PWM4 = 27, /**< GPIO as PWM4 */ - HW_GPIO_FUNC_BLE_DIAG = 28, /**< GPIO as BLE DIAG */ - HW_GPIO_FUNC_FTDF_DIAG = 29, /**< GPIO as FTDF DIAG */ - HW_GPIO_FUNC_PCM_DI = 30, /**< GPIO as PCM DI */ - HW_GPIO_FUNC_PCM_DO = 31, /**< GPIO as PCM DO */ - HW_GPIO_FUNC_PCM_FSC = 32, /**< GPIO as PCM FSC */ - HW_GPIO_FUNC_PCM_CLK = 33, /**< GPIO as PCM CLK */ - HW_GPIO_FUNC_PDM_DI = 34, /**< GPIO as PDM DI */ - HW_GPIO_FUNC_PDM_DO = 35, /**< GPIO as PDM DO */ - HW_GPIO_FUNC_PDM_CLK = 36, /**< GPIO as PDM CLK */ - HW_GPIO_FUNC_USB_SOF = 37, /**< GPIO as USB SOF */ - HW_GPIO_FUNC_ADC = 38, /**< GPIO as ADC */ - HW_GPIO_FUNC_USB = 38, /**< GPIO as USB */ - HW_GPIO_FUNC_QSPI = 38, /**< GPIO as QSPI */ - HW_GPIO_FUNC_XTAL32 = 38, /**< GPIO as XTAL32 */ - HW_GPIO_FUNC_QUADEC_XA = 39, /**< GPIO as QUADEC XA */ - HW_GPIO_FUNC_QUADEC_XB = 40, /**< GPIO as QUADEC XB */ - HW_GPIO_FUNC_QUADEC_YA = 41, /**< GPIO as QUADEC YA */ - HW_GPIO_FUNC_QUADEC_YB = 42, /**< GPIO as QUADEC YB */ - HW_GPIO_FUNC_QUADEC_ZA = 43, /**< GPIO as QUADEC ZA */ - HW_GPIO_FUNC_QUADEC_ZB = 44, /**< GPIO as QUADEC ZB */ - HW_GPIO_FUNC_IR_OUT = 45, /**< GPIO as IR OUT */ - HW_GPIO_FUNC_BREATH = 46, /**< GPIO as BREATH */ - HW_GPIO_FUNC_KB_ROW = 47, /**< GPIO as KB ROW */ - HW_GPIO_FUNC_COEX_EXT_ACT0 = 48, /**< GPIO as COEX EXT ACT0 */ - HW_GPIO_FUNC_COEX_EXT_ACT1 = 49, /**< GPIO as COEX EXT ACT1 */ - HW_GPIO_FUNC_COEX_SMART_ACT = 50, /**< GPIO as COEX SMART ACT */ - HW_GPIO_FUNC_COEX_SMART_PRI = 51, /**< GPIO as COEX SMART PRI */ - HW_GPIO_FUNC_CLOCK = 52, /**< GPIO as CLOCK */ - HW_GPIO_FUNC_ONESHOT = 53, /**< GPIO as ONESHOT */ - HW_GPIO_FUNC_PWM5 = 54, /**< GPIO as PWM5 */ - HW_GPIO_FUNC_PORT0_DCF = 55, /**< GPIO as PORT0 DCF */ - HW_GPIO_FUNC_PORT1_DCF = 56, /**< GPIO as PORT1 DCF */ - HW_GPIO_FUNC_PORT2_DCF = 57, /**< GPIO as PORT2 DCF */ - HW_GPIO_FUNC_PORT3_DCF = 58, /**< GPIO as PORT3 DCF */ - HW_GPIO_FUNC_PORT4_DCF = 59, /**< GPIO as PORT4 DCF */ - HW_GPIO_FUNC_RF_ANT_TRIM0 = 60, /**< GPIO as RF ANT TRIM0 */ - HW_GPIO_FUNC_RF_ANT_TRIM1 = 61, /**< GPIO as RF ANT TRIM1 */ - HW_GPIO_FUNC_RF_ANT_TRIM2 = 62 /**< GPIO as RF ANT TRIM2 */ -} HW_GPIO_FUNC; - -/** - * \brief GPIO pin configuration - * - * It's recommended to use \p HW_GPIO_PINCONFIG and \p HW_GPIO_PINCONFIG_RESERVE to set pin entries. - * Each configuration must be terminated using \p HW_GPIO_PINCONFIG_END macro. - * - */ -typedef struct { - uint8_t pin; /**< pin name, high-nibble is port number and low-nibble is pin */ - HW_GPIO_MODE mode; /**< pin mode */ - HW_GPIO_FUNC func; /**< pin function */ - bool high; /**< initial pin state, true for high and false for low */ - bool reserve; /*<< true if pin should be also reserved */ -} __attribute__((packed)) gpio_config; - -/** - * \brief GPIO pin configuration for \p gpio_config - * - * \p xport and \p xpin are specified as symbols from \p HW_GPIO_PORT and \p HW_GPIO_PIN enums - * respectively or more conveniently as plain numeric values. - * \p xmode and \p xfunc have the same values as defined in \p HW_GPIO_MODE and \p HW_GPIO_FUNC enums - * respectively, except they have prefix stripped. - * - * \param [in] xport port number - * \param [in] xpin pin number - * \param [in] xmode pin mode - * \param [in] xfunc pin function - * \param [in] xhigh true for high state, false otherwise - * - */ -#define HW_GPIO_PINCONFIG(xport, xpin, xmode, xfunc, xhigh) \ - { \ - .pin = (xport << 4) | (xpin & 0x0F), \ - .mode = HW_GPIO_MODE_ ## xmode, \ - .func = HW_GPIO_FUNC_ ## xfunc, \ - .high = xhigh, \ - .reserve = false, \ - } - -/** - * \brief GPIO pin configuration and reservation for \p gpio_config - * - * This macro is virtually identical to \p HW_GPIO_PINCONFIG, except it also reserves pin. - * - * \param [in] xport port number - * \param [in] xpin pin number - * \param [in] xmode pin mode - * \param [in] xfunc pin function - * \param [in] xhigh true for high state, false otherwise - * - * \sa HW_GPIO_PINCONFIG - * - */ -#define HW_GPIO_PINCONFIG_RESERVE(xport, xpin, xmode, xfunc, xhigh) \ - { \ - .pin = (xport << 4) | (xpin & 0x0F), \ - .mode = HW_GPIO_MODE_ ## xmode, \ - .func = HW_GPIO_FUNC_ ## xfunc, \ - .high = xhigh, \ - .reserve = true, \ - } - -/** - * \brief Macro to properly terminate array of \p gpio_config definition - * - */ -#define HW_GPIO_PINCONFIG_END \ - { \ - .pin = 0xFF, \ - } - -/** - * \brief GPIO configuration - * - * This is a shortcut to configure multiple GPIOs in one call. - * \p cfg is an array of GPIO pins configuration, it should be terminated by dummy element with - * \p pin member set to 0xFF (macro \p HW_GPIO_PINCONFIG can be used for this purpose). - * - * \param [in] cfg GPIO pins configuration - * - * \sa hw_gpio_configure_pin - * \sa hw_gpio_set_pin_function - * - */ -void hw_gpio_configure(const gpio_config cfg[]); - -/** - * \brief Reserve GPIO pin - * - * Reserve pin for exclusive usage. - * This macro can be used in application peripheral_setup function to detect - * usage of same GPIO pin by different applications. - * - * \param [in] port GPIO port number - * \param [in] pin GPIO pin number - * - * \return true if pin was successfully reserved and setup, false if pin was already reserved - * - */ -bool hw_gpio_reserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin); - -/** - * \brief Reserve GPIO pin and set pin function - * - * Reserve pin and set up it function. If pin was already reserved do nothing. - * - * \param [in] port GPIO port number - * \param [in] pin GPIO pin number - * \param [in] mode GPIO access mode - * \param [in] function GPIO function - * \param [in] high in case of PID_GPIO and OUTPUT value to set on pin - * - * \return true if pin was successfully reserved and setup, false if pin was already reserved - * - */ -bool hw_gpio_reserve_and_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function, bool high); - -/** - * \brief Unreserve GPIO pin - * - * Free reserved pin. If pin was not reserved do nothing. - * Configuration of pin does not change just reservation. - * - * \note If pin was reserved using RESERVE_GPIO it will also be unreserved. - * If RESERVE_GPIO was not enabled by compile time flags call to this function - * may cause unexpected result. - * - * \param [in] port GPIO port number - * \param [in] pin GPIO pin number - * - * \sa hw_gpio_reserve_and_configure_pin - * \sa hw_gpio_reserve_pin - * \sa RESERVE_GPIO - * - */ -void hw_gpio_unreserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin); - -#if (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) -/** - * \brief Reserve GPIO pin - * - * Reserve pin for exclusive usage. If pin is already allocated trigger breakpoint. - * This macro should be used in application peripheral_setup function to detect - * usage of same GPIO pin by different applications. - * - * If runtime GPIO reservation is needed, use hw_gpio_reserve_pin, - * hw_gpio_reserve_and_configure_pin and hw_gpio_unreserve_pin instead. - * - * \param [in] name parameter ignored, used for debug only - * \param [in] port GPIO port number - * \param [in] pin GPIO pin number - * \param [in] func parameter ignored (for compatibility) - * - * \sa hw_gpio_reserve_pin - * \sa hw_gpio_reserve_and_configure_pin - * \sa hw_gpio_unreserve_pin instead - * - */ -#define RESERVE_GPIO(name, port, pin, func) \ - do { \ - if (!hw_gpio_reserve_pin((port), (pin))) { \ - /* If debugger stops at this line, there is configuration problem */ \ - /* pin is used without being reserved first */ \ - __BKPT(0); /* this pin has not been previously reserved! */ \ - } \ - } while (0) - -#else - -#define RESERVE_GPIO( name, port, pin, func ) \ - do { \ - \ - } while (0) - -#endif // (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) - -/** - * \brief Set the pin type and mode - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * \param [in] mode GPIO pin mode - * \param [in] function GPIO pin usage - * - */ -void hw_gpio_set_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function); - -/** - * \brief Get the pin type and mode - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * \param [out] mode GPIO pin mode - * \param [out] function GPIO pin usage - * - */ -void hw_gpio_get_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE* mode, - HW_GPIO_FUNC* function); - -/** - * \brief Combined function to set the state and the type and mode of the GPIO pin - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * \param [in] mode GPIO pin mode - * \param [in] function GPIO pin usage - * \param [in] high set to TRUE to set the pin into high else low - * - */ -void hw_gpio_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function, const bool high); - -/** - * \brief Configure power source for pin output - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * \param [in] power GPIO power source - * - */ -void hw_gpio_configure_pin_power(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_POWER power); - -/** - * \brief Set a GPIO in high state - * - * The GPIO should have been previously configured as an output! - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * - */ -void hw_gpio_set_active(HW_GPIO_PORT port, HW_GPIO_PIN pin); - -/** - * \brief Set a GPIO in low state - * - * The GPIO should have been previously configured as an output! - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * - */ -void hw_gpio_set_inactive(HW_GPIO_PORT port, HW_GPIO_PIN pin); - -/** - * \brief Get the GPIO status - * - * The GPIO should have been previously configured as input! - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * - * \return true if the pin is high, false if low - * - */ -bool hw_gpio_get_pin_status(HW_GPIO_PORT port, HW_GPIO_PIN pin); - -/** - * \brief Toggle GPIO pin state - * - * \param [in] port GPIO port - * \param [in] pin GPIO pin - * - */ -void hw_gpio_toggle(HW_GPIO_PORT port, HW_GPIO_PIN pin); - -/** - * \brief Find pins with specific function - * - * Function searches for pins configured for specific function. - * If buf is not NULL and buf_size is greater than 0 pins are stored in buf - * high-nibble is port number and low-nibble is pin. - * If number of pins found is greater then buf_size only buf_size entries are filled, though - * the returned number of found pins is correct. - * - * \param [in] func function to lookup - * \param [out] buf buffer for port-pin pairs that are configured for specific function - * \param [in] buf_size size of buf - * - * \return number of pins with specific function put in buf - * 0 - no pin is configured for this function - * - */ -int hw_gpio_get_pins_with_function(HW_GPIO_FUNC func, uint8_t *buf, int buf_size); - - -#endif /* dg_configUSE_HW_GPIO */ - -#endif /* HW_GPIO_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_hard_fault.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_hard_fault.h deleted file mode 100644 index b233fad73..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_hard_fault.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup Exception_Handlers - * \{ - * \brief Generic Exception Handlers - */ - -/** - ***************************************************************************************** - * - * @file hw_hard_fault.h - * - * @brief Hard-Fault Handler include file. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_HARD_FAULT_H_ -#define HW_HARD_FAULT_H_ - - -#include -#include -#include - -#define HARDFAULT_MAGIC_NUMBER 0xBADC0FFE - -/** - * \brief Holds the stack contents when a hard-fault occurs. - * - * \details The stack contents are copied at this variable when a hard-fault occurs. The first - * position is marked with a special "flag" (0xBADC0FFE) to indicate that the data that - * follow are valid. - */ -extern uint32_t hardfault_event_data[9]; - -#endif /* HW_HARD_FAULT_H_ */ - - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_led.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_led.h deleted file mode 100644 index 1f4c484be..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_led.h +++ /dev/null @@ -1,152 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup LED - * \{ - * \brief LED Controller - */ - -/** - ***************************************************************************************** - * - * @file hw_led.h - * - * @brief Definition of API for the LED Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_LED_H_ -#define HW_LED_H_ - -#include - -/** - * \brief Source for LED1 - */ -typedef enum { - HW_LED_SRC1_PWM2 = 0, /**< LED1 controlled by PWM2 */ - HW_LED_SRC1_BREATH = 1 /**< LED1 controlled by Breath Timer */ -} HW_LED_SRC1; - -/** - * \brief Source for LED2 - */ -typedef enum { - HW_LED_SRC2_PWM3 = 0, /**< LED2 controlled by PWM3 */ - HW_LED_SRC2_BREATH = 1 /**< LED2 controlled by Breath Timer */ -} HW_LED_SRC2; - -/** - * \brief Source for LED3 - */ -typedef enum { - HW_LED_SRC3_PWM4 = 0, /**< LED3 controlled by PWM4 */ - HW_LED_SRC3_BREATH = 1 /**< LED3 controlled by Breath Timer */ -} HW_LED_SRC3; - - -/** - * \brief Set the source that controls LED1 - * - * \param [in] src the source that controls LED1 - * - * \sa HW_LED_SRC1 - */ -__STATIC_INLINE void hw_led_set_led1_src(HW_LED_SRC1 src) -{ - REG_SETF(GPREG, LED_CONTROL_REG, LED1_SRC_SEL, src); -} - -/** - * \brief Set the source that controls LED2 - * - * \param [in] src the source that controls LED2 - * - * \sa HW_LED_SRC2 - */ -__STATIC_INLINE void hw_led_set_led2_src(HW_LED_SRC2 src) -{ - REG_SETF(GPREG, LED_CONTROL_REG, LED2_SRC_SEL, src); -} - -/** - * \brief Set the source that controls LED3 - * - * \param [in] src the source that controls LED3 - * - * \sa HW_LED_SRC3 - */ -__STATIC_INLINE void hw_led_set_led3_src(HW_LED_SRC3 src) -{ - REG_SETF(GPREG, LED_CONTROL_REG, LED3_SRC_SEL, src); -} - -/** - * \brief Enable or disable LED1 - * - * \param [in] state true to enable LED1, or false to disable it - * - */ -__STATIC_INLINE void hw_led_enable_led1(bool state) -{ - REG_SETF(GPREG, LED_CONTROL_REG, LED1_EN, state); -} - -/** - * \brief Enable or disable LED2 - * - * \param [in] state true to enable LED2, or false to disable it - * - */ -__STATIC_INLINE void hw_led_enable_led2(bool state) -{ - REG_SETF(GPREG, LED_CONTROL_REG, LED2_EN, state); -} - -/** - * \brief Enable or disable LED3 - * - * \param [in] state true to enable LED3, or false to disable it - * - */ -__STATIC_INLINE void hw_led_enable_led3(bool state) -{ - REG_SETF(GPREG, LED_CONTROL_REG, LED3_EN, state); -} - - -#endif /* HW_LED_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_otpc.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_otpc.h deleted file mode 100644 index 291568601..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_otpc.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup OTPC - * \{ - * \brief OTP Memory Controller - */ - -/** - **************************************************************************************** - * - * @file hw_otpc.h - * - * @brief Definition of API for the OTP Controller driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef HW_OTPC_H_ -#define HW_OTPC_H_ - -#if dg_configUSE_HW_OTPC - -#include -#include -#include - - -/** - * \brief Get the mask of a field of an OTPC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_OTPC_REG_FIELD_MASK(reg, field) \ - (OTPC_OTPC_##reg##_REG_##OTPC_##reg##_##field##_Msk) - -/** - * \brief Get the bit position of a field of an OTPC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_OTPC_REG_FIELD_POS(reg, field) \ - (OTPC_OTPC_##reg##_REG_##OTPC_##reg##_##field##_Pos) - -/** - * \brief Prepare (i.e. shift and mask) a value to be used for an OTPC register field. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * \param [in] val is the value to prepare - * - */ -#define HW_OTPC_FIELD_VAL(reg, field, val) \ - (((val) << HW_OTPC_REG_FIELD_POS(reg, field)) & HW_OTPC_REG_FIELD_MASK(reg, field)) - -/** - * \brief Get the value of a field of an OTPC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * - * \return the value of the register field - * - */ -#define HW_OTPC_REG_GETF(reg, field) \ - ((OTPC->OTPC_##reg##_REG & (OTPC_OTPC_##reg##_REG_##OTPC_##reg##_##field##_Msk)) >> (OTPC_OTPC_##reg##_REG_##OTPC_##reg##_##field##_Pos)) - -/** - * \brief Set the value of a field of an OTPC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * \param [in] new_val is the value to write - * - */ -#define HW_OTPC_REG_SETF(reg, field, new_val) \ - OTPC->OTPC_##reg##_REG = ((OTPC->OTPC_##reg##_REG & ~(OTPC_OTPC_##reg##_REG_##OTPC_##reg##_##field##_Msk)) | \ - ((OTPC_OTPC_##reg##_REG_##OTPC_##reg##_##field##_Msk) & ((new_val) << (OTPC_OTPC_##reg##_REG_##OTPC_##reg##_##field##_Pos)))) - - -/** - * \brief OTP Controller mode - */ -typedef enum { - HW_OTPC_MODE_STBY = 0, - HW_OTPC_MODE_MREAD = 1, - HW_OTPC_MODE_MPROG = 2, - HW_OTPC_MODE_AREAD = 3, - HW_OTPC_MODE_APROG = 4, - HW_OTPC_MODE_TBLANK = 5, - HW_OTPC_MODE_TDEC = 6, - HW_OTPC_MODE_TWR = 7 -} HW_OTPC_MODE; - -#define MAX_RR_AVAIL (8) - -#define OTP_CLK_IS_16M (0) -#define OTP_CLK_IS_32M (1) -#define OTP_CLK_IS_48M (2) - - -/** - * \brief Word inside cell to program/read - * - * Cell contents in memory starts with low word (i.e. to program/read both words in cell at once, - * HW_OTPC_WORD_LOW should be used for addressing). - * - */ -typedef enum { - HW_OTPC_WORD_LOW = 0, - HW_OTPC_WORD_HIGH = 1 -} HW_OTPC_WORD; - - -/** - * \brief System clock frequency in MHz - * - */ -typedef enum { - HW_OTPC_SYS_CLK_FREQ_1 = 0, - HW_OTPC_SYS_CLK_FREQ_2 = 1, - HW_OTPC_SYS_CLK_FREQ_3 = 2, - HW_OTPC_SYS_CLK_FREQ_4 = 3, - HW_OTPC_SYS_CLK_FREQ_6 = 4, - HW_OTPC_SYS_CLK_FREQ_8 = 5, - HW_OTPC_SYS_CLK_FREQ_12 = 6, - HW_OTPC_SYS_CLK_FREQ_16 = 7, - HW_OTPC_SYS_CLK_FREQ_24 = 8, - HW_OTPC_SYS_CLK_FREQ_32 = 9, - HW_OTPC_SYS_CLK_FREQ_48 = 10 -} HW_OTPC_SYS_CLK_FREQ; - -/* - * Reset values of OTPC registers - */ -#define OTPC_MODE_REG_RESET (0x00000000) -#define OTPC_PCTRL_REG_RESET (0x00000000) -#define OTPC_STAT_REG_RESET (0x00000051) -#define OTPC_AHBADR_REG_RESET (0x07FC0000) -#define OTPC_CELADR_REG_RESET (0x00000000) -#define OTPC_NWORDS_REG_RESET (0x00000000) -#define OTPC_FFPRT_REG_RESET (0x00000000) -#define OTPC_FFRD_REG_RESET (0x00000000) -#define OTPC_PWORDL_REG_RESET (0x00000000) -#define OTPC_PWORDH_REG_RESET (0x00000000) -#define OTPC_TIM1_REG_RESET (0x1A104F20) -#define OTPC_TIM2_REG_RESET (0x00010000) - -/** - * \brief Convert system clock frequency expressed in MHz to equivalent HW_OTPC_SYS_CLK_FREQ value - * - * \sa HW_OTPC_SYS_CLK_FREQ - */ -__RETAINED_CODE HW_OTPC_SYS_CLK_FREQ hw_otpc_convert_sys_clk_mhz(uint32_t clk_freq); - - -/** - * \brief Initialize the OTP Controller. - * - * \warning The AHB clock must be up to 48MHz! It is a responsibility of the caller to check this! - * - */ -static inline void hw_otpc_init(void) -{ - GLOBAL_INT_DISABLE(); - if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE))) { - /* - * Reset OTP controller - */ - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_STBY; // Set OTPC to standby - REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, OTPC_RESET_REQ); // Reset the OTPC - REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, OTPC_RESET_REQ); // Get the OTPC out of Reset - - /* - * Initialize the POR registers - */ - OTPC->OTPC_NWORDS_REG = OTPC_NWORDS_REG_RESET; - OTPC->OTPC_TIM1_REG = OTPC_TIM1_REG_RESET; - OTPC->OTPC_TIM2_REG = OTPC_TIM2_REG_RESET; - } - - /* - * Enable OTPC clock - */ - CRG_TOP->CLK_AMBA_REG |= 1 << REG_POS(CRG_TOP, CLK_AMBA_REG, OTP_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Close the OTP Controller. - * - */ -static inline void hw_otpc_close(void) -{ - /* - * Disable OTPC clock - */ - GLOBAL_INT_DISABLE(); - CRG_TOP->CLK_AMBA_REG &= ~REG_MSK(CRG_TOP, CLK_AMBA_REG, OTP_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Check if the OTP Cotnroller is active. - * - * \return 1 if it is active, else 0. - * - */ -static inline uint32_t hw_otpc_is_active(void) __attribute__((always_inline)); - -static inline uint32_t hw_otpc_is_active(void) -{ - /* - * Check if the OTPC clock is enabled - */ - return !!(CRG_TOP->CLK_AMBA_REG & REG_MSK(CRG_TOP, CLK_AMBA_REG, OTP_ENABLE)); -} - -/** - * \brief Put the OTP Controller in STBY mode and turn-off clock. - * - */ -void hw_otpc_disable(void); - -/** - * \brief Set the access speed of the OTP Controller based on the system clock. - * - * \details Switch from PLL to XTAL : call function after clock switch with high_clk_speed == false - * Switch from XTAL to PLL : call function before clock switch with high_clk_speed == true - * - * \param [in] clk_speed The frequency of the system clock: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 and 48. - * - * \warning The OTP clock must have been enabled (OTP_ENABLE == 1). - * (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -__RETAINED_CODE void hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ clk_speed); - -/** - * \brief Set or reset the power saving mode of the OTP Controller. - * - * \param [in] inactivity_period The number of HCLK cycles to remain powered while no access is made. - * If set to 0, this feature is disabled. - * - * \warning The hw_otpc_init() and hw_otpc_set_speed() must have been called. - * (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - */ -void hw_otpc_power_save(uint32_t inactivity_period); - -/** - * \brief Get the number of the Repair Records. - * - * \return The number of used Repair Records. - * - * \warning The hw_otpc_init() and hw_otpc_set_speed() must have been called. The OTPC mode will be reset. - * (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - */ -uint32_t hw_otpc_num_of_rr(void); - -/** - * \brief Program manually an OTP entry. - * - * \param [in] cell_offset Cell offset to be programmed. - * - * \param [in] pword_l The low 32-bits of the 64-bit word to be written. - * - * \param [in] pword_h The high 32-bits of the 64-bit word to be written. - * - * \param [in] use_rr Use a Repair Record if writing fails when true. - * - * \return true for success, false for failure - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -bool hw_otpc_manual_word_prog(uint32_t cell_offset, uint32_t pword_l, uint32_t pword_h, bool use_rr); - -/** - * \brief Program manually an OTP block. - * - * \param [in] p_data The start address of the data to copy from. - * - * \param [in] cell_offset Cell offset to start programming from. - * - * \param [in] cell_word Word inside cell to start programming from. - * - * \param [in] num_of_words The actual number of the words to be written. - * - * \param [in] use_rr true to use Repair Records if writing fails - * - * \return true for success, false for failure - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -bool hw_otpc_manual_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool use_rr); - -/** - * \brief Put the OTP in manual read mode. - * - * \details In manual read mode the OTP is memory mapped to the address MEMORY_OTP_BASE. So, any - * access to this memory space results into reading from the OTP. The caller must make sure - * that the function hw_otpc_manual_read_off() is called when reading from the OTP is - * finished. - * - * \param [in] spare_rows true to access the spare rows area, false to access normal memory cell - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -void hw_otpc_manual_read_on(bool spare_rows); - -/** - * \brief Take the OTP out of manual read mode and put it in STBY. - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -void hw_otpc_manual_read_off(void); - -/** - * \brief Program manually a Repair Record in the OTP's spare area. - * - * \param [in] cell_offset The address programmed with errors. - * \param [in] pword_l The low 32-bits of the 64-bit word to be written. - * \param [in] pword_h The high 32-bits of the 64-bit word to be written. - * \return true for success, false for failure - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -bool hw_otpc_write_rr(uint32_t cell_offset, uint32_t pword_l, uint32_t pword_h); - -/** - * \brief Program OTP via DMA. - * - * \param [in] p_data The start address of the data in RAM. - * - * \param [in] cell_offset Cell offset to be programmed. - * - * \param [in] cell_word Word inside cell to be programmed. - * - * \param [in] num_of_words The actual number of the words to be written. The driver will write this - * value minus 1 to the specific register. - * - * \param [in] spare_rows true to access the spare rows area, false to access normal memory cell - * - * \return true for success, false for failure (the programming should be retried or fixed!) - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -bool hw_otpc_dma_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows); - -/** - * \brief Read OTP via DMA. - * - * \param [in] p_data The address in RAM to write the data to. - * - * \param [in] cell_offset Cell offset to be programmed. - * - * \param [in] cell_word Word inside cell to be programmed. - * - * \param [in] num_of_words The actual number of the words to be read. The driver will write this - * value minus 1 to the specific register. - * - * \param [in] spare_rows true to access the spare rows area, false to access normal memory cell - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -void hw_otpc_dma_read(uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows); - -/** - * \brief Program OTP via FIFO (Auto mode). - * - * \param [in] p_data The start address of the data in RAM. - * - * \param [in] cell_offset Cell offset to be programmed. - * - * \param [in] cell_word Word inside cell to be programmed. - * - * \param [in] num_of_words The actual number of the words to be written. The driver will write this - * value minus 1 to the specific register. - * - * \param [in] spare_rows true to access the spare rows area, false to access normal memory cell - * - * \return true for success, false for failure - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -bool hw_otpc_fifo_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows); - -/** - * \brief Read OTP via FIFO. - * - * \param [in] p_data The address in RAM to write the data to. - * - * \param [in] cell_offset Cell offset to be programmed. - * - * \param [in] cell_word Word inside cell to be programmed. - * - * \param [in] num_of_words The actual number of the words to be read. The driver will write this - * value minus 1 to the specific register. - * - * \param [in] spare_rows true to access the spare rows area, false to access normal memory cell - * - * \return true for success, false for failure - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -bool hw_otpc_fifo_read(uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows); - -/** - * \brief Prepare OTPC to execute an OTP copy after wakeup. - * - * \param [in] num_of_bytes The actual number of the bytes to be copied. The driver will write the - * proper value to the specific register. - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -void hw_otpc_prepare(uint32_t num_of_bytes); - -/** - * \brief Cancel any previous preparations of the OTPC for executing an OTP copy after wakeup. - * - * \warning The hw_otpc_init() and the hw_otpc_set_speed() must have been called and the mode must - * be STBY. (Note: the hw_otpc_set_speed() must be called only once when the PLL is used or - * during each clock switch when both PLL and XTAL16 are used, since the register bits it - * modifies are retained.) - * - */ -void hw_otpc_cancel_prepare(void); - -/** - * \brief Get cell memory address - * - * Returns mapped memory address for given cell, can be used for e.g. manual reading. - * - * \param [in] cell_offset cell offset - * - * \return cell memory address - * - * \sa hw_otpc_manual_read_on - * - */ -static inline void *hw_otpc_cell_to_mem(uint32_t cell_offset) -{ - return (void *) (MEMORY_OTP_BASE + (cell_offset << 3)); // cell size is 8 bytes -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// TEST FUNCTIONALITY -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** - * \brief Execution of the BLANK test. - * - * \return The test result. - *
    - *
  • 0, if the test succeeded - *
  • 1, if the test 1 failed - *
- * - */ -int hw_otpc_blank(void); - -/** - * \brief Execution of the TDEC test. - * - * \return The test result. - *
    - *
  • 0, if the test succeeded - *
  • 1, if the test 1 failed - *
- * - */ -int hw_otpc_tdec(void); - -/** - * \brief Execution of the TWR test. - * - * \return The test result. - *
    - *
  • 0, if the test succeeded - *
  • 1, if the test 1 failed - *
- * - */ -int hw_otpc_twr(void); - -#endif /* dg_configUSE_HW_OTPC */ - -#endif /* HW_OTPC_H_ */ - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_qspi.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_qspi.h deleted file mode 100644 index b1e967e9f..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_qspi.h +++ /dev/null @@ -1,1203 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup QSPI - * \{ - * \brief QSPI Flash Memory Controller - */ - -/** - ***************************************************************************************** - * - * @file hw_qspi.h - * - * @brief Definition of API for the QSPI Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_QSPI_H_ -#define HW_QSPI_H_ - -#if dg_configUSE_HW_QSPI - -#include -#include -#include - - -/** - * \brief Get the mask of a field of an QSPIC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_QSPIC_REG_FIELD_MASK(reg, field) \ - (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk) - -/** - * \brief Get the bit position of a field of an QSPIC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_QSPIC_REG_FIELD_POS(reg, field) \ - (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos) - -/** - * \brief Get the value of a field of an QSPIC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * - * \return the value of the register field - * - */ -#define HW_QSPIC_REG_GETF(reg, field) \ - ((QSPIC->QSPIC_##reg##_REG & (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk)) >> (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)) - -/** - * \brief Set the value of a field of an QSPIC register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * \param [in] new_val is the value to write - * - */ -#define HW_QSPIC_REG_SETF(reg, field, new_val) \ - QSPIC->QSPIC_##reg##_REG = ((QSPIC->QSPIC_##reg##_REG & ~(QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk)) | \ - ((QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk) & ((new_val) << (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)))) - - -extern uint8_t dummy_num[]; - -/* - * ENUMERATION DEFINITIONS - ***************************************************************************************** - */ - -/** - * \brief Bus mode - * - */ -typedef enum { - HW_QSPI_BUS_MODE_SINGLE, /**< Bus mode in single mode */ - HW_QSPI_BUS_MODE_DUAL, /**< Bus mode in dual mode */ - HW_QSPI_BUS_MODE_QUAD /**< Bus mode in quad mode */ -} HW_QSPI_BUS_MODE; - -/** - * \brief Flash memory address size - * - */ -typedef enum { - HW_QSPI_ADDR_SIZE_24, /**< QSPI flash memory uses 24 bits address */ - HW_QSPI_ADDR_SIZE_32 /**< QSPI flash memory uses 32 bits address */ -} HW_QSPI_ADDR_SIZE; - -/** - * \brief Idle clock state - * - */ -typedef enum { - HW_QSPI_POL_LOW = 0, /**< SPI clock will be low at idle */ - HW_QSPI_POL_HIGH = 1 /**< SPI clock will be high at idle */ -} HW_QSPI_POL; - -/** - * \brief Type of QSPI_CLK edge for sampling received data - * - */ -typedef enum { - HW_QSPI_SAMPLING_EDGE_POSITIVE = 0, /**< Sample the received data with the positive edge of the QSPI_SCK */ - HW_QSPI_SAMPLING_EDGE_NEGATIVE = 1 /**< Sample the received data with the negative edge of the QSPI_SCK */ -} HW_QSPI_SAMPLING_EDGE; - -/** - * \brief Selected data size of a wrapping burst - * - */ -typedef enum { - HW_QSPI_WRAP_SIZE_8BITS = 0, /**< Byte access (8-bits) */ - HW_QSPI_WRAP_SIZE_16BITS = 1, /**< Half word access (8-bits) */ - HW_QSPI_WRAP_SIZE_32BITS = 2, /**< Word access (8-bits) */ -} HW_QSPI_WRAP_SIZE; - -/** - * \brief Selected data length of a wrapping burst - * - */ -typedef enum { - HW_QSPI_WRAP_LEN_4BEAT = 0, /**< 4 beat wrapping burst */ - HW_QSPI_WRAP_LEN_8BEAT = 1, /**< 8 beat wrapping burst */ - HW_QSPI_WRAP_LEN_16BEAT = 2, /**< 16 beat wrapping burst */ -} HW_QSPI_WRAP_LEN; - -/** - * \brief Size of Burst Break Sequence - * - */ -typedef enum { - HW_QSPI_BREAK_SEQ_SIZE_1B = 0, /**< One byte */ - HW_QSPI_BREAK_SEQ_SIZE_2B = 1 /**< Two bytes */ -} HW_QSPI_BREAK_SEQ_SIZE; - -/** - * \brief QSPI pads slew rate control - * - */ -typedef enum { - HW_QSPI_SLEW_RATE_0, /**< xx V/ns (weak) */ - HW_QSPI_SLEW_RATE_1, /**< xx V/ns */ - HW_QSPI_SLEW_RATE_2, /**< xx V/ns */ - HW_QSPI_SLEW_RATE_3 /**< xx V/ns (strong) */ -} HW_QSPI_SLEW_RATE; - -/** - * \brief QSPI pads drive current - * - */ -typedef enum { - HW_QSPI_DRIVE_CURRENT_4, /**< 4 mA */ - HW_QSPI_DRIVE_CURRENT_8, /**< 8 mA */ - HW_QSPI_DRIVE_CURRENT_12, /**< 12 mA */ - HW_QSPI_DRIVE_CURRENT_16, /**< 16 mA */ -} HW_QSPI_DRIVE_CURRENT; - -/** - * \brief QSPI clock divider setting - * - */ -typedef enum { - HW_QSPI_DIV_1 = 0, /**< divide by 1 */ - HW_QSPI_DIV_2 = 1, /**< divide by 2 */ - HW_QSPI_DIV_4 = 2, /**< divide by 4 */ - HW_QSPI_DIV_8 = 3 /**< divide by 8 */ -} HW_QSPI_DIV; - -/** - * \brief QSPI configuration - * - */ -typedef struct { - HW_QSPI_ADDR_SIZE address_size; - HW_QSPI_POL idle_clock; - HW_QSPI_SAMPLING_EDGE sampling_edge; -} qspi_config; - -/** - * \brief Enable CS on QSPI bus - * - * Use this in manual mode. - * - */ -static inline void hw_qspi_cs_enable(void) __attribute__((always_inline)); - -static inline void hw_qspi_cs_enable(void) -{ - QSPIC->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk; -} - -/** - * \brief Disable CS on QSPI bus - * - * Use this in manual mode. - * - */ -static inline void hw_qspi_cs_disable(void) __attribute__((always_inline)); - -static inline void hw_qspi_cs_disable(void) -{ - QSPIC->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; -} - -/** - * \brief Select QSPI bus mode - * - * Use this in manual mode. - * - * \note Selecting QUAD mode will automatically configure pins IO2 and IO3 to input. - * - * \param [in] mode selects single/dual/quad mode for QSPI bus - * - */ -void hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE mode); - -/** - * \brief Check is SPI Bus is busy - * - * \return 0 - SPI Bus is idle, - * 1 - SPI Bus is active. ReadData, WriteData or DummyData activity is in progress - * - */ -static inline uint8_t hw_qspi_is_busy(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_is_busy(void) -{ - return (uint8_t) QSPIC->QSPIC_STATUS_REG; -} - -/** - * \brief Generate 32 bits read transfer on QSPI bus - * - * The data is transferred using the selected mode of the SPI bus (SPI, Dual - * SPI, Quad SPI). - * - * \return data read during read transfer - * - */ -static inline uint32_t hw_qspi_read32(void) __attribute__((always_inline)); - -static inline uint32_t hw_qspi_read32(void) -{ - return QSPIC->QSPIC_READDATA_REG; -} - -/** - * \brief Generate 16 bits read transfer on QSPI bus - * - * The data is transferred using the selected mode of the SPI bus (SPI, Dual - * SPI, Quad SPI). - * - * \return data read during read transfer - * - */ -static inline uint16_t hw_qspi_read16(void) __attribute__((always_inline)); - -static inline uint16_t hw_qspi_read16(void) -{ - return *((volatile uint16_t *) &(QSPIC->QSPIC_READDATA_REG)); -} - -/** - * \brief Generate 8 bits read transfer on QSPI bus - * - * The data is transferred using the selected mode of the SPI bus (SPI, Dual - * SPI, Quad SPI). - * - * \return data read during read transfer - * - */ -static inline uint8_t hw_qspi_read8(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_read8(void) -{ - return *((volatile uint8_t *) &(QSPIC->QSPIC_READDATA_REG)); -} - -/** - * \brief Generate 32 bits write transfer on QSPI bus - * - * The data is transferred using the selected mode of the SPI bus (SPI, Dual - * SPI, Quad SPI). - * - * param [in] data data to transfer - * - */ -static inline void hw_qspi_write32(uint32_t data) __attribute__((always_inline)); - -static inline void hw_qspi_write32(uint32_t data) -{ - QSPIC->QSPIC_WRITEDATA_REG = data; -} - -/** - * \brief Generate 16 bits write transfer on QSPI bus - * - * The data is transferred using the selected mode of the SPI bus (SPI, Dual - * SPI, Quad SPI). - * - * param [in] data data to transfer - * - */ -static inline void hw_qspi_write16(uint16_t data) __attribute__((always_inline)); - -static inline void hw_qspi_write16(uint16_t data) -{ - *((volatile uint16_t *) &(QSPIC->QSPIC_WRITEDATA_REG)) = data; -} - -/** - * \brief Generate 8 bits write transfer on QSPI bus - * - * The data is transferred using the selected mode of the SPI bus (SPI, Dual - * SPI, Quad SPI). - * - * param [in] data data to transfer - * - */ -static inline void hw_qspi_write8(uint8_t data) __attribute__((always_inline)); - -static inline void hw_qspi_write8(uint8_t data) -{ - *((volatile uint8_t *) &(QSPIC->QSPIC_WRITEDATA_REG)) = data; -} - -/** - * \brief Generate a clock pulses to the SPI bus for 32 bits transfer - * - * During this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. - * Number of pulses depends on selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). - * - */ -static inline void hw_qspi_dummy32(void) __attribute__((always_inline)); - -static inline void hw_qspi_dummy32(void) -{ - QSPIC->QSPIC_DUMMYDATA_REG = 0; -} - -/** - * \brief Generate a clock pulses to the SPI bus for 16 bits transfer - * - * During this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. - * Number of pulses depends on selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). - * - */ -static inline void hw_qspi_dummy16(void) __attribute__((always_inline)); - -static inline void hw_qspi_dummy16(void) -{ - *((volatile uint16_t *) &(QSPIC->QSPIC_DUMMYDATA_REG)) = 0; -} - -/** - * \brief Generate a clock pulses to the SPI bus for 8 bits transfer - * - * During this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. - * Number of pulses depends on selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). - * - */ -static inline void hw_qspi_dummy8(void) __attribute__((always_inline)); - -static inline void hw_qspi_dummy8(void) -{ - *((volatile uint8_t *) &(QSPIC->QSPIC_DUMMYDATA_REG)) = 0; -} - -/** - * \brief Specifies address with that flash memory uses - * - * The controller uses 32 of 24 bits for address during Auto mode transfer. - * - * \param [in] size selects 32 or 24 address size - * - */ -static inline void hw_qspi_set_address_size(HW_QSPI_ADDR_SIZE size) __attribute__((always_inline)); - -static inline void hw_qspi_set_address_size(HW_QSPI_ADDR_SIZE size) -{ - HW_QSPIC_REG_SETF(CTRLMODE, USE_32BA, (size == HW_QSPI_ADDR_SIZE_32 ? 1 : 0)); -} - -/** - * \brief Get address size that flash memory uses - * - * The controller uses 32 of 24 bits for address during Auto mode transfer. - * - * \return currently selected address size - * - * \sa hw_qspi_set_address_size - * - */ -static inline HW_QSPI_ADDR_SIZE hw_qspi_get_address_size(void) __attribute__((always_inline)); - -static inline HW_QSPI_ADDR_SIZE hw_qspi_get_address_size(void) -{ - return (HW_QSPI_ADDR_SIZE) HW_QSPIC_REG_GETF(CTRLMODE, USE_32BA); -} - -/** - * \brief Controls translation of burst accesses form AMBA bus to the QSPI bus - * - * \param [in] force 0 - controller translates a burst access on the AMBA bus - * to a burst access on the QSPI bus. That results to a minimum - * command/address phases, but the QSPI_CS is low for as - * long as the access occures, - * 1 - controller will split a burst access on the AMBA bus - * into single accesses on the qspi bus. This results to a separate - * read command to the FLASH memory foreach data - * required. A 4-beat word incremental AMBA access will be - * split into 4 different sequences of reading (command/address/ - * extra clock/read data). QSPI_CS will be only high while a qspi - * access occures. This results to lower power dissipation with - * respect to QSPIC_FORCENSEQ_EN=0 at cost of performance - * - */ -static inline void hw_qspi_force_nseq(uint8_t force) __attribute__((always_inline)); - -static inline void hw_qspi_force_nseq(uint8_t force) -{ - HW_QSPIC_REG_SETF(CTRLMODE, FORCENSEQ_EN, force); -} - -/** - * \brief Enable or disable auto mode on QSPI - * - * \note Selecting auto mode when any command previously configured has chosen - * QUAD mode for any phase will automatically configure pins IO2 and IO3 to input. - * - * \param [in] automode true auto mode selected, - * false manual mode selected - * - * \sa hw_qspi_set_read_instruction - * \sa hw_qspi_set_read_status_instruction - * \sa hw_qspi_set_suspend_resume_instructions - * \sa hw_qspi_set_write_enable_instruction - * \sa hw_qspi_set_extra_byte - * \sa hw_qspi_set_erase_instruction - * \sa hw_qspi_set_break_sequence - * - */ -void hw_qspi_set_automode(bool automode); - -/** - * \brief Read automode state - * - * \return true auto mode is selected, - * false manual mode is selected - * - */ -static inline bool hw_qspi_get_automode(void) __attribute__((always_inline)); - -static inline bool hw_qspi_get_automode(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, AUTO_MD); -} - -/** - * \brief Get read pipe clock delay - * - * \return read pipe clock delay relative to the falling edge of QSPI_SCK - * - */ -static inline uint8_t hw_qspi_get_read_pipe_clock_delay(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_get_read_pipe_clock_delay(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, PCLK_MD); -} - -/** - * \brief Set read pipe clock delay - * - * \param [in] delay read pipe clock delay relative to the falling edge of QSPI_SCK - * value should be in range 0..7 - * - */ -static inline void hw_qspi_set_read_pipe_clock_delay(uint8_t delay) __attribute__((always_inline)); - -static inline void hw_qspi_set_read_pipe_clock_delay(uint8_t delay) -{ - HW_QSPIC_REG_SETF(CTRLMODE, PCLK_MD, delay); -} - -/** - * \brief Check if read pipe is enabled - * - * \return 1 if read pipe is enabled, 0 otherwise - * - */ -static inline uint8_t hw_qspi_is_read_pipe_clock_enabled(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_is_read_pipe_clock_enabled(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, RPIPE_EN); -} - -/** - * \brief Enable read pipe - * - * \param [in] enable 1 enable read pipe, - * 0 disable read pipe - * - */ -static inline void hw_qspi_enable_readpipe(uint8_t enable) __attribute__((always_inline)); - -static inline void hw_qspi_enable_readpipe(uint8_t enable) -{ - HW_QSPIC_REG_SETF(CTRLMODE, RPIPE_EN, enable); -} - -/** - * \brief Get read sampling edge - * - * \return type of QSPI_CLK edge for sampling received data - * - */ -static inline HW_QSPI_SAMPLING_EDGE hw_qspi_get_read_sampling_edge(void) __attribute__((always_inline)); - -static inline HW_QSPI_SAMPLING_EDGE hw_qspi_get_read_sampling_edge(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, RXD_NEG); -} - -/** - * \brief Set read sampling edge - * - * \param [in] edge sets whether read samples or taken on rising or falling edge - * of QSPI_SCK - * - */ -static inline void hw_qspi_set_read_sampling_edge(HW_QSPI_SAMPLING_EDGE edge) __attribute__((always_inline)); - -static inline void hw_qspi_set_read_sampling_edge(HW_QSPI_SAMPLING_EDGE edge) -{ - HW_QSPIC_REG_SETF(CTRLMODE, RXD_NEG, edge); -} - -/** - * \brief Check if hready signal is used - * - * \return 0 - when wait states are not added via hready signal during access to - * QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers, - * 1 - when wait states are added via hready signal during access to - * QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. - * In this case read read QSPI_STATUS register to check the end of - * activity at the SPI bus - * - */ -static inline uint8_t hw_qspi_is_hready_enabled(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_is_hready_enabled(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, HRDY_MD); -} - -/** - * \brief Enable/disable adding wait states during register access - * - * \param [in] enable 0 - wait states will be added in hready signal during access to - * QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers - * - */ -static inline void hw_qspi_enable_hready(uint8_t enable) __attribute__((always_inline)); - -static inline void hw_qspi_enable_hready(uint8_t enable) -{ - HW_QSPIC_REG_SETF(CTRLMODE, HRDY_MD, enable); -} - -/** - * \brief Get clock mode - * - * \return 0 - SPI mode 0 is used for QSPI_CLK, the QSPI_SCK is low when QSPI_CS is high (idle), - * 1 - SPI mode 3 is used for QSPI_CLK, the QSPI_SCK is high when QSPI_CS is high (idle) - * - */ -static inline uint8_t hw_qspi_get_clock_mode(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_get_clock_mode(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, CLK_MD); -} - -/** - * \brief Set clock mode - * - * \param [in] mode HW_SPI_POL_LOW - SPI mode 0 is used for QSPI_CLK, - * The QSPI_SCK is low when QSPI_CS is high (idle), - * HW_SPI_POL_HIGH - SPI mode 3 is used for QSPI_CLK, - * The QSPI_SCK is high when QSPI_CS is high (idle) - * - */ -static inline void hw_qspi_set_clock_mode(HW_QSPI_POL mode) __attribute__((always_inline)); - -static inline void hw_qspi_set_clock_mode(HW_QSPI_POL mode) -{ - HW_QSPIC_REG_SETF(CTRLMODE, CLK_MD, mode); -} - -/** - * \brief Set IO2 direction - * - * \param [in] output QSPI_IO2 output enable. Use this only in SPI or Dual SPI - * mode to control /WP signal. When the Auto Mode is selected - * and the QUAD SPI is used, set this to false. - * false: The QSPI_IO2 pad is input - * true: The QSPI_IO2 pad is output - * - */ -#if (dg_configFLASH_POWER_DOWN == 1) -__attribute__((section("text_retained"))) -#endif -static inline void hw_qspi_set_io2_output(bool output) __attribute__((always_inline)); - -static inline void hw_qspi_set_io2_output(bool output) -{ - HW_QSPIC_REG_SETF(CTRLMODE, IO2_OEN, output); -} - -/** - * \brief Set IO3 direction - * - * \param [in] output Use this only in SPI or Dual SPI mode to control /HOLD signal. - * When the Auto Mode is selected and the QUAD SPI is used, - * set this to false. - * false: The QSPI_IO3 pad is input, - * true: The QSPI_IO3 pad is output - * - */ -#if (dg_configFLASH_POWER_DOWN == 1) -__attribute__((section("text_retained"))) -#endif -static inline void hw_qspi_set_io3_output(bool output) __attribute__((always_inline)); - -static inline void hw_qspi_set_io3_output(bool output) -{ - HW_QSPIC_REG_SETF(CTRLMODE, IO3_OEN, output); -} - -/** - * \brief Set state for IO2 when it's configured as output - * - * \param [in] val QSPI_IO2 value to set (0 or 1) - * - * \sa hw_qspi_set_io2_direction - * - */ -static inline void hw_qspi_set_io2(uint8_t val) __attribute__((always_inline)); - -static inline void hw_qspi_set_io2(uint8_t val) -{ - HW_QSPIC_REG_SETF(CTRLMODE, IO2_DAT, val); -} - -/** - * \brief Set state for IO3 when it's configured as output - * - * \param [in] val QSPI_IO3 value to set (0 or 1) - * - * \sa hw_qspi_set_io3_direction - * - */ -static inline void hw_qspi_set_io3(uint8_t val) __attribute__((always_inline)); - -static inline void hw_qspi_set_io3(uint8_t val) -{ - HW_QSPIC_REG_SETF(CTRLMODE, IO3_DAT, val); -} - -/** - * \brief Read state of IO2 when not in QUAD mode - * - * \return value of IO2 pin (0 or 1) - * - */ -static inline uint8_t hw_qspi_get_io2(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_get_io2(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, IO2_DAT); -} - -/** - * \brief Read state of IO3 when not in QUAD mode - * - * \return value of IO3 pin (0 or 1) - * - */ -static inline uint8_t hw_qspi_get_io3(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_get_io3(void) -{ - return HW_QSPIC_REG_GETF(CTRLMODE, IO3_DAT); -} - -/** - * \brief Set read instructions for QSPI flash - * - * This function sets up instruction to be sent to flash memory when data is requested - * on AHB bus. - * - * \param [in] inst instruction for Incremental Burst or Single read access. - * This value is the selected instruction at the cases of incremental - * burst or single read access. Also this value is used when a wrapping - * burst is not supported. - * \param [in] send_once 0 - transmit instruction at any burst access, - * 1 - transmit instruction only in the first access after the - * selection of Auto Mode. - * \param [in] dummy_count number of dummy bytes to send 0..4 - * \param [in] inst_phase describes the mode of the SPI bus during the instruction phase - * \param [in] addr_phase describes the mode of the SPI bus during the address phase - * \param [in] dummy_phase describes the mode of the SPI bus during the dummy phase - * \param [in] data_phase describes the mode of the SPI bus during the data phase - * - * \sa hw_qspi_set_extra_byte - * \sa hw_qspi_set_wrapping_burst_instruction - * - */ -static inline void hw_qspi_set_read_instruction(uint8_t inst, - uint8_t send_once, - uint8_t dummy_count, - HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, - HW_QSPI_BUS_MODE dummy_phase, - HW_QSPI_BUS_MODE data_phase) - __attribute((always_inline)); - -static inline void hw_qspi_set_read_instruction(uint8_t inst, - uint8_t send_once, - uint8_t dummy_count, - HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, - HW_QSPI_BUS_MODE dummy_phase, - HW_QSPI_BUS_MODE data_phase) -{ - QSPIC->QSPIC_BURSTCMDA_REG = - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST, inst) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST_TX_MD, inst_phase) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_ADR_TX_MD, addr_phase) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_DMY_TX_MD, dummy_phase); - - QSPIC->QSPIC_BURSTCMDB_REG = - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DAT_RX_MD, data_phase) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_INST_MD, send_once) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE, (dummy_count == 3 ? 1 : 0)) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, dummy_num[dummy_count]); -} - -/** - * \brief Set wrapping burst read instructions for QSPI flash - * - * Calling this function will set up wrapping burst instruction to use. - * Use this feature only when the serial FLASH memory supports a special - * instruction for wrapping burst access. - * - * \param [in] inst instruction for Wrapping Burst - * \param [in] len describes the selected length of a wrapping burst - * \param [in] size describes the selected data size of a wrapping burst - * - */ -void hw_qspi_set_wrapping_burst_instruction(uint8_t inst, HW_QSPI_WRAP_LEN len, - HW_QSPI_WRAP_SIZE size); - -/** - * \brief Set extra byte to use in read instruction - * - * \param [in] extra_byte the value of an extra byte which will be transferred after - * address. This byte is used for telling memory if it should stay - * in continuous read mode or wait for normal instruction after CS - * goes inactive - * \param [in] bus_mode describes the mode of the SPI bus during the extra byte phase. - * \param [in] half_disable_out 1 - disable (hi-z) output during the transmission - * of bits [3:0] of extra byte - * - * \sa hw_qspi_set_read_instruction - * - */ -static inline void hw_qspi_set_extra_byte(uint8_t extra_byte, HW_QSPI_BUS_MODE bus_mode, - uint8_t half_disable_out) __attribute__((always_inline)); - -static inline void hw_qspi_set_extra_byte(uint8_t extra_byte, HW_QSPI_BUS_MODE bus_mode, - uint8_t half_disable_out) -{ - QSPIC->QSPIC_BURSTCMDA_REG = - (QSPIC->QSPIC_BURSTCMDA_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD))) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE, extra_byte) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD, bus_mode); - - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN, 1) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS, half_disable_out ? 1 : 0); -} - -/** - * \brief Set dummy byte count - * - * Number of dummy bytes to send when read instruction is executed. - * - * \param [in] count number of dummy bytes to send 0..4 - * - */ -void hw_qspi_set_dummy_bytes_count(uint8_t count); - -/** - * \brief Set number of clock when CS stays high - * - * \param [in] clock_count between the transmission of two different instructions to the - * flash memory, the qspi bus stays in idle state (QSPI_CS high) - * for at least this number of spi clock cycles. See the QSPIC_ERS_CS_HI - * register for an exception - * - */ -static inline void hw_qspi_set_min_cs_high(uint8_t clock_count) __attribute__((always_inline)); - -static inline void hw_qspi_set_min_cs_high(uint8_t clock_count) -{ - HW_QSPIC_REG_SETF(BURSTCMDB, CS_HIGH_MIN, clock_count); -} - -/** - * \brief Set up erase instructions - * - * Instruction will be send after call to hw_qspi_erase_block. - * - * \param [in] inst code value of the erase instruction - * \param [in] inst_phase mode of the QSPI Bus during the instruction phase of the erase instruction - * \param [in] addr_phase the mode of the QSPI Bus during the address phase of the erase instruction - * \param [in] hclk_cycles the controller must stay without flash memory reading - * requests for this number of AMBA AHB hclk cycles, before - * performs the command of erase or resume 15 - 0 - * \param [in] cs_hi_cycles after the execution of instructions: write enable, erase, erase - * suspend and erase resume, the QSPI_CS remains high for at - * least this number of qspi bus clock cycles - * - * \sa hw_qspi_erase_block - * - */ -static inline void hw_qspi_set_erase_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, uint8_t hclk_cycles, uint8_t cs_hi_cycles) - __attribute__((always_inline)); - -static inline void hw_qspi_set_erase_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, uint8_t hclk_cycles, uint8_t cs_hi_cycles) -{ - HW_QSPIC_REG_SETF(ERASECMDA, ERS_INST, inst); - QSPIC->QSPIC_ERASECMDB_REG = - (QSPIC->QSPIC_ERASECMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_EAD_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERSRES_HLD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_CS_HI))) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_TX_MD, inst_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_EAD_TX_MD, addr_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERSRES_HLD, hclk_cycles) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_CS_HI, cs_hi_cycles); -} - -/** - * \brief Set up write enable instruction - * - * Instruction setup by this function will be executed before erase. - * - * \param [in] write_enable code value of the write enable instruction - * \param [in] inst_phase mode of the QSPI Bus during the instruction phase - * - * \sa hw_qspi_erase_block - * \sa hw_qspi_set_erase_instruction - * - */ -static inline void hw_qspi_set_write_enable_instruction(uint8_t write_enable, - HW_QSPI_BUS_MODE inst_phase) - __attribute((always_inline)); - -static inline void hw_qspi_set_write_enable_instruction(uint8_t write_enable, - HW_QSPI_BUS_MODE inst_phase) -{ - HW_QSPIC_REG_SETF(ERASECMDA, WEN_INST, write_enable); - HW_QSPIC_REG_SETF(ERASECMDB, WEN_TX_MD, inst_phase); -} - -/** - * \brief Set up erase suspend/resume instructions - * - * \param [in] erase_suspend_inst code value of the erase suspend instruction. - * \param [in] suspend_inst_phase mode of the QSPI Bus during the instruction phase - * of the suspend instruction - * \param [in] erase_resume_inst code value of the erase resume instruction. - * \param [in] resume_inst_phase mode of the QSPI Bus during the instruction phase - * of the resume instruction - * \param [in] minimum_delay defines the minimum time distance between the instruction - * erase suspend and the previous instruction erase resume. - * This delay will be also applied after the Erase command. - * 0 - don't wait. The controller starts the erase suspend procedure - * immediately, - * 1..63 - controller waits at least this number of 288kHz clock cycles - * before the suspension of erasing. Time starts counting after - * the end of the previous erase resume - * - */ -static inline void hw_qspi_set_suspend_resume_instructions(uint8_t erase_suspend_inst, - HW_QSPI_BUS_MODE suspend_inst_phase, - uint8_t erase_resume_inst, - HW_QSPI_BUS_MODE resume_inst_phase, - uint8_t minimum_delay) - __attribute((always_inline)); - -static inline void hw_qspi_set_suspend_resume_instructions(uint8_t erase_suspend_inst, - HW_QSPI_BUS_MODE suspend_inst_phase, - uint8_t erase_resume_inst, - HW_QSPI_BUS_MODE resume_inst_phase, - uint8_t minimum_delay) -{ - QSPIC->QSPIC_ERASECMDA_REG = - (QSPIC->QSPIC_ERASECMDA_REG & - ~(REG_MSK(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_SUS_INST) | - REG_MSK(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_RES_INST))) | - BITS32(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_SUS_INST, erase_suspend_inst) | - BITS32(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_RES_INST, erase_resume_inst); - QSPIC->QSPIC_ERASECMDB_REG = - (QSPIC->QSPIC_ERASECMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_SUS_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RES_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RESSUS_DLY))) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_SUS_TX_MD, suspend_inst_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RES_TX_MD, resume_inst_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RESSUS_DLY, minimum_delay); -} - -/** - * \brief Set status command - * - * This command will be send by QSPI controller when it needs to check status of flash memory. - * This command is also send indirectly when hw_qspi_get_erase_status is called. - * - * \param [in] inst instruction for read status - * \param [in] inst_phase mode of the QSPI Bus during the instruction phase of the read - * status instruction - * \param [in] receive_phase mode of the QSPI Bus during the receive status phase of - * the read status instruction - * \param [in] busy_pos it describes which bit from the bits of status represents - * the Busy bit (7 - 0) - * \param [in] busy_val defines the value of the Busy bit which means that the flash is busy - * 0 - flash is busy when the Busy bit is equal to 0, - * 1 - flash is busy when the Busy bit is equal to 1 - * \param [in] read_delay defines the minimum time distance between the instruction - * read status register and previous instructions like erase or - * resume. The same delay will be also applied after the Erase command. - * 0 - don't wait. The controller starts to read the Flash memory - * status register immediately. - * 1..63 - controller waits at least the number of QSPI_CLK - * cycles and afterwards it starts to read the Flash memory status - * register. Time starts counting after the end of the previous - * erase/resume. - * \param [in] sts_delay defines the register to count the delay to wait for the FLASH Status - * Register read after an erase or erase/ resume command. - * 0 - delay is controlled by the \p read_dealy (QSPIC_RESSTS_DLY) - * which counts on the qspi clock, - * 1 - delay is controlled by the \p minimum_delay value passed to - * hw_qspi_set_suspend_resume_instructions (QSPIC_RESSUS_DLY) which - * counts on the 288 kHz clock - * - * \sa hw_qspi_set_suspend_resume_instructions - * \sa hw_qspi_get_erase_status - * - */ -static inline void hw_qspi_set_read_status_instruction(uint8_t inst, - HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE receive_phase, - uint8_t busy_pos, - uint8_t busy_val, - uint8_t read_delay, - uint8_t sts_delay) - __attribute((always_inline)); - -static inline void hw_qspi_set_read_status_instruction(uint8_t inst, - HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE receive_phase, - uint8_t busy_pos, - uint8_t busy_val, - uint8_t read_delay, - uint8_t sts_delay) -{ - QSPIC->QSPIC_STATUSCMD_REG = - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_VAL, busy_val) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_POS , busy_pos) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_RX_MD, receive_phase) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_TX_MD, inst_phase) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_INST, inst) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_STSDLY_SEL, sts_delay) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RESSTS_DLY, read_delay); -} - -/** - * \brief Erase block/sector of flash memory - * - * For this function to work, erase instructions must be set up - * with hw_qspi_set_erase_instruction. - * User should call hw_qspi_get_erase_status to check if block erased. - * - * \note If user doesn't call hw_qspi_get_erase_status that returns status 0 - * QSPI controller will not be able to switch to manual mode. - * - * \param [in] addr memory address of block/sector thats is requested to be erased - * for 24 bits addressing, bits [23:12] determine the block/sector - * address bits. Bits [11:0] are ignored by the controller. - * For 32 bits addressing, bits [31:12] determine the block/sectors - * address bits. Bits [11:0] are ignored by the controller - * - * \sa hw_qspi_set_erase_instruction - * \sa hw_qspi_get_erase_status - * \sa hw_qspi_set_automode - * - */ -void hw_qspi_erase_block(uint32_t addr); - -/** - * \brief Get erase status - * - * \return progress of sector/block erasing - * 0 = no erase, - * 1 = pending erase request, - * 2 = erase procedure is running, - * 3 = suspended erase procedure, - * 4 = finishing the erase procedure - * - */ -static inline uint8_t hw_qspi_get_erase_status(void) __attribute__((always_inline)); - -static inline uint8_t hw_qspi_get_erase_status(void) -{ - QSPIC->QSPIC_CHCKERASE_REG = 0; - return HW_QSPIC_REG_GETF(ERASECTRL, ERS_STATE); -} - -/** - * \brief Set burst break sequence - * - * \param [in] sequence value will be transmitted as the burst break sequence - * \param [in] mode mode of the QSPI Bus during the transmission of the burst break sequence - * \param [in] size size of Burst Break Sequence - * \param [in] dis_out disable output during the transmission of the second half (sequence[3:0]). - * Setting this bit is only useful if size = 1. - * 0 - controller drives the QSPI bus during the transmission - * of the sequence[3:0], - * 1 - controller leaves the QSPI bus in Hi-Z during the transmission - * of the sequence[3:0] - * - */ -static inline void hw_qspi_set_break_sequence(uint16_t sequence, HW_QSPI_BUS_MODE mode, - HW_QSPI_BREAK_SEQ_SIZE size, uint8_t dis_out) - __attribute__((always_inline)); - -static inline void hw_qspi_set_break_sequence(uint16_t sequence, HW_QSPI_BUS_MODE mode, - HW_QSPI_BREAK_SEQ_SIZE size, uint8_t dis_out) -{ - QSPIC->QSPIC_BURSTBRK_REG = - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_SEC_HF_DS, dis_out) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_SZ, size) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_TX_MD, mode) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_EN, 1) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_WRD, sequence); -} - -/** - * \brief Disable burst break sequence - * - */ -static inline void hw_qspi_disable_burst_break_sequence(void) __attribute__((always_inline)); - -static inline void hw_qspi_disable_burst_break_sequence(void) -{ - HW_QSPIC_REG_SETF(BURSTBRK, BRK_EN, 0); -} - -/** - * \brief Set configuration of QSPI pads - * - * \param [in] rate QSPI pads slew rate control - * \param [in] current QSPI pads drive current - * - */ -void hw_qspi_set_pads(HW_QSPI_SLEW_RATE rate, HW_QSPI_DRIVE_CURRENT current); - -/** - * \brief QSPI controller initialization - * - * This function will enable QSPI controller in manual mode. - * - * \note This function doesn't change QSPI_DIV - * - */ -void hw_qspi_init(const qspi_config *cfg); - -/** - * \brief Enable QSPI controller clock - * - */ -static inline void hw_qspi_enable_clock(void) __attribute__((always_inline)); - -static inline void hw_qspi_enable_clock(void) -{ - GLOBAL_INT_DISABLE(); - CRG_TOP->CLK_AMBA_REG |= 1 << REG_POS(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Disable QSPI controller clock - * - */ -static inline void hw_qspi_disable_clock(void) __attribute__((always_inline)); - -static inline void hw_qspi_disable_clock(void) -{ - GLOBAL_INT_DISABLE(); - CRG_TOP->CLK_AMBA_REG &= ~REG_MSK(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Set the QSPI clock divider - * - * \param [in] div QSPI clock divider - * - * \sa HW_QSPI_DIV - */ -static inline void hw_qspi_set_div(HW_QSPI_DIV div) __attribute__((always_inline)); - -static inline void hw_qspi_set_div(HW_QSPI_DIV div) -{ - GLOBAL_INT_DISABLE(); - REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, div); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Get the QSPI clock divider - * - * \return the QSPI clock divider setting - * - * \sa HW_QSPI_DIV - */ -static inline HW_QSPI_DIV hw_qspi_get_div(void) __attribute__((always_inline)); - -static inline HW_QSPI_DIV hw_qspi_get_div(void) -{ - return REG_GETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV); -} - -#endif /* dg_configUSE_HW_QSPI */ - -#endif /* HW_QSPI_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h deleted file mode 100644 index 7a6a64e85..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h +++ /dev/null @@ -1,331 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup RF - * \{ - * \brief Radio Control - */ - -/** - ***************************************************************************************** - * - * @file hw_rf.h - * - * @brief Radio module (RF) Low Level Driver API. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_RF_H_ -#define HW_RF_H_ - -#if dg_configUSE_HW_RF - -#include -#include "sdk_defs.h" - -#include "hw_cpm.h" - -#if dg_configFEM == FEM_SKY66112_11 -#include "hw_fem_sky66112-11.h" -#endif - -typedef struct __attribute__ ((__packed__)) { - uint8_t tx_power_ble: 4; - uint8_t tx_power_ftdf: 4; -} hw_rf_tx_power_luts_t; - -extern hw_rf_tx_power_luts_t rf_tx_power_luts; - -/** - * \brief Power LUT setting - * - */ -typedef enum { - HW_RF_PWR_LUT_0dbm = 0, /**< TX PWR attenuation 0 dbm */ - HW_RF_PWR_LUT_m1dbm = 1, /**< TX PWR attenuation -1 dbm */ - HW_RF_PWR_LUT_m2dbm = 2, /**< TX PWR attenuation -2 dbm */ - HW_RF_PWR_LUT_m3dbm = 3, /**< TX PWR attenuation -3 dbm */ - HW_RF_PWR_LUT_m4dbm = 4, /**< TX PWR attenuation -4 dbm */ -} HW_RF_PWR_LUT_SETTING; - -/** - * \brief Initializes RF system, and performs the initial calibration - * - * \note The RF PD must be on before this is called - * - * \return True, if iff calib is successful, false otherwise - */ -bool hw_rf_system_init(void); - -/** - * \brief Sets parameters according to their recommended values. - */ -void hw_rf_set_recommended_settings(void); - -/** - * \brief (Re)calibrates RF DC offset. - */ -void hw_rf_dc_offset_calibration(void); - -/** - * \brief (Re)calibrates modulation gain. - */ -void hw_rf_modulation_gain_calibration(bool); - -/** - * \brief Convenience function to (re)calibrate all RF related modules. - * - * \return True if calibration (specifically, the iff calibration part) - * succeeds, false if not - */ -bool hw_rf_calibration(void); - -/** - * \brief Start Calibration procedure and return. - * - * This will block for some time in order to perform - * the first part of calibration (IFF, DC offset and the start of gain calib). - * Interrupts must be disabled by the caller. - * - * \return True if calibration was successful, false if not (i.e. iff calib hang) - * - */ -bool hw_rf_start_calibration(void); - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -/** - * \brief Set TX Power - * - * This actually sets the index of the RF_TX_PWER_LUT_X_REG to use. - * - * \param [in] lut The TX power attenuation setting - * - * \warning Do not call this function before recommended settings are applied - */ -void hw_rf_set_tx_power(HW_RF_PWR_LUT_SETTING lut); -#else - -#ifdef CONFIG_USE_BLE -/** - * \brief Set TX Power for BLE - * - * This actually sets the index of the RF_TX_PWR_LUT_X_REG to use. - * - * \param [in] lut The TX power attenuation setting - * - * \warning Do not call this function before recommended settings are applied - */ -void hw_rf_set_tx_power_ble(HW_RF_PWR_LUT_SETTING lut); -#endif - -#ifdef CONFIG_USE_FTDF -/** - * \brief Set TX Power for FTDF - * - * This actually sets the index of the RF_TX_PWR_LUT_X_REG to use. - * - * \param [in] lut The TX power attenuation setting - * - * \warning Do not call this function before recommended settings are applied - */ -void hw_rf_set_tx_power_ftdf(HW_RF_PWR_LUT_SETTING lut); -#endif - -/** - * \brief Set TX Power - * - * This actually sets the index of the RF_TX_PWR_LUT_X_REG to use. - * - * \param [in] lut The TX power attenuation setting - * - * \deprecated This function is deprecated since it can only set - * BLE and FTDF TX power with the same value. Use hw_rf_set_tx_power_ble() - * and hw_rf_set_tx_power_ftdf() instead. - * - * \warning Do not call this function before recommended settings are applied - */ -static inline void hw_rf_set_tx_power(HW_RF_PWR_LUT_SETTING lut) -{ -#ifdef CONFIG_USE_BLE - hw_rf_set_tx_power_ble(lut); -#endif -#ifdef CONFIG_USE_FTDF - hw_rf_set_tx_power_ftdf(lut); -#endif -} -#endif - -/** - * \brief Turns on RF module. - */ -static inline void hw_rf_poweron(void) __attribute__((always_inline)); - -static inline void hw_rf_poweron(void) -{ - if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { - hw_cpm_deactivate_bod_protection(); - } - - /* If PD_RAD is up, make sure to power it down to issue a reset */ - if (REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_UP)) { - if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { - hw_cpm_delay_usec(30); - } - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); - GLOBAL_INT_RESTORE(); - while (REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_DOWN) == 0x0); - } - - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); - GLOBAL_INT_RESTORE(); - while (!REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_UP)); - - if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { - hw_cpm_delay_usec(30); - hw_cpm_activate_bod_protection(); - } - - // Enable the PLLdig/RFCU clock - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, RFCU_ENABLE); - REG_SETF(CRG_TOP, CLK_RADIO_REG, RFCU_DIV, 1); - GLOBAL_INT_RESTORE(); - -#if dg_configFEM == FEM_SKY66112_11 - hw_fem_start(); -#endif -} - -/** - * \brief Turns off RF module. - */ -static inline void hw_rf_poweroff() -{ -#if dg_configFEM == FEM_SKY66112_11 - hw_fem_stop(); -#endif - - if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { - hw_cpm_deactivate_bod_protection(); - hw_cpm_delay_usec(30); - } - - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); - GLOBAL_INT_RESTORE(); - while (!REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_DOWN)); - - if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { - hw_cpm_delay_usec(30); - hw_cpm_activate_bod_protection(); - } -} - -/** - * \brief Sets parameters according to their recommended values, taking RF state into account. - * - * Acts like \ref hw_rf_set_recommended_settings but makes sure that the RF power domain is on and - * unconfigured. - * Interrupts must be disabled by the caller. - * - */ -void hw_rf_request_recommended_settings(void); - -/** - * \brief Requests that the RF is turned on - * - * Requests that the RF is turned on, if not already on. - * Interrupts must be disabled by the caller. - * - * \param [in] mode_ble True, if the rf is needed for ble - */ -__RETAINED_CODE void hw_rf_request_on(bool mode_ble); - -/** - * \brief Requests that the RF is turned off - * - * Requests that the RF is turned off, if not already off. - * The RF will be turned off only if there are no more - * requests (ie. all requesters have called hw_rf_request_off()) - * Interrupts must be disabled by the caller. - * - * \param [in] mode_ble True, if the rf was needed for ble - */ -void hw_rf_request_off(bool mode_ble); - -/** - * \brief Start transmitting a continuous wave (unmodulated transmission) - * - * \param [in] mode is the mode to use. 1: BLE, 2 or 3: FTDF (0: Normal, use hw_rf_stop_*) - * - * \param [in] ch is the Channel to transmit on, calculated as: - * (mode is BLE) ch = (F – 2402) / 2, where F ranges from 2402 MHz to 2480 MHz. - * Range: 0x00 – 0x27. - * (mode is FTDF) ch = (F – 2405) / 5, where F ranges from 2405 MHz to 2480 MHz. - * Range: 0x00 – 0xf. - */ -void hw_rf_start_continuous_wave(uint8_t mode, uint8_t ch); - -/** - * \brief Start reception of a continuous wave (unmodulated reception) - * - * \param [in] mode is the mode to use. 1: BLE, 2 or 3: FTDF (0: Normal, use hw_rf_stop_*) - * - * \param [in] ch is the Channel to receive on, calculated as: - * (mode is BLE) ch = (F – 2402) / 2, where F ranges from 2402 MHz to 2480 MHz. - * Range: 0x00 – 0x27. - * (mode is FTDF) ch = (F – 2405) / 5, where F ranges from 2405 MHz to 2480 MHz. - * Range: 0x00 – 0xf. - */ -void hw_rf_start_continuous_wave_rx(uint8_t mode, uint8_t ch); - -/** - * \brief Stop transmitting a continuous wave (unmodulated transmission) - * - */ -void hw_rf_stop_continuous_wave(void); - -#endif /* dg_configUSE_HW_RF */ - -#endif /* HW_RF_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer0.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer0.h deleted file mode 100644 index c5dc23a56..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer0.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup Timer0 - * \{ - * \brief Timer0 - */ - -/** - ***************************************************************************************** - * - * @file hw_timer0.h - * - * @brief Definition of API for the Timer0 Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_TIMER0_H_ -#define HW_TIMER0_H_ - -#if dg_configUSE_HW_TIMER0 - -#include -#include -#include - - -/** - * \brief Get the mask of a field of an TIMER0 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_TIMER0_REG_FIELD_MASK(reg, field) \ - (GP_TIMERS_TIMER0_##reg##_REG_##field##_Msk) - -/** - * \brief Get the bit position of a field of an TIMER0 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_TIMER0_REG_FIELD_POS(reg, field) \ - (GP_TIMERS_TIMER0_##reg##_REG_##field##_Pos) - -/** - * \brief Get the value of a field of an TIMER0 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * - * \return the value of the register field - * - */ -#define HW_TIMER0_REG_GETF(reg, field) \ - ((GP_TIMERS->TIMER0_##reg##_REG & (GP_TIMERS_TIMER0_##reg##_REG_##field##_Msk)) >> (GP_TIMERS_TIMER0_##reg##_REG_##field##_Pos)) - -/** - * \brief Set the value of a field of an TIMER0 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * \param [in] new_val is the value to write - * - */ -#define HW_TIMER0_REG_SETF(reg, field, new_val) \ - GP_TIMERS->TIMER0_##reg##_REG = ((GP_TIMERS->TIMER0_##reg##_REG & ~(GP_TIMERS_TIMER0_##reg##_REG_##field##_Msk)) | \ - ((GP_TIMERS_TIMER0_##reg##_REG_##field##_Msk) & ((new_val) << (GP_TIMERS_TIMER0_##reg##_REG_##field##_Pos)))) - - -/** - * \brief Clock source for timer - * - */ -typedef enum { - HW_TIMER0_CLK_SRC_SLOW = 0, /**< 32kHz (slow) clock */ - HW_TIMER0_CLK_SRC_FAST = 1 /**< 2/4/8/16MHz (fast) clock */ -} HW_TIMER0_CLK_SRC; - -/** - * \brief Fast clock division factor - * - */ -typedef enum { - HW_TIMER0_FAST_CLK_DIV_1 = 0, /**< divide by 1 */ - HW_TIMER0_FAST_CLK_DIV_2, /**< divide by 2 */ - HW_TIMER0_FAST_CLK_DIV_4, /**< divide by 4 */ - HW_TIMER0_FAST_CLK_DIV_8, /**< divide by 8 */ -} HW_TIMER0_FAST_CLK_DIV; - -/** - * \brief PWM mode - * - */ -typedef enum { - HW_TIMER0_MODE_PWM = 0, /**< PWM signal is '1' during high state */ - HW_TIMER0_MODE_CLOCK = 1 /**< PWM signal is clock divided by 2 during high state */ -} HW_TIMER0_MODE; - -/** - * \brief Timer interrupt callback - * - */ -typedef void (*hw_timer0_interrupt_cb)(void); - -/* - * \brief Timer configuration - * - */ -typedef struct { - HW_TIMER0_CLK_SRC clk_src; /**< clock source */ - HW_TIMER0_FAST_CLK_DIV fast_clk_div; /**< clock division factor (only applicable when fast clock is selected as source) */ - bool on_clock_div; /**< enable ON-counter clock divider (clock for ON-counter is divided by 10) */ - uint16_t on_reload; /**< reload value for ON-counter */ - uint16_t t0_reload_m; /**< reload value for T0-counter M-register */ - uint16_t t0_reload_n; /**< reload value for T0-counter N-register */ -} timer0_config; - -/** - * \brief Initialize the timer - * - * Turn on clock for timer and configure timer. After initialization both timer and its interrupt - * are disabled. \p cfg can be NULL - no configuration is performed in such case. - * - * \param [in] cfg configuration - * - */ -void hw_timer0_init(const timer0_config *cfg); - -/** - * \brief Timer configuration - * - * Shortcut to call appropriate configuration function. If \p cfg is NULL, this function does - * nothing. - * - * \param [in] cfg configuration - * - */ -void hw_timer0_configure(const timer0_config *cfg); - -/** - * \brief Register an interrupt handler - * - * \param [in] handler Function pointer to call when timer interrupt occurs - * - */ -void hw_timer0_register_int(hw_timer0_interrupt_cb handler); - -/** - * \brief Unregister an interrupt handler - * - */ -void hw_timer0_unregister_int(void); - -/** - * \brief Enable the timer - * - */ -static inline void hw_timer0_enable(void) -{ - HW_TIMER0_REG_SETF(CTRL, TIM0_CTRL, 1); -} - -/** - * \brief Disable the timer - * - */ -static inline void hw_timer0_disable(void) -{ - HW_TIMER0_REG_SETF(CTRL, TIM0_CTRL, 0); -} - -/** - * \brief Set clock source for timer - * - * \param [in] clk_src clock source - * - * \sa TIMER0_CLK_SRC - * - */ -static inline void hw_timer0_set_clock_source(HW_TIMER0_CLK_SRC clk_src) -{ - HW_TIMER0_REG_SETF(CTRL, TIM0_CLK_SEL, clk_src); -} - -/** - * \brief Get current clock source for timer - * - * \return clock source - * - */ -static inline HW_TIMER0_CLK_SRC hw_timer0_get_clock_source(void) -{ - return HW_TIMER0_REG_GETF(CTRL, TIM0_CLK_SEL); -} - -/** - * \brief Set fast clock division factor - * - * \param [in] div division factor - * - * \sa TIMER0_FAST_CLK_DIV - * - */ -static inline void hw_timer0_set_fast_clock_div(HW_TIMER0_FAST_CLK_DIV div) -{ - GLOBAL_INT_DISABLE(); - REG_SETF(CRG_TOP, CLK_TMR_REG, TMR0_DIV, div); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Get current fast clock division factor - * - * \return division factor - * - */ -static inline HW_TIMER0_FAST_CLK_DIV hw_timer0_get_fast_clock_div(void) -{ - return REG_GETF(CRG_TOP, CLK_TMR_REG, TMR0_DIV); -} - -/** - * \brief Set state of clock divider for ON-counter - * - * Once enabled, ON-counter clock will be divided by 10. - * - * \param [in] enabled clock divider status - * - */ -static inline void hw_timer0_set_on_clock_div(bool enabled) -{ - HW_TIMER0_REG_SETF(CTRL, TIM0_CLK_DIV, !enabled); -} - -/** - * \brief Get current state of clock divider for ON-counter - * - * \return clock divider status - * - */ -static inline bool hw_timer0_get_on_clock_div(void) -{ - return !HW_TIMER0_REG_GETF(CTRL, TIM0_CLK_DIV); -} - -/** - * \brief Set PWM mode for timer - * - * \param [in] mode PWM mode - * - * \sa TIMER0_MODE - * - */ -static inline void hw_timer0_set_pwm_mode(HW_TIMER0_MODE mode) -{ - HW_TIMER0_REG_SETF(CTRL, PWM_MODE, mode); -} - -/** - * \brief Get current PWM mode for timer - * - * \return PWM mode - * - */ -static inline HW_TIMER0_MODE hw_timer0_get_pwm_mode(void) -{ - return HW_TIMER0_REG_GETF(CTRL, PWM_MODE); -} - -/** - * \brief Set reload value for T0-counter - * - * T0 counter value is decremented on each clock cycle. At the beginning it's loaded from M-register - * and then, once reached zero, loaded from N-register (and then M and N again). - * - * PWM0 is high when counting down M-register and low when counting down N-register. - * For PWM1 is the opposite. - * - * \param [in] m_value M-register reload value - * \param [in] n_value N-register reload value - * - */ -static inline void hw_timer0_set_t0_reload(uint16_t m_value, uint16_t n_value) -{ - GP_TIMERS->TIMER0_RELOAD_M_REG = m_value; - GP_TIMERS->TIMER0_RELOAD_N_REG = n_value; -} - -/** - * \brief Set reload value for ON-counter - * - * ON counter value is decremented on each clock cycle. Once ON reaches zero it will remain zero - * until T0 counter completes decrementing N-register value. When this happens, interrupt is - * generated. - * - * \param [in] value reload value - * - * \sa hw_timer0_set_on_clock_div - * - */ -static inline void hw_timer0_set_on_reload(uint16_t value) -{ - GP_TIMERS->TIMER0_ON_REG = value; -} - -/** - * \brief Get T0-counter value - * - * \return counter value - * - */ -static inline uint16_t hw_timer0_get_t0(void) -{ - return (GP_TIMERS->TIMER0_RELOAD_M_REG); -} - -/** - * \brief Get ON-counter value - * - * \return counter value - * - */ -static inline uint16_t hw_timer0_get_on(void) -{ - return (GP_TIMERS->TIMER0_ON_REG); -} - -/** - * \brief Freeze timer - * - */ -static inline void hw_timer0_freeze(void) -{ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Msk; -} - -/** - * \brief Unfreeze timer - * - */ -static inline void hw_timer0_unfreeze(void) -{ - GPREG->RESET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Msk; -} - -#endif /* dg_configUSE_HW_TIMER0 */ - -#endif /* HW_TIMER0_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer1.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer1.h deleted file mode 100644 index 3a56baaa7..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer1.h +++ /dev/null @@ -1,1052 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup Timer1 - * \{ - * \brief Timer1 - */ - -/** - ***************************************************************************************** - * - * @file hw_timer1.h - * - * @brief Definition of API for the Timer1 Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_TIMER1_H_ -#define HW_TIMER1_H_ - -#if dg_configUSE_HW_TIMER1 - -#include -#include -#include - - -/** - * \brief Get the mask of a field of an TIMER1 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_TIMER1_REG_FIELD_MASK(reg, field) \ - (TIMER1_CAPTIM_##reg##_REG_##field##_Msk) - -/** - * \brief Get the bit position of a field of an TIMER1 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_TIMER1_REG_FIELD_POS(reg, field) \ - (TIMER1_CAPTIM_##reg##_REG_##field##_Pos) - -/** - * \brief Get the value of a field of an TIMER1 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * - * \return the value of the register field - * - */ -#define HW_TIMER1_REG_GETF(reg, field) \ - ((TIMER1->CAPTIM_##reg##_REG & (TIMER1_CAPTIM_##reg##_REG_##field##_Msk)) >> (TIMER1_CAPTIM_##reg##_REG_##field##_Pos)) - -/** - * \brief Set the value of a field of an TIMER1 register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * \param [in] new_val is the value to write - * - */ -#define HW_TIMER1_REG_SETF(reg, field, new_val) \ - TIMER1->CAPTIM_##reg##_REG = ((TIMER1->CAPTIM_##reg##_REG & ~(TIMER1_CAPTIM_##reg##_REG_##field##_Msk)) | \ - ((TIMER1_CAPTIM_##reg##_REG_##field##_Msk) & ((new_val) << (TIMER1_CAPTIM_##reg##_REG_##field##_Pos)))) - - -#define EXT_CLK 16 // 16 MHz -#define INT_CLK 32 // 32 kHz - -/** - * \brief Mode of operation - * - * PWM is enabled in both modes. - * - */ -typedef enum { - HW_TIMER1_MODE_TIMER = 0, /**< timer/capture mode */ - HW_TIMER1_MODE_ONESHOT = 1 /**< one-shot mode */ -} HW_TIMER1_MODE; - -/** - * \brief Clock source for timer - * - */ -typedef enum { - HW_TIMER1_CLK_SRC_INT = 0, /**< Internal clock 32 kHz (slow) */ - HW_TIMER1_CLK_SRC_EXT = 1 /**< External clock 2/4/8/16 MHz (fast) */ -} HW_TIMER1_CLK_SRC; - -/** - * \brief Counting direction - * - */ -typedef enum { - HW_TIMER1_DIR_UP = 0, /**< Timer counts up (counter is incremented) */ - HW_TIMER1_DIR_DOWN = 1 /**< Timer counts down (counter is decremented) */ -} HW_TIMER1_DIR; - -/** - * \brief Type of triggering events - * - */ -typedef enum { - HW_TIMER1_TRIGGER_RISING = 0, /**< Event activated rising edge */ - HW_TIMER1_TRIGGER_FALLING = 1 /**< Event activated falling edge */ -} HW_TIMER1_TRIGGER; - -/** - * \brief One shot mode phases - * - */ -typedef enum { - HW_TIMER1_ONESHOT_WAIT = 0, /**< Wait for the event */ - HW_TIMER1_ONESHOT_DELAY = 1, /**< Delay before started */ - HW_TIMER1_ONESHOT_STARTED = 2, /**< Start shot */ - HW_TIMER1_ONESHOT_ACTIVE = 3 /**< Shot is active */ -} HW_TIMER1_ONESHOT; - -/** - * \brief GPIOs for timer1 - * - * Mainly use for mark which GPIO will triggers timer counting. - * - */ -typedef enum { - HW_TIMER1_GPIO_NONE = 0, /**< None of GPIO */ - /* port 0 */ - HW_TIMER1_GPIO_P00 = 1, /**< Port 0, pin 0 */ - HW_TIMER1_GPIO_P01 = 2, /**< Port 0, pin 1 */ - HW_TIMER1_GPIO_P02 = 3, /**< Port 0, pin 2 */ - HW_TIMER1_GPIO_P03 = 4, /**< Port 0, pin 3 */ - HW_TIMER1_GPIO_P04 = 5, /**< Port 0, pin 4 */ - HW_TIMER1_GPIO_P05 = 6, /**< Port 0, pin 5 */ - HW_TIMER1_GPIO_P06 = 7, /**< Port 0, pin 6 */ - HW_TIMER1_GPIO_P07 = 8, /**< Port 0, pin 7 */ - /* port 1 */ - HW_TIMER1_GPIO_P10 = 9, /**< Port 1, pin 0 */ - HW_TIMER1_GPIO_P11 = 10, /**< Port 1, pin 1 */ - HW_TIMER1_GPIO_P12 = 11, /**< Port 1, pin 2 */ - HW_TIMER1_GPIO_P13 = 12, /**< Port 1, pin 3 */ - HW_TIMER1_GPIO_P14 = 13, /**< Port 1, pin 4 */ - HW_TIMER1_GPIO_P15 = 14, /**< Port 1, pin 5 */ - HW_TIMER1_GPIO_P16 = 15, /**< Port 1, pin 6 */ - HW_TIMER1_GPIO_P17 = 16, /**< Port 1, pin 7 */ - /* port 2 */ - HW_TIMER1_GPIO_P20 = 17, /**< Port 2, pin 0 */ - HW_TIMER1_GPIO_P21 = 18, /**< Port 2, pin 1 */ - HW_TIMER1_GPIO_P22 = 19, /**< Port 2, pin 2 */ - HW_TIMER1_GPIO_P23 = 20, /**< Port 2, pin 3 */ - HW_TIMER1_GPIO_P24 = 21, /**< Port 2, pin 4 */ - /* port 3 */ - HW_TIMER1_GPIO_P30 = 22, /**< Port 3, pin 0 */ - HW_TIMER1_GPIO_P31 = 23, /**< Port 3, pin 1 */ - HW_TIMER1_GPIO_P32 = 24, /**< Port 3, pin 2 */ - HW_TIMER1_GPIO_P33 = 25, /**< Port 3, pin 3 */ - HW_TIMER1_GPIO_P34 = 26, /**< Port 3, pin 4 */ - HW_TIMER1_GPIO_P35 = 27, /**< Port 3, pin 5 */ - HW_TIMER1_GPIO_P36 = 28, /**< Port 3, pin 6 */ - HW_TIMER1_GPIO_P37 = 29, /**< Port 3, pin 7 */ - /* port 4 */ - HW_TIMER1_GPIO_P40 = 30, /**< Port 4, pin 0 */ - HW_TIMER1_GPIO_P41 = 31, /**< Port 4, pin 1 */ - HW_TIMER1_GPIO_P42 = 32, /**< Port 4, pin 2 */ - HW_TIMER1_GPIO_P43 = 33, /**< Port 4, pin 3 */ - HW_TIMER1_GPIO_P44 = 34, /**< Port 4, pin 4 */ - HW_TIMER1_GPIO_P45 = 35, /**< Port 4, pin 5 */ - HW_TIMER1_GPIO_P46 = 36, /**< Port 4, pin 6 */ - HW_TIMER1_GPIO_P47 = 37, /**< Port 4, pin 7 */ -} HW_TIMER1_GPIO; - -/** - * \brief Timer interrupt callback - * - */ -typedef void (*hw_timer1_handler_cb)(void); - -/* - * \brief Timer configuration for timer/capture mode - * - * \sa timer1_config - * \sa hw_timer1_configure_timer - * - */ -typedef struct { - HW_TIMER1_DIR direction; /**< counting direction */ - uint32_t reload_val; /**< reload value */ - bool free_run; /**< free-running mode state */ - - HW_TIMER1_GPIO gpio1; /**< 1st GPIO for capture mode */ - HW_TIMER1_TRIGGER trigger1; /**< 1st GPIO capture trigger */ - HW_TIMER1_GPIO gpio2; /**< 2nd GPIO for capture mode */ - HW_TIMER1_TRIGGER trigger2; /**< 2nd GPIO capture trigger */ -} timer1_config_timer_capture; - -/* - * \brief Timer configuration for oneshot mode - * - * \sa timer1_config - * \sa hw_timer1_configure_oneshot - * - */ -typedef struct { - uint16_t delay; /**< delay (ticks) between GPIO event and output pulse */ - uint32_t shot_width; /**< width (ticks) of generated pulse */ - HW_TIMER1_GPIO gpio; /**< GPIO to wait for event */ - HW_TIMER1_TRIGGER trigger; /**< GPIO trigger */ -} timer1_config_oneshot; - -/* - * \brief Timer PWM configuration - * - * \sa timer1_config - * \sa hw_timer1_configure_pwm - * \sa hw_timer1_set_pwm_freq - * \sa hw_timer1_set_pwm_duty_cycle - */ -typedef struct { - uint16_t frequency; /**< frequency */ - uint16_t duty_cycle; /**< duty cycle */ -} timer1_config_pwm; - -/* - * \brief Timer configuration - * - * Only one of \p timer and \p oneshot configuration can be set since they are stored in the same - * union (and will overwrite each other). Proper configuration structure is selected depending on - * timer mode set. - * - * \sa timer1_config_timer_capture - * \sa timer1_config_oneshot - * \sa timer1_config_pwm - * \sa hw_timer1_configure - * - */ -typedef struct { - HW_TIMER1_CLK_SRC clk_src; /**< clock source */ - uint16_t prescaler; /**< clock prescaler */ - - union { - timer1_config_timer_capture timer; /**< configuration for timer/capture mode */ - timer1_config_oneshot oneshot; /**< configuration for oneshot mode */ - }; - timer1_config_pwm pwm; /**< PWM configuration */ -} timer1_config; - - -#if dg_configUSER_CAN_USE_TIMER1 == 1 - -/** - * \brief Timer initialization - * - * Turn on clock for timer and configure timer. After initialization both timer and its interrupt - * are disabled. \p cfg can be NULL - no configuration is performed in such case. - * - * \param [in] mode timer mode - * \param [in] cfg configuration - * - */ -void hw_timer1_init(HW_TIMER1_MODE mode, const timer1_config *cfg); - -/** - * \brief Timer configuration - * - * Shortcut to call appropriate configuration function. If \p cfg is NULL, this function does - * nothing except switching timer to selected mode. - * - * \param [in] mode timer mode - * \param [in] cfg configuration - * - */ -void hw_timer1_configure(HW_TIMER1_MODE mode, const timer1_config *cfg); - -/** - * \brief Timer configuration for timer/capture mode - * - * Shortcut to call appropriate configuration function. This does not switch timer to timer/capture - * mode, it should be done separately using hw_timer1_set_mode(). - * - * \param [in] cfg configuration - * - */ -void hw_timer1_configure_timer(const timer1_config_timer_capture *cfg); - -/** - * \brief Timer configuration for oneshot mode - * - * Shortcut to call appropriate configuration function. This does not switch timer to oneshot - * mode, it should be done separately using hw_timer1_set_mode(). - * - * \param [in] cfg configuration - * - */ -void hw_timer1_configure_oneshot(const timer1_config_oneshot *cfg); - -/** - * \brief Freeze timer - * - */ -static inline void hw_timer1_freeze(void) -{ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk; -} - -/** - * \brief Unfreeze timer - * - */ -static inline void hw_timer1_unfreeze(void) -{ - GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Msk; -} - -/** - * \brief Check if timer is frozen - * - * \return true if it is frozen else false - * - */ -static inline bool hw_timer1_frozen(void) -{ - return GPREG->SET_FREEZE_REG & GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk ? true : false; -} - -/** - * \brief Set clock source of the timer - * - * \param [in] clk clock source of the timer, external or internal - * - */ -static inline void hw_timer1_set_clk(HW_TIMER1_CLK_SRC clk) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_SYS_CLK_EN, clk); -} - -/** - * \brief Set timer clock prescaler - * - * Actual timer frequency is \p timer_freq = \p freq_clock / (\p value + 1) - * - * \param [in] value prescaler - * - */ -static inline void hw_timer1_set_prescaler(uint16_t value) -{ - TIMER1->CAPTIM_PRESCALER_REG = value; -} - -/** - * \brief Set timer reload value - * - * \note This changes the same register value as hw_timer1_set_oneshot_delay() since both parameters - * share the same register (value is interpreted differently depending on timer mode). - * - * \param [in] value reload value - * - * \sa hw_timer1_set_oneshot_delay - * \note For DA14682/3 chips, setting the reload value will also freeze the timer until both - * reload registers are set. - */ -static inline void hw_timer1_set_reload(uint32_t value) -{ -#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && (dg_configUSE_AUTO_CHIP_DETECTION != 1) - bool timer1_frozen = hw_timer1_frozen(); - if (!timer1_frozen) { - hw_timer1_freeze(); - } - TIMER1->CAPTIM_RELOAD_REG = (uint16_t) value; - TIMER1->CAPTIM_RELOAD_HIGH_REG = (uint16_t) value >> 16; - if (!timer1_frozen) { - hw_timer1_unfreeze(); - } -#else - TIMER1->CAPTIM_RELOAD_REG = (uint16_t) value; -#endif -} - -/** - * \brief Set pulse delay in oneshot mode - * - * \note This changes the same register value as hw_timer1_set_reload() since both parameters share - * the same register (value is interpreted differently depending on timer mode). - * - * \param [in] delay delay (ticks) - * - * \sa hw_timer1_set_reload - * - */ -static inline void hw_timer1_set_oneshot_delay(uint32_t delay) -{ - TIMER1->CAPTIM_RELOAD_REG = (uint16_t) delay; -} - -/** - * \brief Set shot width - * - * This applies only to one-shot mode. - * - * \param [in] duration shot phase duration - * - */ -static inline void hw_timer1_set_shot_width(uint32_t duration) -{ - TIMER1->CAPTIM_SHOTWIDTH_REG = (uint16_t) duration; -} - -/** - * \brief Turn on free run mode of the timer - * - */ -static inline void hw_timer1_set_freerun(bool enabled) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_FREE_RUN_MODE_EN, enabled); -} - -/** - * \brief Set a type of the edge which triggers event1 - * - * \param [in] edge type of edge, rising or falling - * - */ -static inline void hw_timer1_set_event1_trigger(HW_TIMER1_TRIGGER edge) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_IN1_EVENT_FALL_EN, edge); -} - -/** - * \brief Set a type of the edge which triggers event2 - * - * \param [in] edge type of edge, rising or falling - * - */ -static inline void hw_timer1_set_event2_trigger(HW_TIMER1_TRIGGER edge) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_IN2_EVENT_FALL_EN, edge); -} - -/** - * \brief Set a GPIO input which triggers event1 - * - * \param [in] gpio GPIO input - * - */ -static inline void hw_timer1_set_event1_gpio(HW_TIMER1_GPIO gpio) -{ - TIMER1->CAPTIM_GPIO1_CONF_REG = gpio; -} - -/** - * \brief Set a GPIO input which triggers event2 - * - * \param [in] gpio GPIO input - * - */ -static inline void hw_timer1_set_event2_gpio(HW_TIMER1_GPIO gpio) -{ - TIMER1->CAPTIM_GPIO2_CONF_REG = gpio; -} - -/** - * \brief Get clock source of the timer - * - * \return clock source - * - */ -static inline HW_TIMER1_CLK_SRC hw_timer1_get_clk(void) -{ - return HW_TIMER1_REG_GETF(CTRL, CAPTIM_SYS_CLK_EN); -} - -/** - * \brief Get timer clock prescaler - * - * Actual timer frequency is \p timer_freq = \p freq_clock / (\p retval + 1) - * - * \return prescaler value - * - * \sa hw_timer1_get_prescaler_val - * - */ -static inline uint16_t hw_timer1_get_prescaler(void) -{ - return TIMER1->CAPTIM_PRESCALER_REG; -} - -/** - * \brief Get timer reload value - * - * \return reload value - * - * \sa hw_timer1_set_reload - * - */ -static inline uint32_t hw_timer1_get_reload(void) -{ - return TIMER1->CAPTIM_RELOAD_REG; -} - -/** - * \brief Get pulse delay in oneshot mode - * - * \return delay (ticks) - * - * \sa hw_timer1_get_oneshot_delay - * - */ -static inline uint32_t hw_timer1_get_oneshot_delay(void) -{ - return TIMER1->CAPTIM_RELOAD_REG; -} - -/** - * \brief Get shot width - * - * This applies only to one-shot mode. - * - * \return shot width value - * - */ -static inline uint32_t hw_timer1_get_shot_width(void) -{ - return TIMER1->CAPTIM_SHOTWIDTH_REG; -} - -/** - * \brief Get free-running mode state - * - * \return free-running mode state - * - */ -static inline bool hw_timer1_get_freerun(void) -{ - return HW_TIMER1_REG_GETF(CTRL, CAPTIM_FREE_RUN_MODE_EN); -} - -/** - * \brief Get a type of the edge which triggers event1 - * - * \return edge type - * - */ -static inline HW_TIMER1_TRIGGER hw_timer1_get_event1_trigger(void) -{ - return HW_TIMER1_REG_GETF(CTRL, CAPTIM_IN1_EVENT_FALL_EN); -} - -/** - * \brief Get a type of the edge which triggers event2 - * - * \return edge type - * - */ -static inline HW_TIMER1_TRIGGER hw_timer1_get_event2_trigger(void) -{ - return HW_TIMER1_REG_GETF(CTRL, CAPTIM_IN2_EVENT_FALL_EN); -} - -/** - * \brief Get a GPIO input which triggers event1 - * - * \return GPIO input - * - */ -static inline HW_TIMER1_GPIO hw_timer1_get_event1_gpio(void) -{ - return TIMER1->CAPTIM_GPIO1_CONF_REG; -} - -/** - * \brief Get a GPIO input which triggers event2 - * - * \return GPIO input - * - */ -static inline HW_TIMER1_GPIO hw_timer1_get_event2_gpio(void) -{ - return TIMER1->CAPTIM_GPIO2_CONF_REG; -} - -/** - * \brief Get the capture time for event on GPIO1 - * - * \return time for event on GPIO1 - * - */ -static inline uint32_t hw_timer1_get_capture1(void) -{ - return TIMER1->CAPTIM_CAPTURE_GPIO1_REG; -} - -/** - * \brief Get the capture time for event on GPIO2 - * - * \return time for event on GPIO2 - * - */ -static inline uint32_t hw_timer1_get_capture2(void) -{ - return TIMER1->CAPTIM_CAPTURE_GPIO2_REG; -} - -/** - * \brief Set the direction of timer counting - * - * \param [in] dir counting direction of the timer, up or down - * - */ -static inline void hw_timer1_set_direction(HW_TIMER1_DIR dir) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_COUNT_DOWN_EN, dir); -} - -/** - * \brief Turn on one shot mode - * - */ -static inline void hw_timer1_set_mode(HW_TIMER1_MODE mode) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_ONESHOT_MODE_EN, mode); -} - -/** - * \brief Turn on capture mode - * - */ -static inline HW_TIMER1_MODE hw_timer1_get_mode(void) -{ - return HW_TIMER1_REG_GETF(CTRL, CAPTIM_ONESHOT_MODE_EN); -} - -/** - * \brief Get the tick count of the timer - * - * \return current value of the timer ticks - * - * \sa hw_timer1_get_prescaler_val - * - */ -static inline uint32_t hw_timer1_get_count(void) -{ -#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && (dg_configUSE_AUTO_CHIP_DETECTION != 1) - uint32_t lo, hi; - GLOBAL_INT_DISABLE(); - do { - lo = TIMER1->CAPTIM_TIMER_VAL_REG; - hi = TIMER1->CAPTIM_TIMER_HVAL_REG; - } while (lo != TIMER1->CAPTIM_TIMER_VAL_REG); - GLOBAL_INT_RESTORE(); - return (hi << 16) | lo; -#else - return TIMER1->CAPTIM_TIMER_VAL_REG; -#endif -} - -/** - * \brief Get the current phase of the one shot mode - * - * \return current phase of the one shot mode - * - */ -static inline HW_TIMER1_ONESHOT hw_timer1_get_oneshot_phase(void) -{ - return HW_TIMER1_REG_GETF(STATUS, CAPTIM_ONESHOT_PHASE); -} - -/** - * \brief Get the current state of IN1 - * - * \return current logic level of IN1 - * - */ -static inline bool hw_timer1_get_gpio1_state(void) -{ - return HW_TIMER1_REG_GETF(STATUS, CAPTIM_IN1_STATE); -} - -/** - * \brief Get the current state of IN2 - * - * \return current logic level of IN2 - * - */ -static inline bool hw_timer1_get_gpio2_state(void) -{ - return HW_TIMER1_REG_GETF(STATUS, CAPTIM_IN2_STATE); -} - -/** - * \brief Get the current prescaler counter value - * - * This is value of internal counter used for prescaling. It can be used to have finer granularity - * when reading timer value. - * - * For reading current setting of prescaler, see hw_timer1_get_prescaler(). - * - * \return current prescaler counter value - * - * \sa hw_timer1_get_count - * \sa hw_timer1_get_prescaler - * - */ -static inline uint16_t hw_timer1_get_prescaler_val(void) -{ - return TIMER1->CAPTIM_PRESCALER_VAL_REG; -} - -/** - * \brief Register an interrupt handler. - * - * \param [in] handler function pointer to handler to call when an interrupt occurs - * - */ -void hw_timer1_register_int(hw_timer1_handler_cb handler); - -/** - * \brief Unregister an interrupt handler - * - */ -void hw_timer1_unregister_int(void); - -#else // (dg_configUSER_CAN_USE_TIMER1 == 0) - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#define LP_CNT_REG_RANGE ( 16 ) -#else -#define LP_CNT_REG_RANGE ( 32 ) -#endif -#define LP_CNT_MAX_VALUE ( (1ULL << LP_CNT_REG_RANGE) - 1 ) -#define LP_CNT_PRESCALED_MASK ( LP_CNT_MAX_VALUE ) -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#define LP_CNT_NATIVE_MASK ( (1ULL << (LP_CNT_REG_RANGE + dg_configTim1PrescalerBitRange)) - 1 ) -#else -#define LP_CNT_NATIVE_MASK ( (1ULL << (LP_CNT_REG_RANGE)) - 1 ) -#endif - -/** - * \brief Configure timer as tick timer - * - * \details Setup Timer1 for use as a tick timer: - *
    - *
  • use LP clock and prescaler (if configured) - *
  • free running mode - *
  • IRQ masked - *
  • up counter - *
  • timer mode - *
  • disabled - *
- * - */ -void hw_timer1_lp_clk_init(void); - - -/** - * \brief Enable interrupt - * - * \return void - * - */ -static inline void hw_timer1_int_enable(void) __attribute__((always_inline)); - -static inline void hw_timer1_int_enable(void) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_IRQ_EN, 1); - NVIC_ClearPendingIRQ(SWTIM1_IRQn); - NVIC_EnableIRQ(SWTIM1_IRQn); -} - - -/** - * \brief Disable interrupt - * - * \return void - * - */ -static inline void hw_timer1_int_disable(void) __attribute__((always_inline)); - -static inline void hw_timer1_int_disable(void) -{ - NVIC_DisableIRQ(SWTIM1_IRQn); - HW_TIMER1_REG_SETF(CTRL, CAPTIM_IRQ_EN, 0); -} - - -/** - * \brief Get counter's value - * - * \return The current value of the counter (prescaled). - * - */ -static inline uint32_t hw_timer1_get_value(void) __attribute__((always_inline)); - -static inline uint32_t hw_timer1_get_value(void) -{ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - return TIMER1->CAPTIM_TIMER_VAL_REG; -#else - uint32_t lo, hi; - GLOBAL_INT_DISABLE(); - do { - lo = TIMER1->CAPTIM_TIMER_VAL_REG; - hi = TIMER1->CAPTIM_TIMER_HVAL_REG; - } while (lo != TIMER1->CAPTIM_TIMER_VAL_REG); - GLOBAL_INT_RESTORE(); - return (hi << 16) | lo; -#endif -} - - -/** - * \brief Macro to get the current value of the timer, both prescaled and in LP clock cycles. - * - * \details Special care is needed when a prescaler is used. In this case, the - * counting sequence is the following (assuminga prescaler of 3): - * prescaler: 0 1 2 3 0 1 2 3 0 - * counter: 0 1 2 - * - * If not implemented properly then the following may happen: - * - let's assume that we are at the end of the {0, 3} period - * - the counter's value is read and the result is 0 - * - at that moment, the counter increases it's prescaler value (and the counter's value - * respectively), so the time becomes {1, 0} - * - the reading of the prescaler's value will give 0 but {0, 0} is earlier than {0, 3} (when - * the operation started) and this may result in errors in time computations. - * \note This macro should be used inside a critical section. - * - */ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#define HW_TIMER1_GET_INSTANT(prescaled, fine) \ -do { \ - if (dg_configTim1Prescaler != 0) { \ - uint32_t prescaler_v; \ - \ - do { \ - prescaler_v = TIMER1->CAPTIM_PRESCALER_VAL_REG; \ - prescaled = TIMER1->CAPTIM_TIMER_VAL_REG; \ - } while (prescaler_v != TIMER1->CAPTIM_PRESCALER_VAL_REG); \ - \ - fine = ( (uint32_t)prescaled * (1 + dg_configTim1Prescaler) + prescaler_v); \ - } \ - else { \ - prescaled = TIMER1->CAPTIM_TIMER_VAL_REG; \ - fine = prescaled; \ - } \ -} while (0) -#else -#define HW_TIMER1_GET_INSTANT(prescaled, fine) \ -do { \ - uint32_t lo, hi; \ - do { \ - lo = TIMER1->CAPTIM_TIMER_VAL_REG; \ - hi = TIMER1->CAPTIM_TIMER_HVAL_REG; \ - } while (lo != TIMER1->CAPTIM_TIMER_VAL_REG); \ - prescaled = fine = (hi << 16) | lo; \ -} while (0) -#endif -/** - * \brief Macro to set the trigger value. The previous trigger value is returned to the caller. - * \note For DA14682/3 chips, this macro will disable timer1 interrupt until reload registers - * programmed so that false interrupts are avoided. - */ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#define HW_TIMER1_SET_TRIGGER(value, last_value) \ -do { \ - last_value = TIMER1->CAPTIM_RELOAD_REG; \ - TIMER1->CAPTIM_RELOAD_REG = value; \ -} while (0) -#else -#define HW_TIMER1_SET_TRIGGER(value, last_value) \ -do { \ - bool timer1_irq_en = \ - TIMER1->CAPTIM_CTRL_REG & TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk ? true : false; \ - last_value = TIMER1->CAPTIM_RELOAD_REG | \ - ((uint32_t) TIMER1->CAPTIM_RELOAD_HIGH_REG) << 16; \ - if (timer1_irq_en) { \ - TIMER1->CAPTIM_CTRL_REG &= ~TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk; \ - } \ - TIMER1->CAPTIM_RELOAD_REG = (uint16_t) value; \ - TIMER1->CAPTIM_RELOAD_HIGH_REG = (uint16_t) ((value) >> 16); \ - if (timer1_irq_en) { \ - TIMER1->CAPTIM_CTRL_REG |= TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk; \ - } \ -} while (0) -#endif - -/** - * \brief Get trigger value - * - * \return The current value of the trigger (prescaled). - * - */ -static inline uint32_t hw_timer1_get_trigger(void) -{ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - return TIMER1->CAPTIM_RELOAD_REG; -#else - return TIMER1->CAPTIM_RELOAD_REG | ((uint32_t) TIMER1->CAPTIM_RELOAD_HIGH_REG) << 16; -#endif -} - -/** - * \brief Set an "invalid" trigger value, which refers far away in the future - * - */ -static inline void hw_timer1_invalidate_trigger(void) __attribute__((always_inline)); - -static inline void hw_timer1_invalidate_trigger(void) -{ - uint32_t lp_current_time; // prescaled - uint32_t trigger; - uint32_t dummy __attribute__((unused)); - - lp_current_time = hw_timer1_get_value(); // Get current time - trigger = (lp_current_time - 1) & LP_CNT_PRESCALED_MASK; // Get an "invalid" trigger - HW_TIMER1_SET_TRIGGER(trigger, dummy); // Move trigger too far in the future so - // that no interrupt from the timer arrives. -} - -#endif // dg_configUSER_CAN_USE_TIMER1 - - -/** - * \brief Enable the timer - * - */ -static inline void hw_timer1_enable(void) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_EN, 1); - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Disable the timer - * - */ -static inline void hw_timer1_disable(void) -{ - HW_TIMER1_REG_SETF(CTRL, CAPTIM_EN, 0); - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); - GLOBAL_INT_RESTORE(); -} - -/** - * \brief Timer PWM configuration - * - * Shortcut to call appropriate configuration function. - * - * \param [in] cfg configuration - * - */ -void hw_timer1_configure_pwm(const timer1_config_pwm *cfg); - -/** - * \brief Set PWM frequency prescaler - * - * Actual PWM frequency is \p pwm_freq = \p timer_freq / (\p value + 1) - * - * \param [in] value PWM frequency defined as above - * - * \sa hw_timer1_set_prescaler - * - */ -static inline void hw_timer1_set_pwm_freq(uint16_t value) -{ - TIMER1->CAPTIM_PWM_FREQ_REG = value; -} - -/** - * \brief Set PWM duty cycle - * - * Actualy PWM duty cycle is \p pwm_dc = \p value / (\p pwm_freq + 1) - * - * \param [in] value PWM duty cycle defined as above - * - * \sa hw_timer1_set_pwm_freq - * - */ -static inline void hw_timer1_set_pwm_duty_cycle(uint16_t value) -{ - TIMER1->CAPTIM_PWM_DC_REG = value; -} - -/** - * \brief Get PWM frequency prescaler - * - * Actual PWM frequency is \p pwm_freq = \p timer_freq / (\p retval + 1) - * - * \return PWM frequency as defined above - * - */ -static inline uint16_t hw_timer1_get_pwm_freq(void) -{ - return TIMER1->CAPTIM_PWM_FREQ_REG; -} - -/** - * \brief Get PWM duty cycle - * - * Actualy PWM duty cycle is \p pwm_dc = \p retval / (\p pwm_freq + 1) - * - * \return PWM duty cycle as defined above - * - */ -static inline uint16_t hw_timer1_get_pwm_duty_cycle(void) -{ - return TIMER1->CAPTIM_PWM_DC_REG; -} - -#endif /* dg_configUSE_HW_TIMER1 */ - -#endif /* HW_TIMER1_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_trng.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_trng.h deleted file mode 100644 index 9b092433e..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_trng.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - ***************************************************************************************** - * - * @file hw_trng.h - * - * @brief Definition of API for the True Random Number Generator Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_TRNG_H_ -#define HW_TRNG_H_ - -#if dg_configUSE_HW_TRNG - -#include - -/** - * \brief TRNG callback. - * - * This function is called by the TRNG driver when the interrupt is fired. - * - * \note If the TRNG is not needed anymore the hw_trng_disable function should be called in the - * callback function to save power. - * - */ -typedef void (*hw_trng_cb)(void); - -/** - * \brief TRNG enable. - * - * This function enables the TRNG. If callback is not NULL it will be called when a TRNG interrupt - * occurs. The interrupt is triggered when the TRNG FIFO is full. - * - * \param [in] callback The callback function that is called when a TRNG interrupt occurs. - * - * \note If the amount of random numbers needed is less than the contents of the FIFO it is faster - * and more power efficient to use a wait loop in combination with the hw_trng_get_fifo_level - * function. If the FIFO has the required level use the hw_trng_get_numbers function to get the - * random numbers. - * - */ -void hw_trng_enable(hw_trng_cb callback); - -/** - * \brief Get a random number from TRNG. - * - * This function reads a random number from the TRNG FIFO. - * - * \return A 32-bit unsigned random number. - * - * \warning This function does not check for number availability in the FIFO - * - */ -__attribute__((always_inline)) static inline uint32_t hw_trng_get_number(void) -{ - return *((volatile uint32_t *)MEMORY_TRNG_FIFO); -} - -/** - * \brief Get random numbers from TRNG. - * - * This function fills a buffer with random numbers read from the TRNG FIFO. - * - * \param [in] buffer The buffer to write the numbers to. - * \param [in] size The size of the buffer (max 32). - * - * \note Do not forget to disable the TRNG after reading the amount of numbers needed to save - * power. - * - * \warning This function does not check for number availability in the FIFO - * - */ -void hw_trng_get_numbers(uint32_t* buffer, uint8_t size); - -/** - * \brief TRNG get FIFO level. - * - * This function returns the current level of the TRNG FIFO. - * - * \return The current level of the TRNG FIFO. - * - */ -__RETAINED_CODE uint8_t hw_trng_get_fifo_level(void); - -/** - * \brief TRNG disable. - * - * This function stops TRNG, disables its clock and its interrupt. - * - */ -void hw_trng_disable(void); - -/** - * \brief Stop TRNG operation. - */ -static inline void hw_trng_stop(void) -{ - REG_CLR_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); -} - -/** - * \brief Disable TRNG clock. - */ -void hw_trng_disable_clk(void); - -/** - * \brief Disable TRNG interrupt. - */ -void hw_trng_disable_interrupt(void); - -/** - * \brief Clear TRNG pending interrupt. - */ -void hw_trng_clear_pending(void); - -#endif /* dg_configUSE_HW_TRNG */ - -#endif /* HW_TRNG_H_ */ - diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_uart.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_uart.h deleted file mode 100644 index ea8853320..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_uart.h +++ /dev/null @@ -1,1250 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup UART - * \{ - * \brief UART Controller - */ - -/** - ***************************************************************************************** - * - * @file hw_uart.h - * - * @brief Definition of API for the UART Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_UART_H_ -#define HW_UART_H_ - -#if dg_configUSE_HW_UART - -#include -#include -#include -#include "hw_dma.h" - -#ifndef HW_UART_USE_DMA_SUPPORT -# define HW_UART_USE_DMA_SUPPORT 1 -#endif - -#define UBA(id) ((UART2_Type *)id) -#define HW_UART1 ((uint16_t *)UART_BASE) -#define HW_UART2 ((uint16_t *)UART2_BASE) -typedef uint16_t * HW_UART_ID; - - -/** - * \brief Get the mask of a field of a UART register. - * - * \param [in] instance identifies the UART instance to use (empty: UART, 2: UART2) - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - * \note The stripped register name should be provided, e.g.: - * - to get UART_UART_USR_REG_UART_BUSY_Msk, use - * HW_UART_REG_FIELD_MASK(, USR, UART_BUSY) - * - to get UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk, use - * HW_UART_REG_FIELD_MASK(2, SFE, UART_SHADOW_FIFO_ENABLE) - * - */ -#define HW_UART_REG_FIELD_MASK(instance, reg, field) \ - (UART##instance##_UART##instance##_##reg##_REG_##field##_Msk) - -/** - * \brief Get the bit position of a field of a UART register. - * - * \param [in] instance identifies the UART instance to use (empty: UART, 2: UART2) - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - * \note The stripped register name should be provided, e.g.: - * - to get UART_UART_USR_REG_UART_BUSY_Pos, use - * HW_UART_REG_FIELD_POS(, USR, UART_BUSY) - * - to get UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos, use - * HW_UART_REG_FIELD_POS(2, SFE, UART_SHADOW_FIFO_ENABLE) - * - */ -#define HW_UART_REG_FIELD_POS(instance, reg, field) \ - (UART##instance##_UART##instance##_##reg##_REG_##field##_Pos) - -/** - * \brief Get the value of a field of a UART register. - * - * \param [in] id identifies UART to use - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * - * \return the value of the register field - * - */ -#define HW_UART_REG_GETF(id, reg, field) \ - ((UBA(id)->UART2_##reg##_REG & (UART2_UART2_##reg##_REG_##field##_Msk)) >> (UART2_UART2_##reg##_REG_##field##_Pos)) - -/** - * \brief Set the value of a field of a UART register. - * - * \param [in] id identifies UART to use - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * \param [in] new_val is the value to write - * - */ -#define HW_UART_REG_SETF(id, reg, field, new_val) \ - UBA(id)->UART2_##reg##_REG = ((UBA(id)->UART2_##reg##_REG & ~(UART2_UART2_##reg##_REG_##field##_Msk)) | \ - ((UART2_UART2_##reg##_REG_##field##_Msk) & ((new_val) << (UART2_UART2_##reg##_REG_##field##_Pos)))) - - - -/* - * ENUMERATION DEFINITIONS - ***************************************************************************************** - */ - -/** - * \brief Interrupt Identification codes - * - */ -typedef enum { - HW_UART_INT_MODEM_STAT = 0, - HW_UART_INT_NO_INT_PEND = 1, - HW_UART_INT_THR_EMPTY = 2, - HW_UART_INT_RECEIVED_AVAILABLE = 4, - HW_UART_INT_RECEIVE_LINE_STAT = 6, - HW_UART_INT_BUSY_DETECTED = 7, - HW_UART_INT_TIMEOUT = 12, -} HW_UART_INT; - -/** - * \brief Baud rates dividers - * - * The defined values comprise the values of 3 registers: DLH, DLL, DLF. - * The encoding of the values for each register is: - * - * +--------+--------+--------+--------+ - * | unused | DLH | DLL | DLF | - * +--------+--------+--------+--------+ - * - */ -typedef enum { - HW_UART_BAUDRATE_1000000 = 0x00000100, - HW_UART_BAUDRATE_500000 = 0x00000200, - HW_UART_BAUDRATE_230400 = 0x00000405, - HW_UART_BAUDRATE_115200 = 0x0000080b, - HW_UART_BAUDRATE_57600 = 0x00001106, - HW_UART_BAUDRATE_38400 = 0x00001a01, - HW_UART_BAUDRATE_28800 = 0x0000220c, - HW_UART_BAUDRATE_19200 = 0x00003401, - HW_UART_BAUDRATE_14400 = 0x00004507, - HW_UART_BAUDRATE_9600 = 0x00006803, - HW_UART_BAUDRATE_4800 = 0x0000d005, -} HW_UART_BAUDRATE; - -/** - * \brief Character format - * - */ -typedef enum { - HW_UART_DATABITS_5 = 0, - HW_UART_DATABITS_6 = 1, - HW_UART_DATABITS_7 = 2, - HW_UART_DATABITS_8 = 3, -} HW_UART_DATABITS; - -/** - * \brief Parity - * - */ -typedef enum { - HW_UART_PARITY_NONE = 0, - HW_UART_PARITY_ODD = 1, - HW_UART_PARITY_EVEN = 3, -} HW_UART_PARITY; - -/** - * \brief Stop bits - * - */ -typedef enum { - HW_UART_STOPBITS_1 = 0, - /**< The number of stop bits is 1.5 if a character format with 5 bit is chosen */ - HW_UART_STOPBITS_2 = 1, /**< Stop bit 2 */ -} HW_UART_STOPBITS; - -/** - * \brief UART configuration structure definition - * - */ -typedef struct { - // Baud rate divisor - HW_UART_BAUDRATE baud_rate; - HW_UART_DATABITS data:2; - HW_UART_PARITY parity:2; - HW_UART_STOPBITS stop:1; - uint8_t auto_flow_control:1; - uint8_t use_dma:1; - uint8_t use_fifo:1; - - HW_DMA_CHANNEL tx_dma_channel:4; - HW_DMA_CHANNEL rx_dma_channel:4; -} uart_config; - -/** - * \brief UART configuration structure definition (extended version) - * - */ -typedef struct { - // Baud rate divisor - HW_UART_BAUDRATE baud_rate; - HW_UART_DATABITS data:2; - HW_UART_PARITY parity:2; - HW_UART_STOPBITS stop:1; - uint8_t auto_flow_control:1; - uint8_t use_dma:1; - uint8_t use_fifo:1; - uint8_t tx_fifo_tr_lvl:2; - uint8_t rx_fifo_tr_lvl:2; - - HW_DMA_CHANNEL tx_dma_channel:4; - HW_DMA_CHANNEL rx_dma_channel:4; -} uart_config_ex; - -#ifdef HW_UART_ENABLE_USER_ISR -/** - * \brief User defined interrupt function - * - * User code does not need to handle interrupts. Interrupts are handled by the driver. - * If for some reason the user need to handle interrupts differently it is possible to - * set a different ISR via hw_uart_set_isr(uart_id, user_isr). - * In that case, the user-defined ISR must handle all UART interrupts as required. - * - * \sa hw_uart_set_isr - * - */ -typedef void (*hw_uart_interrupt_isr)(void); - -/** - * \brief Setup user defined interrupt function for uart - * - * \param [in] uart identifies UART - * \param [in] isr user defined interrupt handler - * - */ -void hw_uart_set_isr(HW_UART_ID uart, hw_uart_interrupt_isr isr); -#endif - -typedef void (*hw_uart_tx_callback)(void *user_data, uint16_t written); -typedef void (*hw_uart_rx_callback)(void *user_data, uint16_t read); - -//======================= Status functions ==================================== - -/** - * \brief Check if a serial transfer is inprogress - * - * \return true or false - */ -static inline bool hw_uart_is_busy(HW_UART_ID uart) -{ - return HW_UART_REG_GETF(uart, USR, UART_BUSY); -} - -//===================== Read/Write functions =================================== - -/** - * \brief Read one byte from UART - * - * This is blocking function to read single byte from UART. - * UART must be enabled before. - * - * \param [in] uart identifies UART to use - * - * \return the received byte - * - */ -uint8_t hw_uart_read(HW_UART_ID uart); - -/** - * \brief Write one byte to UART - * - * Function wait till output FIFO has empty space according to - * threshold level, and puts byte to be transmitted. - * - * \param [in] uart identifies UART to use - * \param [in] data byte to be written - * - */ -void hw_uart_write(HW_UART_ID uart, uint8_t data); - -/** - * \brief Stop asynchronous read from UART - * - * If there is outstanding read on given UART it will be stopped. - * Callback will be fired with data already present in buffer. - * Callback may be called from interrupt in the meantime but will be called - * only once. - * - * \param [in] uart identifies UART to use - * - * \return number of bytes actually received - * - */ -uint16_t hw_uart_abort_receive(HW_UART_ID uart); - -/** - * \brief Get number of bytes currently received by asynchronous read - * - * If there is outstanding read on given UART function returns number of - * byte currently received. - * - * \param [in] uart identifies UART to use - * - */ -uint16_t hw_uart_peek_received(HW_UART_ID uart); - -/** - * \brief Read receive buffer register - * - * \param [in] uart identifies UART to use - * - * \return the read byte - * - */ -static inline uint8_t hw_uart_rxdata_getf(HW_UART_ID uart) -{ - // Read element from the receive FIFO - return UBA(uart)->UART2_RBR_THR_DLL_REG; -} - -/** - * \brief Write byte to the transmit holding register - * - * \param [in] uart identifies UART to use - * \param [in] data byte to be written - * - */ -static inline void hw_uart_txdata_setf(HW_UART_ID uart, uint8_t data) -{ - // Write data to the transmit FIFO - UBA(uart)->UART2_RBR_THR_DLL_REG = data; -} - -/** - * \brief Writes number of bytes to UART synchronously - * - * This function finishes when all data is put in FIFO. It does not wait for data to be transmitted - * out from UART. Call \sa hw_uart_is_tx_fifo_empty() to wait for transmission to finish. - * This function does not use interrupts nor DMA. - * - * \param [in] uart identifies UART to use - * \param [in] data data to be written - * \param [in] len length of to be written - * - */ -void hw_uart_write_buffer(HW_UART_ID uart, const void *data, uint16_t len); - -/** - * \brief Writes number of bytes to UART - * - * \param [in] uart identifies UART to use - * \param [in] data data to be written - * \param [in] len length of to be written - * \param [in] cb function to call from interrupt when transmission ends - * \param [in] user_data parameter passed to cb function - * - */ -void hw_uart_send(HW_UART_ID uart, const void *data, uint16_t len, hw_uart_tx_callback cb, - void *user_data); - -/** - * \brief Read number of bytes from UART synchronously - * - * This function waits to receive \p len bytes from UART. - * This function does not use interrupts not DMA, it just waits for all data to arive. - * - * \param [in] uart identifies UART to use - * \param [out] data buffer for incoming data - * \param [in] len number of bytes to read - * - */ -void hw_uart_read_buffer(HW_UART_ID uart, void *data, uint16_t len); - -/** - * \brief Read number of bytes from UART - * - * Function initializes UART for receiving data. - * When \p len data is received or timeout occurs user provided callback will be fired with - * number of bytes read so far. - * - * \param [in] uart identifies UART to use - * \param [out] data buffer for incoming data - * \param [in] len max number of bytes to read - * \param [in] cb function to call from interrupt when data is received - * \param [in] user_data parameter passed to cb function - * - */ -void hw_uart_receive(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callback cb, - void *user_data); - -#if HW_UART_USE_DMA_SUPPORT - -/** - * \brief Assign DMA channel to UART rx and tx - * - * Function specifies DMA channel to use for specified UART rx and tx FIFO. - * It will setup channel only if there is no transmission in progress. - * - * \param [in] uart identifies UART to use - * \param [in] channel id of DMA channel to use for rx, - * tx will use next channel, - * -1 if DMA should not be used - * \param [in] pri priority DMA_PRIO_0 (lowest), - * ..... - * DMA_PRIO_7 (highest) - * - */ -void hw_uart_set_dma_channels(HW_UART_ID uart, int8_t channel, HW_DMA_PRIO pri); - -/** - * \brief Assign DMA channel to UART rx and tx - * - * Function specifies DMA channel to use for specified UART rx and tx FIFO. - * It will setup channel only if there is no transmission in progress. - * - * \param [in] uart identifies UART to use - * \param [in] tx_channel id of DMA channel to use for tx: - * HW_DMA_CHANNEL_0..HW_DMA_CHANNEL_INVALID - * \param [in] rx_channel id of DMA channel to use for rx: - * HW_DMA_CHANNEL_0..HW_DMA_CHANNEL_INVALID - * \param [in] pri priority DMA_PRIO_0 (lowest), - * ..... - * DMA_PRIO_7 (highest) - * - */ -void hw_uart_set_dma_channels_ex(HW_UART_ID uart, int8_t tx_channel, int8_t rx_channel, HW_DMA_PRIO pri); -#endif - -//============== Interrupt handling ============================================ - -/** - * \brief Set the Received Data Available interrupt - * - * \param [in] uart identifies UART to use - * \param [in] recdataavail should be 0 to disable and 1 to enable - * - */ -static inline void hw_uart_rec_data_int_set(HW_UART_ID uart, uint8_t recdataavail) -{ - // Set ERBFI bit in Interrupt Enable Register - HW_UART_REG_SETF(uart, IER_DLH, ERBFI_dlh0, recdataavail); -} -/** - * \brief Set the Transmit Holding Register empty interrupt - * - * \param [in] uart identifies UART to use - * \param [in] txempty should be 0 to disable and 1 to enable - * - */ -static inline void hw_uart_tx_empty_int_set(HW_UART_ID uart, uint8_t txempty) -{ - // Set ETBEI bit in Interrupt Enable Register - HW_UART_REG_SETF(uart, IER_DLH, ETBEI_dlh1, txempty); -} - -/** - * \brief Set the Line Status interrupt - * - * \param [in] uart identifies UART to use - * \param [in] linestat should be 0 to disable and 1 to enable - * - */ -static inline void hw_uart_linestat_int_set(HW_UART_ID uart, uint8_t linestat) -{ - // Set ELSI bit in Interrupt Enable Register - HW_UART_REG_SETF(uart, IER_DLH, ELSI_dhl2, linestat); -} - -/** - * \brief Set the Programmable THRE interrupt - * - * \param [in] uart identifies UART to use - * \param [in] pthre should be 0 to disable and 1 to enable - * - */ -static inline void hw_uart_pthre_int_set(HW_UART_ID uart, uint8_t pthre) -{ - // Set PTIME bit in Interrupt Enable Register - HW_UART_REG_SETF(uart, IER_DLH, PTIME_dlh7, pthre); -} - -/** - * \brief Get the Interrupt ID - * - * \param [in] uart identifies UART to use - * - * \return interrupt type - * - */ -static inline HW_UART_INT hw_uart_get_interrupt_id(HW_UART_ID uart) -{ - return (HW_UART_INT) (UBA(uart)->UART2_IIR_FCR_REG & 0xF); -} - -/** - * \brief Write Scratch pad register - * - * \param [in] uart identifies UART to use - * \param [in] value the value to be written - * - * /warning Reserved when retarget is used else it is free to use. - * - */ -static inline void hw_uart_write_scr(HW_UART_ID uart, uint8_t value) -{ - UBA(uart)->UART2_SCR_REG = value; -} - -/** - * \brief Read Scratch pad register - * - * \param [in] uart identifies UART to use - * - * \return register value - * - * \warning Reserved when retarget is used else it is free to use. - * - */ -static inline uint8_t hw_uart_read_scr(HW_UART_ID uart) -{ - return UBA(uart)->UART2_SCR_REG; -} - -//==================== Configuration functions ================================= - -/** - * \brief Get the baud rate setting - * - * \param [in] uart identifies UART to use - * - * \return baud rate of specified uart - * - */ -HW_UART_BAUDRATE hw_uart_baudrate_get(HW_UART_ID uart); - -/** - * \brief Set the baud rate - * - * \param [in] uart identifies UART to use - * \param [in] baud_rate uart baud rate - * - */ -void hw_uart_baudrate_set(HW_UART_ID uart, HW_UART_BAUDRATE baud_rate); - -//=========================== FIFO control functions =========================== - -/** - * \brief Check if there is data available for read - * - * \param [in] uart identifies UART to use - * - * \return true if there is data to receive - * - */ -static inline bool hw_uart_is_data_ready(HW_UART_ID uart) -{ - return (UBA(uart)->UART2_LSR_REG & 1) != 0; -} - -/** - * \brief Get the FIFO mode setting - * - * \param [in] uart identifies UART to use - * - * \return true if FIFO is enabled (both transmitter and receiver) - * - */ -static inline bool hw_uart_is_fifo_enabled(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - return UART2->UART2_SFE_REG != 0; -} - -/** - * \brief Disable both FIFOs - * - * \param [in] uart identifies UART to use - * - */ -static inline void hw_uart_disable_fifo(HW_UART_ID uart) -{ - uint16_t iir_fcr_reg = UBA(uart)->UART2_IIR_FCR_REG; - iir_fcr_reg &= 0xfffe; - UBA(uart)->UART2_IIR_FCR_REG = iir_fcr_reg; -} - -/** - * \brief Enable both FIFOs - * - * Thresholds should be set before for predictable results. - * - * \param [in] uart identifies UART to use - * - */ -static inline void hw_uart_enable_fifo(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - UART2->UART2_SFE_REG = 1 << HW_UART_REG_FIELD_POS(2, SFE, UART_SHADOW_FIFO_ENABLE); -} - -/** - * \brief Check if receive FIFO is not empty - * - * \param [in] uart identifies UART to use - * - * \return true if FIFO is not empty - * - */ -static inline bool hw_uart_receive_fifo_not_empty(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - return HW_UART_REG_GETF(uart, USR, UART_RFNE) != 0; -} - -/** - * \brief Check if transmit FIFO is not full - * - * \param [in] uart identifies UART to use - * - * \return true if FIFO is full - * - */ -static inline bool hw_uart_transmit_fifo_not_full(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - return HW_UART_REG_GETF(uart, USR, UART_TFNF) != 0; -} - -/** - * \brief Check if transmit FIFO is empty - * - * \param [in] uart identifies UART to use - * - * \return true if FIFO empty - * - */ -static inline bool hw_uart_transmit_fifo_empty(HW_UART_ID uart) -{ - return HW_UART_REG_GETF(uart, USR, UART_TFE) != 0; -} - - -/** - * \brief Read number of byte in receive FIFO - * - * \param [in] uart identifies UART to use - * - * \return number of byte in receive FIFO - * - */ -static inline uint16_t hw_uart_receive_fifo_count(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - return UART2->UART2_RFL_REG; -} - -/** - * \brief Read number of byte in transmit FIFO - * - * \param [in] uart identifies UART to use - * - * \return number of byte in transmit FIFO - * - */ -static inline uint16_t hw_uart_transmit_fifo_count(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - return UART2->UART2_TFL_REG; -} - -/** - * \brief Enable loopback - * - * \param [in] uart identifies UART to use - * - */ -static inline void hw_uart_enable_loopback(HW_UART_ID uart) -{ - HW_UART_REG_SETF(uart, MCR, UART_LB, 1); -} - -/** - * \brief Disable loopback - * - * \param [in] uart identifies UART to use - * - */ -static inline void hw_uart_disable_loopback(HW_UART_ID uart) -{ - HW_UART_REG_SETF(uart, MCR, UART_LB, 0); -} - -/** - * \brief Get the FIFO mode setting - * - * \param [in] uart identifies UART to use - * - * \return the FIFO mode that has been set in the FIFO Control Register: - * 0 = FIFO mode disabled, - * 1 = FIFO mode enabled - * - */ -uint8_t hw_uart_fifo_en_getf(HW_UART_ID uart); - -/** - * \brief Enable or disable the UART FIFO mode - * - * \param [in] uart identifies UART to use - * \param [in] en should be 0 to disable and 1 to enable FIFO mode - * - */ -static inline void hw_uart_fifo_en_setf(HW_UART_ID uart, uint8_t en) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - // Write FIFO Enable (FIFOE) bit in FIFO Control Register - uint16_t iir_fcr_reg = UBA(uart)->UART2_IIR_FCR_REG; - iir_fcr_reg &= ~0x1; - iir_fcr_reg |= (en & 0x1); - UBA(uart)->UART2_IIR_FCR_REG = iir_fcr_reg; -} - -/** - * \brief Get the receive FIFO trigger level at which the - * Received Data Available Interrupt is generated - * - * \param [in] uart identifies UART to use - * - * \return the receive FIFO trigger level: - * 0 = 1 character in the FIFO, - * 1 = FIFO 1/4 full, - * 2 = FIFO 1/2 full, - * 3 = FIFO 2 less than full - * - */ -static inline uint8_t hw_uart_rx_fifo_tr_lvl_getf(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - return UART2->UART2_SRT_REG & UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk; -} - -/** - * \brief Set the receive FIFO trigger level at which the - * Received Data Available Interrupt is generated - * - * \param [in] uart identifies UART to use - * \param [in] tr_lvl The receive FIFO trigger level: - * 0 = 1 character in the FIFO, - * 1 = FIFO 1/4 full, - * 2 = FIFO 1/2 full, - * 3 = FIFO 2 less than full - * - */ -static inline void hw_uart_rx_fifo_tr_lvl_setf(HW_UART_ID uart, uint8_t tr_lvl) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - UART2->UART2_SRT_REG = tr_lvl; -} - -/** - * \brief Get the transmit FIFO trigger level at which the - * Transmit Holding Register Empty (THRE) Interrupt is generated - * - * \param [in] uart identifies UART to use - * - * \return the transmit FIFO trigger level: - * 0 = FIFO empty, - * 1 = 2 characters in the FIFO, - * 2 = FIFO 1/4 full, - * 3 = FIFO 1/2 full - * - */ -uint8_t hw_uart_tx_fifo_tr_lvl_getf(HW_UART_ID uart); - -/** - * \brief Set the transmit FIFO trigger level at which the - * Transmit Holding Register Empty (THRE) Interrupt is generated - * - * \param [in] uart identifies UART to use - * \param [in] tr_lvl the transmit FIFO trigger level: - * 0 = FIFO empty, - * 1 = 2 characters in the FIFO, - * 2 = FIFO 1/4 full, - * 3 = FIFO 1/2 full - * - */ -static inline void hw_uart_tx_fifo_tr_lvl_setf(HW_UART_ID uart, uint8_t tr_lvl) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - UART2->UART2_STET_REG = tr_lvl; -} - -/** - * \brief Reset UART transmit FIFO - * - * \param [in] uart identifies UART to use - * - */ -static inline void hw_uart_tx_fifo_flush(HW_UART_ID uart) -{ - HW_UART_REG_SETF(uart, SRR, UART_XFR, 1); -} - -/** - * \brief Reset UART receive FIFO - * - * \param [in] uart identifies UART to use - * - */ -static inline void hw_uart_rx_fifo_flush(HW_UART_ID uart) -{ - HW_UART_REG_SETF(uart, SRR, UART_RFR, 1); -} - -/** - * \brief Check whether reading buffer is empty - * - * Works for both when Rx FIFO is enabled or not. - * - * \param [in] uart identifies UART to use - * - * \return true if there is no data available for reading - * - */ -static inline bool hw_uart_read_buf_empty(HW_UART_ID uart) -{ - return !HW_UART_REG_GETF(uart, LSR, UART_DR); -} - -/** - * \brief Check whether writing buffer is full - * - * Works for both when Tx FIFO is enabled or not. - * - * \param [in] uart identifies UART to use - * - * \return true if transmit buffer is full - * - */ -static inline bool hw_uart_write_buf_full(HW_UART_ID uart) -{ - return !HW_UART_REG_GETF(uart, LSR, UART_THRE); -} - -#if dg_configUART_SOFTWARE_FIFO -/** - * \brief Set buffer that will be use for incoming data when there is no read in progress - * - * \param [in] uart identifies UART to use - * \param [in] buf buffer to use as software FIFO - * \param [in] size size of \p buf - * - */ -void hw_uart_set_soft_fifo(HW_UART_ID uart, uint8_t *buf, uint8_t size); -#endif - -//=========================== DMA control functions ============================ - -/** - * \brief Set UART DMA mode - * - * \param [in] uart identifies UART to use - * \param [in] dma_mode DMA mode 0 or 1 - * - */ -static inline void hw_uart_dma_mode_setf(HW_UART_ID uart, uint8_t dma_mode) -{ - /* Only UART2 has the SDMAM register */ - ASSERT_ERROR(uart == HW_UART2); - - UART2->UART2_SDMAM_REG = ((dma_mode & 1) << UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos) - << UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk; -} - -/** - * \brief Clear DMA request - * - * \param [in] uart identifies UART to use - * - */ -static inline void hw_uart_clear_dma_request(HW_UART_ID uart) -{ - UBA(uart)->UART2_DMASA_REG = 1; -} - -//=========================== Line control functions ============================ - -/** - * \brief Set UART line settings - * - * This function initialize UART registers with given configuration. - * It also initializes all internal software variables for buffered transmissions. - * - * \param [in] uart identifies UART to use - * \param [in] cfg pointer to the UART configuration structure - * - */ -void hw_uart_init(HW_UART_ID uart, const uart_config *cfg); - -/** - * \brief Set UART line settings - * - * This function initialize UART registers with given configuration, - * including tx and rx fifo trigger levels - * It also initializes all internal software variables for buffered transmissions. - * - * \param [in] uart identifies UART to use - * \param [in] cfg pointer to the UART configuration structure - * - */ -void hw_uart_init_ex(HW_UART_ID uart, const uart_config_ex *cfg); - -/** - * \brief Re-initialize UART registers - * - * Call this function with configuration that should be re-applied, this function should be - * called after platform exits power sleep mode. - * This function is similar to uart_init, but it does not initialize software variables - * used for transmission control it just re-applies hardware configuration. - * It will turn on interrupts if transmission was in progress. - * - * \param [in] uart identifies UART to use - * \param [in] cfg pointer to the UART configuration structure - * - */ -void hw_uart_reinit(HW_UART_ID uart, const uart_config *cfg); - -/** - * \brief Re-initialize UART registers - * - * Call this function with configuration that should be re-applied, this function should be - * called after platform exits power sleep mode. - * This function is similar to uart_init_ex, but it does not initialize software variables - * used for transmission control it just re-applies hardware configuration. - * It will turn on interrupts if transmission was in progress. - * - * \param [in] uart identifies UART to use - * \param [in] cfg pointer to the UART configuration structure - * - */ -void hw_uart_reinit_ex(HW_UART_ID uart, const uart_config_ex *cfg); - -/** - * \brief Get UART line settings - * - * \param [in] uart identifies UART to use - * \param [in] cfg pointer to the UART configuration structure - */ -void hw_uart_cfg_get(HW_UART_ID uart, uart_config *cfg); - -//=========================== Modem control functions ========================== - -/** - * \brief Get the IrDA SIR mode setting - * - * \param [in] uart identifies UART to use - * - * \return IrDA SIR mode: - * 0 = IrDA SIR mode disabled, - * 1 = IrDA SIR mode enabled - * - */ -uint8_t hw_uart_sire_getf(HW_UART_ID uart); - -/** - * \brief Set the IrDA SIR mode - * - * \param [in] uart identifies UART to use - * \param [in] sire 0 = disable IrDA SIR mode, - * 1 = enable IrDA SIR mode - * - */ -void hw_uart_sire_setf(HW_UART_ID uart, uint8_t sire); - -/** - * \brief Get the Auto Flow Control Enable (AFCE) setting - * - * \param [in] uart identifies UART to use - * - * \return Auto Flow Control Enable (AFCE): - * 0 = Auto Flow Control Mode disabled, - * 1 = Auto Flow Control Mode enabled - * - */ -uint8_t hw_uart_afce_getf(HW_UART_ID uart); - -/** - * \brief Enable or disable Auto Flow Control - * - * \param [in] uart identifies UART to use - * \param [in] afce Auto Flow Control Enable (AFCE): - * 0 = disable Auto Flow Control Mode, - * 1 = enable Auto Flow Control Mode - * - */ -void hw_uart_afce_setf(HW_UART_ID uart, uint8_t afce); - -/** - * \brief Get UART diagnostic mode status - * - * \param [in] uart identifies UART to use - * - * \return the value of the loop back bit - * - */ -uint8_t hw_uart_loopback_getf(HW_UART_ID uart); - -/** - * \brief Set UART in diagnostic mode - * - * \param [in] uart identifies UART to use - * \param [in] lb loop back bit value - * - */ -void hw_uart_loopback_setf(HW_UART_ID uart, uint8_t lb); - -/** - * \brief Get RTS output value - * - * \param [in] uart identifies UART to use - * - * \return RTS output value - * - */ -uint8_t hw_uart_rts_getf(HW_UART_ID uart); - -/** - * \brief Set RTS output value - * - * \param [in] uart identifies UART to use - * \param [in] rtsn Value for the RTS output (asserted low) - * - */ -void hw_uart_rts_setf(HW_UART_ID uart, uint8_t rtsn); - -//=========================== Line status functions ============================ - -/** - * \brief Get the value of the Receiver FIFO Error bit - * - * \param [in] uart identifies UART to use - * - * \return receiver FIFO Error bit value: - * 0 = no error in RX FIFO, - * 1 = error in RX FIFO - * - */ -uint8_t hw_uart_rx_fifo_err_getf(HW_UART_ID uart); - -/** - * \brief Get the value of the Transmitter Empty bit - * - * \param [in] uart identifies UART to use - * - * \return 1 if transmitter FIFO is empty - * - */ -uint8_t hw_uart_is_tx_fifo_empty(HW_UART_ID uart); - -/** - * \brief Get the value of the Transmit Holding Register Empty bit - * - * \param [in] uart identifies UART to use - * - * \return the Transmit Holding Register Empty bit value - * - */ -uint8_t hw_uart_thr_empty_getf(HW_UART_ID uart); - -/** - * \brief Get the value of the Break Interrupt bit - * - * \param [in] uart identifies UART to use - * - * \return break interrupt bit value: This is used to indicate the detection of a - * break sequence on the serial input data - * - */ -uint8_t hw_uart_break_int_getf(HW_UART_ID uart); - -/** - * \brief Get the value of the Framing Error bit - * - * \param [in] uart identifies UART to use - * - * \return framing error bit value: - * 0 = no framing error, - * 1 = framing error - * - * - */ -uint8_t hw_uart_frame_err_getf(HW_UART_ID uart); - -/** - * \brief Get the value of the Parity Error bit - * - * \param [in] uart identifies UART to use - * - * \return parity error bit value: - * 0 = no parity error, - * 1 = parity error - * - */ -uint8_t hw_uart_parity_err_getf(HW_UART_ID uart); - -/** - * \brief Get the value of the Overrun Error bit - * - * \param [in] uart identifies UART to use - * - * \return overrun error bit value: - * 0 = no overrun error, - * 1 = overrun error - * - */ -uint8_t hw_uart_overrun_err_getf(HW_UART_ID uart); - -//=========================== Modem status functions =========================== - -/** - * \brief Get CTS input status - * - * \param [in] uart identifies UART to use - * - * \return status of CTS input: - * 0 = CTSn input is de-asserted (logic 1), - * 1 = CTSn input is asserted (logic 0), - * In loopback mode, CTS is the same as RTS - * - */ -uint8_t hw_uart_cts_getf(HW_UART_ID uart); - -/** - * \brief Get Delta CTS - * - * \param [in] uart identifies UART to use - * - * \return DCTS: - * 0 = No change on CTS since last read of Modem Control Register, - * 1 = Change on CTS since last read of Modem Control Register, - * Note that calling this function will clear the DCTS bit, - * In loopback mode, DCTS reflects changes on RTS - * - */ -uint8_t hw_uart_delta_cts_getf(HW_UART_ID uart); - -/** - * \brief Check if buffered write is in progress - * - * \param [in] uart identifies UART to use - * - * \return true if there is TX transmission in progress - * - */ -bool hw_uart_tx_in_progress(HW_UART_ID uart); - -/** - * \brief Check if buffered read is in progress - * - * \param [in] uart identifies UART to use - * - * \return true if there is RX transmission in progress - * - */ -bool hw_uart_rx_in_progress(HW_UART_ID uart); - -#if dg_configUART_RX_CIRCULAR_DMA - -/** - * \brief Enable circular RX DMA for UART - * - * This reconfigures RX DMA channel to use circular buffer for incoming data and enabled it - * immediately. Incoming data will be read by DMA to intermediate buffer. Subsequent calls to - * hw_uart_receive() will fire callback as soon as enough data are available in buffer to be read, - * but the actual read from intermediate buffer has to be done using hw_uart_copy_rx_circular_dma_buffer(). - * - * Recommended way to move between DMA buffer and user buffer is to call hw_uart_abort_receive() - * that will copy the amount specified on read or the actual number of received bytes if - * hw_uart_abort_receive() was called before requested the amount was received. - * - * \note - * This can be only called for an UART which is configured using \p dg_configUARTx_RX_CIRCULAR_DMA_BUF_SIZE. - * - * \param [in] uart identifies UART to use - * - */ -void hw_uart_enable_rx_circular_dma(HW_UART_ID uart); - -/** - * \brief Copy data from circular RX DMA buffer to user buffer - * - * \param [in] uart identifies UART to use - * \param [in] buf buffer to copy data to - * \param [in] len length of data to copy to buffer - * - */ -void hw_uart_copy_rx_circular_dma_buffer(HW_UART_ID uart, uint8_t *buf, uint16_t len); - -#endif /* dg_configUART_RX_CIRCULAR_DMA */ - -#endif /* dg_configUSE_HW_UART */ - -#endif /* HW_UART_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_watchdog.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_watchdog.h deleted file mode 100644 index db969baee..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_watchdog.h +++ /dev/null @@ -1,188 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup Watchdog_Timer - * \{ - * \brief Watchdog Timer - */ - -/** - ***************************************************************************************** - * - * @file hw_watchdog.h - * - * @brief Definition of API for the Watchdog timer Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_WATCHDOG_H_ -#define HW_WATCHDOG_H_ - - -#include -#include -#include - -#define NMI_MAGIC_NUMBER 0xDEADBEEF - -/** - * \brief Holds the stack contents when an NMI occurs. - * - * \details The stack contents are copied at this variable when an NMI occurs. The first position is - * marked with a special "flag" (0xDEADBEEF) to indicate that the data that follow are valid. - */ -extern uint32_t nmi_event_data[9]; - -/** - * \brief Types of generated states if reload value is 0 - * - * Generate NMI (non-maskable interrupt) or RST (reset of the system) - * - */ -typedef enum { - HW_WDG_RESET_NMI = 0, /**< Generate NMI if the watchdog reaches 0 and WDOG reset if the counter become less or equal to -16 */ - HW_WDG_RESET_RST = 1 /**< Generate WDOG reset it the counter becomes less or equal than 0 */ -} HW_WDG_RESET; - -/** - * \brief Watchdog timer interrupt callback - * - * \param [in] hardfault_args pointer to call stack - * - */ -typedef void (*hw_watchdog_interrupt_cb)(unsigned long *exception_args); - -/** - * \brief Freeze the watchdog - * - * \return true if operation is allowed, else false - * - */ -__RETAINED_CODE bool hw_watchdog_freeze(void); - -/** - * \brief Unfreeze the watchdog - * - */ -__RETAINED_CODE void hw_watchdog_unfreeze(void); - -/** - * \brief Set positive reload value of the watchdog timer - * - * \param [in] value reload value from 0 (0x00) to 255 (0xFF) - * - */ -static inline void hw_watchdog_set_pos_val(uint8_t value) __attribute__((always_inline)); - -static inline void hw_watchdog_set_pos_val(uint8_t value) -{ - WDOG->WATCHDOG_REG = (uint16_t)value; -} - -/** - * \brief Set negative reload value of the watchdog timer - * - * \param [in] value reload value from -16 (0x1FF) to 0 (0x00) - * - */ -static inline void hw_watchdog_set_neg_val(uint8_t value) -{ - WDOG->WATCHDOG_REG = WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk | (uint16_t)value; -} - -/** - * \brief Get reload value of the watchdog timer - * - */ -static inline uint16_t hw_watchdog_get_val(void) -{ - return REG_GETF(WDOG, WATCHDOG_REG, WDOG_VAL); -} - -/** - * \brief Generate a reset signal of the system if reload value reaches 0 - * - */ -static inline void hw_watchdog_gen_RST(void) __attribute__((always_inline)); - -static inline void hw_watchdog_gen_RST(void) -{ - REG_SET_BIT(WDOG, WATCHDOG_CTRL_REG, NMI_RST); -} - -/** - * \brief Register an interrupt handler - * - * \param [in] handler function pointer to handler to call when an interrupt occurs - * - */ -void hw_watchdog_register_int(hw_watchdog_interrupt_cb handler); - -/** - * \brief Unregister an interrupt handler - * - */ -__RETAINED_CODE void hw_watchdog_unregister_int(void); - -/** - * \brief Handle NMI interrupt. - * - * \param [in] hardfault_args pointer to call stack - * - */ -__RETAINED_CODE void hw_watchdog_handle_int(unsigned long *hardfault_args); - -/** - * \brief Check whether the timer has expired - * - * \return true, if the timer has expired, false otherwise - * - */ -bool hw_watchdog_is_timer_expired(void); - -/** - * \brief Check what is generated when watchdog reaches 0 value - * - * If it is NMI (interrupt) or RST (system/wdog reset). - * - * \return HW_WDG_RESET_NMI if NMI interrupt is generated, otherwise HW_WDG_RESET_RST - * - */ -HW_WDG_RESET hw_watchdog_is_irq_or_rst_gen(void); - -#endif /* HW_WATCHDOG_H_ */ - - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_wkup.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_wkup.h deleted file mode 100644 index 5aa83328d..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_wkup.h +++ /dev/null @@ -1,600 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup Wakeup_Timer - * \{ - * \brief Wakeup Timer - */ - -/** - ***************************************************************************************** - * - * @file hw_wkup.h - * - * @brief Definition of API for the Wakeup timer Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#ifndef HW_WKUP_H_ -#define HW_WKUP_H_ - -#if dg_configUSE_HW_WKUP - -#include -#include -#include -#include "hw_gpio.h" - - -#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE -#define WKUP_SEL_P0_BASE_REG (volatile uint16_t *)(&WAKEUP->WKUP_SEL_GPIO_P0_REG) -#else -#define WKUP_SEL_P0_BASE_REG (volatile uint16_t *)(&WAKEUP->WKUP_SELECT_P0_REG) -#endif - -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE -/** - * \brief Wakeup timer configuration - * - */ -typedef struct { - uint8_t pin_state[HW_GPIO_NUM_PORTS]; /**< pin states in each port, 1: enabled, 0: disabled */ - uint8_t pin_trigger[HW_GPIO_NUM_PORTS]; /**< pin triggers in each port, 1: low, 0: high */ -} wkup_pin_config_t; -extern volatile wkup_pin_config_t wkup_pin_config; /**< stores wkup pin configuration */ -extern volatile uint8_t wkup_status[HW_GPIO_NUM_PORTS]; /**< stores wakeup sources */ -#endif - -/** - * \brief Get the mask of a field of an WKUP register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_WKUP_REG_FIELD_MASK(reg, field) \ - (WAKEUP_WKUP_##reg##_REG_##field##_Msk) - -/** - * \brief Get the bit position of a field of an WKUP register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to access - * - */ -#define HW_WKUP_REG_FIELD_POS(reg, field) \ - (WAKEUP_WKUP_##reg##_REG_##field##_Pos) - -/** - * \brief Get the value of a field of an WKUP register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * - * \return the value of the register field - * - */ -#define HW_WKUP_REG_GETF(reg, field) \ - ((WAKEUP->WKUP_##reg##_REG & (WAKEUP_WKUP_##reg##_REG_##field##_Msk)) >> (WAKEUP_WKUP_##reg##_REG_##field##_Pos)) - -/** - * \brief Set the value of a field of an WKUP register. - * - * \param [in] reg is the register to access - * \param [in] field is the register field to write - * \param [in] new_val is the value to write - * - */ -#define HW_WKUP_REG_SETF(reg, field, new_val) \ - WAKEUP->WKUP_##reg##_REG = ((WAKEUP->WKUP_##reg##_REG & ~(WAKEUP_WKUP_##reg##_REG_##field##_Msk)) | \ - ((WAKEUP_WKUP_##reg##_REG_##field##_Msk) & ((new_val) << (WAKEUP_WKUP_##reg##_REG_##field##_Pos)))) - - -/** - * \brief Pin state which increments event counter - * - */ -typedef enum { - HW_WKUP_PIN_STATE_HIGH = 0, - HW_WKUP_PIN_STATE_LOW = 1 -} HW_WKUP_PIN_STATE; - -/** - * \brief Wakeup timer configuration - * - */ -typedef struct { -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - /** - * counter threshold - * - * \warning Supported only in DA14680/1 chips - */ - uint8_t threshold; -#endif -#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) - uint8_t debounce; /**< debounce time in ms */ -#endif - uint8_t pin_state[HW_GPIO_NUM_PORTS]; /**< pin states in each port, see hw_wkup_configure_port */ - uint8_t pin_trigger[HW_GPIO_NUM_PORTS]; /**< pin triggers in each port, see hw_wkup_configure_port */ -} wkup_config; - -typedef void (*hw_wkup_interrupt_cb)(void); - -/** - * \brief Initialize peripheral - * - * Resets Wakeup Timer to initial state, i.e. interrupt is disabled and all pin triggers are - * disabled. - * - * \p cfg can be NULL - no configuration is performed in such case. - * - * \param [in] cfg configuration - * - */ -void hw_wkup_init(const wkup_config *cfg); - -/** - * \brief Configure peripheral - * - * Shortcut to call appropriate configuration function. If \p cfg is NULL, this function does - * nothing. - * - * \param [in] cfg configuration - * - */ -void hw_wkup_configure(const wkup_config *cfg); - -/** - * \brief Register interrupt handler - * - * Callback function is called when interrupt is generated, i.e. event counter reaches configured - * value. Interrupt is automatically enabled after calling this function. Application should reset - * interrupt in callback function using hw_wkup_reset_interrupt(). If no callback is specified, - * interrupt will be automatically cleared by the driver. - * - * \param [in] cb callback function - * \param [in] prio the priority of the interrupt - * - * \sa hw_wkup_unregister_interrupt - * \sa hw_wkup_clear_interrupt - * \sa hw_wkup_set_counter_threshold - * \sa hw_wkup_get_counter - * - */ -void hw_wkup_register_interrupt(hw_wkup_interrupt_cb cb, uint32_t prio); - -/** - * \brief Unregister interrupt handler - * - * Interrupt is automatically disabled after calling this function. - * - */ -void hw_wkup_unregister_interrupt(void); - -/** - * \brief Reset interrupt - * - * This function MUST be called by any user-specified interrupt callback, to clear the interrupt. - * - */ -static inline void hw_wkup_reset_interrupt(void) -{ - WAKEUP->WKUP_RESET_IRQ_REG = 1; -} - -/** - * \brief Interrupt handler - * - */ -void hw_wkup_handler(void); - -#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) -/** - * \brief Set debounce time - * - * Setting debounce time to 0 will disable hardware debouncing. Maximum debounce time is 63ms. - * - * \param [in] time_ms debounce time in milliseconds - * - */ -static inline void hw_wkup_set_debounce_time(uint8_t time_ms) -{ - HW_WKUP_REG_SETF(CTRL, WKUP_DEB_VALUE, time_ms); -} -#endif //!((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) - -/** - * \brief Get current debounce time - * - * \return debounce time in milliseconds - * - */ -static inline uint8_t hw_wkup_get_debounce_time(void) -{ - return HW_WKUP_REG_GETF(CTRL, WKUP_DEB_VALUE); -} - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -/** - * \brief Set threshold for event counter - * - * Interrupt is generated after event counter reaches configured value. - * - * \param [in] level number of events - * - * \warning Supported only in DA14680/1 chips - * \sa hw_wkup_register_interrupt - * \sa hw_wkup_get_counter - * - */ -static inline void hw_wkup_set_counter_threshold(uint8_t level) -{ - HW_WKUP_REG_SETF(COMPARE, COMPARE, level); -} - -/** - * \brief Get threshold for event counter - * - * \return number of events - * - * \warning Supported only in DA14680/1 chips - */ -static inline uint8_t hw_wkup_get_counter_threshold(void) -{ - return HW_WKUP_REG_GETF(COMPARE, COMPARE); -} - -/** - * \brief Get current value of event counter - * - * Number of events counted so far. Can be reset using hw_wkup_reset_counter(). - * - * \return number of events - * - * \note The counter is automatically reset by the hardware when the interrupt is generated. - * - * \warning Supported only in DA14680/1 chips - * - * \sa hw_wkup_reset_counter - * - */ -static inline uint8_t hw_wkup_get_counter(void) -{ - return HW_WKUP_REG_GETF(COUNTER, EVENT_VALUE); -} - -/** - * \brief Reset event counter - * - * There is no need to reset counter manually in interrupt callback - it's reset automatically by - * hardware. - * - * \warning Supported only in DA14680/1 chips - */ -static inline void hw_wkup_reset_counter(void) -{ - WAKEUP->WKUP_RESET_CNTR_REG = 1; -} -#endif - -/** - * \brief Set GPIO pin event counting state - * - * Once enabled, state changes on pin will increment event counter. State which triggers event can - * be set using hw_wkup_set_pin_trigger(). - * - * \param [in] port port number - * \param [in] pin pin number - * \param [in] enabled pin event counting state - * - * \sa hw_wkup_set_pin_trigger - * \sa hw_wkup_configure_pin - * \sa hw_wkup_configure_port - * - */ -static inline void hw_wkup_set_pin_state(HW_GPIO_PORT port, HW_GPIO_PIN pin, bool enabled) -{ - volatile uint16_t *wkup_pin_enable_reg = WKUP_SEL_P0_BASE_REG + port; - uint16_t wkup_pin_enable_val = *wkup_pin_enable_reg; - wkup_pin_enable_val &= ~(1 << pin); - wkup_pin_enable_val |= (!!enabled) << pin; - *wkup_pin_enable_reg = wkup_pin_enable_val; -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE - wkup_pin_config.pin_state[port] = wkup_pin_enable_val; -#endif -} - -/** \brief Get GPIO pin event counting state - * - * \param [in] port port number - * \param [in] pin pin number - * - * \return pin event counting state - * - * \sa hw_wkup_set_pin_state - * - */ -static inline bool hw_wkup_get_pin_state(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ - uint16_t wkup_pin_enable_val = *(WKUP_SEL_P0_BASE_REG + port); - return (wkup_pin_enable_val & (1 << pin)) >> pin; -} - -/** - * \brief Set GPIO pin state which triggers event - * - * Pin event counting should be enabled for this setting to have any effect. - * - * \param [in] port port number - * \param [in] pin pin number - * \param [in] state pin state - * - * \sa hw_wkup_set_pin_counter_state - * \sa hw_wkup_configure_pin - * \sa hw_wkup_configure_port - * - */ -static inline void hw_wkup_set_pin_trigger(HW_GPIO_PORT port, HW_GPIO_PIN pin, - HW_WKUP_PIN_STATE state) -{ - uint16_t pol_rx_reg = *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port); - pol_rx_reg &= ~(1 << pin); - pol_rx_reg |= (!!state) << pin; - *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port) = pol_rx_reg; -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE - wkup_pin_config.pin_trigger[port] = pol_rx_reg; -#endif -} - -/** \brief Get GPIO pin state which triggers event - * - * \param [in] port port number - * \param [in] pin pin number - * - * \return pin state - * - * \sa hw_wkup_set_pin_trigger - * - */ -static inline HW_WKUP_PIN_STATE hw_wkup_get_pin_trigger(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ - uint16_t pol_rx_reg = *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port); - return (pol_rx_reg & (1 << pin)) >> pin; -} - -/** - * \brief Set GPIO pin event counting and triggered state - * - * Effectively, this is shortcut for calling hw_wkup_set_pin_state() and hw_wkup_set_pin_trigger(). - * - * \param [in] port port number - * \param [in] pin pin number - * \param [in] enabled pin event counting state - * \param [in] state pin state - * - * \sa hw_wkup_set_pin_counter_state - * \sa hw_wkup_set_pin_trigger - * \sa hw_wkup_configure_port - * - */ -static inline void hw_wkup_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, bool enabled, - HW_WKUP_PIN_STATE state) -{ - // first set up the proper polarity... - hw_wkup_set_pin_trigger(port, pin, state); - // ...then enable counting on the specific GPIO - hw_wkup_set_pin_state(port, pin, enabled); -} - -/** - * \brief Configure event counting and triggering state for whole GPIO port - * - * In \p enabled and \p state bitmasks each bit describes state of corresponding pin in port. - * For \p enabled 0 means disabled and 1 means enabled. - * For \p state 0 means event is triggered on low state and 1 means trigger is on high state. - * - * \param [in] port port number - * \param [in] enabled pin event counting bitmask - * \param [in] state pin state bitmask - * - * \sa hw_wkup_set_pin_counter_state - * \sa hw_wkup_set_pin_trigger - * \sa hw_wkup_configure_pin - * - */ -static inline void hw_wkup_configure_port(HW_GPIO_PORT port, uint8_t enabled, uint8_t state) -{ - *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port) = ~state; // register has inverted logic than state bitmask - *(WKUP_SEL_P0_BASE_REG + port) = enabled; -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE - wkup_pin_config.pin_state[port] = enabled; - wkup_pin_config.pin_trigger[port] = ~state; -#endif -} - -/** - * \brief Get state (enabled/disabled) of all pins in GPIO port - * - * Meaning of bits in returned bitmask is the same as in hw_wkup_configure_port(). - * - * \return port pin event counter state bitmask - * - * \sa hw_wkup_configure_port - * - */ -static inline uint8_t hw_wkup_get_port_state(HW_GPIO_PORT port) -{ -#if dg_configLATCH_WKUP_SOURCE -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - return wkup_pin_config.pin_state[port]; -#else - return *((volatile uint16_t *)(&WAKEUP->WKUP_SEL_GPIO_P0_REG) + port); -#endif -#else - return *((volatile uint16_t *)(&WAKEUP->WKUP_SELECT_P0_REG) + port); -#endif -} - -/** - * \brief Get event triggering state for all pins in GPIO port - * - * Meaning of bits in returned bitmask is the same as in hw_wkup_configure_port(). - * - * \return port pin event triggering state bitmask - * - * \sa hw_wkup_configure_port - * - */ -static inline uint8_t hw_wkup_get_port_trigger(HW_GPIO_PORT port) -{ -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE - return wkup_pin_config.pin_trigger[port]; -#else - return ~(*((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port)); // register has inverted logic that returned bitmask -#endif -} - -/** - * \brief Emulate key hit - * - * Event counter will be increased with debounce time taken into account (if enabled). - * - */ -static inline void hw_wkup_emulate_key_hit(void) -{ - HW_WKUP_REG_SETF(CTRL, WKUP_SFT_KEYHIT, 1); - HW_WKUP_REG_SETF(CTRL, WKUP_SFT_KEYHIT, 0); -} - -/** - * \brief Freeze wakeup timer - * - */ -static inline void hw_wkup_freeze(void) -{ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk; -} - -/** - * \brief Unfreeze wakeup timer - * - */ -static inline void hw_wkup_unfreeze(void) -{ - GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk; -} - -/** - * \brief Get port status on last wake up - * - * Meaning of bits in returned bitmask is the same as in hw_wkup_configure_port(). - * - * \return port pin event counter state bitmask - * - * \sa hw_wkup_configure_port - * - */ -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE -static inline uint8_t hw_wkup_get_status(HW_GPIO_PORT port) -{ - return wkup_status[port]; -} -#elif dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -static inline uint8_t hw_wkup_get_status(HW_GPIO_PORT port) -{ - switch (port) { - case HW_GPIO_PORT_0: - return HW_WKUP_REG_GETF(STATUS_0, WKUP_STAT_P0); - case HW_GPIO_PORT_1: - return HW_WKUP_REG_GETF(STATUS_0, WKUP_STAT_P1); - case HW_GPIO_PORT_2: - return HW_WKUP_REG_GETF(STATUS_1, WKUP_STAT_P2); - case HW_GPIO_PORT_3: - return HW_WKUP_REG_GETF(STATUS_2, WKUP_STAT_P3); - case HW_GPIO_PORT_4: - return HW_WKUP_REG_GETF(STATUS_2, WKUP_STAT_P4); - default: - ASSERT_WARNING(0);//Invalid argument - } -} -#endif - -/** - * \brief Clear latch status - * - * This function MUST be called by any user-specified interrupt callback, - * to clear the interrupt latch status. - * - * \param [in] port port number - * \param [in] status pin status bitmask - * - * \sa hw_wkup_get_status - */ -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE -static inline void hw_wkup_clear_status(HW_GPIO_PORT port, uint8_t status) -{ - ASSERT_WARNING((port>=HW_GPIO_PORT_0) && (port<=HW_GPIO_PORT_4)) - wkup_status[port] &= ~status; -} -#elif dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -static inline void hw_wkup_clear_status(HW_GPIO_PORT port, uint8_t status) -{ - switch (port) { - case HW_GPIO_PORT_0: - HW_WKUP_REG_SETF(CLEAR_0, WKUP_CLEAR_P0, status); - break; - case HW_GPIO_PORT_1: - HW_WKUP_REG_SETF(CLEAR_0, WKUP_CLEAR_P1, status); - break; - case HW_GPIO_PORT_2: - HW_WKUP_REG_SETF(CLEAR_1, WKUP_CLEAR_P2, status); - break; - case HW_GPIO_PORT_3: - HW_WKUP_REG_SETF(CLEAR_2, WKUP_CLEAR_P3, status); - break; - case HW_GPIO_PORT_4: - HW_WKUP_REG_SETF(CLEAR_2, WKUP_CLEAR_P4, status); - break; - default: - ASSERT_WARNING(0);//Invalid argument - } -} -#endif - -#endif /* dg_configUSE_HW_WKUP */ -#endif /* HW_WKUP_H_ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h deleted file mode 100644 index ea91523ee..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup TCS_HANDLER - * - * \brief TCS Handler - * - * \{ - */ - -/** - **************************************************************************************** - * - * @file sys_tcs.h - * - * @brief TCS Handler header file. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef SYS_TCS_H_ -#define SYS_TCS_H_ - -#include -#include "sdk_defs.h" - -typedef enum sys_tcs_area_type { -#ifdef CONFIG_USE_BLE - tcs_ble, -#endif -#ifdef CONFIG_USE_FTDF - tcs_ftdf, -#endif - tcs_radio, - tcs_charger, - tcs_audio, - tcs_system, /* Last area. Add any missing areas above this! */ -} sys_tcs_area_t; - -/** - * \brief Flag to check whether the TCS is written or not. - * \details true, the TCS is written (the BANDGAP_REG value exists in the TCS) - * false, the TCS is empty - */ -extern bool sys_tcs_is_calibrated_chip; - -/** - * \brief The XTAL16M settling time (in TCS). - * \details XTAL32K, the settling time is expressed in clock cycles - * RCX, not applicable; the SDK hard-coded value is used - * If it is zero, the hard-coded value (dg_configXTAL16_SETTLE_TIME) is applied. - */ -extern uint16_t sys_tcs_xtal16m_settling_time; - -/** - * \brief Initialize the variables used from the TCS handling module. - * - */ -void sys_tcs_init(void); - -/** - * \brief Store TCS pair in the Global TCS array if it points to a register - * that is not in the AON power dowmain or is not retained, else it applies the vaule to - * the register. - * - * \param [in] address the address of the register - * \param [in] value the value for this register - * - * \return true if the chip is calibrated (the BANDGAP setting has been applied), else false. - * - * \warning When this function is called, the RC16 must have been set as the system clock! - * - */ -bool sys_tcs_store_pair(uint32_t address, uint32_t value); - -/** - * \brief Sort the registers of the registers in the Memory Map of the chip to a different "classes" - * in the TCS array. - * - */ -void sys_tcs_sort_array(void); - -/** - * \brief Apply the pairs located in a "class" of the TCS array. This is done only - * for calibrated chips! - * - */ -void sys_tcs_apply(sys_tcs_area_t area); - -#endif /* SYS_TCS_H_ */ - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c deleted file mode 100644 index 16e7ec8bb..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c +++ /dev/null @@ -1,414 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup AES_HASH - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_aes_hash.c - * - * @brief Implementation of the AES/Hash Engine Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_AES_HASH - -#include -#include - -#define MODE_IS_AES(m) (m <= HW_AES_CTR) - -static void hw_aes_hash_wait_on_inactive(void) -{ - while (!REG_GETF(AES_HASH, CRYPTO_STATUS_REG, CRYPTO_INACTIVE)) { - ; - }; -} - -static void hw_aes_hash_set_mode(const hw_aes_hash_setup* setup) -{ - uint32_t crypt0_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - - switch (setup->mode) { - case HW_AES_ECB: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 0); - break; - case HW_AES_CBC: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 3); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 0); - AES_HASH->CRYPTO_MREG0_REG = setup->aesIvCtrblk_0_31; - AES_HASH->CRYPTO_MREG1_REG = setup->aesIvCtrblk_32_63; - AES_HASH->CRYPTO_MREG2_REG = setup->aesIvCtrblk_64_95; - AES_HASH->CRYPTO_MREG3_REG = setup->aesIvCtrblk_96_127; - break; - case HW_AES_CTR: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 2); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 0); - AES_HASH->CRYPTO_MREG0_REG = setup->aesIvCtrblk_0_31; - AES_HASH->CRYPTO_MREG1_REG = setup->aesIvCtrblk_32_63; - AES_HASH->CRYPTO_MREG2_REG = setup->aesIvCtrblk_64_95; - AES_HASH->CRYPTO_MREG3_REG = setup->aesIvCtrblk_96_127; - break; - case HW_HASH_MD5: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 0); - break; - case HW_HASH_SHA_1: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 1); - break; - case HW_HASH_SHA_256_224: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 2); - break; - case HW_HASH_SHA_256: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 0); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 3); - break; - case HW_HASH_SHA_384: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 0); - break; - case HW_HASH_SHA_512: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 1); - break; - case HW_HASH_SHA_512_224: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 2); - break; - case HW_HASH_SHA_512_256: - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_SEL, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG_MD, crypt0_ctrl_reg, 1); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ALG, crypt0_ctrl_reg, 3); - break; - } - - AES_HASH->CRYPTO_CTRL_REG = crypt0_ctrl_reg; -} - -static void hw_aes_hash_check_data_size(const hw_aes_hash_setup* setup) -{ - switch (setup->mode) { - case HW_AES_ECB: - // In ECB mode the dataSize needs to be a multiple of 16. - ASSERT_ERROR(setup->dataSize % 0x10 == 0); - break; - case HW_AES_CBC: - case HW_AES_CTR: - // If more data is to come in CBC or CTR mode the dataSize needs to be a multiple of 16. - if (setup->moreDataToCome) { - ASSERT_ERROR(setup->dataSize % 0x10 == 0); - } - break; - case HW_HASH_MD5: - case HW_HASH_SHA_1: - case HW_HASH_SHA_256_224: - case HW_HASH_SHA_256: - case HW_HASH_SHA_384: - case HW_HASH_SHA_512: - case HW_HASH_SHA_512_224: - case HW_HASH_SHA_512_256: - // If more data is to come in hash mode the dataSize needs to be a multiple of 8. - if (setup->moreDataToCome) { - ASSERT_ERROR(setup->dataSize % 0x8 == 0); - } - break; - } -} - -hw_aes_hash_cb hw_aes_hash_old_style_cb = NULL; - -static void hw_aes_hash_old_cb_style_support(unsigned int status) -{ - if (hw_aes_hash_old_style_cb) { - hw_aes_hash_old_style_cb(); - } -} - -void hw_aes_hash_enable_interrupt(hw_aes_hash_cb cb) -{ - hw_aes_hash_old_style_cb = cb; - hw_crypto_enable_aes_hash_interrupt(hw_aes_hash_old_cb_style_support); - REG_SET_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_IRQ_EN); -} - -void hw_aes_hash_disable_interrupt(void) -{ - REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_IRQ_EN); - hw_crypto_disable_aes_hash_interrupt(); -} - -static inline uint32 hw_aes_hash_construct_word(const uint8 *data) -{ - if ((uint32)data & 0x3) { - uint32 internal_buf; - uint8 *p = (uint8 *)&internal_buf + 3; - unsigned int i; - - for (i = 0; i < 4; i++) { - *(p--) = *(data++); - } - - return internal_buf; - } - else { - return SWAP32(*(uint32 *)data); - } -} - -void hw_aes_hash_store_keys(hw_aes_key_size key_size, const uint8 *aes_keys, hw_aes_hash_key_exp_t key_exp) -{ - volatile uint32 *kmem_ptr = &AES_HASH->CRYPTO_KEYS_START; - unsigned int key_wrds; - - if (key_exp == HW_AES_DO_NOT_PERFORM_KEY_EXPANSION) { - /* Key expansion is provided by the software */ - REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEXP); - key_wrds = (key_size == HW_AES_256) ? 60 : (key_size == HW_AES_192) ? 52 : 44; - } - else { - /* Key expansion needs to be performed by the engine */ - REG_SET_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEXP); - key_wrds = (key_size == HW_AES_256) ? 8 : (key_size == HW_AES_192) ? 6 : 4; - } - - do { - *(kmem_ptr++) = hw_aes_hash_construct_word(aes_keys); - aes_keys += 4; - key_wrds--; - } while (key_wrds > 0); -} - -void hw_aes_hash_enable(const hw_aes_hash_setup setup) -{ - hw_aes_hash_check_data_size(&setup); - - hw_aes_hash_enable_clock(); - - hw_aes_hash_set_mode(&setup); - - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN, crypto_ctrl_reg, - setup.moreDataToCome); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (setup.hashOutLength - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ENCDEC, crypto_ctrl_reg, - setup.aesDirection); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEXP, crypto_ctrl_reg, - setup.aesKeyExpand); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEY_SZ, crypto_ctrl_reg, - setup.aesKeySize); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_OUT_MD, crypto_ctrl_reg, - !setup.aesWriteBackAll); - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; - - if (MODE_IS_AES(setup.mode)) { - hw_aes_hash_store_keys(setup.aesKeySize, (uint8 *)setup.aesKeys, !setup.aesKeyExpand); - } - - hw_aes_hash_cfg_dma((const uint8 *)setup.sourceAddress, (uint8 *)setup.destinationAddress, - (unsigned int)setup.dataSize); - - if (setup.enableInterrupt) { - hw_aes_hash_old_style_cb = setup.callback; - hw_aes_hash_enable_interrupt_source(); - hw_crypto_enable_aes_hash_interrupt(hw_aes_hash_old_cb_style_support); - } - else { - hw_aes_hash_disable_interrupt_source(); - hw_crypto_disable_aes_hash_interrupt(); - } - - hw_aes_hash_start(); -} - -void hw_aes_hash_init(hw_aes_hash_setup *setup) -{ - hw_aes_hash_check_data_size(setup); - - hw_aes_hash_enable_clock(); - - hw_aes_hash_set_mode(setup); - - uint32_t crypto_ctrl_reg = AES_HASH->CRYPTO_CTRL_REG; - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN, crypto_ctrl_reg, - setup->moreDataToCome); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_HASH_OUT_LEN, crypto_ctrl_reg, - (setup->hashOutLength - 1)); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_ENCDEC, crypto_ctrl_reg, - setup->aesDirection); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEXP, crypto_ctrl_reg, - setup->aesKeyExpand); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_AES_KEY_SZ, crypto_ctrl_reg, - setup->aesKeySize); - REG_SET_FIELD(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_OUT_MD, crypto_ctrl_reg, - !setup->aesWriteBackAll); - AES_HASH->CRYPTO_CTRL_REG = crypto_ctrl_reg; - - if (MODE_IS_AES(setup->mode)) { - hw_aes_hash_store_keys(setup->aesKeySize, (uint8 *)setup->aesKeys, !setup->aesKeyExpand); - } - - hw_aes_hash_cfg_dma((const uint8 *)setup->sourceAddress, (uint8 *)setup->destinationAddress, - (unsigned int)setup->dataSize); - - if (setup->enableInterrupt) { - hw_aes_hash_old_style_cb = setup->callback; - hw_aes_hash_enable_interrupt_source(); - hw_crypto_enable_aes_hash_interrupt(hw_aes_hash_old_cb_style_support); - } - else { - hw_aes_hash_disable_interrupt_source(); - hw_crypto_disable_aes_hash_interrupt(); - } -} - -void hw_aes_hash_restart(const uint32 sourceAddress, const uint32 dataSize, - const bool moreDataToCome) -{ - hw_aes_hash_cfg_dma((const uint8 *)sourceAddress, NULL, (unsigned int)dataSize); - REG_SETF(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN, moreDataToCome); - hw_aes_hash_start(); -} - -bool hw_aes_hash_is_active() -{ - return REG_GETF(AES_HASH, CRYPTO_STATUS_REG, CRYPTO_INACTIVE) == 0; -} - -bool hw_aes_hash_wait_for_in() -{ - return REG_GETF(AES_HASH, CRYPTO_STATUS_REG, CRYPTO_WAIT_FOR_IN) == 1; -} - -void hw_aes_hash_disable(const bool waitOnFinish) -{ - if (waitOnFinish) - hw_aes_hash_wait_on_inactive(); - - hw_aes_hash_disable_interrupt_source(); - AES_HASH->CRYPTO_CLRIRQ_REG = 1; - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, AES_CLK_ENABLE); - GLOBAL_INT_RESTORE(); - REG_CLR_BIT(AES_HASH, CRYPTO_CTRL_REG, CRYPTO_MORE_IN); -} - -void hw_aes_hash_cfg_dma(const uint8 *src, uint8 *dst, unsigned int len) -{ - /* Source address setting */ - AES_HASH->CRYPTO_FETCH_ADDR_REG = DA15000_phy_addr((uint32)src); - - /* Destination address setting */ - if (dst) { - unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); - - if (IS_SYSRAM_ADDRESS(dst) || - (IS_REMAPPED_ADDRESS(dst) && (remap_type == 0x3))) { - AES_HASH->CRYPTO_DEST_ADDR_REG = DA15000_phy_addr((uint32)dst); -#if dg_configEXEC_MODE != MODE_IS_CACHED - } else if (IS_CACHERAM_ADDRESS(dst)) { - AES_HASH->CRYPTO_DEST_ADDR_REG = DA15000_phy_addr((uint32)dst); -#endif - } else { - /* - * Destination address can only reside in RAM or Cache RAM, but in case of remapped - * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) - */ - ASSERT_ERROR(0); - } - } - - /* Data length setting */ - AES_HASH->CRYPTO_LEN_REG = (uint32)len; -} - -static void hw_aes_hash_store_in_mode_dependent_regs(const uint8 *buf) -{ - AES_HASH->CRYPTO_MREG0_REG = hw_aes_hash_construct_word(buf + 12); - AES_HASH->CRYPTO_MREG1_REG = hw_aes_hash_construct_word(buf + 8); - AES_HASH->CRYPTO_MREG2_REG = hw_aes_hash_construct_word(buf + 4); - AES_HASH->CRYPTO_MREG3_REG = hw_aes_hash_construct_word(buf + 0); -} - -void hw_aes_hash_store_iv(const uint8 *iv) -{ - hw_aes_hash_store_in_mode_dependent_regs(iv); -} - -void hw_aes_hash_store_ic(const uint8 *ic) -{ - hw_aes_hash_store_in_mode_dependent_regs(ic); -} - -int hw_aes_hash_check_restrictions(void) -{ - unsigned int is_hash = AES_HASH->CRYPTO_CTRL_REG & AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk; - unsigned int more_in = AES_HASH->CRYPTO_CTRL_REG & AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk; - - if (is_hash) { - if (more_in && (AES_HASH->CRYPTO_LEN_REG & 0x7)) { - return -1; - } - } - else { - unsigned int is_ecb = (((AES_HASH->CRYPTO_CTRL_REG & AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk) == 0) | - ((AES_HASH->CRYPTO_CTRL_REG & AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk) == 0x0100)); - - if ((is_ecb || more_in) && (AES_HASH->CRYPTO_LEN_REG & 0x15)) { - return -1; - } - } - - return 0; -} - -#endif /* dg_configUSE_HW_AES_HASH */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c deleted file mode 100644 index a375f69fd..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c +++ /dev/null @@ -1,856 +0,0 @@ -/** -\addtogroup BSP -\{ -\addtogroup DEVICES -\{ -\addtogroup CPM -\{ -*/ - -/** - **************************************************************************************** - * - * @file hw_cpm.c - * - * @brief Clock and Power Manager Driver - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_CPM - - -#include -#include "hw_cpm.h" -#include "hw_watchdog.h" - - -/* - * These variables should be defined and initialized by the framework/sdk used - */ -extern sys_clk_t cm_sysclk; -extern ahb_div_t cm_ahbclk; - - -/* - * Global variables - */ -__RETAINED_UNINIT uint16_t hw_cpm_bod_enabled_in_tcs; - -#if (dg_configPOWER_1V8_ACTIVE == 1) -__RETAINED_RW static bool cpm_1v8_state = true; -#else -static const bool cpm_1v8_state = false; -#endif - - -/* - * Local variables - */ - - - -/* - * Forward declarations - */ - - - -/* - * Function definitions - */ - - -uint32_t hw_cpm_sysclk_is_rc16(void) -{ - uint32_t ret = 0; - - if (REG_GETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL) == SYS_CLK_IS_RC16) { - ret = 1; - } - - return ret; -} - - -uint32_t hw_cpm_sysclk_is_xtal16m(void) -{ - uint32_t ret = 0; - - if (REG_GETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL) == SYS_CLK_IS_XTAL16M) { - ret = 1; - } - - return ret; -} - - -void hw_cpm_set_divn(bool freq) -{ - uint32_t regval; - int val; - - if (freq) { - val = 1; - } - else { - val = 0; - } - - regval = CRG_TOP->CLK_CTRL_REG; - REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, DIVN_XTAL32M_MODE, regval, val); - REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, XTAL32M_MODE, regval, val); - CRG_TOP->CLK_CTRL_REG = regval; -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - CRG_TOP->DIVN_SYNC_REG = val; -#endif -} - - -bool hw_cpm_is_rc16_allowed(void) -{ - bool ret = false; - uint32_t tmp; - - do { - tmp = CRG_TOP->SYS_STAT_REG; - -#ifdef CONFIG_USE_FTDF - // Check FTDF - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP)) { - break; - } -#endif - -#ifdef CONFIG_USE_BLE - // Check BLE - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, BLE_IS_UP)) { - break; - } -#endif - - // Check APHY/DPHY & COEX - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, RAD_IS_UP)) { - break; - } - - if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, PER_IS_UP)) { - // Check SRC - if (REG_GETF(APU, SRC1_CTRL_REG, SRC_EN) == 1) { - break; - } - - // Check PDM - if (REG_GETF(CRG_PER, PDM_DIV_REG, CLK_PDM_EN) == 1) { - break; - } - - // Check USB - if (REG_GETF(USB, USB_MCTRL_REG, USBEN) == 1) { - break; - } - - tmp = CRG_PER->CLK_PER_REG; - // Check UART1/2 - if (tmp & REG_MSK(CRG_PER, CLK_PER_REG, UART_ENABLE)) { - break; - } - - /* -------------------------------------------------------------------------------*/ - - // Check ADC clock - if (REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_EN) && - (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, ADC_CLK_SEL)))) { - break; - } - - // Check I2C clock - if ((tmp & REG_MSK(CRG_PER, CLK_PER_REG, I2C_ENABLE)) && - (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, I2C_CLK_SEL)))) { - break; - } - - // Check SPI clock - if ((tmp & REG_MSK(CRG_PER, CLK_PER_REG, SPI_ENABLE)) && - (!(tmp & REG_MSK(CRG_PER, CLK_PER_REG, SPI_CLK_SEL)))) { - break; - } - - // Check PCM clock - tmp = CRG_PER->PCM_DIV_REG; - if ((tmp & REG_MSK(CRG_PER, PCM_DIV_REG, CLK_PCM_EN)) && - (!(tmp & REG_MSK(CRG_PER, PCM_DIV_REG, PCM_SRC_SEL)))) { - break; - } - - /* KBSCN and QUAD are not seriously affected by the clock switch and, thus, - * they cannot block it! - */ - } - - tmp = CRG_TOP->CLK_TMR_REG; - // Check Timer0 clock - if ((tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_ENABLE)) && - (!(tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR0_CLK_SEL)))) { - break; - } - - // Check Timer2 clock - if ((tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_ENABLE)) && - (!(tmp & REG_MSK(CRG_TOP, CLK_TMR_REG, TMR2_CLK_SEL)))) { - break; - } - - /* Breathe, SOC and WDOG are not seriously affected by the clock switch and, thus, - * they cannot block it! - */ - - ret = true; - } while (0); - - return ret; -} - - -void hw_cpm_set_sysclk(uint32_t mode) -{ - /* Make sure a valid sys clock is requested */ - ASSERT_WARNING(mode <= SYS_CLK_IS_PLL); - - REG_SETF(CRG_TOP, CLK_CTRL_REG, SYS_CLK_SEL, mode); - - // Wait until the switch is done! - switch (mode) { - case SYS_CLK_IS_XTAL16M: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_XTAL16M) == 0) {} - break; - - case SYS_CLK_IS_RC16: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_RC16M) == 0) {} - break; - - case SYS_CLK_IS_LP: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_32K) == 0) {} - break; - - case SYS_CLK_IS_PLL: - while (REG_GETF(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M) == 0) {} - break; - - default: - ASSERT_WARNING(0); - break; - } -} - - -void hw_cpm_short_delay(void) -{ - volatile int i; - - for (i = 0; i < 20; i++); -} - - -void hw_cpm_pll_sys_on(void) -{ - /* Before enabling the PLL LDO, the 1.4V voltage needs to be present; in real-life this - * is achieved by first turning on the 1.4V ACORE LDO, then the DCDC converter to take over - * the generation of 1.4V and finally turning off the ACORE LDO. - */ - - /* LDO PLL enable. */ - REG_SET_BIT(GPREG, PLL_SYS_CTRL1_REG, LDO_PLL_ENABLE); - - /* Configure system PLL. */ - REG_SETF(GPREG, PLL_SYS_CTRL1_REG, PLL_R_DIV, 1); /* Default/reset value. */ - - /* Program N-divider and DEL_SEL. */ - REG_SET_BIT(GPREG, PLL_SYS_CTRL2_REG, PLL_SEL_MIN_CUR_INT); // Last review date: Feb 15, 2016 - 12:25:47 - - /* Now turn on PLL. */ - REG_SET_BIT(GPREG, PLL_SYS_CTRL1_REG, PLL_EN); - - while ((GPREG->PLL_SYS_STATUS_REG & REG_MSK(GPREG, PLL_SYS_STATUS_REG, LDO_PLL_OK)) == 0) {} - - /* And wait until lock. */ - while ((GPREG->PLL_SYS_STATUS_REG & REG_MSK(GPREG, PLL_SYS_STATUS_REG, PLL_LOCK_FINE)) == 0) {} -} - - -void hw_cpm_pll_sys_off(void) -{ - // The PLL is not the system clk. - while ((CRG_TOP->CLK_CTRL_REG & REG_MSK(CRG_TOP, CLK_CTRL_REG, RUNNING_AT_PLL96M)) != 0); - GPREG->PLL_SYS_CTRL1_REG = 0x0000; // Switch off the PLL. -} - - -__RETAINED_CODE void hw_cpm_start_calibration(cal_clk_t clk_type, uint32_t cycles) -{ - ASSERT_WARNING(REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 0); // Must be disabled - - ANAMISC->CLK_REF_CNT_REG = cycles; // # of cal clock cycles - REG_SETF(ANAMISC, CLK_REF_SEL_REG, REF_CLK_SEL, clk_type); - REG_SET_BIT(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START); -} - - -uint32_t hw_cpm_get_calibration_data(void) -{ - uint32_t high; - uint32_t low; - uint32_t value; - - while (REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 1); // Wait until it's finished - - high = ANAMISC->CLK_REF_VAL_H_REG; - low = ANAMISC->CLK_REF_VAL_L_REG; - value = ( high << 16 ) + low; - - return value; -} - -void hw_cpm_dcdc_config(void) -{ - uint32_t reg; - - /* - * Preferred settings section - * Last review date: January 03, 2017 - 16:26:35 - */ - REG_CLR_BIT(DCDC, DCDC_CTRL_0_REG, DCDC_FW_ENABLE); - - reg = DCDC->DCDC_IRQ_MASK_REG; - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V18P_TIMEOUT_IRQ_MASK, reg, 1); - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_VDD_TIMEOUT_IRQ_MASK, reg, 1); - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V18_TIMEOUT_IRQ_MASK, reg, 1); - REG_SET_FIELD(DCDC, DCDC_IRQ_MASK_REG, DCDC_V14_TIMEOUT_IRQ_MASK, reg, 1); - DCDC->DCDC_IRQ_MASK_REG = reg; - - REG_SET_BIT(DCDC, DCDC_TRIM_REG, DCDC_P_COMP_MAN_TRIM); - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - DCDC->DCDC_V14_0_REG &= ~(REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_FAST_RAMPING)); - - DCDC->DCDC_V18_0_REG &= ~(REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_FAST_RAMPING)); - - DCDC->DCDC_V18P_0_REG &= ~(REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_FAST_RAMPING)); - - DCDC->DCDC_VDD_0_REG &= ~(REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_CUR_LIM_MIN) | - REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_FAST_RAMPING)); -#else - DCDC->DCDC_V14_0_REG &= ~REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_FAST_RAMPING); - - DCDC->DCDC_V18_0_REG &= ~REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_FAST_RAMPING); - - DCDC->DCDC_V18P_0_REG &= ~REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_FAST_RAMPING); - - DCDC->DCDC_VDD_0_REG &= ~REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_FAST_RAMPING); - - reg = DCDC->DCDC_CTRL_2_REG; - REG_SET_FIELD(DCDC, DCDC_CTRL_2_REG, DCDC_LSSUP_TRIM, reg, 0); - REG_SET_FIELD(DCDC, DCDC_CTRL_2_REG, DCDC_HSGND_TRIM, reg, 0); - DCDC->DCDC_CTRL_2_REG = reg; -#endif - - REG_SETF(DCDC, DCDC_VDD_1_REG, DCDC_VDD_CUR_LIM_MAX_LV, 0xD); - - REG_SETF(DCDC, DCDC_V14_0_REG, DCDC_V14_VOLTAGE, 0x8); - - if (dg_configPOWER_1V8_ACTIVE == 1) { - REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, 0x16); - } - - if (dg_configPOWER_1V8P == 1) { - REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, 0x16); - } - // End of preferred settings - - DCDC->DCDC_VDD_1_REG |= ((1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_HV)) | - (1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_LV))); - - if ((dg_configPOWER_1V8_ACTIVE == 1) && cpm_1v8_state) { - DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV)); - DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV); - } - else { - DCDC->DCDC_V18_1_REG &= ~(REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV) | - REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); - } - - if (dg_configPOWER_1V8P == 1) { - DCDC->DCDC_V18P_1_REG |= (1 << REG_POS(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_HV)); - DCDC->DCDC_V18P_1_REG &= ~REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_LV); - } - else { - DCDC->DCDC_V18P_1_REG &= ~(REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_HV) | - REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_LV)); - } -} - -void hw_cpm_dcdc_on(void) -{ - DCDC->DCDC_V14_1_REG |= ((1 << REG_POS(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_HV)) | - (1 << REG_POS(DCDC, DCDC_V14_1_REG, DCDC_V14_ENABLE_LV))); - - REG_SETF(DCDC, DCDC_VDD_0_REG, DCDC_VDD_VOLTAGE, 0x10); // 1.2 V - - REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 1); - - // Trim the LDOs down to lowest possible voltage so DCDC can take over - CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_SETVDD); - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, 0x2); - - // Turn off LDOs - CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_ENABLE); - CRG_TOP->LDO_CTRL2_REG &= ~(REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V2_ON) | - REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON) | - REG_MSK(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_ON)); - - // Trim the LDOs back to normal levels - hw_cpm_reset_radio_vdd(); - CRG_TOP->LDO_CTRL1_REG &= ~REG_MSK(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD); -} - - -void hw_cpm_set_preferred_values(void) -{ - uint32_t reg; - - reg = CRG_TOP->CLK_16M_REG; - - REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_HPASS_FLT_EN, reg, 1); // Last review date: Feb 15, 2016 - 12:25:47 - REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_AMP_TRIM, reg, 5); - REG_SET_FIELD(CRG_TOP, CLK_16M_REG, XTAL16_CUR_SET, reg, 5); - - CRG_TOP->CLK_16M_REG = reg; - - REG_SETF(CRG_TOP, BANDGAP_REG, LDO_SLEEP_TRIM, 0x8); -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - REG_SETF(CRG_TOP, BANDGAP_REG, BYPASS_COLD_BOOT_DISABLE, 1); // Last review date: Feb 15, 2016 - 12:25:47 -#else - /* Hardcoding this since this will be used in AUTO mode as well (uartboot), where - * the AE datasheet is included (it doesn't contain this reg) - */ - volatile uint16_t *xtal16m_ctrl_reg = (volatile uint16_t *)0x50000056; - - /* The following code corresponds to (in BB): - REG_SET_FIELD(CRG_TOP, XTAL16M_CTRL_REG, XTAL16M_ENABLE_ZERO, reg, 1); - REG_SET_FIELD(CRG_TOP, XTAL16M_CTRL_REG, XTAL16M_AMP_REG_SIG_SEL, reg, 1); - */ - *xtal16m_ctrl_reg |= 0x100UL | 0x8UL; - - /* The following corresponds to - REG_SETF(CRG_TOP, BANDGAP_REG, LDO_SUPPLY_USE_BGREF, 1); - */ - CRG_TOP->BANDGAP_REG |= 0x4000UL; -#endif -} - -void hw_cpm_configure_xtal32k_pins(void) -{ - GPIO->P20_MODE_REG = 0x26; - GPIO->P21_MODE_REG = 0x26; -} - -void hw_cpm_configure_ext32k_pins(void) -{ - GPIO->P20_MODE_REG = 0x0; -} - -void hw_cpm_trigger_sw_cursor(void) -{ - if (dg_configUSE_SW_CURSOR == 1) { - if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) { - SW_CURSOR_SET = 1 << SW_CURSOR_PIN; - } - else { - SW_CURSOR_RESET = 1 << SW_CURSOR_PIN; - } - - SW_CURSOR_GPIO = 0x300; - - hw_cpm_delay_usec(50); - - if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) { - SW_CURSOR_RESET = 1 << SW_CURSOR_PIN; - } - - hw_cpm_setup_sw_cursor(); - } -} - -void hw_cpm_reset_system(void) -{ - __asm volatile ( " cpsid i " ); - - hw_watchdog_unregister_int(); - hw_watchdog_set_pos_val(1); - hw_watchdog_unfreeze(); - - while (1); -} - -void hw_cpm_reboot_system(void) -{ - __asm volatile ( " cpsid i " ); - - hw_watchdog_gen_RST(); - hw_watchdog_set_pos_val(1); - hw_watchdog_unfreeze(); - - while (1); -} - -void hw_cpm_assert_trigger_gpio(void) -{ - if (EXCEPTION_DEBUG == 1) { - if (dg_configLP_CLK_SOURCE == LP_CLK_IS_DIGITAL) { - hw_cpm_configure_ext32k_pins(); - } else if ((dg_configUSE_LP_CLK == LP_CLK_32000) - || (dg_configUSE_LP_CLK == LP_CLK_32768)) { - hw_cpm_configure_xtal32k_pins(); - } - hw_cpm_power_up_per_pd(); - hw_cpm_deactivate_pad_latches(); - - DBG_SET_HIGH(EXCEPTION_DEBUG, EXCEPTIONDBG); - } -} - -#define HW_CPM_ACTIVATE_BOD_PROTECTION \ -do { \ - uint16_t val = 0; \ - \ - REG_SETF(CRG_TOP, BOD_CTRL_REG, BOD_VDD_LVL, 1); /* VDD Level (700mV) */ \ - \ - if (hw_cpm_bod_enabled_in_tcs == 0) { \ - val = 0; \ - /* VBAT enable */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_VBAT_EN, val, 1); \ - /* 1V8 Flash enable */ \ - if ((dg_configPOWER_1V8_ACTIVE == 1) && (dg_configPOWER_1V8_SLEEP == 1)) { \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN, val, 1); \ - } \ - /* 1V8P enable */ \ - if (dg_configPOWER_1V8P == 1) { \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN, val, 1); \ - } \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_VDD_EN, val, 1); /* VDD enable */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_RESET_EN, val, 1); /* Reset enable */\ - CRG_TOP->BOD_CTRL2_REG = val; \ - } \ - else { \ - CRG_TOP->BOD_CTRL2_REG = hw_cpm_bod_enabled_in_tcs; \ - } \ -} while (0); - -void hw_cpm_activate_bod_protection(void) -{ - HW_CPM_ACTIVATE_BOD_PROTECTION -} - -void hw_cpm_activate_bod_protection_at_init(void) -{ - HW_CPM_ACTIVATE_BOD_PROTECTION -} - -void hw_cpm_configure_bod_protection(void) -{ - REG_SETF(CRG_TOP, BOD_CTRL_REG, BOD_VDD_LVL, 1); /* VDD Level (700mV) */ - - if (hw_cpm_bod_enabled_in_tcs == 0) { - /* VBAT enable */ - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_VBAT_EN); - - /* 1V8 Flash enable */ - if ((dg_configPOWER_1V8_ACTIVE == 1) && (dg_configPOWER_1V8_SLEEP == 1)) { - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); - } else { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); - } - - /* 1V8P enable */ - if (dg_configPOWER_1V8P == 1) { - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); - } else { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); - } - /* Generate Reset on a BOD event */ - REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_RESET_EN); - } - else { - CRG_TOP->BOD_CTRL2_REG = hw_cpm_bod_enabled_in_tcs; - } -} - -void hw_cpm_set_1v8_state(bool state) -{ - if ((dg_configPOWER_1V8_ACTIVE == 1) && (cpm_1v8_state != state)) { - uint32_t reg; - uint32_t dcdc_state; - - GLOBAL_INT_DISABLE(); - - reg = CRG_TOP->LDO_CTRL2_REG; - dcdc_state = (uint32_t)REG_GETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE); - -#if (dg_configPOWER_1V8_ACTIVE == 1) - cpm_1v8_state = state; -#endif - - if (!cpm_1v8_state) { - // Disable BOD for the 1V8 rail - if (dg_configUSE_BOD == 1) { - REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); - } - - // Deactivate 1V8 rail in LDOs - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, reg); - - if (dg_configPOWER_1V8_SLEEP == 1) { - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, - reg, 1); - } - - CRG_TOP->LDO_CTRL2_REG = reg; - - // Deactivate 1V8 rail in DCDC - if (dg_configUSE_DCDC == 1) { - // Disable DCDC to apply change - REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 0); - - DCDC->DCDC_V18_1_REG &= - ~(REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV) | - REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); - - // Restore DCDC - REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, dcdc_state); - } - } else { - // Restore 1V8 rail in LDOs - /* But not when DCDC is running... */ - if (dcdc_state != 1) { - REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, - reg, 1); - } - - if (dg_configPOWER_1V8_SLEEP == 1) { - REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, - reg); - } - - CRG_TOP->LDO_CTRL2_REG = reg; - - // Restore 1V8 rail in DCDC - if (dg_configUSE_DCDC == 1) { - DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, - DCDC_V18_ENABLE_HV)); - DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, - DCDC_V18_ENABLE_LV); - } - - // Restore BOD setup - if (dg_configUSE_BOD == 1) { - hw_cpm_delay_usec(200); - hw_cpm_configure_bod_protection(); - } - } - - GLOBAL_INT_RESTORE(); - } -} - -bool hw_cpm_get_1v8_state(void) -{ - return cpm_1v8_state; -} - -void hw_cpm_delay_usec(uint32_t usec) -{ - sys_clk_t sclk; - ahb_div_t hclk; - uint8_t freq; - - sclk = cm_sysclk; - hclk = cm_ahbclk; - freq = 16 >> hclk; - - /* Requested delay time must be > 0 usec */ - ASSERT_WARNING(usec != 0); - - /* - * ldr r3, [pc, #148] 2 cycles - * push {r4, lr} 2 cycles - * ldrb r1, [r3, #17] 2 cycles - * ldrb r2, [r3, #8] 2 cycles - * movs r3, #16 1 cycle - * asrs r3, r2 1 cycle - * uxtb r3, r2 1 cycle - * ---------- - * cmp r0, #0 4 cycles overhead in total - * bne.n 0x8003106 - * cpsid i - * bkpt 0x0002 - * - * Total: 11 cycles - */ - - __asm volatile( " cmp %[sclk], #1 \n" // 1 cycle : 1 (sysclk_RC16, sysclk_XTAL16M) - " ble start \n" // 1 or 3 cycles: 2/4 - " cmp %[sclk], #3 \n" // 1 cycle : 3 (sysclk_PLL48) - " bgt s96M \n" // 1 or 3 cycles: 4/6 - " blt s32M \n" // 1 or 3 cycles: 5/7 - "s48M: add r4, %[freq], %[freq] \n" // 1 cycle : 6 - " add %[freq], r4, %[freq] \n" // 1 cycle : 7 - " b start \n" // 3 cycles : 10 - "s96M: add r4, %[freq], %[freq] \n" // 1 cycle : 7 - " add %[freq], r4, %[freq] \n" // 1 cycle : 8 - " lsl %[freq], %[freq], #1 \n" // 1 cycle : 9 - " b start \n" // 3 cycles : 12 - "s32M: lsl %[freq], %[freq], #1 \n" // 1 cycle : 8 - /* -----------------------------------------------------*/ - /* Overhead up to this point: - * sysclk_RC16 : 15 cycles (error: 15/16 - 15 usec) - * sysclk_XTAL16M : 15 cycles (error: 15/16 - 15 usec) - * sysclk_XTAL32M : 19 cycles (error: 19/32 - 19/2 usec) - * sysclk_PLL48 : 21 cycles (error: 21/48 - 21/3 usec) - * sysclk_PLL96 : 23 cycles (error: 23/96 - 23/6 usec) - */ - "start: cmp %[freq], #16 \n" // 1 cycle : 1 - " bgt high \n" // 1 or 3 cycles: 2/4 - " blt low \n" // 1 or 3 cycles: 3/5 - " mov %[sclk], #4 \n" // 1 cycle : 4 - " b calc \n" // 3 cycles : 7 - "high: cmp %[freq], #24 \n" // 1 cycle : 5 - " bne c32M \n" // 1 or 3 cycles: 6/8 - " mov %[sclk], #6 \n" // 1 cycle : 7 - " b calc \n" // 3 cycles : 10 - "c32M: cmp %[freq], #32 \n" // 1 cycle : 9 - " bne c48M \n" // 1 or 3 cycles: 10/12 - " mov %[sclk], #8 \n" // 1 cycle : 11 - " b calc \n" // 3 cycles : 12 - "c48M: cmp %[freq], #48 \n" // 1 cycle : 13 - " bne c96M \n" // 1 or 3 cycles: 14/16 - " mov %[sclk], #12 \n" // 1 cycle : 15 - " b calc \n" // 3 cycles : 18 - "c96M: mov %[sclk], #24 \n" // 1 cycle : 17 - " b calc \n" // 3 cycles : 20 - "low: cmp %[freq], #1 \n" // 1 cycle : 6 - " bgt c2M \n" // 1 or 3 cycles: 7/9 - " lsr %[usec], %[usec], #2 \n" // 1 cycle : 8 - " b loop \n" // 3 cycles : 11 - "c2M: cmp %[freq], #2 \n" // 1 cycle : 10 - " bgt c3M \n" // 1 or 3 cycles: 11/13 - " lsr %[usec], %[usec], #1 \n" // 1 cycle : 12 - " b loop \n" // 3 cycles : 15 - "c3M: cmp %[freq], #3 \n" // 1 cycle : 14 - " bgt c4M \n" // 1 or 3 cycles: 15/17 - " lsr %[usec], %[usec], #1 \n" // 1 cycle : 16 - " b loop1 \n" // 3 cycles : 19 - "c4M: cmp %[freq], #4 \n" // 1 cycle : 18 - " bgt c6M \n" // 1 or 3 cycles: 19/21 - " b loop \n" // 3 cycles : 22 - "c6M: cmp %[freq],#6 \n" // 1 cycle : 22 - " bgt c8M \n" // 1 or 3 cycles: 23/25 - " b loop1 \n" // 3 cycles : 26 - "c8M: cmp %[freq], #8 \n" // 1 cycle : 26 - " bgt c12M \n" // 1 or 3 cycles: 27/29 - " mov %[sclk], #2 \n" // 1 cycle : 28 - " b calc \n" // 3 cycles : 31 - "c12M: mov %[sclk], #2 \n" // 1 cycle : 30 - " mul %[usec], %[sclk], %[usec] \n" // 1 cycle : 31 - /* Error: - * 1MHz: 11 cycles, 11usec - * 2MHz: 15 cycles, 7.5usec - * 3MHz: 19 cycles, 6.33usec - * 4MHz: 22 cycles, 5.5usec - * 6MHz: 26 cycles, 4.33usec - * 8MHz: 31 cycles, 3.875usec - * 12MHz: 31 cycles, 2.584usec - * 16MHz: 8 cycles, 0.5usec - * 24MHz: 11 cycles, 0.459usec - * 32MHz: 13 cycles, 0.406usec - * 48MHz: 19 cycles, 0.396usec - * 96MHz: 21 cycles, 0.219usec - * - * 1 loop of 4 cycles is --- 1 usec is # loops - * 1MHz: 4usec --- divide (usec) by 4 (up to 5usec error) - * 2MHz: 2usec --- divide (usec) by 2 (up to 2usec error) - * 4MHz: 1usec --- 1 loop ( 0*4 + 1*2, 0.5000usec error) - * 8MHz: 500nsec --- 2 loops ( 1*4 + 1*2, 0.2500usec error) - * 16MHz: 250nsec --- 4 loops ( 3*4 + 1*2, 0.5000usec error) - * 24MHz: 167nsec --- 6 loops ( 5*4 + 1*2, 0.0830usec error) - * 32MHz: 125nsec --- 8 loops ( 7*4 + 1*2, 0.0625usec error) - * 48MHz: 84nsec --- 12 loops (11*4 + 1*2, 0.0420usec error) - * 96MHz: 42nsec --- 24 loops (23*4 + 1*2, 0.0210usec error) - * - * 1 loop of 6 cycles is --- 1 usec is # loops - * 3MHz: 2usec --- divide (usec) by 2 (up to 3usec error) - * 6MHz: 1usec --- 1 loop ( 0*6 + 1*7, 0.1670usec error) - * 12MHz: 0.5usec --- 2 loops ( 1*6 + 1*7, 0.0830usec error) - * - * Cumulative error is: - * 1MHz: 11 + 5 = 16usec - * 2MHz: 7.5 + 2 = 9.5usec - * 3MHz: 6.33 + 3 = 9.33usec - * 4MHz: 5.5 + 0.5 = 6usec - * 6MHz: 4.33 + 0.167 = 4.5usec - * 8MHz: 3.875 + 0.25 = 4.125usec - * 12MHz: 2.584 + 0.083 = 2.67usec - * 16MHz: 0.5 + 0.5 = 1usec - * 24MHz: 0.459 + 0.083 = 0.541usec - * 32MHz: 0.406 + 0.0625 = 0.469usec - * 48MHz: 0.396 + 0.042 = 0.438usec - * 96MHz: 0.219 + 0.021 = 0.429usec - */ - "loop1: sub %[usec], %[usec], #1 \n" // 1 cycle - " nop \n" // 1 cycle - " nop \n" // 1 cycle - " bne loop1 \n" // 3 cycles except for the last one which is 1 - " b exit \n" // 3 cycles - "calc: mul %[usec], %[sclk], %[usec] \n" // 1 cycle - "loop: sub %[usec], %[usec], #1 \n" // 1 cycle - " bne loop \n" // 3 cycles except for the last one which is 1 - "exit: \n" - : - : /* output */ - [usec] "r" (usec), [freq] "r" (freq), [sclk] "r" (sclk) : /* inputs (%0, %1, %2) */ - "r4"); /* registers that are destroyed */ -} - -#endif /* dg_configUSE_HW_CPM */ -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c deleted file mode 100644 index b43a393b0..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup CRYPTO - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_crypto.c - * - * @brief Implementation of interrupt handling for the AES/Hash and ECC Engines. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC) - -#include "hw_crypto.h" - -#if (dg_configSYSTEMVIEW) -# include "SEGGER_SYSVIEW_FreeRTOS.h" -#else -# define SEGGER_SYSTEMVIEW_ISR_ENTER() -# define SEGGER_SYSTEMVIEW_ISR_EXIT() -#endif - -__RETAINED static hw_crypto_cb hw_crypto_aes_hash_cb; -__RETAINED static hw_crypto_cb hw_crypto_ecc_cb; - -void hw_crypto_enable_aes_hash_interrupt(hw_crypto_cb cb) -{ - /* A callback for the interrupt must be provided */ - ASSERT_ERROR(cb); - hw_crypto_aes_hash_cb = cb; - NVIC_EnableIRQ(CRYPTO_IRQn); -} - -void hw_crypto_enable_ecc_interrupt(hw_crypto_cb cb) -{ - /* A callback for the interrupt must be provided */ - ASSERT_ERROR(cb); - hw_crypto_ecc_cb = cb; - NVIC_EnableIRQ(CRYPTO_IRQn); -} - -void hw_crypto_disable_aes_hash_interrupt(void) -{ - hw_crypto_aes_hash_cb = NULL; - if (!hw_crypto_ecc_cb) { - NVIC_DisableIRQ(CRYPTO_IRQn); - } -} - -void hw_crypto_disable_ecc_interrupt(void) -{ - hw_crypto_ecc_cb = NULL; - if (!hw_crypto_aes_hash_cb) { - NVIC_DisableIRQ(CRYPTO_IRQn); - } -} - -void CRYPTO_Handler(void) -{ - SEGGER_SYSTEMVIEW_ISR_ENTER(); - - uint32_t status = AES_HASH->CRYPTO_STATUS_REG; - - /* In case both AES/HASH and ECC have triggered an interrupt, first the AES/HASH - will be served, and then the ISR will be called again since the ECC interrupt - source is only cleared by reading its status register */ - if (status & AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk) { - /* Clear AES/HASH interrupt source */ - AES_HASH->CRYPTO_CLRIRQ_REG = 0x1; - - if (hw_crypto_aes_hash_cb != NULL) { - hw_crypto_aes_hash_cb(status); - } - } else { - /* Clear ECC interrupt source */ - status = ECC->ECC_STATUS_REG; - - if (hw_crypto_ecc_cb != NULL) { - hw_crypto_ecc_cb(status); - } - } - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - - -#endif /* (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC) */ -/** - * \} - * \} - * \} - */ - diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c deleted file mode 100644 index a90e4460a..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c +++ /dev/null @@ -1,425 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup DMA - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_dma.c - * - * @brief Implementation of the DMA Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_DMA - -#include -#include - -#if (dg_configSYSTEMVIEW) -# include "SEGGER_SYSVIEW_FreeRTOS.h" -#else -# define SEGGER_SYSTEMVIEW_ISR_ENTER() -# define SEGGER_SYSTEMVIEW_ISR_EXIT() -#endif - -static struct hw_dma_callback_data { - hw_dma_transfer_cb callback; - void *user_data; -} dma_callbacks_user_data[8]; - -#define DMA_CHN_REG(reg, chan) ((volatile uint16 *)(&(reg)) + ((chan) * 8)) - -/** - * \brief Initialize DMA Channel - * - * \param [in] channel_setup pointer to struct of type DMA_Setup - * - */ -void hw_dma_channel_initialization(DMA_setup *channel_setup) -{ - volatile uint16 *dma_x_ctrl_reg; - volatile uint16 *dma_x_a_start_low_reg; - volatile uint16 *dma_x_a_start_high_reg; - volatile uint16 *dma_x_b_start_low_reg; - volatile uint16 *dma_x_b_start_high_reg; - volatile uint16 *dma_x_len_reg; - volatile uint16 *dma_x_int_reg; - uint32 src_address; - uint32 dest_address; - - /* Make sure the DMA channel length is not zero */ - ASSERT_WARNING(channel_setup->length > 0); - - // Look up DMAx_CTRL_REG address - dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_setup->channel_number); - - // Look up DMAx_A_STARTL_REG address - dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel_setup->channel_number); - - // Look up DMAx_A_STARTH_REG address - dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel_setup->channel_number); - - // Look up DMAx_B_STARTL_REG address - dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel_setup->channel_number); - - // Look up DMAx_B_STARTH_REG address - dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel_setup->channel_number); - - // Look up DMAX_LEN_REG address - dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel_setup->channel_number); - - // Look up DMAX_INT - dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel_setup->channel_number); - - // Make sure DMA channel is disabled first - REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, HW_DMA_STATE_DISABLED); - - // Set DMAx_CTRL_REG width provided settings, but do not start the channel. - // Start the channel with the "dma_channel_enable" function separately. - *dma_x_ctrl_reg = - channel_setup->bus_width | - channel_setup->irq_enable | - channel_setup->dreq_mode | - channel_setup->b_inc | - channel_setup->a_inc | - channel_setup->circular | - channel_setup->dma_prio | - channel_setup->dma_idle | - channel_setup->dma_init; - - // Set DMA_REQ_MUX_REG for the requested channel / trigger combination - if (channel_setup->dma_req_mux != HW_DMA_TRIG_NONE) { - switch (channel_setup->channel_number) { - case HW_DMA_CHANNEL_0: - case HW_DMA_CHANNEL_1: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - case HW_DMA_CHANNEL_2: - case HW_DMA_CHANNEL_3: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - case HW_DMA_CHANNEL_4: - case HW_DMA_CHANNEL_5: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - case HW_DMA_CHANNEL_6: - case HW_DMA_CHANNEL_7: - GLOBAL_INT_DISABLE(); - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA67_SEL, channel_setup->dma_req_mux); - GLOBAL_INT_RESTORE(); - break; - default: - break; - } -#if dg_configDMA_DYNAMIC_MUX || (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - /* - * When different DMA channels are used for same device it is important - * that only one trigger is set for specific device at a time. - * Having same trigger for different channels can cause unpredictable results. - * Following code also should help when SPI1 is assigned to non 0 channel. - */ - GLOBAL_INT_DISABLE(); - switch (channel_setup->channel_number) { - case HW_DMA_CHANNEL_6: - case HW_DMA_CHANNEL_7: - if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL) == channel_setup->dma_req_mux) { - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, HW_DMA_TRIG_NONE); - } - /* no break */ - case HW_DMA_CHANNEL_4: - case HW_DMA_CHANNEL_5: - if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL) == channel_setup->dma_req_mux) { - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, HW_DMA_TRIG_NONE); - } - /* no break */ - case HW_DMA_CHANNEL_2: - case HW_DMA_CHANNEL_3: - if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL) == channel_setup->dma_req_mux) { - REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, HW_DMA_TRIG_NONE); - } - break; - case HW_DMA_CHANNEL_0: - case HW_DMA_CHANNEL_1: - default: - break; - } - GLOBAL_INT_RESTORE(); -#endif - } - -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) - //Set REQ_SENSE bit of i2c, USB and Uart peripherals TX path - if (((channel_setup->dma_req_mux == HW_DMA_TRIG_UART_RXTX) || - (channel_setup->dma_req_mux == HW_DMA_TRIG_UART2_RXTX) || - (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C_RXTX) || - (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C2_RXTX) || - (channel_setup->dma_req_mux == HW_DMA_TRIG_USB_RXTX)) && - (channel_setup->channel_number & 1)) {//odd channels used for TX - REG_SET_FIELD(DMA, DMA0_CTRL_REG, REQ_SENSE, *dma_x_ctrl_reg, 1); - } -#endif - src_address = DA15000_phy_addr(channel_setup->src_address); - dest_address = DA15000_phy_addr(channel_setup->dest_address); - - // Set source address registers - *dma_x_a_start_low_reg = (src_address & 0xffff); - *dma_x_a_start_high_reg = (src_address >> 16); - - // Set destination address registers - *dma_x_b_start_low_reg = (dest_address & 0xffff); - *dma_x_b_start_high_reg = (dest_address >> 16); - - // Set IRQ number of transfers - if (channel_setup->irq_nr_of_trans > 0) { - // If user explicitly set this number use it - *dma_x_int_reg = channel_setup->irq_nr_of_trans - 1; - } else { - // If user passed 0, use transfer length to fire interrupt after transfer ends - *dma_x_int_reg = channel_setup->length - 1; - } - - // Set the transfer length - *dma_x_len_reg = (channel_setup->length) - 1; - - if (channel_setup->irq_enable) - dma_callbacks_user_data[channel_setup->channel_number].callback = channel_setup->callback; - else - dma_callbacks_user_data[channel_setup->channel_number].callback = NULL; - dma_callbacks_user_data[channel_setup->channel_number].user_data = channel_setup->user_data; -} - -void hw_dma_channel_update_source(HW_DMA_CHANNEL channel, void *addr, uint16_t length, - hw_dma_transfer_cb cb) -{ - uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr); - - dma_callbacks_user_data[channel].callback = cb; - - // Look up DMAx_A_STARTL_REG address - volatile uint16 *dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel); - - // Look up DMAx_A_STARTH_REG address - volatile uint16 *dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel); - - // Look up DMAX_LEN_REG address - volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); - - - volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); - - // Set source address registers - *dma_x_a_start_low_reg = (phy_addr & 0xffff); - *dma_x_a_start_high_reg = (phy_addr >> 16); - - *dma_x_int_reg = length - 1; - - // Set the transfer length - *dma_x_len_reg = length - 1; -} - -void hw_dma_channel_update_destination(HW_DMA_CHANNEL channel, void *addr, uint16_t length, - hw_dma_transfer_cb cb) -{ - uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr); - - dma_callbacks_user_data[channel].callback = cb; - - // Look up DMAx_B_STARTL_REG address - volatile uint16 *dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel); - - // Look up DMAx_B_STARTH_REG address - volatile uint16 *dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel); - - // Look up DMAX_LEN_REG address - volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); - volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); - - // Set destination address registers - *dma_x_b_start_low_reg = (phy_addr & 0xffff); - *dma_x_b_start_high_reg = (phy_addr >> 16); - - *dma_x_int_reg = length - 1; - - // Set the transfer length - *dma_x_len_reg = length - 1; -} - -void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix) -{ - volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); - - *dma_x_int_reg = int_ix; -} - -/** - * \brief Enable or disable a DMA channel - * - * \param [in] channel_number DMA channel number to start/stop - * \param [in] dma_on enable/disable DMA channel - * - */ -void hw_dma_channel_enable(HW_DMA_CHANNEL channel_number, HW_DMA_STATE dma_on) -{ - volatile uint16 *dma_x_ctrl_reg; - - // Look up DMAx_CTRL_REG address - dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_number); - - - if (dma_on == HW_DMA_STATE_ENABLED) { - uint16_t dma_ctrl = *dma_x_ctrl_reg; - - REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, dma_ctrl, 1); - if (dma_callbacks_user_data[channel_number].callback) { - REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, dma_ctrl, 1); - } - // Start the chosen DMA channel - *dma_x_ctrl_reg = dma_ctrl; - NVIC_EnableIRQ(DMA_IRQn); - } else { - // Stop the chosen DMA channel - REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, 0); - REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, *dma_x_ctrl_reg, 0); - } -} - -static inline void dma_helper(HW_DMA_CHANNEL channel_number, uint16_t len, bool stop_dma) -{ - hw_dma_transfer_cb cb; - - NVIC_DisableIRQ(DMA_IRQn); - cb = dma_callbacks_user_data[channel_number].callback; - if (stop_dma) { - dma_callbacks_user_data[channel_number].callback = NULL; - hw_dma_channel_enable(channel_number, HW_DMA_STATE_DISABLED); - } - if (cb) { - cb(dma_callbacks_user_data[channel_number].user_data, len); - } - NVIC_EnableIRQ(DMA_IRQn); -} - -bool hw_dma_channel_active(void) -{ - int dma_on; - - dma_on = REG_GETF(DMA, DMA0_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA1_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA2_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA3_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA4_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA5_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA6_CTRL_REG, DMA_ON); - dma_on |= REG_GETF(DMA, DMA7_CTRL_REG, DMA_ON); - - return (dma_on == 1); -} - -/** - * \brief Capture DMA Interrupt Handler - * - * Calls user interrupt handler - * - */ -void DMA_Handler(void) -{ - SEGGER_SYSTEMVIEW_ISR_ENTER(); - - uint16_t risen; - uint16_t i; - volatile uint16 *dma_x_len_reg; - volatile uint16 *dma_x_int_reg; - volatile uint16 *dma_x_ctrl_reg; - - risen = DMA->DMA_INT_STATUS_REG; - - for (i = 0; risen != 0 && i < 8; ++i, risen >>= 1) { - if (risen & 1) { - bool stop; - - /* - * DMAx_INT_REG shows after how many transfers the interrupt - * is generated - */ - dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, i); - - /* - * DMAx_LEN_REG shows the length of the DMA transfer - */ - dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, i); - - dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, i); - - /* - * Stop DMA if: - * - transfer is completed - * - mode is not circular - */ - stop = (*dma_x_int_reg == *dma_x_len_reg) - && (!REG_GET_FIELD(DMA, DMA0_CTRL_REG, CIRCULAR, *dma_x_ctrl_reg)); - DMA->DMA_CLEAR_INT_REG = 1 << i; - dma_helper(i, *dma_x_int_reg + 1, stop); - } - } - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - -void hw_dma_channel_stop(HW_DMA_CHANNEL channel_number) -{ - // Stopping DMA will clear DMAx_IDX_REG so read it before - volatile uint16 *dma_x_idx_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); - dma_helper(channel_number, *dma_x_idx_reg, true); -} - -uint16_t hw_dma_transfered_bytes(HW_DMA_CHANNEL channel_number) -{ - volatile uint16 *dma_x_int_reg = dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); - - return *dma_x_int_reg; -} - -#endif /* dg_configUSE_HW_DMA */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c deleted file mode 100644 index 299d4fe53..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c +++ /dev/null @@ -1,301 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup GPADC - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_gpadc.c - * - * @brief Implementation of the GPADC Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_GPADC - - -#include -#include -#include - -#if (dg_configSYSTEMVIEW) -# include "SEGGER_SYSVIEW_FreeRTOS.h" -#else -# define SEGGER_SYSTEMVIEW_ISR_ENTER() -# define SEGGER_SYSTEMVIEW_ISR_EXIT() -#endif - -static hw_gpadc_interrupt_cb intr_cb = NULL; - -int16_t hw_gpadc_differential_gain_error __RETAINED; -int16_t hw_gpadc_single_ended_gain_error __RETAINED; - -void hw_gpadc_init(const gpadc_config *cfg) -{ - GPADC->GP_ADC_CTRL_REG = 0; - GPADC->GP_ADC_CTRL2_REG = 0; - GPADC->GP_ADC_CTRL3_REG = 0x40; // default value for GP_ADDC_EN_DEL - - NVIC_DisableIRQ(ADC_IRQn); - - hw_gpadc_configure(cfg); -} - -void hw_gpadc_reset(void) -{ - GPADC->GP_ADC_CTRL_REG = REG_MSK(GPADC, GP_ADC_CTRL_REG, GP_ADC_EN); - GPADC->GP_ADC_CTRL2_REG = 0; - GPADC->GP_ADC_CTRL3_REG = 0x40; // default value for GP_ADDC_EN_DEL - - NVIC_DisableIRQ(ADC_IRQn); -} - -void hw_gpadc_configure(const gpadc_config *cfg) -{ - if (cfg) { - hw_gpadc_set_clock(cfg->clock); - hw_gpadc_set_input_mode(cfg->input_mode); - hw_gpadc_set_input(cfg->input); - hw_gpadc_set_sample_time(cfg->sample_time); - hw_gpadc_set_continuous(cfg->continous); - hw_gpadc_set_interval(cfg->interval); - hw_gpadc_set_input_attenuator_state(cfg->input_attenuator); - hw_gpadc_set_chopping(cfg->chopping); - hw_gpadc_set_oversampling(cfg->oversampling); - } -} - -void hw_gpadc_register_interrupt(hw_gpadc_interrupt_cb cb) -{ - intr_cb = cb; - - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_MINT, 1); - - NVIC_EnableIRQ(ADC_IRQn); -} - -void hw_gpadc_unregister_interrupt(void) -{ - NVIC_DisableIRQ(ADC_IRQn); - - REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_MINT, 0); - - intr_cb = NULL; -} - -void hw_gpadc_adc_measure(void) -{ - hw_gpadc_start(); - while (hw_gpadc_in_progress()); - hw_gpadc_clear_interrupt(); -} - -void hw_gpadc_calibrate(void) -{ - uint16_t adc_off_p, adc_off_n; - uint32_t diff; - int i; - - for (i = 0; i < 5; i++) { // Try up to five times to calibrate correctly. - hw_gpadc_set_offset_positive(0x200); - hw_gpadc_set_offset_negative(0x200); - hw_gpadc_set_mute(true); - if (dg_configUSE_SOC == 1) { - hw_gpadc_set_oversampling(4); - } - - hw_gpadc_set_sign_change(false); - hw_gpadc_adc_measure(); - if (dg_configUSE_SOC == 1) { - adc_off_p = ((hw_gpadc_get_value_without_gain() >> 6) - 0x200); - } else { - adc_off_p = hw_gpadc_get_value() - 0x200; - } - - hw_gpadc_set_sign_change(true); - hw_gpadc_adc_measure(); - if (dg_configUSE_SOC == 1) { - adc_off_n = ((hw_gpadc_get_value_without_gain() >> 6) - 0x200); - } else { - adc_off_n = hw_gpadc_get_value() - 0x200; - } - - if (hw_gpadc_get_input_mode() == HW_GPADC_INPUT_MODE_SINGLE_ENDED) { - hw_gpadc_set_offset_positive(0x200 - 2 * adc_off_p); - hw_gpadc_set_offset_negative(0x200 - 2 * adc_off_n); - } else { - hw_gpadc_set_offset_positive(0x200 - adc_off_p); - hw_gpadc_set_offset_negative(0x200 - adc_off_n); - } - - hw_gpadc_set_sign_change(false); - - // Verify calibration result - hw_gpadc_adc_measure(); - if (dg_configUSE_SOC == 1) { - adc_off_n = (hw_gpadc_get_value_without_gain() >> 6); - } else { - adc_off_n = hw_gpadc_get_value(); - } - - if (adc_off_n > 0x200) { - diff = adc_off_n - 0x200; - } - else { - diff = 0x200 - adc_off_n; - } - - if (diff < 0x8) { - break; - } - else if (i == 4) { - ASSERT_WARNING(0); // Calibration does not converge. - } - } - - hw_gpadc_set_mute(false); -} - -void ADC_Handler(void) -{ - SEGGER_SYSTEMVIEW_ISR_ENTER(); - - if (intr_cb) { - intr_cb(); - } else { - hw_gpadc_clear_interrupt(); - } - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - -void hw_gpadc_test_measurements(void) -{ - uint32_t val[16]; - uint32_t mid = 0, diff_n = 0, diff_p = 0; - volatile bool loop = true; - - if (hw_gpadc_get_input_mode() != HW_GPADC_INPUT_MODE_SINGLE_ENDED) { - hw_gpadc_set_input_mode(HW_GPADC_INPUT_MODE_SINGLE_ENDED); - hw_gpadc_set_ldo_constant_current(true); - hw_gpadc_set_ldo_dynamic_current(true); - hw_gpadc_calibrate(); - } - hw_gpadc_reset(); - hw_gpadc_set_input_mode(HW_GPADC_INPUT_MODE_SINGLE_ENDED); - hw_gpadc_set_ldo_constant_current(true); - hw_gpadc_set_ldo_dynamic_current(true); - hw_gpadc_set_sample_time(15); - hw_gpadc_set_chopping(true); - hw_gpadc_set_input(HW_GPADC_INPUT_SE_VBAT); -// hw_gpadc_set_oversampling(1); // 2 samples - hw_gpadc_set_oversampling(2); // 4 samples - - while (loop) { - for (volatile int i = 0; i < 4; i++); // wait ~1.5usec - for (int j = 0; j < 16; j++) { - hw_gpadc_adc_measure(); - -// val[j] = hw_gpadc_get_raw_value() >> 4; // 2 samples - val[j] = hw_gpadc_get_raw_value() >> 3; // 4 samples - - if (j == 0) { - mid = 0; - diff_p = 0; - diff_n = 0; - } - - mid += val[j]; - - if (j == 15) { - mid /= 16; - for (int k = 0; k < 16; k++) { - if ((mid > val[k]) && (diff_p < mid - val[k])) { - diff_p = mid - val[k]; - } - - if ((mid < val[k]) && (diff_n < val[k] - mid)) { - diff_n = val[k] - mid; - } - } - } - } - } -} - -uint16_t hw_gpadc_get_raw_value(void) -{ - uint16_t adc_raw_res = GPADC->GP_ADC_RESULT_REG; - int32_t res = adc_raw_res; - - if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) { - if (hw_gpadc_pre_check_for_gain_error()) { - int16_t gain_trim; - const HW_GPADC_INPUT_MODE input_mode = hw_gpadc_get_input_mode(); - - if (input_mode == HW_GPADC_INPUT_MODE_SINGLE_ENDED) { - gain_trim = hw_gpadc_single_ended_gain_error; - /* Gain correction */ - res = 0xFFFFU * adc_raw_res / (0xFFFFU + gain_trim); - /* Boundary check */ - if ((uint32_t)res > UINT16_MAX) { - return UINT16_MAX; - } - } else if (input_mode == HW_GPADC_INPUT_MODE_DIFFERENTIAL) { - gain_trim = hw_gpadc_differential_gain_error; - res = (int16_t)(adc_raw_res ^ 0x8000); - /* Gain correction */ - res = 0xFFFF * res / (0xFFFF + gain_trim); - /* Boundary check for lower limit */ - if (res < INT16_MIN) { - return 0; /* INT16_MIN ^ 0x8000 */ - } - /* Boundary check for upper limit */ - if (res > INT16_MAX) { - return UINT16_MAX; /* INT16_MAX ^ 0x8000 */ - } - res ^= 0x8000; - } - } - } - - return res; -} - -#endif /* dg_configUSE_HW_GPADC */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c deleted file mode 100644 index ca5ab57db..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c +++ /dev/null @@ -1,302 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup GPIO - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_gpio.c - * - * @brief Implementation of the GPIO Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_GPIO - - -#include -#include - -/* Register adresses */ -#define PX_DATA_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_DATA_REG)) + _port) -#define PX_DATA_REG(_port) *PX_DATA_REG_ADDR(_port) -#define PX_SET_DATA_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_SET_DATA_REG)) + _port) -#define PX_SET_DATA_REG(_port) *PX_SET_DATA_REG_ADDR(_port) -#define PX_RESET_DATA_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_RESET_DATA_REG)) + _port) -#define PX_RESET_DATA_REG(_port) *PX_RESET_DATA_REG_ADDR(_port) -#define PXX_MODE_REG_ADDR(_port, _pin) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P00_MODE_REG)) + (_port * 8) + _pin) -#define PXX_MODE_REG(_port, _pin) *PXX_MODE_REG_ADDR(_port, _pin) -#define PX_PADPWR_CTRL_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_PADPWR_CTRL_REG)) + _port) -#define PX_PADPWR_CTRL_REG(_port) *PX_PADPWR_CTRL_REG_ADDR(_port) - -/* on FPGA we cannot read the state of an output GPIO */ - -#ifdef FPGA_PAD_LOOPBACK_BROKEN -static uint16_t Px_DATA_REG_cache[5]; -#endif - -#if (dg_configIMAGE_SETUP == PRODUCTION_MODE) && (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) - #warning "GPIO assignment monitoring is active in PRODUCTION build!" -#endif - -static volatile uint8_t GPIO_status[HW_GPIO_NUM_PORTS] = { 0 }; - -const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS] = { - HW_GPIO_PORT_0_NUM_PINS, HW_GPIO_PORT_1_NUM_PINS, - HW_GPIO_PORT_2_NUM_PINS, HW_GPIO_PORT_3_NUM_PINS, - HW_GPIO_PORT_4_NUM_PINS }; - -/* - * Global Functions - **************************************************************************************** - */ - -void hw_gpio_configure(const gpio_config cfg[]) -{ -#if dg_configIMAGE_SETUP == DEVELOPMENT_MODE - int num_pins = 0; - uint8_t set_mask[HW_GPIO_NUM_PORTS] = { 0 }; -#endif - - if (!cfg) { - return; - } - - while (cfg->pin != 0xFF) { - uint8_t port = cfg->pin >> 4; - uint8_t pin = cfg->pin & 0x0F; - -#if dg_configIMAGE_SETUP == DEVELOPMENT_MODE - if (port >= HW_GPIO_NUM_PORTS || pin >= hw_gpio_port_num_pins[port]) { - /* - * invalid port or pin number specified, it was either incorrectly specified - * of cfg was not terminated properly using HW_GPIO_PINCONFIG_END so we're - * reading garbage - */ - __BKPT(0); - } - - if (++num_pins > HW_GPIO_NUM_PINS) { - /* - * trying to set more pins than available, perhaps cfg was not terminated - * properly using HW_GPIO_PINCONFIG_END? - */ - __BKPT(0); - } - - if (set_mask[port] & (1 << pin)) { - /* - * trying to set pin which has been already set by this call which means - * there is duplicated pin in configuration - does not make sense - */ - __BKPT(0); - } - - set_mask[port] |= (1 << pin); -#endif - - if (cfg->reserve) { - hw_gpio_reserve_and_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high); - } else { - hw_gpio_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high); - } - - cfg++; - } -} - -bool hw_gpio_reserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ - if ((GPIO_status[port] & (1 << pin))) { - return false; - } - - GPIO_status[port] |= (1 << pin); - - return true; -} - -bool hw_gpio_reserve_and_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function, bool high) -{ - if (!hw_gpio_reserve_pin(port, pin)) { - return false; - } - - hw_gpio_configure_pin(port, pin, mode, function, high); - - return true; -} - -void hw_gpio_unreserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ - GPIO_status[port] &= ~(1 << pin); -} - -static void hw_gpio_verify_reserved(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ -#if (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) - if (!(GPIO_status[port] & (1 << pin))) { - // If debugger stops at this line, there is configuration problem - // pin is used without being reserved first - __BKPT(0); /* this pin has not been previously reserved! */ - } -#endif // (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1) -} - - -void hw_gpio_set_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function) -{ - hw_gpio_verify_reserved(port, pin); - - PXX_MODE_REG(port, pin) = mode | function; -} - -void hw_gpio_get_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE* mode, - HW_GPIO_FUNC* function) -{ - uint16_t val; - - hw_gpio_verify_reserved(port, pin); - - val = PXX_MODE_REG(port, pin); - *mode = val & 0x0700; - *function = val & 0x00ff; -} - -void hw_gpio_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode, - HW_GPIO_FUNC function, const bool high) -{ - hw_gpio_verify_reserved(port, pin); - - if (high) - hw_gpio_set_active(port, pin); - else - hw_gpio_set_inactive(port, pin); - - hw_gpio_set_pin_function(port, pin, mode, function); -} - -void hw_gpio_configure_pin_power(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_POWER power) -{ - uint16_t padpwr; - - padpwr = PX_PADPWR_CTRL_REG(port); - padpwr &= ~(1 << pin); - if (power == HW_GPIO_POWER_VDD1V8P) { - padpwr |= (1 << pin); - } - PX_PADPWR_CTRL_REG(port) = padpwr; -} - -void hw_gpio_set_active(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ - hw_gpio_verify_reserved(port, pin); - - PX_SET_DATA_REG(port) = 1 << pin; -#ifdef FPGA_PAD_LOOPBACK_BROKEN - Px_DATA_REG_cache[port] |= 1 << pin; -#endif -} - -void hw_gpio_set_inactive(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ - hw_gpio_verify_reserved(port, pin); - - PX_RESET_DATA_REG(port) = 1 << pin; -#ifdef FPGA_PAD_LOOPBACK_BROKEN - Px_DATA_REG_cache[port] &= ~(1 << pin); -#endif -} - -bool hw_gpio_get_pin_status(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ -#ifdef FPGA_PAD_LOOPBACK_BROKEN - HW_GPIO_MODE mode; - HW_GPIO_FUNC function; -#endif - hw_gpio_verify_reserved(port, pin); - -#ifdef FPGA_PAD_LOOPBACK_BROKEN - hw_gpio_get_pin_function(port, pin, &mode, &function); - if (mode != HW_GPIO_MODE_OUTPUT) - return !!(PX_DATA_REG(port) & (1 << pin)); - else - return !!(Px_DATA_REG_cache[port] & (1 << pin)); -#else - return ( (PX_DATA_REG(port) & (1 << pin)) != 0 ); -#endif -} - -void hw_gpio_toggle(HW_GPIO_PORT port, HW_GPIO_PIN pin) -{ - hw_gpio_verify_reserved(port, pin); - - if (hw_gpio_get_pin_status(port, pin)) - hw_gpio_set_inactive(port, pin); - else - hw_gpio_set_active(port, pin); -} - -int hw_gpio_get_pins_with_function(HW_GPIO_FUNC func, uint8_t *buf, int buf_size) -{ - int count = 0; - int port; - int pin; - HW_GPIO_MODE mode; - HW_GPIO_FUNC pin_func; - - - for (port = 0; port < HW_GPIO_NUM_PORTS; ++port) { - for (pin = 0; pin < hw_gpio_port_num_pins[port]; ++pin) { - hw_gpio_get_pin_function(port, pin, &mode, &pin_func); - if (pin_func != func) { - continue; - } - if (count < buf_size && buf != NULL) { - buf[count] = (uint8_t) ((port << 4) | pin); - } - count++; - } - } - return count; -} - -#endif /* dg_configUSE_HW_GPIO */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c deleted file mode 100644 index 53dd3203c..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c +++ /dev/null @@ -1,172 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup Exception_Handlers - * \{ -*/ - -/** - **************************************************************************************** - * - * @file hw_hard_fault.c - * - * @brief HardFault handler. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#include -#include -#include "sdk_defs.h" -#include "hw_hard_fault.h" -#include "hw_watchdog.h" -#include "hw_cpm.h" - - - -/* - * Global variables - */ -uint32_t hardfault_event_data[9] __attribute__((section("hard_fault_info"))); - -/* - * Local variables - */ - - -/* - * This is the base address in Retention RAM where the stacked information will be copied. - */ -#define STATUS_BASE (0x7FC5600) - -/* - * Compilation switch to enable verbose output on HardFault - */ -#ifndef VERBOSE_HARDFAULT -# define VERBOSE_HARDFAULT 0 -#endif - - -/* - * Function definitions - */ - -/** -* \brief HardFault handler implementation. During development it will copy the system's status -* to a predefined location in memory. In release mode, it will cause a system reset. -* -* \param [in] hardfault_args The system's status when the HardFault event occurred. -* -* \return void -* -*/ -#if (dg_configCODE_LOCATION == NON_VOLATILE_IS_FLASH) -__attribute__((section("text_retained"))) -#endif -void HardFault_HandlerC(unsigned long *hardfault_args) -{ - // Stack frame contains: - // r0, r1, r2, r3, r12, r14, the return address and xPSR - // - Stacked R0 = hf_args[0] - // - Stacked R1 = hf_args[1] - // - Stacked R2 = hf_args[2] - // - Stacked R3 = hf_args[3] - // - Stacked R12 = hf_args[4] - // - Stacked LR = hf_args[5] - // - Stacked PC = hf_args[6] - // - Stacked xPSR= hf_args[7] - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { - hw_watchdog_freeze(); // Stop WDOG - - ENABLE_DEBUGGER; - - *(volatile unsigned long *)(STATUS_BASE ) = hardfault_args[0]; // R0 - *(volatile unsigned long *)(STATUS_BASE + 0x04) = hardfault_args[1]; // R1 - *(volatile unsigned long *)(STATUS_BASE + 0x08) = hardfault_args[2]; // R2 - *(volatile unsigned long *)(STATUS_BASE + 0x0C) = hardfault_args[3]; // R3 - *(volatile unsigned long *)(STATUS_BASE + 0x10) = hardfault_args[4]; // R12 - *(volatile unsigned long *)(STATUS_BASE + 0x14) = hardfault_args[5]; // LR - *(volatile unsigned long *)(STATUS_BASE + 0x18) = hardfault_args[6]; // PC - *(volatile unsigned long *)(STATUS_BASE + 0x1C) = hardfault_args[7]; // PSR - *(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)hardfault_args; // Stack Pointer - - *(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR - *(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR - *(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR - *(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR - *(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR - *(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR - - if (VERBOSE_HARDFAULT) { - printf("HardFault Handler:\r\n"); - printf("- R0 = 0x%08lx\r\n", hardfault_args[0]); - printf("- R1 = 0x%08lx\r\n", hardfault_args[1]); - printf("- R2 = 0x%08lx\r\n", hardfault_args[2]); - printf("- R3 = 0x%08lx\r\n", hardfault_args[3]); - printf("- R12 = 0x%08lx\r\n", hardfault_args[4]); - printf("- LR = 0x%08lx\r\n", hardfault_args[5]); - printf("- PC = 0x%08lx\r\n", hardfault_args[6]); - printf("- xPSR= 0x%08lx\r\n", hardfault_args[7]); - } - - hw_cpm_assert_trigger_gpio(); - - while (1); - } - else { -# ifdef PRODUCTION_DEBUG_OUTPUT -# if (USE_WDOG) - WDOG->WATCHDOG_REG = 0xC8; // Reset WDOG! 200 * 10.24ms active time for UART to finish printing! -# endif - - dbg_prod_output(1, hardfault_args); -# endif // PRODUCTION_DEBUG_OUTPUT - - hardfault_event_data[0] = HARDFAULT_MAGIC_NUMBER; - hardfault_event_data[1] = hardfault_args[0]; // R0 - hardfault_event_data[2] = hardfault_args[1]; // R1 - hardfault_event_data[3] = hardfault_args[2]; // R2 - hardfault_event_data[4] = hardfault_args[3]; // R3 - hardfault_event_data[5] = hardfault_args[4]; // R12 - hardfault_event_data[6] = hardfault_args[5]; // LR - hardfault_event_data[7] = hardfault_args[6]; // PC - hardfault_event_data[8] = hardfault_args[7]; // PSR - - hw_cpm_reboot_system(); // Force reset - - while (1); - } -} - -/** - * \} - * \} - * \} - * */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c deleted file mode 100644 index f9bc9efd2..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c +++ /dev/null @@ -1,1008 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup OTPC - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_otpc.c - * - * @brief Implementation of the OTP Controller Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_OTPC - - - -#include -#include "hw_otpc.h" - - -/* - * Local variables - */ - -/* - * 1MHz: 1 cycle = 1us ==> - * 25ns : 1us, 200ns : 1us, 500ns : 1us, 1us : 2us, 5us : 5us, 2us : 3us, blanc : 1us - * - * 2MHz: 1 cycle = 500ns ==> - * 25ns : 500ns, 200ns : 500ns, 500ns : 1us, 1us : 1.5us, 5us : 5us, 2us : 2.5us, blanc : 500ns - * - * 3MHz: 1 cycle = 333ns ==> - * 25ns : 333ns, 200ns : 333ns, 500ns : 666ns, 1us : 1.33us, 5us : 5us, 2us : 2.33us, blanc : 333ns - * - * 4MHz: 1 cycle = 250ns ==> - * 25ns : 250ns, 200ns : 250ns, 500ns : 750ns, 1us : 1.25ns, 5us : 5us, 2us : 2.25ns, blanc : 250ns - * - * 6MHz: 1 cycle = 167ns ==> - * 25ns : 167ns, 200ns : 333ns, 500ns : 667ns, 1us : 1.167ns, 5us : 5us, 2us : 2.167ns, blanc : 167ns - * - * 8MHz: 1 cycle = 125ns ==> - * 25ns : 125ns, 200ns : 250ns, 500ns : 625ns, 1us : 1.125ns, 5us : 5us, 2us : 2.125ns, blanc : 125ns - * - * 12MHz: 1 cycle = 83.33ns ==> - * 25ns : 83ns, 200ns : 250ns, 500ns : 583ns, 1us : 1.083ns, 5us : 5us, 2us : 2.083ns, blanc : 167ns - * - * 16MHz: 1 cycle = 62.5ns ==> - * 25ns : 62ns, 200ns : 250ns, 500ns : 562ns, 1us : 1.062ns, 5us : 5us, 2us : 2.062ns, blanc : 125ns - * - * 24MHz: 1 cycle = 41.67ns ==> - * 25ns : 41ns, 200ns : 208ns, 500ns : 541ns, 1us : 1.041ns, 5us : 5us, 2us : 2.041ns, blanc : 125ns - * - * 32MHz: 1 cycle = 31.25ns ==> - * 25ns : 31ns, 200ns : 219ns, 500ns : 531ns, 1us : 1.031ns, 5us : 5us, 2us : 2.031ns, blanc : 125ns - * - * 48MHz: 1 cycle = 41.67ns ==> - * 25ns : 41ns, 200ns : 208ns, 500ns : 521ns, 1us : 1.021ns, 5us : 5us, 2us : 2.021ns, blanc : 125ns - * - */ -const uint32_t tim1[11] = { - /* 1 MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 2MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 9 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 3MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 14 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 4MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 19 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 6MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 29 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 8MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 39 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 12MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 2 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 59 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 16MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 3 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 8 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - ( 79 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 32 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 24MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 4 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 12 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (119 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 48 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 32MHz */ - ( 0 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 6 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 16 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 32 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (159 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 64 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos), - /* 48MHz */ - ( 1 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos) | - ( 9 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos) | - ( 24 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos) | - ( 48 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos) | - (239 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos) | - ( 96 << OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos) -}; - -static const uint8_t tim2[HW_OTPC_SYS_CLK_FREQ_48 + 1] = - { 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 5 }; - - -/* - * Forward declarations - */ - - - -/* - * Inline helpers - */ - -/** - * Wait for programming to finish. - */ -__STATIC_INLINE void wait_for_prog_done(void) -{ - while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PRDY))) - ; -} - -/** - * Wait for AREAD or APROG to finish. - */ -__STATIC_INLINE void wait_for_auto_done(void) -{ - while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, ARDY))) - ; -} - -/** - * Check for correctable or uncorrectable programming error. - */ -__STATIC_INLINE bool have_prog_error(void) -{ - return OTPC->OTPC_STAT_REG & - (HW_OTPC_FIELD_VAL(STAT, PERR_UNC, 1) | HW_OTPC_FIELD_VAL(STAT, PERR_COR, 1)); -} - -/* - * Assertion macros - */ - -/* - * Make sure that the OTP clock is enabled - */ -#define ASSERT_WARNING_OTP_CLK_ENABLED \ - ASSERT_WARNING(CRG_TOP->CLK_AMBA_REG & REG_MSK(CRG_TOP, CLK_AMBA_REG, OTP_ENABLE)) - -/* - * Make sure that the OTPC is in given state - */ -#define ASSERT_WARNING_OTPC_MODE(s) \ - ASSERT_WARNING((OTPC->OTPC_MODE_REG & HW_OTPC_REG_FIELD_MASK(MODE, MODE)) \ - == HW_OTPC_FIELD_VAL(MODE, MODE, s)) - -/* - * Make sure that the cell address is valid - */ -#define ASSERT_CELL_OFFSET_VALID(off) \ - ASSERT_WARNING(off < 0x2000) - -/* - * Make sure val is non-zero and less than maximum - */ -#define ASSERT_WARNING_NONZERO_RANGE(val, maximum) \ - do { \ - ASSERT_WARNING(val); \ - ASSERT_WARNING((val) < (maximum)); \ - } while (0) - - -/* - * Function definitions - */ - -__RETAINED_CODE HW_OTPC_SYS_CLK_FREQ hw_otpc_convert_sys_clk_mhz(uint32_t clk_freq) -{ - HW_OTPC_SYS_CLK_FREQ f; - - /* Value to convert must be at most 48 MHz */ - ASSERT_WARNING(clk_freq <= 48); - - if (--clk_freq < 4) { - /* - * cover 1, 2, 3, 4 - */ - f = (HW_OTPC_SYS_CLK_FREQ)clk_freq; - } else { - clk_freq -= 5; - /* - * remaining valid values: - * - 0 (initially 6) - * - 2 (initially 8) - * - 6 (initially 12) - * - 10 (initially 16) - * - 18 (initially 24) - * - 26 (initially 32) - * - 42 (initially 48) - */ - - /* no odd valid values any more */ - ASSERT_WARNING(!(clk_freq & 1)); - - clk_freq >>= 1; - /* - * remaining valid values: - * - 0 (initially 6) - * - 1 (initially 8) - * - 3 (initially 12) - * - 5 (initially 16) - * - 9 (initially 24) - * - 13 (initially 32) - * - 21 (initially 48) - */ - if (clk_freq > 8) { - /* - * remaining valid values: - * - 9 (initially 24) - * - 13 (initially 32) - * - 21 (initially 48) - */ - if (clk_freq > 16) { - ASSERT_WARNING(clk_freq == 21); - - f = HW_OTPC_SYS_CLK_FREQ_48; - } else { - clk_freq -= 8; - /* - * remaining valid values: - * - 1 (initially 24) - * - 5 (initially 32) - */ - ASSERT_WARNING((clk_freq == 1) || (clk_freq == 5)); - - if (clk_freq < 4) - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_24; - else - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_32; - } - } else { - /* - * remaining valid values: - * - 0 (initially 6) - * - 1 (initially 8) - * - 3 (initially 12) - * - 5 (initially 16) - */ - if (clk_freq > 2) { - ASSERT_WARNING((clk_freq == 3) || (clk_freq == 5)); - - if (clk_freq > 4) - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_16; - else - f = (HW_OTPC_SYS_CLK_FREQ)HW_OTPC_SYS_CLK_FREQ_12; - } else { - f = (HW_OTPC_SYS_CLK_FREQ)(HW_OTPC_SYS_CLK_FREQ_6 + clk_freq); - } - } - } - - return f; -} - - -void hw_otpc_disable(void) -{ - /* - * Enable OTPC clock - */ - hw_otpc_init(); - - /* - * set OTPC to stand-by mode - */ - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - - /* - * Disable OTPC clock - */ - hw_otpc_close(); -} - - -__RETAINED_CODE void hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ clk_speed) -{ - ASSERT_WARNING_OTP_CLK_ENABLED; - - /* - * Set access speed - */ - ASSERT_WARNING(clk_speed <= HW_OTPC_SYS_CLK_FREQ_48); - - OTPC->OTPC_TIM1_REG = tim1[clk_speed]; - HW_OTPC_REG_SETF(TIM2, CC_T_BCHK, tim2[clk_speed]); -} - - -void hw_otpc_power_save(uint32_t inactivity_period) -{ - /* Only go to power save for an inactivity_period < 1024 */ - ASSERT_WARNING(inactivity_period < 1024); - - HW_OTPC_REG_SETF(TIM2, CC_STBY_THR, inactivity_period); -} - - -uint32_t hw_otpc_num_of_rr(void) -{ - unsigned int i; - - volatile uint32_t *ptr = (volatile uint32_t *)MEMORY_OTP_BASE; - - ASSERT_WARNING_OTP_CLK_ENABLED; - - // STBY mode - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - - // The access will be performed in the spare rows - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 1); - - // MREAD mode - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); - - // Read Records - i = 0; - while ((i < MAX_RR_AVAIL) && (ptr[0x9e - 4 * i] & 0x1)) { - i++; - } - - // STBY mode - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - - // Select the normal memory array - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 0); - - return i; -} - -static bool manual_prog_verify(uint32_t cell_offset, uint32_t pword_l, uint32_t pword_h) -{ - uint32_t val_l, val_h, old_mode = OTPC->OTPC_MODE_REG; - uint32_t *addr = hw_otpc_cell_to_mem(cell_offset); - - /* we have to go through standby mode first */ - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - __DMB(); - HW_OTPC_REG_SETF(MODE, ERR_RESP_DIS, 1); - __DMB(); - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); - - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { - HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually (can only happen if a previous read has not checked/cleared it) - } - /* - * Read cell in manual mode, as 2 32-bit values (little-endian) - */ - val_l = addr[0]; - val_h = addr[1]; - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - __DMB(); - OTPC->OTPC_MODE_REG = old_mode; - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { - HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually - return false; - } - return (pword_h == val_h) && (pword_l == val_l); -} - -/* - * Set to 1 to manually verify the programmed cell value, if the auto-verification fails. - */ -#define MANUAL_PROG_VERIFICATION 1 - -bool hw_otpc_manual_word_prog(uint32_t cell_offset, uint32_t pword_l, uint32_t pword_h, bool use_rr) -{ - int i; - bool ret = true; - - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - ASSERT_CELL_OFFSET_VALID(cell_offset); - - /* - * Program the data regs - */ - OTPC->OTPC_PWORDL_REG = pword_l; - OTPC->OTPC_PWORDH_REG = pword_h; - - /* - * Start programming - */ - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MPROG); - OTPC->OTPC_PCTRL_REG = - HW_OTPC_FIELD_VAL(PCTRL, WADDR, cell_offset) | - HW_OTPC_FIELD_VAL(PCTRL, PSTART, 1); - wait_for_prog_done(); - - /* - * Check and retry up to 10 times - */ - i = 0; - while (have_prog_error()) { - if (i == 10) { - break; - } - i = i + 1; - - OTPC->OTPC_PCTRL_REG = - HW_OTPC_FIELD_VAL(PCTRL, WADDR, cell_offset) | - HW_OTPC_FIELD_VAL(PCTRL, PSTART, 1) | - HW_OTPC_FIELD_VAL(PCTRL, PRETRY, 1); - - wait_for_prog_done(); - } - - if (i == 10) { - ret = false; - if (MANUAL_PROG_VERIFICATION) - ret = manual_prog_verify(cell_offset, pword_l, pword_h); - - if (use_rr && !ret) { - do { - // Reset state - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - - // Abort if the writing was done in the spare area - if (OTPC->OTPC_MODE_REG & HW_OTPC_REG_FIELD_MASK(MODE, USE_SP_ROWS)) { - break; - } - - // Write the repair record to the spare area - if (!hw_otpc_write_rr(cell_offset, pword_l, pword_h)) { - break; - } - - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - // force reloading - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_MREAD); - - ret = true; - break; - } while (0); - } - } - - HW_OTPC_REG_SETF(MODE, MODE, HW_OTPC_MODE_STBY); - - return ret; -} - -bool hw_otpc_manual_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool use_rr) -{ - uint32_t w, c, ncells, off, val; - bool ret = true; - const uint32_t* addr; - - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - ASSERT_CELL_OFFSET_VALID(cell_offset); - - if (num_of_words == 0) - return true; // early exit - - /* index in p_data[] */ - w = 0; - off = cell_offset; - if (cell_word == HW_OTPC_WORD_HIGH) { - /* - * read low 32-bit word so that we program the same value - */ - addr = hw_otpc_cell_to_mem(cell_offset); - - hw_otpc_manual_read_on(use_rr); - /* little-endian */ - val = addr[0]; - hw_otpc_manual_read_off(); - - if (!hw_otpc_manual_word_prog(off++, val, p_data[w++], use_rr)) - return false; - - ncells = (num_of_words - 1) >> 1; - } else { - ncells = num_of_words >> 1; - } - - for (c = 0; c < ncells; c++, off++, w += 2) { - if (!hw_otpc_manual_word_prog(off, p_data[w], p_data[w + 1], use_rr)) - return false; - } - - if (w < num_of_words) { - /* - * read high 32-bit word so that we program the same value - */ - addr = hw_otpc_cell_to_mem(off); - - hw_otpc_manual_read_on(use_rr); - /* little-endian */ - val = addr[1]; - hw_otpc_manual_read_off(); - - if (!hw_otpc_manual_word_prog(off, p_data[w++], val, use_rr)) - return false; - } - - ASSERT_WARNING(w == num_of_words); - - return ret; -} - -bool hw_otpc_write_rr(uint32_t cell_addr, uint32_t pword_l, uint32_t pword_h) -{ - uint32_t repair_cnt; - bool ret = false; - - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - // Get the number of used Repair Records - repair_cnt = hw_otpc_num_of_rr(); - - // Abort if all repair records are being used - if (repair_cnt < MAX_RR_AVAIL) { - do { - // The access will be performed in the spare rows - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 1); - - // Write the data to the spare area - if (!hw_otpc_manual_word_prog(0x4F - repair_cnt - 1, - pword_l, pword_h, false)) { - break; - } - - // Write the header of the repair record to the spare area - if (!hw_otpc_manual_word_prog(0x4F - repair_cnt, - 1 | (cell_addr << 1), 0x00000000, false)) { - break; - } - - ret = true; - } while (0); - - // Return to the normal memory array - HW_OTPC_REG_SETF(MODE, USE_SP_ROWS, 0); - - if (ret) { - /* - * Request the reloading of the repair records at the next - * enabling of the OTP cell - */ - HW_OTPC_REG_SETF(MODE, RLD_RR_REQ, 1); - } - } - - return ret; -} - - -void hw_otpc_manual_read_on(bool spare_rows) -{ - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - /* - * Place the OTPC in manual read mode - */ - if (spare_rows) { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_MREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else { - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_MREAD; - } -} - - -void hw_otpc_manual_read_off(void) -{ - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_MREAD); - - /* - * Place the OTPC in STBY mode - */ - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_STBY; -} - - -bool hw_otpc_dma_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) -{ - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - ASSERT_CELL_OFFSET_VALID(cell_offset); - - /* - * Make sure that the size is valid - */ - ASSERT_WARNING(num_of_words); - ASSERT_WARNING(num_of_words < 16384); - - /* - * Set up DMA - */ - unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); - - if (IS_SYSRAM_ADDRESS(p_data) || - (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#if dg_configEXEC_MODE != MODE_IS_CACHED - } else if (IS_CACHERAM_ADDRESS(p_data)) { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#endif - } else { - /* - * Destination address can only reside in RAM or Cache RAM, but in case of remapped - * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) - */ - ASSERT_WARNING(0); - } - - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words-1; - - /* - * Start DMA programming - */ - if (spare_rows) { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1); - } - - wait_for_auto_done(); - - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PERR_UNC)) { - return false; - } - - return true; -} - - -void hw_otpc_dma_read(uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) -{ - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - ASSERT_CELL_OFFSET_VALID(cell_offset); - - /* - * Make sure that the size is valid - */ - ASSERT_WARNING(num_of_words); - ASSERT_WARNING(num_of_words < 16384); - - /* - * Set up DMA - */ - unsigned int remap_type = REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0); - - if (IS_SYSRAM_ADDRESS(p_data) || - (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#if dg_configEXEC_MODE != MODE_IS_CACHED - } else if (IS_CACHERAM_ADDRESS(p_data)) { - OTPC->OTPC_AHBADR_REG = DA15000_phy_addr((uint32_t)p_data); -#endif - } else { - /* - * Destination address can only reside in RAM or Cache RAM, but in case of remapped - * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) - */ - ASSERT_WARNING(0); - } - - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words-1; - - /* - * Start DMA programming - */ - if (spare_rows) { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_DMA, 1); - } - - wait_for_auto_done(); -} - - -bool hw_otpc_fifo_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) -{ - unsigned int i; - - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - ASSERT_CELL_OFFSET_VALID(cell_offset); - - ASSERT_WARNING_NONZERO_RANGE(num_of_words, 16384); - - /* - * Set up FIFO - */ - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words-1; - - /* - * Perform programming via FIFO - */ - if (spare_rows) { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else { - OTPC->OTPC_MODE_REG = HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_APROG); - } - - for (i = 0; i < num_of_words; i++) { - while (HW_OTPC_REG_GETF(STAT, FWORDS) == 8) - ; - OTPC->OTPC_FFPRT_REG = p_data[i]; // Write FIFO data - } - - /* - * Wait for completion - */ - wait_for_auto_done(); - - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, PERR_UNC)) { - return false; - } - - return true; -} - - -bool hw_otpc_fifo_read(uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_word, - uint32_t num_of_words, bool spare_rows) -{ - unsigned int i; - - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - ASSERT_CELL_OFFSET_VALID(cell_offset); - - ASSERT_WARNING_NONZERO_RANGE(num_of_words, 16384); - - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { - HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually (can only happen if a previous read has not checked/cleared it) - } - - /* - * Set up FIFO - */ - OTPC->OTPC_CELADR_REG = (cell_offset << 1) | (cell_word == HW_OTPC_WORD_HIGH); - OTPC->OTPC_NWORDS_REG = num_of_words-1; - - /* - * Perform reading via FIFO - */ - if (spare_rows) { - OTPC->OTPC_MODE_REG = - HW_OTPC_FIELD_VAL(MODE, MODE, HW_OTPC_MODE_AREAD) | - HW_OTPC_FIELD_VAL(MODE, USE_SP_ROWS, 1); - } - else { - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_AREAD; - } - - for (i = 0; i < num_of_words; i++) { - while (HW_OTPC_REG_GETF(STAT, FWORDS) == 0) - ; - p_data[i] = OTPC->OTPC_FFPRT_REG; - } - - /* - * Wait for completion - */ - wait_for_auto_done(); - - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, RERROR)) { - HW_OTPC_REG_SETF(STAT, RERROR, 1); //This bit need to be cleared manually - return false; - } - - return true; -} - - -void hw_otpc_prepare(uint32_t num_of_bytes) -{ - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - ASSERT_WARNING_NONZERO_RANGE(num_of_bytes, 65536); - - /* - * Set up image size - */ - OTPC->OTPC_NWORDS_REG = ((num_of_bytes + 3) >> 2) - 1; - - /* - * Enable OTP_COPY - */ - GLOBAL_INT_DISABLE(); - CRG_TOP->SYS_CTRL_REG |= 1 << REG_POS(CRG_TOP, SYS_CTRL_REG, OTP_COPY); - GLOBAL_INT_RESTORE(); -} - - -void hw_otpc_cancel_prepare(void) -{ - ASSERT_WARNING_OTP_CLK_ENABLED; - - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - /* - * Disable OTP_COPY - */ - GLOBAL_INT_DISABLE(); - CRG_TOP->SYS_CTRL_REG &= ~REG_MSK(CRG_TOP, SYS_CTRL_REG, OTP_COPY); - GLOBAL_INT_RESTORE(); -} - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// TEST FUNCTIONALITY -//////////////////////////////////////////////////////////////////////////////////////////////////// - - -/** - * \brief Execution of the test. - * - * \return The test result. - *
    - *
  • 0, if the test succeeded - *
  • 1, if the test 1 failed - *
- * - */ -static int hw_otpc_core_test(int mode) -{ - ASSERT_WARNING_OTPC_MODE(HW_OTPC_MODE_STBY); - - /* - * Put OTPC in the proper test mode - */ - HW_OTPC_REG_SETF(MODE, MODE, mode); - - /* - * Wait end of test - */ - while (!(OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, TRDY))) - ; - - - /* - * Check result - */ - if (OTPC->OTPC_STAT_REG & HW_OTPC_REG_FIELD_MASK(STAT, TERROR)) { - return 1; - } - - return 0; -} - - -int hw_otpc_blank(void) -{ - return hw_otpc_core_test(HW_OTPC_MODE_TBLANK); -} - - -int hw_otpc_tdec(void) -{ - return hw_otpc_core_test(HW_OTPC_MODE_TDEC); -} - - -int hw_otpc_twr(void) -{ - return hw_otpc_core_test(HW_OTPC_MODE_TWR); -} - - -#endif /* dg_configUSE_HW_OTPC */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c deleted file mode 100644 index 862367c1c..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c +++ /dev/null @@ -1,177 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup QSPI - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_qspi.c - * - * @brief Implementation of the QSPI Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_QSPI - -#include -#include "hw_qspi.h" - -__RETAINED_RW uint8_t dummy_num[] = { 0, 1, 2, 0, 3 }; - -#if (dg_configFLASH_POWER_DOWN == 1) -__attribute__((section("text_retained"))) -#endif -void hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) -{ - switch (mode) { - case HW_QSPI_BUS_MODE_SINGLE: - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE); - break; - case HW_QSPI_BUS_MODE_DUAL: - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_DUAL); - break; - case HW_QSPI_BUS_MODE_QUAD: - QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD); - hw_qspi_set_io2_output(false); - hw_qspi_set_io3_output(false); - break; - } -} - -__attribute__((section("text_retained"))) void hw_qspi_set_automode(bool automode) -{ - if (automode) { - const uint32_t burst_cmd_a = QSPIC->QSPIC_BURSTCMDA_REG; - const uint32_t burst_cmd_b = QSPIC->QSPIC_BURSTCMDB_REG; - const uint32_t status_cmd = QSPIC->QSPIC_STATUSCMD_REG; - const uint32_t erase_cmd_b = QSPIC->QSPIC_ERASECMDB_REG; - const uint32_t burstbrk = QSPIC->QSPIC_BURSTBRK_REG; - if (GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_INST_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_ADR_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_DMY_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_EXT_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_ERS_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_WEN_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_SUS_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_RES_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_EAD_TX_MD) == HW_QSPI_BUS_MODE_QUAD || - GETBITS32(QSPIC, QSPIC_BURSTBRK_REG, burstbrk, QSPIC_BRK_TX_MD) == HW_QSPI_BUS_MODE_QUAD) { - hw_qspi_set_io2_output(false); - hw_qspi_set_io3_output(false); - } - } - HW_QSPIC_REG_SETF(CTRLMODE, AUTO_MD, automode); -} - -void hw_qspi_set_wrapping_burst_instruction(uint8_t inst, HW_QSPI_WRAP_LEN len, - HW_QSPI_WRAP_SIZE size) -{ - HW_QSPIC_REG_SETF(BURSTCMDA, INST_WB, inst); - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE, size) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN, len) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_MD, 1); -} - -void hw_qspi_set_dummy_bytes_count(uint8_t count) -{ - if (count == 3) { - HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1); - } else { - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, - dummy_num[count]); - } -} - -void hw_qspi_erase_block(uint32_t addr) -{ - if (!hw_qspi_get_automode()) { - hw_qspi_set_automode(true); - } - // Wait for previous erase to end - while (hw_qspi_get_erase_status() != 0) { - } - - if (hw_qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32) { - addr >>= 12; - } else { - addr >>= 4; - } - // Setup erase block page - HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr); - // Fire erase - HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); -} - -void hw_qspi_set_pads(HW_QSPI_SLEW_RATE rate, HW_QSPI_DRIVE_CURRENT current) -{ - QSPIC->QSPIC_GP_REG = - BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_SLEW, rate) | - BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_DRV, current); -} - -void hw_qspi_init(const qspi_config *cfg) -{ - hw_qspi_enable_clock(); - hw_qspi_set_automode(false); - hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - hw_qspi_set_io2_output(true); - hw_qspi_set_io2(1); - hw_qspi_set_io3_output(true); - hw_qspi_set_io3(1); - - if (cfg) { - hw_qspi_set_address_size(cfg->address_size); - hw_qspi_set_clock_mode(cfg->idle_clock); - hw_qspi_set_read_sampling_edge(cfg->sampling_edge); - } -} - -#endif /* dg_configUSE_HW_QSPI */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c deleted file mode 100644 index 68f2caf26..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c +++ /dev/null @@ -1,1512 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup RF - * \{ - */ - -/** - ***************************************************************************************** - * - * @file hw_rf.c - * - * @brief Radio module (RF) Low Level Driver API definition. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************************** - */ - -#if dg_configUSE_HW_RF - - -#include "hw_rf.h" -#include "sdk_defs.h" -#include "hw_cpm.h" -#include "hw_gpio.h" - -#if (dg_configSYSTEMVIEW) -# include "SEGGER_SYSVIEW_FreeRTOS.h" -#else -# define SEGGER_SYSTEMVIEW_ISR_ENTER() -# define SEGGER_SYSTEMVIEW_ISR_EXIT() -#endif - -#if dg_configUSE_HW_COEX == 1 -#include "hw_coex.h" -#endif - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -#define KMODE_ALPHA_ACAD_PREF 0x0410 -#define KMODE_ALPHA_AA_PREF 0x0416 - -#define DF1_DAC_CHECK_VALUE 32 -#define DF1_DGAIN_THR0 16 -#define DF1_DGAIN_THR1 24 -#define DF1_DGAIN_THR2 32 -#endif - -/* User callbacks (defined as weak functions) definitions */ -bool hw_rf_preoff_cb(void) __attribute__((weak)); -void hw_rf_postconf_cb(void) __attribute__((weak)); -void hw_rf_precalib_cb(void) __attribute__((weak)); -void hw_rf_postcalib_cb(void) __attribute__((weak)); -void hw_rf_apply_tcs_cb(void) __attribute__((weak)); -uint64_t hw_rf_get_start_iff_time(void) __attribute__((weak)); -bool hw_rf_check_iff_timeout(uint64_t start_time) __attribute__((weak)); - -#if dg_configFEM == FEM_SKY66112_11 -#include "hw_fem_sky66112-11.h" -#endif - -typedef enum rf_states_e { - RF_ST_OFF = 0, - RF_ST_ON, - RF_ST_CONFIG, - RF_ST_WAIT_NEXT1, - RF_ST_WAIT_NEXT2 -} rf_states_e; - -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A -typedef enum { - IFF_MODE_CTRL_BLE = 0, - IFF_MODE_CTRL_FTDF = 1, - IFF_MODE_CTRL_COMBO = 2 -} iff_mode_ctrl_e; - -typedef enum { - IFF_MODE_OVR_BLE = 1, - IFF_MODE_OVR_FTDF = 2 -} iff_mode_ovr_e; - -typedef enum { - MGC_MODE_CTRL_BLE_GAUSSDAC = 0, - MGC_MODE_CTRL_BLE_TXDAC = 1, - MGC_MODE_CTRL_FTDF = 2 -} mgc_mode_ctrl_e; - -#endif - -/** RF status bitmap. */ -typedef uint8_t rf_request_t; - -/** Indicates whether FTDF MAC has turned RF on. */ -#define RF_REQUEST_FTDF_ON (1 << 0) - -/** Indicates whether BLE MAC has turned RF on. */ -#define RF_REQUEST_BLE_ON (1 << 1) - - - -static rf_request_t rf_request __RETAINED; -static rf_states_e rf_state __RETAINED; -hw_rf_tx_power_luts_t rf_tx_power_luts __RETAINED; - -/* Variables used for holding previous reg values during gain calib */ -static uint32_t rf_cntrl_timer14_reg_set_offset; -static uint32_t rf_cntrl_timer_7_reg_value; -static uint32_t rf_cal_ctrl_reg_value; -static uint32_t rf_mgain_ctrl_reg_value; -static uint32_t rf_mgain_ctrl2_reg_value; -static uint16_t rf_synth_ctrl2_ble_reg_value; -static uint16_t rf_synth_ctrl2_ftdf_reg_value; - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -static uint8_t kmoda_cal __RETAINED; -__RETAINED_RW static uint32_t gg_cal_modified = 128; -static uint32_t rf_enable_config14_ble_reg_value; -static uint32_t rf_enable_config15_ble_reg_value; -static uint32_t rf_enable_config14_ftdf_reg_value; -static uint32_t rf_enable_config15_ftdf_reg_value; -static uint16_t rf_bmcw_reg_value; -static uint16_t rf_vcocal_ctrl_reg_value; -#else -static uint16_t rf_enable_config14_reg_value; -static uint16_t rf_enable_config15_reg_value; -static uint16_t rf_overrule_reg_value; -static uint16_t rf_enable_config23_ble_reg_value; -static uint16_t rf_enable_config23_ftdf_reg_value; -static uint16_t rf_enable_config45_ble_reg_value; -static uint16_t rf_enable_config45_ftdf_reg_value; -#endif -bool hw_rf_system_init(void) -{ - bool calib_succeeded; - - rf_state = RF_ST_OFF; - rf_request = 0; - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - /* Initially set kmoda_cal to its preferred settings value */ - if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) - && (CHIP_IS_AE))) { - kmoda_cal = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, - KMOD_ALPHA_BLE); - } -#endif - -#if dg_configCOEX_ENABLE_CONFIG == 1 - hw_coex_init(); -#endif - /* Apply tcs and preferred settings */ - hw_rf_apply_tcs_cb(); - hw_rf_set_recommended_settings(); - - /* Perform calibration */ - calib_succeeded = hw_rf_calibration(); - -#ifndef CONFIG_USE_BLE - /* Force disable the ble, making the ftdf the only requester */ - REG_SET_BIT(CRG_TOP, FORCE_SLEEP_REG, FORCE_BLE_SLEEP); -#endif -#ifndef CONFIG_USE_FTDF - /* Force disable the ftdf, making the ble the only requester */ - REG_SET_BIT(CRG_TOP, FORCE_SLEEP_REG, FORCE_FTDF_SLEEP); -#endif - - /* System is ready to be used */ - return calib_succeeded; -} - -/** - * \brief Preferred settings 680 radio - * - */ -void hw_rf_set_recommended_settings(void) -{ - - // Preferred Settings File for DCTMON - // Device : DA14680AA - // Package : All packages, no dependency on package. - // Last change date : June 18, 2015 - 18:00:48 - // Last change item : Register: RF_KMOD_ALPHA_REG, Field: KMOD_ALPHA_FTDF, Value: 0x10 - // File date : June 18, 2015 - 19:16:16 - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - if (((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)) - || (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, E))) { - REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0030, 0x00F5); - REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); - - // MP - REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_10_REG, 0xFF00, 0x182E); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_11_REG, 0xFF00, 0x1830); - RFCU_POWER->RF_CNTRL_TIMER_12_REG = 0x3C; - RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x163C; - RFCU_POWER->RF_CNTRL_TIMER_15_REG = 0x183C; - RFCU_POWER->RF_CNTRL_TIMER_16_REG = 0x2207; - RFCU_POWER->RF_CNTRL_TIMER_17_REG = 0x410; - RFCU_POWER->RF_CNTRL_TIMER_18_REG = 0x218; - RFCU_POWER->RF_CNTRL_TIMER_19_REG = 0x218; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x1E00); - RFCU_POWER->RF_CNTRL_TIMER_20_REG = 0x508; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_21_REG, 0x00FF, 0x44); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_22_REG, 0x00FF, 0x40); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_23_REG, 0x00FF, 0x52); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x1B08); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x1A10); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x1818); - REG_SET_MASKED(RFCU, RF_CP_CTRL_BLE_REG, 0x0F0F, 0x7575); - REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); - REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0202, 0x01D0); - REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL3_REG, 0x00FF, 0xDCE4); - REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_BLE_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_FTDF_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_BLE_REG, 0x03E0, 0x01E0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_FTDF_REG, 0x03E0, 0x01E0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_BLE_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_FTDF_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG24_FTDF_REG, 0x03E0, 0x01A0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG25_FTDF_REG, 0x03E0, 0x0060); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_BLE_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_FTDF_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_BLE_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_FTDF_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_BLE_REG, 0x001F, 0x00F3); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_FTDF_REG, 0x001F, 0x00F3); - RFCU_POWER->RF_ENABLE_CONFIG42_BLE_REG = 0x210; - RFCU_POWER->RF_ENABLE_CONFIG42_FTDF_REG = 0x210; - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_BLE_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_FTDF_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_BLE_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_FTDF_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_BLE_REG, 0x001F, 0x0017); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_FTDF_REG, 0x001F, 0x0017); - REG_SET_MASKED(DEM, RF_FTDF_CTRL1_REG, 0xC000, 0x87C0); - REG_SET_MASKED(DEM, RF_FTDF_CTRL2_REG, 0x0700, 0x6810); - REG_SET_MASKED(DEM, RF_FTDF_CTRL5_REG, 0x1FFF, 0x4708); - REG_SET_MASKED(DEM, RF_FTDF_LOOP_GAIN_DS_REG, 0x00FF, 0x0060); - REG_SET_MASKED(DEM, RF_FTDF_LOOP_GAIN_PD_REG, 0x00FF, 0x0060); - PLLDIG->RF_KMOD_ALPHA_REG = KMODE_ALPHA_ACAD_PREF; - REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x001F, 0x00C0); - REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_BLE_REG, 0x0F0F, 0x7474); - REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); - - - PLLDIG->RF_MGAIN_CTRL2_REG = 0x0006; - REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_BLE_REG, 0x1C00, 0x1403); - - - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL2_REG, 0x001F, 0x0000); - REG_SET_MASKED(PLLDIG, RF_MSKMOD_CTRL1_REG, 0x0003, 0x0003); - REG_SET_MASKED(RFCU, RF_REF_OSC_BLE_REG, 0x7FC0, 0x302C); - REG_SET_MASKED(RFCU, RF_REF_OSC_FTDF_REG, 0x7FC0, 0x302C); - REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); - - REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x4800, 0x4000); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x14C0, 0x108B); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x00C0, 0x009B); - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_1_REG, 0x003F, 0x003B); - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_2_REG, 0x003F, 0x0037); - RFCU->RF_TX_PWR_LUT_3_REG = 0x01F6; - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_4_REG, 0x003F, 0x0036); - PLLDIG->RF_VCO_CALCAP_BIT14_REG = 0xD59D; - - /* FTDF specific */ - REG_SETF(DEM, RF_FTDF_CTRL5_REG, RSSITH, 1800); - } - - REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); -#else - REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0330, 0x01F5); - REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); - REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); - REG_SET_MASKED(DEM, RF_CCA_RSSITH_REG, 0xE000, 0xE708); - - RFCU_POWER->RF_CNTRL_TIMER_10_REG = 0x0A42; - RFCU_POWER->RF_CNTRL_TIMER_11_REG = 0x0A44; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_12_REG, 0x00FF, 0x0050); - RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x0850; - RFCU_POWER->RF_CNTRL_TIMER_14_REG = 0x1858; - RFCU_POWER->RF_CNTRL_TIMER_15_REG = 0x0A50; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_16_REG, 0xFF00, 0x1207); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x0F00); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_21_REG, 0x00FF, 0x0044); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_22_REG, 0x00FF, 0x0040); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_23_REG, 0x00FF, 0x0052); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x0D08); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x0C10); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x0A18); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x0A18); - RFCU->RF_CP_CTRL_BLE_REG = 0x3535; - REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); - REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0402, 0x05D0); - REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG16_REG, 0x001F, 0x0014); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, 0x03E0, 0x0000); - RFCU_POWER->RF_ENABLE_CONFIG42_REG = 0x0210; - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, 0x03E0, 0x0060); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_BLE_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_FTDF_REG, 0x001F, 0x0015); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_BLE_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_FTDF_REG, 0x001F, 0x0016); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_BLE_REG, 0x001F, 0x0017); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_FTDF_REG, 0x001F, 0x0017); - REG_SET_MASKED(DEM, RF_FTDF_CTRL1_REG, 0xCC00, 0x4BC0); - REG_SET_MASKED(DEM, RF_FTDF_CTRL4_REG, 0x0500, 0xC6A7); - REG_SET_MASKED(DEM, RF_FTDF_SIGDET_CTRL_REG, 0x1FFF, 0x0BC3); - REG_SET_MASKED(PLLDIG, RF_KMOD_ALPHA_BLE_REG, 0x0FC0, 0x030C); - PLLDIG->RF_KMOD_ALPHA_FTDF_REG = 0x000D; - RFCU->RF_LF_RES_CTRL_BLE_REG = 0x3434; - REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x0040, 0x0080); - REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); - RFCU->RF_LO_IQ_TRIM_REG = 0x0001; - PLLDIG->RF_MGAIN_CTRL3_REG = 0x0050; - REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_FTDF_REG, 0xFF00, 0x5000); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); - REG_SET_MASKED(RFCU, RF_OVERRULE_REG, 0x3C00, 0x5800); - REG_SET_MASKED(RFCU, RF_REF_OSC_FTDF_REG, 0x7FFF, 0x31EB); - REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); - REG_SET_MASKED(RFCU, RF_SPARE1_BLE_REG, 0x0038, 0x0018); - REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x0008, 0x0008); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x20C0, 0x304B); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x0040, 0x004B); - RFCU->RF_TX_PWR_LUT_5_REG = 0x09FF; - REG_SET_MASKED(RFCU, RF_TXDAC_CTRL_REG, 0x0040, 0x0000); -#endif -} - - - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -/** - * \brief Modulation gain calibration - * - * \param[in] bool, true for BLE, false for FTDF - * \param[in] bool, true to enable RFCAL IRQ, false to poll - * - */ -static void hw_rf_modulation_gain_calibration_start(bool mode_ble) -{ - - uint32_t calcap_mid; // MP-12-02-2016 - - // Store all the registers that will be changed in this function - rf_cntrl_timer14_reg_set_offset = REG_GETF(RFCU_POWER, RF_CNTRL_TIMER_14_REG, - SET_OFFSET); - rf_cntrl_timer_7_reg_value = RFCU_POWER->RF_CNTRL_TIMER_7_REG; - rf_enable_config14_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG; - rf_enable_config15_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG; - rf_enable_config14_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG; - rf_enable_config15_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG; - rf_cal_ctrl_reg_value = RFCU->RF_CAL_CTRL_REG; - rf_mgain_ctrl_reg_value = PLLDIG->RF_MGAIN_CTRL_BLE_REG; - rf_mgain_ctrl2_reg_value = PLLDIG->RF_MGAIN_CTRL2_REG; - rf_synth_ctrl2_ble_reg_value = PLLDIG->RF_SYNTH_CTRL2_BLE_REG; - rf_synth_ctrl2_ftdf_reg_value = PLLDIG->RF_SYNTH_CTRL2_FTDF_REG; - rf_bmcw_reg_value = PLLDIG->RF_BMCW_REG; - rf_vcocal_ctrl_reg_value = PLLDIG->RF_VCOCAL_CTRL_REG; - - // move PLLCLOSED_EN to after PLL is in lock - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_7_REG, SET_OFFSET, - rf_cntrl_timer14_reg_set_offset + 150); - - // Disable PA and PA ramp. - RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG = 0x0000; - - RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG = 0x0000; - - // Disable end-of-packet detection (not needed for the MGC) - REG_SET_BIT(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, EO_PACKET_DIS); - - //Set modulator inversion -// REG_CLR_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_SDM_POL); // Normal SDM polarity -// REG_SET_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_DAC_POL); // Inverted DAC polarity - - //Make sure that normal operation is selected. - REG_CLR_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); - - // Settings for modulation gain calibration - REG_SET_BIT(RFCU, RF_MGC_CTRL_REG, MGC_GAIN_SET); - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, 0x2); - - // invert the comparator value if mode bit is set to true. - if (!mode_ble) { - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x2); // Set radio in FTDF mode - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - // Set length dependent on mode , JH-09-11-2015 - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 12); - // Need to set ModIndex value to 0x3F. - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, FTDF_MODINDEX, 0x3F); - } else { - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Set radio in BLE mode - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - // Set length dependent on mode , JH-09-11-2015 - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); - // Set modindex to 266kHz to improve df2/df1 , JH-09-17-2015 - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); - - // Start with a VCO coarse cal to find the calcap for mid channel - REG_SETF(PLLDIG, RF_BMCW_REG, CN_SEL, 1); - REG_SETF(PLLDIG, RF_BMCW_REG, CN_WR, 18); - - // Disable all calibrations except the VCO coarse cal. - RFCU->RF_CAL_CTRL_REG = 0x001C; - - // Clear eo-cal interrupt, such that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Wait until the VCO coarse calibration can be started - while ((RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL))) {} - - // Start the VCO coarse calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the VCO coarse calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - - // Wait until the VCO coarse calibration is completed - while ((RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - - // Clear eo_cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - calcap_mid = REG_GETF(PLLDIG, RF_SYNTH_RESULT_BLE_REG, VCO_FREQTRIM_RD); - REG_SETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_WR, - calcap_mid - REG_GETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL)); - - REG_SETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL, 2); // manual calcap - - } - - // Disable all calibrations except the modulation gain cal. - RFCU->RF_CAL_CTRL_REG = 0x0038; - - // Clear eo-cal interrupt, such that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Wait until next calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - - NVIC_ClearPendingIRQ(RFCAL_IRQn); - - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} -} -#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ -static void hw_rf_modulation_gain_calibration_generic_start(mgc_mode_ctrl_e mode_ctrl, - int16_t average, int16_t mgain_mode, int16_t force, int16_t length) -{ - - // Store all the registers that will be changed in this function - rf_cntrl_timer14_reg_set_offset = REG_GETF(RFCU_POWER, RF_CNTRL_TIMER_14_REG, - SET_OFFSET); - rf_cntrl_timer_7_reg_value = RFCU_POWER->RF_CNTRL_TIMER_7_REG; - rf_enable_config14_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_REG; - rf_enable_config15_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_REG; - rf_cal_ctrl_reg_value = RFCU->RF_CAL_CTRL_REG; - rf_mgain_ctrl_reg_value = PLLDIG->RF_MGAIN_CTRL_BLE_REG; - rf_mgain_ctrl2_reg_value = PLLDIG->RF_MGAIN_CTRL2_REG; - rf_synth_ctrl2_ble_reg_value = PLLDIG->RF_SYNTH_CTRL2_BLE_REG; - rf_synth_ctrl2_ftdf_reg_value = PLLDIG->RF_SYNTH_CTRL2_FTDF_REG; - rf_overrule_reg_value = RFCU->RF_OVERRULE_REG; - rf_enable_config23_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG; - rf_enable_config23_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG; - rf_enable_config45_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG; - rf_enable_config45_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG; - - // move PLLCLOSED_EN to after PLL is in lock - REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_7_REG, SET_OFFSET, - rf_cntrl_timer14_reg_set_offset + 150); - - // Disable PA and PA ramp. - RFCU_POWER->RF_ENABLE_CONFIG14_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG15_REG = 0x0000; - - // Disable end-of-packet detection (not needed for the MGC) - REG_SET_BIT(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, EO_PACKET_DIS); - - // Set Gain in Analog comparator to 1 - REG_SET_BIT(RFCU, RF_MGC_CTRL_REG, MGC_GAIN_SET); - - - /* Set mode specific settings for BLE mode with GaussDAC */ - if (mode_ctrl == MGC_MODE_CTRL_BLE_GAUSSDAC) { - /* Set radio in BLE mode */ - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); - /* Inversion of analog comparator signal */ - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - - if (force != -1) { - /* Disable Gauss Gain override */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); - } - - if (average != -1) { - /* Set number of averaging */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); - } - - /* Setting number of zeros and ones */ - if (length == -1) { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); - } else { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, - length & 0x7f); - } - - /* Set modindex to 266kHz */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); - /* Select the GaussDac in BLE mode */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x0); - - if (mgain_mode != -1) { - /* Use the new algorithm */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); - } - - /* Disable TXDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x0); - /* Enable GaussDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x3); - /* Disable TX-DAC output selection */ - REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); - /* Enable GaussDAC output selection switch */ - REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); - } - - /* Set mode specific settings for BLE mode with TXDAC */ - if (mode_ctrl == MGC_MODE_CTRL_BLE_TXDAC) { - /* Set radio in BLE mode */ - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); - /* Inversion of analog comparator signal */ - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - - if (force != -1) { - /* Disable Gauss Gain override */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); - } - - if (average != -1) { - /* Set number of averaging */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); - } - - /* Setting number of zeros and ones */ - if (length == -1) { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); - } else { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, - length & 0x7f); - } - - /* Set modindex to 250kHz */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x0); - /* Select the TXDAC in BLE mode */ - REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x1); - - if (mgain_mode != -1) { - /* Use the new algorithm */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); - } - - /* Enable TXDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x3); - /* Disable GaussDAC in BLE mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x0); - /* Select TX-DAC output selection */ - REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x2); - /* Unselect GaussDAC output selection switch */ - REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x1); - } - - /* Set mode specific settings for FTDF mode */ - if (mode_ctrl == MGC_MODE_CTRL_FTDF) { - /* Set radio in FTDF mode */ - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x2); - /* Inversion of analog comparator signal */ - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); - - if (force != -1) { - /* Disable Gauss Gain override */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); - } - - if (average != -1) { - /* Set number of averaging */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); - } - - /* Setting number of zeros and ones */ - if (length == -1) { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 16); - } else { - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, - length & 0x7f); - } - - if (mgain_mode != -1) { - /* Use the new algorithm */ - REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); - } - - /* Enable TXDAC in FTDF mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_FTDF_REG, txdac_en_ftdf_dcf_tx, 0x3); - /* Disable GaussDAC in FTDF mode */ - REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_FTDF_REG, gauss_en_ftdf_dcf_tx, 0x0); - /* Select TX-DAC output selection */ - REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); - /* Unselect GaussDAC output selection switch */ - REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); - } - - // Disable all calibrations except the modulation gain cal. - RFCU->RF_CAL_CTRL_REG = 0x0038; - - // Clear eo-cal interrupt, such that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Wait until next calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - - NVIC_ClearPendingIRQ(RFCAL_IRQn); - - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} -} - -static inline void hw_rf_modulation_gain_calibration_start(bool mode_ble) -{ - if (mode_ble) { - hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_BLE_TXDAC, 2, 1, 0, 8); - } else { - hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_FTDF, 2, 1, 0, 8); - } -} -#endif - -static void hw_rf_modulation_gain_calibration_end(void) -{ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - uint32_t ch_cal,gg_cal,gg_ch_prod,kmoda_max, gg0, gg_th1, gg_th2; // MP-12-02-2016 - uint32_t kmoda_base; - uint32_t Y; - uint32_t tmp; - uint32_t dgain_kill_second_jump; - uint32_t dgain; - - if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) - && (CHIP_IS_AE))) { - kmoda_base = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, - KMOD_ALPHA_BLE); - } - - // Clear eo_cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - ch_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT2_BLE_REG, CN_CAL_RD); - gg_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT_BLE_REG, GAUSS_GAIN_CAL_RD); - - gg0 = gg_cal + ((gg_cal*kmoda_base*ch_cal+1024)>>11); - gg_th1 = (gg_cal&0xE0) + DF1_DAC_CHECK_VALUE; // gg_th1 = (gg_cal&0xE0)+32; - gg_th2 = (gg_th1 + DF1_DAC_CHECK_VALUE); // gg_th2 = (gg_th1+32); - - if (gg0 >= gg_th2) { //so 2 jumps are on the left of the cal. channel - /* - Formula (MP): - Y = 1 + ((kmoda_base*ch_cal)/2048); - dgain_kill_second_jump = gg_cal - (gg_th2-1)/Y; - - Improve the resolution, - Y = 2048* + (kmoda_base*ch_cal); - dgain_kill_second_jump = gg_cal - (gg_th2-1)*2048/Y; - */ - - Y = 2048 + (kmoda_base*ch_cal); - tmp = (((gg_th2-1)<<11)/Y); - - if (gg_cal > tmp) {//check to prevent negative value for dgain_kill_second_jump - dgain_kill_second_jump = gg_cal - tmp; - - if (dgain_kill_second_jump <= DF1_DGAIN_THR1) { - dgain = DF1_DGAIN_THR1; - } else if (dgain_kill_second_jump >= DF1_DGAIN_THR2) { - dgain = DF1_DGAIN_THR2; // Should never end up here � but better to be safe than sorry. dgain_thr2 is default 16 - } else { - dgain = dgain_kill_second_jump; - } - } else { - dgain = 0; // End up here because something went wrong with the calculation of tmp! - } - - } else if (gg0 >= gg_th1) { - dgain = DF1_DGAIN_THR1; - } else { - dgain = DF1_DGAIN_THR0; - } - - if (gg_cal>dgain) { - gg_cal_modified = gg_cal-dgain; - } else { - gg_cal_modified = gg_cal; - } - - gg_ch_prod = (uint32_t) (gg_cal_modified * ch_cal); - - if (gg_ch_prod == 0) { // Avoid HardFault due to division by 0 (not likely) - kmoda_cal = kmoda_base; - } else { - - kmoda_max = (255*2048 - 2048 * gg_cal_modified) / gg_ch_prod ; - - if (kmoda_max >= kmoda_base) { - kmoda_cal = kmoda_base; - } else { - kmoda_cal = kmoda_max; - } - } - - // This should be done both here (to take effect after calib) AND after preferred settings - REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); - - //Restore the values of the registers that were changed in the function - //REG_SET_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_SDM_POL); // Inverted SDM polarity - //REG_CLR_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_DAC_POL); // Normal DAC polarity - RFCU_POWER->RF_CNTRL_TIMER_7_REG = rf_cntrl_timer_7_reg_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG14_BLE_REG = rf_enable_config14_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG14_FTDF_REG = rf_enable_config14_ftdf_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG15_BLE_REG = rf_enable_config15_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG15_FTDF_REG = rf_enable_config15_ftdf_reg_value; - - PLLDIG->RF_MGAIN_CTRL_BLE_REG = rf_mgain_ctrl_reg_value; - PLLDIG->RF_MGAIN_CTRL2_REG = rf_mgain_ctrl2_reg_value; - PLLDIG->RF_SYNTH_CTRL2_BLE_REG = rf_synth_ctrl2_ble_reg_value; - PLLDIG->RF_SYNTH_CTRL2_FTDF_REG = rf_synth_ctrl2_ftdf_reg_value; - - PLLDIG->RF_BMCW_REG = rf_bmcw_reg_value; // MP-12-02-2016 - PLLDIG->RF_VCOCAL_CTRL_REG = rf_vcocal_ctrl_reg_value; // MP-12-02-2016 - - REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); - REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); - - // Disable overrule mode - RFCU->RF_OVERRULE_REG &= ~REG_MSK(RFCU, RF_OVERRULE_REG, RF_MODE_OVR); -#else - // Clear eo_cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - //Restore the values of the registers that were changed in the function - RFCU_POWER->RF_CNTRL_TIMER_7_REG = rf_cntrl_timer_7_reg_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG14_REG = rf_enable_config14_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG15_REG = rf_enable_config15_reg_value; - PLLDIG->RF_MGAIN_CTRL_BLE_REG = rf_mgain_ctrl_reg_value; - PLLDIG->RF_MGAIN_CTRL2_REG = rf_mgain_ctrl2_reg_value; - PLLDIG->RF_SYNTH_CTRL2_BLE_REG = rf_synth_ctrl2_ble_reg_value; - PLLDIG->RF_SYNTH_CTRL2_FTDF_REG = rf_synth_ctrl2_ftdf_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG = rf_enable_config23_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG = rf_enable_config23_ftdf_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG = rf_enable_config45_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG = rf_enable_config45_ftdf_reg_value; - - // Disable overrule mode - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value; - -#endif -} - -/** - * \brief Modulation gain calibration - Wrapper function - * - * Used on boot, and generally whenever the interrupt-based approach is not - * needed - * - * \param[in] bool, true for FTDF, false for BLE - * - */ -void hw_rf_modulation_gain_calibration(bool mode_ble) -{ - /* Start the gain calibration */ - hw_rf_modulation_gain_calibration_start(mode_ble); - - // Wait until the modulation gain calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} - - hw_rf_modulation_gain_calibration_end(); -} - - -void hw_rf_dc_offset_calibration(void) -{ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - // Save the values of registers that will be changed in the function - uint32_t RF_ENABLE_CONFIG0_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG; - uint32_t RF_ENABLE_CONFIG1_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG; - uint32_t RF_ENABLE_CONFIG2_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG; - uint32_t RF_ENABLE_CONFIG46_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; - - uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; - uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; - - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = 0x0000; // Disable LNA_CGM - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC - - // DCNGAIN = 3, DCNSTEP = 5, DCPARCAL_EN = 0, DCOFFSET_SEL = 0 - DEM->RF_DC_OFFSET_CTRL2_REG = 0x01D0; - // Disable all calibrations except the DC-offset cal. - RFCU->RF_CAL_CTRL_REG = 0x002C; - - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Overrule RF_MODE <- BLE_MODE - - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Wait until the DC-offset calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - - // Wait until the modulation gain calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} - - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Restore the values of registers that were changed in the function - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = RF_ENABLE_CONFIG0_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = RF_ENABLE_CONFIG1_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = RF_ENABLE_CONFIG2_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = RF_ENABLE_CONFIG46_BLE_REG_value; - - DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; -#else /* REV_B */ - // Save the values of registers that will be changed in the function - uint32_t RF_ENABLE_CONFIG0_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; - uint32_t RF_ENABLE_CONFIG1_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; - uint32_t RF_ENABLE_CONFIG2_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; - - uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; - uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; - - uint32_t rf_enable_config46_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; - uint32_t rf_enable_config46_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG; - - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM - - // DCNGAIN = 3, DCNSTEP = 5, DCPARCAL_EN = 0, DCOFFSET_SEL = 0 - DEM->RF_DC_OFFSET_CTRL2_REG = 0x01D0; - // Disable all calibrations except the DC-offset cal. - RFCU->RF_CAL_CTRL_REG = 0x002C; - - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; - RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = 0x0000; - - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Overrule RF_MODE <- BLE_MODE - - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Wait until the DC-offset calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} - - // Start the modulation gain calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the modulation gain calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} - - // Wait until the modulation gain calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} - - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Restore the values of registers that were changed in the function - RFCU_POWER->RF_ENABLE_CONFIG0_REG = RF_ENABLE_CONFIG0_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG1_REG = RF_ENABLE_CONFIG1_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG2_REG = RF_ENABLE_CONFIG2_REG_value; - - DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = rf_enable_config46_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = rf_enable_config46_ftdf_reg_value; - -#endif -} - - - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -bool hw_rf_iff_calibration(void) -{ - uint64_t start_time; - - uint16_t calcap_result; - - // Save the values of registers that will be changed in the function - uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - - // Configure the reference oscillator for the calibration - // 21-04-2015 : JH - Removed to use preferred settings instead - //uint16_t reg = RFCU->RF_REF_OSC_BLE_REG; - //REG_SET_FIELD(RFCU, RF_REF_OSC_BLE_REG, CNT_CLK, reg, 0xA6); - //REG_SET_FIELD(RFCU, RF_REF_OSC_BLE_REG, CNT_RO, reg, 0x2C); - //RFCU->RF_REF_OSC_BLE_REG = reg; - //reg = RFCU->RF_REF_OSC_FTDF_REG; - //REG_SET_FIELD(RFCU, RF_REF_OSC_FTDF_REG, CNT_CLK, reg, 0xA6); - //REG_SET_FIELD(RFCU, RF_REF_OSC_FTDF_REG, CNT_RO, reg, 0x2C); - //RFCU->RF_REF_OSC_FTDF_REG = reg; - - // Save the values of registers that will be changed in the function - uint32_t RF_ENABLE_CONFIG0_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG; - uint32_t RF_ENABLE_CONFIG1_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG; - uint32_t RF_ENABLE_CONFIG2_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG; - uint32_t RF_ENABLE_CONFIG46_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; - - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = 0x0000; // Disable LNA_CGM - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC - - // Disable all calibrations except the Iff cal. - RFCU->RF_CAL_CTRL_REG = 0x0034; - // Select the IF calcap to use the FSM value - REG_SET_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - - start_time = hw_rf_get_start_iff_time(); - - // Wait until the IFF calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) { - if (hw_rf_check_iff_timeout(start_time)) { - /* IFF lockup detected. Abort */ - return false; - } - } - - /* - * New code by SR 3/23/2016 - * (Disable partial calibration before IFF calibrations starts) - * - * Save current content of RF_DC_OFFSET_CTRl2_REG and set DCPARCAL_EN = 0 - * - */ - uint16_t rf_dc_offset_ctrl2_reg = DEM->RF_DC_OFFSET_CTRL2_REG; //GetWord16(RF_DC_OFFSET_CTRL2_REG); - REG_CLR_BIT(DEM, RF_DC_OFFSET_CTRL2_REG, DCPARCAL_EN); - - // Start the IFF calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the IFF calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) { - if (hw_rf_check_iff_timeout(start_time)) { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Wait until the IFF calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) { - if (hw_rf_check_iff_timeout(start_time)) { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Store the result to all IFF CC registers - calcap_result = RFCU->RF_IFF_CAL_CAP_STAT_REG; - RFCU->RF_IFF_CC_BLE_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_BLE_SET2_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; - - // Restore the values of registers that were changed in the function - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - // De-select the IF calcap to use the FSM value - REG_CLR_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - - - /* - * New code by SR 3/23/2016 - * (Disable partial calibration before IFF calibrations starts) - * - * Restore RF_DC_OFFSET_CTRl2_REG - * - */ - DEM->RF_DC_OFFSET_CTRL2_REG = rf_dc_offset_ctrl2_reg; - - // Restore the values of registers that were changed in the function - RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = RF_ENABLE_CONFIG0_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = RF_ENABLE_CONFIG1_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = RF_ENABLE_CONFIG2_BLE_REG_value; - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = RF_ENABLE_CONFIG46_BLE_REG_value; - return true; -} -#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ -static bool iff_calib_internal(iff_mode_ovr_e rf_mode_ovr, iff_mode_ctrl_e mode_ctrl) -{ - uint16_t calcap_result; - uint64_t start_time; - - // Set mode - REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, rf_mode_ovr); - - // Disable all calibrations except the Iff cal. - RFCU->RF_CAL_CTRL_REG = 0x0034; - - // Select the IF calcap to use the FSM value - REG_SET_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - - // Clear eo-cal interrupt, so that new calibration can be stared - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - start_time = hw_rf_get_start_iff_time(); - - // Wait until the IFF calibration can be started - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) { - if (hw_rf_check_iff_timeout(start_time)) { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Start the IFF calibration - REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); - - // Wait until the IFF calibration has started - while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) { - if (hw_rf_check_iff_timeout(start_time)) { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Wait until the IFF calibration is completed - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) { - if (hw_rf_check_iff_timeout(start_time)) { - /* IFF lockup detected. Abort */ - return false; - } - } - - // Clear eo-cal interrupt, so that new calibration can be started - RFCU->RF_IRQ_CTRL_REG = 0x0000; - - // Store the result to all IFF CC BLE registers - calcap_result = RFCU->RF_IFF_CAL_CAP_STAT_REG; - if (mode_ctrl != IFF_MODE_CTRL_COMBO || rf_mode_ovr == IFF_MODE_OVR_BLE) { - RFCU->RF_IFF_CC_BLE_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_BLE_SET2_REG = calcap_result; - } - - switch (mode_ctrl) { - case IFF_MODE_CTRL_BLE: // BLE - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; - break; - case IFF_MODE_CTRL_FTDF: // FTDF - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; - break; - case IFF_MODE_CTRL_COMBO: // COMBO - if (rf_mode_ovr == IFF_MODE_OVR_FTDF) { - RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; - RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; - } - break; - } - return true; -} - -static bool hw_rf_iff_calibration(iff_mode_ctrl_e mode_ctrl) -{ - bool ret = false; - - ////////////////////////////////////////////////////////////// - /// Capacitance calibration for different modes - /// mode_ctrl=0 : Calibration in BLE mode, use offsetted values in FTDF - /// mode_ctrl=1 : Calibration in FTDF mode, use offsetted values in BLE - /// mode_ctrl=2 : Calibration done in BLE mode and FTDF mode - ////////////////////////////////////////////////////////////// - - - // Save the values of registers that will be changed in the function - uint16_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - uint16_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; - uint16_t rf_enable_config0_reg_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; - uint16_t rf_enable_config1_reg_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; - uint16_t rf_enable_config2_reg_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; - uint16_t rf_enable_config46_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; - uint16_t rf_enable_config46_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG; - uint16_t rf_dc_offset_ctrl2_reg_value = DEM->RF_DC_OFFSET_CTRL2_REG; - - // Required setting for the DC-offset calibration - RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO - RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE - RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC - RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = 0x0000; // Disable the DCF triggered Partial DCOC - REG_SETF(DEM, RF_DC_OFFSET_CTRL2_REG, DCPARCAL_EN, 0x0); - - - switch (mode_ctrl) { - case IFF_MODE_CTRL_BLE: // BLE - ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_BLE); - break; - case IFF_MODE_CTRL_FTDF: // FTDF - ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_FTDF); - break; - case IFF_MODE_CTRL_COMBO: // COMBO - ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_COMBO); - if (ret) - ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_COMBO); - break; - default: - /* should never reach this point */ - ASSERT_WARNING(0); - } - - if (!ret) - return false; - - // Restore the values of registers that were changed in the function - RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; - RFCU_POWER->RF_ENABLE_CONFIG0_REG = rf_enable_config0_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG1_REG = rf_enable_config1_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG2_REG = rf_enable_config2_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = rf_enable_config46_ble_reg_value; - RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = rf_enable_config46_ftdf_reg_value; - DEM->RF_DC_OFFSET_CTRL2_REG = rf_dc_offset_ctrl2_reg_value; - - // De-select the IF calcap to use the FSM value - REG_CLR_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); - - return true; -} -#endif - -bool hw_rf_calibration(void) -{ - bool iff_result; - - GLOBAL_INT_DISABLE(); - hw_rf_dc_offset_calibration(); -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - iff_result = hw_rf_iff_calibration(); -#else -#if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) - iff_result = hw_rf_iff_calibration(0x2); -#elif defined(CONFIG_USE_BLE) - iff_result = hw_rf_iff_calibration(0x0); -#elif defined(CONFIG_USE_FTDF) - iff_result = hw_rf_iff_calibration(0x1); -#endif -#endif - if (iff_result) { -#ifdef CONFIG_USE_FTDF - hw_rf_modulation_gain_calibration(0); -#endif -#ifdef CONFIG_USE_BLE - hw_rf_modulation_gain_calibration(1); -#endif - } - GLOBAL_INT_RESTORE(); - - return iff_result; -} - -void hw_rf_request_on(bool mode_ble) -{ - /* First RF requester. Switch it on */ - if (rf_request == 0) { - if (rf_state == RF_ST_OFF) { - hw_rf_poweron(); - rf_state = RF_ST_ON; -#if dg_configCOEX_ENABLE_CONFIG == 1 - hw_coex_apply_config(); -#endif - } - } - - if (mode_ble) { - rf_request |= RF_REQUEST_BLE_ON; - } else { - rf_request |= RF_REQUEST_FTDF_ON; - } - -} - - -void hw_rf_request_off(bool mode_ble) -{ - if (mode_ble) { - rf_request &= ~RF_REQUEST_BLE_ON; - } else { - rf_request &= ~RF_REQUEST_FTDF_ON; - } - - /* If not already off or during recalibration... */ - if (rf_state == RF_ST_ON || rf_state == RF_ST_CONFIG) { - /* If not RF requesters remain, switch it off */ - if (rf_request == 0) { - /* If user pre-off cb returns true, don't shutdown */ - if (hw_rf_preoff_cb() == false) { - hw_rf_poweroff(); - rf_state = RF_ST_OFF; - } - } - } -} - - -bool hw_rf_start_calibration() -{ - bool iff_result; - if (rf_state == RF_ST_CONFIG) { - /* Call pre-calibration user cb */ - hw_rf_precalib_cb(); - - /* force RADIO_BUSY to BLE to 0 */ - REG_SETF(COEX, COEX_CTRL_REG, SEL_BLE_RADIO_BUSY, 1); - /* Ignore BLE/FTDF TX/RX_EN */ - REG_SET_BIT(COEX, COEX_CTRL_REG, IGNORE_BLE); - REG_SET_BIT(COEX, COEX_CTRL_REG, IGNORE_FTDF); - - /* Wait until DCFs have settled */ - while (REG_GETF(COEX, COEX_STAT_REG, COEX_RADIO_BUSY)); - - /* Perform DC offset calibration */ - hw_rf_dc_offset_calibration(); - - /* Perform IFF calibration */ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - iff_result = hw_rf_iff_calibration(); -#else /* BLACK_ORCA_IC_REV_B */ -#if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) - iff_result = hw_rf_iff_calibration(0x2); -#elif defined(CONFIG_USE_BLE) - iff_result = hw_rf_iff_calibration(0x0); -#elif defined(CONFIG_USE_FTDF) - iff_result = hw_rf_iff_calibration(0x1); -#endif -#endif - - if (iff_result == false) { - return false; - } - - NVIC_EnableIRQ(RFCAL_IRQn); - -#if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) - /* Start the gain calibration, on ftdf mode */ - hw_rf_modulation_gain_calibration_start(0); - rf_state = RF_ST_WAIT_NEXT1; -#elif defined(CONFIG_USE_FTDF) - /* Start the gain calibration, on ftdf mode */ - hw_rf_modulation_gain_calibration_start(0); - rf_state = RF_ST_WAIT_NEXT2; -#elif defined(CONFIG_USE_BLE) - /* Start the gain calibration, on ble mode */ - hw_rf_modulation_gain_calibration_start(1); - rf_state = RF_ST_WAIT_NEXT2; -#endif - - } - - return true; -} - -void RFCAL_Handler(void) -{ - SEGGER_SYSTEMVIEW_ISR_ENTER(); - - uint32_t iser; - - /* Interrupts must be disabled. However, some callbacks actually - * use FreeRTOS critical sections. To overcome this problem. use - * ISER/ICER to enable/disable interrupts - */ - GLOBAL_INT_DISABLE(); - iser = NVIC->ISER[0];; - NVIC->ICER[0] = iser; - GLOBAL_INT_RESTORE(); - - switch (rf_state) { - case RF_ST_WAIT_NEXT1: - /* FTDF gain calib (boot) completed. Proceed with ble gain - * calib - */ - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} - hw_rf_modulation_gain_calibration_end(); - - /* Make sure RFCAL IRQ will be enabled when interrupts are enabled */ - iser |= ((uint32_t)(1 << RFCAL_IRQn)); - - /* Start the gain calibration, on ble mode */ - hw_rf_modulation_gain_calibration_start(1); - - rf_state = RF_ST_WAIT_NEXT2; - break; - case RF_ST_WAIT_NEXT2: - /* BLE (or ftdf) gain calib (boot) completed. - */ - while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} - hw_rf_modulation_gain_calibration_end(); - - /* Make sure RFCAL IRQ will be disabled when interrupts are enabled */ - iser &= ~((uint32_t)(1 << RFCAL_IRQn)); - - /* Restore state to normal BLE/FTDF MAC operation */ - REG_CLR_BIT(COEX, COEX_CTRL_REG, IGNORE_BLE); - REG_CLR_BIT(COEX, COEX_CTRL_REG, IGNORE_FTDF); - REG_SETF(COEX, COEX_CTRL_REG, SEL_BLE_RADIO_BUSY, 0); - - /* Calibration complete. */ - /* Call post-calibration user cb */ - hw_rf_postcalib_cb(); - - /* Check if RF is still needed on, - * otherwise, switch it off - */ - if (rf_request == 0) { - hw_rf_poweroff(); - rf_state = RF_ST_OFF; - } else { - rf_state = RF_ST_CONFIG; - hw_rf_postconf_cb(); - } - break; - default: - break; - } - - /* Re-enable interrupts */ - NVIC->ISER[0] = iser; - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - -void hw_rf_request_recommended_settings(void) -{ - if (rf_state == RF_ST_ON) { - hw_rf_apply_tcs_cb(); - hw_rf_set_recommended_settings(); - - /* Initialize TX Power LUTs */ -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - hw_rf_set_tx_power(rf_tx_power_luts.tx_power_ble); -#else -#ifdef CONFIG_USE_BLE - hw_rf_set_tx_power_ble(rf_tx_power_luts.tx_power_ble); -#endif -#ifdef CONFIG_USE_FTDF - hw_rf_set_tx_power_ftdf(rf_tx_power_luts.tx_power_ftdf); -#endif -#endif - - rf_state = RF_ST_CONFIG; - hw_rf_postconf_cb(); - } -} - -bool __attribute__((weak)) hw_rf_preoff_cb(void) -{ - return false; -} - -void hw_rf_start_continuous_wave(uint8_t mode, uint8_t ch) -{ - REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 1); // disable TX overrule - REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 0); // NORMAL TX - - REG_SETF(PLLDIG,RF_BMCW_REG, CN_SEL, 1); - REG_SETF(PLLDIG,RF_BMCW_REG, CN_WR, ch); - - REG_SETF(RFCU,RF_OVERRULE_REG, RF_MODE_OVR, mode); - REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 2); // OVERRULE TX ENABLED -} - -void hw_rf_start_continuous_wave_rx(uint8_t mode, uint8_t ch) -{ - REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 1); // disable RX overrule - REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 0); // NORMAL RX - - REG_SETF(PLLDIG,RF_BMCW_REG, CN_SEL, 1); - REG_SETF(PLLDIG,RF_BMCW_REG, CN_WR, ch); - - REG_SETF(RFCU,RF_OVERRULE_REG, RF_MODE_OVR, mode); // BLE MODE - REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 2); // OVERRULE RX ENABLED -} - -void hw_rf_stop_continuous_wave(void) -{ - REG_SETF(PLLDIG,RF_BMCW_REG, CN_SEL, 0); - REG_SETF(PLLDIG,RF_BMCW_REG, CN_WR, 0); - - REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 1); // disable TX overrule - REG_SETF(RFCU,RF_OVERRULE_REG, TX_EN_OVR, 0); // NORMAL TX - REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 1); // disable RX overrule - REG_SETF(RFCU,RF_OVERRULE_REG, RX_EN_OVR, 0); // NORMAL RX - REG_SETF(RFCU,RF_OVERRULE_REG, RF_MODE_OVR, 0); // NORMAL RF mode, so disable BLE mode -} - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -void hw_rf_set_tx_power(HW_RF_PWR_LUT_SETTING lut) -{ - RFCU->RF_TX_PWR_REG = lut; - rf_tx_power_luts.tx_power_ble = lut; -} -#else - -#ifdef CONFIG_USE_BLE -void hw_rf_set_tx_power_ble(HW_RF_PWR_LUT_SETTING lut) -{ - RFCU->RF_TX_PWR_BLE_REG = lut; - rf_tx_power_luts.tx_power_ble = lut; -} -#endif - -#ifdef CONFIG_USE_FTDF -void hw_rf_set_tx_power_ftdf(HW_RF_PWR_LUT_SETTING lut) -{ - RFCU->RF_TX_PWR_FTDF_REG = lut; - rf_tx_power_luts.tx_power_ftdf = lut; -} -#endif - -#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ -#endif /* dg_configUSE_HW_RF */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c deleted file mode 100644 index 9bac6479b..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c +++ /dev/null @@ -1,122 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup Timer0 - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_timer0.c - * - * @brief Implementation of the Timer0 Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_TIMER0 - - -#include -#include -#include - -#if (dg_configSYSTEMVIEW) -# include "SEGGER_SYSVIEW_FreeRTOS.h" -#else -# define SEGGER_SYSTEMVIEW_ISR_ENTER() -# define SEGGER_SYSTEMVIEW_ISR_EXIT() -#endif - -static hw_timer0_interrupt_cb intr_cb; - -void hw_timer0_init(const timer0_config *cfg) -{ - /* Enable clock for peripheral */ - GLOBAL_INT_DISABLE(); - uint32_t clk_tmr_reg = CRG_TOP->CLK_TMR_REG; - clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk; - clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk; - clk_tmr_reg |= CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk; - CRG_TOP->CLK_TMR_REG = clk_tmr_reg ; - GLOBAL_INT_RESTORE(); - - /* Reset control register, i.e. disable timer */ - GP_TIMERS->TIMER0_CTRL_REG = 0x0; - - /* Disable NVIC interrupt */ - NVIC_DisableIRQ(SWTIM0_IRQn); - - intr_cb = NULL; - - hw_timer0_configure(cfg); -} - -void hw_timer0_configure(const timer0_config *cfg) -{ - if (cfg) { - hw_timer0_set_clock_source(cfg->clk_src); - hw_timer0_set_fast_clock_div(cfg->fast_clk_div); - hw_timer0_set_on_clock_div(cfg->on_clock_div); - hw_timer0_set_on_reload(cfg->on_reload); - hw_timer0_set_t0_reload(cfg->t0_reload_m, cfg->t0_reload_n); - } -} - -void hw_timer0_register_int(hw_timer0_interrupt_cb handler) -{ - intr_cb = handler; - NVIC_EnableIRQ(SWTIM0_IRQn); -} - -void hw_timer0_unregister_int(void) -{ - NVIC_DisableIRQ(SWTIM0_IRQn); - intr_cb = NULL; -} - -void SWTIM0_Handler(void) -{ - SEGGER_SYSTEMVIEW_ISR_ENTER(); - - if (intr_cb) { - intr_cb(); - } - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - -#endif /* dg_configUSE_HW_TIMER0 */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c deleted file mode 100644 index a8510eede..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - **************************************************************************************** - * - * @file hw_trng.c - * - * @brief Implementation of the True Random Number Generator Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_TRNG - -#include - -#if (dg_configSYSTEMVIEW) -# include "SEGGER_SYSVIEW_FreeRTOS.h" -#else -# define SEGGER_SYSTEMVIEW_ISR_ENTER() -# define SEGGER_SYSTEMVIEW_ISR_EXIT() -#endif - -#define HW_TRNG_FIFO_DEPTH (32) - -static hw_trng_cb trng_cb; - -void hw_trng_disable_clk(void) -{ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); - GLOBAL_INT_RESTORE(); -} - -void hw_trng_clear_pending(void) -{ - uint32_t dummy __attribute__((unused)); - /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ - dummy = TRNG->TRNG_FIFOLVL_REG; - NVIC_ClearPendingIRQ(TRNG_IRQn); -} - -void hw_trng_enable(hw_trng_cb callback) -{ - if (callback != NULL) { - trng_cb = callback; - hw_trng_clear_pending(); - NVIC_EnableIRQ(TRNG_IRQn); - } - - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); - GLOBAL_INT_RESTORE(); - REG_SET_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); -} - -void hw_trng_get_numbers(uint32_t* buffer, uint8_t size) -{ - if (size > HW_TRNG_FIFO_DEPTH) - size = HW_TRNG_FIFO_DEPTH; - - for (int i = 0; i < size ; i++) { - buffer[i] = hw_trng_get_number(); - } -} - -__RETAINED_CODE uint8_t hw_trng_get_fifo_level(void) -{ - return (TRNG->TRNG_FIFOLVL_REG) & (REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOLVL) | - REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOFULL)); -} - -void hw_trng_disable_interrupt(void) -{ - NVIC_DisableIRQ(TRNG_IRQn); - trng_cb = NULL; -} - -void hw_trng_disable(void) -{ - hw_trng_stop(); - hw_trng_disable_interrupt(); - hw_trng_clear_pending(); - hw_trng_disable_clk(); -} - -void TRNG_Handler(void) -{ - uint32_t dummy __attribute__((unused)); - - SEGGER_SYSTEMVIEW_ISR_ENTER(); - - if (trng_cb != NULL) - trng_cb(); - - /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ - dummy = TRNG->TRNG_FIFOLVL_REG; - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - -#endif /* dg_configUSE_HW_TRNG */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c deleted file mode 100644 index b08bded9a..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c +++ /dev/null @@ -1,1464 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup UART - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_uart.c - * - * @brief Implementation of the UART Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_UART - - -#include -#include -#include -#include - -#if (dg_configSYSTEMVIEW) -# include "SEGGER_SYSVIEW_FreeRTOS.h" -#else -# define SEGGER_SYSTEMVIEW_ISR_ENTER() -# define SEGGER_SYSTEMVIEW_ISR_EXIT() -#endif - -#if (dg_configUART1_SOFTWARE_FIFO_SIZE && dg_configUART_SOFTWARE_FIFO) -#if dg_configUART_RX_CIRCULAR_DMA && (dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE > 0) -#error UART1 can not be configured to use software FIFO and circular DMA FIFO at the same time -#endif -__RETAINED static uint8_t uart1_sw_fifo[dg_configUART1_SOFTWARE_FIFO_SIZE]; -#else -#define uart1_sw_fifo (NULL) -#endif - -#if (dg_configUART2_SOFTWARE_FIFO_SIZE && dg_configUART_SOFTWARE_FIFO) -#if dg_configUART_RX_CIRCULAR_DMA && (dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE > 0) -#error UART2 can not be configured to use software FIFO and circular DMA FIFO at the same time -#endif -__RETAINED static uint8_t uart2_sw_fifo[dg_configUART2_SOFTWARE_FIFO_SIZE]; -#else -#define uart2_sw_fifo (NULL) -#endif - -#if dg_configUART1_SOFTWARE_FIFO_SIZE > 255 || dg_configUART2_SOFTWARE_FIFO_SIZE > 255 -typedef uint16_t fifo_size_t; -#else -typedef uint8_t fifo_size_t; -#endif - -#if dg_configUART1_SOFTWARE_FIFO_SIZE > 256 || dg_configUART2_SOFTWARE_FIFO_SIZE > 256 -typedef uint16_t fifo_ptr_t; -#else -typedef uint8_t fifo_ptr_t; -#endif - -#if dg_configUART_RX_CIRCULAR_DMA - -#if !HW_UART_USE_DMA_SUPPORT -# error "dg_configUART_RX_CIRCULAR_DMA requires HW_UART_USE_DMA_SUPPORT to be enabled!" -#endif - -#if dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE > 0 -__RETAINED static uint8_t uart1_rx_dma_buf[dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE]; -#else -#define uart1_rx_dma_buf (NULL) -#endif - -#if dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE > 0 -__RETAINED static uint8_t uart2_rx_dma_buf[dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE]; -#else -#define uart2_rx_dma_buf (NULL) -#endif - -#endif /* dg_configUART_RX_CIRCULAR_DMA */ - -typedef struct { -#ifdef HW_UART_ENABLE_USER_ISR - hw_uart_interrupt_isr user_isr; -#endif - const uint8_t *tx_buffer; - void *tx_user_data; - hw_uart_tx_callback tx_cb; - uint16_t tx_len; - uint16_t tx_ix; - - void *rx_user_data; - uint8_t *rx_buffer; - hw_uart_rx_callback rx_cb; - uint16_t rx_len; - uint16_t rx_ix; - - uint8_t tx_fifo_on:1; - uint8_t rx_fifo_on:1; - uint8_t tx_fifo_level:2; - uint8_t rx_fifo_level:2; -#if dg_configUART_SOFTWARE_FIFO - uint8_t *rx_soft_fifo; - fifo_size_t rx_soft_fifo_size; - fifo_ptr_t rx_soft_fifo_rd_ptr; - fifo_ptr_t rx_soft_fifo_wr_ptr; -#endif -#if HW_UART_USE_DMA_SUPPORT - uint8_t use_dma:1; - DMA_setup tx_dma; - DMA_setup rx_dma; -#if dg_configUART_RX_CIRCULAR_DMA - bool rx_dma_active; - uint8_t *rx_dma_buf; - uint16_t rx_dma_buf_size; - uint16_t rx_dma_head; -#endif /* dg_configUART_RX_CIRCULAR_DMA */ -#endif /* HW_UART_USE_DMA_SUPPORT */ -} UART_Data; - -__RETAINED_RW static UART_Data uart_data[2] = { - { -#if dg_configUART_SOFTWARE_FIFO - .rx_soft_fifo = uart1_sw_fifo, - .rx_soft_fifo_size = dg_configUART1_SOFTWARE_FIFO_SIZE, -#endif -#if dg_configUART_RX_CIRCULAR_DMA - .rx_dma_buf = uart1_rx_dma_buf, - .rx_dma_buf_size = dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE, -#endif - }, - { -#if dg_configUART_SOFTWARE_FIFO - .rx_soft_fifo = uart2_sw_fifo, - .rx_soft_fifo_size = dg_configUART2_SOFTWARE_FIFO_SIZE, -#endif -#if dg_configUART_RX_CIRCULAR_DMA - .rx_dma_buf = uart2_rx_dma_buf, - .rx_dma_buf_size = dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE, -#endif - }, -}; - -#define UART_INT(id) ((id) == HW_UART1 ? (UART_IRQn) : (UART2_IRQn)) -#define UARTIX(id) ((id) == HW_UART1 ? 0 : 1) -#define UARTDATA(id) (&uart_data[UARTIX(id)]) -#define UARTID(ud) ((ud) == uart_data ? HW_UART1 : HW_UART2) - -#ifdef HW_UART_ENABLE_USER_ISR -void hw_uart_set_isr(HW_UART_ID uart, hw_uart_interrupt_isr isr) -{ - uart_data[UARTIX(uart)].user_isr = isr; -} -#endif - -//===================== Read/Write functions =================================== - -uint8_t hw_uart_read(HW_UART_ID uart) -{ - // Wait until received data are available - while (hw_uart_read_buf_empty(uart)); - - // Read element from the receive FIFO - return UBA(uart)->UART2_RBR_THR_DLL_REG; -} - -void hw_uart_write(HW_UART_ID uart, uint8_t data) -{ - // Wait if Transmit Holding Register is full - while (hw_uart_write_buf_full(uart)); - - // Write data to the transmit FIFO - UBA(uart)->UART2_RBR_THR_DLL_REG = data; -} - -void hw_uart_write_buffer(HW_UART_ID uart, const void *data, uint16_t len) -{ - const uint8_t *p = data; - - while (len > 0) { - hw_uart_write(uart, *p++); - len--; - } -} - -void hw_uart_send(HW_UART_ID uart, const void *data, uint16_t len, hw_uart_tx_callback cb, - void *user_data) -{ - UART_Data *ud = &uart_data[UARTIX(uart)]; - - if (cb == NULL) { - hw_uart_write_buffer(uart, data, len); - ud->tx_ix = 0; - ud->tx_len = 0; - return; - } - ud->tx_buffer = data; - ud->tx_user_data = user_data; - ud->tx_len = len; - ud->tx_ix = 0; - ud->tx_cb = cb; - -#if HW_UART_USE_DMA_SUPPORT - if (ud->tx_dma.channel_number != HW_DMA_CHANNEL_INVALID && len > 1) { - ud->tx_dma.src_address = (uint32) data; - ud->tx_dma.length = len; - // DMA requested - hw_uart_clear_dma_request(uart); - hw_dma_channel_initialization(&ud->tx_dma); - hw_dma_channel_enable(ud->tx_dma.channel_number, HW_DMA_STATE_ENABLED); - return; - } -#endif - // Interrupt driven - NVIC_DisableIRQ(UART_INT(uart)); - // Enable transmit interrupts - uint16_t ier_dlh_reg = UBA(uart)->UART2_IER_DLH_REG; - ier_dlh_reg |= ((1 << UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos) | (1 << UART_UART_IER_DLH_REG_PTIME_dlh7_Pos)); - UBA(uart)->UART2_IER_DLH_REG = ier_dlh_reg; - - NVIC_EnableIRQ(UART_INT(uart)); -} - -static inline void hw_uart_enable_rx_int(HW_UART_ID uart, bool enable) -{ - NVIC_DisableIRQ(UART_INT(uart)); - HW_UART_REG_SETF(uart, IER_DLH, ERBFI_dlh0, enable); - NVIC_EnableIRQ(UART_INT(uart)); -} - -#if dg_configUART_SOFTWARE_FIFO - -#define SOFTWARE_FIFO_PRESENT(ud) ((ud)->rx_soft_fifo != NULL) - -/* - * Copy bytes from software FIFO to user provided buffer. - * This function allows software FIFO interrupts to read more data while copy takes place. - * - * Function returns true if all requested data is already in user buffer. - */ -static bool hw_uart_drain_rx(HW_UART_ID uart, UART_Data *ud, int len) -{ - /* - * This function is called with RX interrupt disabled. - * - * Get current software FIFO pointers before enabling interrupt again. - * ud->rx_len is still set to 0, so interrupt will not try to copy data to - * application buffer till all data from software FIFO is drained to user buffer. - */ - fifo_ptr_t rd_ptr = ud->rx_soft_fifo_rd_ptr; - fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr; - int idx = 0; - - /* - * ud->rx_ix is 0, set ud->rx_len to 0 to prevent interrupt from using it - * before all data from software FIFO is moved to application buffer. - */ - ud->rx_len = 0; - - hw_uart_enable_rx_int(uart, true); - - while (idx < len) { - - if (wr_ptr == rd_ptr) { - /* - * No more data in software FIFO, at least from state before - * interrupt was enabled. - * Disable interrupt and update read pointer to reflect position - * of already copied data. - */ - hw_uart_enable_rx_int(uart, false); - ud->rx_soft_fifo_rd_ptr = rd_ptr; - - /* - * Check if write pointer moved, if so interrupt put some more data - * in buffer. Remember current write position and try again with - * interrupts enabled. - */ - if (ud->rx_soft_fifo_wr_ptr != wr_ptr) { - wr_ptr = ud->rx_soft_fifo_wr_ptr; - hw_uart_enable_rx_int(uart, true); - continue; - } - - /* - * All was copied from software FIFO. - * Setup user transaction ix and len so when interrupts are enabled - * again (not in this function) interrupt or DMA can continue. - */ - ud->rx_ix = idx; - ud->rx_len = len; - - return false; - } - - /* Copy from software FIFO to user provided buffer */ - ud->rx_buffer[idx++] = ud->rx_soft_fifo[rd_ptr++]; - - if (rd_ptr >= ud->rx_soft_fifo_size) { - rd_ptr = 0; - } - } - - /* - * User buffer is filled, block interrupt so end of transmission callback will not be - * called from interrupt. - */ - hw_uart_enable_rx_int(uart, false); - ud->rx_soft_fifo_rd_ptr = rd_ptr; - ud->rx_len = len; - ud->rx_ix = len; - - return true; -} - -void hw_uart_read_buffer(HW_UART_ID uart, void *data, uint16_t len) -{ - UART_Data *ud = UARTDATA(uart); - uint8_t *p = data; - - /* - * Disable RX interrupt before draining software FIFO. - */ - hw_uart_enable_rx_int(uart, false); - if (SOFTWARE_FIFO_PRESENT(ud)) { - /* - * Drain uses ud fields so setup them accordingly. - */ - ud->rx_buffer = data; - - hw_uart_drain_rx(uart, ud, len); - len -= ud->rx_ix; - p += ud->rx_ix; - } - /* - * Read all remaining bytes with RX interrupt still disabled. - */ - while (len > 0) { - *p++ = hw_uart_read(uart); - len--; - } - ud->rx_ix = 0; - ud->rx_len = 0; - hw_uart_enable_rx_int(uart, SOFTWARE_FIFO_PRESENT(ud)); -} - -void hw_uart_set_soft_fifo(HW_UART_ID uart, uint8_t *buf, uint8_t size) -{ - UART_Data *ud = UARTDATA(uart); - - hw_uart_enable_rx_int(uart, false); - - ud->rx_soft_fifo = buf; - ud->rx_soft_fifo_size = size; - ud->rx_soft_fifo_rd_ptr = 0; - ud->rx_soft_fifo_wr_ptr = 0; - - hw_uart_enable_rx_int(uart, buf != NULL); -} - -#else - -#define SOFTWARE_FIFO_PRESENT(ud) false - -void hw_uart_read_buffer(HW_UART_ID uart, void *data, uint16_t len) -{ - uint8_t *p = data; - - while (len > 0) { - *p++ = hw_uart_read(uart); - len--; - } -} -#endif - -static void hw_uart_fire_callback(UART_Data *ud) -{ - hw_uart_rx_callback cb = ud->rx_cb; - ud->rx_cb = NULL; - /* Just finished receiving, disable RX interrupts unless software FIFO is enabled */ - hw_uart_enable_rx_int(UARTID(ud), SOFTWARE_FIFO_PRESENT(ud)); - if (cb) { - cb(ud->rx_user_data, ud->rx_len); - } -} - -void hw_uart_receive(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callback cb, - void *user_data) -{ - UART_Data *ud = UARTDATA(uart); - - if (cb == NULL) { - hw_uart_read_buffer(uart, data, len); - ud->rx_ix = 0; - ud->rx_len = 0; - return; - } - - ud->rx_buffer = data; - ud->rx_user_data = user_data; - hw_uart_enable_rx_int(uart, false); - ud->rx_len = len; - ud->rx_ix = 0; - ud->rx_cb = cb; -#if dg_configUART_SOFTWARE_FIFO - if (hw_uart_drain_rx(uart, ud, len)) { - hw_uart_fire_callback(ud); - return; - } -#endif - -#if dg_configUART_RX_CIRCULAR_DMA - if (ud->rx_dma_buf_size > 0) { - ASSERT_ERROR(len < ud->rx_dma_buf_size); - - uint16_t new_int, cur_idx; - bool data_ready = false; - - ASSERT_ERROR(ud->rx_dma_active == false); - - /* Calculate index of end of requested data (do not wrap it!) */ - new_int = ud->rx_dma_head + ud->rx_len - 1; - - /* Freeze DMA so it does not move pointers while we try to update them */ - hw_dma_freeze(); - - cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); - - /* cur_idx is lower than rx_head only if it wrapped-around - fix it */ - if (cur_idx < ud->rx_dma_head) { - cur_idx += ud->rx_dma_buf_size; - } - - /* - * If DMA has not read past the calculated index, we can set it and just wait for an - * interrupt. In other case, data are ready immediately in buffer. - */ - if (cur_idx <= new_int) { - new_int %= ud->rx_dma_buf_size; - hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, new_int); - ud->rx_dma_active = true; - } else { - hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, cur_idx - 1); - data_ready = true; - } - - /* Unfreeze DMA now, it can start reading */ - hw_dma_unfreeze(); - - /* Fire callback immediately if data already available in buffer */ - if (data_ready) { - hw_uart_fire_callback(ud); - } - - return; - } -#endif - -#if HW_UART_USE_DMA_SUPPORT - if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID && (ud->rx_len - ud->rx_ix > 1)) { - /* rx_ix could already be changed by hw_uart_drain_rx() */ - ud->rx_dma.dest_address = (uint32) data + ud->rx_ix; - ud->rx_dma.length = ud->rx_len - ud->rx_ix; - hw_uart_clear_dma_request(uart); - /* Prepare and start DMA */ - hw_dma_channel_initialization(&ud->rx_dma); - hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_ENABLED); - return; - } -#endif - /* Interrupt driven */ - hw_uart_enable_rx_int(uart, true); -} - -static void hw_uart_irq_stop_receive(HW_UART_ID uart) -{ - UART_Data *ud = &uart_data[UARTIX(uart)]; - - // Disable RX interrupt - hw_uart_enable_rx_int(uart, false); - - ud->rx_len = ud->rx_ix; - - hw_uart_fire_callback(ud); -} - -#if dg_configUART_RX_CIRCULAR_DMA -static void hw_uart_copy_dma_rx_to_user_buffer(HW_UART_ID uart) -{ - UART_Data *ud = &uart_data[UARTIX(uart)]; - - uint16_t cur_idx; - uint16_t to_copy = 0; - hw_uart_rx_callback cb; - - ud->rx_dma_active = false; - cb = ud->rx_cb; - - if (cb) { - ud->rx_cb = NULL; - /* - * User callback was not fired, since rx_dma_active is false it will not - * fire even if requested number of bytes was received when abort was initiated. - */ - cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); - - if (ud->rx_ix < ud->rx_len) { - if (cur_idx < ud->rx_dma_head) { - cur_idx += ud->rx_dma_buf_size; - } - to_copy = cur_idx - ud->rx_dma_head; - if (to_copy >= ud->rx_len - ud->rx_ix) { - to_copy = ud->rx_len - ud->rx_ix; - } - } - } else { - /* - * Callback already fired, circular buffer holds enough data. - */ - to_copy = ud->rx_len - ud->rx_ix; - } - - hw_uart_copy_rx_circular_dma_buffer(uart, ud->rx_buffer + ud->rx_ix, to_copy); - ud->rx_ix += to_copy; - ud->rx_len = ud->rx_ix; - - if (cb) { - cb(ud->rx_user_data, ud->rx_len); - } -} -#endif - -uint16_t hw_uart_abort_receive(HW_UART_ID uart) -{ - UART_Data *ud = &uart_data[UARTIX(uart)]; - -#if HW_UART_USE_DMA_SUPPORT - if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID) { -#if dg_configUART_RX_CIRCULAR_DMA - if (ud->rx_dma_buf_size > 0) { - hw_uart_copy_dma_rx_to_user_buffer(uart); - return ud->rx_ix; - } -#else - /* No DMA circular buffer, stop DMA */ - hw_dma_channel_stop(ud->rx_dma.channel_number); -#endif - } - else -#endif - hw_uart_irq_stop_receive(uart); - - return ud->rx_ix; -} - -uint16_t hw_uart_peek_received(HW_UART_ID uart) -{ - UART_Data *ud = &uart_data[UARTIX(uart)]; - -#if HW_UART_USE_DMA_SUPPORT - if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID) - ud->rx_ix = hw_dma_transfered_bytes(ud->rx_dma.channel_number); -#endif - return ud->rx_ix; -} - -//============== Interrupt handling ============================================ - -static inline void hw_uart_tx_isr(HW_UART_ID uart) -{ - UART_Data *ud = UARTDATA(uart); - - while (ud->tx_ix < ud->tx_len) { - if (ud->tx_fifo_on) { - if (!hw_uart_transmit_fifo_not_full(uart)) { - break; - } - } else if (!hw_uart_thr_empty_getf(uart)) { - break; - } - hw_uart_txdata_setf(uart, ud->tx_buffer[ud->tx_ix++]); - } - // Everything sent? - if (ud->tx_ix >= ud->tx_len) { - hw_uart_tx_callback cb = ud->tx_cb; - // Disable TX interrupts - // They can be re-enabled in user callback - uint16_t ier_dlh_reg = UBA(uart)->UART2_IER_DLH_REG; - ier_dlh_reg &= ~((1 << UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos) | (1 << UART_UART_IER_DLH_REG_PTIME_dlh7_Pos)); - UBA(uart)->UART2_IER_DLH_REG = ier_dlh_reg; - ud->tx_cb = NULL; - if (cb) { - cb(ud->tx_user_data, ud->tx_len); - } - } -} - -static inline void hw_uart_rx_isr(HW_UART_ID uart) -{ - UART_Data *ud = UARTDATA(uart); - - if (SOFTWARE_FIFO_PRESENT(ud)) { -#if dg_configUART_SOFTWARE_FIFO - for (;;) { - fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr + 1; - if (wr_ptr >= ud->rx_soft_fifo_size) { - wr_ptr = 0; - } - if (wr_ptr == ud->rx_soft_fifo_rd_ptr) { - /* Software FIFO full, disable interrupt since no one is reading */ - hw_uart_enable_rx_int(uart, false); - return; - } - if (!hw_uart_is_data_ready(uart)) { - break; - } - ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr] = hw_uart_rxdata_getf(uart); - - /* - * Application read is in progress. Copy data from software FIFO to - * user provided buffer. - */ - if (ud->rx_ix < ud->rx_len) { - ud->rx_buffer[ud->rx_ix++] = ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr]; - /* - * When application read is in progress, rx_ix < rx_len - * This interrupt is enabled only if all data was already copied from - * FIFO to user buffer. It is safe to modify rx_soft_fifo_rd_ptr. - */ - ud->rx_soft_fifo_rd_ptr = wr_ptr; - } - - ud->rx_soft_fifo_wr_ptr = wr_ptr; - } -#endif - } else { - while (ud->rx_ix < ud->rx_len) { - if (hw_uart_is_data_ready(uart)) { - ud->rx_buffer[ud->rx_ix++] = hw_uart_rxdata_getf(uart); - } else { - break; - } - } - } - - // Everything read? - if (ud->rx_len > 0 && ud->rx_ix >= ud->rx_len) { - // Disable RX interrupts, fire callback if present - hw_uart_irq_stop_receive(uart); - } - -} - -static inline void hw_uart_rx_timeout_isr(HW_UART_ID uart) -{ - UART_Data *ud = UARTDATA(uart); - - hw_uart_rx_isr(uart); - - /* - * Not everything was received yet, disable interrupt anyway since - * some data was received. - */ - if (ud->rx_ix > 0 && ud->rx_ix < ud->rx_len) { - // Disable RX interrupts fire callback if present - hw_uart_irq_stop_receive(uart); - } -} - -void UART_Interrupt_Handler(HW_UART_ID uart) -{ - HW_UART_INT int_id; - - for (;;) { - int_id = hw_uart_get_interrupt_id(uart); - switch (int_id) { - case HW_UART_INT_TIMEOUT: - hw_uart_rx_timeout_isr(uart); - break; - case HW_UART_INT_MODEM_STAT: - break; - case HW_UART_INT_NO_INT_PEND: - return; - break; - case HW_UART_INT_THR_EMPTY: - hw_uart_tx_isr(uart); - break; - case HW_UART_INT_RECEIVED_AVAILABLE: - hw_uart_rx_isr(uart); - break; - case HW_UART_INT_RECEIVE_LINE_STAT: - break; - case HW_UART_INT_BUSY_DETECTED: -#ifdef CONFIG_UART_IGNORE_BUSY_DETECT - hw_uart_transmit_fifo_empty(uart); -#else - /* - * Stop here means that timing rules for access divisor latch were not - * followed. See description of register RBR_THR_DLL. - */ - __BKPT(0); -#endif - break; - } - } -} - -/** - * \brief HW_UART1 Interrupt Handler - * - */ -void UART_Handler(void) -{ - SEGGER_SYSTEMVIEW_ISR_ENTER(); - -#ifdef HW_UART_ENABLE_USER_ISR - if (uart_data[UARTIX(HW_UART1)].user_isr) { - uart_data[UARTIX(HW_UART1)].user_isr(); - } else { -#endif - UART_Interrupt_Handler(HW_UART1); -#ifdef HW_UART_ENABLE_USER_ISR - } -#endif - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - -/** - * \brief UART2 Interrupt Handler - * - */ -void UART2_Handler(void) -{ - SEGGER_SYSTEMVIEW_ISR_ENTER(); - -#ifdef HW_UART_ENABLE_USER_ISR - if (uart_data[UARTIX(HW_UART2)].user_isr) { - uart_data[UARTIX(HW_UART2)].user_isr(); - } else { -#endif - UART_Interrupt_Handler(HW_UART2); -#ifdef HW_UART_ENABLE_USER_ISR - } -#endif - - SEGGER_SYSTEMVIEW_ISR_EXIT(); -} - -//==================== Configuration functions ================================= - -HW_UART_BAUDRATE hw_uart_baudrate_get(HW_UART_ID uart) -{ - uint32_t baud_rate; - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Read baud rate low byte from DLL register - baud_rate = (0xFF & UBA(uart)->UART2_RBR_THR_DLL_REG) << 8; - // Read baud rate high byte from DLH register - baud_rate += (0xFF & UBA(uart)->UART2_IER_DLH_REG) << 16; - // Read baud rate fraction byte from DLF register - baud_rate += 0xFF & UBA(uart)->UART2_DLF_REG; - // Reset Divisor Latch Access Bit in Line Control Register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - - return (HW_UART_BAUDRATE) baud_rate; -} - -void hw_uart_baudrate_set(HW_UART_ID uart, HW_UART_BAUDRATE baud_rate) -{ - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (baud_rate >> 8); - // Set high byte of baud rare - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); -} - -//=========================== FIFO control functions =========================== - -uint8_t hw_uart_fifo_en_getf(HW_UART_ID uart) -{ - uint16_t fifo_enabled; - - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - fifo_enabled = (UBA(uart)->UART2_IIR_FCR_REG & 0x00C0); /* Bits[7:6] */ - - switch (fifo_enabled) { - case 0x00C0: - return 1; - case 0x0000: - return 0; - default: - ASSERT_ERROR(0); - return 255; // To satisfy the compiler - } -} - -uint8_t hw_uart_tx_fifo_tr_lvl_getf(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - - return (UART2->UART2_STET_REG & HW_UART_REG_FIELD_MASK(2, STET, UART_SHADOW_TX_EMPTY_TRIGGER)) - >> HW_UART_REG_FIELD_POS(2, STET, UART_SHADOW_TX_EMPTY_TRIGGER); -} - -//=========================== DMA control functions ============================ - -#if HW_UART_USE_DMA_SUPPORT - -static void hw_uart_rx_dma_callback(void *user_data, uint16_t len) -{ - UART_Data *ud = user_data; - hw_uart_rx_callback cb = ud->rx_cb; - - ud->rx_cb = NULL; - ud->rx_ix += len; - if (cb) { - ud->rx_len = ud->rx_ix; - hw_uart_enable_rx_int(UARTID(ud), SOFTWARE_FIFO_PRESENT(ud)); - cb(ud->rx_user_data, ud->rx_ix); - } -} - -static void hw_uart_tx_dma_callback(void *user_data, uint16_t len) -{ - UART_Data *ud = user_data; - hw_uart_tx_callback cb = ud->tx_cb; - - ud->tx_cb = NULL; - ud->tx_ix = len; - if (cb) { - cb(ud->tx_user_data, len); - } -} - -void hw_uart_set_dma_channels(HW_UART_ID uart, int8_t channel, HW_DMA_PRIO pri) -{ - UART_Data *ud = UARTDATA(uart); - - /* Only specific DMA channels (or -1 for no DMA) are allowed */ - ASSERT_ERROR(channel < 0 || - channel == HW_DMA_CHANNEL_0 || - channel == HW_DMA_CHANNEL_2 || - channel == HW_DMA_CHANNEL_4 || - channel == HW_DMA_CHANNEL_6 || - channel == HW_DMA_CHANNEL_INVALID); - - if (channel < 0) { - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - } else { - ud->use_dma = 1; - - ud->rx_dma.channel_number = channel; - ud->rx_dma.bus_width = HW_DMA_BW_BYTE; - ud->rx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->rx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->rx_dma.irq_nr_of_trans = 0; - ud->rx_dma.a_inc = HW_DMA_AINC_FALSE; - ud->rx_dma.b_inc = HW_DMA_BINC_TRUE; - ud->rx_dma.circular = HW_DMA_MODE_NORMAL; - ud->rx_dma.dma_prio = pri; - ud->rx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->rx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->rx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->rx_dma.src_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->rx_dma.dest_address = 0; // Change during transmission - ud->rx_dma.length = 0; // Change during transmission - ud->rx_dma.callback = hw_uart_rx_dma_callback; - ud->rx_dma.user_data = ud; - - ud->tx_dma.channel_number = channel + 1; - ud->tx_dma.bus_width = HW_DMA_BW_BYTE; - ud->tx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->tx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->tx_dma.irq_nr_of_trans = 0; - ud->tx_dma.a_inc = HW_DMA_AINC_TRUE; - ud->tx_dma.b_inc = HW_DMA_BINC_FALSE; - ud->tx_dma.circular = HW_DMA_MODE_NORMAL; - ud->tx_dma.dma_prio = pri; - ud->tx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->tx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->tx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->tx_dma.src_address = 0; // Change during transmission - ud->tx_dma.dest_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->tx_dma.length = 0; // Change during transmission - ud->tx_dma.callback = hw_uart_tx_dma_callback; - ud->tx_dma.user_data = ud; - } -} - -void hw_uart_set_dma_channels_ex(HW_UART_ID uart, int8_t tx_channel, int8_t rx_channel, HW_DMA_PRIO pri) -{ - UART_Data *ud = UARTDATA(uart); - - /* Only specific DMA channels are allowed (or HW_DMA_CHANNEL_INVALID for no DMA) */ - ASSERT_ERROR(tx_channel >= HW_DMA_CHANNEL_0 && - tx_channel <= HW_DMA_CHANNEL_INVALID); - - /* Only specific DMA channels are allowed (or HW_DMA_CHANNEL_INVALID for no DMA) */ - ASSERT_ERROR(rx_channel >= HW_DMA_CHANNEL_0 && - rx_channel <= HW_DMA_CHANNEL_INVALID); - - if (tx_channel == HW_DMA_CHANNEL_INVALID && rx_channel== HW_DMA_CHANNEL_INVALID) { - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - } else { - if (tx_channel != HW_DMA_CHANNEL_INVALID && rx_channel!= HW_DMA_CHANNEL_INVALID) {//not both invalid - ASSERT_ERROR(tx_channel != rx_channel);//not equal - ASSERT_ERROR(tx_channel>>1 == rx_channel>>1);//on same pair - } - if (tx_channel != HW_DMA_CHANNEL_INVALID) { - ASSERT_ERROR(tx_channel & 1);//odd number - } - if (rx_channel != HW_DMA_CHANNEL_INVALID) { - ASSERT_ERROR((rx_channel & 1) == 0);//odd number - } - - ud->use_dma = 1; - - ud->rx_dma.channel_number = rx_channel; - ud->rx_dma.bus_width = HW_DMA_BW_BYTE; - ud->rx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->rx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->rx_dma.irq_nr_of_trans = 0; - ud->rx_dma.a_inc = HW_DMA_AINC_FALSE; - ud->rx_dma.b_inc = HW_DMA_BINC_TRUE; - ud->rx_dma.circular = HW_DMA_MODE_NORMAL; - ud->rx_dma.dma_prio = pri; - ud->rx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->rx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->rx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->rx_dma.src_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->rx_dma.dest_address = 0; // Change during transmission - ud->rx_dma.length = 0; // Change during transmission - ud->rx_dma.callback = hw_uart_rx_dma_callback; - ud->rx_dma.user_data = ud; - - ud->tx_dma.channel_number = tx_channel; - ud->tx_dma.bus_width = HW_DMA_BW_BYTE; - ud->tx_dma.irq_enable = HW_DMA_IRQ_STATE_ENABLED; - ud->tx_dma.dma_req_mux = UARTIX(uart) == 0 ? HW_DMA_TRIG_UART_RXTX : - HW_DMA_TRIG_UART2_RXTX; - ud->tx_dma.irq_nr_of_trans = 0; - ud->tx_dma.a_inc = HW_DMA_AINC_TRUE; - ud->tx_dma.b_inc = HW_DMA_BINC_FALSE; - ud->tx_dma.circular = HW_DMA_MODE_NORMAL; - ud->tx_dma.dma_prio = pri; - ud->tx_dma.dma_idle = HW_DMA_IDLE_INTERRUPTING_MODE; /* Not used by the HW in this case */ - ud->tx_dma.dma_init = HW_DMA_INIT_AX_BX_AY_BY; - ud->tx_dma.dreq_mode = HW_DMA_DREQ_TRIGGERED; - ud->tx_dma.src_address = 0; // Change during transmission - ud->tx_dma.dest_address = (uint32_t) &UBA(uart)->UART2_RBR_THR_DLL_REG; - ud->tx_dma.length = 0; // Change during transmission - ud->tx_dma.callback = hw_uart_tx_dma_callback; - ud->tx_dma.user_data = ud; - } -} - -#if dg_configUART_RX_CIRCULAR_DMA - -static void hw_uart_rx_circular_dma_callback(void *user_data, uint16_t len) -{ - UART_Data *ud = user_data; - hw_uart_rx_callback cb = ud->rx_cb; - - if (!ud->rx_dma_active) { - return; - } - - ud->rx_cb = NULL; - ud->rx_dma_active = false; - - if (cb) { - cb(ud->rx_user_data, ud->rx_len); - } -} - -void hw_uart_enable_rx_circular_dma(HW_UART_ID uart) -{ - UART_Data *ud = UARTDATA(uart); - - ASSERT_ERROR(ud->rx_dma_buf_size > 0); - - hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_DISABLED); - - /* Need to reconfigure few things for circular operation... */ - ud->rx_dma.circular = HW_DMA_MODE_CIRCULAR; - ud->rx_dma.dest_address = (uint32_t) ud->rx_dma_buf; - ud->rx_dma.length = ud->rx_dma_buf_size; - ud->rx_dma.callback = hw_uart_rx_circular_dma_callback; - ud->rx_dma.user_data = ud; - - /* Reset DMA buffer read pointer */ - ud->rx_dma_head = 0; - - /* Start DMA now since it should be always-running */ - hw_uart_clear_dma_request(uart); - hw_dma_channel_initialization(&ud->rx_dma); - hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_ENABLED); -} - -void hw_uart_copy_rx_circular_dma_buffer(HW_UART_ID uart, uint8_t *buf, uint16_t len) -{ - UART_Data *ud = UARTDATA(uart); - - ASSERT_ERROR(len < ud->rx_dma_buf_size); - - if (ud->rx_dma_head + len <= ud->rx_dma_buf_size) { - memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], len); - } else { - uint16_t chunk_len = ud->rx_dma_buf_size - ud->rx_dma_head; - memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], chunk_len); - memcpy(buf + chunk_len, &ud->rx_dma_buf[0], len - chunk_len); - } - - /* This should be protected so ISR does not try to read rx_dma_head while we update it */ - GLOBAL_INT_DISABLE(); - ud->rx_dma_head = (ud->rx_dma_head + len) % ud->rx_dma_buf_size; - GLOBAL_INT_RESTORE(); -} - -#endif /* dg_configUART_RX_CIRCULAR_DMA */ - -#endif /* HW_UART_USE_DMA_SUPPORT */ - -//=========================== Line control functions ============================ -void hw_uart_init_ex(HW_UART_ID uart, const uart_config_ex *uart_init) -{ - UART_Data *ud = UARTDATA(uart); - - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); - - - if (uart == HW_UART1) { - // there is no FIFO for UART0 as yet - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; - hw_uart_disable_fifo(uart); - } else { - if (uart_init->use_fifo) { - ud->rx_fifo_on = 1; - ud->tx_fifo_on = 1; - hw_uart_enable_fifo(uart); - ud->rx_fifo_level = uart_init->rx_fifo_tr_lvl; - hw_uart_rx_fifo_tr_lvl_setf(uart, uart_init->rx_fifo_tr_lvl); - ud->tx_fifo_level = uart_init->tx_fifo_tr_lvl; - hw_uart_tx_fifo_tr_lvl_setf(uart, uart_init->tx_fifo_tr_lvl); - } else { - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; - hw_uart_disable_fifo(uart); - } - } - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rate - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - ud->tx_cb = NULL; - ud->rx_cb = NULL; - ud->rx_len = 0; - ud->tx_len = 0; - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; -#if HW_UART_USE_DMA_SUPPORT - if (uart_init->use_dma) { - hw_uart_set_dma_channels_ex(uart, uart_init->tx_dma_channel, uart_init->rx_dma_channel, HW_DMA_PRIO_2); - } -#endif -} - -void hw_uart_reinit_ex(HW_UART_ID uart, const uart_config_ex *uart_init) -{ - UART_Data *ud = UARTDATA(uart); - - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); - - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); - - if (uart == HW_UART2) { - if (uart_init->use_fifo) { - hw_uart_enable_fifo(uart); - hw_uart_rx_fifo_tr_lvl_setf(uart, uart_init->rx_fifo_tr_lvl); - hw_uart_tx_fifo_tr_lvl_setf(uart, uart_init->tx_fifo_tr_lvl); - } else { - hw_uart_disable_fifo(uart); - } - } - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rare - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - - if (ud->rx_cb && ud->rx_len != ud->rx_ix) { - if (ud->rx_len > 1 && uart_init->use_dma && uart_init->rx_dma_channel != HW_DMA_CHANNEL_INVALID) { - } else { - // Interrupt driven - hw_uart_enable_rx_int(uart, true); - } - } -} - -void hw_uart_init(HW_UART_ID uart, const uart_config *uart_init) -{ - UART_Data *ud = UARTDATA(uart); - - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); - - - if (uart == HW_UART1) { - // there is no FIFO for UART0 as yet - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; - hw_uart_disable_fifo(uart); - } else { - if (uart_init->use_fifo) { - ud->rx_fifo_on = 1; - ud->tx_fifo_on = 1; - hw_uart_enable_fifo(uart); - hw_uart_rx_fifo_tr_lvl_setf(uart, 0); - hw_uart_tx_fifo_tr_lvl_setf(uart, 0); - } else { - ud->rx_fifo_on = 0; - ud->tx_fifo_on = 0; - hw_uart_disable_fifo(uart); - } - } - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rate - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - ud->tx_cb = NULL; - ud->rx_cb = NULL; - ud->rx_len = 0; - ud->tx_len = 0; - ud->use_dma = 0; - ud->rx_dma.channel_number = HW_DMA_CHANNEL_INVALID; - ud->tx_dma.channel_number = HW_DMA_CHANNEL_INVALID; -#if HW_UART_USE_DMA_SUPPORT - if (uart_init->use_dma) { - hw_uart_set_dma_channels_ex(uart, uart_init->tx_dma_channel, uart_init->rx_dma_channel, HW_DMA_PRIO_2); - } -#endif -} - -void hw_uart_reinit(HW_UART_ID uart, const uart_config *uart_init) -{ - UART_Data *ud = UARTDATA(uart); - - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); - GLOBAL_INT_RESTORE(); - - /* - * Read UART_USR_REG to clear any pending busy interrupt. - */ - hw_uart_transmit_fifo_empty(uart); - - if (uart == HW_UART2) { - if (uart_init->use_fifo) { - hw_uart_enable_fifo(uart); - hw_uart_rx_fifo_tr_lvl_setf(uart, 0); - hw_uart_tx_fifo_tr_lvl_setf(uart, 0); - } else { - hw_uart_disable_fifo(uart); - } - } - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Set fraction byte of baud rate - UBA(uart)->UART2_DLF_REG = 0xFF & uart_init->baud_rate; - // Set low byte of baud rate - UBA(uart)->UART2_RBR_THR_DLL_REG = 0xFF & (uart_init->baud_rate >> 8); - // Set high byte of baud rare - UBA(uart)->UART2_IER_DLH_REG = 0xFF & (uart_init->baud_rate >> 16); - // Reset Divisor Latch Access Bit in LCR register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - // Set Parity - UBA(uart)->UART2_LCR_REG = (uart_init->parity) << 3; - // Set Data Bits - HW_UART_REG_SETF(uart, LCR, UART_DLS, uart_init->data); - // Set Stop Bits - HW_UART_REG_SETF(uart, LCR, UART_STOP, uart_init->stop); - // Set Auto flow control - HW_UART_REG_SETF(uart, MCR, UART_AFCE, uart_init->auto_flow_control); - HW_UART_REG_SETF(uart, MCR, UART_RTS, uart_init->auto_flow_control); - - if (ud->rx_cb && ud->rx_len != ud->rx_ix) { - if (ud->rx_len > 1 && uart_init->use_dma && uart_init->rx_dma_channel != HW_DMA_CHANNEL_INVALID) { - } else { - // Interrupt driven - hw_uart_enable_rx_int(uart, true); - } - } -} - -void hw_uart_cfg_get(HW_UART_ID uart, uart_config *uart_cfg) -{ -#if HW_UART_USE_DMA_SUPPORT - UART_Data *ud = UARTDATA(uart); -#endif - - // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); - // Read baud rate low byte from DLL register - uart_cfg->baud_rate = (0xFF & UBA(uart)->UART2_RBR_THR_DLL_REG) << 8; - // Read baud rate high byte from DLH register - uart_cfg->baud_rate += (0xFF & UBA(uart)->UART2_IER_DLH_REG) << 16; - // Read baud rate fraction byte from DLF register - uart_cfg->baud_rate += 0xFF & UBA(uart)->UART2_DLF_REG; - // Reset Divisor Latch Access Bit in Line Control Register - HW_UART_REG_SETF(uart, LCR, UART_DLAB, 0); - - // Fill-in the rest of the configuration settings - uart_cfg->data = HW_UART_REG_GETF(uart, LCR, UART_DLS); - uart_cfg->parity = UBA(uart)->UART2_LCR_REG; - uart_cfg->parity &= ((1 << UART_UART_LCR_REG_UART_EPS_Pos) | (1 << UART_UART_LCR_REG_UART_PEN_Pos)); - uart_cfg->parity = uart_cfg->parity >> UART_UART_LCR_REG_UART_PEN_Pos; - uart_cfg->stop = HW_UART_REG_GETF(uart, LCR, UART_STOP); -#if HW_UART_USE_DMA_SUPPORT - uart_cfg->tx_dma_channel = ud->tx_dma.channel_number; - uart_cfg->rx_dma_channel = ud->rx_dma.channel_number; - uart_cfg->use_dma = ud->use_dma; -#endif - uart_cfg->auto_flow_control = hw_uart_afce_getf(uart); -} - -//=========================== Modem control functions ========================== - -uint8_t hw_uart_sire_getf(HW_UART_ID uart) -{ - // Get the value of the SIRE bit from the Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MCR, UART_SIRE); -} - -void hw_uart_sire_setf(HW_UART_ID uart, uint8_t sire) -{ - // Set the value of the SIRE bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_SIRE, sire); -} - -uint8_t hw_uart_afce_getf(HW_UART_ID uart) -{ - // Get the value of the AFCE bit from the Modem Control Register - return 0xFF & HW_UART_REG_GETF(uart, MCR, UART_AFCE); -} - -void hw_uart_afce_setf(HW_UART_ID uart, uint8_t afce) -{ - // Set the value of the AFCE bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_AFCE, afce); -} - -uint8_t hw_uart_loopback_getf(HW_UART_ID uart) -{ - // Get the value of the loop back (LB) bit from the Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MCR, UART_LB); -} - -void hw_uart_loopback_setf(HW_UART_ID uart, uint8_t lb) -{ - // Set the value of the loop back (LB) bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_LB, lb); -} - -uint8_t hw_uart_rts_getf(HW_UART_ID uart) -{ - // Get the value of the RTS bit from the Modem Control Register - return 0xFF & HW_UART_REG_GETF(uart, MCR, UART_RTS); -} - -void hw_uart_rts_setf(HW_UART_ID uart, uint8_t rtsn) -{ - // Set the value of the RTS bit in the Modem Control Register - HW_UART_REG_SETF(uart, MCR, UART_RTS, rtsn); -} - -//=========================== Line status functions ============================ - -uint8_t hw_uart_rx_fifo_err_getf(HW_UART_ID uart) -{ - /* Only UART2 has a FIFO */ - ASSERT_ERROR(uart == HW_UART2); - // Get Receiver FIFO Error bit - return (uint8_t) HW_UART_REG_GETF(uart, LSR, UART_RFE); -} - -uint8_t hw_uart_is_tx_fifo_empty(HW_UART_ID uart) -{ - // Get Transmitter Empty bit from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_TEMT) != 0; -} - -uint8_t hw_uart_thr_empty_getf(HW_UART_ID uart) -{ - // Get Transmit Holding Register Empty bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_THRE); -} - -uint8_t hw_uart_break_int_getf(HW_UART_ID uart) -{ - // Get Break Interrupt bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_BI); -} - -uint8_t hw_uart_frame_err_getf(HW_UART_ID uart) -{ - // Get Framing Error bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_FE); -} - -uint8_t hw_uart_parity_err_getf(HW_UART_ID uart) -{ - // Get Parity Error bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_PE); -} - -uint8_t hw_uart_overrun_err_getf(HW_UART_ID uart) -{ - // Get Overrun Error bit value from Line Status Register - return HW_UART_REG_GETF(uart, LSR, UART_OE); -} - -//=========================== Modem status functions =========================== - -uint8_t hw_uart_cts_getf(HW_UART_ID uart) -{ - // Get CTS bit from Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MSR, UART_CTS); -} - -uint8_t hw_uart_delta_cts_getf(HW_UART_ID uart) -{ - // Get the DCTS bit value from the Modem Control Register - return (uint8_t) HW_UART_REG_GETF(uart, MSR, UART_DCTS); -} - -bool hw_uart_tx_in_progress(HW_UART_ID uart) -{ - UART_Data *ud = UARTDATA(uart); - return ud->tx_cb != NULL; -} - -bool hw_uart_rx_in_progress(HW_UART_ID uart) -{ - UART_Data *ud = UARTDATA(uart); - return ud->rx_cb != NULL; -} - -#endif /* dg_configUSE_HW_UART */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c deleted file mode 100644 index 78a90e3f9..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c +++ /dev/null @@ -1,172 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup Watchdog_Timer - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_watchdog.c - * - * @brief Implementation of the Watchdog timer Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ -#include -#include "hw_watchdog.h" -#include "hw_cpm.h" - -/* - * Global variables - */ -uint32_t nmi_event_data[9] __attribute__((section("nmi_info"))); - -/* - * Local variables - */ -static hw_watchdog_interrupt_cb int_handler __RETAINED = NULL; - -/* - * This is the base address in Retention RAM where the stacked information will be copied. - */ -#define STATUS_BASE (0x7FC5600) - -bool hw_watchdog_freeze(void) -{ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; - - return !REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST); -} - -void hw_watchdog_unfreeze(void) -{ - GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk; -} - -HW_WDG_RESET hw_watchdog_is_irq_or_rst_gen(void) -{ - if (REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST)) { - return HW_WDG_RESET_RST; - } - - return HW_WDG_RESET_NMI; -} - -void hw_watchdog_register_int(hw_watchdog_interrupt_cb handler) -{ - int_handler = handler; -} - -void hw_watchdog_unregister_int(void) -{ - int_handler = NULL; -} - -__RETAINED_CODE void hw_watchdog_handle_int(unsigned long *exception_args) -{ - // Reached this point due to a WDOG timeout - uint16_t pmu_ctrl_reg = CRG_TOP->PMU_CTRL_REG; - pmu_ctrl_reg |= ((1 << CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos) | /* turn off BLE */ - (1 << CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos) | /* turn off FTDF */ - (1 << CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos) | /* turn off radio PD */ - (1 << CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos)); /* turn off peripheral power domain */ - CRG_TOP->PMU_CTRL_REG = pmu_ctrl_reg; - REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, BLE_LP_RESET); /* reset the BLE LP timer */ - -#if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) - hw_watchdog_freeze(); // Stop WDOG - - ENABLE_DEBUGGER; - - if (exception_args != NULL) { - *(volatile unsigned long *)(STATUS_BASE ) = exception_args[0]; // R0 - *(volatile unsigned long *)(STATUS_BASE + 0x04) = exception_args[1]; // R1 - *(volatile unsigned long *)(STATUS_BASE + 0x08) = exception_args[2]; // R2 - *(volatile unsigned long *)(STATUS_BASE + 0x0C) = exception_args[3]; // R3 - *(volatile unsigned long *)(STATUS_BASE + 0x10) = exception_args[4]; // R12 - *(volatile unsigned long *)(STATUS_BASE + 0x14) = exception_args[5]; // LR - *(volatile unsigned long *)(STATUS_BASE + 0x18) = exception_args[6]; // PC - *(volatile unsigned long *)(STATUS_BASE + 0x1C) = exception_args[7]; // PSR - *(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)exception_args; // Stack Pointer - - *(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR - *(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR - *(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR - *(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR - *(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR - *(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR - } - - hw_cpm_assert_trigger_gpio(); - - if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE)) { - __BKPT(0); - } - else { - while (1); - } - -#else // dg_configIMAGE_SETUP == DEVELOPMENT_MODE - if (exception_args != NULL) { - nmi_event_data[0] = NMI_MAGIC_NUMBER; - nmi_event_data[1] = exception_args[0]; // R0 - nmi_event_data[2] = exception_args[1]; // R1 - nmi_event_data[3] = exception_args[2]; // R2 - nmi_event_data[4] = exception_args[3]; // R3 - nmi_event_data[5] = exception_args[4]; // R12 - nmi_event_data[6] = exception_args[5]; // LR - nmi_event_data[7] = exception_args[6]; // PC - nmi_event_data[8] = exception_args[7]; // PSR - } - - // Wait for the reset to occur - while (1); -#endif // dg_configIMAGE_SETUP == DEVELOPMENT_MODE -} - -__RETAINED_CODE void NMI_HandlerC(unsigned long *exception_args); - -void NMI_HandlerC(unsigned long *exception_args) -{ - if (int_handler) { - int_handler(exception_args); - } - else { - hw_watchdog_handle_int(exception_args); - } -} - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_wkup.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_wkup.c deleted file mode 100644 index e009d6f46..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_wkup.c +++ /dev/null @@ -1,209 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup DEVICES - * \{ - * \addtogroup Wakeup_Timer - * \{ - */ - -/** - **************************************************************************************** - * - * @file hw_wkup.c - * - * @brief Implementation of the Wakeup timer Low Level Driver. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#if dg_configUSE_HW_WKUP - - -#include -#include -#include - -static hw_wkup_interrupt_cb intr_cb __RETAINED /* = NULL*/; - -#if ((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A)) -#define PX_DATA_REG_ADDR(_port) ((uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_DATA_REG)) + _port) -#define PX_DATA_REG(_port) *PX_DATA_REG_ADDR(_port) -#define BF_GET(_var, _pos) ((_var>>_pos) & 1) - -__RETAINED volatile wkup_pin_config_t wkup_pin_config; -volatile uint8_t wkup_status[HW_GPIO_NUM_PORTS]; - -static bool hw_wkup_update_status(void) -{ - uint8_t i, j, enable_loop_cnt = 0; - uint8_t pol_rx_reg; - bool wkup_status_updated = false; - uint8_t cur_port_data[HW_GPIO_NUM_PORTS]; - - for (i = 0; i < HW_GPIO_NUM_PORTS; i++) { - wkup_status[i] = 0; - if (wkup_pin_config.pin_state[i]) { - //read port status - cur_port_data[i] = PX_DATA_REG(i); - //read trigger polarity - pol_rx_reg = *((volatile uint16_t *)WAKEUP_BASE + 10 + i); - for (j = 0; j < 8; j++) { - if ((wkup_pin_config.pin_state[i] & (1 << j)) && - (BF_GET(pol_rx_reg, j) - == BF_GET(~cur_port_data[i], j))) { - //invert trigger polarity - pol_rx_reg ^= (1 << j); - if (BF_GET(wkup_pin_config.pin_trigger[i], j) - == BF_GET(~cur_port_data[i], j)) { - wkup_status[i] |= (1 << j); - wkup_status_updated = true; - } - } - } - //update trigger polarity - *((volatile uint16_t *)WAKEUP_BASE + 10 + i) = pol_rx_reg; - } - } - - return wkup_status_updated; -} -#endif /* dg_configLATCH_WKUP_SOURCE */ - -void hw_wkup_init(const wkup_config *cfg) -{ - unsigned int i; - - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, CLK_TMR_REG, WAKEUPCT_ENABLE); - GLOBAL_INT_RESTORE(); - - /* reset configuration */ - WAKEUP->WKUP_CTRL_REG = 0; - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - WAKEUP->WKUP_COMPARE_REG = 0; -#endif - - /* disable all pins */ - for (i = 0; i < HW_GPIO_NUM_PORTS; i++) { - *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + i) = 0; - *((volatile uint16_t *)(&WAKEUP->WKUP_SELECT_P0_REG) + i) = 0; -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - *((volatile uint16_t *)(&WAKEUP-> WKUP_SEL_GPIO_P0_REG) + i) = 0; -#endif -#if dg_configLATCH_WKUP_SOURCE -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - wkup_pin_config.pin_state[i] = 0; - wkup_pin_config.pin_trigger[i] = 0; - wkup_status[i] = 0; - hw_wkup_clear_status(i, 0xFF); -#endif -#endif //dg_configLATCH_WKUP_SOURCE - } -#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A - WAKEUP->WKUP_CLEAR_0_REG = WAKEUP->WKUP_CLEAR_1_REG = WAKEUP->WKUP_CLEAR_2_REG = 0xFFFF; -#endif - NVIC_DisableIRQ(WKUP_GPIO_IRQn); - - hw_wkup_configure(cfg); -} - -void hw_wkup_configure(const wkup_config *cfg) -{ - int i; - - if (!cfg) { - return; - } - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A - hw_wkup_set_counter_threshold(cfg->threshold); -#endif -#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) - hw_wkup_set_debounce_time(cfg->debounce); -#endif - for (i = 0; i < HW_GPIO_NUM_PORTS; i++) { - hw_wkup_configure_port(i, cfg->pin_state[i], cfg->pin_trigger[i]); - } -} - -void hw_wkup_register_interrupt(hw_wkup_interrupt_cb cb, uint32_t prio) -{ - intr_cb = cb; -#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) - HW_WKUP_REG_SETF(CTRL, WKUP_ENABLE_IRQ, 1); -#endif - NVIC_ClearPendingIRQ(WKUP_GPIO_IRQn); - NVIC_SetPriority(WKUP_GPIO_IRQn, prio); - NVIC_EnableIRQ(WKUP_GPIO_IRQn); -} - -void hw_wkup_unregister_interrupt(void) -{ - intr_cb = NULL; -#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) - HW_WKUP_REG_SETF(CTRL, WKUP_ENABLE_IRQ, 0); -#endif - NVIC_DisableIRQ(WKUP_GPIO_IRQn); -} - -void hw_wkup_handler(void) -{ -#if ((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A)) - if (intr_cb && hw_wkup_update_status()) { -#else - if (intr_cb) { -#endif - intr_cb(); - } - else { - hw_wkup_reset_interrupt(); -#if dg_configLATCH_WKUP_SOURCE - hw_wkup_clear_status(HW_GPIO_PORT_0, 0xFF); - hw_wkup_clear_status(HW_GPIO_PORT_1, 0xFF); - hw_wkup_clear_status(HW_GPIO_PORT_2, 0xFF); - hw_wkup_clear_status(HW_GPIO_PORT_3, 0xFF); - hw_wkup_clear_status(HW_GPIO_PORT_4, 0xFF); -#endif - } -} - -#ifdef OS_BAREMETAL -void WKUP_GPIO_Handler(void) -{ - hw_wkup_handler(); -} -#endif - -#endif /* dg_configUSE_HW_WKUP */ -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c deleted file mode 100644 index b97f2d192..000000000 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c +++ /dev/null @@ -1,454 +0,0 @@ -/** -\addtogroup BSP -\{ -\addtogroup SYSTEM -\{ -\addtogroup TCS_Handling -\{ -*/ - -/** - **************************************************************************************** - * - * @file sys_tcs.c - * - * @brief TCS HAndler - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#include -#include "hw_cpm.h" -#include "sys_tcs.h" -#include "hw_gpadc.h" - -#define APPEND_TCS_LENGTH (0) - -#define RADIO_AREA_SIZE (0x1000) -#define PERIPHERAL_AREA_SIZE (0xC4A) - -#define IS_IN_AREA(addr, base, size) ((addr >= base) && (addr <= (base + size))) - -#define ADC_SE_GAIN_ERROR(value) ((value) & 0x0000FFFF) -#define ADC_DIFF_GAIN_ERROR(value) (((value) & 0xFFFF0000) >> 16) - -/* - * Global and / or retained variables - */ - -uint32_t tcs_data[24 * 2 + APPEND_TCS_LENGTH] __RETAINED_UNINIT; -uint8_t tcs_length __RETAINED_UNINIT; - -uint8_t area_offset[tcs_system + 1] __RETAINED; -uint8_t area_size_global[tcs_system + 1] __RETAINED; -uint16_t sys_tcs_xtal16m_settling_time __RETAINED; - - -const uint32_t *tcs_ptr __RETAINED; - -bool sys_tcs_is_calibrated_chip __RETAINED_UNINIT; // Initial value: false - -/* - * Local variables - */ - -static const uint32_t uncalibrated_tcs_data[] = { - /* BANDGAP_REG: (offset 0) - * [14]: BYPASS_COLD_BOOT_DISABLE = 0 - * [13:10]: LDO_SLEEP_TRIM = 0x4 - * [9:5]: BGR_ITRIM = 0x00 - * [4:0]: BGR_TRIM = 0x13 (change until V12 is 1.2V) - * - * Especially for this register, merge the trimmed and preferred settings. - */ - (uint32_t)&CRG_TOP->BANDGAP_REG, 0x1013, - - /* CLK_FREQ_TRIM_REG: (offset 2) - * [10:8]: COARSE_ADJ = 0x4 - * [7:0]: FINE_ADJ = 0x60 - */ - (uint32_t)&CRG_TOP->CLK_FREQ_TRIM_REG, 0x0460, - - /* CLK_16M_REG: (offset 4) - * [15]: RC16M_STARTUP_DISABLE = 0 - * [14]: XTAL16_HPASS_FLT_EN = 0 - * [13]: XTAL16_SPIKE_FLT_BYPASS = 0 - * [12:10]: XTAL16_AMP_TRIM = 0x5 - * [9]: XTAL16_EXT_CLK_ENABLE = 0 - * [8]: XTAL16_MAX_CURRENT = 0 - * [7:5]: XTAL16_CUR_SET = 0x5 - * [4:1]: RC16M_TRIM = 0x9 - * [0]: RC16M_ENABLE = 0 - * - * Apply the trimmed and a default preferred value. The correct one is applied - * later. - */ - (uint32_t)&CRG_TOP->CLK_16M_REG, 0x14B2, - - /* CLK_32K_REG: (offset 6) - * [15:13]: 0 - * [12]: XTAL32K_DISABLE_AMPREG0 = 0 - * [11:8]: RC32K_TRIM = 0x07 - * [7]: RC32K_ENABLE = 0x1 (reset value) - * [6:3]: XTAL32K_CUR = 0x3 (reset value) - * [2:1]: XTAL32K_RBIAS = 0x2 (reset value) - * [0]: XTAL32K_ENABLE = 0 - */ - (uint32_t)&CRG_TOP->CLK_32K_REG, 0x79C, - - /* CHARGER_CTRL2_REG: (offset 8) - * [15:13]: 0 - * [12:8]: CURRENT_OFFSET_TRIM = 0x0C - * [7:4]: CHARGER_VFLOAT_ADJ = 0x5 - * [3:0]: CURRENT_GAIN_TRIM = 0xA - */ - (uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 0x0C5A, -}; - -#define UNCALIBRATED_DATA_NON_RETAINED_OFFSET (8) - -#ifdef CONFIG_USE_BLE -#define UNCALIBRATED_DATA_BLE_SIZE (0) -#define UNCALIBRATED_DATA_BLE_OFFSET (0) -#endif - -#ifdef CONFIG_USE_FTDF -#define UNCALIBRATED_DATA_FTDF_SIZE (0) -#define UNCALIBRATED_DATA_FTDF_OFFSET (0) -#endif - -#define UNCALIBRATED_DATA_RADIO_SIZE (0) -#define UNCALIBRATED_DATA_RADIO_OFFSET (0) - -#define UNCALIBRATED_DATA_CHARGER_SIZE (1 * 2) -#define UNCALIBRATED_DATA_CHARGER_OFFSET (8) - -#define UNCALIBRATED_DATA_AUDIO_SIZE (0) -#define UNCALIBRATED_DATA_AUDIO_OFFSET (0) - -#define UNCALIBRATED_DATA_SYSTEM_SIZE (0) -#define UNCALIBRATED_DATA_SYSTEM_OFFSET (0) - - -/* - * Forward declarations - */ - - - -/* - * Function definitions - */ - -/** - * \brief Apply a TCS pair. - * - * \param [in] address the address of the register - * \param [in] value the value for this register - * - */ -static void apply_pair(uint32_t address, uint32_t value) -{ - if (address & 0x2) { - *(volatile uint16_t *)address = value; - } - else { - *(volatile uint32_t *)address = value; - } -} - -/** - * \brief Apply a TCS entry of the TCS array. - * - * \param [in] address the address of the register - * \param [in] value the value for this register - * - */ -static void apply_entry(uint8_t index) -{ - uint32_t address = tcs_ptr[index]; - uint32_t value = tcs_ptr[index + 1]; - - if (address & 0x2) { - *(volatile uint16_t *)address = value; - } - else { - *(volatile uint32_t *)address = value; - } -} - -/** - * \brief Store TCS pair in the Global TCS array. - * - * \param [in] address the address of the register - * \param [in] value the value for this register - * - */ -static void store_in_array(uint32_t address, uint32_t value) -{ - tcs_data[tcs_length] = address; - tcs_length++; - tcs_data[tcs_length] = value; - tcs_length++; -} - -/** - * \brief Swaps the contents of two entries in the TCS array. - * - * \param [in] address the address of the register - * \param [in] value the value for this register - * - * \warning When this function is called, the RC16 must have been set as the system clock! - * - */ -static void swap_entries(uint32_t first_pos, uint32_t second_pos) -{ - uint32_t address_stored; - uint32_t value_stored; - - address_stored = tcs_data[second_pos]; - value_stored = tcs_data[second_pos + 1]; - tcs_data[second_pos] = tcs_data[first_pos]; - tcs_data[second_pos + 1] = tcs_data[first_pos + 1]; - tcs_data[first_pos] = address_stored; - tcs_data[first_pos + 1] = value_stored; -} - -/** - * \brief Sort the registers of a specific Memory Map area of the chip to a continuous region in the - * TCS array. - * - * \param [in] area_base the base address of the Memory Map area - * \param [in] area_size the size of the Memory Map region in bytes - * \param [in] array_ptr the current position in the TCS array to start reading from (all previous - * positions have been sorted) - * \param [out] ptr the offset of the beginning of the sorted region in the TCS array - * \param [out] size the size of the sorted region in bytes - * - * \return The updated position in the TCS array to start reading next time - */ -static int sys_tcs_sort_area(uint32_t area_base, uint32_t area_size, uint32_t array_ptr, uint8_t *ptr, uint8_t *size) -{ - uint32_t i = array_ptr; - uint32_t sort_start; - uint32_t sort_end; - - if (array_ptr == tcs_length) { - return array_ptr; // Nothing else is left in the array or tcs_length is zero - } - - sort_start = array_ptr; - sort_end = array_ptr; - - /* Make sure that the values in TCS don't overflow the allocated array */ - ASSERT_WARNING(tcs_length <= sizeof(tcs_data)/sizeof(tcs_data[0])); - - while (i < (tcs_length - 1)) { - if (IS_IN_AREA(tcs_data[i], area_base, area_size)) { - if (i == array_ptr) { - if (sort_start == array_ptr) { - sort_start = array_ptr; - sort_end = sort_start + 2; - } - } - else { - // Copy it to the proper place. - if (i != sort_end) { - swap_entries(sort_end, i); - } - sort_end += 2; - } - } - i += 2; - } - - *ptr = sort_start; - *size = sort_end - sort_start; - - return sort_end; -} - -void sys_tcs_init(void) -{ - tcs_length = 0; - sys_tcs_is_calibrated_chip = false; - hw_cpm_bod_enabled_in_tcs = 0; -} - -bool sys_tcs_store_pair(uint32_t address, uint32_t value) -{ - // If it stops here then tcs_length must become uint16_t. - ASSERT_WARNING( (256 * sizeof(tcs_length)) >= (24 * 2 + APPEND_TCS_LENGTH) ); - - // Check if the address is in Always-ON or of a retained register and apply it. - if (IS_IN_AREA(address, CRG_TOP_BASE, sizeof(CRG_TOP_Type)) - || IS_IN_AREA(address, TIMER1_BASE, sizeof(TIMER1_Type)) - || IS_IN_AREA(address, WAKEUP_BASE, sizeof(WAKEUP_Type)) - || IS_IN_AREA(address, DCDC_BASE, sizeof(DCDC_Type)) - || IS_IN_AREA(address, QSPIC_BASE, sizeof(QSPIC_Type)) - || IS_IN_AREA(address, CACHE_BASE, sizeof(CACHE_Type)) - || IS_IN_AREA(address, OTPC_BASE, sizeof(OTPC_Type))) { - if (address == (uint32_t)&CRG_TOP->BANDGAP_REG) { - sys_tcs_is_calibrated_chip = true; - } else if (address == (uint32_t)&CRG_TOP->CLK_16M_REG) { - value |= CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk; // Make sure that RC16 is enabled! - } else if (address == (uint32_t)&CRG_TOP->XTALRDY_CTRL_REG) { - sys_tcs_xtal16m_settling_time = value; - } else if (address == (uint32_t)&CRG_TOP->BOD_CTRL2_REG) { - hw_cpm_bod_enabled_in_tcs = value; - /* - * Read the ADC Gain Error. Given that the Chip Configuration Section - * (CCS) of OTP is out of space, the values are stored in the TCS section - * using as address the read-only register SYS_STAT_REG. - * The 16 LSB of the 32bit data-value is the single ended gain error. - * The 16 MSB of the 32bit data-value is the differential gain error. - * Both gain error values should be interpreted as signed 16bit integers. - */ - } else if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) { - if (address == (uint32_t)&CRG_TOP->SYS_STAT_REG) { - hw_gpadc_store_se_gain_error(ADC_SE_GAIN_ERROR(value)); - hw_gpadc_store_diff_gain_error(ADC_DIFF_GAIN_ERROR(value)); - } - } - apply_pair(address, value); - } else { - store_in_array(address, value); - } - - return sys_tcs_is_calibrated_chip; -} - -void sys_tcs_sort_array(void) -{ - int entry_ptr = 0; - int i; - - /* - * Apply a default value to CLK_FREQ_TRIM_REG, if not set in TCS. - * [10:8]: COARSE_ADJ = 0x4 - * [7:0]: FINE_ADJ = 0x60 - */ - if (CRG_TOP->CLK_FREQ_TRIM_REG == 0) { - CRG_TOP->CLK_FREQ_TRIM_REG = 0x0460; - } - - if (sys_tcs_is_calibrated_chip) { -#ifdef CONFIG_USE_BLE - entry_ptr = sys_tcs_sort_area(BLE_BASE, sizeof(BLE_Type), entry_ptr, - &area_offset[tcs_ble], &area_size_global[tcs_ble]); -#endif - -#ifdef CONFIG_USE_FTDF - entry_ptr = sys_tcs_sort_area(FTDF_BASE, sizeof(FTDF_Type), entry_ptr, - &area_offset[tcs_ftdf], &area_size_global[tcs_ftdf]); -#endif - - entry_ptr = sys_tcs_sort_area(RFCU_BASE, RADIO_AREA_SIZE, entry_ptr, - &area_offset[tcs_radio], &area_size_global[tcs_radio]); - - entry_ptr = sys_tcs_sort_area((uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 1, entry_ptr, - &area_offset[tcs_charger], &area_size_global[tcs_charger]); - - entry_ptr = sys_tcs_sort_area(APU_BASE, sizeof(APU_Type), entry_ptr, - &area_offset[tcs_audio], &area_size_global[tcs_audio]); - - // The rest should be System. Assert if not! - for (i = entry_ptr; i < tcs_length; i += 2) { - if (IS_IN_AREA(tcs_data[i], UART_BASE, PERIPHERAL_AREA_SIZE)) { - ASSERT_WARNING(0); - } - - if (IS_IN_AREA(tcs_data[i], CRG_TOP_BASE, 0x6100)) { - // It is ok (most probably). - } - else { - ASSERT_WARNING(0); - } - } - area_offset[tcs_system] = entry_ptr; - area_size_global[tcs_system] = tcs_length - entry_ptr; - - tcs_ptr = tcs_data; - } - else { - tcs_ptr = uncalibrated_tcs_data; - - for (i = 0; i < UNCALIBRATED_DATA_NON_RETAINED_OFFSET; i += 2) { - apply_pair(tcs_ptr[i], tcs_ptr[i + 1]); - } - -#ifdef CONFIG_USE_BLE - if (UNCALIBRATED_DATA_BLE_SIZE > 0) { - area_offset[tcs_ble] = UNCALIBRATED_DATA_BLE_OFFSET; - area_size_global[tcs_ble] = UNCALIBRATED_DATA_BLE_SIZE; - } -#endif - -#ifdef CONFIG_USE_FTDF - if (UNCALIBRATED_DATA_FTDF_SIZE > 0) { - area_offset[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_OFFSET; - area_size_global[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_SIZE; - } -#endif - - if (UNCALIBRATED_DATA_RADIO_SIZE > 0) { - area_offset[tcs_radio] = UNCALIBRATED_DATA_RADIO_OFFSET; - area_size_global[tcs_radio] = UNCALIBRATED_DATA_RADIO_SIZE; - } - - if (UNCALIBRATED_DATA_CHARGER_SIZE > 0) { - area_offset[tcs_charger] = UNCALIBRATED_DATA_CHARGER_OFFSET; - area_size_global[tcs_charger] = UNCALIBRATED_DATA_CHARGER_SIZE; - } - - if (UNCALIBRATED_DATA_AUDIO_SIZE > 0) { - area_offset[tcs_audio] = UNCALIBRATED_DATA_AUDIO_OFFSET; - area_size_global[tcs_audio] = UNCALIBRATED_DATA_AUDIO_SIZE; - } - - if (UNCALIBRATED_DATA_SYSTEM_SIZE > 0) { - area_offset[tcs_system] = UNCALIBRATED_DATA_SYSTEM_OFFSET; - area_size_global[tcs_system] = UNCALIBRATED_DATA_SYSTEM_SIZE; - } - } -} - -void sys_tcs_apply(sys_tcs_area_t area) -{ - int i; - - for (i = area_offset[area]; i < (area_offset[area] + area_size_global[area]); i += 2) { - apply_entry(i); - } -} - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/startup/config.c b/third_party/dialog/DialogSDK/bsp/startup/config.c deleted file mode 100755 index 4a2b82304..000000000 --- a/third_party/dialog/DialogSDK/bsp/startup/config.c +++ /dev/null @@ -1,143 +0,0 @@ -/** - **************************************************************************************** - * - * @file config.c - * - * @brief Configure system. - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -/** -\addtogroup BSP -\{ -\addtogroup SYSTEM -\{ -\addtogroup Start-up -\{ -*/ - -#include -#include -#include "sdk_defs.h" -#include "interrupts.h" - -/* - * Dialog default priority configuration table. - * - * Content of this table will be applied at system start. - * - * \note If interrupt priorities provided by Dialog need to be changed, do not modify this file. - * Create similar table with SAME name instead somewhere inside code without week attribute, - * and it will be used instead of table below. - */ -#pragma weak __dialog_interrupt_priorities -INTERRUPT_PRIORITY_CONFIG_START(__dialog_interrupt_priorities) - PRIORITY_0, /* Start interrupts with priority 0 (highest) */ - SVCall_IRQn, - PendSV_IRQn, - XTAL16RDY_IRQn, - PRIORITY_1, /* Start interrupts with priority 1 */ - BLE_WAKEUP_LP_IRQn, - BLE_GEN_IRQn, - FTDF_WAKEUP_IRQn, - FTDF_GEN_IRQn, - RFCAL_IRQn, - COEX_IRQn, - CRYPTO_IRQn, - RF_DIAG_IRQn, - PRIORITY_2, /* Start interrupts with priority 2 */ - DMA_IRQn, - I2C_IRQn, - I2C2_IRQn, - SPI_IRQn, - SPI2_IRQn, - ADC_IRQn, - SRC_IN_IRQn, - SRC_OUT_IRQn, - TRNG_IRQn, - LAST_IRQn, - PRIORITY_3, /* Start interrupts with priority 3 (lowest) */ - SysTick_IRQn, - UART_IRQn, - UART2_IRQn, - MRM_IRQn, - KEYBRD_IRQn, - IRGEN_IRQn, - WKUP_GPIO_IRQn, - SWTIM0_IRQn, - SWTIM1_IRQn, - QUADEC_IRQn, - USB_IRQn, - PCM_IRQn, - VBUS_IRQn, - DCDC_IRQn, -INTERRUPT_PRIORITY_CONFIG_END - -void set_interrupt_priorities(const int8_t prios[]) -{ - uint32_t old_primask, iser; - int i = 0; - uint32_t prio = 0; - - /* - * We shouldn't change the priority of an enabled interrupt. - * 1. Globally disable interrupts, saving the global interrupts disable state. - * 2. Explicitly disable all interrupts, saving the individual interrupt enable state. - * 3. Set interrupt priorities. - * 4. Restore individual interrupt enables. - * 5. Restore global interrupt enable state. - */ - old_primask = __get_PRIMASK(); - __disable_irq(); - iser = NVIC->ISER[0]; - NVIC->ICER[0] = iser; - - for (i = 0; prios[i] != PRIORITY_TABLE_END; ++i) { - switch (prios[i]) { - case PRIORITY_0: - case PRIORITY_1: - case PRIORITY_2: - case PRIORITY_3: - prio = prios[i] - PRIORITY_0; - break; - default: - NVIC_SetPriority(prios[i], prio); - break; - } - } - - NVIC->ISER[0] = iser; - __set_PRIMASK(old_primask); -} - -/** -\} -\} -\} -*/ diff --git a/third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S b/third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S deleted file mode 100755 index 776754021..000000000 --- a/third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S +++ /dev/null @@ -1,367 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V2.0 - * Date: 16 August 2013 - */ - -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - .syntax unified - .arch armv6-m - .section text_reset - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -#if (dg_configSKIP_MAGIC_CHECK_AT_START == 0) -/* If the Magic Word {0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEAD10CC} is found at 0x7fd0000 then the - * execution will block for a while in order to give time to a debugger to attach. */ - ldr r4, =0x7fd0000 - ldmia r4!, {r0-r3} - ldr r4, =0xDEADBEEF - cmp r0, r4 - bne .code_starts - cmp r1, r4 - bne .code_starts - cmp r2, r4 - bne .code_starts - ldr r4, =0xDEAD10CC - cmp r3, r4 - bne .code_starts - /* Enable debugger */ - ldr r4, =0x50000012 - ldrh r5, [r4] - mov r6, r5 - movs r1, #128 - orrs r5, r5, r1 - strh r5, [r4] - /* Block for 2'' */ - ldr r0, =0x150000 -.delay_loop: - subs r0, #1 - bgt .delay_loop - /* Make sure that this will happen only once! */ - ldr r4, =0x7fd0000 - movs r0, #0 - str r0, [r4] - /* Restore debugger setting */ - ldr r4, =0x50000012 - strh r6, [r4] - -.code_starts: -#endif - -/* RAM shuffling configuration should be determined from the image in the QSPI Flash or OTP - * and must be applied at the beginning of the Reset Vector. The interrupt vector table must - * be copied to the RAM base after the shuffling is done. - * NOTE: Even though there is an OTP field specifically for the shuffling configuration - * we must bypass it here since the shuffling might change between different - * QSPI FLASH image versions. For OTP images RAM shuffling configuration will never change, - * but we also apply it to ignore the OTP field in any case. */ - ldr r4, =0x50000012 - movs r0, #0 - ldrh r0, [r4] - movs r1, #0x18 - bics r0, r0, r1 - movs r1, #dg_configSHUFFLING_MODE<<3 - orrs r0, r0, r1 - /* Update SYS_CTRL_REG. */ - strh r0, [r4] - - /* Copy ISR VT from from QSPI Flash/OTP to RAM. This must be done - * after applying shuffling mode. */ -# if (dg_configIMAGE_FLASH_OFFSET == 0) - ldr r1, =0x8000008 -# else - ldr r1, =(0x8000000 + dg_configIMAGE_FLASH_OFFSET) -# endif - ldr r2, =0x7FC0000 - ldr r3, =0x7FC00C0 - /* Block should be a multiple of 16 to traverse correctly L_loopIV */ - subs r3, r2 - ble .L_loopIV_done - -.L_loopIV: - ldmia r1!, {r4-r7} - stmia r2!, {r4-r7} - subs r3, #16 - bgt .L_loopIV - -.L_loopIV_done: - - bl SystemInitPre - bl SystemInit - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ -#define __STARTUP_COPY_MULTIPLE - -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r0, =__copy_table_end__ - -.L_loop0: - cmp r4, r0 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - push {r4} - -.L_loop0_0: - subs r3, #16 - blt .L_loop0_0_done - ldmia r1!, {r4-r7} - stmia r2!, {r4-r7} - b .L_loop0_0 - -.L_loop0_0_done: - pop {r4} - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#define __STARTUP_CLEAR_BSS_MULTIPLE - -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r0, =__zero_table_end__ - movs r4, 0 - movs r5, r4 - mov r6, r4 - mov r7, r4 - -.L_loop2: - cmp r3, r0 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - -.L_loop2_0: - subs r2, #32 // Requires 32-byte alignment! - blt .L_loop2_0_done - stmia r1!, {r4-r7} - stmia r1!, {r4-r7} - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - /* Copy the address of the retained NMI and HardFault handlers to the vector table. */ - ldr r0, =0x7FC0008 - ldr r1, =NMI_Handler - str r1, [r0, #0] - ldr r1, =HardFault_Handler - str r1, [r0, #4] - - bl SystemInitPost - - bl main - - .pool - .size Reset_Handler, . - Reset_Handler - - .text - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* - * enable debugger: - * CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 1; - */ - movs r1, #0x50 - lsls r1, #24 - ldrh r2, [r1, #0x12] - movs r3, #0x80 - orrs r2, r2, r3 - strh r2, [r1, #0x12] - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - .thumb - .thumb_func - .align 1 - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - def_irq_handler BLE_WAKEUP_LP_Handler - def_irq_handler BLE_GEN_Handler - def_irq_handler FTDF_WAKEUP_Handler - def_irq_handler FTDF_GEN_Handler - def_irq_handler RFCAL_Handler - def_irq_handler COEX_Handler - def_irq_handler CRYPTO_Handler - def_irq_handler MRM_Handler - def_irq_handler UART_Handler - def_irq_handler UART2_Handler - def_irq_handler I2C_Handler - def_irq_handler I2C2_Handler - def_irq_handler SPI_Handler - def_irq_handler SPI2_Handler - def_irq_handler ADC_Handler - def_irq_handler KEYBRD_Handler - def_irq_handler IRGEN_Handler - def_irq_handler WKUP_GPIO_Handler - def_irq_handler SWTIM0_Handler - def_irq_handler SWTIM1_Handler - def_irq_handler QUADEC_Handler - def_irq_handler USB_Handler - def_irq_handler PCM_Handler - def_irq_handler SRC_IN_Handler - def_irq_handler SRC_OUT_Handler - def_irq_handler VBUS_Handler - def_irq_handler DMA_Handler - def_irq_handler RF_DIAG_Handler - def_irq_handler TRNG_Handler - def_irq_handler DCDC_Handler - def_irq_handler XTAL16RDY_Handler - def_irq_handler RESERVED31_Handler - - .section text_retained - .align 1 - .thumb - .thumb_func - .globl NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r1, =NMI_HandlerC - movs r0, #4 - mov r2, lr - tst r0, r2 - beq NMI_stacking_using_MSP - mrs r0, psp - b stack_check -NMI_stacking_using_MSP: - mrs r0, msp - b stack_check - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb - .thumb_func - .globl HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r1, =HardFault_HandlerC - movs r0, #4 - mov r2, lr - tst r0, r2 - beq HF_stacking_using_MSP - mrs r0, psp - b stack_check -HF_stacking_using_MSP: - mrs r0, msp -stack_check: - /* 0x7FC0000 is start of RAM */ - ldr r2, =0x7FC0000 - cmp r0, r2 - blt Wrong_SP - /* Check SYS_CTRL_REG:CACHERAM_MUX */ - ldr r2, =0x50000012 - ldrh r2, [r2] - movs r3, #1 - lsls r3, r3, #10 - ands r2, r2, r3 - bne cache_is_on - /* 0x7FE4000 marks end of RAM (assuming that the CACHE is used as RAM) */ - ldr r2, =0x7FE4000-32 - b check_end_of_ram -cache_is_on: - /* 0x7FE0000 marks end of RAM */ - ldr r2, =0x7FE0000-32 -check_end_of_ram: - cmp r0, r2 - bgt Wrong_SP - bx r1 -Wrong_SP: - /* Freeze WDog at all times */ - ldr r0, =0x50003300 - ldr r1, =8 - strh r1, [r0, #0] - /* Enable debugger at all times */ - ldr r4, =0x50000012 - ldrh r0, [r4, #0] - movs r1, #0x80 - orrs r0, r0, r1 - /* Update SYS_CTRL_REG */ - strh r0, [r4, #0] - - /* Wait for the WDog to hit or a debug session to start */ - b . - .size HardFault_Handler, . - HardFault_Handler - - .end - diff --git a/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c b/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c deleted file mode 100755 index 2e7339544..000000000 --- a/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c +++ /dev/null @@ -1,571 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM0.c - * @brief CMSIS Device System Source File for - * ARMCM0 Device Series - * @version V2.00 - * @date 18. August 2015 - ******************************************************************************/ -/* Copyright (c) 2011 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#include -#include -#include -#include -#include "sdk_defs.h" -#include "interrupts.h" -#include "hw_cpm.h" -#include "hw_otpc.h" -#include "hw_qspi.h" -#include "hw_watchdog.h" -#include "sys_tcs.h" -#include "qspi_automode.h" - -/* - * This is just so that compilation doesn't break for RAM builds. - * The code that uses it is optimized out in RAM builds. - */ -extern uint32_t NVMS_PARAM_PART_end; - -/* - * TCS Offsets - */ -#define OTP_HEADER_BASE_ADDR_IN_OTP (0x7F8E9C0) - -#define TCS_SECTION_OFFSET (184) /* 0x7F8EA78 - 0x7F8E9C0 */ -#define TCS_SECTION_LENGTH (24) /* 24 entries, 16 bytes each for OTP */ - -#ifndef __SYSTEM_CLOCK -# define __SYSTEM_CLOCK (16000000UL) /* 16 MHz */ -#endif - -#if (dg_configUSE_LP_CLK == LP_CLK_32000) -# define LP_CLK_FREQ (32000) - -#elif (dg_configUSE_LP_CLK == LP_CLK_32768) -# define LP_CLK_FREQ (32768) - -#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) -# define LP_CLK_FREQ (0) - -#else -# error "dg_configUSE_LP_CLK is not defined or has an unknown value!" -#endif - -/* - * Linker symbols - * - * Note: if any of them is missing, please correct your linker script. Please refer to the linker - * script of pxp_reporter. - */ -extern uint32_t __copy_table_start__; -extern uint32_t __copy_table_end__; -extern uint32_t __zero_table_start__; -extern uint32_t __zero_table_end__; -extern uint8_t end; -extern uint8_t __HeapLimit; - -/* - * Global variables - */ -__RETAINED_RW static uint8_t *heapend = &end; -__RETAINED_UNINIT __attribute__((unused)) uint32_t black_orca_chip_version; -uint32_t SystemCoreClock __RETAINED = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemLPClock __RETAINED = LP_CLK_FREQ; /*!< System Low Power Clock Frequency (LP Clock)*/ - -/** - * @brief Memory safe implementation of newlib's _sbrk(). - * - */ -__LTO_EXT -void *_sbrk(int incr) -{ - uint8_t *newheapstart; - - if (heapend + incr > &__HeapLimit) { - /* Hitting this, means that the value of _HEAP_SIZE is too small. - * The value of incr is in stored_incr at this point. By checking the equation - * above, it is straightforward to determine the missing space. - */ - volatile int stored_incr __attribute__((unused)); - - stored_incr = incr; - ASSERT_ERROR(0); - - errno = ENOMEM; - return (void *)-1; - } - - newheapstart = heapend; - heapend += incr; - - return newheapstart; -} - -/** - * Apply trim values from OTP. - * - * @brief Writes the trim values located in the OTP to the corresponding system registers. - * - * @param[out] tcs_array The valid pairs are placed in this buffer. - * @param[out] valid_entries The number of valid pairs. - * - * @return True if at least one trim value has been applied, else false. - * - */ -static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entries) -{ - uint32_t address; - uint32_t inverted_address; - uint32_t value; - uint32_t inverted_value; - uint32_t *p; - int i; - int index = 0; - int vdd = 0; - int retries = 0; - bool forward_reading = true; - bool res = false; - - p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET); - - for (i = 0; i < TCS_SECTION_LENGTH; i++) { - do { - address = *p; - p++; - inverted_address = *p; - p++; - value = *p; - p++; - inverted_value = *p; - p++; - - if ((address == 0) && (value == 0)) { - break; - } - - // Check validity - if ((address != ~inverted_address) || (value != ~inverted_value)) { - // Change LDO core voltage level and retry - vdd++; - vdd &= 0x3; - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, vdd); - - // Wait for the voltage to settle... - SysTick->CTRL = 0; - SysTick->LOAD = 500; // 500 * (62.5 * 4) = 125usec - SysTick->VAL = 0; - SysTick->CTRL = 0x5; // Start using system clock - while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {} - - // Adjust the read pointer - p -= 4; - } - - retries++; - if (retries == 32) { - // Unrecoverable problem! Assert in development mode - ASSERT_WARNING(0); - - // Unrecoverable problem! Issue a HW reset. - hw_cpm_reset_system(); - } - } while ((address != ~inverted_address) || (value != ~inverted_value)); - - retries = 0; - - // Read the complete TCS area but skip empty entries. - if ((address == 0) && (value == 0)) { - if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E)) - || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) - && (CHIP_IS_AE || CHIP_IS_BB))) { - if (!forward_reading) { - break; - } - - forward_reading = false; - p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET); - p += (TCS_SECTION_LENGTH - 1) * 4; - } - else { - (void)forward_reading; - } - - continue; - } - - if (!forward_reading) { - p -= 8; - } - - sys_tcs_store_pair(address, value); - - tcs_array[(index * 2) + 0] = address; - tcs_array[(index * 2) + 1] = value; - - *valid_entries = index + 1; - index++; - - res = true; - } - - return res; -} - -/** - * Check whether the code has been compiled for a chip version that is compatible with the chip - * it runs on. - */ -static bool is_compatible_chip_version(void) -{ - const uint32_t ver = black_orca_get_chip_version(); - - /* Oldest supported version is AE. */ - if ((ver < BLACK_ORCA_IC_VERSION(A, E)) && (dg_configUSE_AUTO_CHIP_DETECTION == 0)) { - return false; - } - - if ((ver == BLACK_ORCA_TARGET_IC) || (dg_configUSE_AUTO_CHIP_DETECTION == 1)) { - return true; - } - - return false; -} - -#ifdef OS_BAREMETAL - -static volatile bool nortos_xtal16m_settled = false; - -void XTAL16RDY_Handler(void) -{ - nortos_xtal16m_settled = true; -} - -/* carry out clock initialization sequence */ -static void nortos_clk_setup(void) -{ - // Setup DIVN - if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M) { - hw_cpm_set_divn(false); // External crystal is 16MHz - } - else { - hw_cpm_set_divn(true); // External crystal is 32MHz - } - hw_cpm_enable_rc32k(); - hw_cpm_lp_set_rc32k(); - - NVIC_ClearPendingIRQ(XTAL16RDY_IRQn); - nortos_xtal16m_settled = false; - NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ - - hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K); - hw_cpm_enable_xtal16m(); // Enable XTAL16M - hw_watchdog_unfreeze(); // Start watchdog - - while(!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts - - /* Wait for XTAL16M to settle */ - while(!nortos_xtal16m_settled); - - hw_watchdog_freeze(); // Stop watchdog - hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M); -} - -#endif /* OS_BAREMETAL */ - -static __RETAINED_CODE void configure_cache(void) -{ - bool flush = false; - - GLOBAL_INT_DISABLE(); - - if (dg_configCACHEABLE_QSPI_AREA_LEN != -1) { - uint32_t cache_len; - - /* dg_configCACHEABLE_QSPI_AREA_LEN must be 64KB-aligned */ - ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0xFFFF) == 0); - /* - * dg_configCACHEABLE_QSPI_AREA_LEN shouldn't set any bits that do not fit in - * CACHE_CTRL2_REG.CACHE_LEN (9 bits wide) after shifting out the lower 16 bits - */ - ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0x1FF0000) - == dg_configCACHEABLE_QSPI_AREA_LEN); - /* - * set cacheable area - * - * setting CACHE_CTRL2_REG.CACHE_LEN to N, actually sets the size of the cacheable - * area to (N + 1) * 64KB - * special cases: - * N == 0 --> no caching - * N == 1 --> 128KB are cached, i.e. no way to cache only 64KB - */ - cache_len = dg_configCACHEABLE_QSPI_AREA_LEN >> 16; - /* cannot cache only 64KB! */ - ASSERT_WARNING(cache_len != 1); - if (cache_len > 1) { - cache_len--; - } - REG_SETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN, cache_len); - } - - if (dg_configCACHE_ASSOCIATIVITY != CACHE_ASSOC_AS_IS) { - if (CACHE->CACHE_ASSOCCFG_REG != dg_configCACHE_ASSOCIATIVITY) { - /* override the set associativity setting */ - CACHE->CACHE_ASSOCCFG_REG = dg_configCACHE_ASSOCIATIVITY; - flush = true; - } - } - - if (dg_configCACHE_LINESZ != CACHE_LINESZ_AS_IS) { - if (CACHE->CACHE_LNSIZECFG_REG != dg_configCACHE_LINESZ) { - /* override the cache line setting */ - CACHE->CACHE_LNSIZECFG_REG = dg_configCACHE_LINESZ; - flush = true; - } - } - - if (flush && (REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN) > 0)) { - /* flush cache */ - REG_SET_BIT(CACHE, CACHE_CTRL1_REG, CACHE_FLUSH); - } - - GLOBAL_INT_RESTORE(); -} - -/** - * Basic system setup - * - * @brief Setup the AMBA clocks. Ensure proper alignment of copy and zero table entries. - */ -void SystemInitPre(void) __attribute__((section("text_reset"))); - -void SystemInitPre(void) -{ - /* - * Enable debugger. - */ - if (dg_configENABLE_DEBUGGER) { - ENABLE_DEBUGGER; - } - - /* - * Bandgap has already been set by the bootloader. - * Use fast clocks from now on. - */ - hw_cpm_set_hclk_div(0); - hw_cpm_set_pclk_div(0); - - /* - * Ensure 16-byte alignment for all elements of each entry in the Copy Table. This is - * a requirement imposed by the fast start-up code! If any of the assertions below hits, - * please correct your linker script file accordingly! - */ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { - uint32_t *p; - - for (p = &__copy_table_start__; p < &__copy_table_end__; p += 3) { - ASSERT_WARNING_UNINIT( (p[0] & 0xF) == 0 ); // from - ASSERT_WARNING_UNINIT( (p[1] & 0xF) == 0 ); // to - ASSERT_WARNING_UNINIT( (p[2] & 0xF) == 0 ); // size - } - } - - /* - * Ensure 32-byte alignment for all elements of each entry in the Data Table. This is - * a requirement imposed by the fast start-up code! If any of the assertions below hits, - * please correct your linker script file accordingly! - */ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { - uint32_t *p; - - for (p = &__zero_table_start__; p < &__zero_table_end__; p += 2) { - ASSERT_WARNING_UNINIT( (p[0] & 0x1F) == 0 ); // start at - ASSERT_WARNING_UNINIT( (p[1] & 0x1F) == 0 ); // size - } - } -} - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ - /* - * Make sure we are running on a chip version that the code has been built for. - */ - ASSERT_WARNING_UNINIT(is_compatible_chip_version()); - - /* - * Detect chip version (optionally). - */ - if (dg_configUSE_AUTO_CHIP_DETECTION == 1) { - black_orca_chip_version = black_orca_get_chip_version(); - - if (!CHIP_IS_AE && !CHIP_IS_BB) { - // Oldest supported version is AE. - ASSERT_WARNING_UNINIT(0); - } - } - - /* - * Initialize UNINIT variables. - */ - sys_tcs_init(); - - /* - * BOD protection - */ - if (dg_configUSE_BOD == 1) { - /* BOD has already been enabled at this point but it must be reconfigured */ - hw_cpm_configure_bod_protection(); - } else { - hw_cpm_deactivate_bod_protection(); - } - - /* - * Apply default priorities to interrupts. - */ - set_interrupt_priorities(__dialog_interrupt_priorities); - - /* - * If we are executing from RAM, make sure that code written in Flash won't have left the - * system in "unknown" state. - */ - if (dg_configCODE_LOCATION == NON_VOLATILE_IS_NONE) { - GLOBAL_INT_DISABLE(); - CRG_TOP->PMU_CTRL_REG |= 0xE; - CRG_TOP->PMU_CTRL_REG &= ~1; - GLOBAL_INT_RESTORE(); - } - - /* - * Switch to RC16. - */ - hw_cpm_set_sysclk(SYS_CLK_IS_RC16); // Use RC16 - hw_cpm_disable_xtal16m(); // Disable XTAL16M - - /* - * Set highest access speed for QSPI Flash. - */ - if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) { - hw_qspi_set_div(HW_QSPI_DIV_1); - } -} - -/** - * Process the TCS - * - * @brief Process the TCS section. - */ -void SystemInitPost(void) -{ - SystemCoreClock = __SYSTEM_CLOCK; - SystemLPClock = LP_CLK_FREQ; - - uint32_t tcs_pairs[TCS_SECTION_LENGTH * 2]; - uint32_t valid_tcs_pairs = 0; - - hw_cpm_start_ldos(); // Make sure all LDOs are as expected - hw_cpm_reset_radio_vdd(); // Set Radio voltage to 1.40V - - /* - * Initialize Flash - */ - if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) { - qspi_automode_init(); // The bootloader may have left the Flash in wrong mode... - } - - /* - * Retrieve trim values from OTP. - */ - hw_otpc_init(); // Start clock. - hw_otpc_disable(); // Make sure it is in standby mode. - hw_otpc_init(); // Restart clock. - hw_otpc_manual_read_on(false); - - /* - * Apply trim values from OTP. - */ - apply_trim_values_from_otp(tcs_pairs, &valid_tcs_pairs); - - if (dg_configIMAGE_SETUP == PRODUCTION_MODE) { - ASSERT_ERROR(sys_tcs_is_calibrated_chip); // Uncalibrated chip!!! - } - - hw_otpc_manual_read_off(); - hw_otpc_disable(); - - if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) { - hw_cpm_enable_qspi_init(); // Enable QSPI init after wakeup - - hw_qspi_set_read_pipe_clock_delay(6); // Set read pipe clock delay to 6 (Last review date: Feb 15, 2016 - 12:25:47) - } - - /* - * All trim values have been loaded from TCS or defaults are used. - */ - sys_tcs_sort_array(); - sys_tcs_apply(tcs_system); - hw_cpm_set_preferred_values(); - -#ifdef OS_BAREMETAL - /* perform clock initialization here, as there is no CPM to do it later for us */ - nortos_clk_setup(); -#endif - - configure_cache(); -} - -uint32_t DA15000_phy_addr(uint32_t addr) -{ - static const uint32 remap[] = { - MEMORY_ROM_BASE, - MEMORY_OTP_BASE, - MEMORY_QSPIF_BASE, - MEMORY_SYSRAM_BASE, - MEMORY_QSPIF_BASE, - MEMORY_OTP_BASE, - MEMORY_CACHERAM_BASE, - 0 - }; - - if (addr >= MEMORY_REMAPPED_END) - return addr; - - return addr + remap[REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0)]; -} - -__extension__ typedef int __guard __attribute__((mode(__DI__))); -int __cxa_guard_acquire(__guard *g) { return !*(char *)(g); } -void __cxa_guard_release(__guard *g) { *(char *)g = 1; } -void __cxa_guard_abort(__guard *g) { (void)g; } -void __cxa_pure_virtual(void) { while (1); } - diff --git a/third_party/dialog/DialogSDK/bsp/startup/vector_table.S b/third_party/dialog/DialogSDK/bsp/startup/vector_table.S deleted file mode 100755 index 2700c1777..000000000 --- a/third_party/dialog/DialogSDK/bsp/startup/vector_table.S +++ /dev/null @@ -1,178 +0,0 @@ -/** - **************************************************************************************** - * - * @file vector_table.S - * - * @brief Interrupt Vector Table and Patch Table - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 - .equ Stack_Size, __STACK_SIZE - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 - .equ Heap_Size, __HEAP_SIZE - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long Default_Handler /* replaced by NMI_Handler after the ISR is copied to retRAM*/ - .long Default_Handler /* replaced by HardFault_Handler after the ISR is copied to retRAM */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long BLE_WAKEUP_LP_Handler /* 0 */ - .long BLE_GEN_Handler /* 1 */ - .long FTDF_WAKEUP_Handler /* 2 */ - .long FTDF_GEN_Handler /* 3 */ - .long RFCAL_Handler /* 4 */ - .long COEX_Handler /* 5 */ - .long CRYPTO_Handler /* 6 */ - .long MRM_Handler /* 7 */ - .long UART_Handler /* 8 */ - .long UART2_Handler /* 9 */ - .long I2C_Handler /* 10 */ - .long I2C2_Handler /* 11 */ - .long SPI_Handler /* 12 */ - .long SPI2_Handler /* 13 */ - .long ADC_Handler /* 14 */ - .long KEYBRD_Handler /* 15 */ - .long IRGEN_Handler /* 16 */ - .long WKUP_GPIO_Handler /* 17 */ - .long SWTIM0_Handler /* 18 */ - .long SWTIM1_Handler /* 19 */ - .long QUADEC_Handler /* 20 */ - .long USB_Handler /* 21 */ - .long PCM_Handler /* 22 */ - .long SRC_IN_Handler /* 23 */ - .long SRC_OUT_Handler /* 24 */ - .long VBUS_Handler /* 25 */ - .long DMA_Handler /* 26 */ - .long RF_DIAG_Handler /* 27 */ - .long TRNG_Handler /* 28 */ - .long DCDC_Handler /* 29 */ - .long XTAL16RDY_Handler /* 30 */ - .long RESERVED31_Handler /* 31 */ - - .size __isr_vector, . - __isr_vector - - /* - * Patch Table - * Notice: it crosses the 0x100 boundary - * in cached mode, the first entries will be copied to - * (and accessed from) RAM and others will only lie on - * QSPI flash or OTP. - * - * In C declare: extern uint32_t __patch_table_start[]; - */ - .section .patch_table, "a" - .align 4 - .globl __patch_table_start -__patch_table_start: - /* - * 28 32-bit entries, initialized to "pointer to Default_Patch_Code" - * - * NOTE: we assume that SYS_CTRL_REG.REMAP_INTVECT == 1 - */ - .long Default_Patch_Code_Handler /* 0, in RAM */ - .long Default_Patch_Code_Handler /* 1, in RAM */ - .long Default_Patch_Code_Handler /* 2, in RAM */ - .long Default_Patch_Code_Handler /* 3, in RAM */ - .long Default_Patch_Code_Handler /* 4, in RAM */ - .long Default_Patch_Code_Handler /* 5, in RAM */ - .long Default_Patch_Code_Handler /* 6, in RAM */ - .long Default_Patch_Code_Handler /* 7, in RAM */ - .long Default_Patch_Code_Handler /* 8, in RAM */ - .long Default_Patch_Code_Handler /* 9, in RAM */ - .long Default_Patch_Code_Handler /* 10, in RAM */ - .long Default_Patch_Code_Handler /* 11, in RAM */ - /* - * Chip version: AD - * Entries 12, 13, 14 and 15 are unusable and skipped in the QSPI image, - * to account for the overhead of the QSPI header (16 bytes). - * - * Chip version: AA, AC, AE - * Entries 14 and 15 are unusable and skipped in the QSPI image, - * to account for the overhead of the QSPI header (8 bytes). - * - * The mkimage tool is responsible for stripping the proper entries from the QSPI image. - */ - .long Default_Patch_Code_Handler /* 12 */ - .long Default_Patch_Code_Handler /* 13 */ - .long 0xDEADBEEF /* 14 */ - .long 0xDEADBEEF /* 15 */ - .size __patch_table_start, . - __patch_table_start - -__patch_table_end: - - .section .default_patch_code_handler_section, "a" - .globl Default_Patch_Code_Handler - .align 1 - .thumb - .thumb_func - .type Default_Patch_Code_Handler, %function -Default_Patch_Code_Handler: - bkpt #0 - bkpt #0 - diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h deleted file mode 100644 index 26a3858b7..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - \addtogroup INTERFACES - \{ - \addtogroup FTDF - \{ - */ - -/** - **************************************************************************************** - * - * @file ad_ftdf_config.h - * - * @brief FTDF Adapter API - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef AD_FTDF_CONFIG_H -#define AD_FTDF_CONFIG_H - -#ifndef FTDF_PHY_API -#include "queue.h" -#endif - -#include "ftdf.h" - - -/** - * \brief Sleep When Idle - * - * If set, the block will sleep when Idle - * - */ -#define AD_FTDF_SLEEP_WHEN_IDLE 1 - -/** - * \brief Idle Timeout - * - * Idle Timeout, in OS scheduler ticks, after which, if still Idle, FTDF will - * be put to sleep. Only applicable if AD_FTDF_SLEEP_WHEN_IDLE 1 - * - */ -#define AD_FTDF_IDLE_TIMEOUT 1 - -/** - * \brief UP Queue size - * - * Defines the UP (UMAC to client app) Queue length, in number of messages - * - */ -#define AD_FTDF_UP_QUEUE_LENGTH 16 - -/** - * \brief DOWN Queue size - * - * Defines the DOWN (client app to UMAC) Queue length, in number of messages - * - */ -#define AD_FTDF_DOWN_QUEUE_LENGTH 16 - -/** - * \brief Low Power Clock cycle - * - * Defines the Low Power clock cycle in pico secs. Used for computation needed - * for sleeping / waking up FTDF - * - */ -#define AD_FTDF_LP_CLOCK_CYCLE 30517578 - -/** - * \brief Wake Up Latency - * - * Defines the Wake Up Latency expressed in Low Power clock cycles, that is - * the number of LP clock cycles needed for the FTDF to be fully operational - * (calculations and FTDF timer synchronization) - * - */ -#define AD_FTDF_WUP_LATENCY 10 - -/** - * \brief Sleep value compensation - * - * Defines the sleep value compensation expressed in microseconds. This value - * is subtracted from the sleep time returned by ftdf_can_sleep() - */ -#define AD_FTDF_SLEEP_COMPENSATION 1500 - -#endif /* AD_FTDF_CONFIG_H */ -/** - \} - \} - \} - */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h deleted file mode 100644 index 4b878cf8c..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - \addtogroup INTERFACES - \{ - \addtogroup FTDF - \{ - */ - -/** - **************************************************************************************** - * - * @file ad_ftdf_phy_api.h - * - * @brief FTDF PHY Adapter API - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef AD_FTDF_PHY_API_H -#define AD_FTDF_PHY_API_H - -#include "ftdf.h" -#include "ad_ftdf_config.h" - -/** - * \brief Initialize adapter - create queues - * - */ -void ad_ftdf_init(void); - -/** - * \brief Set Extended Address - * - * Sets interface extended address. This is thread safe. - * - * \param[in] address - The extended address to set - */ -void ad_ftdf_set_ext_address(ftdf_ext_address_t address); - -/** - * \brief Get Extended Address - * - * Gets interface extended address. This is thread safe. - * - * \returns The extended address of the interface - */ -ftdf_ext_address_t ad_ftdf_get_ext_address(void); - -/** - * \brief Transmits a frame - * - * Transmits a frame. Params: - * - * \param[in] frame_length - The total length of the frame passed in bytes - * \param[in] frame - a pointer to the passed frame buffer - * \param[in] channel - The channel to use for transmission in [11, 26] - * \param[in] csma_suppress - If true, csma protocol (i.e. CCA) will not be performed - * \param[in] pti - Packet Traffic Information that will be used for this transaction. - */ -ftdf_status_t ad_ftdf_send_frame_simple(ftdf_data_length_t frame_length, - ftdf_octet_t* frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t csma_suppress); - -/** - * \brief Instructs the MAC and PHY to go to sleep - * - * \param[in] allow_deferred_sleep - If true, then if the MAC cannot go to sleep immediately - * (e.g. a transmission is pending), the MAC will go to sleep - * as soon as possible. If false, and the MAC cannot go to sleep - * immediately, sleep will be aborted. - */ -void ad_ftdf_sleep_when_possible(ftdf_boolean_t allow_deferred_sleep); - -/** - * \brief Instructs the MAC and PHY to wakeup, if sleeping - * - */ -void ad_ftdf_wake_up(void); - -#if FTDF_DBG_BUS_ENABLE -/** - * \brief Configures GPIO pins for the FTDF debug bus - * - * if FTDF_DBG_BUS_USE_PORT_4 == 0, the FTDF debug bus uses the following (fixed) GPIO pins, - * - * bit 0: HW_GPIO_PORT_1, HW_GPIO_PIN_4 - * bit 1: HW_GPIO_PORT_1, HW_GPIO_PIN_5 - * bit 2: HW_GPIO_PORT_1, HW_GPIO_PIN_6 - * bit 3: HW_GPIO_PORT_1, HW_GPIO_PIN_7 - * bit 4: HW_GPIO_PORT_0, HW_GPIO_PIN_6 - * bit 5: HW_GPIO_PORT_0, HW_GPIO_PIN_7 - * bit 6: HW_GPIO_PORT_1, HW_GPIO_PIN_3 - * bit 7: HW_GPIO_PORT_2, HW_GPIO_PIN_3 - * - * if FTDF_DBG_BUS_USE_PORT_4 == 1, the FTDF debug bus uses the following pins: - * - * bit 0: HW_GPIO_PORT_4, HW_GPIO_PIN_0 - * bit 1: HW_GPIO_PORT_4, HW_GPIO_PIN_1 - * bit 2: HW_GPIO_PORT_4, HW_GPIO_PIN_2 - * bit 3: HW_GPIO_PORT_4, HW_GPIO_PIN_3 - * bit 4: HW_GPIO_PORT_4, HW_GPIO_PIN_4 - * bit 5: HW_GPIO_PORT_4, HW_GPIO_PIN_5 - * bit 6: HW_GPIO_PORT_4, HW_GPIO_PIN_6 - * bit 7: HW_GPIO_PORT_4, HW_GPIO_PIN_7 - * - */ -void ad_ftdf_dbg_bus_gpio_config(void); -#endif /* FTDF_DBG_BUS_ENABLE */ - -#endif /* AD_FTDF_PHY_API_H */ - -/** - \} - \} - \} - */ - diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h deleted file mode 100644 index 3b0b157bd..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h +++ /dev/null @@ -1,3413 +0,0 @@ -/** - \addtogroup INTERFACES - \{ - \addtogroup FTDF - \{ - \brief IEEE 802.15.4 Wireless - */ -/** - **************************************************************************************** - * - * @file ftdf.h - * - * @brief FTDF UMAC API header file - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef FTDF_H_ -#define FTDF_H_ - -#include -#ifdef FTDF_PHY_API -#include -#else -#include -#endif - -#define __private1 request -#define __private2 requestASN -#define __private3 requestSN - -#define FTDF_CAPABILITY_IS_FFD 0x02 -#define FTDF_CAPABILITY_AC_POWER 0x04 -#define FTDF_CAPABILITY_RECEIVER_ON_WHEN_IDLE 0x08 -#define FTDF_CAPABILITY_FAST_ASSOCIATION 0x10 -#define FTDF_CAPABILITY_SUPPORTS_SECURITY 0x40 -#define FTDF_CAPABILITY_WANTS_SHORT_ADDRESS 0x80 - -#define FTDF_TRANSPARENT_USE_WAIT_FOR_ACK 1 - -// Transparency options -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_0 0x00000001 -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_1 0x00000002 -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_2 0x00000004 -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_3 0x00000008 -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_4 0x00000010 -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_5 0x00000020 -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_6 0x00000040 -#define FTDF_TRANSPARENT_PASS_FRAME_TYPE_7 0x00000080 -#define FTDF_TRANSPARENT_PASS_ALL_FRAME_TYPES 0x000000ff -#define FTDF_TRANSPARENT_AUTO_ACK 0x00000100 -#define FTDF_TRANSPARENT_AUTO_FP_ACK 0x00000200 -#define FTDF_TRANSPARENT_PASS_CRC_ERROR 0x00000400 -#define FTDF_TRANSPARENT_PASS_ALL_FRAME_VERSION 0x00001000 -#define FTDF_TRANSPARENT_PASS_ALL_PAN_ID 0x00002000 -#define FTDF_TRANSPARENT_PASS_ALL_ADDR 0x00004000 -#define FTDF_TRANSPARENT_PASS_ALL_BEACON 0x00008000 -#define FTDF_TRANSPARENT_PASS_ALL_NO_DEST_ADDR 0x00010000 -#define FTDF_TRANSPARENT_ENABLE_CSMA_CA 0x01000000 -#define FTDF_TRANSPARENT_ENABLE_FCS_GENERATION 0x02000000 -#define FTDF_TRANSPARENT_ENABLE_SECURITY 0x04000000 -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK -#define FTDF_TRANSPARENT_WAIT_FOR_ACK 0x08000000 -#endif - -// Transparent TX statuses -#define FTDF_TRANSPARENT_SEND_SUCCESSFUL 0x00000000 -#define FTDF_TRANSPARENT_CSMACA_FAILURE 0x00000001 -#define FTDF_TRANSPARENT_OVERFLOW 0x00000002 -#if FTDF_TRANSPARENT_WAIT_FOR_ACK -#define FTDF_TRANSPARENT_NO_ACK 0x00000004 -#endif - -// Transparent RX statuses -#define FTDF_TRANSPARENT_RCV_SUCCESSFUL 0x00000000 -#define FTDF_TRANSPARENT_RCV_CRC_ERROR 0x00000001 -#define FTDF_TRANSPARENT_RCV_SECURITY_ERROR 0x00000002 -#define FTDF_TRANSPARENT_RCV_RES_FRAMETYPE 0x00000004 -#define FTDF_TRANSPARENT_RCV_RES_FRAME_VERSION 0x00000008 -#define FTDF_TRANSPARENT_RCV_UNEXP_DST_ADDR 0x00000010 -#define FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID 0x00000020 -#define FTDF_TRANSPARENT_RCV_UNEXP_BEACON 0x00000040 -#define FTDF_TRANSPARENT_RCV_UNEXP_NO_DEST_ADDR 0x00000080 - -typedef uint8_t ftdf_msg_id_t; -#define FTDF_DATA_REQUEST 1 -#define FTDF_DATA_INDICATION 2 -#define FTDF_DATA_CONFIRM 3 -#define FTDF_PURGE_REQUEST 4 -#define FTDF_PURGE_CONFIRM 5 -#define FTDF_ASSOCIATE_REQUEST 6 -#define FTDF_ASSOCIATE_INDICATION 7 -#define FTDF_ASSOCIATE_RESPONSE 8 -#define FTDF_ASSOCIATE_CONFIRM 9 -#define FTDF_DISASSOCIATE_REQUEST 10 -#define FTDF_DISASSOCIATE_INDICATION 11 -#define FTDF_DISASSOCIATE_CONFIRM 12 -#define FTDF_BEACON_NOTIFY_INDICATION 13 -#define FTDF_COMM_STATUS_INDICATION 14 -#define FTDF_GET_REQUEST 15 -#define FTDF_GET_CONFIRM 16 -#define FTDF_SET_REQUEST 17 -#define FTDF_SET_CONFIRM 18 -#define FTDF_GTS_REQUEST 19 -#define FTDF_GTS_CONFIRM 20 -#define FTDF_GTS_INDICATION 21 -#define FTDF_ORPHAN_INDICATION 22 -#define FTDF_ORPHAN_RESPONSE 23 -#define FTDF_RESET_REQUEST 24 -#define FTDF_RESET_CONFIRM 25 -#define FTDF_RX_ENABLE_REQUEST 26 -#define FTDF_RX_ENABLE_CONFIRM 27 -#define FTDF_SCAN_REQUEST 28 -#define FTDF_SCAN_CONFIRM 29 -#define FTDF_START_REQUEST 30 -#define FTDF_START_CONFIRM 31 -#define FTDF_SYNC_REQUEST 32 -#define FTDF_SYNC_LOSS_INDICATION 33 -#define FTDF_POLL_REQUEST 34 -#define FTDF_POLL_CONFIRM 35 -#define FTDF_SET_SLOTFRAME_REQUEST 36 -#define FTDF_SET_SLOTFRAME_CONFIRM 37 -#define FTDF_SET_LINK_REQUEST 38 -#define FTDF_SET_LINK_CONFIRM 39 -#define FTDF_TSCH_MODE_REQUEST 40 -#define FTDF_TSCH_MODE_CONFIRM 41 -#define FTDF_KEEP_ALIVE_REQUEST 42 -#define FTDF_KEEP_ALIVE_CONFIRM 43 -#define FTDF_BEACON_REQUEST 44 -#define FTDF_BEACON_CONFIRM 45 -#define FTDF_BEACON_REQUEST_INDICATION 46 -#define FTDF_TRANSPARENT_CONFIRM 47 -#define FTDF_TRANSPARENT_INDICATION 48 -#define FTDF_TRANSPARENT_REQUEST 49 -#define FTDF_TRANSPARENT_ENABLE_REQUEST 50 -#define FTDF_SLEEP_REQUEST 51 -#define FTDF_EXPLICIT_WAKE_UP 52 -#define FTDF_REMOTE_REQUEST 53 -#if FTDF_DBG_BUS_ENABLE -#define FTDF_DBG_MODE_SET_REQUEST 54 -#endif /* FTDF_DBG_BUS_ENABLE */ -#define FTDF_FPPR_MODE_SET_REQUEST 55 - -/** - * \brief Request status - * \remark Valid statuses: - * - FTDF_SUCCESS: Successful - * - FTDF_CHANNEL_ACCESS_FAILURE: CCA failure - * - FTDF_NO_ACK: No ack received after macMaxFrameRetries - * - FTDF_NO_DATA: No data frames pending - * - FTDF_COUNTER_ERROR: Security frame counter error - * - FTDF_FRAME_TOO_LONG: Too long frame - * - FTDF_IMPROPER_KEY_TYPE: Improper key type - * - FTDF_IMPROPER_SECURITY_LEVEL: Improper security level - * - FTDF_SECURITY_ERROR: Security authentication error - * - FTDF_UNAVAILABLE_KEY: Unavailable key - * - FTDF_UNAVAILABLE_DEVICE: Unavailable device - * - FTDF_UNAVAILABLE_SECURITY_LEVEL: Unavailable security level - * - FTDF_UNSUPPORTED_LEGACY: Unsupported legacy - * - FTDF_UNSUPPORTED_SECURITY: Unsupporteds security - * - FTDF_INVALID_PARAMETER: Invalid parameter - * - FTDF_TRANSACTION_OVERFLOW: Transaction overflow - * - FTDF_TRANSACTION_EXPIRED: Transaction expired - * - FTDF_NO_BEACON: No beacon received - * - FTDF_SCAN_IN_PROGRESS: Scan in progress - * - FTDF_NO_SHORT_ADDRESS: FTDF does not have a short address - * - FTDF_SLOTFRAME_NOT_FOUND: Slotframe not found - * - FTDF_MAX_SLOTFRAMES_EXCEEDED: Max slotframes exceeded - * - FTDF_UNKNOWN_LINK: Unknown link - * - FTDF_MAX_LINKS_EXCEEDED: Max links exceeded - * - FTDF_UNSUPPORTED_ATTRIBUTE: Unsupported PIB attribute - * - FTDF_READ_ONLY: Read onli PIB attribute - * - FTDF_INVALID_HANDLE: Invalid handle - * - FTDF_PAN_AT_CAPACITY: PAN at capacity - * - FTDF_PAN_ACCESS_DENIED: PAN access denied - * - FTDF_HOPPING_SEQUENCE_OFFSET_DUPLICATION: Hopping sequence offset duplication - */ -typedef uint8_t ftdf_status_t; -#define FTDF_SUCCESS 0 -#define FTDF_CHANNEL_ACCESS_FAILURE 1 -#define FTDF_NO_ACK 2 -#define FTDF_NO_DATA 3 -#define FTDF_COUNTER_ERROR 4 -#define FTDF_FRAME_TOO_LONG 5 -#define FTDF_IMPROPER_KEY_TYPE 6 -#define FTDF_IMPROPER_SECURITY_LEVEL 7 -#define FTDF_SECURITY_ERROR 8 -#define FTDF_UNAVAILABLE_KEY 9 -#define FTDF_UNAVAILABLE_DEVICE 10 -#define FTDF_UNAVAILABLE_SECURITY_LEVEL 11 -#define FTDF_UNSUPPORTED_LEGACY 12 -#define FTDF_UNSUPPORTED_SECURITY 13 -#define FTDF_INVALID_PARAMETER 14 -#define FTDF_TRANSACTION_OVERFLOW 15 -#define FTDF_TRANSACTION_EXPIRED 16 -#define FTDF_ON_TIME_TOO_LONG 17 -#define FTDF_LIMIT_REACHED 18 -#define FTDF_NO_BEACON 19 -#define FTDF_SCAN_IN_PROGRESS 20 -#define FTDF_INVALID_INDEX 21 -#define FTDF_NO_SHORT_ADDRESS 22 -#define FTDF_SUPERFRAME_OVERLAP 23 -#define FTDF_TRACKING_OFF 24 -#define FTDF_SLOTFRAME_NOT_FOUND 25 -#define FTDF_MAX_SLOTFRAMES_EXCEEDED 26 -#define FTDF_UNKNOWN_LINK 27 -#define FTDF_MAX_LINKS_EXCEEDED 28 -#define FTDF_UNSUPPORTED_ATTRIBUTE 29 -#define FTDF_READ_ONLY 30 -#define FTDF_INVALID_HANDLE 31 -#define FTDF_PAN_AT_CAPACITY 32 -#define FTDF_PAN_ACCESS_DENIED 33 -#define FTDF_HOPPING_SEQUENCE_OFFSET_DUPLICATION 34 - -/** - * \brief Association status - * \remark Supported statuses: - * - FTDF_ASSOCIATION_SUCCESSFUL: Associate request granted - * - FTDF_ASSOCIATION_PAN_AT_CAPACITY: Asscociate denied, PAN at capacity - * - FTDF_ASSOCIATION_PAN_ACCESS_DENIED: Associate denied - * - FTDF_FAST_ASSOCIATION_SUCCESSFUL: Associate request granted (fast) - */ -typedef uint8_t ftdf_association_status_t; -#define FTDF_ASSOCIATION_SUCCESSFUL 0x00 -#define FTDF_ASSOCIATION_PAN_AT_CAPACITY 0x01 -#define FTDF_ASSOCIATION_PAN_ACCESS_DENIED 0x02 -#define FTDF_ASSOCIATION_HOPPING_SEQUENCE_OFFSET_DUPLICATION 0x03 -#define FTDF_FAST_ASSOCIATION_SUCCESSFUL 0x80 - -/** - * \brief Address mode - * \remark Supported address modes: - * - FTDF_NO_ADDRESS - * - FTDF_SHORT_ADDRESS - * - FTDF_EXTENDED_ADDRESS - */ -typedef uint8_t ftdf_address_mode_t; -#define FTDF_NO_ADDRESS 0 -#define FTDF_SIMPLE_ADDRESS 1 -#define FTDF_SHORT_ADDRESS 2 -#define FTDF_EXTENDED_ADDRESS 3 - -/** - * \brief PAN id - * \remark Range 0.. 65535 - */ -typedef uint16_t ftdf_pan_id_t; - -typedef uint8_t ftdf_simple_address_t; - -/** - * \brief Short address - * \remark Range 00:00 - ff:ff - */ -typedef uint16_t ftdf_short_address_t; - -/** - * \brief Extended address - * \remark Range 00:00:00:00:00:00:00:00 - ff:ff:ff:ff:ff:ff:ff:ff - */ -typedef uint64_t ftdf_ext_address_t; - -typedef union { - /** \brief DO NOT USE */ - ftdf_simple_address_t simple_address; - /** \brief Short address */ - ftdf_short_address_t short_address; - /** \brief Extended address */ - ftdf_ext_address_t ext_address; -} ftdf_address_t; - -#ifdef SIMULATOR -typedef uint16_t ftdf_data_length_t; -#else -typedef uint8_t ftdf_data_length_t; -#endif - -/** - * \brief Handle - * \remark Range 0..255 - */ -typedef uint8_t ftdf_handle_t; - -/** - * \brief Boolean - * \remark Valid values: - * - FTDF_FALSE - * - FTDF_TRUE - */ -typedef uint8_t ftdf_boolean_t; - -/** \brief FTDF boolean FALSE */ -#define FTDF_FALSE 0 -/** \brief FTDF boolean TRUE */ -#define FTDF_TRUE 1 - -/** - * \brief Security level - * \remark Valid range 0..7 - */ -typedef uint8_t ftdf_security_level_t; - -/** - * \brief Security key id mode - * \remark Valid range 0..3 - */ -typedef uint8_t ftdf_key_id_mode_t; - -/** - * \brief Security key index - * \remark Valid range 0..255 - */ -typedef uint8_t ftdf_key_index_t; - -/** - * \brief Sequence number - * \remark Valid range 0..255 - */ -typedef uint8_t ftdf_sn_t; - -/** - * \brief Sequence number - * \remark Valid range 0..0xffffffffff (5 octets) - */ -typedef uint64_t ftdf_asn_t; - -/** - * \brief Order - */ -typedef uint8_t ftdf_order_t; - -/** - * \brief Time - * \remark Timestamp in symbols which wraps around every 0x100000000 symbols - */ -typedef uint32_t ftdf_time_t; - -/** - * \brief Real time - * \remark Timestamp in symbols which does not wrap (in the lifetime of the device) - */ -typedef uint64_t ftdf_time64_t; - -typedef uint32_t ftdf_usec_t; - -typedef uint64_t ftdf_psec_t; - -typedef uint32_t ftdf_nr_low_power_clock_cycles_t; - -typedef uint8_t ftdf_nr_backoff_periods_t; - -/** - * \brief Link Quality mode - * \remark 0: RSSI, 1: LQI - */ -typedef uint8_t ftdf_link_quality_mode_t; -#define FTDF_LINK_QUALITY_MODE_RSSI 0 -#define FTDF_LINK_QUALITY_MODE_LQI 1 - -/** - * \brief Period of time - * \remark Range 0..65535 - */ -typedef uint16_t ftdf_period_t; - -/** - * \brief Size type - */ -typedef uint8_t ftdf_size_t; - -/** - * \brief Length type - */ -typedef uint8_t ftdf_length_t; - -/** - * \brief Priority type - */ -typedef uint8_t ftdf_priority_t; - -/** - * \brief Performance counter - * \remark Range 0..0xffffffff - */ -typedef uint32_t ftdf_count_t; - -/** - * \brief Disassociate reason - * \remark Allowed values: - * - FTDF_COORD_WISH_DEVICE_LEAVE_PAN: Coordinator wishes that device leaves PAN - * - FTDF_DEVICE_WISH_LEAVE_PAN: Device wishes to leave PAN - */ -typedef uint8_t ftdf_disassociate_reason_t; -#define FTDF_COORD_WISH_DEVICE_LEAVE_PAN 1 -#define FTDF_DEVICE_WISH_LEAVE_PAN 2 - -/** - * \brief Beacon type - * \remark Allowed values: - * - FTDF_NORMAL_BEACON: Normal beacon - * - FTDF_ENHANCED_BEACON: Enhanced beacon - */ -typedef uint8_t ftdf_beacon_type_t; -#define FTDF_NORMAL_BEACON 0 -#define FTDF_ENHANCED_BEACON 1 - -// MAC constants -/** \brief aBaseSlotDuration */ -#define FTDF_BASE_SLOT_DURATION 60 -/** \brief aNumSuperframeSlots */ -#define FTDF_NUM_SUPERFRAME_SLOTS 16 -/** \brief aBaseSuperframeDuration */ -#define FTDF_BASE_SUPERFRAME_DURATION (FTDF_BASE_SLOT_DURATION * FTDF_NUM_SUPERFRAME_SLOTS) -/** \brief NOT USED */ -#define FTDF_GTS_PERSISTENCE_TIME 4 -/** \brief aMaxBeaconOverhead */ -#define FTDF_MAX_BEACON_OVERHEAD 75 -/** \brief aMaxBeaconOverhead */ -#define FTDF_MAX_PHY_PACKET_SIZE 127 -/** \brief aMaxPHYPacketSize */ -#define FTDF_MAX_BEACON_PAYLOAD_LENGTH (FTDF_MAX_PHY_PACKET_SIZE - FTDF_MAX_BEACON_OVERHEAD) -/** \brief NOT USED */ -#define FTDF_MAX_LOST_BEACONS 4 -/** \brief aMaxMPDUUnsecuredOverhead */ -#define FTDF_MAX_MPDU_UNSECURED_OVERHEAD 25 -/** \brief aMinMPDUOverhead */ -#define FTDF_MIN_MPDU_OVERHEAD 9 -/** \brief aMaxMACSafePayloadSize */ -#define FTDF_MAX_MAC_SAFE_PAYLOAD_SIZE (FTDF_MAX_PHY_PACKET_SIZE - FTDF_MAX_MPDU_UNSECURED_OVERHEAD) -/** \brief aMaxMACSafePayloadSize */ -#define FTDF_MAX_PAYLOAD_SIZE (FTDF_MAX_PHY_PACKET_SIZE - FTDF_MIN_MPDU_OVERHEAD) -/** \brief aMaxMACPayloadSize */ -#define FTDF_MAX_SIFS_FRAME_SIZE 18 -/** \brief NOT USED */ -#define FTDF_MIN_CAP_LENGTH 440 -/** \brief aUnitBackoffPeriod */ -#define FTDF_UNIT_BACKOFF_PERIOD 20 - -/** - * \brief PIB attribute id - * \remark List of supported PIB attributes, their types/structures and description - * - FTDF_PIB_EXTENDED_ADDRESS, \link ftdf_ext_address_t \endlink, - * The extended address of the device - * - FTDF_PIB_ACK_WAIT_DURATION, \link ftdf_period_t \endlink, The maximum time in symbols that is - waited for an ack, Read only - * - FTDF_PIB_ASSOCIATION_PAN_COORD, \link ftdf_boolean_t \endlink, Indication whether the device - is associated with a PAN coordinator - * - FTDF_PIB_ASSOCIATION_PERMIT, \link ftdf_boolean_t \endlink, Indication whether the PAN - coordinator grats association requests - * - FTDF_PIB_AUTO_REQUEST, \link ftdf_boolean_t \endlink, Indication whether beacon received while - scanning are forwarded to the application or not - * - FTDF_PIB_BEACON_PAYLOAD, ftdf_octet_t*, Pointer to the data to be included in a beacon as - payload - * - FTDF_PIB_BEACON_PAYLOAD_LENGTH, \link ftdf_size_t \endlink, Size of the data to be included - in a beacon as payload - * - FTDF_PIB_BEACON_ORDER, \link ftdf_order_t \endlink, Fixed to 15 indicating beaconless mode - * - FTDF_PIB_BSN, \link ftdf_sn_t \endlink, The current beacon sequence number - * - FTDF_PIB_COORD_EXTENDED_ADDRESS, \link ftdf_ext_address_t \endlink, The extended address of - the coordinator - * - FTDF_PIB_COORD_SHORT_ADDRESS, \link ftdf_short_address_t \endlink, The short address of the - coordinator - * - FTDF_PIB_DSN, \link ftdf_sn_t \endlink, The current data sequence number - * - FTDF_PIB_MAX_BE, \link ftdf_be_exponent_t \endlink, The maximum backoff exponent - * - FTDF_PIB_MAX_CSMA_BACKOFFS, \link ftdf_size_t \endlink, The maximum number of backoffs - * - FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME, \link ftdf_period_t \endlink, The maximum time in symbols - that RX is ON after that a frame is received with FP set. - * - FTDF_PIB_MAX_FRAME_RETRIES, \link ftdf_size_t \endlink, The maximum number of frame retries - * - FTDF_PIB_MIN_BE, \link ftdf_be_exponent_t \endlink, The minimum backoff exponent - * - FTDF_PIB_LIFS_PERIOD, \link ftdf_period_t \endlink, The long IFS period in number of symbols, - Read oonly - * - FTDF_PIB_SIFS_PERIOD, \link ftdf_period_t \endlink, The short IFS period in number of symbols, - Read oonly - * - FTDF_PIB_PAN_ID, \link ftdf_pan_id_t \endlink, The PAN id of the device - * - FTDF_PIB_PROMISCUOUS_MODE, \link ftdf_boolean_t \endlink, Indication whether the promiscuous - is enable or not - * - FTDF_PIB_RESPONSE_WAIT_TIME, \link ftdf_size_t \endlink, The maximum time in - aBaseSuperFramePeriod's (960 symbols) that is waited for a command frame response - * - FTDF_PIB_RX_ON_WHEN_IDLE, \link ftdf_boolean_t \endlink, Indication whether the receiver - must be on when idle - * - FTDF_PIB_SECURITY_ENABLED, \link ftdf_boolean_t \endlink, Indication whether the security - is enabled - * - FTDF_PIB_SHORT_ADDRESS, \link ftdf_short_address_t \endlink, The short address of the device - * - FTDF_PIB_SYNC_SYMBOL_OFFSET, \link ftdf_period_t \endlink, The offset in symbols between the - start of frame and that the timestamp is taken - * - FTDF_PIB_TIMESTAMP_SUPPORTED, \link ftdf_boolean_t \endlink, Indication whether - timestamping is supported - * - FTDF_PIB_TRANSACTION_PERSISTENCE_TIME, \link ftdf_period_t \endlink, The maximum time in - aBaseSuperFramePeriod's (960 symbols) that indirect data requests are queued - * - FTDF_PIB_ENH_ACK_WAIT_DURATION, \link ftdf_period_t \endlink, The maximum time in symbols - that is waited for an enhanced ack - * - FTDF_PIB_IMPLICIT_BROADCAST, \link ftdf_boolean_t \endlink, Indication whether frames without - a destination PAN are treated as broadcasts - * - FTDF_PIB_DISCONNECT_TIME, \link ftdf_period_t \endlink, The time in timeslots that disassoctate - frames are send before disconnecting - * - FTDF_PIB_JOIN_PRIORITY, \link ftdf_priority_t \endlink, The join priority - * - FTDF_PIB_ASN, \link ftdf_asn_t \endlink, The current ASN - * - FTDF_PIB_SLOTFRAME_TABLE, \link ftdf_slotframe_table_t \endlink, The slotframe table, Read only - * - FTDF_PIB_LINK_TABLE, \link FTDF_LinkTable \endlink, The link table, Read only - * - FTDF_PIB_TIMESLOT_TEMPLATE, \link ftdf_timeslot_template_t \endlink, The current timeslot - template - * - FTDF_PIB_HOPPINGSEQUENCE_ID, \link ftdf_hopping_sequence_id_t \endlink, The id of the current - hopping sequence - * - FTDF_PIB_CHANNEL_PAGE, \link ftdf_channel_page_t \endlink, The current channel page - * - FTDF_PIB_HOPPING_SEQUENCE_LENGTH, \link ftdf_length_t \endlink, Length of the current hopping - sequence - * - FTDF_PIB_HOPPING_SEQUENCE_LIST, \link ftdf_channel_number_t \endlink, Hopping sequence - * - FTDF_PIB_CURRENT_HOP, \link ftdf_length_t \endlink, The current hop - * - FTDF_PIB_CSL_PERIOD, \link ftdf_period_t \endlink, The CSL sample period in units of 10 symbols - * - FTDF_PIB_CSL_MAX_PERIOD, \link ftdf_period_t \endlink, The maximum CSL sample period of devices - in the PAN in units of 10 symbols - * - FTDF_PIB_CSL_CHANNEL_MASK, \link ftdf_bitmap32_t \endlink, Bitmapped list of channels to be - sample in CSL mode - * - FTDF_PIB_CSL_FRAME_PENDING_WAIT_T, \link ftdf_period_t \endlink, The maximum time in symbols - that RX is ON after that a frame is received with FP set in CSL mode. - * - FTDF_PIB_PERFORMANCE_METRICS, \link ftdf_performance_metrics_t \endlink, - The performance metrics, Read only - * - FTDF_PIB_EB_IE_LIST, \link ftdf_ie_list_t \endlink, Payload IE list to be added to an - enhanced beacon - * - FTDF_PIB_EBSN, \link ftdf_sn_t \endlink, Current enhanced beacon sequence number - * - FTDF_PIB_EB_AUTO_SA, \link ftdf_auto_sa_t \endlink, Source address mode of auto generated - enhanced beacons - * - FTDF_PIB_EACK_IE_LIST, \link ftdf_ie_list_t \endlink, Payload IE list to be added - to an enhanced ack - * - FTDF_PIB_KEY_TABLE, \link ftdf_key_table_t \endlink, Security key table - * - FTDF_PIB_DEVICE_TABLE, \link ftdf_device_table_t \endlink, Security device table - * - FTDF_PIB_SECURITY_LEVEL_TABLE, \link ftdf_security_level_table_t \endlink, Security level table - * - FTDF_PIB_FRAME_COUNTER, \link ftdf_frame_counter_t \endlink, Current security frame counter - * - FTDF_PIB_MT_DATA_SECURITY_LEVEL, \link ftdf_security_level_t \endlink, Security level for - auto generated data frames - * - FTDF_PIB_MT_DATA_KEY_ID_MODE, \link ftdf_key_id_mode_t \endlink, Security key id mode for - auto generated data frames - * - FTDF_PIB_MT_DATA_KEY_SOURCE, ftdf_octet_t[8], Security key source for auto generated - data frames - * - FTDF_PIB_MT_DATA_KEY_INDEX, \link ftdf_key_index_t \endlink, Security key index for auto - generated data frames - * - FTDF_PIB_DEFAULT_KEY_SOURCE, ftdf_octet_t[8], Default key source - * - FTDF_PIB_FRAME_COUNTER_MODE, \link ftdf_frame_counter_mode_t \endlink, Security frame counter - mode - * - FTDF_PIB_CSL_SYNC_TX_MARGIN, \link ftdf_period_t \endlink, The margin in unit of 10 symbols - used by FTDF in CSL mode in case of a synchronised transmission - * - FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO, \link ftdf_period_t \endlink, The time in unit of 10 symbols - after which FTDF discard the remote synchronisation info. - * - FTDF_PIB_TSCH_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether the TSCH mode is - enabled or not, Read only - * - FTDF_PIB_LE_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether the CSL mode is - enabled or not - * - FTDF_PIB_CURRENT_CHANNEL, \link ftdf_channel_number_t \endlink, The current channel used - by FTDF - * - FTDF_PIB_CHANNELS_SUPPORTED, \link ftdf_channel_descriptor_list_t \endlink, List of channels - supported by FTDF - * - FTDF_PIB_TX_POWER_TOLERANCE, \link ftdf_tx_power_tolerance_t \endlink, TX power tolerance - * - FTDF_PIB_TX_POWER, \link ftdf_dbm \endlink, TX power - * - FTDF_PIB_CCA_MODE, \link ftdf_cca_mode_t \endlink, CCA mode - * - FTDF_PIB_CURRENT_PAGE, \link ftdf_channel_page_t \endlink, Current channel page - * - FTDF_PIB_MAX_FRAME_DURATION, \link ftdf_period_t \endlink, The maximum number of symbols in - frame, Read only - * - FTDF_PIB_SHR_DURATION, \link ftdf_period_t \endlink, Synchronisation header length in - symbols, Read only - * - FTDF_PIB_TRAFFIC_COUNTERS, \link ftdf_traffic_counters_t \endlink, Miscelaneous - traffic counters, Read only - * - FTDF_PIB_LE_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports LE (CSL), - Read only - * - FTDF_PIB_LL_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports LL, - Read only - * - FTDF_PIB_DSME_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports DSME, - Read only - * - FTDF_PIB_RFID_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports RFID, - Read only - * - FTDF_PIB_AMCA_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports AMCA, - Read only - * - FTDF_PIB_TSCH_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports FTDF, - Read only - * - FTDF_PIB_METRICS_CAPABLE, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports - metrics, Read only - * - FTDF_PIB_RANGING_SUPPORTED, \link ftdf_boolean_t \endlink, Indicates whether FTDF supports - ranging, Read only - * - FTDF_PIB_KEEP_PHY_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether the PHY must - be kept enabled - * - FTDF_PIB_METRICS_ENABLED, \link ftdf_boolean_t \endlink, Indicates whether metrics - are enabled or not - * - FTDF_PIB_BEACON_AUTO_RESPOND, \link ftdf_boolean_t \endlink, Indicates whether FTDF must - send automatically a beacon at a BECAON_REQUEST command frame or must forward the request - to the application using FTDF_BEACON_REQUEST_INDICATION. - * - FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD, \link ftdf_period_t \endlink, The minimum TSCH slot sync - offset in microseconds before resyncing - */ -typedef uint8_t ftdf_pib_attribute_t; -// See Table 52 "MAC PIB attributes" of IEEE 802.15.4-2011 and IEEE 802.15.4e-2012 for more details - -// NOTE: Be careful with changing the order of these PIB attributes because initialization of related -// registers will be done in the order defined here. -#define FTDF_PIB_EXTENDED_ADDRESS 1 -#define FTDF_PIB_ACK_WAIT_DURATION 2 -#define FTDF_PIB_ASSOCIATION_PAN_COORD 3 -#define FTDF_PIB_ASSOCIATION_PERMIT 4 -#define FTDF_PIB_AUTO_REQUEST 5 -#define FTDF_PIB_BATT_LIFE_EXT 6 -#define FTDF_PIB_BATT_LIFE_EXT_PERIODS 7 -#define FTDF_PIB_BEACON_PAYLOAD 8 -#define FTDF_PIB_BEACON_PAYLOAD_LENGTH 9 -#define FTDF_PIB_BEACON_ORDER 10 -#define FTDF_PIB_BEACON_TX_TIME 11 -#define FTDF_PIB_BSN 12 -#define FTDF_PIB_COORD_EXTENDED_ADDRESS 13 -#define FTDF_PIB_COORD_SHORT_ADDRESS 14 -#define FTDF_PIB_DSN 15 -#define FTDF_PIB_GTS_PERMIT 16 -#define FTDF_PIB_MAX_BE 17 -#define FTDF_PIB_MAX_CSMA_BACKOFFS 18 -#define FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME 19 -#define FTDF_PIB_MAX_FRAME_RETRIES 20 -#define FTDF_PIB_MIN_BE 21 -#define FTDF_PIB_LIFS_PERIOD 22 -#define FTDF_PIB_SIFS_PERIOD 23 -#define FTDF_PIB_PAN_ID 24 -#define FTDF_PIB_PROMISCUOUS_MODE 25 -#define FTDF_PIB_RESPONSE_WAIT_TIME 26 -#define FTDF_PIB_RX_ON_WHEN_IDLE 27 -#define FTDF_PIB_SECURITY_ENABLED 28 -#define FTDF_PIB_SHORT_ADDRESS 29 -#define FTDF_PIB_SUPERFRAME_ORDER 30 -#define FTDF_PIB_SYNC_SYMBOL_OFFSET 31 -#define FTDF_PIB_TIMESTAMP_SUPPORTED 32 -#define FTDF_PIB_TRANSACTION_PERSISTENCE_TIME 33 -#define FTDF_PIB_TX_CONTROL_ACTIVE_DURATION 34 -#define FTDF_PIB_TX_CONTROL_PAUSE_DURATION 35 -#define FTDF_PIB_ENH_ACK_WAIT_DURATION 36 -#define FTDF_PIB_IMPLICIT_BROADCAST 37 -#define FTDF_PIB_SIMPLE_ADDRESS 38 -#define FTDF_PIB_DISCONNECT_TIME 39 -#define FTDF_PIB_JOIN_PRIORITY 40 -#define FTDF_PIB_ASN 41 -#define FTDF_PIB_NO_HL_BUFFERS 42 -#define FTDF_PIB_SLOTFRAME_TABLE 43 -#define FTDF_PIB_LINK_TABLE 44 -#define FTDF_PIB_TIMESLOT_TEMPLATE 45 -#define FTDF_PIB_HOPPINGSEQUENCE_ID 46 -#define FTDF_PIB_CHANNEL_PAGE 47 -#define FTDF_PIB_NUMBER_OF_CHANNELS 48 -#define FTDF_PIB_PHY_CONFIGURATION 49 -#define FTDF_PIB_EXTENTED_BITMAP 50 -#define FTDF_PIB_HOPPING_SEQUENCE_LENGTH 51 -#define FTDF_PIB_HOPPING_SEQUENCE_LIST 52 -#define FTDF_PIB_CURRENT_HOP 53 -#define FTDF_PIB_DWELL_TIME 54 -#define FTDF_PIB_CSL_PERIOD 55 -#define FTDF_PIB_CSL_MAX_PERIOD 56 -#define FTDF_PIB_CSL_CHANNEL_MASK 57 -#define FTDF_PIB_CSL_FRAME_PENDING_WAIT_T 58 -#define FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED 59 -#define FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL 60 -#define FTDF_PIB_PERFORMANCE_METRICS 61 -#define FTDF_PIB_USE_ENHANCED_BEACON 62 -#define FTDF_PIB_EB_IE_LIST 63 -#define FTDF_PIB_EB_FILTERING_ENABLED 64 -#define FTDF_PIB_EBSN 65 -#define FTDF_PIB_EB_AUTO_SA 66 -#define FTDF_PIB_EACK_IE_LIST 67 -#define FTDF_PIB_KEY_TABLE 68 -#define FTDF_PIB_DEVICE_TABLE 69 -#define FTDF_PIB_SECURITY_LEVEL_TABLE 70 -#define FTDF_PIB_FRAME_COUNTER 71 -#define FTDF_PIB_MT_DATA_SECURITY_LEVEL 72 -#define FTDF_PIB_MT_DATA_KEY_ID_MODE 73 -#define FTDF_PIB_MT_DATA_KEY_SOURCE 74 -#define FTDF_PIB_MT_DATA_KEY_INDEX 75 -#define FTDF_PIB_DEFAULT_KEY_SOURCE 76 -#define FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS 77 -#define FTDF_PIB_PAN_COORD_SHORT_ADDRESS 78 -#define FTDF_PIB_FRAME_COUNTER_MODE 79 -#define FTDF_PIB_CSL_SYNC_TX_MARGIN 80 -#define FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO 81 -#define FTDF_PIB_TSCH_ENABLED 82 -#define FTDF_PIB_LE_ENABLED 83 - -// See Table 71 "PHY PIB attributes" of IEEE 802.15.4-2011 for more details -#define FTDF_PIB_CURRENT_CHANNEL 84 -#define FTDF_PIB_CHANNELS_SUPPORTED 85 -#define FTDF_PIB_TX_POWER_TOLERANCE 86 -#define FTDF_PIB_TX_POWER 87 -#define FTDF_PIB_CCA_MODE 88 -#define FTDF_PIB_CURRENT_PAGE 89 -#define FTDF_PIB_MAX_FRAME_DURATION 90 -#define FTDF_PIB_SHR_DURATION 91 - -#define FTDF_PIB_TRAFFIC_COUNTERS 92 -#define FTDF_PIB_LE_CAPABLE 93 -#define FTDF_PIB_LL_CAPABLE 94 -#define FTDF_PIB_DSME_CAPABLE 95 -#define FTDF_PIB_RFID_CAPABLE 96 -#define FTDF_PIB_AMCA_CAPABLE 97 -#define FTDF_PIB_METRICS_CAPABLE 98 -#define FTDF_PIB_RANGING_SUPPORTED 99 -#define FTDF_PIB_KEEP_PHY_ENABLED 100 -#define FTDF_PIB_METRICS_ENABLED 101 -#define FTDF_PIB_BEACON_AUTO_RESPOND 102 -#define FTDF_PIB_TSCH_CAPABLE 103 -#define FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD 104 - -/* Proprietary PIB. */ -#define FTDF_PIB_BO_IRQ_THRESHOLD 105 -#define FTDF_PIB_PTI_CONFIG 106 -#define FTDF_PIB_LINK_QUALITY_MODE 107 - -// Total number of PIB attributes -#define FTDF_NR_OF_PIB_ATTRIBUTES 107 - -/* Default values */ -#ifndef FTDF_BO_IRQ_THRESHOLD -#define FTDF_BO_IRQ_THRESHOLD 0xff -#endif - -#if FTDF_DBG_BUS_ENABLE -/** - * \brief Debug bus mode. - * - */ -typedef uint8_t ftdf_dbg_mode_t; - -/** - * \brief Disable debug signals - */ -#define FTDF_DBG_DISABLE 0x00 - -/** - * \brief Legacy debug mode - * diagnose bus bit 7 = ed_request - * diagnose bus bit 6 = gen_irq - * diagnose bus bit 5 = tx_en - * diagnose bus bit 4 = rx_en - * diagnose bus bit 3 = phy_en - * diagnose bus bit 2 = tx_valid - * diagnose bus bit 1 = rx_sof - * diagnose bus bit 0 = rx_eof - */ -#define FTDF_DBG_LEGACY 0x01 - -/** - * \brief Clocks and reset - * diagnose bus bit 7-3 = "00000" - * diagnose bus bit 2 = lp_clk divide by 2 - * diagnose bus bit 1 = mac_clk divide by 2 - * diagnose bus bit 0 = hclk divided by 2 - */ -#define FTDF_DBG_CLK_RESET 0x02 - -/** - * \brief Rx phy signals - * diagnose_bus bit 7 = rx_enable towards the rx_pipeline - * diagnose bus bit 6 = rx_sof from phy - * diagnose bus bit 5-2 = rx_data from phy - * diagnose bus bit 1 = rx_eof to phy - * diagnose bus bit 0 = rx_sof event from rx_mac_timing block - */ -#define FTDF_DBG_RX_PHY_SIGNALS 0x10 - -/** - * \brief Rx sof and length - * diagnose_bus bit 7 = rx_sof - * diagnose bus bit 6-0 = rx_mac_length from rx_mac_timing block - */ -#define FTDF_DBG_RX_SOF_AND_LENGTH 0x11 - -/** - * \brief Rx mac timing output - * diagnose_bus bit 7 = Enable from rx_mac_timing block - * diagnose bus bit 6 = Sop from rx_mac_timing block - * diagnose bus bit 5 = Eop from rx_mac_timing block - * diagnose bus bit 4 = Crc from rx_mac_timing block - * diagnose bus bit 3 = Err from rx_mac_timing block - * diagnose bus bit 2 = Drop from rx_mac_timing block - * diagnose bus bit 1 = Forward from rx_mac_timing block - * diagnose bus bit 0 = rx_sof - */ -#define FTDF_DBG_RX_MAC_TIMING_OUTPUT 0x12 - -/** - * \brief Rx mac frame parser output - * diagnose_bus bit 7 = Enable from mac_frame_parser block - * diagnose bus bit 6 = Sop from mac_frame_parser block - * diagnose bus bit 5 = Eop from mac_frame_parser block - * diagnose bus bit 4 = Crc from mac_frame_parser block - * diagnose bus bit 3 = Err from mac_frame_parser block - * diagnose bus bit 2 = Drop from mac_frame_parser block - * diagnose bus bit 1 = Forward from mac_frame_parser block - * diagnose bus bit 0 = rx_sof - */ -#define FTDF_DBG_RX_MAC_FRAME_PARSER_OUTPUT 0x13 - -/** - * \brief Rx status to Umac - * diagnose_bus bit 7 = rx_frame_stat_umac.crc16_error - * diagnose bus bit 6 = rx_frame_stat_umac.res_frm_type_error - * diagnose bus bit 5 = rx_frame_stat_umac.res_frm_version_error - * diagnose bus bit 4 = rx_frame_stat_umac.dpanid_error - * diagnose bus bit 3 = rx_frame_stat_umac.daddr_error - * diagnose bus bit 2 = rx_frame_stat_umac.spanid_error - * diagnose bus bit 1 = rx_frame_stat_umac.ispan_coord_error - * diagnose bus bit 0 = rx_sof - */ -#define FTDF_DBG_RX_STATUS_TO_UMAC 0x14 - -/** - * \brief Rx status to lmac - * diagnose_bus bit 7 = rx_frame_stat.packet_valid - * diagnose bus bit 6 = rx_frame_stat.rx_sof_e - * diagnose bus bit 5 = rx_frame_stat.rx_eof_e - * diagnose bus bit 4 = rx_frame_stat.wakeup_frame - * diagnose bus bit 3-1 = rx_frame_stat.frame_type - * diagnose bus bit 0 = rx_frame_stat.rx_sqnr_valid - */ -#define FTDF_DBG_RX_STATUS_TO_LMAC 0x15 - -/** - * \brief Rx buffer control - * diagnose_bus bit 7-4 = prov_from_swio.rx_read_buf_ptr - * diagnose bus bit 3-0 = stat_to_swio.rx_write_buf_ptr - */ -#define FTDF_DBG_RX_BUFFER_CONTROL 0x16 - -/** - * \brief Rx interrupts - * diagnose_bus bit 7 = stat_to_swio.rx_buf_avail_e - * diagnose bus bit 6 = stat_to_swio.rx_buf_full - * diagnose bus bit 5 = stat_to_swio.rx_buf_overflow_e - * diagnose bus bit 4 = stat_to_swio.rx_sof_e - * diagnose bus bit 3 = stat_to_swio.rxbyte_e - * diagnose bus bit 2 = rx_frame_ctrl.rx_enable - * diagnose bus bit 1 = rx_eof - * diagnose bus bit 0 = rx_sof - */ -#define FTDF_DBG_RX_INTERRUPTS 0x17 - -/** - * \brief MAC frame parser events - * diagnose_bus bit 7-3 = - * Prt statements mac frame parser - * 0 Reset - * 1 Multipurpose frame with no destination PAN id and macImplicitBroadcast is - * false and not PAN coordinator dropped - * 2 Multipurpose frame with no destination address and macImplicitBroadcast is - * false and not PAN coordinator dropped - * 3 RX unsupported frame type detected - * 4 RX non Beacon frame detected and dropped in RxBeaconOnly mode - * 5 RX frame passed due to macAlwaysPassFrmType set - * 6 RX unsupported da_mode = 01 for frame_version 0x0- detected - * 7 RX unsupported sa_mode = 01 for frame_version 0x0- detected - * 8 Data or command frame with no destination PAN id and macImplicitBroadcast - * is false and not PAN coordinator dropped - * 9 Data or command frame with no destination address and macImplicitBroadcast - * is false and not PAN coordinator dropped - * 10 RX unsupported frame_version detected - * 11 Multipurpose frame with no destination PAN id and macImplicitBroadcast is - * false and not PAN coordinator dropped - * 12 Multipurpose frame with no destination address and macImplicitBroadcast - * is false and not PAN coordinator dropped - * 13 RX unsupported frame_version detected - * 14 RX Destination PAN Id check failed - * 15 RX Destination address (1 byte) check failed - * 16 RX Destination address (2 byte) check failed - * 17 RX Destination address (8 byte) check failed - * 18 RX Source PAN Id check for Beacon frames failed - * 19 RX Source PAN Id check failed - * 20 Auxiliary Security Header security control word received - * 21 Auxiliary Security Header unsupported_legacy received frame_version 00 - * 22 Auxiliary Security Header unsupported_legacy security frame_version 11 - * 23 Auxiliary Security Header frame counter field received - * 24 Auxiliary Security Header Key identifier field received - * 25 Errored dDestination Wakeup frame found send to UMAC, not indicated - * towards LMAC controller - * 26 MacAlwaysPassWakeUpFrames = 1, Wakeup frame found send to UMAC, not - * indicated towards LMAC controller - * 27 Wakeup frame found send to LMAC controller and UMAC - * 28 Wakeup frame found send to LMAC controller, dropped towards UMAC - * 29 Command frame with data_request command received - * 30 Coordinator realignment frame received - * 31 Not Used - * diagnose bus bit 2-0 = frame_type - */ -#define FTDF_DBG_RX_MAC_FRAME_PARSER_EVENTS 0x18 - -/** - * \brief MAC frame parser states - * diagnose_bus bit 7-4 = - * Framestates mac frame parser - * 0 idle_state - * 1 fr_ctrl_state - * 2 fr_ctrl_long_state - * 3 seq_nr_state - * 4 dest_pan_id_state - * 5 dest_addr_state - * 6 src_pan_id_state - * 7 src_addr_state - * 8 aux_sec_hdr_state - * 9 hdr_ie_state - * 10 pyld_ie_state - * 11 ignore_state - * 12-16 Not used - * diagnose bus bit 3 = rx_mac_sof_e - * diagnose bus bit 2-0 = frame_type - */ -#define FTDF_DBG_RX_MAC_FRAME_PARSER_STATES 0x19 - -/** - * \brief Top and bottom interfaces tx datapath - * diagnose_bus bit 7 = tx_mac_ld_strb - * diagnose bus bit 6 = tx_mac_drdy - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = symbol_ena - */ -#define FTDF_DBG_TX_TOP_BOTTOM_INTERFACES 0x20 - -/** - * \brief Control signals for tx datapath - * diagnose_bus bit 7 = TxTransparentMode - * diagnose bus bit 6 = ctrl_lmac_to_tx.CRC16_ena - * diagnose bus bit 5 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose bus bit 3 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 2-1 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose bus bit 0 = tx_valid - */ -#define FTDF_DBG_TX_CONTROL_SIGNALS 0x21 - -/** - * \brief Control signals for wakeup frames - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 5-1 = ctrl_lmac_to_tx.gen_wu_RZ(4 DOWNTO 0) - * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero - */ -#define FTDF_DBG_TX_WAKEUP_CONTROL_SIGNALS 0x22 - -/** - * \brief Data signals for wakeup frame - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero - */ -#define FTDF_DBG_TX_WAKUP_DATA_SIGNALS 0x23 - -/** - * \brief Data and control ack frame - * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start - * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_ack - * diagnose bus bit 5 = tx_valid - * diagnose bus bit 4-1 = tx_data - * diagnose bus bit 0 = symbol_ena - */ -#define FTDF_DBG_TX_ACK_ 0x24 - - -/** - * \brief PHY signals - * diagnose_bus bit 7 = phy_en - * diagnose bus bit 6 = tx_en - * diagnose bus bit 5 = rx_en - * diagnose bus bit 4-1 = phyattr(3 downto 0) - * diagnose bus bit 0 = ed_request - */ -#define FTDF_DBG_LMAC_PHY_SIGNALS 0x30 - -/** - * \brief PHY enable and detailed state machine info - * diagnose_bus bit 7 = phy_en - * diagnose bus bit 6-0 = prt statements detailed state machine info - * 0 Reset - * 1 MAIN_STATE_IDLE TX_ACKnowledgement frame skip CSMA_CA - * 2 MAIN_STATE_IDLE : Wake-Up frame resides in buffer no - * 3 MAIN_STATE_IDLE : TX frame in TSCH mode - * 4 MAIN_STATE_IDLE : TX frame - * 5 MAIN_STATE_IDLE : goto SINGLE_CCA - * 6 MAIN_STATE_IDLE : goto Energy Detection - * 7 MAIN_STATE_IDLE : goto RX - * 8 MAIN_STATE_IDLE de-assert phy_en wait for - * 9 MAIN_STATE_IDLE Start phy_en and assert phy_en wait for : - * 10 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA framenr : - * 11 MAIN_STATE_CSMA_CA framenr : - * 12 MAIN_STATE_CSMA_CA start CSMA_CA - * 14 MAIN_STATE_CSMA_CA skip CSMA_CA - * 15 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed for CSL mode - * 16 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed - * 17 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Success - * 18 MAIN_STATE_SINGLE_CCA CCA failed - * 19 MAIN_STATE_SINGLE_CCA CCA ok - * 20 MAIN_STATE_WAIT_ACK_DELAY wait time elapsed - * 21 MAIN_STATE_WAIT ACK_DELAY : Send Ack in TSCH mode - * 22 MAIN_STATE_WAIT ACK_DELAY : Ack not scheduled in time in TSCH mode - * 23 MAIN_STATE_TSCH_TX_FRAME macTSRxTx time elapsed - * 24 MAIN_STATE_TX_FRAME it is CSL mode, start the WU seq for macWUPeriod - * 25 MAIN_STATE_TX_FRAME1 - * 26 MAIN_STATE_TX_FRAME_W1 exit, waited for : - * 27 MAIN_STATE_TX_FRAME_W2 exit, waited for : - * 28 MAIN_STATE_TX_WAIT_LAST_SYMBOL exit - * 29 MAIN_STATE_TX_RAMPDOWN_W exit, waited for : - * 30 MAIN_STATE_TX_PHYTRXWAIT exit, waited for : - * 31 MAIN_STATE_GEN_IFS , Ack with frame pending received - * 32 MAIN_STATE_GEN_IFS , Ack requested but DisRXackReceivedca is set - * 33 MAIN_STATE_GEN_IFS , instead of generating an IFS, switch the rx-on for - * an ACK - * 34 MAIN_STATE_GEN_IFS , generating an SIFS (Short Inter Frame Space) - * 35 MAIN_STATE_GEN_IFS , generating an LIFS (Long Inter Frame Space) - * 36 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'cslperiod_timer_ready' is ready - * sent the data frame - * 37 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'Rendezvous zero time not yet - * transmitted sent another WU frame - * 38 MAIN_STATE_GEN_IFS_FINISH exit, corrected for : - * 39 MAIN_STATE_GEN_IFS_FINISH in CSL mode, rx_resume_after_tx is set - * 40 MAIN_STATE_SENT_STATUS CSLMode wu_sequence_done_flag : - * 41 MAIN_STATE_ADD_DELAY exit, goto RX for frame pending time - * 42 MAIN_STATE_ADD_DELAY exit, goto IDLE - * 43 MAIN_STATE_RX switch the RX from off to on - * 44 MAIN_STATE_RX_WAIT_PHYRXSTART waited for - * 45 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the MacAckDuration timer - * 46 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the ack wait timer - * 47 MAIN_STATE_RX_WAIT_PHYRXLATENCY NORMAL mode : start rx_duration - * 48 MAIN_STATE_RX_WAIT_PHYRXLATENCY TSCH mode : start macTSRxWait - * (macTSRxWait) timer - * 49 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration - * (macCSLsamplePeriod) timer - * 50 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration - * (macCSLdataPeriod) timer - * 51 MAIN_STATE_RX_CHK_EXPIRED 1 ackwait_timer_ready or ack_received_ind - * 52 MAIN_STATE_RX_CHK_EXPIRED 2 normal_mode. ACK with FP bit set, start frame - * pending timer - * 54 MAIN_STATE_RX_CHK_EXPIRED 4 RxAlwaysOn is set to 0 - * 55 MAIN_STATE_RX_CHK_EXPIRED 5 TSCH mode valid frame rxed - * 56 MAIN_STATE_RX_CHK_EXPIRED 6 TSCH mode macTSRxwait expired - * 57 MAIN_STATE_RX_CHK_EXPIRED 7 macCSLsamplePeriod timer ready - * 58 MAIN_STATE_RX_CHK_EXPIRED 8 csl_mode. Data frame recieved with FP bit - * set, increment RX duration time - * 59 MAIN_STATE_RX_CHK_EXPIRED 9 CSL mode : Received wu frame in data - * listening period restart macCSLdataPeriod timer - * 60 MAIN_STATE_RX_CHK_EXPIRED 10 csl_rx_duration_ready or csl data frame - * received: - * 61 MAIN_STATE_RX_CHK_EXPIRED 11 normal_mode. FP bit is set, start frame - * pending timer - * 62 MAIN_STATE_RX_CHK_EXPIRED 12 normal mode rx_duration_timer_ready and - * frame_pending_timer_ready - * 63 MAIN_STATE_RX_CHK_EXPIRED 13 acknowledge frame requested - * 64 MAIN_STATE_RX_CHK_EXPIRED 14 Interrupt to sent a frame. found_tx_packet - * 65 MAIN_STATE_CSL_RX_IDLE_END RZ time is far away, switch receiver Off and - * wait for csl_rx_rz_time before switching on - * 66 MAIN_STATE_CSL_RX_IDLE_END RZ time is not so far away, keep receiver On - * and wait for - * 67 MAIN_STATE_RX_START_PHYRXSTOP ack with fp received keep rx on - * 68 MAIN_STATE_RX_START_PHYRXSTOP switch the RX from on to off - * 69 MAIN_STATE_RX_WAIT_PHYRXSTOP acknowledge done : switch back to finish TX - * 70 MAIN_STATE_RX_WAIT_PHYRXSTOP switch the RX off - * 71 MAIN_STATE_ED switch the RX from off to on - * 72 MAIN_STATE_ED_WAIT_PHYRXSTART waited for phyRxStartup - * 73 MAIN_STATE_ED_WAIT_EDSCANDURATION waited for EdScanDuration - * 74 MAIN_STATE_ED_WAIT_PHYRXSTOP end of Energy Detection, got IDLE - * 75 - 127 Not used - */ -#define FTDF_DBG_LMAC_ENABLE_AND_SM 0x31 - -/** - * \brief RX enable and detailed state machine info - * diagnose_bus bit 7 = rx_en - * diagnose bus bit 6-0 = detailed state machine info see FTDF_DBG_LMAC_ENABLE_AND_SM - */ -#define FTDF_DBG_LMAC_RX_ENABLE_AND_SM 0x32 - -/** - * \brief TX enable and detailed state machine info - * diagnose_bus bit 7 = tx_en - * diagnose bus bit 6-0 = detailed state machine info see FTDF_DBG_LMAC_ENABLE_AND_SM - */ -#define FTDF_DBG_LMAC_TX_ENABLE_AND_SM 0x33 - -/** - * \brief PHY enable, TX enable and Rx enable and state machine states - * diagnose_bus bit 7 = phy_en - * diagnose_bus bit 6 = tx_en - * diagnose_bus bit 5 = rx_en - * diagnose bus bit 4-0 = State machine states - * 1 MAIN_STATE_IDLE - * 2 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA - * 3 MAIN_STATE_CSMA_CA - * 4 MAIN_STATE_WAIT_FOR_CSMA_CA_0 - * 5 MAIN_STATE_WAIT_FOR_CSMA_CA - * 6 MAIN_STATE_SINGLE_CCA - * 7 MAIN_STATE_WAIT_ACK_DELAY - * 8 MAIN_STATE_TSCH_TX_FRAME - * 9 MAIN_STATE_TX_FRAME - * 10 MAIN_STATE_TX_FRAME1 - * 11 MAIN_STATE_TX_FRAME_W1 - * 12 MAIN_STATE_TX_FRAME_W2 - * 13 MAIN_STATE_TX_WAIT_LAST_SYMBOL - * 14 MAIN_STATE_TX_RAMPDOWN - * 15 MAIN_STATE_TX_RAMPDOWN_W - * 16 MAIN_STATE_TX_PHYTRXWAIT - * 17 MAIN_STATE_GEN_IFS - * 18 MAIN_STATE_GEN_IFS_FINISH - * 19 MAIN_STATE_SENT_STATUS - * 20 MAIN_STATE_ADD_DELAY - * 21 MAIN_STATE_TSCH_RX_ACKDELAY - * 22 MAIN_STATE_RX - * 23 MAIN_STATE_RX_WAIT_PHYRXSTART - * 24 MAIN_STATE_RX_WAIT_PHYRXLATENCY - * 25 MAIN_STATE_RX_CHK_EXPIRED - * 26 MAIN_STATE_CSL_RX_IDLE_END - * 27 MAIN_STATE_RX_START_PHYRXSTOP - * 28 MAIN_STATE_RX_WAIT_PHYRXSTOP - * 29 MAIN_STATE_ED - * 30 MAIN_STATE_ED_WAIT_PHYRXSTART - * 31 MAIN_STATE_ED_WAIT_EDSCANDURATION - */ -#define FTDF_DBG_LMAC_RX_TX_ENABLE_AND_STATES 0x34 - -/** - * \brief LMAC controller to tx interface with wakeup - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen_wu - * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start - * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol - */ -#define FTDF_DBG_LMAC_TO_TX_AND_WAKEUP 0x35 - -/** - * \brief LMAC controller to tx interface with frame pending - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen.fp_bit - * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack - * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr - * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start - * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol - */ -#define FTDF_DBG_LMAC_TO_TX_AND_FRAME_PENDING 0x36 - -/** - * \brief Rx pipepline to LMAC controller interface - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = ctrl_rx_to_lmac.rx_sof_e - * diagnose_bus bit 4 = ctrl_rx_to_lmac.rx_eof_e - * diagnose_bus bit 3 = ctrl_rx_to_lmac.packet_valid - * diagnose_bus bit 2 = ack_received_ind - * diagnose_bus bit 1 = ack_request_ind - * diagnose_bus bit 0 = ctrl_rx_to_lmac.data_request_frame - */ -#define FTDF_DBG_LMAC_RX_TO_LMAC 0x37 - -/** - * \brief CSL start - * diagnose_bus bit 7 = tx_en - * diagnose_bus bit 6 = rx_en - * diagnose_bus bit 5 = csl_start - * diagnose_bus bit 4-1 = swio_always_on_to_lmac_ctrl.tx_flag_stat - * diagnose_bus bit 0 = found_wu_packet; - */ -#define FTDF_DBG_LMAC_CSL_START 0x38 - -/** - * \brief TSCH TX ACK timing - * diagnose_bus bit 7-4 = swio_always_on_to_lmac_ctrl.tx_flag_stat - * diagnose_bus bit 3 = tx_en - * diagnose_bus bit 2 = rx_en - * diagnose_bus bit 1 = ctrl_rx_to_lmac.packet_valid - * diagnose_bus bit 0 = one_us_timer_ready - */ -#define FTDF_DBG_LMAC_TSCH_ACK_TIMING 0x39 - - -/** - * \brief Security control - * diagnose_bus bit 7 = swio_to_security.secStart - * diagnose_bus bit 6 = swio_to_security.secTxRxn - * diagnose_bus bit 5 = swio_to_security.secAbort - * diagnose_bus bit 4 = swio_to_security.secEncDecn - * diagnose_bus bit 3 = swio_from_security.secBusy - * diagnose_bus bit 2 = swio_from_security.secAuthFail - * diagnose_bus bit 1 = swio_from_security.secReady_e - * diagnose_bus bit 0 = '0' - */ -#define FTDF_DBG_SEC_CONTROL 0x40 - -/** - * \brief Security CTLID access Rx and Tx - * diagnose_bus bit 7 = tx_sec_ci.ld_strb - * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = tx_sec_ci.selectp - * diagnose_bus bit 4 = tx_sec_co.d_rdy - * diagnose_bus bit 3 = rx_sec_ci.ld_strb - * diagnose_bus bit 2 = rx_sec_ci.ctlid_rw - * diagnose_bus bit 1 = rx_sec_ci.selectp - * diagnose_bus bit 0 = rx_sec_co.d_rdy - */ -#define FTDF_DBG_SEC_CTLID_ACCESS_RX_TX 0x41 - -/** - * \brief Security ctlid access tx with sec_wr_data_valid - * diagnose_bus bit 7 = tx_sec_ci.ld_strb - * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = tx_sec_ci.selectp - * diagnose_bus bit 4 = tx_sec_co.d_rdy - * diagnose_bus bit 3-0 = sec_wr_data_valid - */ -#define FTDF_DBG_SEC_CTLID_ACCESS_TX_AND_SEC_WR_DATA_VALID 0x42 - -/** - * \brief Security ctlid access rx with sec_wr_data_valid - * diagnose_bus bit 7 = rx_sec_ci.ld_strb - * diagnose_bus bit 6 = rx_sec_ci.ctlid_rw - * diagnose_bus bit 5 = rx_sec_ci.selectp - * diagnose_bus bit 4 = rx_sec_co.d_rdy - * diagnose_bus bit 3-0 = sec_wr_data_valid - */ -#define FTDF_DBG_SEC_CTLID_ACCESS_RX_AND_SEC_WR_DATA_VALID 0x43 - -/** - * \brief AHB bus without hsize - * diagnose_bus bit 7 = hsel - * diagnose_bus bit 6-5 = htrans - * diagnose_bus bit 4 = hwrite - * diagnose_bus bit 3 = hready_in - * diagnose_bus bit 2 = hready_out - * diagnose_bus bit 1-0 = hresp - */ -#define FTDF_DBG_AHB_WO_HSIZE 0x50 - -/** - * \brief AHB bus without hwready_in and hresp(1) - * diagnose_bus bit 7 = hsel - * diagnose_bus bit 6-5 = htrans - * diagnose_bus bit 4 = hwrite - * diagnose_bus bit 3-2 = hhsize(1 downto 0) - * diagnose_bus bit 1 = hready_out - * diagnose_bus bit 0 = hresp(0) - */ -#define FTDF_DBG_AHB_WO_HW_READY_HRESP 0x51 - -/** - * \brief AMBA Tx signals - * diagnose_bus bit 7 = ai_tx.penable - * diagnose_bus bit 6 = ai_tx.psel - * diagnose_bus bit 5 = ai_tx.pwrite - * diagnose_bus bit 4 = ao_tx.pready - * diagnose_bus bit 3 = ao_tx.pslverr - * diagnose_bus bit 2-1 = psize_tx - * diagnose_bus bit 0 = hready_out - */ -#define FTDF_DBG_AHB_AMBA_TX_SIGNALS 0x52 - -/** - * \brief AMBA Rx signals - * diagnose_bus bit 7 = ai_rx.penable - * diagnose_bus bit 6 = ai_rx.psel - * diagnose_bus bit 5 = ai_rx.pwrite - * diagnose_bus bit 4 = ao_rx.pready - * diagnose_bus bit 3 = ao_rx.pslverr - * diagnose_bus bit 2-1 = psize_rx - * diagnose_bus bit 0 = hready_out - */ -#define FTDF_DBG_AHB_AMBA_RX_SIGNALS 0x53 - -/** - * \brief AMBA register map signals - * diagnose_bus bit 7 = ai_reg.penable - * diagnose_bus bit 6 = ai_reg.psel - * diagnose_bus bit 5 = ai_reg.pwrite - * diagnose_bus bit 4 = ao_reg.pready - * diagnose_bus bit 3 = ao_reg.pslverr - * diagnose_bus bit 2-1 = "00" - * diagnose_bus bit 0 = hready_out - */ -#define FTDF_DBG_AHB_AMBA_REG_MAP_SIGNALS 0x54 - -#endif /* FTDF_DBG_BUS_ENABLE */ - -#define FTDF_MAX_HOPPING_SEQUENCE_LENGTH 16 - -typedef void ftdf_pib_attribute_value_t; - -/** - * \brief Link quality - * \remark Range: 0..255 - * \remark A higher number is a higher quality - */ -typedef uint8_t ftdf_link_quality_t; - -/** - * \brief Hopping sequence id - */ -typedef uint16_t ftdf_hopping_sequence_id_t; - -/** - * \brief Channel number - * \remark Supported range: 11..27 - */ -typedef uint8_t ftdf_channel_number_t; - -/** - * \brief Packet Traffic Information (PTI) used to classify a transaction in the radio arbiter. - */ -typedef uint8_t ftdf_pti_t; - -enum { - /* PTI index for explicit Rx. */ - FTDF_PTI_CONFIG_RX, - /* PTI index for Tx. */ - FTDF_PTI_CONFIG_TX, - FTDF_PTI_CONFIG_RESERVED0, - FTDF_PTI_CONFIG_RESERVED1, - FTDF_PTI_CONFIG_RESERVED2, - FTDF_PTI_CONFIG_RESERVED3, - FTDF_PTI_CONFIG_RESERVED4, - FTDF_PTI_CONFIG_RESERVED5, - /* Enumeration end. */ - FTDF_PTIS, -}; - -typedef struct { - ftdf_pti_t ptis[FTDF_PTIS]; -} ftdf_pti_config_t; - -/** - * \brief Channel page - * \remark Supported values: 0 - */ -typedef uint8_t ftdf_channel_page_t; - -typedef uint8_t ftdf_channel_offset_t; - -typedef uint8_t ftdf_octet_t; - -/** - * \brief 8-bit type bitmap - */ -typedef uint8_t ftdf_bitmap8_t; - -/** - * \brief 16-bit type bitmap - */ -typedef uint16_t ftdf_bitmap16_t; - -/** - * \brief 32-bit type bitmap - */ -typedef uint32_t ftdf_bitmap32_t; - -typedef uint8_t ftdf_num_of_backoffs_t; - -typedef uint8_t ftdf_gts_charateristics_t; - -/** - * \brief Scan type - * \remark Allowed values: - * - FTDF_ED_SCAN: Energy detect scan - * - FTDF_ACTIVE_SCAN: Active scan - * - FTDF_PASSIVE_SCAN: Passive scan - * - FTDF_ORPHAN_SCAN: Orphan scan - * - FTDF_ENHANCED_ACTIVE_SCAN: Enhanced active scan - */ -typedef uint8_t ftdf_scan_type_t; -#define FTDF_ED_SCAN 1 -#define FTDF_ACTIVE_SCAN 2 -#define FTDF_PASSIVE_SCAN 3 -#define FTDF_ORPHAN_SCAN 4 -#define FTDF_ENHANCED_ACTIVE_SCAN 7 - -typedef uint8_t ftdf_scan_duration_t; - -/** - * \brief Loss operation - * \remark Possible values: - * - FTDF_PAN_ID_CONFLICT - * - FTDF_REALIGNMENT - * - FTDF_BEACON_LOST (not supported because only beaconless mode is supported) - */ -typedef uint8_t ftdf_loss_reason_t; -#define FTDF_PAN_ID_CONFLICT 1 -#define FTDF_REALIGNMENT 2 -#define FTDF_BEACON_LOST 3 - -typedef uint16_t ftdf_slotframe_size_t; - -/** - * \brief Set operation - * \remark Allowed values: - * - FTDF_ADD: Add an entry - * - FTDF_DELETE: Delete an entry - * - FTDF_MODIFY: Modify an entry - */ -typedef uint8_t ftdf_operation_t; -#define FTDF_ADD 0 -#define FTDF_DELETE 2 -#define FTDF_MODIFY 3 - -typedef uint16_t ftdf_timeslot_t; - -/** - * \brief Set operation - * \remark Allowed values: - * - FTDF_NORMAL_LINK - * - FTDF_ADVERTISING_LINK - */ -typedef uint8_t ftdf_link_type_t; -#define FTDF_NORMAL_LINK 0 -#define FTDF_ADVERTISING_LINK 1 - -/** - * \brief TSCH mode status - * \remark Allowed values: - * - FTDF_TSCH_OFF - * - FTDF_TSCH_ON - */ -typedef uint8_t ftdf_tsch_mode_t; -#define FTDF_TSCH_OFF 0 -#define FTDF_TSCH_ON 1 - -typedef uint16_t ftdf_keep_alive_period_t; - -/** - * \brief BE exponent - */ -typedef uint8_t ftdf_be_exponent_t; - -#define FTDF_MAX_SLOTFRAMES 4 - -typedef struct { - /** \brief Handle of this slotframe */ - ftdf_handle_t slotframe_handle; - /** \brief The number of timeslots in this slotframe */ - ftdf_slotframe_size_t slotframe_size; -} ftdf_slotframe_entry_t; - -typedef struct { - /** \brief Number of slotframes in the slotframe table */ - ftdf_size_t nr_of_slotframes; - /** \brief Pointer to the first slotframe entry */ - ftdf_slotframe_entry_t* slotframe_entries; -} ftdf_slotframe_table_t; - -#define FTDF_MAX_LINKS 16 - -#define FTDF_LINK_OPTION_TRANSMIT 0x01 -#define FTDF_LINK_OPTION_RECEIVE 0x02 -#define FTDF_LINK_OPTION_SHARED 0x04 -#define FTDF_LINK_OPTION_TIME_KEEPING 0x08 - -typedef struct { - /** \brief Handle of this link, used for delete and modify operations */ - ftdf_handle_t link_handle; - /** - * \brief Bit mapped link options, the following options are supported:
- * FTDF_LINK_OPTION_TRANSMIT: Lik can be used for transmitting
- * FTDF_LINK_OPTION_RECEIVE: Link can be used for receiving
- * FTDF_LINK_OPTION_SHARED: Shared link, multiple device can transmit in this link
- * FTDF_LINK_OPTION_TIME_KEEPING: Link will be used to synchronise timeslots
- * Multiple options can be defined by or-ing them. - */ - ftdf_bitmap8_t link_options; - /** \brief Link type */ - ftdf_link_type_t link_type; - /** \brief Handle of the slotframe of this link */ - ftdf_handle_t slotframe_handle; - /** \brief Short address of the peer node, only valid if is a transmit link */ - ftdf_short_address_t node_address; - /** \brief Timeslot in the slotframe */ - ftdf_timeslot_t timeslot; - /** \brief Channel offset */ - ftdf_channel_offset_t channel_offset; - /** \brief DO NOT USE */ - void* __private1; - /** \brief DO NOT USE */ - uint64_t __private2; -} ftdf_link_entry_t; - -typedef struct { - /** \brief Number of links in the link table */ - ftdf_size_t nr_of_links; - /** \brief Pointer to the first link entry */ - ftdf_link_entry_t* link_entries; -} FTDF_LinkTable; - -typedef struct { - ftdf_handle_t timeslot_template_id; - ftdf_period_t ts_cca_offset; - ftdf_period_t ts_cca; - ftdf_period_t ts_tx_offset; - ftdf_period_t ts_rx_offset; - ftdf_period_t ts_rx_ack_delay; - ftdf_period_t ts_tx_ack_delay; - ftdf_period_t ts_rx_wait; - ftdf_period_t ts_ack_wait; - ftdf_period_t ts_rx_tx; - ftdf_period_t ts_max_ack; - ftdf_period_t ts_max_ts; - ftdf_period_t ts_timeslot_length; -} ftdf_timeslot_template_t; - -typedef struct { - ftdf_size_t counter_octets; - ftdf_count_t retry_count; - ftdf_count_t multiple_retry_count; - ftdf_count_t tx_fail_count; - ftdf_count_t tx_success_count; - ftdf_count_t fcs_error_count; - ftdf_count_t security_failure_count; - ftdf_count_t duplicate_frame_count; - ftdf_count_t rx_success_count; - ftdf_count_t nack_count; - ftdf_count_t rx_expired_count; - ftdf_count_t bo_irq_count; -} ftdf_performance_metrics_t; - -typedef struct { - ftdf_count_t tx_data_frm_cnt; - ftdf_count_t tx_cmd_frm_cnt; - ftdf_count_t tx_std_ack_frm_cnt; - ftdf_count_t tx_enh_ack_frm_cnt; - ftdf_count_t tx_ceacon_frm_cnt; - ftdf_count_t tx_multi_purp_frm_cnt; - ftdf_count_t rx_data_frm_ok_cnt; - ftdf_count_t rx_cmd_frm_ok_cnt; - ftdf_count_t rx_std_ack_frm_ok_cnt; - ftdf_count_t rx_enh_ack_frm_ok_cnt; - ftdf_count_t rx_beacon_frm_ok_cnt; - ftdf_count_t rx_multi_purp_frm_ok_cnt; -} ftdf_traffic_counters_t; - -typedef uint8_t ftdf_energy_t; - -typedef struct { - /** \brief Coordinator address mode */ - ftdf_address_mode_t coord_addr_mode; - /** \brief Coordinator PAN id */ - ftdf_pan_id_t coord_pan_id; - /** \brief Coordinator address */ - ftdf_address_t coord_addr; - /** \brief Channel number */ - ftdf_channel_number_t channel_number; - /** \brief Channnel page */ - ftdf_channel_page_t channel_page; - /** \brief NOT USED */ - ftdf_bitmap16_t superframe_spec; - /** \brief NOT USED */ - ftdf_boolean_t gts_permit; - /** \brief Link quality */ - ftdf_link_quality_t link_quality; - /** \brief */ - ftdf_time_t timestamp; -} ftdf_pan_descriptor_t; - -typedef struct { - /** \brief Coordinator PAN id */ - ftdf_pan_id_t coord_pan_id; - /** \brief Coordinator short address */ - ftdf_short_address_t coord_short_addr; - /** \brief Channel number */ - ftdf_channel_number_t channel_number; - /** \brief Device short address */ - ftdf_short_address_t short_addr; - /** \brief Channnel page */ - ftdf_channel_page_t channel_page; -} ftdf_coord_realign_descriptor_t; - -/** - * \brief Auto frame source address mode - * \remark Valid values: - * - FTDF_AUTO_NONE: No address - * - FTDF_AUTO_SHORT: Short address - * - FTDF_AUTO_FULL: Extended address - */ -typedef uint8_t ftdf_auto_sa_t; -#define FTDF_AUTO_NONE 1 -#define FTDF_AUTO_SHORT 2 -#define FTDF_AUTO_FULL 3 - -/** - * \brief TX Power tolerance - * \remark Valid values: - * - FTDF_POWER_TOLERANCE_1_DB - * - FTDF_POWER_TOLERANCE_3_DB - * - FTDF_POWER_TOLERANCE_6_DB - */ -typedef uint8_t ftdf_tx_power_tolerance_t; -#define FTDF_POWER_TOLERANCE_1_DB 1 -#define FTDF_POWER_TOLERANCE_3_DB 2 -#define FTDF_POWER_TOLERANCE_6_DB 3 - -/** - * \brief CCA mode - * \remark Valid values: - * - FTDF_CCA_MODE_1 - * - FTDF_CCA_MODE_2 - * - FTDF_CCA_MODE_3 - */ -typedef uint8_t ftdf_cca_mode_t; -#define FTDF_CCA_MODE_1 1 -#define FTDF_CCA_MODE_2 2 -#define FTDF_CCA_MODE_3 3 - -/** - * \brief Frame control options - * \remark Supported options: - * - FTDF_PAN_ID_PRESENT: Controls the PAN id compression/present bit in multipurpose and - version 2 frames - * - FTDF_IES_INCLUDED: Indicates that ie must be included - * - FTDF_SEQ_NR_SUPPRESSED: Controls suppression of the sequence number - * \remark Multiple options can specified by bit wise or-ing them - */ -typedef uint8_t ftdf_frame_control_options_t; -#define FTDF_PAN_ID_PRESENT 0x01 -#define FTDF_IES_INCLUDED 0x02 -#define FTDF_SEQ_NR_SUPPRESSED 0x04 - -typedef struct { - ftdf_channel_page_t channel_page; - ftdf_size_t nr_of_channels; - ftdf_channel_number_t* channels; -} ftdf_channel_descriptor_t; - -typedef struct { - ftdf_size_t nr_of_channel_descriptors; - ftdf_channel_descriptor_t* channel_descriptors; -} ftdf_channel_descriptor_list_t; - -/** - * \brief Dbm data type - */ -typedef int8_t ftdf_dbm; - -typedef uint8_t ftdf_frame_type_t; -#define FTDF_BEACON_FRAME 0 -#define FTDF_DATA_FRAME 1 -#define FTDF_ACKNOWLEDGEMENT_FRAME 2 -#define FTDF_MAC_COMMAND_FRAME 3 -#define FTDF_LLDN_FRAME 4 -#define FTDF_MULTIPURPOSE_FRAME 5 - -/** - * \brief Command frame id - * \remark Supported command frame IDs: - * - FTDF_COMMAND_ASSOCIATION_REQUEST - * - FTDF_COMMAND_ASSOCIATION_RESPONSE - * - FTDF_COMMAND_DISASSOCIATION_NOTIFICATION - * - FTDF_COMMAND_DATA_REQUEST - * - FTDF_COMMAND_PAN_ID_CONFLICT_NOTIFICATION - * - FTDF_COMMAND_ORPHAN_NOTIFICATION - * - FTDF_COMMAND_BEACON_REQUEST - * - FTDF_COMMAND_COORDINATOR_REALIGNMENT - * - FTDF_COMMAND_GTS_REQUEST - */ -typedef uint8_t ftdf_command_frame_id_t; -#define FTDF_COMMAND_ASSOCIATION_REQUEST 1 -#define FTDF_COMMAND_ASSOCIATION_RESPONSE 2 -#define FTDF_COMMAND_DISASSOCIATION_NOTIFICATION 3 -#define FTDF_COMMAND_DATA_REQUEST 4 -#define FTDF_COMMAND_PAN_ID_CONFLICT_NOTIFICATION 5 -#define FTDF_COMMAND_ORPHAN_NOTIFICATION 6 -#define FTDF_COMMAND_BEACON_REQUEST 7 -#define FTDF_COMMAND_COORDINATOR_REALIGNMENT 8 -#define FTDF_COMMAND_GTS_REQUEST 9 - -/** - * \brief Security frame counter - * \remark Valid range 0..0xffffffff (4 octets) if frame counter mode equals 4 - * \remark Valid range 0..0xffffffffff (5 octets) if frame counter mode equals 5 - */ -typedef uint64_t ftdf_frame_counter_t; - -/** - * \brief Security frame counter mode - * \remark Valid range 4..5 - */ -typedef uint8_t ftdf_frame_counter_mode_t; - -typedef struct { - ftdf_key_id_mode_t key_id_mode; - ftdf_octet_t key_source[8]; - ftdf_key_index_t key_index; - ftdf_address_mode_t device_addr_mode; - ftdf_pan_id_t device_pan_id; - ftdf_address_t device_address; -} ftdf_key_id_lookup_descriptor_t; - -typedef struct { - ftdf_pan_id_t pan_id; - ftdf_short_address_t short_address; - ftdf_ext_address_t ext_address; - ftdf_frame_counter_t frame_counter; - ftdf_boolean_t exempt; -} ftdf_device_descriptor_t; - -/** - * \brief Device descriptor handle - * \remark This is the index of a device in \link ftdf_device_table_t \endlink - */ -typedef uint8_t ftdf_device_descriptor_handle_t; - -typedef struct { - /** \brief Frame type */ - ftdf_frame_type_t frame_type; - /** \brief Command frame id */ - ftdf_command_frame_id_t command_frame_id; -} ftdf_key_usage_descriptor_t; - -typedef struct { - ftdf_size_t nr_of_key_id_lookup_descriptors; - ftdf_key_id_lookup_descriptor_t *key_id_lookup_descriptors; - ftdf_size_t nr_of_device_descriptor_handles; - ftdf_device_descriptor_handle_t *device_descriptor_handles; - ftdf_size_t nr_of_key_usage_descriptors; - ftdf_key_usage_descriptor_t *key_usage_descriptors; - ftdf_octet_t key[16]; -} ftdf_key_descriptor_t; - -typedef struct { - ftdf_frame_type_t frame_type; - ftdf_command_frame_id_t command_frame_id; - ftdf_security_level_t security_minimum; - ftdf_boolean_t device_override_security_minimum; - ftdf_bitmap8_t allowed_security_levels; -} ftdf_security_level_descriptor_t; - -/** - * \brief Key table - * \remark As followes an example how to initialize a key table for usage with FTDF_SET_REQUEST: - * \code - * ftdf_key_id_lookup_descriptor_t lookupDescriptorsKey1[] = - * { { 2, { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef }, 7, 0, 0 0 }, - * { 0, { 0, 0, 0, 0, 0, 0, 0, 0 }, 0, 2, 0x1234, 0x0001 } }; - * ftdf_key_id_lookup_descriptor_t lookupDescriptorsKey2[] = - * { { 1, { 0, 0, 0, 0, 0, 0, 0, 0 }, 5, 0, 0, 0 } }; - * ftdf_device_descriptor_handle_t deviceDescriptorHandlesKey1[] = { 0, 2 }; - * ftdf_device_descriptor_handle_t deviceDescriptorHandlesKey2[] = { 1 }; - * ftdf_key_usage_descriptor_t keyUsageDescriptorKey1[] = { { 1, 0 }, { 3, 4 } }; - * ftdf_key_usage_descriptor_t keyUsageDescriptorKey2[] = { { 1, 0 } }; - * ftdf_key_descriptor_t key_descriptors[] = - * { { sizeof(lookupDescriptorsKey1) / sizeof(ftdf_key_id_lookup_descriptor_t), - * lookupDescriptorsKey1, - * sizeof(deviceDescriptorHandlesKey1) / sizeof(ftdf_device_descriptor_handle_t), - * deviceDescriptorHandlesKey1, - * sizeof(keyUsageDescriptorKey1) / sizeof(ftdf_key_usage_descriptor_t), - * keyUsageDescriptorKey1, - * { 0x7e, 0x37, 0x2d, 0x41, 0xdf, 0x74, 0x72, 0x3f, 0x4c, 0x3a, 0xa7, 0x53, 0xa1, 0x11, 0x46, 0x8b } }, - * { sizeof(lookupDescriptorsKey2) / sizeof(ftdf_key_id_lookup_descriptor_t), - * lookupDescriptorsKey2, - * sizeof(deviceDescriptorHandlesKey2) / sizeof(ftdf_device_descriptor_handle_t), - * deviceDescriptorHandlesKey2, - * sizeof(keyUsageDescriptorKey2) / sizeof(ftdf_key_usage_descriptor_t), - * keyUsageDescriptorKey1, - * { 0xdf, 0x74, 0x72, 0x3f, 0x7e, 0x37, 0x2d, 0x41, 0x4c, 0x3a, 0xa1, 0x11, 0x46, 0x8, 0xa7, 0x53b } } }; - * ftdf_key_table_t keyTable = - * { sizeof(key_descriptors) / sizeof(ftdf_key_descriptor_t), key_descriptors }; - * \endcode - */ -typedef struct { - /** \brief Number of key descriptors in the key table */ - ftdf_size_t nr_of_key_descriptors; - /** \brief Pointer to the first key descriptor entry */ - ftdf_key_descriptor_t *key_descriptors; -} ftdf_key_table_t; - -typedef struct { - /** \brief Number of device descriptors in the key table */ - ftdf_size_t nr_of_device_descriptors; - /** \brief Pointer to the first device descriptor entry */ - ftdf_device_descriptor_t *device_descriptors; -} ftdf_device_table_t; - -typedef struct { - /** \brief Number of security level descriptors in the key table */ - ftdf_size_t nr_of_security_level_descriptors; - /** \brief Pointer to the first security level descriptor entry */ - ftdf_security_level_descriptor_t *security_level_descriptors; -} ftdf_security_level_table_t; - -/** - * \brief IE type - * \remark Supported IE types: - * - FTDF_SHORT_IE - * - FTDF_LONG_IE - */ -typedef uint8_t ftdf_ie_type_t; -#define FTDF_SHORT_IE 0 -#define FTDF_LONG_IE 1 - -typedef uint8_t ftdf_ie_id_t; - -typedef uint8_t ftdf_ie_length_t; - -typedef struct { - /** \brief IE type */ - ftdf_ie_type_t type; - /** \brief Sub IE id*/ - ftdf_ie_id_t sub_id; - /** \brief Sub IE length */ - ftdf_ie_length_t length; - /** \brief Pointer to sub IE content */ - ftdf_octet_t *sub_content; -} ftdf_sub_ie_descriptor_t; - -typedef struct { - /** \brief Number of sub IE descriptors in an MLME payload IE (id = 1) */ - ftdf_size_t nr_of_sub_ie; - /** \brief Pointer to the first sub IE descriptor */ - ftdf_sub_ie_descriptor_t *sub_ie; -} ftdf_sub_ie_list_t; - -typedef union { - /** \brief IE content if not a MLME payload IE (id = 1) */ - ftdf_octet_t *raw; - /** \brief IE content if a MLME payload IE (id = 1) */ - ftdf_sub_ie_list_t *nested; -} ftdf_ie_content_t; - -typedef struct { - /** \brief IE id */ - ftdf_ie_id_t id; - /** \brief Content length of the IE, undefined/unused in case of a MLME payload IE (id = 1) */ - ftdf_ie_length_t length; - /** \brief Content of the IE */ - ftdf_ie_content_t content; -} ftdf_ie_descriptor_t; - -typedef struct { - /** \brief Number of IE descriptors */ - ftdf_size_t nr_of_ie; - /** \brief Pointer to the first IE descriptor */ - ftdf_ie_descriptor_t *ie; -} ftdf_ie_list_t; - -typedef struct { - /** \brief Message id */ - ftdf_msg_id_t msg_id; -} ftdf_msg_buffer_t; - -typedef struct { - /** \brief Message id = FTDF_DATA_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Source address mode */ - ftdf_address_mode_t src_addr_mode; - /** \brief Destination address mode */ - ftdf_address_mode_t dst_addr_mode; - /** \brief Destination PAN id */ - ftdf_pan_id_t dst_pan_id; - /** \brief Destination address */ - ftdf_address_t dst_addr; - /** \brief Length of MSDU payload */ - ftdf_data_length_t msdu_length; - /** - * \brief MSDU payload data buffer. Must be freed by the application using FTDF_REL_DATA_BUFFER - * when it receives the FTDF_DATA_CONFIRM message - */ - ftdf_octet_t *msdu; - /** \brief Handle */ - ftdf_handle_t msdu_handle; - /** \brief Whether the data frame needs to be acknowledged or */ - ftdf_boolean_t ack_tx; - /** \brief NOT USED */ - ftdf_boolean_t gts_tx; - /** - * \brief Indication whether the frame must be send directly or be queued until a - * DATA_REQUEST COMMAND frame is received - */ - ftdf_boolean_t indirect_tx; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; - /** \brief Frame control option bitmap */ - ftdf_frame_control_options_t frame_control_options; - /** - * \brief Header IE list to be inserted. - * Ignored if the FTDF_IES_INCLUDED frame control option is NOT set. - * The IE list must be located in rentention RAM - */ - ftdf_ie_list_t *header_ie_list; - /** - * \brief Payload IE list to be inserted. - * Ignored if the FTDF_IES_INCLUDED frame control option is NOT set. - * The IE list must be located in rentention RAM - */ - ftdf_ie_list_t *payload_ie_list; - /** Indication whether a DATA or MULTIPURPOSE frame must be set */ - ftdf_boolean_t send_multi_purpose; - /** \brief DO NOT USE */ - uint8_t __private3; -} ftdf_data_request_t; - -typedef struct { - /** \brief Message id = FTDF_DATA_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief Source address mode */ - ftdf_address_mode_t src_addr_mode; - /** \brief Source PAN id */ - ftdf_pan_id_t src_pan_id; - /** \brief Source address */ - ftdf_address_t src_addr; - /** \brief Destination address mode */ - ftdf_address_mode_t dst_addr_mode; - /** \brief Destination PAN id */ - ftdf_pan_id_t dst_pan_id; - /** \brief Destination address */ - ftdf_address_t dst_addr; - /** \brief Length of MSDU payload */ - ftdf_data_length_t msdu_length; - /** \brief MSDU payload data buffer Must be freed by the application using FTDF_REL_DATA_BUFFER */ - ftdf_octet_t *msdu; - /** \brief MPDU link quality */ - ftdf_link_quality_t mpdu_link_quality; - /** \brief Data sequence number */ - ftdf_sn_t dsn; - /** \brief Timestamp of the time the frame was received */ - ftdf_time_t timestamp; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; - /** /brief Payload IE list
- * The whole payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocated in one data buffer that must be freed by the application using - * FTDF_REL_DATA_BUFFER - * with the ie_list pointer as parameter - */ - ftdf_ie_list_t *payload_ie_list; -} ftdf_data_indication_t; - -typedef struct { - /** \brief Message id = FTDF_DATA_CONFIRM */ - ftdf_msg_id_t msg_id; - /** /brief The handle given by the application in the correspoding FTDF_DATA_REQUEST */ - ftdf_handle_t msdu_handle; - /** /brief Timestmap of the time the frame has been sent */ - ftdf_time_t timestamp; - /** /brief Status of the data request */ - ftdf_status_t status; - /** /brief Number of backoffs, undefined in case status not equal to FTDF_SUCCESS or TSCH enabled */ - ftdf_num_of_backoffs_t num_of_backoffs; - /** /brief Data sequence number of the sent frame */ - ftdf_sn_t dsn; - /** /brief Acknowledgement payload IE list
- * The whole payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocated in one data buffer that must be freed by the application using - * FTDF_REL_DATA_BUFFER with the ie_list pointer as parameter - */ - ftdf_ie_list_t *ack_payload; -} ftdf_data_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_PURGE_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Handle the data request to be purged */ - ftdf_handle_t msdu_handle; -} ftdf_purge_request_t; - -typedef struct { - /** \brief Message id = FTDF_PURGE_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Handle of the purged data request */ - ftdf_handle_t msdu_handle; - /** /brief Status of the purge request */ - ftdf_status_t status; -} ftdf_purge_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_ASSOCIATE_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Channel number to be used for the associate request. Ignored in TSCH mode */ - ftdf_channel_number_t channel_number; - /** \brief Channel page to be used for the associate request. Ignored in TSCH mode */ - ftdf_channel_page_t channel_page; - /** \brief Coordinator address mode */ - ftdf_address_mode_t coord_addr_mode; - /** \brief Coordinator PAN id */ - ftdf_pan_id_t coord_pan_id; - /** \brief Coordinator address */ - ftdf_address_t coord_addr; - /** - * \brief Capabillity information bitmap. The following capabilities are defined:
- * FTDF_CAPABILITY_IS_FFD: Device is a full function device
- * FTDF_CAPABILITY_AC_POWER: Device has AC power
- * FTDF_CAPABILITY_RECEIVER_ON_WHEN_IDLE: Device receiver is on when idle
- * FTDF_CAPABILITY_FAST_ASSOCIATION: Device wants a fast association
- * FTDF_CAPABILITY_SUPPORTS_SECURITY: Device supports security
- * FTDF_CAPABILITY_WANTS_SHORT_ADDRESS: Device wants short address
- */ - ftdf_bitmap8_t capability_information; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; - /** \brief NOT USED */ - ftdf_channel_offset_t channel_offset; - /** \brief NOT USED */ - ftdf_hopping_sequence_id_t hopping_sequence_id; - /** \brief DO NOT USE */ - uint8_t __private3; -} ftdf_associate_request_t; - -typedef struct { - /** \brief Message id = FTDF_ASSOCIATE_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief Extended address of the device that did the association request */ - ftdf_ext_address_t device_address; - /** - * \brief Capabillity information bitmap. The following capabilities are defined:
- * FTDF_CAPABILITY_IS_FFD: Device is a full function device
- * FTDF_CAPABILITY_AC_POWER: Device has AC power
- * FTDF_CAPABILITY_RECEIVER_ON_WHEN_IDLE: Device receiver is on when idle
- * FTDF_CAPABILITY_FAST_ASSOCIATION: Device wants a fast association
- * FTDF_CAPABILITY_SUPPORTS_SECURITY: Device supports security
- * FTDF_CAPABILITY_WANTS_SHORT_ADDRESS: Device wants short address
- */ - ftdf_bitmap8_t capability_information; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; - /** \brief NOT USED */ - ftdf_channel_offset_t channel_offset; - /** \brief NOT USED */ - ftdf_hopping_sequence_id_t hopping_sequence_id; -} ftdf_associate_indication_t; - -typedef struct { - /** \brief Message id = FTDF_ASSOCIATE_RESPONSE */ - ftdf_msg_id_t msg_id; - /** \brief Extended address of the device that did association request and to which the response needs to be send */ - ftdf_ext_address_t device_address; - /** \brief The short address for the device that did the associate request */ - ftdf_short_address_t assoc_short_address; - /** \brief The association status of the associate request */ - ftdf_association_status_t status; - /** \brief Indication whether this a response to fast or normal association request */ - ftdf_boolean_t fast_a; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; - /** \brief NOT USED */ - ftdf_channel_offset_t channel_offset; - /** \brief NOT USED */ - ftdf_length_t hopping_sequence_length; - /** \brief NOT USED */ - ftdf_octet_t* hopping_sequence; - /** \brief DO NOT USE */ - uint8_t __private3; -} ftdf_associate_response_t; - -typedef struct { - /** \brief Message id = FTDF_ASSOCIATE_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief The short adddress assigned by the coordinator */ - ftdf_short_address_t assoc_short_address; - /** \brief Status of the associate request */ - ftdf_status_t status; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; - /** \brief NOT USED */ - ftdf_channel_offset_t channel_offset; - /** \brief NOT USED */ - ftdf_length_t hopping_sequence_length; - /** \brief NOT USED */ - ftdf_octet_t *hopping_sequence; -} ftdf_associate_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_DISASSOCIATE_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Device address mode */ - ftdf_address_mode_t device_addr_mode; - /** \brief Device PAN id */ - ftdf_pan_id_t device_pan_id; - /** \brief Device address */ - ftdf_address_t device_address; - /** \brief Disassociate reason */ - ftdf_disassociate_reason_t disassociate_reason; - /** - * \brief Indication whether the disassociate request must be send directly or be queued until a - * DATA_REQUEST command frame is received - */ - ftdf_boolean_t tx_indirect; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; - /** \brief DO NOT USE */ - uint8_t __private3; -} ftdf_disassociate_request_t; - -typedef struct { - /** \brief Message id = FTDF_DISASSOCIATE_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief Extended address of the device that did disassociate request */ - ftdf_ext_address_t device_address; - /** \brief Disassociate reason */ - ftdf_disassociate_reason_t disassociate_reason; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; -} ftdf_disassociate_indication_t; - -typedef struct { - /** \brief Message id = FTDF_DISASSOCIATE_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Disassociate request status */ - ftdf_status_t status; - /** \brief Address mode of the device that want/must disassociate */ - ftdf_address_mode_t device_addr_mode; - /** \brief PAN id of the device that want/must disassociate */ - ftdf_pan_id_t device_pan_id; - /** \brief address of the device that want/must disassociate */ - ftdf_address_t device_address; -} ftdf_disassociate_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_BEACON_NOTIFY_INDCATION */ - ftdf_msg_id_t msg_id; - /** \brief Beacon sequence number, valid only when beacon type is FTDF_NORMAL_BEACON */ - ftdf_sn_t bsn; - /** \brief PAN descriptor*/ - ftdf_pan_descriptor_t *pan_descriptor; - /** \brief NOT USED */ - ftdf_bitmap8_t pend_addr_spec; - /** \brief NOT USED */ - ftdf_address_t *addr_list; - /** \brief Length of the beacon payload */ - ftdf_data_length_t sdu_length; - /** \brief Beacon payload */ - ftdf_octet_t *sdu; - /** \brief Enhanced beacon sequence number, valid only when beacon type is FTDF_ENHANCED_BEACON */ - ftdf_sn_t eb_sn; - /** \brief Beacon type */ - ftdf_beacon_type_t beacon_type; - /** - * \brief Payload IE list
- * The whole Payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocate in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER - * with the ie_list pointer as parameter. - */ - ftdf_ie_list_t *ie_list; - /** - * \brief Timestamp of the time the beacon frame was received
- * In TSCH mode this timestamp should be used to calculate the TSCH timeslot start time - * required in a FTDF_TSCH_MODE_REQUEST message - */ - ftdf_time64_t timestamp; -} ftdf_beacon_notify_indication_t; - -typedef struct { - /** \brief Message id = FTDF_COMM_STATUS_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief PAN id of the frame causing the error */ - ftdf_pan_id_t pan_id; - /** \brief Source address mode of the frame causing the error */ - ftdf_address_mode_t src_addr_mode; - /** \brief Source address of the frame causing the error */ - ftdf_address_t src_addr; - /** \brief Destination address mode of the frame causing the error */ - ftdf_address_mode_t dst_addr_mode; - /** \brief Destination address of the frame causing the error */ - ftdf_address_t dst_addr; - /** \brief Error status */ - ftdf_status_t status; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; -} ftdf_comm_status_indication_t; - -typedef struct { - /** \brief Message id = FTDF_GET_REQUEST */ - ftdf_msg_id_t msg_id; - ftdf_pib_attribute_t pib_attribute; -} ftdf_get_request_t; - -typedef struct { - /** \brief Message id = FTDF_GET_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the get request */ - ftdf_status_t status; - /** \brief PIB attribute id of PIB attribute gotten */ - ftdf_pib_attribute_t pib_attribute; - /** - * \brief Pointer to the PIB attribute value to be set
- * Each PIB attribute has its own type, see \link ftdf_pib_attribute_t \endlink
- * In order to access the attribute value the application must cast this pinter - * to the correct type. - */ - const ftdf_pib_attribute_value_t *pib_attribute_value; -} ftdf_get_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_SET_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief PIB attribute id of attribute to be set */ - ftdf_pib_attribute_t pib_attribute; - /** - * \brief Pointer to the PIB attribute value to be set
- * Each PIB attribute has its own type, see \link ftdf_pib_attribute_t \endlink
- * FTDF does a shallow copy of the PIB attribute. So if the PIB attribute contains pointers to - * other data this data is NOT copied by FTDF. The application must make sure that data referred - * from a PIB attribute is statically allocated in retention RAM. - */ - const ftdf_pib_attribute_value_t *pib_attribute_value; -} ftdf_set_request_t; - -typedef struct { - /** \brief Message id = FTDF_GET_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Set request status */ - ftdf_status_t status; - /** \brief PIB Attribute id of PIB attribute that has been set */ - ftdf_pib_attribute_t pib_attribute; -} ftdf_set_confirm_t; - -typedef struct { - ftdf_msg_id_t msg_id; - ftdf_gts_charateristics_t gts_charateristics; - ftdf_security_level_t security_level; - ftdf_key_id_mode_t key_id_mode; - ftdf_octet_t key_source[8]; - ftdf_key_index_t key_index; -} ftdf_gts_request_t; - -typedef struct { - ftdf_msg_id_t msg_id; - ftdf_gts_charateristics_t gts_charateristics; - ftdf_status_t status; -} ftdf_gts_confirm_t; - -typedef struct { - ftdf_msg_id_t msg_id; - ftdf_short_address_t device_address; - ftdf_gts_charateristics_t gts_charateristics; - ftdf_security_level_t security_level; - ftdf_key_id_mode_t key_id_mode; - ftdf_octet_t key_source[8]; - ftdf_key_index_t key_index; -} ftdf_gts_indication_t; - -typedef struct { - /** \brief Message id = FTDF_ORPHAN_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief Extended address of orphaned device */ - ftdf_ext_address_t orphan_address; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; -} ftdf_orphan_indication_t; - -typedef struct { - /** \brief Message id = FTDF_ORPHAN_RESPONSE */ - ftdf_msg_id_t msg_id; - /** \brief Extended address of orphaned device */ - ftdf_ext_address_t orphan_address; - /** \brief Short address of orphaned device */ - ftdf_short_address_t short_address; - /** \brief Indication whether the device is associated with this coordinator or not */ - ftdf_boolean_t associated_member; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; -} ftdf_orphan_response_t; - -typedef struct { - /** \brief Message id = FTDF_RESET_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Indication whether the PIB attributes must be reset to their default values or not */ - ftdf_boolean_t set_default_pib; -} ftdf_reset_request_t; - -typedef struct { - /** \brief Message id = FTDF_RESET_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the reset request */ - ftdf_status_t status; -} ftdf_reset_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_RX_ENABLE_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief NOT USED */ - ftdf_boolean_t defer_permit; - /** \brief NOT USED */ - ftdf_time_t rx_on_time; - /** \brief The time in aBaseSuperFramePeriod's (960 symbols) that the receiver will be on */ - ftdf_time_t rx_on_duration; -} ftdf_rx_enable_request_t; - -typedef struct { - /** \brief Message id = FTDF_RX_ENABLE_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the RX enable request */ - ftdf_status_t status; -} ftdf_rx_enable_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_SCAN_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Scan Type */ - ftdf_scan_type_t scan_type; - /** \brief Bitmap of the channels to be scanned (only channel 11 - 27 are supported) */ - ftdf_bitmap32_t scan_channels; - /** \brief Channel page of the channels to be scanned (only page 0 is supported) */ - ftdf_channel_page_t channel_page; - /** \brief Scan duration per channel, duration = ((scan_duration ^ 2) - 1) * aBaseSuperFramePeriod symbols */ - ftdf_scan_duration_t scan_duration; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; -} ftdf_scan_request_t; - -typedef struct { - /** \brief Message id = FTDF_SCAN_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the scan request */ - ftdf_status_t status; - /** \brief Scan Type */ - ftdf_scan_type_t scan_type; - /** \brief Channel page of the scanned channels */ - ftdf_channel_page_t channel_page; - /** \brief Bitmap of the channels not scanned but were requested to be scanned */ - ftdf_bitmap32_t unscanned_channels; - /** \brief Number of entries in energy_detect_list or pan_descriptor_list */ - ftdf_size_t result_list_size; - /** \brief Pointer to the first energy detect result */ - ftdf_energy_t *energy_detect_list; - /** \brief Pointer to the first PAN descriptor */ - ftdf_pan_descriptor_t *pan_descriptor_list; - /** \brief */ - ftdf_coord_realign_descriptor_t *coord_realign_descriptor; -} ftdf_scan_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_START_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief PAN id that will be used by the coordinator */ - ftdf_pan_id_t pan_id; - /** \brief Channel number that will be used by the coordinator */ - ftdf_channel_number_t channel_number; - /** \brief Channel page that will be used by the coordinator */ - ftdf_channel_page_t channel_page; - /** \brief NOT USED */ - ftdf_time_t start_time; - /** \brief Beacon order, only beacon order 15 (beaconless) is supported */ - ftdf_order_t beacon_order; - /** \brief NOT USED */ - ftdf_order_t superframe_order; - /** \brief Indication whether the device must be a coordinator or a PAN coordinator */ - ftdf_boolean_t pan_coordinator; - /** \brief NOT USED */ - ftdf_boolean_t battery_life_extension; - /** \brief NOT USED */ - ftdf_boolean_t coord_realignment; - /** \brief NOT USED */ - ftdf_security_level_t coord_realign_security_level; - /** \brief NOT USED */ - ftdf_key_id_mode_t coord_realign_key_id_mode; - /** \brief NOT USED */ - ftdf_octet_t coord_realign_key_source[8]; - /** \brief NOT USED */ - ftdf_key_index_t coord_realign_key_index; - /** \brief NOT USED */ - ftdf_security_level_t beacon_security_level; - /** \brief NOT USED */ - ftdf_key_id_mode_t beacon_key_id_mode; - /** \brief NOT USED */ - ftdf_octet_t beacon_key_source[8]; - /** \brief NOT USED */ - ftdf_key_index_t beacon_key_index; -} ftdf_start_request_t; - -typedef struct { - /** \brief Message id = FTDF_START_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the start request */ - ftdf_status_t status; -} ftdf_start_confirm_t; - -typedef struct { - ftdf_msg_id_t msg_id; - ftdf_channel_number_t channnel_number; - ftdf_channel_page_t channel_page; - ftdf_boolean_t trackbeacon; -} ftdf_sync_request_t; - -typedef struct { - /** \brief Message id = FTDF_SYNC_LOSS_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief Loss Reason */ - ftdf_loss_reason_t loss_reason; - /** \brief PAN id */ - ftdf_pan_id_t pan_id; - /** \brief Channel number */ - ftdf_channel_number_t channel_number; - /** \brief Channel page */ - ftdf_channel_page_t channel_page; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; -} ftdf_sync_loss_indication_t; - -typedef struct { - /** \brief Message id = FTDF_POLL_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Coordinator address mode */ - ftdf_address_mode_t coord_addr_mode; - /** \brief coordinator PAN id */ - ftdf_pan_id_t coord_pan_id; - /** \brief Coordinator address */ - ftdf_address_t coord_addr; - /** \brief Security level */ - ftdf_security_level_t security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t key_id_mode; - /** \brief Security key source */ - ftdf_octet_t key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t key_index; -} ftdf_poll_request_t; - -typedef struct { - /** \brief Message id = FTDF_POLL_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the poll request */ - ftdf_status_t status; -} ftdf_poll_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_SET_SLOTFRAME_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Slotframe handle */ - ftdf_handle_t handle; - /** \brief Set operation */ - ftdf_operation_t operation; - /** \brief Number of timeslots in this slotframe */ - ftdf_slotframe_size_t size; -} ftdf_set_slotframe_request_t; - -typedef struct { - /** \brief Message id = FTDF_SET_SLOTFRAME_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Slotframe handle */ - ftdf_handle_t handle; - /** \brief Status of the set sloytframe request */ - ftdf_status_t status; -} ftdf_set_slotframe_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_SET_LINK_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Set operation */ - ftdf_operation_t operation; - /** \brief Handle of this link, used for delete and modify operations */ - ftdf_handle_t link_handle; - /** \brief Handle of the slotframe of this link */ - ftdf_handle_t slotframe_handle; - /** \brief Timeslot in the slotframe */ - ftdf_timeslot_t timeslot; - /** \brief Channel offset */ - ftdf_channel_offset_t channel_offset; - /** - * \brief Bit mapped link options, the following options are supported:
- * FTDF_LINK_OPTION_TRANSMIT: Lik can be used for transmitting
- * FTDF_LINK_OPTION_RECEIVE: Link can be used for receiving
- * FTDF_LINK_OPTION_SHARED: Shared link, multiple device can transmit in this link
- * FTDF_LINK_OPTION_TIME_KEEPING: Link will be used to synchronise timeslots
- * Multiple options can be defined by or-ing them. - */ - ftdf_bitmap8_t link_options; - /** \brief Link type */ - ftdf_link_type_t link_type; - /** \brief Short address of the peer node, only valid if is a transmit link */ - ftdf_short_address_t node_address; -} ftdf_set_link_request_t; - -typedef struct { - /** \brief Message id = FTDF_SET_LINK_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the set link request */ - ftdf_status_t status; - /** \brief Link handle */ - ftdf_handle_t link_handle; - /** \brief Slotframe handle */ - ftdf_handle_t slotframe_handle; -} ftdf_set_link_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_TSCH_MODE_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief The new TSCH mode */ - ftdf_tsch_mode_t tschMode; - /** - * \brief The timestamp in symbols of the start of the timeslot with ASN equal to the PIB attribute - * FTDF_PIB_ASN
- * The timestamp should be calculated from the timestamp of the BEACON_NOTIFY_INDICATION message
- * Before sending the FTDF_TSCH_MODE_REQUEST message the application should set FTDF_PIB_ASN with - * the ASN of the TSCH synchronization IE of the ie_list of the BEACON_NOTIFY_INDICATION message - */ - ftdf_time_t timeslotStartTime; -} ftdf_tsch_mode_request_t; - -typedef struct { - /** \brief Message id = FTDF_TSCH_MODE_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief The new TSCH mode */ - ftdf_tsch_mode_t tschMode; - /** \brief Status of the TSCH mode request */ - ftdf_status_t status; -} ftdf_tsch_mode_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_KEEP_ALIVE_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Short address to which keep alive message should be send */ - ftdf_short_address_t dst_address; - /** \brief */ - ftdf_keep_alive_period_t keep_alive_period; -} ftdf_keep_alive_request_t; - -typedef struct { - /** \brief Message id = FTDF_KEEP_ALIVE_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the keep alive request */ - ftdf_status_t status; -} ftdf_keep_alive_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_BEACON_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Beacon type */ - ftdf_beacon_type_t beacon_type; - /** \brief Channel number at which the beacon must be sent, ignored in TSCH mode */ - ftdf_channel_number_t channel; - /** \brief Channel page, ignored in TSCH mode */ - ftdf_channel_page_t channel_page; - /** \brief NOT USED */ - ftdf_order_t superframe_order; - /** \brief Security level */ - ftdf_security_level_t beacon_security_level; - /** \brief Security key id mode */ - ftdf_key_id_mode_t beacon_key_id_mode; - /** \brief Security key source */ - ftdf_octet_t beacon_key_source[8]; - /** \brief Security key index */ - ftdf_key_index_t beacon_key_index; - /** \brief Beacon destination address mode */ - ftdf_address_mode_t dst_addr_mode; - /** \brief Beacon destination address */ - ftdf_address_t dst_addr; - /** \brief Indication whether the bsn (or eb_sn) in the beacon frame must suppressed */ - ftdf_boolean_t bsn_suppression; - /** \brief DO NOT USE */ - uint8_t __private3; -} ftdf_beacon_request_t; - -typedef struct { - /** \brief Message id = FTDF_BEACON_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Status of the beacon request */ - ftdf_status_t status; -} ftdf_beacon_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_BEACON_REQUEST_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief Beacon type */ - ftdf_beacon_type_t beacon_type; - /** \brief Source address mode */ - ftdf_address_mode_t src_addr_mode; - /** \brief Source address */ - ftdf_address_t src_addr; - /** \brief Source PAN id */ - ftdf_pan_id_t dst_pan_id; - /** - * \brief Payload IE list
- * The whole Payload IE list (including IE descriptors, Sub IE descriptors and content) - * is allocate in one data buffer that must be freed by the application using FTDF_REL_DATA_BUFFER - * with the ie_list pointer as parameter. - */ - ftdf_ie_list_t *ie_list; -} ftdf_beacon_request_indication_t; - -typedef struct { - /** \brief Message id = FTDF_TRANSPARENT_ENABLE_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Enable or disable of transparent mode */ - ftdf_boolean_t enable; - /** \brief Bitmapped transparent options, see ftdf_enable_transparent_mode */ - ftdf_bitmap32_t options; -} ftdf_transparent_enable_request_t; - -typedef struct { - /** \brief Message id = FTDF_TRANSPARENT_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Frame length */ - ftdf_data_length_t frame_length; - /** \brief Pointer to frame, must be allocated with FTDF_GET_DATA_BUFFER */ - ftdf_octet_t *frame; - /** \brief Channel number */ - ftdf_channel_number_t channel; - /** \brief Packet Traffic Information (PTI) used for transmitting the frame. */ - ftdf_pti_t pti; - /** \brief CSMA suppression */ - ftdf_boolean_t cmsa_suppress; - /** \brief Application provided handle, will be returned in the transparent confirm call */ - void *handle; -} ftdf_transparent_request_t; - -typedef struct { - /** \brief Message id = FTDF_TRANSPARENT_CONFIRM */ - ftdf_msg_id_t msg_id; - /** \brief Application provided handle of the corresponding FTDF_SEND_FRAME_TRANSPARENT call */ - void *handle; - /** \brief Bit mapped status */ - ftdf_bitmap32_t status; -} ftdf_transparent_confirm_t; - -typedef struct { - /** \brief Message id = FTDF_TRANSPARENT_INDICATION */ - ftdf_msg_id_t msg_id; - /** \brief Frame length */ - ftdf_data_length_t frame_length; - /** \brief Pointer to frame, must be freed by the application using FTDF_REL_DATA_BUFFER */ - ftdf_octet_t *frame; - /** \brief Bit mapped receive status */ - ftdf_bitmap32_t status; -} ftdf_transparent_indication_t; - -typedef struct { - /** \brief Message id = FTDF_SLEEP_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Sleep time */ - ftdf_usec_t sleep_time; -} ftdf_sleep_request_t; - -#if FTDF_DBG_BUS_ENABLE -typedef struct { - /** \brief Message id = FTDF_DBG_MODE_SET_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief Debug bus mode */ - ftdf_dbg_mode_t dbg_mode; -} ftdf_dbg_mode_set_request_t; -#endif /* FTDF_DBG_BUS_ENABLE */ - -typedef struct -{ - /** \brief Message ID = FTDF_FPPR_MODE_SET_REQUEST */ - ftdf_msg_id_t msg_id; - /** \brief fp bit value to set when src address matches*/ - ftdf_bitmap8_t match_fp; - /** \brief When set, fp_force_value will be applied to fp bit for all src addresses*/ - ftdf_bitmap8_t fp_override; - /** \brief The value will be set to fp bit for all src addresses when fp_override is set*/ - ftdf_bitmap8_t fp_force; -} ftdf_fppr_mode_set_request_t; - -/** - * \brief ftdf_get_release_info - gets the LMAC (FPGA) and UMAC (FTDF SW driver) release info - * \param[out] lmac_rel_name: LMAC release name - * \param[out] lmac_build_time: LMAC build time - * \param[out] umac_rel_name: UMAC release name - * \param[out] umac_build_time: UMAC build time - * \remark Sets the application character strings pointers to character strings containing the release - * info. The character string space is statically allocated by FTDF and does not need - * to be released by the application. - */ -void ftdf_get_release_info(char **lmac_rel_name, char **lmac_build_time, char **umac_rel_name, - char **umac_build_time); - -/** - * \brief ftdf_confirm_lmac_interrupt - Confirmation that the LMAC interrupt has been received - * by the application - * \remark This function disables the LMAC interrupt. The application must wait for any other - * FTDF API function to be completed and call the function ftdf_event_handler. This function - * will enable the LMAC interrupt again the function ftdf_event_handler. - */ -void ftdf_confirm_lmac_interrupt(void); - -/** - * \brief ftdf_event_handler - Handles an event signalled by the LMAC interrupt - * \remark This function handles the event signalled by the LMAC interrupt and enables the LMAC - * interrupt when finished. - * \warning FTDF is strictly NON reentrant, so ftdf_event_handler is NOT allowed to be called when another FTDF - * is being executed - */ -void ftdf_event_handler(void); - -/** - * \brief ftdf_snd_msg - Sends a request (response) message to FTDF driver - * \param[in] msg_buf: The message to be send. To application must set the msg_id field and the request - * specific parameters by casting it to the appropriate request message structure. - * \remark The message must be allocated by the application using the function ftdf_get_msg_buffer - * and will be released by FTDF using ftdf_rel_msg_buffer. When finished FTDF releases the message - * buffer and sends a confirm (indication) to the application using the function ftdf_rcv_msg. - * \remark As follows a table of message IDs accepted by ftdf_snd_msg, the message structure corresponding - * to this message id and the confirm send back to the application when the request has been - * completed by FTDF: - * \remark
- * \remark Request message id, Request structure, Request confirm - * \remark --------------------------------------------------------------------------------- - * \remark FTDF_DATA_REQUEST, ftdf_data_request_t, FTDF_DATA_CONFIRM - * \remark FTDF_PURGE_REQUEST, ftdf_purge_request_t, FTDF_DATA_CONFIRM - * \remark FTDF_ASSOCIATE_REQUEST, ftdf_associate_request_t, FTDF_ASSOCIATE_CONFIRM - * \remark FTDF_ASSOCIATE_RESPONSE, ftdf_associate_response_t, FTDF_COMM_STATUS_INDICATION - * \remark FTDF_DISASSOCIATE_REQUEST, ftdf_disassociate_request_t, FTDF_DISASSOCIATE_CONFIRM - * \remark FTDF_GET_REQUEST, ftdf_get_request_t, FTDF_GET_CONFIRM - * \remark FTDF_SET_REQUEST, ftdf_set_request_t, FTDF_SET_CONFIRM - * \remark FTDF_ORPHAN_RESPONSE, ftdf_orphan_response_t, FTDF_COMM_STATUS_INDICATION - * \remark FTDF_RESET_REQUEST, ftdf_reset_request_t, FTDF_RESET_CONFIRM - * \remark FTDF_RX_ENABLE_REQUEST, ftdf_scan_request_t, FTDF_RX_ENABLE_CONFIRM - * \remark FTDF_SCAN_REQUEST, ftdf_scan_request_t, FTDF_SCAN_CONFIRM - * \remark FTDF_START_REQUEST, ftdf_start_request_t, FTDF_START_CONFIRM - * \remark FTDF_POLL_REQUEST, ftdf_poll_request_t, FTDF_POLL_CONFIRM - * \remark FTDF_SET_SLOTFRAME_REQUEST, ftdf_set_slotframe_request_t, FTDF_SET_SLOTFRAME_CONFIRM - * \remark FTDF_SET_LINK_REQUEST, ftdf_set_link_request_t, FTDF_SET_LINK_CONFIRM - * \remark FTDF_TSCH_MODE_REQUEST, ftdf_tsch_mode_request_t, FTDF_TSCH_MODE_CONFIRM - * \remark FTDF_KEEP_ALIVE_REQUEST, ftdf_keep_alive_request_t, FTDF_KEEP_ALIVE_CONFIRM - * \remark FTDF_BEACON_REQUEST, ftdf_beacon_request_t, FTDF_BEACON_CONFIRM - * \warning FTDF is strictly NON reentrant, so it is NOT allowed to call any other FTDF function before this API has been completed. This including the ftdf_event_handler function. - */ -void ftdf_snd_msg(ftdf_msg_buffer_t *msg_buf); - -/** - * \brief FTDF_RCV_MSG - Receives a confir or indication message from the FTDF driver - * \param[in] msg_buf: The received message. The msg_id field indicates the received message - * \remark This function must be implemented by the application and is called by FTDF to pass - * a confirm or indication message to the application. It must be configured in the - * configuration file ftdf_config.h. - * \remark The message buffer is allocated by FTDF using FTDF_GET_MSG_BUFFER and must be released - * by the application using ftdf_rel_msg_buffer - * \remark As follows a table of the confirm and indications messages and their message structures. - * \remark
- * \remark Confirm/indication message id, Confirm/indication structure - * \remark --------------------------------------------------------------------------------- - * \remark FTDF_DATA_INDICATION, ftdf_data_indication_t - * \remark FTDF_DATA_CONFIRM, ftdf_data_confirm_t - * \remark FTDF_PURGE_CONFIRM, ftdf_purge_confirm_t - * \remark FTDF_ASSOCIATE_INDICATION, ftdf_associate_indication_t - * \remark FTDF_ASSOCIATE_CONFIRM, ftdf_associate_confirm_t - * \remark FTDF_DISASSOCIATE_INDICATION, ftdf_disassociate_indication_t - * \remark FTDF_DISASSOCIATE_CONFIRM,ftdf_disassociate_confirm_t - * \remark FTDF_BEACON_NOTIFY_INDICATION, ftdf_beacon_notify_indication_t - * \remark FTDF_COMM_STATUS_INDICATION, ftdf_comm_status_indication_t - * \remark FTDF_GET_CONFIRM, ftdf_get_confirm_t - * \remark FTDF_SET_CONFIRM, ftdf_set_confirm_t - * \remark FTDF_ORPHAN_INDICATION, ftdf_orphan_indication_t - * \remark FTDF_RESET_CONFIRM, ftdf_reset_confirm_t - * \remark FTDF_RX_ENABLE_CONFIRM, ftdf_rx_enable_confirm_t - * \remark FTDF_SCAN_CONFIRM, ftdf_scan_confirm_t - * \remark FTDF_START_CONFIRM, ftdf_start_confirm_t - * \remark FTDF_SYNC_LOSS_INDICATION, ftdf_sync_loss_indication_t - * \remark FTDF_POLL_CONFIRM, ftdf_poll_confirm_t - * \remark FTDF_SET_SLOTFRAME_CONFIRM, ftdf_set_slotframe_confirm_t - * \remark FTDF_SET_LINK_CONFIRM, ftdf_set_link_confirm_t - * \remark FTDF_TSCH_MODE_CONFIRM, ftdf_tsch_mode_confirm_t - * \remark FTDF_KEEP_ALIVE_CONFIRM, ftdf_keep_alive_confirm_t - * \remark FTDF_BEACON_CONFIRM, ftdf_beacon_confirm_t - * \remark FTDF_BEACON_REQUEST_INDICATION, ftdf_beacon_request_indication_t - * \warning FTDF is strictly NON reentrant. Because ftdf_rcv_msg can be called by ftdf_snd_msg or ftdf_event_handler - * it is not allowed to call other FTDF functions within ftdf_rcv_msg - */ -void FTDF_RCV_MSG(ftdf_msg_buffer_t *msg_buf); - -/** - * \brief FTDF_GET_MSG_BUFFER - Allocates a message buffer - * \param[in] len: The length of the message buffer to be allocated - * \remark This function must be implemented by the application it will called by both the - * application and FTDF. It must be configured in the configuration file ftdf_config.h. - * \remark The allocated message buffer must be freed using ftdf_rel_msg_buffer - * \remark The message buffer must be located in retention RAM - * \return pointer to the allocated message buffer. - */ -ftdf_msg_buffer_t *FTDF_GET_MSG_BUFFER(ftdf_size_t len); - -/** - * \brief FTDF_REL_MSG_BUFFER - Frees a message buffer - * \param[in] msg_buf: Pointer to the message buffer to be released - * \remark This function must be implemented by the application it will called by both the - * application and FTDF. It must be configured in the configuration file ftdf_config.h. - * \remark It will free message buffers allocated with ftdf_get_msg_buffer - */ -void FTDF_REL_MSG_BUFFER(ftdf_msg_buffer_t *msg_buf); - -/** - * \brief FTDF_GET_DATA_BUFFER - Allocates a data buffer - * \param[in] len: The length of the data buffer to be allocated - * \remark This function must be implemented by the application it will called by both the - * application and FTDF. It must be configured in the configuration file ftdf_config.h. - * \remark The allocated data buffer must be freed using FTDF_REL_DATA_BUFFER - * \remark The data buffer must located in retention RAM - * \return pointer to the allocated data buffer. - */ -ftdf_octet_t *FTDF_GET_DATA_BUFFER(ftdf_data_length_t len); - -/** - * \brief FTDF_REL_DATA_BUFFER - Frees a data buffer - * \param[in] data_buf: Pointer to the data buffer to be released - * \remark This function must be implemented by the application it will called by both the - * application and FTDF. It must be configured in the configuration file ftdf_config.h. - * \remark It will free data buffers allocated with FTDF_GET_DATA_BUFFER - */ -void FTDF_REL_DATA_BUFFER(ftdf_octet_t *data_buf); - -/** - * \brief FTDF_GET_EXT_ADDRESS - Gets the extended address - * \remark This function must be implemented by the application it will called by FTDF. It must - * be configured in the configuration file ftdf_config.h. - * \remark After a reset it is used by FTDF to get the extended address of the device - * \return An extended address. - */ -ftdf_ext_address_t FTDF_GET_EXT_ADDRESS(void); - -/** - * \brief ftdf_enable_transparent_mode - Enables or disables the transparent mode - * \param[in] enable: If FTDF_TRUE transparent mode is enabled else it will be disabled - * \param[in] options: A bitmap of transparent mode options. Not used if enable equals to FTDF_FALSE. - * \remark If the transparent mode is enabled received frame are passed to the application using - * FTDF_RCV_FRAME_TRANSPARENT. The whole MAC frame including frame headers, security headers - * and FCS are passed to the application. Depending on the defined options some filtering - * is done. - * \remark When the transparent mode is enabled frames must be send using the function FTDF_SEND_FRAME_TRANSPARENT - * \remark When the transparent mode is enabled only the following request messages are supported: - * \remark
- * \remark FTDF_GET_REQUEST - * \remark FTDF_SET_REQUEST - * \remark FTDF_RESET_REQUEST - * \remark
- * \remark The behavior of FTDF when it receives request not supported in transparent mode is NOT defined! - * \remark
- * \remark Transparent mode cannot be enabled if FTDF is in CSL or TSCH mode. - * \remark
- * \remark The following options are supported: - * \remark
- * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_0: Frames of type 0 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_1: Frames of type 1 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_2: Frames of type 2 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_3: Frames of type 3 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_4: Frames of type 4 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_5: Frames of type 5 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_6: Frames of type 6 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_FRAME_TYPE_7: Frames of type 7 are always passed to the application - * \remark FTDF_TRANSPARENT_PASS_ALL_FRAME_TYPES: All frame types are always passed to the application - * \remark FTDF_TRANSPARENT_AUTO_ACK: FTDF sends an automatically and ACK if it receives an version 0 or 1 - * frame with AR set in the fram control field - * \remark FTDF_TRANSPARENT_AUTO_FP_ACK: FTDF sends an automatically and ACK frame with FP set if it - * receives an version 0 or 1 DATA_REQUEST command frame with AR set in the fram control field - * \remark FTDF_TRANSPARENT_PASS_CRC_ERROR: Frames with a CRC (FCS) error are passed to the application - * \remark FTDF_TRANSPARENT_PASS_ALL_FRAME_VERSION: Frames with any frame version are passed to the - * application - * \remark FTDF_TRANSPARENT_PASS_ALL_PAN_ID: Frames with any PAN id (even when it does not match its own - * PAN id) are passed to the application - * \remark FTDF_TRANSPARENT_PASS_ALL_PAN_ID: Frames with any address (even when it does not match its own - * extended or short address) are passed to the application - * \remark FTDF_TRANSPARENT_PASS_ALL_BEACON: Any beacon frame is passed to the application - * \remark FTDF_TRANSPARENT_PASS_ALL_NO_DEST_ADDR: Frames with no destination address are always passed to - * the application - * \remark FTDF_TRANSPARENT_ENABLE_FCS_GENERATION: FTDF adds an FCS to frames send with FTDF_SEND_FRAME_TRANSPARENT - */ -void ftdf_enable_transparent_mode(ftdf_boolean_t enable, ftdf_bitmap32_t options); - -/** - * \brief ftdf_send_frame_transparent - Sends a frame transparent - * \param[in] frame_length: Length of the MAC frame to be send - * \param[in] frame: Data buffer with the frame to be sent. Must be allocate using FTDF_GET_DATA_BUFFER - * \param[in] channel: The channel used to send the frame - * \param[in] pti: Packet Traffic Information used for transmitting the packet - * \param[in] cmsa_suppress: If FTDF_TRUE no CSMA-CA is performed before sending the frame - * \param[in] handle: A user defined handle. - * \remark FTDF sends the frame tarnsparently. That is the application has to compose the MAC frame header, - * security header, etc and make sure that it complies with the IEEE802.15.4 standard. Before sending - * it FTDF adds the preamble, frame start, phy header octets and optionally an FCS to the frame provide - * by the application. - * \remark When FTDF has send the frame or failed to send the frame it will call FTDF_SEND_FRAME_TRANSPARENT_CONFIRM - * with the handle provided by the application and the send status. - */ -void ftdf_send_frame_transparent(ftdf_data_length_t frame_length, - ftdf_octet_t *frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t cmsa_suppress, - void *handle); - -/** - * \brief FTDF_SEND_FRAME_TRANSPARENT_CONFIRM - Confirms a transparent send - * \param[in] handle: The application provided handle of the corresponding ftdf_send_frame_transparent call call - * \param[in] status: Bit mapped status - * \remark This function must be implemented by the application it will called by FTDF. It must - * be configured in the configuration file ftdf_config.h. - * \remark FTDF calls this function when a frame has send successfully or failed to send. The application can - * now free the data buffer of the corresponding ftdf_send_frame_transparent call using ftdf_rel_data_buffer - * \remark If the frame is send successfully status is equal to 0 - * \remark If sending the frame failed one of more of the following status bits is set: - * - FTDF_TRANSPARENT_CSMACA_FAILURE: Sending failed because CSMA-CA failed - * - FTDF_TRANSPARENT_OVERFLOW: Sending failed because of internal resource overflow - */ -void FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(void *handle, ftdf_bitmap32_t status); - -/** - * \brief ftdf_send_frame_transparent_confirm - Converts the FTDF_SEND_FRAME_TRANSPARENT_CONFIRM to a msg buffer - * and then calls ftdf_rcv_msg. - * \param[in] handle: The application provided handle of the corresponding ftdf_send_frame_transparent call - * \param[in] status: Bit mapped status - * \remark This function converts the input parameters to a ftdf_transparent_confirm_t structure - * and then calls ftdf_rcv_msg. - * \remark FTDF_SEND_FRAME_TRANSPARENT_CONFIRM can be defined to be this function. - */ -void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status); - -/** - * \brief FTDF_RCV_FRAME_TRANSPARENT - Receive frame transparent - * \param[in] frame_length: Length of the received frame - * \param[in] frame: Pointer to received frame. - * \param[in] status: Bitmapped receive status - * \param[in] link_quality: LQI/RSSI value for this packet. Depends on FTDF_PIB_LINK_QUALITY_MODE - * PIB parameter. - * - * \remark This function must be implemented by the application it will called by FTDF. It must - * be configured in the configuration file ftdf_config.h. - * \remark FTDF calls this function when a frame is received when transparent mode is enabled - * \remark The buffer with the frame must be copied by the application before this function returns - * \remark The following status bits can be set: - * - FTDF_TRANSPARENT_RCV_CRC_ERROR: The CRC (FCS) of the received frame is not correct - * - FTDF_TRANSPARENT_RCV_RES_FRAMETYPE: Received a reserved frame type - * - FTDF_TRANSPARENT_RCV_RES_FRAME_VERSION: Received a reserved frame version - * - FTDF_TRANSPARENT_RCV_UNEXP_DST_ADDR: Unexpected destination address - * - FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID: Unexpected destionation PAN id - * - FTDF_TRANSPARENT_RCV_UNEXP_BEACON: Unexpected beacon frame - * - FTDF_TRANSPARENT_RCV_UNEXP_NO_DEST_ADDR: Unexpected frame without destination adres. - */ -void FTDF_RCV_FRAME_TRANSPARENT(ftdf_data_length_t frame_length, ftdf_octet_t *frame, - ftdf_bitmap32_t status, ftdf_link_quality_t link_quality); - -/** - * \brief ftdf_rcv_frame_transparent - Converts the FTDF_RCV_FRAME_TRANSPARENT to a msg buffer - * and then calls ftdf_rcv_msg. - * \param[in] frame_length: Length of the received frame - * \param[in] frame: Pointer to received frame. - * \param[in] status: Bitmapped receive status - * \param[in] link_quality: Received packet link quality (RSSI/LQI) - * \remark This function convers the input parameters to a ftdf_transparent_indication_t structure - * and then calls ftdf_rcv_msg. - * \remark FTDF_RCV_FRAME_TRANSPARENT can be defined to be this function. - */ -void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length, ftdf_octet_t *frame, - ftdf_bitmap32_t status, ftdf_link_quality_t link_quality); - -/** - * \brief ftdf_set_sleep_attributes - Set sleep atributes - * \param[in] low_power_clock_cycle: The LP clock cycle in picoseconds - * \param[in] wakeup_latency: The wakep up latency time in low power clock cycles - * \remark This functions sets some attributes required by FTDF to go into a deep sleep and wake up from it. - * \remark The wake up latency is the time between the wakeup signal send by FTDF and the moment that the - * clocks are stable. It will be used by FTDF to determine when it must must send the wakeup signal. - * \remark The low power clock cycle will be used to determine how long the system has slept and recover - * the symbol counter internally used by FTDF. - */ -void ftdf_set_sleep_attributes(ftdf_psec_t low_power_clock_cycle, - ftdf_nr_low_power_clock_cycles_t wakeup_latency); - -/** - * \brief ftdf_can_sleep - Indicates whether FTDF can go in a deep sleep - * \remark This function returns the time in microseconds that the FTDF can deep sleep. - * \remark It does NOT take into account the wakeup latency. - * \return The number of microseconds that the FTDF can deep sleep. If equal to 0 the FTDF is still active - * and cannot deep sleep - */ -ftdf_usec_t ftdf_can_sleep(void); - -/** - * \brief ftdf_prepare_for_sleep - Prepare the FTDF for a deep sleep - * \param[in] sleep_time: The sleep time. After the sleep time the FTDF must be ready to do next scheduled activity. - * \remark When this function is completed the application can safely power off the FTDF and put the uP in - * a deep sleep. At least wake up latency time microseconds before sleep time is expired the FTDF - * will send a wakeup signal. FTDF expect that the application calls ftdf_wakeup as it has been - * woken up. - * \return FTDF_TRUE if the FTDF can be put in deep sleep, FTDF_FALSE if the sleep_time is too short to go to - * deep sleep and wake up again after sleep_time microseconds, the FTDF cannot be put in deep sleep. - */ -ftdf_boolean_t ftdf_prepare_for_sleep(ftdf_usec_t sleep_time); - -/** - * \brief ftdf_wakeup - Wake up the FTDF after a sleep - * \remark This function will restores the FTDF to state before the deep sleep. It will does this in 2 steps - * 1. It initialises it internal states and data structures and all the non timing specific HW. After - * that it waits until the wake up latency time has been expired. When expired FTDF assumes that the - * slocks are stable. - * 2. It restores timers in HW and calls the function FTDF_WAKE_UP_READY to indicate FTDF is up again, - * ready to perform scheduled activities and ready to process new requests from the application. - */ -void ftdf_wakeup(void); - -/** - * \brief FTDF_WAKE_UP_READY - Indication that FTDF has woke up - * \remark This function must be implemented by the application it will called by FTDF. It must - * be configured in the configuration file ftdf_config.h. - * \remark FTDF calls this function when it is up again, ready to perform scheduled activities and ready to - * process new requests from the application. - */ -void FTDF_WAKE_UP_READY(void); - -/** - * \brief FTDF_SLEEP_CALLBACK - Callback from FTDF_SLEEP_REQUEST - * \remark This function must be implemented by the application, it will be called by FTDF. - * It must be configured in the configuration file ftdf_config.h - * \remark FTDF calls this function when an FTDF_SLEEP_REQUEST message is sent through the ftdf_snd_msg function. - */ -void FTDF_SLEEP_CALLBACK(ftdf_usec_t sleep_time); - -void ftdf_reset(int set_default_pib); - -ftdf_pti_t ftdf_get_rx_pti(void); - - -#if dg_configCOEX_ENABLE_CONFIG -void ftdf_set_rx_pti(ftdf_pti_t rx_pti); -#if FTDF_USE_AUTO_PTI -void ftdf_restore_rx_pti(void); -#endif -#endif - - -#ifdef FTDF_PHY_API -ftdf_status_t ftdf_send_frame_simple(ftdf_data_length_t frame_length, - ftdf_octet_t *frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t csmaSuppress); - -ftdf_pib_attribute_value_t *ftdf_get_value(ftdf_pib_attribute_t pib_attribute); -ftdf_status_t ftdf_set_value(ftdf_pib_attribute_t pib_attribute, - const ftdf_pib_attribute_value_t *pib_attribute_value); - -void ftdf_rx_enable(ftdf_time_t rx_on_duration); -#endif /* FTDF_PHY_API */ - -#if FTDF_DBG_BUS_ENABLE -/** - * \brief Checks current debug mode and makes appropriate hardware configurations. - */ -void ftdf_check_dbg_mode(void); - -/** - * \brief Sets debug bus mode. - */ -void ftdf_set_dbg_mode(ftdf_dbg_mode_t dbg_mode); - -/** - * \brief Debug bus GPIO configuration callback. Makes appropriate GPIO configurations for the debug - * bus. - */ -void FTDF_DBG_BUS_GPIO_CONFIG(void); -#endif /* FTDF_DBG_BUS_ENABLE */ - -#if dg_configUSE_FTDF_DDPHY == 1 -void ftdf_ddphy_set(uint16_t cca_reg); -#endif /* dg_configUSE_FTDF_DDPHY == 1 */ - -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO -#ifndef FTDF_LITE -/** - * \brief Controls when the FPPR address invalidation will be performed. - * - * If set to 0 (recommended), address invalidation in FPPR occurs right after the frame is passed to - * LMAC for direct transmission. If set to 1, address invalidation occurs after the associated - * confirm message is received. - */ -#define FTDF_FPPR_DEFER_INVALIDATION 0 - -/** - * \brief Adds a new short address to FPPR, initializing the corresponding FSM. - * - * A short address FP FSM accepts the following notifications (events): - * - * - New address (initialize) by calling @ref ftdf_fp_fsm_short_address_new() - * - Last frame pending (passed to direct sending) by calling @ref - * ftdf_fp_fsm_short_address_last_frame_pending() - * - Last pending frame sent by calling @ref ftdf_fp_fsm_clear_pending() - * - * A new address may be rejected if there is no adequate space left in FPPR. - * - * \param [in] pan_id Destination PAN ID. - * \param [in] short_address Destination short address. - * - * \return \ref FTDF_TRUE on success. - */ -ftdf_boolean_t ftdf_fp_fsm_short_address_new(ftdf_pan_id_t pan_id, ftdf_short_address_t short_address); - -/** - * \brief Adds a new extended address to FPPR, initializing the corresponding FSM. - * - * An extended address FP FSM accepts the following notifications (events): - * - * - New address (initialize) by calling @ref ftdf_fp_fsm_rxt_address_new() - * - Last frame pending (passed to direct sending) by calling @ref - * ftdf_fp_fsm_ext_address_last_frame_pending() - * - Last pending frame sent by calling @ref ftdf_fp_fsm_clear_pending() - * - * A new address may be rejected if there is no adequate space left in FPPR. - * - * \param [in] pan_id Destination PAN ID. - * \param [in] ext_address Destination extended address. - * - * \return \ref FTDF_TRUE on success. - */ -ftdf_boolean_t ftdf_fp_fsm_rxt_address_new(ftdf_pan_id_t pan_id, ftdf_ext_address_t ext_address); - -/** - * \brief Notifies FP FSM that the last packet for the associated destination has been passed for - * direct transmission. - * - * \param [in] pan_id Destination PAN ID. - * \param [in] short_address Destination short address. - */ -void ftdf_fp_fsm_short_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_short_address_t short_address); - -/** - * \brief Notifies FP FSM that the last packet for the associated destination has been passed for - * direct transmission. - * - * \param [in] pan_id Destination PAN ID. - * \param [in] ext_address Destination extended address. - */ -void ftdf_fp_fsm_ext_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_ext_address_t ext_address); - -/** - * \brief Notifies FP FSM that the last pending packet has been transmitted (UMAC state machine - * closed). - */ -void ftdf_fp_fsm_clear_pending(void); - -#endif /* #ifndef FTDF_LITE */ - -/** - * \brief Number of FPPR table entries. - */ -#define FTDF_FPPR_TABLE_ENTRIES 24 - -/** - * \brief Number of extended address table entries. - */ -#define FTDF_FPPR_TABLE_EXT_ADDRESS_ENTRIES FTDF_FPPR_TABLE_ENTRIES - -/** - * \brief Number of short address table entries. - */ -#define FTDF_FPPR_TABLE_SHORT_ADDRESS_ENTRIES (FTDF_FPPR_TABLE_ENTRIES * 4) - -/** - * \brief Resets FPPR table, invalidating all addresses. - */ -void ftdf_fppr_reset(void); - -/** - * \brief Gets the short address programmed at the specified FPPR table position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] short_addr_idx Short address position within the entry (0 to 3). - * - * \return Requested short address - */ -ftdf_short_address_t ftdf_fppr_get_short_address(uint8_t entry, uint8_t short_addr_idx); - -/** - * \brief Programs a short address programmed at the specified FPPR table position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] short_addr_idx Short address position within the entry (0 to 3). - * \param [in] short_address short address. - */ -void ftdf_fppr_set_short_address(uint8_t entry, uint8_t short_addr_idx, - ftdf_short_address_t short_address); - -/** - * \brief Determines validity of a short address programmed at the specified FPPR table position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] short_addr_idx Short address position within the entry (0 to 3). - * - * \return FTDF_TRUE if the address is valid. - */ -ftdf_boolean_t ftdf_fppr_get_short_address_valid(uint8_t entry, uint8_t short_addr_idx); - -/** - * \brief Sets validity of a short address programmed at the specified FPPR table position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] short_addr_idx Short address position within the entry (0 to 3). - * \param [in] valid Associated validity. - */ -void ftdf_fppr_set_short_address_valid(uint8_t entry, uint8_t short_addr_idx, - ftdf_boolean_t valid); - -/** - * \brief Gets the extended address programmed at the specified FPPR table position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * - * \return Requested extended address - */ -ftdf_ext_address_t ftdf_fppr_get_ext_address(uint8_t entry); - -/** - * \brief Programs an extended address programmed at the specified FPPR table position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] ext_address Associated extended address. - */ -void ftdf_fppr_set_ext_address(uint8_t entry, ftdf_ext_address_t ext_address); - -/** - * \brief Determines validity of an extended address programmed at the specified FPPR table - * position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * - * \return \ref FTDF_TRUE if the address is valid. - */ -ftdf_boolean_t ftdf_fppr_get_ext_address_valid(uint8_t entry); - -/** - * \brief Sets validity of an extended address programmed at the specified FPPR table position. - * - * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). - * \param [in] valid Associated validity. - */ -void ftdf_fppr_set_ext_address_valid(uint8_t entry, ftdf_boolean_t valid); - -/** - * \brief Gets a free (invalid) short address position in the FPPR table. - * - * \param [out] entry Reference to the FPPR table entry. - * \param [out] short_addr_idx Reference to the short address position within the entry. - * - * \return \ref FTDF_TRUE if a free position was found. - */ -ftdf_boolean_t ftdf_fppr_get_free_short_address(uint8_t * entry, uint8_t *short_addr_idx); - -/** - * \brief Gets a free (invalid) extended address position in the FPPR table. - * - * \param [out] entry Reference to the FPPR table entry. - * - * \return \ref FTDF_TRUE if a free position was found. - */ -ftdf_boolean_t ftdf_fppr_get_free_ext_address(uint8_t * entry); - -/** - * \brief Looks up a short address within the FPPR table. - * - * \param [in] shortAddr Associated short address. - * \param [out] entry Reference to the FPPR table entry. - * \param [out] short_addr_idx Reference to the short address position within the entry. - * - * * \return \ref FTDF_TRUE if the address was found. - */ -ftdf_boolean_t ftdf_fppr_lookup_short_address(ftdf_short_address_t shortAddr, uint8_t *entry, - uint8_t *short_addr_idx); - -/** - * \brief Looks up an extended address within the FPPR table. - * - * \param [in] ext_addr Associated extended address. - * \param [out] entry Reference to the FPPR table entry. - * - * * \return \ref FTDF_TRUE if the address was found. - */ -ftdf_boolean_t ftdf_fppr_lookup_ext_address(ftdf_ext_address_t ext_addr, uint8_t *entry); - -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - -/** - * \brief Sets FPPR mode. - * - * \param [in] match_fp Specifies the value of the FP bit when acknowledging a received frame with a - * source address that matches a valid a address in the FPPR table. The opposite value is set if the - * source address does not match. Ignored if \a fp_override is \ref FTDF_TRUE. - * - * \param [in] fp_override If \ref FTDF_TRUE, the value of \a fp_force is used for setting the FP bit, - * regardless of the address table matching result. - * - * \param [in] fp_force FP bit value when fp_override is \ref FTDF_TRUE. Ignored otherwise. - */ -void ftdf_fppr_set_mode(ftdf_boolean_t match_fp, ftdf_boolean_t fp_override, ftdf_boolean_t fp_force); - -#if FTDF_FP_BIT_TEST_MODE -/** - * \brief Gets FPPR mode. - * - * \param [out] match_fp Reference to the returned value. \see FTDF_fpprRamSetMode - * - * \param [out] fp_override Reference to the returned value. \see FTDF_fpprRamSetMode - * - * \param [out] fp_force FP Reference to the returned value. \see FTDF_fpprRamSetMode - */ -void ftdf_fppr_get_mode(ftdf_boolean_t *match_fp, ftdf_boolean_t *fp_override, ftdf_boolean_t *fp_force); -#endif //FTDF_FP_BIT_TEST_MODE - -#if FTDF_USE_LPDP == 1 - -/** - * \brief Enable or disable LPDP. - * - * \param [in] enable if FTDF_TRUE, LPDP functionality is enabled. - */ -void ftdf_lpdp_enable(ftdf_boolean_t enable); - -#if FTDF_FP_BIT_TEST_MODE -/** - * \brief Checks whether LPDP is enabled. - * - * \return FTDF_TRUE, if LPDP functionality is enabled. - */ -ftdf_boolean_t ftdf_lpdp_is_enabled(void); -#endif - -#endif /* #if FTDF_USE_LPDP == 1 */ - -#endif /* FTDF_H_ */ - -/** - * \} - * \} - * \} - */ - diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h deleted file mode 100644 index ceaec5e2d..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h +++ /dev/null @@ -1,192 +0,0 @@ -/** - **************************************************************************************** - * - * @file ftdf_config_phy_api.h - * - * @brief FTDF PHY API configuration template file - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef FTDF_CONFIG_PHY_API_H_ -#define FTDF_CONFIG_PHY_API_H_ - -#include "osal.h" // OS_FREERTOS macro is checked within the header file. - -/** - * \remark phy configuration values in microseconds - */ -#define FTDF_PHYTXSTARTUP 0x4c -#define FTDF_PHYTXLATENCY 0x02 -#define FTDF_PHYTXFINISH 0x00 -#define FTDF_PHYTRXWAIT 0x22 -#define FTDF_PHYRXSTARTUP 0x54 -#define FTDF_PHYRXLATENCY 0 -#define FTDF_PHYENABLE 0x20 - -#ifndef FTDF_LITE -#define FTDF_LITE -#endif - -/** - * \remark See FTDF_GET_MSG_BUFFER in ftdf.h - */ -#define FTDF_GET_MSG_BUFFER ad_ftdf_get_msg_buffer - -/** - * \remark See FTDF_REL_MSG_BUFFER in ftdf.h - */ -#define FTDF_REL_MSG_BUFFER ad_ftdf_rel_msg_buffer - -/** - * \remark See FTDF_REC_MSG in ftdf.h - */ -#define FTDF_RCV_MSG ad_ftdf_rcv_msg - -/** - * \remark See FTDF_GET_DATA_BUFFER in ftdf.h - */ -#define FTDF_GET_DATA_BUFFER ad_ftdf_get_data_buffer - -/** - * \remark See FTDF_REL_DATA_BUFFER in ftdf.h - */ -#define FTDF_REL_DATA_BUFFER ad_ftdf_rel_data_buffer - -/** - * \remark See FTDF_GET_EXT_ADDRESS in ftdf.h - */ -#define FTDF_GET_EXT_ADDRESS ad_ftdf_get_ext_address - -/** - * \remark See FTDF_RCV_FRAME_TRANSPARENT in ftdf.h - */ -#define FTDF_RCV_FRAME_TRANSPARENT ftdf_rcv_frame_transparent - -/** - * \remark See FTDF_SEND_FRAME_TRANSPARENT_CONFIRM in ftdf.h - */ -#define FTDF_SEND_FRAME_TRANSPARENT_CONFIRM ftdf_send_frame_transparent_confirm - -/** - * \remark See FTDF_WAKE_UP_READY in ftdf.h - */ -#define FTDF_WAKE_UP_READY ad_ftdf_wake_up_ready - -/** - * \remark See FTDF_SLEEP_CALLBACK in ftdf.h - */ -#define FTDF_SLEEP_CALLBACK ad_ftdf_sleep_cb - -/* Forward declaration */ -void sleep_when_possible(uint8_t explicit_request, uint32_t sleep_time); - -#define FTDF_LMACREADY4SLEEP_CB sleep_when_possible - -#ifndef OS_FREERTOS -#define portDISABLE_INTERRUPTS() \ - do { \ - __asm volatile (" cpsid i "); \ - DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \ - } while (0) -#define portENABLE_INTERRUPTS() \ - do { \ - DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \ - __asm volatile (" cpsie i "); \ - } while (0) -void vPortEnterCritical(void); -void vPortExitCritical(void); -#define OS_ENTER_CRITICAL_SECTION vPortEnterCritical -#define OS_LEAVE_CRITICAL_SECTION vPortExitCritical -#endif - -/** - * \remark Critical section - */ - -#define ftdf_critical_var( ) -#define ftdf_enter_critical( ) OS_ENTER_CRITICAL_SECTION() -#define ftdf_exit_critical( ) OS_LEAVE_CRITICAL_SECTION() - -#ifndef FTDF_DBG_BUS_ENABLE -/** - * \brief Whether FTDF debug bus will be available or not. - * - * Define to 0 for production software. - * - * Refer to \ref ad_ftdf_dbgBusGpioConfig for the GPIO pins used for the debug bus. - */ -#define FTDF_DBG_BUS_ENABLE 0 -#endif - -#if FTDF_DBG_BUS_ENABLE -#define FTDF_DBG_BUS_GPIO_CONFIG ad_ftdf_dbg_bus_gpio_config - -#ifndef FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 -/** - * \brief Enables FTDF diagnostics on diagnostic pins 6 and 7 on GPIO P1_3 and P2_3. - * - * When enabled, UART must use pins other than the default P1_3, P2_3. - */ -#define FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 (0) -#endif - -#ifndef FTDF_DBG_BUS_USE_SWDIO_PIN -/** - * \brief Enables diagnostics on diagnostic pin 4 on GPIO P0_6. - * - * When enabled, the debugger must be disabled since SWD uses the same pin for SWDIO. - */ -#define FTDF_DBG_BUS_USE_SWDIO_PIN (0) -#endif - -#ifndef FTDF_DBG_BUS_USE_PORT_4 -/** - * \brief Uses Port 4 (instead of GPIOs at Ports 0, 1 and 2) for diagnostics - * - * When enabled, FTDF diagnostics pins uses P4_0 to P4_7 - */ -#define FTDF_DBG_BUS_USE_PORT_4 (0) -#endif - -#endif /* FTDF_DBG_BUS_ENABLE */ - -#ifndef FTDF_USE_AUTO_PTI -#define FTDF_USE_AUTO_PTI 0 -#endif - -#ifndef FTDF_USE_FP_PROCESSING_RAM -/** - * \brief Whether to use HW acceleration for indirect sending. - * - */ -#define FTDF_USE_FP_PROCESSING_RAM 1 -#endif /* FTDF_USE_FP_PROCESSING_RAM */ - -#endif /* FTDF_CONFIG_PHY_API_H_ */ - diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c deleted file mode 100644 index 84147e561..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c +++ /dev/null @@ -1,341 +0,0 @@ -/** - **************************************************************************************** - * - * @file ad_ftdf.c - * - * @brief FTDF FreeRTOS Adapter - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ -#ifdef CONFIG_USE_FTDF - -#include -#include -#ifndef FTDF_PHY_API -#include "osal.h" -#include "queue.h" - -#include "sys_power_mgr.h" -#endif - -#if dg_configRF_ADAPTER -#include "ad_rf.h" -#else -#include "hw_rf.h" -#endif - -#include "sys_tcs.h" - -#include "sdk_defs.h" -#include "ad_ftdf.h" -#include "internal.h" -#if FTDF_DBG_BUS_ENABLE -#include "hw_gpio.h" -#endif /* FTDF_DBG_BUS_ENABLE */ - -#if FTDF_DBG_BLOCK_SLEEP_ENABLE -#include "hw_gpio.h" -#endif - -#if dg_configUSE_FTDF_DDPHY == 1 -#include "radio.h" -#endif - -#define WUP_LATENCY (AD_FTDF_LP_CLOCK_CYCLE * AD_FTDF_WUP_LATENCY) - -#ifdef FTDF_PHY_API -#ifndef PRIVILEGED_DATA -#define PRIVILEGED_DATA __attribute__((section("privileged_data_zi"))) -#endif -#ifndef INITIALIZED_PRIVILEGED_DATA -#define INITIALIZED_PRIVILEGED_DATA __attribute__((section("privileged_data_init"))) -#endif -#endif - -PRIVILEGED_DATA ftdf_boolean_t explicit_sleep; /* = FTDF_FALSE; */ -PRIVILEGED_DATA sleep_status_t sleep_status; - -PRIVILEGED_DATA ftdf_ext_address_t u_ext_address; - -static void ad_ftdf_sleep(void) -{ - ftdf_critical_var(); - ftdf_enter_critical(); - REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go sleep - ftdf_exit_critical(); - - // don't go-go before I sleep - while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_DOWN) == 0x0) { - - } -#if FTDF_DBG_BLOCK_SLEEP_ENABLE - hw_gpio_set_inactive(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN); -#endif -} - -void ad_ftdf_wake_up_internal(bool sync) -{ - if ( sleep_status != BLOCK_SLEEPING ) { - return; - } - - ftdf_critical_var(); - ftdf_enter_critical(); - /* Wake up power domains */ - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up - ftdf_exit_critical(); - - // don't go-go before I sleep - while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) { - - } -#if FTDF_DBG_BLOCK_SLEEP_ENABLE - hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); -#endif - - /* Power on and configure RF */ -#if dg_configRF_ADAPTER - ad_rf_request_on(false); -#else - hw_rf_request_on(false); -#endif - - /* Apply trim values */ - sys_tcs_apply(tcs_ftdf); - -#if dg_configRF_ADAPTER - ad_rf_request_recommended_settings(); -#else - hw_rf_request_recommended_settings(); -#endif - - - if (sync) { - ftdf_init_lmac( ); - sleep_status = BLOCK_ACTIVE; - } else { - /* Wake up FTDF block */ - sleep_status = BLOCK_WAKING_UP; - ftdf_wakeup(); -#if defined(FTDF_NO_CSL) && defined(FTDF_NO_TSCH) - ad_ftdf_wake_up_ready(); -#endif - } - -} - -void ad_ftdf_wake_up_async(void) -{ - ad_ftdf_wake_up_internal(false); -} - -void ad_ftdf_wake_up_sync(void) -{ - ad_ftdf_wake_up_internal(true); -} - -void sleep_when_possible(uint8_t explicit_request, uint32_t sleep_time ) -{ - ftdf_boolean_t block_sleep = FTDF_FALSE; - - if ((!AD_FTDF_SLEEP_WHEN_IDLE && !explicit_request) || sleep_status != BLOCK_ACTIVE) { - return; - } - - ftdf_usec_t us; - - - ftdf_critical_var(); - ftdf_enter_critical(); -#ifdef FTDF_PHY_API - if (explicit_request && (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0)) { - - /* clear a previous interrupt */ - FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, LMACREADY4SLEEP_D); - - /* Enable (unmask) interrupt */ - REG_SET_BIT(FTDF, FTDF_LMAC_CONTROL_MASK_REG, LMACREADY4SLEEP_M); - us = 0; - } else { - us = ftdf_can_sleep(); - } -#else - us = ftdf_can_sleep(); -#endif - /* Try to sleep as much as needed (if sleep_time is 0, then sleep as much as possible). - * Otherwise, sleep as much as possible. */ - if ( explicit_request == FTDF_TRUE ) { - if (sleep_time && us > sleep_time) - us = sleep_time; - } - - if (us > ( WUP_LATENCY / 1000000) + AD_FTDF_SLEEP_COMPENSATION) { - // Subtract sleep compensation from the sleep time, compensating for delays - us -= AD_FTDF_SLEEP_COMPENSATION; - - block_sleep = ftdf_prepare_for_sleep(us); - - if (block_sleep) { - // FTDF ready to sleep, disable clocks - sleep_status = BLOCK_SLEEPING; - explicit_sleep = explicit_request; -#if FTDF_USE_SLEEP_DURING_BACKOFF - ftdf_sdb_fsm_sleep(); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ -#if dg_configUSE_FTDF_DDPHY == 1 - ftdf_ddphy_save(); -#endif /* dg_configUSE_FTDF_DDPHY */ - ad_ftdf_sleep(); - } else { -#if FTDF_USE_SLEEP_DURING_BACKOFF - ftdf_sdb_fsm_abort_sleep(); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - } - } - ftdf_exit_critical(); - if (block_sleep) { -#if dg_configRF_ADAPTER - ad_rf_request_off(false); -#else - hw_rf_request_off(false); -#endif - } -} - -/** - * @brief Initialization function of FTDF adapter - */ -void ad_ftdf_init(void) -{ - /* Wake up power domains */ - GLOBAL_INT_DISABLE(); - REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up - GLOBAL_INT_RESTORE(); - - // don't go-go before I sleep - while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) { - - } - -#if FTDF_DBG_BLOCK_SLEEP_ENABLE - hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, - HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); -#endif - GLOBAL_INT_DISABLE(); - REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE); // on - REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); // divide by 1 - GLOBAL_INT_RESTORE(); - - /* Power on and configure RF */ -#if dg_configRF_ADAPTER - ad_rf_request_on(false); -#else - hw_rf_request_on(false); -#endif - - /* Apply trim values */ - sys_tcs_apply(tcs_ftdf); - -#if dg_configRF_ADAPTER - ad_rf_request_recommended_settings(); -#else - hw_rf_request_recommended_settings(); -#endif - - ftdf_set_sleep_attributes( AD_FTDF_LP_CLOCK_CYCLE, AD_FTDF_WUP_LATENCY ); - -#ifdef FTDF_PHY_API - ad_ftdf_init_phy_api(); -#else - ad_ftdf_init_mac_api(); -#endif -} - -void ad_ftdf_sleep_cb(ftdf_usec_t sleep_time ) -{ - sleep_when_possible( FTDF_TRUE, sleep_time ); -} - -#if FTDF_DBG_BUS_ENABLE -void ad_ftdf_dbg_bus_gpio_config(void) -{ - -#if FTDF_DBG_BUS_USE_PORT_4 == 1 - - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_0, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_1, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_2, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - - -#else - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); -#if FTDF_DBG_BUS_USE_SWDIO_PIN - /* - * Note that this pin has a conflict with SWD. Disable the debugger in order to use this - * pin. - */ - hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); -#endif - hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); -#if FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 - /* - * Note that these pins have a conflict with the pins used for UART by default. Configure - * UART on different pins if you would like to use the pins below for diagnostics. - */ - hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); - hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, - HW_GPIO_FUNC_FTDF_DIAG); -#endif -#endif /* FTDF_DBG_BUS_USE_PORT_4 == 1 */ -} -#endif /* FTDF_DBG_BUS_ENABLE */ -#endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h deleted file mode 100644 index b432d7a9f..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - \addtogroup INTERFACES - \{ - \addtogroup FTDF - \{ - */ - -/** - **************************************************************************************** - * - * @file ad_ftdf.h - * - * @brief FTDF Adapter internal header file - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#ifndef AD_FTDF_H -#define AD_FTDF_H - -#ifndef FTDF_PHY_API -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" -#endif - -#include "ftdf.h" -#include "ad_ftdf_config.h" - -typedef enum { - BLOCK_ACTIVE = 0, BLOCK_SLEEPING, BLOCK_WAKING_UP -} sleep_status_t; - -extern sleep_status_t sleep_status; -extern ftdf_ext_address_t u_ext_address; -extern ftdf_boolean_t explicit_sleep; - -void ad_ftdf_init_mac_api(void); -void ad_ftdf_init_phy_api(void); - -void ad_ftdf_wake_up_async(void); -void ad_ftdf_wake_up_sync(void); - -void sleep_when_possible( uint8_t explicit_request, uint32_t sleep_time ); - -#if FTDF_DBG_BUS_ENABLE -/** - * \brief Configures GPIO pins for the FTDF debug bus - * - * Debug bus uses the following (fixed) GPIO pins: - * - * bit 0: HW_GPIO_PORT_1, HW_GPIO_PIN_4 - * bit 1: HW_GPIO_PORT_1, HW_GPIO_PIN_5 - * bit 2: HW_GPIO_PORT_1, HW_GPIO_PIN_6 - * bit 3: HW_GPIO_PORT_1, HW_GPIO_PIN_7 - * bit 4: HW_GPIO_PORT_0, HW_GPIO_PIN_6 - * bit 5: HW_GPIO_PORT_0, HW_GPIO_PIN_7 - * bit 6: HW_GPIO_PORT_1, HW_GPIO_PIN_3 - * bit 7: HW_GPIO_PORT_2, HW_GPIO_PIN_3 - */ -void ad_ftdf_dbg_bus_gpio_config(void); -#endif /* FTDF_DBG_BUS_ENABLE */ - -#endif /* AD_FTDF_H */ -/** - \} - \} - \} - */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c deleted file mode 100644 index 098817ec3..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c +++ /dev/null @@ -1,164 +0,0 @@ -/** - **************************************************************************************** - * - * @file ad_ftdf_phy_api.c - * - * @brief FTDF FreeRTOS Adapter - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ -#ifdef CONFIG_USE_FTDF - -#ifdef FTDF_PHY_API - -#include -#include - -#include "sdk_defs.h" -#include "ad_ftdf.h" -#include "ad_ftdf_phy_api.h" -#include "internal.h" -#if FTDF_DBG_BUS_ENABLE -#include "hw_gpio.h" -#endif /* FTDF_DBG_BUS_ENABLE */ - -#ifndef OS_FREERTOS -static unsigned long uxCriticalNesting = 0xaaaaaaaa; - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; - __asm volatile( "dsb" ); - __asm volatile( "isb" ); -} - -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - - uxCriticalNesting--; - if ( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -#endif /* !OS_FREERTOS */ - -/** - * @brief ftdf_gen_irq interrupt service routine - */ -void FTDF_GEN_Handler( void) -{ - ftdf_confirm_lmac_interrupt(); - ftdf_event_handler(); -} -/** - * @brief ftdf_wakup_irq interrupt service routine - */ -void FTDF_WAKEUP_Handler( void) -{ - ad_ftdf_wake_up_async(); -} - -void ad_ftdf_set_ext_address( ftdf_ext_address_t address) -{ - u_ext_address = address; -} - -ftdf_ext_address_t ad_ftdf_get_ext_address( void) -{ - return u_ext_address; -} - -void ad_ftdf_wake_up_ready( void) -{ -} - -ftdf_status_t ad_ftdf_send_frame_simple( ftdf_data_length_t frameLength, - ftdf_octet_t *frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t csmaSuppress) -{ - ftdf_critical_var(); - ftdf_enter_critical(); - if (ftdf_tx_in_progress == FTDF_TRUE) { - ftdf_exit_critical(); - return FTDF_TRANSPARENT_OVERFLOW; - } - ftdf_tx_in_progress = FTDF_TRUE; - ftdf_exit_critical(); - - if (sleep_status == BLOCK_SLEEPING) { - /* Wake-up the block */ - ad_ftdf_wake_up_async(); -#if FTDF_DBG_BUS_ENABLE - ftdf_check_dbg_mode(); -#endif /* FTDF_DBG_BUS_ENABLE */ - sleep_status = BLOCK_ACTIVE; - } - return ftdf_send_frame_simple(frameLength, frame, channel, pti, csmaSuppress); -} - - -void ad_ftdf_sleep_when_possible( ftdf_boolean_t allow_deferred_sleep) -{ - sleep_when_possible(allow_deferred_sleep, 0); -} - -void ad_ftdf_wake_up(void) -{ - if (sleep_status == BLOCK_SLEEPING) { - /* Wake-up the block */ - ad_ftdf_wake_up_async(); -#if FTDF_DBG_BUS_ENABLE - ftdf_check_dbg_mode(); -#endif /* FTDF_DBG_BUS_ENABLE */ - sleep_status = BLOCK_ACTIVE; - } - -} - -void ad_ftdf_init_phy_api(void) -{ - NVIC_ClearPendingIRQ(FTDF_WAKEUP_IRQn); - NVIC_EnableIRQ(FTDF_WAKEUP_IRQn); - - NVIC_ClearPendingIRQ(FTDF_GEN_IRQn); - NVIC_EnableIRQ(FTDF_GEN_IRQn); - sleep_status = BLOCK_ACTIVE; -#ifndef OS_FREERTOS - uxCriticalNesting = 0; -#endif - - ftdf_reset(1); -} -#endif /* FTDF_PHY_API */ -#endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c deleted file mode 100644 index 4f7342079..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c +++ /dev/null @@ -1,5217 +0,0 @@ -/** - **************************************************************************************** - * - * @file common.c - * - * @brief Common FTDF functions - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#include -#include - -#include -#include "internal.h" -#include "sdk_defs.h" - -#ifdef CONFIG_USE_FTDF -#if dg_configCOEX_ENABLE_CONFIG -#include "hw_coex.h" -#endif -typedef struct { - void *addr; - uint8_t size; - void (*getFunc)(void); - void (*setFunc)(void); -} pib_attribute_def_t; - -typedef struct { - pib_attribute_def_t attribute_defs[FTDF_NR_OF_PIB_ATTRIBUTES + 1]; -} pib_attribute_table_h; - -ftdf_pib_t ftdf_pib __attribute__ ((section(".retention"))); - -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO -#if FTDF_FPPR_DEFER_INVALIDATION -static struct { - ftdf_address_mode_t addr_mode; - ftdf_pan_id_t pan_id; - ftdf_address_t addr; -} ftdf_fppr_pending __attribute__ ((section(".retention"))); -#endif /* FTDF_FPPR_DEFER_INVALIDATION */ -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - -#ifndef FTDF_LITE -const ftdf_channel_number_t page_0_channels[FTDF_NR_OF_CHANNELS] = { - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; -const ftdf_channel_descriptor_t channel_descriptors[1] = { - { 0, 16, (ftdf_channel_number_t*)page_0_channels } }; -const ftdf_channel_descriptor_list_t channels_supported = { - 1, (ftdf_channel_descriptor_t*)channel_descriptors }; -#endif - -const pib_attribute_table_h pib_attribute_table = { - .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].addr = &ftdf_pib.ext_address, - .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].size = sizeof(ftdf_pib.ext_address), - .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].getFunc = ftdf_get_ext_address, - .attribute_defs[FTDF_PIB_EXTENDED_ADDRESS].setFunc = ftdf_set_ext_address, - .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].addr = &ftdf_pib.ack_wait_duration, - .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].size = 0, - .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].getFunc = ftdf_get_ack_wait_duration, - .attribute_defs[FTDF_PIB_ACK_WAIT_DURATION].setFunc = NULL, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].addr = &ftdf_pib.associated_pan_coord, - .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].size = sizeof(ftdf_pib.associated_pan_coord), - .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].getFunc = NULL, - .attribute_defs[FTDF_PIB_ASSOCIATION_PAN_COORD].setFunc = NULL, - .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].addr = &ftdf_pib.association_permit, - .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].size = sizeof(ftdf_pib.association_permit), - .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].getFunc = NULL, - .attribute_defs[FTDF_PIB_ASSOCIATION_PERMIT].setFunc = NULL, - .attribute_defs[FTDF_PIB_AUTO_REQUEST].addr = &ftdf_pib.auto_request, - .attribute_defs[FTDF_PIB_AUTO_REQUEST].size = sizeof(ftdf_pib.auto_request), - .attribute_defs[FTDF_PIB_AUTO_REQUEST].getFunc = NULL, - .attribute_defs[FTDF_PIB_AUTO_REQUEST].setFunc = NULL, - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].addr = &ftdf_pib.batt_life_ext, - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].size = sizeof(ftdf_pib.batt_life_ext), - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].getFunc = NULL, - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT].setFunc = NULL, - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].addr = &ftdf_pib.batt_life_ext_periods, - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].size = sizeof(ftdf_pib.batt_life_ext_periods), - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].getFunc = NULL, - .attribute_defs[FTDF_PIB_BATT_LIFE_EXT_PERIODS].setFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].addr = &ftdf_pib.beacon_payload, - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].size = sizeof(ftdf_pib.beacon_payload), - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].getFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD].setFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].addr = &ftdf_pib.beacon_payload_length, - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].size = sizeof(ftdf_pib.beacon_payload_length), - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].getFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_PAYLOAD_LENGTH].setFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_ORDER].addr = &ftdf_pib.beacon_order, - .attribute_defs[FTDF_PIB_BEACON_ORDER].size = 0, - .attribute_defs[FTDF_PIB_BEACON_ORDER].getFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_ORDER].setFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_TX_TIME].addr = &ftdf_pib.beacon_tx_time, - .attribute_defs[FTDF_PIB_BEACON_TX_TIME].size = sizeof(ftdf_pib.beacon_tx_time), - .attribute_defs[FTDF_PIB_BEACON_TX_TIME].getFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_TX_TIME].setFunc = NULL, - .attribute_defs[FTDF_PIB_BSN].addr = &ftdf_pib.bsn, - .attribute_defs[FTDF_PIB_BSN].size = sizeof(ftdf_pib.bsn), - .attribute_defs[FTDF_PIB_BSN].getFunc = NULL, - .attribute_defs[FTDF_PIB_BSN].setFunc = NULL, - .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].addr = &ftdf_pib.coord_ext_address, - .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].size = sizeof(ftdf_pib.coord_ext_address), - .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].getFunc = NULL, - .attribute_defs[FTDF_PIB_COORD_EXTENDED_ADDRESS].setFunc = NULL, - .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].addr = &ftdf_pib.coord_short_address, - .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].size = sizeof(ftdf_pib.coord_short_address), - .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].getFunc = NULL, - .attribute_defs[FTDF_PIB_COORD_SHORT_ADDRESS].setFunc = NULL, - .attribute_defs[FTDF_PIB_DSN].addr = &ftdf_pib.dsn, - .attribute_defs[FTDF_PIB_DSN].size = sizeof(ftdf_pib.dsn), - .attribute_defs[FTDF_PIB_DSN].getFunc = NULL, - .attribute_defs[FTDF_PIB_DSN].setFunc = NULL, - .attribute_defs[FTDF_PIB_GTS_PERMIT].addr = &ftdf_pib.gts_permit, - .attribute_defs[FTDF_PIB_GTS_PERMIT].size = 0, - .attribute_defs[FTDF_PIB_GTS_PERMIT].getFunc = NULL, - .attribute_defs[FTDF_PIB_GTS_PERMIT].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_MAX_BE].addr = &ftdf_pib.max_be, - .attribute_defs[FTDF_PIB_MAX_BE].size = sizeof(ftdf_pib.max_be), - .attribute_defs[FTDF_PIB_MAX_BE].getFunc = NULL, - .attribute_defs[FTDF_PIB_MAX_BE].setFunc = ftdf_set_max_be, - .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].addr = &ftdf_pib.max_csma_backoffs, - .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].size = sizeof(ftdf_pib.max_csma_backoffs), - .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].getFunc = NULL, - .attribute_defs[FTDF_PIB_MAX_CSMA_BACKOFFS].setFunc = ftdf_set_max_csma_backoffs, - .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].addr = &ftdf_pib.max_frame_total_wait_time, - .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].size = sizeof(ftdf_pib.max_frame_total_wait_time), - .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].getFunc = ftdf_get_max_frame_total_wait_time, - .attribute_defs[FTDF_PIB_MAX_FRAME_TOTAL_WAIT_TIME].setFunc = ftdf_set_max_frame_total_wait_time, - .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].addr = &ftdf_pib.max_frame_retries, - .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].size = - sizeof(ftdf_pib.max_frame_retries), - .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].getFunc = NULL, - .attribute_defs[FTDF_PIB_MAX_FRAME_RETRIES].setFunc = NULL, - .attribute_defs[FTDF_PIB_MIN_BE].addr = &ftdf_pib.min_be, - .attribute_defs[FTDF_PIB_MIN_BE].size = sizeof(ftdf_pib.min_be), - .attribute_defs[FTDF_PIB_MIN_BE].getFunc = NULL, - .attribute_defs[FTDF_PIB_MIN_BE].setFunc = ftdf_set_min_be, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_LIFS_PERIOD].addr = &ftdf_pib.lifs_period, - .attribute_defs[FTDF_PIB_LIFS_PERIOD].size = 0, - .attribute_defs[FTDF_PIB_LIFS_PERIOD].getFunc = NULL, - .attribute_defs[FTDF_PIB_LIFS_PERIOD].setFunc = NULL, - .attribute_defs[FTDF_PIB_SIFS_PERIOD].addr = &ftdf_pib.sifs_period, - .attribute_defs[FTDF_PIB_SIFS_PERIOD].size = 0, - .attribute_defs[FTDF_PIB_SIFS_PERIOD].getFunc = NULL, - .attribute_defs[FTDF_PIB_SIFS_PERIOD].setFunc = NULL, -#endif - .attribute_defs[FTDF_PIB_PAN_ID].addr = &ftdf_pib.pan_id, - .attribute_defs[FTDF_PIB_PAN_ID].size = sizeof(ftdf_pib.pan_id), - .attribute_defs[FTDF_PIB_PAN_ID].getFunc = ftdf_getpan_id, - .attribute_defs[FTDF_PIB_PAN_ID].setFunc = ftdf_setpan_id, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].addr = &ftdf_pib.promiscuous_mode, - .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].size = sizeof(ftdf_pib.promiscuous_mode), - .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].getFunc = NULL, - .attribute_defs[FTDF_PIB_PROMISCUOUS_MODE].setFunc = NULL, - .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].addr = &ftdf_pib.response_wait_time, - .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].size = sizeof(ftdf_pib.response_wait_time), - .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].getFunc = NULL, - .attribute_defs[FTDF_PIB_RESPONSE_WAIT_TIME].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].addr = &ftdf_pib.rx_on_when_idle, - .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].size = sizeof(ftdf_pib.rx_on_when_idle), - .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].getFunc = ftdf_get_rx_on_when_idle, - .attribute_defs[FTDF_PIB_RX_ON_WHEN_IDLE].setFunc = ftdf_set_rx_on_when_idle, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_SECURITY_ENABLED].addr = &ftdf_pib.security_enabled, - .attribute_defs[FTDF_PIB_SECURITY_ENABLED].size = sizeof(ftdf_pib.security_enabled), - .attribute_defs[FTDF_PIB_SECURITY_ENABLED].getFunc = NULL, - .attribute_defs[FTDF_PIB_SECURITY_ENABLED].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_SHORT_ADDRESS].addr = &ftdf_pib.short_address, - .attribute_defs[FTDF_PIB_SHORT_ADDRESS].size = sizeof(ftdf_pib.short_address), - .attribute_defs[FTDF_PIB_SHORT_ADDRESS].getFunc = NULL, - .attribute_defs[FTDF_PIB_SHORT_ADDRESS].setFunc = ftdf_set_short_address, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].addr = &ftdf_pib.superframe_order, - .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].size = 0, - .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].getFunc = NULL, - .attribute_defs[FTDF_PIB_SUPERFRAME_ORDER].setFunc = NULL, - .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].addr = &ftdf_pib.sync_symbol_offset, - .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].size = 0, - .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].getFunc = NULL, - .attribute_defs[FTDF_PIB_SYNC_SYMBOL_OFFSET].setFunc = NULL, - .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].addr = &ftdf_pib.timestamp_supported, - .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].size = 0, - .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].getFunc = NULL, - .attribute_defs[FTDF_PIB_TIMESTAMP_SUPPORTED].setFunc = NULL, - .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].addr = &ftdf_pib.transaction_persistence_time, - .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].size = sizeof(ftdf_pib.transaction_persistence_time), - .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].getFunc = NULL, - .attribute_defs[FTDF_PIB_TRANSACTION_PERSISTENCE_TIME].setFunc = NULL, - .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].addr = &ftdf_pib.enh_ack_wait_duration, - .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].size = sizeof(ftdf_pib.enh_ack_wait_duration), - .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].getFunc = ftdf_get_enh_ack_wait_duration, - .attribute_defs[FTDF_PIB_ENH_ACK_WAIT_DURATION].setFunc = ftdf_set_enh_ack_wait_duration, - .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].addr = &ftdf_pib.implicit_broadcast, - .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].size = sizeof(ftdf_pib.implicit_broadcast), - .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].getFunc = ftdf_get_implicit_broadcast, - .attribute_defs[FTDF_PIB_IMPLICIT_BROADCAST].setFunc = ftdf_set_implicit_broadcast, - .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].addr = &ftdf_pib.simple_address, - .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].size = sizeof(ftdf_pib.simple_address), - .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].getFunc = NULL, - .attribute_defs[FTDF_PIB_SIMPLE_ADDRESS].setFunc = ftdf_set_simple_address, - .attribute_defs[FTDF_PIB_DISCONNECT_TIME].addr = &ftdf_pib.disconnect_time, - .attribute_defs[FTDF_PIB_DISCONNECT_TIME].size = sizeof(ftdf_pib.disconnect_time), - .attribute_defs[FTDF_PIB_DISCONNECT_TIME].getFunc = NULL, - .attribute_defs[FTDF_PIB_DISCONNECT_TIME].setFunc = NULL, - .attribute_defs[FTDF_PIB_JOIN_PRIORITY].addr = &ftdf_pib.join_priority, - .attribute_defs[FTDF_PIB_JOIN_PRIORITY].size = sizeof(ftdf_pib.join_priority), - .attribute_defs[FTDF_PIB_JOIN_PRIORITY].getFunc = NULL, - .attribute_defs[FTDF_PIB_JOIN_PRIORITY].setFunc = NULL, - .attribute_defs[FTDF_PIB_ASN].addr = &ftdf_pib.asn, - .attribute_defs[FTDF_PIB_ASN].size = sizeof(ftdf_pib.asn), - .attribute_defs[FTDF_PIB_ASN].getFunc = NULL, - .attribute_defs[FTDF_PIB_ASN].setFunc = NULL, - .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].addr = &ftdf_pib.no_hl_buffers, - .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].size = sizeof(ftdf_pib.no_hl_buffers), - .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].getFunc = NULL, - .attribute_defs[FTDF_PIB_NO_HL_BUFFERS].setFunc = NULL, - .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].addr = &ftdf_pib.slotframe_table, - .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].size = 0, - .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_SLOTFRAME_TABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_LINK_TABLE].addr = &ftdf_pib.link_table, - .attribute_defs[FTDF_PIB_LINK_TABLE].size = 0, - .attribute_defs[FTDF_PIB_LINK_TABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_LINK_TABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].addr = &ftdf_pib.timeslot_template, - .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].size = sizeof(ftdf_pib.timeslot_template), - .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].getFunc = NULL, -#ifdef FTDF_NO_TSCH - .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].setFunc = NULL, -#else - .attribute_defs[FTDF_PIB_TIMESLOT_TEMPLATE].setFunc = ftdf_set_timeslot_template, -#endif /* FTDF_NO_TSCH */ - .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].addr = &ftdf_pib.hopping_sequence_id, - .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].size = sizeof(ftdf_pib.hopping_sequence_id), - .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].getFunc = NULL, - .attribute_defs[FTDF_PIB_HOPPINGSEQUENCE_ID].setFunc = NULL, - .attribute_defs[FTDF_PIB_CHANNEL_PAGE].addr = &ftdf_pib.channel_page, - .attribute_defs[FTDF_PIB_CHANNEL_PAGE].size = sizeof(ftdf_pib.channel_page), - .attribute_defs[FTDF_PIB_CHANNEL_PAGE].getFunc = NULL, - .attribute_defs[FTDF_PIB_CHANNEL_PAGE].setFunc = NULL, - .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].addr = &ftdf_pib.number_of_channels, - .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].size = sizeof(ftdf_pib.number_of_channels), - .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].getFunc = NULL, - .attribute_defs[FTDF_PIB_NUMBER_OF_CHANNELS].setFunc = NULL, - .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].addr = &ftdf_pib.phy_configuration, - .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].size = sizeof(ftdf_pib.phy_configuration), - .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].getFunc = NULL, - .attribute_defs[FTDF_PIB_PHY_CONFIGURATION].setFunc = NULL, - .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].addr = &ftdf_pib.extended_bitmap, - .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].size = sizeof(ftdf_pib.extended_bitmap), - .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].getFunc = NULL, - .attribute_defs[FTDF_PIB_EXTENTED_BITMAP].setFunc = NULL, - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].addr = &ftdf_pib.hopping_sequence_length, - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].size = sizeof(ftdf_pib.hopping_sequence_length), - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].getFunc = NULL, - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LENGTH].setFunc = NULL, - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].addr = ftdf_pib.hopping_sequence_list, - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].size = sizeof(ftdf_pib.hopping_sequence_list), - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].getFunc = NULL, - .attribute_defs[FTDF_PIB_HOPPING_SEQUENCE_LIST].setFunc = NULL, - .attribute_defs[FTDF_PIB_CURRENT_HOP].addr = &ftdf_pib.current_hop, - .attribute_defs[FTDF_PIB_CURRENT_HOP].size = sizeof(ftdf_pib.current_hop), - .attribute_defs[FTDF_PIB_CURRENT_HOP].getFunc = NULL, - .attribute_defs[FTDF_PIB_CURRENT_HOP].setFunc = NULL, - .attribute_defs[FTDF_PIB_DWELL_TIME].addr = &ftdf_pib.dwell_time, - .attribute_defs[FTDF_PIB_DWELL_TIME].size = sizeof(ftdf_pib.dwell_time), - .attribute_defs[FTDF_PIB_DWELL_TIME].getFunc = NULL, - .attribute_defs[FTDF_PIB_DWELL_TIME].setFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_PERIOD].addr = &ftdf_pib.csl_period, - .attribute_defs[FTDF_PIB_CSL_PERIOD].size = sizeof(ftdf_pib.csl_period), - .attribute_defs[FTDF_PIB_CSL_PERIOD].getFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_PERIOD].setFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].addr = &ftdf_pib.csl_max_period, - .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].size = sizeof(ftdf_pib.csl_max_period), - .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].getFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_MAX_PERIOD].setFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].addr = &ftdf_pib.csl_channel_mask, - .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].size = sizeof(ftdf_pib.csl_channel_mask), - .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].getFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_CHANNEL_MASK].setFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].addr = &ftdf_pib.csl_frame_pending_wait, - .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].size = sizeof(ftdf_pib.csl_frame_pending_wait), -#ifdef FTDF_NO_CSL - .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].getFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].setFunc = NULL, -#else - .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].getFunc = ftdf_get_csl_frame_pending_wait, - .attribute_defs[FTDF_PIB_CSL_FRAME_PENDING_WAIT_T].setFunc = ftdf_set_csl_frame_pending_wait, -#endif /* FTDF_NO_CSL */ - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].addr = &ftdf_pib.low_energy_superframe_supported, - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].size = sizeof(ftdf_pib.low_energy_superframe_supported), - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].getFunc = NULL, - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SUPPORTED].setFunc = NULL, - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].addr = &ftdf_pib.low_energy_superframe_sync_interval, - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].size = sizeof(ftdf_pib.low_energy_superframe_sync_interval), - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].getFunc = NULL, - .attribute_defs[FTDF_PIB_LOW_ENERGY_SUPERFRAME_SYNC_INTERVAL].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].addr = &ftdf_pib.performance_metrics, - .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].size = sizeof(ftdf_pib.performance_metrics), - .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].getFunc = ftdf_get_lmac_pm_data, - .attribute_defs[FTDF_PIB_PERFORMANCE_METRICS].setFunc = NULL, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].addr = &ftdf_pib.use_enhanced_becaon, - .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].size = sizeof(ftdf_pib.use_enhanced_becaon), - .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].getFunc = NULL, - .attribute_defs[FTDF_PIB_USE_ENHANCED_BEACON].setFunc = NULL, - .attribute_defs[FTDF_PIB_EB_IE_LIST].addr = &ftdf_pib.eb_ie_list, - .attribute_defs[FTDF_PIB_EB_IE_LIST].size = sizeof(ftdf_pib.eb_ie_list), - .attribute_defs[FTDF_PIB_EB_IE_LIST].getFunc = NULL, - .attribute_defs[FTDF_PIB_EB_IE_LIST].setFunc = NULL, - .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].addr = &ftdf_pib.eb_filtering_enabled, - .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].size = sizeof(ftdf_pib.eb_filtering_enabled), - .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].getFunc = NULL, - .attribute_defs[FTDF_PIB_EB_FILTERING_ENABLED].setFunc = NULL, - .attribute_defs[FTDF_PIB_EBSN].addr = &ftdf_pib.eb_sn, - .attribute_defs[FTDF_PIB_EBSN].size = sizeof(ftdf_pib.eb_sn), - .attribute_defs[FTDF_PIB_EBSN].getFunc = NULL, - .attribute_defs[FTDF_PIB_EBSN].setFunc = NULL, - .attribute_defs[FTDF_PIB_EB_AUTO_SA].addr = &ftdf_pib.eb_auto_sa, - .attribute_defs[FTDF_PIB_EB_AUTO_SA].size = sizeof(ftdf_pib.eb_auto_sa), - .attribute_defs[FTDF_PIB_EB_AUTO_SA].getFunc = NULL, - .attribute_defs[FTDF_PIB_EB_AUTO_SA].setFunc = NULL, - .attribute_defs[FTDF_PIB_EACK_IE_LIST].addr = &ftdf_pib.e_ack_ie_list, - .attribute_defs[FTDF_PIB_EACK_IE_LIST].size = sizeof(ftdf_pib.e_ack_ie_list), - .attribute_defs[FTDF_PIB_EACK_IE_LIST].getFunc = NULL, - .attribute_defs[FTDF_PIB_EACK_IE_LIST].setFunc = NULL, - .attribute_defs[FTDF_PIB_KEY_TABLE].addr = &ftdf_pib.key_table, - .attribute_defs[FTDF_PIB_KEY_TABLE].size = sizeof(ftdf_pib.key_table), - .attribute_defs[FTDF_PIB_KEY_TABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_KEY_TABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_DEVICE_TABLE].addr = &ftdf_pib.device_table, - .attribute_defs[FTDF_PIB_DEVICE_TABLE].size = sizeof(ftdf_pib.device_table), - .attribute_defs[FTDF_PIB_DEVICE_TABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_DEVICE_TABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].addr = &ftdf_pib.security_level_table, - .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].size = sizeof(ftdf_pib.security_level_table), - .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_SECURITY_LEVEL_TABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_FRAME_COUNTER].addr = &ftdf_pib.frame_counter, - .attribute_defs[FTDF_PIB_FRAME_COUNTER].size = sizeof(ftdf_pib.frame_counter), - .attribute_defs[FTDF_PIB_FRAME_COUNTER].getFunc = NULL, - .attribute_defs[FTDF_PIB_FRAME_COUNTER].setFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].addr = &ftdf_pib.mt_data_security_level, - .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].size = sizeof(ftdf_pib.mt_data_security_level), - .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].getFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_SECURITY_LEVEL].setFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].addr = &ftdf_pib.mt_data_key_id_mode, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].size = sizeof(ftdf_pib.mt_data_key_id_mode), - .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].getFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_ID_MODE].setFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].addr = &ftdf_pib.mt_data_key_source, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].size = sizeof(ftdf_pib.mt_data_key_source), - .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].getFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_SOURCE].setFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].addr = &ftdf_pib.mt_data_key_index, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].size = sizeof(ftdf_pib.mt_data_key_index), - .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].getFunc = NULL, - .attribute_defs[FTDF_PIB_MT_DATA_KEY_INDEX].setFunc = NULL, - .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].addr = &ftdf_pib.default_key_source, - .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].size = sizeof(ftdf_pib.default_key_source), - .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].getFunc = NULL, - .attribute_defs[FTDF_PIB_DEFAULT_KEY_SOURCE].setFunc = NULL, - .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].addr = &ftdf_pib.pan_coord_ext_address, - .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].size = sizeof(ftdf_pib.pan_coord_ext_address), - .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].getFunc = NULL, - .attribute_defs[FTDF_PIB_PAN_COORD_EXTENDED_ADDRESS].setFunc = NULL, - .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].addr = &ftdf_pib.pan_coord_short_address, - .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].size = sizeof(ftdf_pib.pan_coord_short_address), - .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].getFunc = NULL, - .attribute_defs[FTDF_PIB_PAN_COORD_SHORT_ADDRESS].setFunc = NULL, - .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].addr = &ftdf_pib.frame_counter_mode, - .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].size = sizeof(ftdf_pib.frame_counter_mode), - .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].getFunc = NULL, - .attribute_defs[FTDF_PIB_FRAME_COUNTER_MODE].setFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].addr = &ftdf_pib.csl_sync_tx_margin, - .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].size = sizeof(ftdf_pib.csl_sync_tx_margin), - .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].getFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_SYNC_TX_MARGIN].setFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].addr = &ftdf_pib.csl_max_age_remote_info, - .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].size = sizeof(ftdf_pib.csl_max_age_remote_info), - .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].getFunc = NULL, - .attribute_defs[FTDF_PIB_CSL_MAX_AGE_REMOTE_INFO].setFunc = NULL, - .attribute_defs[FTDF_PIB_TSCH_ENABLED].addr = &ftdf_pib.tsch_enabled, - .attribute_defs[FTDF_PIB_TSCH_ENABLED].size = 0, - .attribute_defs[FTDF_PIB_TSCH_ENABLED].getFunc = NULL, - .attribute_defs[FTDF_PIB_TSCH_ENABLED].setFunc = NULL, -#ifdef FTDF_NO_CSL - .attribute_defs[FTDF_PIB_LE_ENABLED].addr = &ftdf_pib.le_enabled, - .attribute_defs[FTDF_PIB_LE_ENABLED].size = 0, - .attribute_defs[FTDF_PIB_LE_ENABLED].getFunc = NULL, - .attribute_defs[FTDF_PIB_LE_ENABLED].setFunc = NULL, -#else - .attribute_defs[FTDF_PIB_LE_ENABLED].addr = &ftdf_pib.le_enabled, - .attribute_defs[FTDF_PIB_LE_ENABLED].size = sizeof(ftdf_pib.le_enabled), - .attribute_defs[FTDF_PIB_LE_ENABLED].getFunc = NULL, - .attribute_defs[FTDF_PIB_LE_ENABLED].setFunc = ftdf_set_le_enabled, -#endif /* FTDF_NO_CSL */ -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].addr = &ftdf_pib.current_channel, - .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].size = sizeof(ftdf_pib.current_channel), - .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].getFunc = ftdf_get_current_channel, - .attribute_defs[FTDF_PIB_CURRENT_CHANNEL].setFunc = ftdf_set_current_channel, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].addr = (void*)&channels_supported, - .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].size = 0, - .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].getFunc = NULL, - .attribute_defs[FTDF_PIB_CHANNELS_SUPPORTED].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].addr = &ftdf_pib.tx_power_tolerance, - .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].size = sizeof(ftdf_pib.tx_power_tolerance), - .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].getFunc = NULL, - .attribute_defs[FTDF_PIB_TX_POWER_TOLERANCE].setFunc = NULL, - .attribute_defs[FTDF_PIB_TX_POWER].addr = &ftdf_pib.tx_power, - .attribute_defs[FTDF_PIB_TX_POWER].size = sizeof(ftdf_pib.tx_power), - .attribute_defs[FTDF_PIB_TX_POWER].getFunc = NULL, - .attribute_defs[FTDF_PIB_TX_POWER].setFunc = NULL, - .attribute_defs[FTDF_PIB_CCA_MODE].addr = &ftdf_pib.cca_mode, - .attribute_defs[FTDF_PIB_CCA_MODE].size = sizeof(ftdf_pib.cca_mode), - .attribute_defs[FTDF_PIB_CCA_MODE].getFunc = NULL, - .attribute_defs[FTDF_PIB_CCA_MODE].setFunc = NULL, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_CURRENT_PAGE].addr = &ftdf_pib.current_page, - .attribute_defs[FTDF_PIB_CURRENT_PAGE].size = 0, - .attribute_defs[FTDF_PIB_CURRENT_PAGE].getFunc = NULL, - .attribute_defs[FTDF_PIB_CURRENT_PAGE].setFunc = NULL, - .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].addr = &ftdf_pib.max_frame_duration, - .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].size = 0, - .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].getFunc = NULL, - .attribute_defs[FTDF_PIB_MAX_FRAME_DURATION].setFunc = NULL, - .attribute_defs[FTDF_PIB_SHR_DURATION].addr = &ftdf_pib.shr_duration, - .attribute_defs[FTDF_PIB_SHR_DURATION].size = 0, - .attribute_defs[FTDF_PIB_SHR_DURATION].getFunc = NULL, - .attribute_defs[FTDF_PIB_SHR_DURATION].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].addr = &ftdf_pib.traffic_counters, - .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].size = 0, - .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].getFunc = ftdf_get_lmac_traffic_counters, - .attribute_defs[FTDF_PIB_TRAFFIC_COUNTERS].setFunc = NULL, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_LE_CAPABLE].addr = &ftdf_pib.le_capable, - .attribute_defs[FTDF_PIB_LE_CAPABLE].size = 0, - .attribute_defs[FTDF_PIB_LE_CAPABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_LE_CAPABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_LL_CAPABLE].addr = &ftdf_pib.ll_capable, - .attribute_defs[FTDF_PIB_LL_CAPABLE].size = 0, - .attribute_defs[FTDF_PIB_LL_CAPABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_LL_CAPABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_DSME_CAPABLE].addr = &ftdf_pib.dsme_capable, - .attribute_defs[FTDF_PIB_DSME_CAPABLE].size = 0, - .attribute_defs[FTDF_PIB_DSME_CAPABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_DSME_CAPABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_RFID_CAPABLE].addr = &ftdf_pib.rfid_capable, - .attribute_defs[FTDF_PIB_RFID_CAPABLE].size = 0, - .attribute_defs[FTDF_PIB_RFID_CAPABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_RFID_CAPABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_AMCA_CAPABLE].addr = &ftdf_pib.amca_capable, - .attribute_defs[FTDF_PIB_AMCA_CAPABLE].size = 0, - .attribute_defs[FTDF_PIB_AMCA_CAPABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_AMCA_CAPABLE].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_METRICS_CAPABLE].addr = &ftdf_pib.metrics_capable, - .attribute_defs[FTDF_PIB_METRICS_CAPABLE].size = 0, - .attribute_defs[FTDF_PIB_METRICS_CAPABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_METRICS_CAPABLE].setFunc = NULL, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].addr = &ftdf_pib.ranging_supported, - .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].size = 0, - .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].getFunc = NULL, - .attribute_defs[FTDF_PIB_RANGING_SUPPORTED].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].addr = &ftdf_pib.keep_phy_enabled, - .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].size = sizeof(ftdf_pib.keep_phy_enabled), - .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].getFunc = ftdf_get_keep_phy_enabled, - .attribute_defs[FTDF_PIB_KEEP_PHY_ENABLED].setFunc = ftdf_set_keep_phy_enabled, - .attribute_defs[FTDF_PIB_METRICS_ENABLED].addr = &ftdf_pib.metrics_enabled, - .attribute_defs[FTDF_PIB_METRICS_ENABLED].size = sizeof(ftdf_pib.metrics_enabled), - .attribute_defs[FTDF_PIB_METRICS_ENABLED].getFunc = NULL, - .attribute_defs[FTDF_PIB_METRICS_ENABLED].setFunc = NULL, -#ifndef FTDF_LITE - .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].addr = &ftdf_pib.beacon_auto_respond, - .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].size = sizeof(ftdf_pib.beacon_auto_respond), - .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].getFunc = NULL, - .attribute_defs[FTDF_PIB_BEACON_AUTO_RESPOND].setFunc = NULL, - .attribute_defs[FTDF_PIB_TSCH_CAPABLE].addr = &ftdf_pib.tsch_capable, - .attribute_defs[FTDF_PIB_TSCH_CAPABLE].size = 0, - .attribute_defs[FTDF_PIB_TSCH_CAPABLE].getFunc = NULL, - .attribute_defs[FTDF_PIB_TSCH_CAPABLE].setFunc = NULL, - .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].addr = &ftdf_pib.ts_sync_correct_threshold, - .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].size = sizeof(ftdf_pib.ts_sync_correct_threshold), - .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].getFunc = NULL, - .attribute_defs[FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD].setFunc = NULL, -#endif /* !FTDF_LITE */ - .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].addr = &ftdf_pib.bo_irq_threshold, - .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].size = sizeof(ftdf_pib.bo_irq_threshold), - .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].getFunc = ftdf_get_bo_irq_threshold, - .attribute_defs[FTDF_PIB_BO_IRQ_THRESHOLD].setFunc = ftdf_set_bo_irq_threshold, - .attribute_defs[FTDF_PIB_PTI_CONFIG].addr = &ftdf_pib.pti_config, - .attribute_defs[FTDF_PIB_PTI_CONFIG].size = sizeof(ftdf_pib.pti_config), - .attribute_defs[FTDF_PIB_PTI_CONFIG].getFunc = NULL, - .attribute_defs[FTDF_PIB_PTI_CONFIG].setFunc = ftdf_set_pti_config, - .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].addr = &ftdf_pib.link_quality_mode, - .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].size = sizeof(ftdf_pib.link_quality_mode), - .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].getFunc = NULL, - .attribute_defs[FTDF_PIB_LINK_QUALITY_MODE].setFunc = NULL, -}; - -ftdf_boolean_t ftdf_transparent_mode __attribute__ ((section(".retention"))); -ftdf_bitmap32_t ftdf_transparent_mode_options __attribute__ ((section(".retention"))); -#if FTDF_DBG_BUS_ENABLE -ftdf_dbg_mode_t ftdf_dbg_mode __attribute__ ((section(".retention"))); -#endif -#if dg_configUSE_FTDF_DDPHY == 1 -uint16_t ftdf_ddphy_cca_reg __attribute__ ((section(".retention"))); -#endif -#ifndef FTDF_LITE -ftdf_buffer_t ftdf_req_buffers[FTDF_NR_OF_REQ_BUFFERS] __attribute__ ((section(".retention"))); -ftdf_queue_t ftdf_req_queue __attribute__ ((section(".retention"))); -ftdf_queue_t ftdf_free_queue __attribute__ ((section(".retention"))); -ftdf_pending_t ftdf_tx_pending_list[FTDF_NR_OF_REQ_BUFFERS] __attribute__ ((section(".retention"))); -ftdf_pending_tl_t ftdf_tx_pending_timer_list[FTDF_NR_OF_REQ_BUFFERS] __attribute__ ((section(".retention"))); -ftdf_pending_tl_t *ftdf_tx_pending_timer_head __attribute__ ((section(".retention"))); -ftdf_time_t ftdf_tx_pending_timer_lt __attribute__ ((section(".retention"))); -ftdf_time_t ftdf_tx_pending_timer_time __attribute__ ((section(".retention"))); -#endif /* !FTDF_LITE */ -#ifndef FTDF_PHY_API -ftdf_msg_buffer_t *ftdf_req_current __attribute__ ((section(".retention"))); -#endif -ftdf_size_t ftdf_nr_of_retries __attribute__ ((section(".retention"))); -#if FTDF_USE_SLEEP_DURING_BACKOFF -static ftdf_sdb_t ftdf_sdb __attribute__ ((section(".retention"))); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ -#ifndef FTDF_LITE -ftdf_boolean_t ftdf_is_pan_coordinator __attribute__ ((section(".retention"))); -ftdf_time_t ftdf_start_csl_sample_time __attribute__ ((section(".retention"))); -ftdf_rx_address_admin_t ftdf_rxa[FTDF_NR_OF_RX_ADDRS] __attribute__ ((section(".retention"))); -#endif /* !FTDF_LITE */ -ftdf_boolean_t ftdf_tx_in_progress __attribute__ ((section(".retention"))); -#ifndef FTDF_LITE -#ifndef FTDF_NO_CSL -ftdf_peer_csl_timing_t ftdf_peer_csl_timing[FTDF_NR_OF_CSL_PEERS] __attribute__ ((section(".retention"))); -ftdf_boolean_t ftdf_old_le_enabled __attribute__ ((section(".retention"))); -ftdf_time_t ftdf_rz_time __attribute__ ((section(".retention"))); -ftdf_short_address_t ftdf_send_frame_pending __attribute__ ((section(".retention"))); -#endif /* FTDF_NO_CSL */ -#endif /* !FTDF_LITE */ -uint32_t ftdf_cur_time[2] __attribute__ ((section(".retention"))); -ftdf_lmac_counters_t ftdf_lmac_counters __attribute__ ((section(".retention"))); -ftdf_frame_header_t ftdf_fh; -#ifndef FTDF_LITE -ftdf_security_header ftdf_sh; -ftdf_assoc_admin_t ftdf_aa; -#endif /* !FTDF_LITE */ - -#if dg_configCOEX_ENABLE_CONFIG -/* Packet traffic information used when FTDF is in RX enable. */ -static ftdf_pti_t ftdf_rx_pti __attribute__ ((section(".retention"))); -#endif -static void send_confirm(ftdf_status_t status, ftdf_msg_id_t msg_id); - -void ftdf_reset(int set_default_pib) -{ - if (set_default_pib) { - /* Reset PIB values to their default values */ - memset(&ftdf_pib, 0, sizeof(ftdf_pib)); - - ftdf_pib.ext_address = FTDF_GET_EXT_ADDRESS(); - ftdf_pib.ack_wait_duration = 0x36; -#ifndef FTDF_LITE - ftdf_pib.auto_request = FTDF_TRUE; - ftdf_pib.beacon_order = 15; - ftdf_pib.dsn = ftdf_pib.ext_address & 0xff; - ftdf_pib.bsn = ftdf_pib.ext_address & 0xff; - ftdf_pib.eb_sn = ftdf_pib.ext_address & 0xff; - ftdf_pib.coord_short_address = 0xffff; -#endif /* !FTDF_LITE */ - ftdf_pib.max_be = 5; - ftdf_pib.max_csma_backoffs = 4; - ftdf_pib.max_frame_total_wait_time = 1026; /* see asic_vol v40.100.2.30 PR2540 */ - ftdf_pib.max_frame_retries = 3; - ftdf_pib.min_be = 3; -#ifndef FTDF_LITE - ftdf_pib.lifs_period = 40; - ftdf_pib.sifs_period = 12; -#endif /* !FTDF_LITE */ - ftdf_pib.pan_id = 0xffff; -#ifndef FTDF_LITE - ftdf_pib.response_wait_time = 32; -#endif /* !FTDF_LITE */ - ftdf_pib.short_address = 0xffff; -#ifndef FTDF_LITE - ftdf_pib.superframe_order = 15; - ftdf_pib.timestamp_supported = FTDF_TRUE; - ftdf_pib.transaction_persistence_time = 0x1f4; - ftdf_pib.enh_ack_wait_duration = 0x360; - ftdf_pib.eb_auto_sa = FTDF_AUTO_FULL; -#endif /* !FTDF_LITE */ - ftdf_pib.current_channel = 11; - ftdf_pib.cca_mode = FTDF_CCA_MODE_1; -#ifndef FTDF_LITE - ftdf_pib.max_frame_duration = FTDF_TBD; - ftdf_pib.shr_duration = FTDF_TBD; - ftdf_pib.frame_counter_mode = 4; -#endif /* !FTDF_LITE */ - ftdf_pib.metrics_capable = FTDF_TRUE; -#ifndef FTDF_LITE - ftdf_pib.beacon_auto_respond = FTDF_TRUE; -#endif /* !FTDF_LITE */ - ftdf_pib.performance_metrics.counter_octets = 4; /* 32 bit counters */ -#ifndef FTDF_LITE - ftdf_pib.join_priority = 1; - ftdf_pib.slotframe_table.slotframe_entries = ftdf_slotframe_table; - ftdf_pib.link_table.link_entries = ftdf_link_table; - ftdf_pib.timeslot_template.ts_cca_offset = 1800; - ftdf_pib.timeslot_template.ts_cca = 128; - ftdf_pib.timeslot_template.ts_tx_offset = 2120; - ftdf_pib.timeslot_template.ts_rx_offset = 1020; - ftdf_pib.timeslot_template.ts_rx_ack_delay = 800; - ftdf_pib.timeslot_template.ts_tx_ack_delay = 1000; - ftdf_pib.timeslot_template.ts_rx_wait = 2200; - ftdf_pib.timeslot_template.ts_ack_wait = 400; - ftdf_pib.timeslot_template.ts_rx_tx = 192; - ftdf_pib.timeslot_template.ts_max_ack = 2400; - ftdf_pib.timeslot_template.ts_max_ts = 4256; - ftdf_pib.timeslot_template.ts_timeslot_length = 10000; - ftdf_pib.ts_sync_correct_threshold = 220; - ftdf_pib.hopping_sequence_length = 16; - int i; - for (i = 0; i < FTDF_PTIS; i++) { - ftdf_pib.pti_config.ptis[i] = 0; - } -#ifdef FTDF_NO_CSL - ftdf_pib.le_capable = FTDF_FALSE; -#else - ftdf_pib.le_capable = FTDF_TRUE; -#endif /* FTDF_NO_CSL */ -#ifdef FTDF_NO_TSCH - ftdf_pib.tsch_capable = FTDF_FALSE; -#else - ftdf_pib.tsch_capable = FTDF_TRUE; -#endif /* FTDF_NO_TSCH */ - - int n; - - for (n = 0; n < FTDF_MAX_HOPPING_SEQUENCE_LENGTH; n++) { - ftdf_pib.hopping_sequence_list[n] = n + 11; - } -#endif /* !FTDF_LITE */ - - ftdf_transparent_mode = FTDF_FALSE; -#ifndef FTDF_LITE - ftdf_is_pan_coordinator = FTDF_FALSE; -#endif /* !FTDF_LITE */ - ftdf_lmac_counters.fcs_error_cnt = 0; - ftdf_lmac_counters.tx_std_ack_cnt = 0; - ftdf_lmac_counters.rx_std_ack_cnt = 0; - -#ifndef FTDF_LITE - memset(ftdf_pib.default_key_source, 0xff, 8); -#endif /* !FTDF_LITE */ - ftdf_pib.bo_irq_threshold = FTDF_BO_IRQ_THRESHOLD; - ftdf_pib.link_quality_mode = FTDF_LINK_QUALITY_MODE_RSSI; - } - - ftdf_init_queues(); - - FTDF->FTDF_LMACRESET_REG = REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_CONTROL) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_RX) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_TX) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_AHB) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_OREG) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_TSTIM) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_SEC) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_COUNT) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACRESET_TIMCTRL) | - REG_MSK(FTDF, FTDF_LMACRESET_REG, LMACGLOBRESET_COUNT); - - uint32_t wait = 0; - - while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) { - wait++; - } - - REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_OS_REG, WAKEUPTIMERENABLE_CLEAR, 1); - - while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, WAKEUPTIMERENABLESTATUS)) {} - - REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_OS_REG, WAKEUPTIMERENABLE_SET, 1); - - while ((REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, WAKEUPTIMERENABLESTATUS)) == 0) {} - -#ifndef FTDF_LITE - int n; - -#ifndef FTDF_NO_CSL - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { - ftdf_peer_csl_timing[n].addr = 0xffff; - } - - ftdf_old_le_enabled = FTDF_FALSE; - ftdf_wake_up_enable_le = FTDF_FALSE; - ftdf_send_frame_pending = 0xfffe; -#endif /* FTDF_NO_CSL */ -#endif /* !FTDF_LITE */ - ftdf_tx_in_progress = FTDF_FALSE; - - ftdf_init_cur_time64(); -#ifndef FTDF_NO_TSCH - ftdf_init_tsch_retries(); - ftdf_init_backoff(); -#endif /* FTDF_NO_TSCH */ - -#ifndef FTDF_LITE - for (n = 0; n < FTDF_NR_OF_RX_ADDRS; n++) { - ftdf_rxa[n].addr_mode = FTDF_NO_ADDRESS; - ftdf_rxa[n].dsn_valid = FTDF_FALSE; - ftdf_rxa[n].bsn_valid = FTDF_FALSE; - ftdf_rxa[n].ebsn_valid = FTDF_FALSE; - } - -#ifndef FTDF_NO_TSCH - for (n = 0; n < FTDF_NR_OF_NEIGHBORS; n++) { - ftdf_neighbor_table[n].dst_addr = 0xffff; - } -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ -#if FTDF_USE_SLEEP_DURING_BACKOFF - ftdf_sdb_fsm_reset(); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - ftdf_init_lmac(); - -#ifndef FTDF_NO_CSL - ftdf_rz_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); -#endif /* FTDF_NO_CSL */ - -#if dg_configUSE_FTDF_DDPHY == 1 - ftdf_ddphy_set(0); -#endif -} - - -#ifndef FTDF_LITE -void ftdf_cleanup_queues(void) -{ - while (!ftdf_is_queue_empty(&ftdf_req_queue)) { - ftdf_msg_buffer_t *request = ftdf_dequeue_req_tail(&ftdf_req_queue); - if (request) { - ad_ftdf_rel_msg_data(request); - } - } - - int n; - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { - while (!ftdf_is_queue_empty(&ftdf_tx_pending_list[n].queue)) { - ftdf_msg_buffer_t *request = ftdf_dequeue_req_tail(&ftdf_tx_pending_list[n].queue); - if (request) { - ad_ftdf_rel_msg_data(request); - } - } - } -} -#endif /* !FTDF_LITE */ - -#ifndef FTDF_PHY_API -void ftdf_process_reset_request(ftdf_reset_request_t *reset_request) -{ -#ifndef FTDF_LITE - ftdf_cleanup_queues(); -#endif - ftdf_reset(reset_request->set_default_pib); - ftdf_reset_confirm_t* resetConfirm = - (ftdf_reset_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_reset_confirm_t)); - - resetConfirm->msg_id = FTDF_RESET_CONFIRM; - resetConfirm->status = FTDF_SUCCESS; - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)reset_request); - - FTDF_RCV_MSG((ftdf_msg_buffer_t*)resetConfirm); -} -#endif /* FTDF_PHY_API */ - -void ftdf_init_lmac(void) -{ - ftdf_pib_attribute_t pib_attribute; - - for (pib_attribute = 1; pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES; pib_attribute++) { - if (pib_attribute_table.attribute_defs[pib_attribute].setFunc != NULL) { - pib_attribute_table.attribute_defs[pib_attribute].setFunc(); - } - } - - if (ftdf_transparent_mode == FTDF_TRUE) { - ftdf_enable_transparent_mode(FTDF_TRUE, ftdf_transparent_mode_options); - } - -#ifndef FTDF_LITE - if (ftdf_is_pan_coordinator) { - REG_SETF(FTDF, FTDF_GLOB_CONTROL_0_REG, ISPANCOORDINATOR, 1); - } -#endif /* !FTDF_LITE */ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, CCAIDLEWAIT, 192); - - FTDF->FTDF_TX_CLEAR_OS_REG = REG_MSK(FTDF, FTDF_TX_CLEAR_OS_REG, TX_FLAG_CLEAR); - - uint32_t phy_params = 0; - REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTXSTARTUP, phy_params, FTDF_PHYTXSTARTUP); - REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTXLATENCY, phy_params, FTDF_PHYTXLATENCY); - REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTXFINISH, phy_params, FTDF_PHYTXFINISH); - REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_2_REG, PHYTRXWAIT, phy_params, FTDF_PHYTRXWAIT); - FTDF->FTDF_PHY_PARAMETERS_2_REG = phy_params; - - phy_params = 0; - REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_3_REG, PHYRXSTARTUP, phy_params, FTDF_PHYRXSTARTUP); - REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_3_REG, PHYRXLATENCY, phy_params, FTDF_PHYRXLATENCY); - REG_SET_FIELD(FTDF, FTDF_PHY_PARAMETERS_3_REG, PHYENABLE, phy_params, FTDF_PHYENABLE); - FTDF->FTDF_PHY_PARAMETERS_3_REG = phy_params; - - - REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM, - (FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE)); - - uint32_t rx_mask = REG_MSK(FTDF, FTDF_RX_MASK_REG, RXSOF_M) | - REG_MSK(FTDF, FTDF_RX_MASK_REG, RX_OVERFLOW_M) | - REG_MSK(FTDF, FTDF_RX_MASK_REG, RX_BUF_AVAIL_M) | - REG_MSK(FTDF, FTDF_RX_MASK_REG, RXBYTE_M); - FTDF->FTDF_RX_MASK_REG = rx_mask; - - FTDF->FTDF_LMAC_MASK_REG = REG_MSK(FTDF, FTDF_LMAC_MASK_REG, RXTIMEREXPIRED_M); - - uint32_t lmac_ctrl_mask = REG_MSK(FTDF, FTDF_LMAC_CONTROL_MASK_REG, SYMBOLTIMETHR_M) | - REG_MSK(FTDF, FTDF_LMAC_CONTROL_MASK_REG, SYMBOLTIME2THR_M) | - REG_MSK(FTDF, FTDF_LMAC_CONTROL_MASK_REG, SYNCTIMESTAMP_M); - FTDF->FTDF_LMAC_CONTROL_MASK_REG = lmac_ctrl_mask; - - FTDF->FTDF_TX_FLAG_CLEAR_M_0_REG |= REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_M_0_REG, TX_FLAG_CLEAR_M); - FTDF->FTDF_TX_FLAG_CLEAR_M_1_REG |= REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_M_1_REG, TX_FLAG_CLEAR_M); - -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - ftdf_fppr_reset(); - ftdf_fppr_set_mode(FTDF_TRUE, FTDF_FALSE, FTDF_FALSE); -#else - ftdf_fppr_set_mode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); -#endif /* #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ -#if FTDF_USE_SLEEP_DURING_BACKOFF - /* Unmask long BO interrupt. */ - REG_SETF(FTDF, FTDF_LMAC_MASK_REG, CSMA_CA_BO_THR_M, 1); -#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ - /* Set BO threshold. */ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_BO_THRESHOLD, FTDF_BO_IRQ_THRESHOLD); - - /* Mask long BO interrupt. */ - REG_SETF(FTDF, FTDF_LMAC_MASK_REG, CSMA_CA_BO_THR_M, 0); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ -#if FTDF_USE_LPDP == 1 - ftdf_lpdp_enable(FTDF_TRUE); -#endif /* #if FTDF_USE_LPDP == 1 */ -} - -#ifdef FTDF_PHY_API -ftdf_pib_attribute_value_t *ftdf_get_value(ftdf_pib_attribute_t pib_attribute) -{ - - if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && - (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { - - /* Update PIB attribute with current LMAC status if a getFunc is defined */ - if (pib_attribute_table.attribute_defs[pib_attribute].getFunc != NULL) { - pib_attribute_table.attribute_defs[pib_attribute].getFunc(); - } - - return pib_attribute_table.attribute_defs[pib_attribute].addr; - } - - return NULL; -} - -ftdf_status_t ftdf_set_value(ftdf_pib_attribute_t pib_attribute, const ftdf_pib_attribute_value_t *pib_attribute_value) -{ - if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && - (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { - - if (pib_attribute_table.attribute_defs[pib_attribute].size != 0) { - memcpy(pib_attribute_table.attribute_defs[pib_attribute].addr, - pib_attribute_value, - pib_attribute_table.attribute_defs[pib_attribute].size); - - /* Update LMAC with new PIB attribute value if a setFunc is defined */ - if (pib_attribute_table.attribute_defs[pib_attribute].setFunc != NULL) { - pib_attribute_table.attribute_defs[pib_attribute].setFunc(); - } - - return FTDF_SUCCESS; - - } else { - return FTDF_READ_ONLY; - } - } - - return FTDF_UNSUPPORTED_ATTRIBUTE; -} - -#else /* FTDF_PHY_API */ -void ftdf_process_get_request(ftdf_get_request_t *get_request) -{ - ftdf_get_confirm_t *get_confirm = - (ftdf_get_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_get_confirm_t)); - ftdf_pib_attribute_t pib_attribute = get_request->pib_attribute; - - get_confirm->msg_id = FTDF_GET_CONFIRM; - get_confirm->pib_attribute = pib_attribute; - - if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && - (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { - - /* Update PIB attribute with current LMAC status if a getFunc is defined */ - if (pib_attribute_table.attribute_defs[pib_attribute].getFunc != NULL) { - pib_attribute_table.attribute_defs[pib_attribute].getFunc(); - } - - get_confirm->status = FTDF_SUCCESS; - get_confirm->pib_attribute_value = - pib_attribute_table.attribute_defs[pib_attribute].addr; - - } else { - get_confirm->status = FTDF_UNSUPPORTED_ATTRIBUTE; - } - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)get_request); - - FTDF_RCV_MSG((ftdf_msg_buffer_t*)get_confirm); -} - -void ftdf_process_set_request(ftdf_set_request_t *set_request) -{ - ftdf_set_confirm_t *set_confirm = - (ftdf_set_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_set_confirm_t)); - ftdf_pib_attribute_t pib_attribute = set_request->pib_attribute; - - set_confirm->msg_id = FTDF_SET_CONFIRM; - set_confirm->pib_attribute = pib_attribute; - - if ((pib_attribute <= FTDF_NR_OF_PIB_ATTRIBUTES) && - (pib_attribute_table.attribute_defs[pib_attribute].addr != NULL)) { - - if (pib_attribute_table.attribute_defs[pib_attribute].size != 0) { - - set_confirm->status = FTDF_SUCCESS; - memcpy(pib_attribute_table.attribute_defs[pib_attribute].addr, - set_request->pib_attribute_value, - pib_attribute_table.attribute_defs[pib_attribute].size); - - /* Update LMAC with new PIB attribute value if a setFunc is defined */ - if (pib_attribute_table.attribute_defs[pib_attribute].setFunc != NULL) { - pib_attribute_table.attribute_defs[pib_attribute].setFunc(); - } - - } else { - set_confirm->status = FTDF_READ_ONLY; - } - - } else { - set_confirm->status = FTDF_UNSUPPORTED_ATTRIBUTE; - } - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)set_request); - - FTDF_RCV_MSG((ftdf_msg_buffer_t*)set_confirm); -} - -void ftdf_send_comm_status_indication(ftdf_msg_buffer_t *request, - ftdf_status_t status, - ftdf_pan_id_t pan_id, - ftdf_address_mode_t src_addr_mode, - ftdf_address_t src_addr, - ftdf_address_mode_t dst_addr_mode, - ftdf_address_t dst_addr, - ftdf_security_level_t security_level, - ftdf_key_id_mode_t key_id_mode, - ftdf_octet_t *key_source, - ftdf_key_index_t key_index) -{ - ftdf_comm_status_indication_t *comm_status = - (ftdf_comm_status_indication_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_comm_status_indication_t)); - - comm_status->msg_id = FTDF_COMM_STATUS_INDICATION; - comm_status->pan_id = pan_id; - comm_status->src_addr_mode = src_addr_mode; - comm_status->src_addr = src_addr; - comm_status->dst_addr_mode = dst_addr_mode; - comm_status->dst_addr = dst_addr; - comm_status->status = status; - comm_status->security_level = security_level; - comm_status->key_id_mode = key_id_mode; - comm_status->key_index = key_index; - - uint8_t n; - - if (security_level != 0) { - if (key_id_mode == 0x2) { - for (n = 0; n < 4; n++) { - comm_status->key_source[n] = key_source[n]; - } - } else if (key_id_mode == 0x3) { - for (n = 0; n < 8; n++) { - comm_status->key_source[n] = key_source[n]; - } - } - } -#ifndef FTDF_LITE - if (request && ((request->msg_id == FTDF_ORPHAN_RESPONSE) || - (request->msg_id == FTDF_ASSOCIATE_RESPONSE))) { - - if (ftdf_req_current == request) { - ftdf_req_current = NULL; - } - - FTDF_REL_MSG_BUFFER(request); - FTDF_RCV_MSG((ftdf_msg_buffer_t*)comm_status); -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - ftdf_fp_fsm_clear_pending(); -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - ftdf_process_next_request(); - return; - } -#endif /* !FTDF_LITE */ - FTDF_RCV_MSG((ftdf_msg_buffer_t*)comm_status); -} -#endif /* FTDF_PHY_API */ - -#ifndef FTDF_LITE -ftdf_octet_t* ftdf_add_frame_header(ftdf_octet_t *tx_ptr, - ftdf_frame_header_t *frame_header, - ftdf_data_length_t msdu_length) -{ - uint8_t frame_version; - uint8_t long_frame_control = 0x00; - ftdf_boolean_t pan_id_compression = FTDF_FALSE; - ftdf_bitmap8_t options = frame_header->options; - ftdf_boolean_t secure = options & FTDF_OPT_SECURITY_ENABLED; - ftdf_boolean_t frame_pending = options & FTDF_OPT_FRAME_PENDING; - ftdf_boolean_t ack_tx = options & FTDF_OPT_ACK_REQUESTED; - ftdf_boolean_t pan_id_present = options & FTDF_OPT_PAN_ID_PRESENT; - ftdf_boolean_t seq_nr_suppressed = options & FTDF_OPT_SEQ_NR_SUPPRESSED; - ftdf_boolean_t ies_included = options & FTDF_OPT_IES_PRESENT; - ftdf_frame_type_t frame_type = frame_header->frame_type; - ftdf_address_mode_t dst_addr_mode = frame_header->dst_addr_mode; - ftdf_address_mode_t src_addr_mode = frame_header->src_addr_mode; - ftdf_pan_id_t dstpan_id = frame_header->dst_pan_id; - - if (frame_type == FTDF_MULTIPURPOSE_FRAME) { - - if (options & (FTDF_OPT_SECURITY_ENABLED | FTDF_OPT_ACK_REQUESTED | - FTDF_OPT_PAN_ID_PRESENT | FTDF_OPT_IES_PRESENT | - FTDF_OPT_SEQ_NR_SUPPRESSED | FTDF_OPT_FRAME_PENDING)) { - - long_frame_control = 0x08; - } - - /* Frame control field byte 1 */ - *tx_ptr++ = 0x05 | long_frame_control | dst_addr_mode << 4 | src_addr_mode << 6; - - if (long_frame_control) { - /* Frame control field byte 2 */ - *tx_ptr++ = (pan_id_present ? 0x01 : 0x00) | - (secure ? 0x02 : 0x00) | - (seq_nr_suppressed ? 0x04 : 0x00) | - (frame_pending ? 0x08 : 0x00) | - (ack_tx ? 0x40 : 0x00) | - (ies_included ? 0x80 : 0x00); - } - - } else { - // if (panIdPresent || iesIncluded || seqNrSuppressed || (options & FTDF_OPT_ENHANCED) || ftdf_pib.tsch_enabled) - if (pan_id_present || ies_included || seq_nr_suppressed || (options & FTDF_OPT_ENHANCED)) { - frame_version = 0x02; - } else { - - if (secure || (msdu_length > FTDF_MAX_MAC_SAFE_PAYLOAD_SIZE)) { - frame_version = 0x01; - } else { - frame_version = 0x00; - } - } - - if (frame_version < 0x02) { - if ((dst_addr_mode != FTDF_NO_ADDRESS) && - (src_addr_mode != FTDF_NO_ADDRESS) && - (dstpan_id == frame_header->src_pan_id)) { - - pan_id_compression = FTDF_TRUE; - } - - } else { - pan_id_compression = pan_id_present; - } - - /* Frame control field byte 1 */ - *tx_ptr++ = (frame_type & 0x7) | - (secure ? 0x08 : 0x00) | - (frame_pending ? 0x10 : 0x00) | - (ack_tx ? 0x20 : 0x00) | - (pan_id_compression ? 0x40 : 0x00); - - /* Frame control field byte 2 */ - *tx_ptr++ = (seq_nr_suppressed ? 0x01 : 0x00) | - (ies_included ? 0x02 : 0x00) | - (dst_addr_mode << 2) | - (frame_version << 4) | - (src_addr_mode << 6); - } - - if (!seq_nr_suppressed) { - *tx_ptr++ = frame_header->sn; - } - - ftdf_boolean_t add_dstpan_id = FTDF_FALSE; - - if (frame_type == FTDF_MULTIPURPOSE_FRAME) { - if (pan_id_present) { - add_dstpan_id = FTDF_TRUE; - } - - } else { - - if (frame_version < 0x02) { - if (dst_addr_mode != FTDF_NO_ADDRESS) { - add_dstpan_id = FTDF_TRUE; - } - - } else { - - /* See Table 2a "PAN ID Compression" of IEEE 802.15.4-2011 for more details */ - if (((src_addr_mode == FTDF_NO_ADDRESS) && - (dst_addr_mode == FTDF_NO_ADDRESS) && pan_id_compression) || - ((src_addr_mode == FTDF_NO_ADDRESS) && - (dst_addr_mode != FTDF_NO_ADDRESS && !pan_id_compression)) || - ((src_addr_mode != FTDF_NO_ADDRESS) && - (dst_addr_mode != FTDF_NO_ADDRESS && !pan_id_compression))) { - - add_dstpan_id = FTDF_TRUE; - } - } - } - - if (add_dstpan_id) { - ftdf_octet_t *pan_idPtr = (ftdf_octet_t*)&dstpan_id; - - *tx_ptr++ = *pan_idPtr++; - *tx_ptr++ = *pan_idPtr; - } - - ftdf_address_t dst_addr = frame_header->dst_addr; - - if (dst_addr_mode == FTDF_SIMPLE_ADDRESS) { - *tx_ptr++ = dst_addr.simple_address; - } else if (dst_addr_mode == FTDF_SHORT_ADDRESS) { - ftdf_octet_t* short_address_ptr = (ftdf_octet_t*)&dst_addr.short_address; - - *tx_ptr++ = *short_address_ptr++; - *tx_ptr++ = *short_address_ptr; - } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { - ftdf_octet_t* ext_address_ptr = (ftdf_octet_t*)&dst_addr.ext_address; - int n; - - for (n = 0; n < 8; n++) { - *tx_ptr++ = *ext_address_ptr++; - } - } - - ftdf_boolean_t add_srcpan_id = FTDF_FALSE; - - if (frame_type != FTDF_MULTIPURPOSE_FRAME) { - if (frame_version < 0x02) { - if ((src_addr_mode != FTDF_NO_ADDRESS) && !pan_id_compression) { - add_srcpan_id = FTDF_TRUE; - } - - } else { - - /* See Table 2a "PAN ID Compression" of IEEE 802.15.4-2011 for more details */ - if ((src_addr_mode != FTDF_NO_ADDRESS) && (dst_addr_mode == FTDF_NO_ADDRESS) && - !pan_id_compression) { - - add_srcpan_id = FTDF_TRUE; - } - } - } - - if (add_srcpan_id) { - ftdf_octet_t* pan_idPtr = (ftdf_octet_t*)&frame_header->src_pan_id; - - *tx_ptr++ = *pan_idPtr++; - *tx_ptr++ = *pan_idPtr; - } - - if (src_addr_mode == FTDF_SIMPLE_ADDRESS) { - *tx_ptr++ = ftdf_pib.simple_address; - } - else if (src_addr_mode == FTDF_SHORT_ADDRESS) { - ftdf_octet_t* short_address_ptr = (ftdf_octet_t*)&ftdf_pib.short_address; - - *tx_ptr++ = *short_address_ptr++; - *tx_ptr++ = *short_address_ptr; - } - else if (src_addr_mode == FTDF_EXTENDED_ADDRESS) { - ftdf_octet_t* ext_address_ptr = (ftdf_octet_t*)&ftdf_pib.ext_address; - int n; - - for (n = 0; n < 8; n++) { - *tx_ptr++ = *ext_address_ptr++; - } - } - - return tx_ptr; -} -#endif /* !FTDF_LITE */ - -ftdf_pti_t ftdf_get_rx_pti(void) -{ -#if dg_configCOEX_ENABLE_CONFIG - ftdf_pti_t rx_pti; - ftdf_critical_var(); - ftdf_enter_critical(); - rx_pti = ftdf_rx_pti; - ftdf_exit_critical(); - - return rx_pti; -#else - return 0; -#endif -} - -#ifdef FTDF_PHY_API -void ftdf_rx_enable(ftdf_time_t rx_on_duration) -{ -#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI - /* We do not force decision here. It will be automatically made when FTDF begins - * transaction. - */ - hw_coex_update_ftdf_pti((hw_coex_pti_t) ftdf_get_rx_pti(), NULL, false); -#endif - - ftdf_set_link_quality_mode(); - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 0); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXONDURATION, rx_on_duration); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 1); -} -#else -void ftdf_process_rx_enable_request(ftdf_rx_enable_request_t *rx_enable_request) -{ - ftdf_set_link_quality_mode(); - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 0); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXONDURATION, rx_enable_request->rx_on_duration); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 1); - - ftdf_rx_enable_confirm_t *rx_enable_confirm = - (ftdf_rx_enable_confirm_t *) FTDF_GET_MSG_BUFFER(sizeof(ftdf_rx_enable_confirm_t)); - - rx_enable_confirm->msg_id = FTDF_RX_ENABLE_CONFIRM; - rx_enable_confirm->status = FTDF_SUCCESS; - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t *)rx_enable_request); - FTDF_RCV_MSG((ftdf_msg_buffer_t *)rx_enable_confirm); -} -#endif /* FTDF_PHY_API */ - -ftdf_octet_t *ftdf_get_frame_header(ftdf_octet_t *rx_buffer, - ftdf_frame_header_t* frame_header) -{ - ftdf_frame_type_t frame_type = *rx_buffer & 0x07; - uint8_t frame_version = 0x00; - ftdf_bitmap8_t options = 0; - ftdf_address_mode_t dst_addr_mode; - ftdf_address_mode_t src_addr_mode; - ftdf_boolean_t pan_id_compression = FTDF_FALSE; - ftdf_boolean_t pan_id_present = FTDF_FALSE; - - if (frame_type == FTDF_MULTIPURPOSE_FRAME) { - dst_addr_mode = (*rx_buffer & 0x30) >> 4; - src_addr_mode = (*rx_buffer & 0xc0) >> 6; - - /* Check Long Frame Control */ - if (*rx_buffer & 0x08) { - rx_buffer++; - - pan_id_present = *rx_buffer & 0x01; - - if (*rx_buffer & 0x02) { - options |= FTDF_OPT_SECURITY_ENABLED; - } - - if (*rx_buffer & 0x04) { - options |= FTDF_OPT_SEQ_NR_SUPPRESSED; - } - - if (*rx_buffer & 0x08) { - options |= FTDF_OPT_FRAME_PENDING; - } - - if (*rx_buffer & 0x40) { - options |= FTDF_OPT_ACK_REQUESTED; - } - - if (*rx_buffer & 0x80) { - options |= FTDF_OPT_IES_PRESENT; - } - - frame_version = 0x00; - - frame_header->frame_version = FTDF_FRAME_VERSION_E; - - rx_buffer++; - } else { - rx_buffer++; - } - - } else { - - if (*rx_buffer & 0x08) { - options |= FTDF_OPT_SECURITY_ENABLED; - } - - if (*rx_buffer & 0x10) { - options |= FTDF_OPT_FRAME_PENDING; - } - - if (*rx_buffer & 0x20) { - options |= FTDF_OPT_ACK_REQUESTED; - } - - pan_id_compression = *rx_buffer & 0x40; - - rx_buffer++; - - frame_version = (*rx_buffer & 0x30) >> 4; - - if (frame_version == 0x02) { - if (*rx_buffer & 0x01) { - options |= FTDF_OPT_SEQ_NR_SUPPRESSED; - } - - if (*rx_buffer & 0x02) { - options |= FTDF_OPT_IES_PRESENT; - } - - frame_header->frame_version = FTDF_FRAME_VERSION_E; - } else if (frame_version == 0x01) { - frame_header->frame_version = FTDF_FRAME_VERSION_2011; - } else if (frame_version == 0x00) { - frame_header->frame_version = FTDF_FRAME_VERSION_2003; - } else { - frame_header->frame_version = FTDF_FRAME_VERSION_NOT_SUPPORTED; - return rx_buffer; - } - - dst_addr_mode = (*rx_buffer & 0x0c) >> 2; - src_addr_mode = (*rx_buffer & 0xc0) >> 6; - - rx_buffer++; - } - - if ((options & FTDF_OPT_SEQ_NR_SUPPRESSED) == 0) { - frame_header->sn = *rx_buffer++; - } - - ftdf_boolean_t has_dstpan_id = FTDF_FALSE; - - if (frame_type == FTDF_MULTIPURPOSE_FRAME) { - has_dstpan_id = pan_id_present; - } else { - - if (frame_version < 0x02) { - if (dst_addr_mode != FTDF_NO_ADDRESS) { - has_dstpan_id = FTDF_TRUE; - } - - } else { - - if (((src_addr_mode == FTDF_NO_ADDRESS) && - (dst_addr_mode == FTDF_NO_ADDRESS) && pan_id_compression) || - ((src_addr_mode == FTDF_NO_ADDRESS) && - (dst_addr_mode != FTDF_NO_ADDRESS) && !pan_id_compression) || - ((src_addr_mode != FTDF_NO_ADDRESS) && - (dst_addr_mode != FTDF_NO_ADDRESS) && !pan_id_compression)) { - - has_dstpan_id = FTDF_TRUE; - } - } - } - - if (has_dstpan_id) { - ftdf_octet_t *pan_id_ptr = (ftdf_octet_t*)&frame_header->dst_pan_id; - - *pan_id_ptr++ = *rx_buffer++; - *pan_id_ptr = *rx_buffer++; - } - - if (dst_addr_mode == FTDF_SIMPLE_ADDRESS) { - frame_header->dst_addr.simple_address = *rx_buffer++; - } else if (dst_addr_mode == FTDF_SHORT_ADDRESS) { - ftdf_octet_t *short_address_ptr = (ftdf_octet_t*)&frame_header->dst_addr.short_address; - - *short_address_ptr++ = *rx_buffer++; - *short_address_ptr = *rx_buffer++; - } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { - ftdf_octet_t *ext_address_ptr = (ftdf_octet_t*)&frame_header->dst_addr.ext_address; - int n; - - for (n = 0; n < 8; n++) { - *ext_address_ptr++ = *rx_buffer++; - } - } - - ftdf_boolean_t has_srcpan_id = FTDF_FALSE; - - if (frame_version < 0x02 && frame_type != FTDF_MULTIPURPOSE_FRAME) { - if (src_addr_mode != FTDF_NO_ADDRESS && !pan_id_compression) { - has_srcpan_id = FTDF_TRUE; - } - - } else { - - if ((src_addr_mode != FTDF_NO_ADDRESS) && (dst_addr_mode == FTDF_NO_ADDRESS) && - !pan_id_compression) { - - has_srcpan_id = FTDF_TRUE; - } - } - - if (has_srcpan_id) { - ftdf_octet_t *pan_id_ptr = (ftdf_octet_t*)&frame_header->src_pan_id; - - *pan_id_ptr++ = *rx_buffer++; - *pan_id_ptr = *rx_buffer++; - } else { - frame_header->src_pan_id = frame_header->dst_pan_id; - } - - if (src_addr_mode == FTDF_SIMPLE_ADDRESS) { - frame_header->src_addr.simple_address = *rx_buffer++; - } else if (src_addr_mode == FTDF_SHORT_ADDRESS) { - ftdf_octet_t *short_address_ptr = - (ftdf_octet_t*)&frame_header->src_addr.short_address; - - *short_address_ptr++ = *rx_buffer++; - *short_address_ptr = *rx_buffer++; - } else if (src_addr_mode == FTDF_EXTENDED_ADDRESS) { - ftdf_octet_t* ext_address_ptr = (ftdf_octet_t*)&frame_header->src_addr.ext_address; - int n; - - for (n = 0; n < 8; n++) { - *ext_address_ptr++ = *rx_buffer++; - } - } - - frame_header->frame_type = frame_type; - frame_header->options = options; - frame_header->dst_addr_mode = dst_addr_mode; - frame_header->src_addr_mode = src_addr_mode; - - return rx_buffer; -} - -#ifndef FTDF_LITE -void ftdf_process_next_request(void) -{ -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - ftdf_msg_buffer_t *request = ftdf_tsch_get_pending(ftdf_tsch_slot_link->request); - - ftdf_tsch_slot_link->request = NULL; - - ftdf_schedule_tsch(request); - - return; - } -#endif /* FTDF_NO_TSCH */ - - while (ftdf_req_current == NULL) { - ftdf_msg_buffer_t *request = ftdf_dequeue_req_tail(&ftdf_req_queue); - - if (request) { - ftdf_process_request(request); - } else { - break; - } - } -} -#endif /* !FTDF_LITE */ - -static void process_rx_frame(int read_buf) -{ - static ftdf_pan_descriptor_t pan_descriptor; - static ftdf_address_t pend_addr_list[7]; - - ftdf_frame_header_t *frame_header = &ftdf_fh; -#ifndef FTDF_LITE - ftdf_security_header *security_header = &ftdf_sh; -#endif /* !FTDF_LITE */ - - uint8_t pend_addr_spec = 0; - - ftdf_octet_t *rx_buffer = - (ftdf_octet_t*) (&FTDF->FTDF_RX_FIFO_0_0_REG) + (read_buf * FTDF_BUFFER_LENGTH); - ftdf_octet_t *rx_ptr = rx_buffer; - ftdf_data_length_t frameLen = *rx_ptr++; - - if (ftdf_transparent_mode) { - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.rx_success_count++; - } - - uint32_t rx_meta_1 = 0; - - ftdf_bitmap32_t status = FTDF_TRANSPARENT_RCV_SUCCESSFUL; - - switch (read_buf) { - case 0: - rx_meta_1 = FTDF->FTDF_RX_META_1_0_REG; - break; - case 1: - rx_meta_1 = FTDF->FTDF_RX_META_1_1_REG; - break; - case 2: - rx_meta_1 = FTDF->FTDF_RX_META_1_2_REG; - break; - case 3: - rx_meta_1 = FTDF->FTDF_RX_META_1_3_REG; - break; - case 4: - rx_meta_1 = FTDF->FTDF_RX_META_1_4_REG; - break; - case 5: - rx_meta_1 = FTDF->FTDF_RX_META_1_5_REG; - break; - case 6: - rx_meta_1 = FTDF->FTDF_RX_META_1_6_REG; - break; - case 7: - rx_meta_1 = FTDF->FTDF_RX_META_1_7_REG; - break; - default: - OS_ASSERT(0); - } - - status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, CRC16_ERROR) ? - FTDF_TRANSPARENT_RCV_CRC_ERROR : 0; - status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, RES_FRM_TYPE_ERROR) ? - FTDF_TRANSPARENT_RCV_RES_FRAMETYPE : 0; - status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, RES_FRM_VERSION_ERROR) ? - FTDF_TRANSPARENT_RCV_RES_FRAME_VERSION : 0; - status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, DPANID_ERROR) ? - FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID : 0; - status |= rx_meta_1 & REG_MSK(FTDF, FTDF_RX_META_1_0_REG, DADDR_ERROR) ? - FTDF_TRANSPARENT_RCV_UNEXP_DST_ADDR : 0; - -#ifdef FTDF_PASS_ACK_FRAME - FTDF_RCV_FRAME_TRANSPARENT(frameLen, rx_ptr, status, - REG_GET_FIELD(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR, rx_meta_1)); -#endif /* FTDF_PASS_ACK_FRAME */ - -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - if ((ftdf_transparent_mode_options & FTDF_TRANSPARENT_WAIT_FOR_ACK)) { - - ftdf_get_frame_header(rx_ptr, frame_header); - - if ((frame_header->frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) && - (status == FTDF_TRANSPARENT_RCV_SUCCESSFUL)) { - -#ifndef FTDF_PHY_API - while (REG_GETF(FTDF, FTDF_TX_FLAG_S_0_REG, TX_FLAG_STAT)) {} - - /* It is required to call FTDF_processTxEvent here because an RX ack - * generates two events. The RX event is raised first, then after - * an IFS the TX event is raised. However, the ftdf_process_next_request - * requires that both events have been handled. */ - ftdf_process_tx_event(); -#endif /* !FTDF_PHY_API */ - - ftdf_sn_t SN = REG_GETF(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN); - -#ifdef FTDF_PHY_API - ftdf_critical_var(); - ftdf_enter_critical(); - if (ftdf_tx_in_progress && (frame_header->sn == SN)) { - ftdf_exit_critical(); - return; - } - - ftdf_exit_critical(); -#else - if (ftdf_req_current && (frame_header->sn == SN)) { - - ftdf_transparent_request_t *transparent_request = - (ftdf_transparent_request_t*)ftdf_req_current; - - ftdf_critical_var(); - ftdf_enter_critical(); - ftdf_req_current = NULL; - ftdf_exit_critical(); - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, - FTDF_TRANSPARENT_SEND_SUCCESSFUL); - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t *)transparent_request); - - return; - } -#endif /* FTDF_PHY_API */ - } - } -#endif /* FTDF_TRANSPARENT_USE_WAIT_FOR_ACK */ -#ifndef FTDF_PASS_ACK_FRAME - FTDF_RCV_FRAME_TRANSPARENT(frameLen, rx_ptr, status, - REG_GET_FIELD(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR, rx_meta_1)); -#endif /* !FTDF_PASS_ACK_FRAME */ - - return; - } - -#ifndef FTDF_LITE - rx_ptr = ftdf_get_frame_header(rx_ptr, frame_header); - -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_MANUAL - if (frame_header->options & FTDF_OPT_ACK_REQUESTED) { - int n; - ftdf_boolean_t address_found = FTDF_FALSE; - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { - if (ftdf_tx_pending_list[n].addr_mode == frame_header->src_addr_mode && - ftdf_tx_pending_list[n].pan_id == frame_header->src_pan_id) { - if (frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) { - if (ftdf_tx_pending_list[n].addr.short_address == frame_header->src_addr.short_address) { - address_found = FTDF_TRUE; - break; - } - } else if (frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) { - if (ftdf_tx_pending_list[n].addr.ext_address == frame_header->src_addr.ext_address) { - address_found = FTDF_TRUE; - break; - } - } else { - // Invalid srcAddrMode - return; - } - } - } - if (address_found) { - ftdf_fppr_set_mode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); - } else { - ftdf_fppr_set_mode(FTDF_FALSE, FTDF_TRUE, FTDF_FALSE); - } - } -#endif - - if (frame_header->frame_version == FTDF_FRAME_VERSION_NOT_SUPPORTED) { - return; - } -#if defined(FTDF_NO_CSL) && defined(FTDF_NO_TSCH) - else if ((frame_header->frame_version == FTDF_FRAME_VERSION_E) || - (frame_header->frame_type == FTDF_MULTIPURPOSE_FRAME)) { - - return; - } -#endif /* FTDF_NO_CSL && FTDF_NO_TSCH */ - - ftdf_frame_type_t frame_type = frame_header->frame_type; - ftdf_boolean_t duplicate = FTDF_FALSE; - - if (((frame_header->options & FTDF_OPT_SEQ_NR_SUPPRESSED) == 0) && - (frame_header->src_addr_mode != FTDF_NO_ADDRESS)) { - - ftdf_time_t timestamp; - ftdf_sn_sel sn_sel = FTDF_SN_SEL_DSN; - ftdf_boolean_t drop; - - switch(read_buf) { - case 0: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); - break; - case 1: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); - break; - case 2: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); - break; - case 3: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); - break; - case 4: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); - break; - case 5: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); - break; - case 6: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); - break; - case 7: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); - break; - default: - OS_ASSERT(0); - } - - if ((ftdf_pib.tsch_enabled || (frame_header->frame_version == FTDF_FRAME_VERSION_E)) && - (frame_header->options & FTDF_OPT_ACK_REQUESTED)) { - - drop = FTDF_FALSE; - } else { - drop = FTDF_TRUE; - } - - if (frame_type == FTDF_BEACON_FRAME) { - sn_sel = (frame_header->frame_version == FTDF_FRAME_VERSION_E) ? - FTDF_SN_SEL_EBSN : FTDF_SN_SEL_BSN; - } - - uint8_t i; - - for (i = 0; i < FTDF_NR_OF_RX_ADDRS; i++) { - - /* Check if entry is empty or matches */ - if ((ftdf_rxa[i].addr_mode == FTDF_NO_ADDRESS) || - ((ftdf_rxa[i].addr_mode == frame_header->src_addr_mode) && - (((frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) && - (frame_header->src_addr.short_address == ftdf_rxa[i].addr.short_address)) || - ((frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) && - (frame_header->src_addr.ext_address == ftdf_rxa[i].addr.ext_address))))) { - - break; - } - } - - if (i < FTDF_NR_OF_RX_ADDRS) { - if (ftdf_rxa[i].addr_mode != FTDF_NO_ADDRESS) { - switch (sn_sel) { - case FTDF_SN_SEL_DSN: - - if (ftdf_rxa[i].dsn_valid == FTDF_TRUE) { - if (frame_header->sn == ftdf_rxa[i].dsn) { - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.duplicate_frame_count++; - } - - if (drop) { - return; - } - - duplicate = FTDF_TRUE; - } - } else { - ftdf_rxa[i].dsn_valid = FTDF_TRUE; - } - - ftdf_rxa[i].dsn = frame_header->sn; - break; - case FTDF_SN_SEL_BSN: - - if (ftdf_rxa[i].bsn_valid == FTDF_TRUE) { - if (frame_header->sn == ftdf_rxa[i].bsn) { - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.duplicate_frame_count++; - } - - if (drop) { - return; - } - - duplicate = FTDF_TRUE; - } - } else { - ftdf_rxa[i].bsn_valid = FTDF_TRUE; - } - - ftdf_rxa[i].bsn = frame_header->sn; - break; - case FTDF_SN_SEL_EBSN: - - if (ftdf_rxa[i].ebsn_valid == FTDF_TRUE) { - if (frame_header->sn == ftdf_rxa[i].eb_sn) { - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.duplicate_frame_count++; - } - - if (drop) { - return; - } - - duplicate = FTDF_TRUE; - } - } else { - ftdf_rxa[i].ebsn_valid = FTDF_TRUE; - } - - ftdf_rxa[i].eb_sn = frame_header->sn; - break; - } - } else { - ftdf_rxa[i].addr_mode = frame_header->src_addr_mode; - ftdf_rxa[i].addr = frame_header->src_addr; - - switch (sn_sel) { - case FTDF_SN_SEL_DSN: - ftdf_rxa[i].dsn_valid = FTDF_TRUE; - ftdf_rxa[i].dsn = frame_header->sn; - break; - case FTDF_SN_SEL_BSN: - ftdf_rxa[i].bsn_valid = FTDF_TRUE; - ftdf_rxa[i].bsn = frame_header->sn; - break; - case FTDF_SN_SEL_EBSN: - ftdf_rxa[i].ebsn_valid = FTDF_TRUE; - ftdf_rxa[i].eb_sn = frame_header->sn; - break; - } - } - - ftdf_rxa[i].timestamp = timestamp; - } else { - /* find oldest entry and overwrite it */ - ftdf_time_t cur_time = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - ftdf_time_t delta, greatest_delta = 0; - uint8_t entry = 0; - - for (i = 0; i < FTDF_NR_OF_RX_ADDRS; i++) { - delta = cur_time - ftdf_rxa[i].timestamp; - - if (delta > greatest_delta) { - greatest_delta = delta; - entry = i; - } - } - - ftdf_rxa[entry].addr_mode = frame_header->src_addr_mode; - ftdf_rxa[entry].addr = frame_header->src_addr; - - switch (sn_sel) { - case FTDF_SN_SEL_DSN: - ftdf_rxa[entry].bsn_valid = FTDF_FALSE; - ftdf_rxa[entry].ebsn_valid = FTDF_FALSE; - ftdf_rxa[entry].dsn_valid = FTDF_TRUE; - ftdf_rxa[entry].dsn = frame_header->sn; - break; - case FTDF_SN_SEL_BSN: - ftdf_rxa[entry].dsn_valid = FTDF_FALSE; - ftdf_rxa[entry].ebsn_valid = FTDF_FALSE; - ftdf_rxa[entry].bsn_valid = FTDF_TRUE; - ftdf_rxa[entry].bsn = frame_header->sn; - break; - case FTDF_SN_SEL_EBSN: - ftdf_rxa[entry].dsn_valid = FTDF_FALSE; - ftdf_rxa[entry].bsn_valid = FTDF_FALSE; - ftdf_rxa[entry].ebsn_valid = FTDF_TRUE; - ftdf_rxa[entry].eb_sn = frame_header->sn; - break; - } - } - } - - if (frame_header->options & FTDF_OPT_SECURITY_ENABLED) { - rx_ptr = ftdf_get_security_header(rx_ptr, frame_header->frame_version, security_header); - } else { - security_header->security_level = 0; - security_header->key_id_mode = 0; - } - - ftdf_ie_list_t* header_ie_list = NULL; - ftdf_ie_list_t* payload_ie_list = NULL; - int mic_length = ftdf_get_mic_length(security_header->security_level); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (frame_header->options & FTDF_OPT_IES_PRESENT) { - rx_ptr = ftdf_get_ies(rx_ptr, rx_buffer + (frameLen - mic_length - FTDF_FCS_LENGTH), - &header_ie_list, &payload_ie_list); - } -#endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - - /* Get start of private data (needed to unsecure a frame) */ - if (frame_type == FTDF_MAC_COMMAND_FRAME) { - - frame_header->command_frame_id = *rx_ptr++; - - } else if (frame_type == FTDF_BEACON_FRAME) { - - pan_descriptor.coord_addr_mode = frame_header->src_addr_mode; - pan_descriptor.coord_pan_id = frame_header->src_pan_id; - pan_descriptor.coord_addr = frame_header->src_addr; - pan_descriptor.channel_number = REG_GETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN) + 11; - pan_descriptor.channel_page = 0; - - switch (read_buf) { - case 0: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR); - break; - case 1: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_1_REG, QUALITY_INDICATOR); - break; - case 2: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_2_REG, QUALITY_INDICATOR); - break; - case 3: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_3_REG, QUALITY_INDICATOR); - break; - case 4: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_4_REG, QUALITY_INDICATOR); - break; - case 5: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_5_REG, QUALITY_INDICATOR); - break; - case 6: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_6_REG, QUALITY_INDICATOR); - break; - case 7: - pan_descriptor.timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); - pan_descriptor.link_quality = REG_GETF(FTDF, FTDF_RX_META_1_7_REG, QUALITY_INDICATOR); - break; - default: - /* Unsupported register index occurred */ - OS_ASSERT(0); - } - - ftdf_octet_t* superframe_spec_ptr = (ftdf_octet_t*)&pan_descriptor.superframe_spec; - *superframe_spec_ptr++ = *rx_ptr++; - *superframe_spec_ptr = *rx_ptr++; - - uint8_t gts_spec = *rx_ptr++; - - pan_descriptor.gts_permit = (gts_spec & 0x08) ? FTDF_TRUE : FTDF_FALSE; - uint8_t gts_descr_count = gts_spec & 0x7; - - if (gts_descr_count != 0) { - /* GTS is not supported, so just skip the GTS direction and GTS list - * fields if present */ - rx_ptr += (1 + (3 * gts_descr_count)); - } - - pend_addr_spec = *rx_ptr++; - uint8_t nr_of_short_addrs = pend_addr_spec & 0x07; - uint8_t nr_of_ext_addrs = (pend_addr_spec & 0x70) >> 4; - - int n; - - for (n = 0; n < (nr_of_short_addrs + nr_of_ext_addrs); n++) { - if (n < nr_of_short_addrs) { - - ftdf_octet_t* short_address_ptr = - (ftdf_octet_t*)&pend_addr_list[n].short_address; - *short_address_ptr++ = *rx_buffer++; - *short_address_ptr = *rx_buffer++; - - } else { - - ftdf_octet_t* ext_address_ptr = - (ftdf_octet_t*)&pend_addr_list[n].ext_address; - int m; - - for (m = 0; m < 8; m++) { - *ext_address_ptr++ = *rx_buffer++; - } - } - } - } else if ((frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) && - (security_header->security_level != 0)) { - - if (ftdf_req_current) { - switch (ftdf_req_current->msg_id) { - case FTDF_DATA_REQUEST: - { - ftdf_data_request_t *data_request = - (ftdf_data_request_t*)ftdf_req_current; - - frame_header->src_pan_id = data_request->dst_pan_id; - frame_header->src_addr_mode = data_request->dst_addr_mode; - frame_header->src_addr = data_request->dst_addr; - break; - } - case FTDF_POLL_REQUEST: - { - ftdf_poll_request_t *poll_request = - (ftdf_poll_request_t*)ftdf_req_current; - - frame_header->src_pan_id = poll_request->coord_pan_id; - frame_header->src_addr_mode = poll_request->coord_addr_mode; - frame_header->src_addr = poll_request->coord_addr; - break; - } - case FTDF_ASSOCIATE_REQUEST: - { - ftdf_associate_request_t *associate_request = - (ftdf_associate_request_t*)ftdf_req_current; - - frame_header->src_pan_id = associate_request->coord_pan_id; - frame_header->src_addr_mode = associate_request->coord_addr_mode; - frame_header->src_addr = associate_request->coord_addr; - break; - } - case FTDF_DISASSOCIATE_REQUEST: - { - ftdf_disassociate_request_t *disassociate_request = - (ftdf_disassociate_request_t*)ftdf_req_current; - - frame_header->src_pan_id = disassociate_request->device_pan_id; - frame_header->src_addr_mode = - disassociate_request->device_addr_mode; - frame_header->src_addr = disassociate_request->device_address; - break; - } - case FTDF_ASSOCIATE_RESPONSE: - { - ftdf_associate_response_t *associate_response = - (ftdf_associate_response_t*)ftdf_req_current; - - frame_header->src_addr_mode = FTDF_EXTENDED_ADDRESS; - frame_header->src_addr.ext_address = - associate_response->device_address; - break; - } - } - } - } - - ftdf_status_t status = ftdf_unsecure_frame(rx_buffer, rx_ptr, frame_header, security_header); - - if (status != FTDF_SUCCESS) { - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.security_failure_count++; - } - - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - - /* Since unsecure of acknowledgement frame is always successful, - * nothing special has to be done to get the address information correct. */ - ftdf_send_comm_status_indication(ftdf_req_current, status, - ftdf_pib.pan_id, - frame_header->src_addr_mode, - frame_header->src_addr, - frame_header->dst_addr_mode, - frame_header->dst_addr, - security_header->security_level, - security_header->key_id_mode, - security_header->key_source, - security_header->key_index); - - if ((frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) && ftdf_req_current) { - - send_confirm(FTDF_NO_ACK, ftdf_req_current->msg_id); - - ftdf_process_next_request(); - } - - return; - } - - if (ftdf_pib.metrics_enabled && frame_type != FTDF_ACKNOWLEDGEMENT_FRAME) { - ftdf_pib.performance_metrics.rx_success_count++; - } - -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled && frame_type != FTDF_ACKNOWLEDGEMENT_FRAME) { - ftdf_time_t timestamp; - - switch (read_buf) { - case 0: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); - break; - case 1: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); - break; - case 2: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); - break; - case 3: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); - break; - case 4: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); - break; - case 5: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); - break; - case 6: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); - break; - case 7: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); - break; - default: - /* Unsupported register index occurred */ - OS_ASSERT(0); - } - - ftdf_correct_slot_time(timestamp); - } -#endif /* FTDF_NO_TSCH */ - - switch (frame_type) { - case FTDF_ACKNOWLEDGEMENT_FRAME: - if (ftdf_pib.metrics_enabled) { - if (ftdf_nr_of_retries == 0) { - ftdf_pib.performance_metrics.tx_success_count++; - } else if (ftdf_nr_of_retries == 1) { - ftdf_pib.performance_metrics.retry_count++; - } else { - ftdf_pib.performance_metrics.multiple_retry_count++; - } - } - - if (frame_header->frame_version == FTDF_FRAME_VERSION_E) { - ftdf_pib.traffic_counters.rx_enh_ack_frm_ok_cnt++; - } - break; - case FTDF_BEACON_FRAME: - ftdf_pib.traffic_counters.rx_beacon_frm_ok_cnt++; - break; - case FTDF_DATA_FRAME: - ftdf_pib.traffic_counters.rx_data_frm_ok_cnt++; - break; - case FTDF_MAC_COMMAND_FRAME: - ftdf_pib.traffic_counters.rx_cmd_frm_ok_cnt++; - break; - case FTDF_MULTIPURPOSE_FRAME: - ftdf_pib.traffic_counters.rx_multi_purp_frm_ok_cnt++; - break; - } - - if (frame_type == FTDF_ACKNOWLEDGEMENT_FRAME) { - - while (REG_GETF(FTDF, FTDF_TX_FLAG_S_0_REG, TX_FLAG_STAT)) {} - - /* It is required to call ftdf_process_tx_event here because an RX ack generates two events - * The RX event is raised first, then after an IFS the TX event is raised. However, - * the ftdf_process_next_request requires that both events have been handled. */ - ftdf_process_tx_event(); - - ftdf_sn_t SN = REG_GETF(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN); - - if (ftdf_req_current && frame_header->sn == SN) { -#ifndef FTDF_NO_CSL - if (ftdf_pib.le_enabled == FTDF_TRUE) { - ftdf_time_t timestamp; - - switch (read_buf) { - case 0: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); - break; - case 1: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); - break; - case 2: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); - break; - case 3: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); - break; - case 4: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); - break; - case 5: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); - break; - case 6: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); - break; - case 7: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); - break; - default: - /* Unsupported register index occurred */ - OS_ASSERT(0); - } - - ftdf_set_peer_csl_timing(header_ie_list, timestamp); - } -#endif /* FTDF_NO_CSL */ - -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled == FTDF_TRUE) { - ftdf_correct_slot_time_from_ack(header_ie_list); - - ftdf_tsch_retry_t* tsch_retry = - ftdf_get_tsch_retry(ftdf_get_request_address(ftdf_req_current)); - - tsch_retry->nr_of_retries = 0; - ftdf_tsch_slot_link->request = NULL; - } -#endif /* FTDF_NO_TSCH */ - - switch (ftdf_req_current->msg_id) { - case FTDF_DATA_REQUEST: - { - ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_0_0_REG, TXTIMESTAMP); - ftdf_num_of_backoffs_t num_of_backoffs = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, CSMACANRRETRIES); - - ftdf_send_data_confirm((ftdf_data_request_t*)ftdf_req_current, - FTDF_SUCCESS, - timestamp, - SN, - num_of_backoffs, - payload_ie_list); - break; - } - case FTDF_POLL_REQUEST: - { - if (!(frame_header->options & FTDF_OPT_FRAME_PENDING)) { - ftdf_send_poll_confirm((ftdf_poll_request_t*)ftdf_req_current, - FTDF_NO_DATA); - } - break; - } - case FTDF_ASSOCIATE_REQUEST: - { - ftdf_assoc_admin_t* assoc_admin = &ftdf_aa; - - if ((assoc_admin->fast_a == FTDF_TRUE) || (assoc_admin->data_r == FTDF_FALSE)) { - uint32_t timestamp = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - - REG_SETF(FTDF, FTDF_SYMBOLTIME2THR_REG, SYMBOLTIME2THR, - (timestamp + ftdf_pib.response_wait_time * FTDF_BASE_SUPERFRAME_DURATION)); - - } else if (!(frame_header->options & FTDF_OPT_FRAME_PENDING)) { - - ftdf_send_associate_confirm((ftdf_associate_request_t*)ftdf_req_current, - FTDF_NO_DATA, - 0xffff); - } - break; - } - case FTDF_ASSOCIATE_RESPONSE: - { - ftdf_associate_response_t* assoc_resp = - (ftdf_associate_response_t*)ftdf_req_current; - - ftdf_address_t src_addr, dst_addr; - src_addr.ext_address = ftdf_pib.ext_address; - dst_addr.ext_address = assoc_resp->device_address; - - ftdf_send_comm_status_indication(ftdf_req_current, FTDF_SUCCESS, - ftdf_pib.pan_id, - FTDF_EXTENDED_ADDRESS, - src_addr, - FTDF_EXTENDED_ADDRESS, - dst_addr, - assoc_resp->security_level, - assoc_resp->key_id_mode, - assoc_resp->key_source, - assoc_resp->key_index); - break; - } - case FTDF_ORPHAN_RESPONSE: - { - ftdf_orphan_response_t* orphan_resp = - (ftdf_orphan_response_t*)ftdf_req_current; - - ftdf_address_t src_addr, dst_addr; - src_addr.ext_address = ftdf_pib.ext_address; - dst_addr.ext_address = orphan_resp->orphan_address; - - ftdf_send_comm_status_indication(ftdf_req_current, FTDF_SUCCESS, - ftdf_pib.pan_id, - FTDF_EXTENDED_ADDRESS, - src_addr, - FTDF_EXTENDED_ADDRESS, - dst_addr, - orphan_resp->security_level, - orphan_resp->key_id_mode, - orphan_resp->key_source, - orphan_resp->key_index); - break; - } - case FTDF_DISASSOCIATE_REQUEST: - { - ftdf_send_disassociate_confirm((ftdf_disassociate_request_t*)ftdf_req_current, - FTDF_SUCCESS); - break; - } - case FTDF_REMOTE_REQUEST: - { - ftdf_remote_request_t* remote_request = - (ftdf_remote_request_t*)ftdf_req_current; - - if (remote_request->remote_id == - FTDF_REMOTE_PAN_ID_CONFLICT_NOTIFICATION) { - - ftdf_send_sync_loss_indication(FTDF_PAN_ID_CONFLICT, - security_header); - } - - ftdf_req_current = NULL; - break; - } - } - - if (ftdf_req_current->msg_id != FTDF_DATA_REQUEST) { - /* for data request the application owns the memory */ - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - } - - ftdf_process_next_request(); - } else { - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - } - } else if (((frame_header->frame_version == FTDF_FRAME_VERSION_E) || ftdf_pib.tsch_enabled) && - (frame_header->options & FTDF_OPT_ACK_REQUESTED)) { - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - static ftdf_frame_header_t afh; - ftdf_frame_header_t *ack_frame_header = &afh; - - ack_frame_header->frame_type = FTDF_ACKNOWLEDGEMENT_FRAME; - ack_frame_header->options = - (frame_header->options & (FTDF_OPT_SECURITY_ENABLED | FTDF_OPT_SEQ_NR_SUPPRESSED)) | - FTDF_OPT_ENHANCED; - - if ((ftdf_pib.le_enabled == FTDF_TRUE) || (ftdf_pib.tsch_enabled == FTDF_TRUE) || - (ftdf_pib.e_ack_ie_list.nr_of_ie != 0)) { - - ack_frame_header->options |= FTDF_OPT_IES_PRESENT; - } - - ack_frame_header->dst_addr_mode = FTDF_NO_ADDRESS; - ack_frame_header->src_addr_mode = FTDF_NO_ADDRESS; - ack_frame_header->sn = frame_header->sn; - - ftdf_octet_t *tx_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_2_0_REG; - - /* Skip PHY header (= MAC length) */ - tx_ptr++; - - tx_ptr = ftdf_add_frame_header(tx_ptr, ack_frame_header, 0); - - if (frame_header->options & FTDF_OPT_SECURITY_ENABLED) { - security_header->frame_counter = ftdf_pib.frame_counter; - security_header->frame_counter_mode = ftdf_pib.frame_counter_mode; - - tx_ptr = ftdf_add_security_header(tx_ptr, security_header); - } - -#ifndef FTDF_NO_CSL - if (ftdf_pib.le_enabled == FTDF_TRUE) { - static ftdf_octet_t phase_and_period[4]; - static ftdf_ie_descriptor_t cslIE = { 0x1a, 4, { phase_and_period } }; - static ftdf_ie_list_t cslIEList = { 1, &cslIE }; - ftdf_time_t curTime = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - - ftdf_time_t delta = - curTime - (ftdf_start_csl_sample_time - ftdf_pib.csl_period * 10); - - *(ftdf_period_t*)(phase_and_period + 0) = (ftdf_period_t)(delta / 10); - *(ftdf_period_t*)(phase_and_period + 2) = ftdf_pib.csl_period; - - tx_ptr = ftdf_add_ies(tx_ptr, &cslIEList, &ftdf_pib.e_ack_ie_list, FTDF_FALSE); - } -#endif /* FTDF_NO_CSL */ - -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled == FTDF_TRUE) { - ftdf_time_t rx_timestamp; - - switch (read_buf) { - case 0: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); - break; - case 1: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); - break; - case 2: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); - break; - case 3: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); - break; - case 4: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); - break; - case 5: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); - break; - case 6: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); - break; - case 7: - rx_timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); - break; - default: - /* Unsupported register index occurred */ - OS_ASSERT(0); - } - - tx_ptr = ftdf_add_corr_time_ie(tx_ptr, rx_timestamp); - } -#endif /* FTDF_NO_TSCH */ - - if (!ftdf_pib.le_enabled && !ftdf_pib.tsch_enabled) { - tx_ptr = ftdf_add_ies(tx_ptr, NULL, &ftdf_pib.e_ack_ie_list, FTDF_FALSE); - } - - ftdf_send_ack_frame(frame_header, security_header, tx_ptr); -#endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - - if (duplicate) { - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - return; - } - } - - if ((frame_type == FTDF_DATA_FRAME) || (frame_type == FTDF_MULTIPURPOSE_FRAME)) { - ftdf_data_length_t payload_length = - frameLen - (rx_ptr - rx_buffer) + 1 - mic_length - FTDF_FCS_LENGTH; - - if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_POLL_REQUEST)) { - ftdf_poll_request_t *poll_request = (ftdf_poll_request_t*)ftdf_req_current; - - if ((frame_header->src_addr_mode == poll_request->coord_addr_mode) && - (frame_header->src_pan_id == poll_request->coord_pan_id) && - (((frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) && - (frame_header->src_addr.short_address == poll_request->coord_addr.short_address)) || - ((frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) && - (frame_header->src_addr.ext_address = poll_request->coord_addr.ext_address)))) { - - if (payload_length == 0) { - ftdf_send_poll_confirm(poll_request, FTDF_NO_DATA); - } else { - ftdf_send_poll_confirm(poll_request, FTDF_SUCCESS); - } - } - } else if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_ASSOCIATE_REQUEST) && - (payload_length == 0)) { - - send_confirm(FTDF_NO_DATA, FTDF_ASSOCIATE_REQUEST); - } - - if (payload_length != 0) { - ftdf_link_quality_t mpdu_link_quality; - ftdf_time_t timestamp; - - switch (read_buf) { - case 0: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_0_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); - break; - case 1: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_1_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); - break; - case 2: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_2_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); - break; - case 3: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_3_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); - break; - case 4: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_4_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); - break; - case 5: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_5_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); - break; - case 6: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_6_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); - break; - case 7: - mpdu_link_quality = REG_GETF(FTDF, FTDF_RX_META_1_7_REG, QUALITY_INDICATOR); - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); - break; - default: - OS_ASSERT(0); - } - - ftdf_send_data_indication(frame_header, - security_header, - payload_ie_list, - payload_length, - rx_ptr, - mpdu_link_quality, - timestamp); - } -#ifndef FTDF_NO_CSL - else if ((header_ie_list->nr_of_ie == 1) && (header_ie_list->ie[0].id == 0x1d)) { - ftdf_period_t rz_time = *(uint16_t*)header_ie_list->ie[0].content.raw; - - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_time_t cur_time = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - - ftdf_rz_time = cur_time + (ftdf_time_t)rz_time * 10 + 260; /* 260 length of max frame in symbols */ - - ftdf_time_t csl_period = ftdf_pib.csl_period * 10; - ftdf_time_t delta = ftdf_rz_time - ftdf_start_csl_sample_time; - - /* A delta larger than 0x80000000 is assumed a negative delta */ - while (delta < 0x80000000) { - ftdf_start_csl_sample_time += csl_period; - delta = ftdf_rz_time - ftdf_start_csl_sample_time; - } - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, - ftdf_start_csl_sample_time); - - ftdf_exit_critical(); - - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - } -#endif /* FTDF_NO_CSL */ - else { - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - } - } else if (frame_type == FTDF_MAC_COMMAND_FRAME) { - ftdf_process_command_frame(rx_ptr, frame_header, security_header, payload_ie_list); - } else if (frame_type == FTDF_BEACON_FRAME) { - ftdf_octet_t* superframe_spec_ptr = (ftdf_octet_t*)&pan_descriptor.superframe_spec; - superframe_spec_ptr++; - - if (ftdf_is_pan_coordinator) { - if ((frame_header->src_pan_id == ftdf_pib.pan_id) && (*superframe_spec_ptr & 0x40)) { - - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - ftdf_send_sync_loss_indication(FTDF_PAN_ID_CONFLICT, - security_header); - - return; - } - } else if (ftdf_pib.associated_pan_coord) { - if ((frame_header->src_pan_id == ftdf_pib.pan_id) && (*superframe_spec_ptr & 0x40) && - (((frame_header->src_addr_mode == FTDF_SHORT_ADDRESS) && - (frame_header->src_addr.short_address != ftdf_pib.coord_short_address)) || - ((frame_header->src_addr_mode == FTDF_EXTENDED_ADDRESS) && - (frame_header->src_addr.ext_address != ftdf_pib.coord_ext_address)))) { - - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - ftdf_sendpan_id_conflict_notification(frame_header, security_header); - return; - } - } - - ftdf_data_length_t beacon_payload_length = - frameLen - (rx_ptr - rx_buffer) + 1- mic_length - FTDF_FCS_LENGTH; - - if ((ftdf_pib.auto_request == FTDF_FALSE) || (beacon_payload_length != 0)) { - ftdf_time_t timestamp; - - switch (read_buf) { - case 0: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_0_REG, RX_TIMESTAMP); - break; - case 1: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_1_REG, RX_TIMESTAMP); - break; - case 2: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_2_REG, RX_TIMESTAMP); - break; - case 3: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_3_REG, RX_TIMESTAMP); - break; - case 4: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_4_REG, RX_TIMESTAMP); - break; - case 5: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_5_REG, RX_TIMESTAMP); - break; - case 6: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_6_REG, RX_TIMESTAMP); - break; - case 7: - timestamp = REG_GETF(FTDF, FTDF_RX_META_0_7_REG, RX_TIMESTAMP); - break; - default: - /* Unsupported register index occurred */ - OS_ASSERT(0); - } - - ftdf_beacon_notify_indication_t* beacon_notify_indication = - (ftdf_beacon_notify_indication_t*) FTDF_GET_MSG_BUFFER( - sizeof(ftdf_beacon_notify_indication_t)); - - beacon_notify_indication->msg_id = FTDF_BEACON_NOTIFY_INDICATION; - beacon_notify_indication->bsn = frame_header->sn; - beacon_notify_indication->pan_descriptor = &pan_descriptor; - beacon_notify_indication->pend_addr_spec = pend_addr_spec; - beacon_notify_indication->addr_list = pend_addr_list; - beacon_notify_indication->sdu_length = beacon_payload_length; - beacon_notify_indication->sdu = FTDF_GET_DATA_BUFFER(beacon_payload_length); - beacon_notify_indication->eb_sn = frame_header->sn; - beacon_notify_indication->beacon_type = - frame_header->frame_version == FTDF_FRAME_VERSION_E ? - FTDF_ENHANCED_BEACON : FTDF_NORMAL_BEACON; - beacon_notify_indication->ie_list = payload_ie_list; - beacon_notify_indication->timestamp = timestamp; - - memcpy(beacon_notify_indication->sdu, rx_ptr, beacon_payload_length); - - FTDF_RCV_MSG((ftdf_msg_buffer_t*)beacon_notify_indication); - - } else if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_SCAN_REQUEST)) { - - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - ftdf_add_pan_descriptor(&pan_descriptor); - - } else { - FTDF_REL_DATA_BUFFER((ftdf_octet_t*)payload_ie_list); - } - } -#if FTDF_USE_LPDP -#if FTDF_FP_BIT_TEST_MODE - if (ftdf_lpdp_is_enabled() && !ftdf_req_current && (frame_type == FTDF_DATA_FRAME)) { - ftdf_process_tx_pending(frame_header, security_header); - } -#else /* FTDF_FP_BIT_TEST_MODE */ - if (!ftdf_req_current && frame_type == FTDF_DATA_FRAME) { - ftdf_process_tx_pending(frame_header, security_header); - } -#endif /* FTDF_FP_BIT_TEST_MODE */ -#endif /* FTDF_USE_LPDP */ -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled == FTDF_TRUE) { - ftdf_schedule_tsch(NULL); - } -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ -} - -void ftdf_process_rx_event(void) -{ - if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RXSOF_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RXSOF_E); -#else - FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RXSOF_E); -#endif - } - - if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RXBYTE_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RXBYTE_E); -#else - FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RXBYTE_E); -#endif - } - - if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RX_OVERFLOW_E)) { - // No API defined to report this error to the higher layer, so just clear it. -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RX_OVERFLOW_E); -#else - FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RX_OVERFLOW_E); -#endif - } - - if (REG_GETF(FTDF, FTDF_RX_EVENT_REG, RX_BUF_AVAIL_E)) { - int read_buf = REG_GETF(FTDF, FTDF_RX_CONTROL_0_REG, RX_READ_BUF_PTR); - int write_buf = REG_GETF(FTDF, FTDF_RX_STATUS_REG, RX_WRITE_BUF_PTR); - - while (read_buf != write_buf) { - process_rx_frame(read_buf % 8); - read_buf = (read_buf + 1) % 16; - } - - REG_SETF(FTDF, FTDF_RX_CONTROL_0_REG, RX_READ_BUF_PTR, read_buf); - -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_RX_EVENT_REG, RX_BUF_AVAIL_E); -#else - FTDF->FTDF_RX_EVENT_REG = REG_MSK(FTDF, FTDF_RX_EVENT_REG, RX_BUF_AVAIL_E); -#endif - } - - if (REG_GETF(FTDF, FTDF_LMAC_EVENT_REG, EDSCANREADY_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_LMAC_EVENT_REG, EDSCANREADY_E); -#else - FTDF->FTDF_LMAC_EVENT_REG = REG_MSK(FTDF, FTDF_LMAC_EVENT_REG, EDSCANREADY_E); -#endif - -#ifndef FTDF_LITE - ftdf_msg_buffer_t *request = ftdf_req_current; - - if (request->msg_id == FTDF_SCAN_REQUEST) { - ftdf_scan_ready((ftdf_scan_request_t*)request); - } -#endif /* !FTDF_LITE */ - } - - if (REG_GETF(FTDF, FTDF_LMAC_EVENT_REG, RXTIMEREXPIRED_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_LMAC_EVENT_REG, RXTIMEREXPIRED_E); -#else - FTDF->FTDF_LMAC_EVENT_REG = REG_MSK(FTDF, FTDF_LMAC_EVENT_REG, RXTIMEREXPIRED_E); -#endif - - if ( ftdf_pib.metrics_enabled ) { - ftdf_pib.performance_metrics.rx_expired_count++; - } -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - ftdf_schedule_tsch(NULL); - } else -#endif /* FTDF_NO_TSCH */ - if (ftdf_req_current) { - ftdf_msg_id_t msg_id = ftdf_req_current->msg_id; - - if (msg_id == FTDF_POLL_REQUEST) { - ftdf_send_poll_confirm((ftdf_poll_request_t*)ftdf_req_current, - FTDF_NO_DATA); - } else if (msg_id == FTDF_SCAN_REQUEST) { - ftdf_scan_ready((ftdf_scan_request_t*)ftdf_req_current); - } else if (msg_id == FTDF_ASSOCIATE_REQUEST) { - ftdf_send_associate_confirm((ftdf_associate_request_t*)ftdf_req_current, - FTDF_NO_DATA, - 0xffff); - } - } -#endif /* !FTDF_LITE */ - } - - if (REG_GETF(FTDF, FTDF_LMAC_EVENT_REG, CSMA_CA_BO_THR_E)) { -#ifdef SIMULATOR - REG_CLEAR_BIT(FTDF, FTDF_LMAC_EVENT_REG, CSMA_CA_BO_THR_E); -#else - FTDF->FTDF_LMAC_EVENT_REG = REG_MSK(FTDF, FTDF_LMAC_EVENT_REG, CSMA_CA_BO_THR_E); - -#if FTDF_USE_SLEEP_DURING_BACKOFF - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.bo_irq_count++; - } - ftdf_sdb_fsm_backoff_irq(); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - } -#endif -} - -static void send_confirm(ftdf_status_t status, ftdf_msg_id_t msg_id) -{ - - switch (msg_id) { -#ifndef FTDF_LITE - case FTDF_DATA_REQUEST: - { - ftdf_data_request_t* data_request = (ftdf_data_request_t*)ftdf_req_current; - - ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_0_0_REG, TXTIMESTAMP); - ftdf_sn_t sn = REG_GETF(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN); - ftdf_num_of_backoffs_t num_of_backoffs = REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, CSMACANRRETRIES); - - ftdf_send_data_confirm(data_request, status, timestamp, sn, num_of_backoffs, NULL); - - break; - } - - case FTDF_POLL_REQUEST: - if (status != FTDF_SUCCESS) { - ftdf_send_poll_confirm((ftdf_poll_request_t*)ftdf_req_current, status); - } - - break; - case FTDF_ASSOCIATE_REQUEST: - if (status != FTDF_SUCCESS) { - ftdf_send_associate_confirm((ftdf_associate_request_t*)ftdf_req_current, - status, - 0xffff); - } - - break; - case FTDF_ASSOCIATE_RESPONSE: - if (status != FTDF_SUCCESS) { - ftdf_associate_response_t *assoc_resp = - (ftdf_associate_response_t*)ftdf_req_current; - - ftdf_address_t src_addr, dst_addr; - src_addr.ext_address = ftdf_pib.ext_address; - dst_addr.ext_address = assoc_resp->device_address; - - ftdf_send_comm_status_indication(ftdf_req_current, status, - ftdf_pib.pan_id, - FTDF_EXTENDED_ADDRESS, - src_addr, - FTDF_EXTENDED_ADDRESS, - dst_addr, - assoc_resp->security_level, - assoc_resp->key_id_mode, - assoc_resp->key_source, - assoc_resp->key_index); - } - - break; - case FTDF_ORPHAN_RESPONSE: - if (status != FTDF_SUCCESS) { - ftdf_orphan_response_t *orphan_resp = - (ftdf_orphan_response_t*)ftdf_req_current; - - ftdf_address_t src_addr, dst_addr; - src_addr.ext_address = ftdf_pib.ext_address; - dst_addr.ext_address = orphan_resp->orphan_address; - - ftdf_send_comm_status_indication(ftdf_req_current, status, - ftdf_pib.pan_id, - FTDF_EXTENDED_ADDRESS, - src_addr, - FTDF_EXTENDED_ADDRESS, - dst_addr, - orphan_resp->security_level, - orphan_resp->key_id_mode, - orphan_resp->key_source, - orphan_resp->key_index); - } - - break; - case FTDF_DISASSOCIATE_REQUEST: - if (status != FTDF_SUCCESS) { - ftdf_send_disassociate_confirm( - (ftdf_disassociate_request_t*)ftdf_req_current, status); - } - - break; - case FTDF_SCAN_REQUEST: - if (status != FTDF_SUCCESS) { - ftdf_send_scan_confirm((ftdf_scan_request_t*)ftdf_req_current, status); - } - - break; - case FTDF_BEACON_REQUEST: - ftdf_send_beacon_confirm((ftdf_beacon_request_t*)ftdf_req_current, status); - break; - case FTDF_REMOTE_REQUEST: - ftdf_req_current = NULL; - break; -#endif /* !FTDF_LITE */ - case FTDF_TRANSPARENT_REQUEST: - { -#ifndef FTDF_PHY_API - ftdf_transparent_request_t *transparent_request = - (ftdf_transparent_request_t*)ftdf_req_current; -#endif - ftdf_bitmap32_t transparent_status = 0; - - switch (status) { - case FTDF_SUCCESS: - transparent_status = FTDF_TRANSPARENT_SEND_SUCCESSFUL; - break; - case FTDF_CHANNEL_ACCESS_FAILURE: - transparent_status = FTDF_TRANSPARENT_CSMACA_FAILURE; - break; -#if FTDF_TRANSPARENT_WAIT_FOR_ACK - case FTDF_NO_ACK: - transparent_status = FTDF_TRANSPARENT_NO_ACK; - break; -#endif - } - - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.tx_success_count++; - } -#ifdef FTDF_PHY_API - ftdf_critical_var(); - ftdf_enter_critical(); - ftdf_tx_in_progress = FTDF_FALSE; - ftdf_exit_critical(); - - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(NULL, transparent_status); -#else - - ftdf_req_current = NULL; - - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, transparent_status); - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*)transparent_request); -#ifndef FTDF_LITE - ftdf_process_next_request(); -#endif /* !FTDF_LITE */ - -#endif /* FTDF_PHY_API */ - break; - } - } -} - -void ftdf_process_tx_event(void) -{ - volatile uint32_t *tx_flag_state; - ftdf_status_t status = FTDF_SUCCESS; - -#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI - /* Restore Rx PTI in case the Tx transaction that just ended interrupted an Rx-always-on - * transaction. */ - hw_coex_pti_t tx_pti; - hw_coex_update_ftdf_pti(ftdf_get_rx_pti(), &tx_pti, true); -#endif - - if (REG_GETF(FTDF, FTDF_TX_FLAG_CLEAR_E_1_REG, TX_FLAG_CLEAR_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_TX_FLAG_CLEAR_E_1_REG, TX_FLAG_CLEAR_E); -#else - FTDF->FTDF_TX_FLAG_CLEAR_E_1_REG = REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_E_1_REG, TX_FLAG_CLEAR_E); -#endif - - if (REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_1_REG, CSMACAFAIL)) { - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.tx_fail_count++; - } - - status = FTDF_CHANNEL_ACCESS_FAILURE; - } - } - - if (REG_GETF(FTDF, FTDF_TX_FLAG_CLEAR_E_0_REG, TX_FLAG_CLEAR_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_TX_FLAG_CLEAR_E_0_REG, TX_FLAG_CLEAR_E); -#else - FTDF->FTDF_TX_FLAG_CLEAR_E_0_REG = REG_MSK(FTDF, FTDF_TX_FLAG_CLEAR_E_0_REG, TX_FLAG_CLEAR_E); -#endif - } else { - return; - } - -#ifndef FTDF_PHY_API - ftdf_tx_in_progress = FTDF_FALSE; - - if (ftdf_req_current == NULL) { - return; - } -#else - ftdf_critical_var(); - ftdf_enter_critical(); - - if (ftdf_tx_in_progress == FTDF_FALSE) { - ftdf_exit_critical(); - - return; - } - - ftdf_exit_critical(); -#endif -#if FTDF_USE_SLEEP_DURING_BACKOFF - ftdf_sdb_fsm_tx_irq(); -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - ftdf_boolean_t ack_tx = REG_GETF(FTDF, FTDF_TX_META_DATA_0_0_REG, ACKREQUEST); - - if (status == FTDF_SUCCESS) { - ftdf_frame_type_t frame_type = REG_GETF(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAMETYPE); - - switch (frame_type) { - case FTDF_BEACON_FRAME: - ftdf_pib.traffic_counters.tx_ceacon_frm_cnt++; - break; - case FTDF_DATA_FRAME: - ftdf_pib.traffic_counters.tx_data_frm_cnt++; - break; - case FTDF_MAC_COMMAND_FRAME: - ftdf_pib.traffic_counters.tx_cmd_frm_cnt++; - break; - case FTDF_MULTIPURPOSE_FRAME: - ftdf_pib.traffic_counters.tx_multi_purp_frm_cnt++; - break; - } - -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - ftdf_tsch_retry_t *tsch_retry = NULL; - - if (ftdf_pib.tsch_enabled) { - tsch_retry = ftdf_get_tsch_retry(ftdf_get_request_address(ftdf_req_current)); - } -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - if (REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, ACKFAIL)) { -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - tsch_retry->nr_of_retries++; - ftdf_tsch_slot_link->request = NULL; - status = ftdf_schedule_tsch(ftdf_req_current); - - if (status == FTDF_SUCCESS) { - /* If ftdf_req_current is not equal to NULL the retried - * request will be queued rather then send again */ - ftdf_req_current = NULL; - } - - } else -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - - if (ftdf_nr_of_retries < ftdf_pib.max_frame_retries) { - ftdf_nr_of_retries++; -#ifndef FTDF_LITE -#ifndef FTDF_NO_CSL - if (ftdf_pib.le_enabled) { - ftdf_set_peer_csl_timing(NULL, 0); - - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_time_t cur_time = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - - ftdf_tx_in_progress = FTDF_TRUE; - REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, - cur_time + 5); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACWUPERIOD, - ftdf_pib.csl_max_period); - - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, - ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER))); - - ftdf_exit_critical(); - - } else -#endif /* FTDF_NO_CSL */ -#endif /* !FTDF_LITE */ - { -#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI - hw_coex_update_ftdf_pti(tx_pti, NULL, true); -#endif - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_DATA_BUFFER)); - } - - return; - - } else { - - if (ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.tx_fail_count++; - } - - status = FTDF_NO_ACK; - } - - } else if (REG_GETF(FTDF, FTDF_TX_RETURN_STATUS_1_0_REG, CSMACAFAIL)) { -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - tsch_retry->nr_of_cca_retries++; - - if (tsch_retry->nr_of_cca_retries < ftdf_pib.max_csma_backoffs) { - - ftdf_tsch_slot_link->request = NULL; - status = ftdf_schedule_tsch(ftdf_req_current); - - if (status == FTDF_SUCCESS) { - /* If ftdf_req_current is not equal to NULL the - * retried request will be queued rather then send again */ - ftdf_req_current = NULL; - } - - } else { - status = FTDF_CHANNEL_ACCESS_FAILURE; - } - } else -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - { - status = FTDF_CHANNEL_ACCESS_FAILURE; - } - - if (ftdf_pib.metrics_enabled && status != FTDF_SUCCESS) { - ftdf_pib.performance_metrics.tx_fail_count++; - } - - } else { - - if (ack_tx == FTDF_FALSE && ftdf_pib.metrics_enabled) { - ftdf_pib.performance_metrics.tx_success_count++; - } - -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - tsch_retry->nr_of_cca_retries = 0; - } -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - } - } - -#ifndef FTDF_PHY_API - if (((ack_tx == FTDF_FALSE) || (status != FTDF_SUCCESS)) && ftdf_req_current) { - send_confirm(status, ftdf_req_current->msg_id); -#ifndef FTDF_LITE - ftdf_process_next_request(); -#endif /* !FTDF_LITE */ - } - -#else - if (ftdf_tx_in_progress) { - send_confirm(status, FTDF_TRANSPARENT_REQUEST); - } -#endif -} - -void ftdf_process_symbol_timer_event(void) -{ -#ifdef FTDF_PHY_API - if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, LMACREADY4SLEEP_D)) { - FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, LMACREADY4SLEEP_D); - - /* If lmac ready 4 sleep, call respective callback, after disabling the interrupt */ - if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 1) { - REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_MASK_REG, LMACREADY4SLEEP_M); - FTDF_LMACREADY4SLEEP_CB(FTDF_TRUE, 0); - } - } -#endif - - /* sync timestamp event */ - if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYNCTIMESTAMP_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYNCTIMESTAMP_E); -#else - FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYNCTIMESTAMP_E); -#endif - - REG_SETF(FTDF, FTDF_TIMER_CONTROL_1_REG, SYNCTIMESTAMPENA, 0); -#ifndef FTDF_LITE -#ifndef FTDF_NO_CSL - ftdf_old_le_enabled = FTDF_FALSE; - - if (ftdf_wake_up_enable_le) { - ftdf_pib.le_enabled = FTDF_TRUE; - ftdf_set_le_enabled(); - ftdf_wake_up_enable_le = FTDF_FALSE; - } -#endif /* FTDF_NO_CSL */ - -#ifndef FTDF_NO_TSCH - if (ftdf_wake_up_enable_tsch) { - ftdf_set_tsch_enabled(); - } -#endif /* FTDF_NO_TSCH */ - - ftdf_restore_tx_pending_timer(); -#endif /* !FTDF_LITE */ - FTDF_WAKE_UP_READY(); - } - - /* miscellaneous event - * - Non-TSCH mode: association timer - * - TSCH mode: next active link timer */ - if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIME2THR_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIME2THR_E); -#else - FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIME2THR_E); -#endif - -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - ftdf_tsch_process_request(); - } else -#endif /* FTDF_NO_TSCH */ - if (ftdf_req_current && (ftdf_req_current->msg_id == FTDF_ASSOCIATE_REQUEST)) { - ftdf_assoc_admin_t* assoc_admin = &ftdf_aa; - - /* macResponseWaitTime expired */ - assoc_admin->data_r = FTDF_TRUE; - - ftdf_send_associate_data_request(); - } -#endif /* !FTDF_LITE */ - } - - /* pending queue symbol timer event */ - if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIMETHR_E)) { -#ifdef SIMULATOR - REG_CLR_BIT(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIMETHR_E); -#else - FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, SYMBOLTIMETHR_E); -#endif - -#ifndef FTDF_LITE - ftdf_remove_tx_pending_timer(NULL); -#endif /* !FTDF_LITE */ - } -} - -#ifndef FTDF_LITE -ftdf_status_t ftdf_send_frame(ftdf_channel_number_t channel, - ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header, - ftdf_octet_t *tx_ptr, - ftdf_data_length_t payload_size, - ftdf_octet_t *payload) -{ - ftdf_octet_t *tx_buf_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG; - - ftdf_data_length_t mic_length = ftdf_get_mic_length(security_header->security_level); - ftdf_data_length_t phy_payload_size = - (tx_ptr - tx_buf_ptr) - 1 + payload_size + mic_length + FTDF_FCS_LENGTH; - - if (phy_payload_size > (FTDF_BUFFER_LENGTH - 1)) { - return FTDF_FRAME_TOO_LONG; - } - - *tx_buf_ptr = phy_payload_size; - - ftdf_octet_t* priv_ptr = tx_ptr; - - int n; - - for (n = 0; n < payload_size; n++) { - *tx_ptr++ = *payload++; - } - - ftdf_status_t status = ftdf_secure_frame(tx_buf_ptr, priv_ptr, frame_header, security_header); - - if (status != FTDF_SUCCESS) { - return status; - } - - ftdf_bitmap8_t options = frame_header->options; - - uint32_t meta_data_0 = 0; - - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAME_LENGTH, meta_data_0, phy_payload_size); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_DEM_PTI, meta_data_0, ((ftdf_pib.cca_mode & 0x3) | 0x08)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_CN, meta_data_0, (channel - 11)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAMETYPE, meta_data_0, frame_header->frame_type); - - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CSMACA_ENA, meta_data_0, 1); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, ACKREQUEST, meta_data_0, - ((options & FTDF_OPT_ACK_REQUESTED) ? 1 : 0)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CRC16_ENA, meta_data_0, 1); - - FTDF->FTDF_TX_META_DATA_0_0_REG = meta_data_0; - - uint32_t meta_data_1 = 0; - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, frame_header->sn); - FTDF->FTDF_TX_META_DATA_1_0_REG = meta_data_1; - - uint32_t tmp = FTDF->FTDF_LMAC_CONTROL_5_REG; - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_DEM_PTI, tmp, (ftdf_pib.cca_mode & 0x3)); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CN, tmp, (channel - 11)); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CALCAP, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_RF_GPIO_PINS, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_HSI, tmp, 0); - FTDF->FTDF_LMAC_CONTROL_5_REG = tmp; - -#ifndef FTDF_NO_CSL - if (ftdf_pib.le_enabled == FTDF_TRUE) { - if (frame_header->dst_addr_mode != FTDF_SHORT_ADDRESS) { - return FTDF_NO_SHORT_ADDRESS; - } - - /* Clear CSMACA of data frame buffer */ - REG_SETF(FTDF, FTDF_TX_META_DATA_0_0_REG, CSMACA_ENA, 0); - - tx_ptr = tx_buf_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_1_0_REG; - - *tx_ptr++ = 0x0d; - *tx_ptr++ = 0x2d; - *tx_ptr++ = 0x81; - *tx_ptr++ = frame_header->sn; - *(ftdf_pan_id_t*)tx_ptr = frame_header->dst_pan_id; - tx_ptr += 2; - *(ftdf_short_address_t*)tx_ptr = frame_header->dst_addr.short_address; - tx_ptr += 2; - *tx_ptr++ = 0x82; - *tx_ptr++ = 0x0e; - - meta_data_0 = 0; - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, FRAME_LENGTH, meta_data_0, 0x0d); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, PHYATTR_DEM_PTI, meta_data_0, ((ftdf_pib.cca_mode & 0x3) | 0x08)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, PHYATTR_CN, meta_data_0, (channel - 11)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, FRAMETYPE, meta_data_0, FTDF_MULTIPURPOSE_FRAME); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, CSMACA_ENA, meta_data_0, 1); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_1_REG, CRC16_ENA, meta_data_0, 1); - FTDF->FTDF_TX_META_DATA_0_1_REG = meta_data_0; - - uint32_t meta_data_1 = 0; - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_1_REG, MACSN, meta_data_1, frame_header->sn); - FTDF->FTDF_TX_META_DATA_1_1_REG = meta_data_1; - -#if FTDF_USE_AUTO_PTI - FTDF->FTDF_TX_PRIORITY_1_REG |= REG_MSK(FTDF, FTDF_TX_PRIORITY_1_REG, ISWAKEUP); -#else - FTDF->FTDF_TX_PRIORITY_1_REG = REG_MSK(FTDF, FTDF_TX_PRIORITY_1_REG, ISWAKEUP); -#endif - } -#endif /* FTDF_NO_CSL */ - -#ifndef FTDF_NO_CSL - if (ftdf_pib.le_enabled == FTDF_TRUE) { - ftdf_time_t cur_time = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - ftdf_time_t delta = cur_time - ftdf_rz_time; - - if (delta > 0x80000000) { - - /* Receiving an wakeup frame sequence, delay sending until RZ has passed. */ - ftdf_send_frame_pending = frame_header->dst_addr.short_address; - - } else { - - ftdf_time_t wakeup_start_time; - ftdf_period_t wakeup_period; - - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_get_wakeup_params(frame_header->dst_addr.short_address, - &wakeup_start_time, &wakeup_period); - - ftdf_tx_in_progress = FTDF_TRUE; - REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, - wakeup_start_time); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACWUPERIOD, wakeup_period); - - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, - ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER))); - - ftdf_exit_critical(); - } - - } else -#endif /* FTDF_NO_CSL */ - if (!ftdf_pib.tsch_enabled) { - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_DATA_BUFFER)); - } - - return FTDF_SUCCESS; -} - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -ftdf_status_t ftdf_send_ack_frame(ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header, - ftdf_octet_t *tx_ptr) -{ - ftdf_octet_t *tx_buf_ptr = ((ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_2_0_REG); - ftdf_data_length_t mic_length = ftdf_get_mic_length(security_header->security_level); - ftdf_data_length_t phy_payload_size = - (tx_ptr - tx_buf_ptr) - 1 + mic_length + FTDF_FCS_LENGTH; - - *tx_buf_ptr = phy_payload_size; - - ftdf_status_t status = ftdf_secure_frame(tx_buf_ptr, - tx_ptr, - frame_header, - security_header); - - if (status != FTDF_SUCCESS) { - return status; - } - - uint32_t meta_data_0 = 0; - - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, FRAME_LENGTH, meta_data_0, phy_payload_size); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, PHYATTR_DEM_PTI, meta_data_0, ((ftdf_pib.cca_mode & 0x3) | 0x08)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, PHYATTR_CN, meta_data_0, REG_GETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, FRAMETYPE, meta_data_0, FTDF_ACKNOWLEDGEMENT_FRAME); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_2_REG, CRC16_ENA, meta_data_0, 1); - - FTDF->FTDF_TX_META_DATA_0_2_REG = meta_data_0; - - uint32_t meta_data_1 = 0; - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_2_REG, MACSN, meta_data_1, frame_header->sn); - FTDF->FTDF_TX_META_DATA_1_2_REG = meta_data_1; - -#if FTDF_USE_AUTO_PTI - REG_SETF(FTDF, FTDF_TX_PRIORITY_2_REG, TX_PRIORITY, 1); -#else - FTDF->FTDF_TX_PRIORITY_2_REG = 1; -#endif - -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_period_t tx_ack_delay_val = - REG_GETF(FTDF, FTDF_MACTSTXACKDELAYVAL_REG, MACTSTXACKDELAYVAL); - - if (tx_ack_delay_val > 20) { - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_ACK_BUFFER)); - } - - ftdf_exit_critical(); - - } else - #endif /* FTDF_NO_TSCH */ - { - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_ACK_BUFFER)); - } - - ftdf_pib.traffic_counters.tx_enh_ack_frm_cnt++; - - return FTDF_SUCCESS; -} -#endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - -void ftdf_send_transparent_frame(ftdf_data_length_t frame_length, - ftdf_octet_t *frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t cmsa_suppress) -{ - uint32_t meta_data_0 = 0; - uint32_t tmp; - -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - ftdf_boolean_t use_ack = FTDF_FALSE; - //ftdf_frame_header_t *frame_header = &ftdf_fh; - ftdf_frame_header_t frame_header; - ftdf_sn_t sn; -#endif - -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - if (ftdf_transparent_mode_options & FTDF_TRANSPARENT_WAIT_FOR_ACK) { - ftdf_get_frame_header(frame, &frame_header); - if (frame_header.options & FTDF_OPT_ACK_REQUESTED) { - use_ack = FTDF_TRUE; - } - sn = frame_header.sn; - } -#endif - - tmp = 0; - REG_SET_FIELD(FTDF, FTDF_TX_PRIORITY_0_REG, PTI_TX, tmp, pti); - REG_SET_FIELD(FTDF, FTDF_TX_PRIORITY_0_REG, TX_PRIORITY, tmp, 1); - FTDF->FTDF_TX_PRIORITY_0_REG = tmp; - - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAME_LENGTH, meta_data_0, frame_length); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_DEM_PTI, meta_data_0, (ftdf_pib.cca_mode & 0x3) | 0x08); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_CN, meta_data_0, (channel - 11)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, PHYATTR_RF_GPIO_PINS, meta_data_0, (ftdf_pib.tx_power & 0x07)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, FRAMETYPE, meta_data_0, (*frame & 0x7)); - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CSMACA_ENA, meta_data_0, ((cmsa_suppress) ? 0 : 1)); - -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, ACKREQUEST, meta_data_0, (use_ack ? 1 : 0)); -#endif - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_0_0_REG, CRC16_ENA, meta_data_0, - ((ftdf_transparent_mode_options & FTDF_TRANSPARENT_ENABLE_FCS_GENERATION) ? 1 : 0)); - - FTDF->FTDF_TX_META_DATA_0_0_REG = meta_data_0; - - uint32_t meta_data_1 = 0; -#if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK - if (use_ack) { - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, sn); - } else { - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, 0); - } -#else - REG_SET_FIELD(FTDF, FTDF_TX_META_DATA_1_0_REG, MACSN, meta_data_1, 0); -#endif - FTDF->FTDF_TX_META_DATA_1_0_REG = meta_data_1; - - tmp = FTDF->FTDF_LMAC_CONTROL_5_REG; - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_DEM_PTI, tmp, (ftdf_pib.cca_mode & 0x3)); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CN, tmp, (channel - 11)); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CALCAP, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_RF_GPIO_PINS, tmp, (ftdf_pib.tx_power & 0x07)); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_HSI, tmp, 0); - FTDF->FTDF_LMAC_CONTROL_5_REG = tmp; - -#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI - hw_coex_update_ftdf_pti((hw_coex_pti_t)pti, NULL, true); -#else - // REG_SETF(FTDF, FTDF_TX_PRIORITY_0_REG, PTI_TX, pti); -#endif - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, (1 << FTDF_TX_DATA_BUFFER)); -} - -void ftdf_init_queues(void) -{ -#ifndef FTDF_LITE - ftdf_init_queue(&ftdf_free_queue); - ftdf_init_queue(&ftdf_req_queue); - - int n; - - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { - ftdf_queue_buffer_head(&ftdf_req_buffers[n], &ftdf_free_queue); - - ftdf_tx_pending_list[n].addr.ext_address = 0xFFFFFFFFFFFFFFFFLL; - ftdf_tx_pending_list[n].addr_mode = FTDF_NO_ADDRESS; - ftdf_tx_pending_list[n].pan_id = 0xFFFF; - ftdf_init_queue(&ftdf_tx_pending_list[n].queue); - - ftdf_tx_pending_timer_list[n].free = FTDF_TRUE; - ftdf_tx_pending_timer_list[n].next = NULL; - } - - ftdf_tx_pending_timer_head = ftdf_tx_pending_timer_list; - ftdf_tx_pending_timer_time = 0; -#endif /* !FTDF_LITE */ -#ifndef FTDF_PHY_API - ftdf_req_current = NULL; -#endif -} - -#ifndef FTDF_LITE -void ftdf_init_queue(ftdf_queue_t *queue) -{ - queue->head.next = (ftdf_buffer_t*)&queue->tail; - queue->head.prev = NULL; - queue->tail.next = NULL; - queue->tail.prev = (ftdf_buffer_t*)&queue->head; -} - -void ftdf_queue_buffer_head(ftdf_buffer_t *buffer, ftdf_queue_t *queue) -{ - ftdf_buffer_t *next = queue->head.next; - - queue->head.next = buffer; - next->header.prev = buffer; - buffer->header.next = next; - buffer->header.prev = (ftdf_buffer_t*)&queue->head; -} - -ftdf_buffer_t *ftdf_dequeue_buffer_tail(ftdf_queue_t *queue) -{ - ftdf_buffer_t *buffer = queue->tail.prev; - - if (buffer->header.prev == NULL) { - return NULL; - } - - queue->tail.prev = buffer->header.prev; - buffer->header.prev->header.next = (ftdf_buffer_t*)&queue->tail; - - return buffer; -} - -ftdf_status_t ftdf_queue_req_head(ftdf_msg_buffer_t *request, ftdf_queue_t *queue) -{ - ftdf_buffer_t *buffer = ftdf_dequeue_buffer_tail(&ftdf_free_queue); - - if (buffer == NULL) { - return FTDF_TRANSACTION_OVERFLOW; - } - - ftdf_buffer_t *next = queue->head.next; - - queue->head.next = buffer; - next->header.prev = buffer; - buffer->header.next = next; - buffer->header.prev = (ftdf_buffer_t*)&queue->head; - buffer->request = request; - - return FTDF_SUCCESS; -} - -ftdf_msg_buffer_t *ftdf_dequeue_req_tail(ftdf_queue_t *queue) -{ - ftdf_buffer_t *buffer = queue->tail.prev; - - if (buffer->header.prev == NULL) { - return NULL; - } - - queue->tail.prev = buffer->header.prev; - buffer->header.prev->header.next = (ftdf_buffer_t*)&queue->tail; - - ftdf_msg_buffer_t *request = buffer->request; - - ftdf_queue_buffer_head(buffer, &ftdf_free_queue); - - return request; -} - -ftdf_msg_buffer_t *ftdf_dequeue_by_handle(ftdf_handle_t handle, ftdf_queue_t *queue) -{ - ftdf_buffer_t *buffer = queue->head.next; - - while (buffer->header.next != NULL) { - if (buffer->request && buffer->request->msg_id == FTDF_DATA_REQUEST && - ((ftdf_data_request_t*)buffer->request)->msdu_handle == handle) { - buffer->header.prev->header.next = buffer->header.next; - buffer->header.next->header.prev = buffer->header.prev; - - ftdf_msg_buffer_t *request = buffer->request; - - ftdf_queue_buffer_head(buffer, &ftdf_free_queue); - - return request; - } - - buffer = buffer->header.next; - } - - return NULL; -} - -ftdf_msg_buffer_t *ftdf_dequeue_by_request(ftdf_msg_buffer_t *request, ftdf_queue_t *queue) -{ - ftdf_buffer_t *buffer = queue->head.next; - - while (buffer->header.next != NULL) { - if (buffer->request == request) { - buffer->header.prev->header.next = buffer->header.next; - buffer->header.next->header.prev = buffer->header.prev; - - ftdf_msg_buffer_t *req = buffer->request; - - ftdf_queue_buffer_head(buffer, &ftdf_free_queue); - - return req; - } - - buffer = buffer->header.next; - } - - return NULL; -} - -ftdf_boolean_t ftdf_is_queue_empty(ftdf_queue_t *queue) -{ - if (queue->head.next->header.next == NULL) { - return FTDF_TRUE; - } else { - return FTDF_FALSE; - } -} - -static ftdf_pending_tl_t *ftdf_find_free_pending_timer(void) -{ - uint8_t i; - - for (i = 0; i < FTDF_NR_OF_REQ_BUFFERS; i++) { - if (ftdf_tx_pending_timer_list[i].free == FTDF_TRUE) { - break; - } - } - - return &ftdf_tx_pending_timer_list[i]; -} - -void ftdf_add_tx_pending_timer(ftdf_msg_buffer_t *request, uint8_t pendListNr, ftdf_time_t delta, - void (*func)(ftdf_pending_tl_t*)) -{ - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_pending_tl_t *ptr = ftdf_tx_pending_timer_head; - ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, - SYMBOLTIMESNAPSHOTVAL); - - if (ptr->free == FTDF_FALSE) { - while (ptr) { - ptr->delta -= timestamp - ftdf_tx_pending_timer_lt; - ptr = ptr->next; - } - } - - ftdf_tx_pending_timer_lt = timestamp; - ptr = ftdf_tx_pending_timer_head; - - if (ptr->free == FTDF_TRUE) { - ptr->free = FTDF_FALSE; - ptr->next = NULL; - ptr->request = request; - ptr->delta = delta; - ptr->pend_list_nr = pendListNr; - ptr->func = func; - - REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, delta + timestamp); - ftdf_tx_pending_timer_time = delta + timestamp; - ftdf_exit_critical(); - return; - } - - if (ptr->delta > delta) { - ftdf_tx_pending_timer_head = ftdf_find_free_pending_timer(); - ftdf_tx_pending_timer_head->free = FTDF_FALSE; - ftdf_tx_pending_timer_head->next = ptr; - ftdf_tx_pending_timer_head->request = request; - ftdf_tx_pending_timer_head->delta = delta; - ftdf_tx_pending_timer_head->pend_list_nr = pendListNr; - ftdf_tx_pending_timer_head->func = func; - - REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, delta + timestamp); - ftdf_tx_pending_timer_time = delta + timestamp; - ftdf_exit_critical(); - - return; - } else if (ptr->delta == delta) { - delta++; - } - - ftdf_pending_tl_t *prev; - - while (ptr->next) { - prev = ptr; - ptr = ptr->next; - - if (ptr->delta == delta) { - delta++; - } - - if (prev->delta < delta && ptr->delta > delta) { - prev->next = ftdf_find_free_pending_timer(); - prev->next->next = ptr; - ptr = prev->next; - ptr->free = FTDF_FALSE; - ptr->request = request; - ptr->delta = delta; - ptr->pend_list_nr = pendListNr; - ptr->func = func; - - ftdf_exit_critical(); - - return; - } - } - - ptr->next = ftdf_find_free_pending_timer(); - ptr = ptr->next; - ptr->free = FTDF_FALSE; - ptr->next = NULL; - ptr->request = request; - ptr->delta = delta; - ptr->pend_list_nr = pendListNr; - ptr->func = func; - - ftdf_exit_critical(); -} - -void ftdf_remove_tx_pending_timer(ftdf_msg_buffer_t *request) -{ - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_pending_tl_t *ptr = ftdf_tx_pending_timer_head; - ftdf_time_t timestamp = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - - if (ptr->free == FTDF_TRUE) { - REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, timestamp - 1); - ftdf_tx_pending_timer_time = timestamp - 1; - ftdf_exit_critical(); - - return; - } - - while (ptr) { - ptr->delta -= timestamp - ftdf_tx_pending_timer_lt; - ptr = ptr->next; - } - - ftdf_tx_pending_timer_lt = timestamp; - ptr = ftdf_tx_pending_timer_head; - - if (!request || ptr->request == request) { - if (ptr->next) { - ftdf_pending_tl_t *temp = ptr; - - if (ptr->next->delta < 75) { - while (temp) { - temp->delta += 75; - temp = temp->next; - } - } - - REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, - timestamp + ptr->next->delta); - ftdf_tx_pending_timer_time = timestamp + ptr->next->delta; - ftdf_tx_pending_timer_head = ptr->next; - - ptr->free = FTDF_TRUE; - ptr->next = NULL; - } else { - REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, timestamp - 1); - ftdf_tx_pending_timer_time = timestamp - 1; - - ptr->free = FTDF_TRUE; - ptr->next = NULL; - } - - ftdf_exit_critical(); - - if (!request) { - if (ptr->func) { - ptr->func(ptr); - } - } - - return; - } - - ftdf_pending_tl_t *prev = ptr; - - while (ptr->next) { - prev = ptr; - ptr = ptr->next; - - if (ptr->request == request) { - prev->next = ptr->next; - ptr->free = FTDF_TRUE; - ptr->next = NULL; - - ftdf_exit_critical(); - - return; - } - } - - REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, timestamp - 1); - ftdf_tx_pending_timer_time = timestamp - 1; - ftdf_exit_critical(); -} - -void ftdf_restore_tx_pending_timer(void) -{ - REG_SETF(FTDF, FTDF_SYMBOLTIMETHR_REG, SYMBOLTIMETHR, ftdf_tx_pending_timer_time); -} - -ftdf_boolean_t ftdf_get_tx_pending_timer_head(ftdf_time_t *time) -{ - ftdf_pending_tl_t *ptr = ftdf_tx_pending_timer_head; - - if (ptr->free == FTDF_TRUE) { - return FTDF_FALSE; - } - - *time = ftdf_tx_pending_timer_time; - - return FTDF_TRUE; -} - -#ifndef FTDF_NO_TSCH -void ftdf_process_keep_alive_timer_exp(ftdf_pending_tl_t *ptr) { - ftdf_remote_request_t *remote_request = (ftdf_remote_request_t*)ptr->request; - - remote_request->msg_id = FTDF_REMOTE_REQUEST; - remote_request->remote_id = FTDF_REMOTE_KEEP_ALIVE; - remote_request->dst_addr = ftdf_neighbor_table[ptr->pend_list_nr].dst_addr; - - ftdf_process_remote_request(remote_request); -} -#endif /* FTDF_NO_TSCH */ - -void ftdf_send_transaction_expired(ftdf_pending_tl_t *ptr) -{ - ftdf_msg_buffer_t *req = - ftdf_dequeue_by_request(ptr->request, - &ftdf_tx_pending_list[ptr->pend_list_nr].queue); - - if (!req) { - return; - } - - if (ftdf_is_queue_empty(&ftdf_tx_pending_list[ptr->pend_list_nr].queue)) { -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - ftdf_tx_pending_list[ptr->pend_list_nr].addr.short_address = 0xfffe; - } else -#endif /* FTDF_NO_TSCH */ - { -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - if (ftdf_tx_pending_list[ptr->pend_list_nr].addr_mode == FTDF_SHORT_ADDRESS) { - uint8_t entry, short_addr_idx; - ftdf_boolean_t found = ftdf_fppr_lookup_short_address( - ftdf_tx_pending_list[ptr->pend_list_nr].addr.short_address, &entry, - &short_addr_idx); - ASSERT_WARNING(found); - ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_FALSE); - } else if (ftdf_tx_pending_list[ptr->pend_list_nr].addr_mode == FTDF_EXTENDED_ADDRESS) { - uint8_t entry; - ftdf_boolean_t found = ftdf_fppr_lookup_ext_address( - ftdf_tx_pending_list[ptr->pend_list_nr].addr.ext_address, &entry); - ASSERT_WARNING(found); - ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); - } else { - ASSERT_WARNING(0); - } -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - ftdf_tx_pending_list[ptr->pend_list_nr].addr_mode = FTDF_NO_ADDRESS; - } - } - - switch (req->msg_id) { - case FTDF_DATA_REQUEST: - { - ftdf_data_request_t *data_request = (ftdf_data_request_t*)req; - - ftdf_send_data_confirm(data_request, FTDF_TRANSACTION_EXPIRED, 0, 0, 0, NULL); - - break; - } - case FTDF_ASSOCIATE_REQUEST: - { - ftdf_associate_request_t* associate_request = (ftdf_associate_request_t*)req; - - ftdf_send_associate_confirm(associate_request, FTDF_TRANSACTION_EXPIRED, 0xffff); - - break; - } - case FTDF_ASSOCIATE_RESPONSE: - { - ftdf_associate_response_t *assoc_resp = (ftdf_associate_response_t*)req; - - ftdf_address_t src_addr, dst_addr; - src_addr.ext_address = ftdf_pib.ext_address; - dst_addr.ext_address = assoc_resp->device_address; - - ftdf_send_comm_status_indication(req, FTDF_TRANSACTION_EXPIRED, - ftdf_pib.pan_id, - FTDF_EXTENDED_ADDRESS, - src_addr, - FTDF_EXTENDED_ADDRESS, - dst_addr, - assoc_resp->security_level, - assoc_resp->key_id_mode, - assoc_resp->key_source, - assoc_resp->key_index); - - break; - } - case FTDF_DISASSOCIATE_REQUEST: - { - ftdf_disassociate_request_t* dis_req = (ftdf_disassociate_request_t*)req; - - ftdf_send_disassociate_confirm(dis_req, FTDF_TRANSACTION_EXPIRED); - - break; - } - case FTDF_BEACON_REQUEST: - { - ftdf_beacon_request_t* beacon_request = (ftdf_beacon_request_t*)req; - - ftdf_send_beacon_confirm(beacon_request, FTDF_TRANSACTION_EXPIRED); - - break; - } - } -} - -#ifndef FTDF_NO_TSCH -void ftdf_reset_keep_alive_timer(ftdf_short_address_t dst_addr) -{ - uint8_t n; - - for (n = 0; n < FTDF_NR_OF_NEIGHBORS; n++) { - if (ftdf_neighbor_table[n].dst_addr == dst_addr) { - break; - } - } - - if (n == FTDF_NR_OF_NEIGHBORS) { - return; - } - - ftdf_remove_tx_pending_timer((ftdf_msg_buffer_t*)&ftdf_neighbor_table[n].msg); - - ftdf_time_t ts_timeslot_length = (ftdf_time_t)ftdf_pib.timeslot_template.ts_timeslot_length - / 16; - ftdf_time_t delta = ts_timeslot_length * ftdf_neighbor_table[n].period; - - ftdf_add_tx_pending_timer((ftdf_msg_buffer_t*)&ftdf_neighbor_table[n].msg, n, delta, - ftdf_process_keep_alive_timer_exp); -} -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - -void ftdf_enable_transparent_mode(ftdf_boolean_t enable, - ftdf_bitmap32_t options) -{ -#ifndef FTDF_LITE - if ((ftdf_pib.le_enabled == FTDF_TRUE) || (ftdf_pib.tsch_enabled == FTDF_TRUE)) { - return; - } -#endif /* !FTDF_LITE */ - - - ftdf_transparent_mode = enable; - ftdf_transparent_mode_options = options; - - uint32_t tmp = FTDF->FTDF_RX_CONTROL_0_REG; - - if (enable) { - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSFRMTYPE, tmp, - (options & FTDF_TRANSPARENT_PASS_ALL_FRAME_TYPES)); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, DISRXACKREQUESTCA, tmp, - (options & FTDF_TRANSPARENT_AUTO_ACK ? 0 : 1)); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSCRCERROR, tmp, - (options & FTDF_TRANSPARENT_PASS_CRC_ERROR ? 1 : 0)); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSRESFRAMEVERSION, tmp, - (options & FTDF_TRANSPARENT_PASS_ALL_FRAME_VERSION ? 1 : 0)); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDPANID, tmp, - (options & FTDF_TRANSPARENT_PASS_ALL_PAN_ID ? 1 : 0)); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDADDR, tmp, - (options & FTDF_TRANSPARENT_PASS_ALL_ADDR ? 1 : 0)); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSBEACONWRONGPANID, tmp, - (options & FTDF_TRANSPARENT_PASS_ALL_BEACON ? 1 : 0)); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSTOPANCOORDINATOR, tmp, - (options & FTDF_TRANSPARENT_PASS_ALL_NO_DEST_ADDR ? 1 : 0)); - } else { - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSFRMTYPE, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, DISRXACKREQUESTCA, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSCRCERROR, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSRESFRAMEVERSION, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDPANID, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSWRONGDADDR, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSBEACONWRONGPANID, tmp, 0); - REG_SET_FIELD(FTDF, FTDF_RX_CONTROL_0_REG, MACALWAYSPASSTOPANCOORDINATOR, tmp, 0); - } - - FTDF->FTDF_RX_CONTROL_0_REG = tmp; -} - -#if FTDF_DBG_BUS_ENABLE -void ftdf_check_dbg_mode(void) -{ - REG_SET_MASKED(FTDF, FTDF_DEBUGCONTROL_REG, 0xFF, ftdf_dbg_mode); - if (ftdf_dbg_mode) { - FTDF_DBG_BUS_GPIO_CONFIG(); - } -} - -void ftdf_set_dbg_mode(ftdf_dbg_mode_t dbg_mode) -{ - ftdf_dbg_mode = dbg_mode; - ftdf_check_dbg_mode(); -} -#endif /* FTDF_DBG_BUS_ENABLE */ - -#ifndef FTDF_LITE -#ifndef FTDF_NO_CSL -void ftdf_set_peer_csl_timing(ftdf_ie_list_t *header_ie_list, ftdf_time_t time_stamp) -{ - if (ftdf_req_current->msg_id != FTDF_DATA_REQUEST) { - /* Only use the CSL timing of data frame acks */ - return; - } - - ftdf_data_request_t* data_request = (ftdf_data_request_t*)ftdf_req_current; - ftdf_short_address_t dst_addr = data_request->dst_addr.short_address; - - if ((data_request->dst_addr_mode != FTDF_SHORT_ADDRESS) || (dst_addr == 0xffff)) { - return; - } - - int n; - - /* Search for an existing entry */ - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { - if (ftdf_peer_csl_timing[n].addr == dst_addr) { - break; - } - } - - if (header_ie_list == NULL) { - if (n < FTDF_NR_OF_CSL_PEERS) { - /* Delete entry */ - ftdf_peer_csl_timing[n].addr = 0xffff; - } - - return; - } - - int ie_nr = 0; - - while (ie_nr < header_ie_list->nr_of_ie && header_ie_list->ie[ie_nr].id != 0x1a) { - ie_nr++; - } - - if (ie_nr == header_ie_list->nr_of_ie) { - return; - } - - if (n == FTDF_NR_OF_CSL_PEERS) { - /* Search for an empty entry */ - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { - if (ftdf_peer_csl_timing[n].addr == 0xffff) { - break; - } - } - } - - if (n == FTDF_NR_OF_CSL_PEERS) { - /* No free entry, search for the least recently used entry */ - ftdf_time_t max_delta = 0; - int lru = 0; - - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { - ftdf_time_t delta = time_stamp - ftdf_peer_csl_timing[n].time; - - if (delta > max_delta) { - max_delta = delta; - lru = n; - } - } - - n = lru; - } - - ftdf_period_t phase = (*(ftdf_period_t*)(header_ie_list->ie[0].content.raw + 0)); - ftdf_period_t period = (*(ftdf_period_t*)(header_ie_list->ie[0].content.raw + 2)); - - ftdf_peer_csl_timing[n].addr = dst_addr; - ftdf_peer_csl_timing[n].time = time_stamp - (phase * 10); - ftdf_peer_csl_timing[n].period = period; -} - -void ftdf_get_wakeup_params(ftdf_short_address_t dst_addr, ftdf_time_t *wakeup_start_time, - ftdf_period_t *wakeup_period) -{ - int n; - - for (n = 0; n < FTDF_NR_OF_CSL_PEERS; n++) { - if (ftdf_peer_csl_timing[n].addr == dst_addr) { - break; - } - } - - ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, - SYMBOLTIMESNAPSHOTVAL); - - if (dst_addr == 0xffff || - n == FTDF_NR_OF_CSL_PEERS) { - *wakeup_start_time = cur_time + 5; - *wakeup_period = ftdf_pib.csl_max_period; - - return; - } - - ftdf_time_t peer_time = ftdf_peer_csl_timing[n].time; - ftdf_time_t peer_period = ftdf_peer_csl_timing[n].period * 10; - ftdf_time_t delta = cur_time - peer_time; - - if (delta > (uint32_t)(ftdf_pib.csl_max_age_remote_info * 10)) { - *wakeup_start_time = cur_time + 5; - *wakeup_period = ftdf_pib.csl_max_period; - - return; - } - - ftdf_time_t w_start = peer_time + (((delta / peer_period) + 1) * peer_period) - - ftdf_pib.csl_sync_tx_margin; - delta = w_start - cur_time; - - /* A delta larger than 0x80000000 is assumed a negative delta */ - if ((delta < 3) || (delta > 0x80000000)) { - w_start += peer_period; - } - - *wakeup_period = (ftdf_pib.csl_sync_tx_margin / 10) * 2; - *wakeup_start_time = w_start; -} - -void ftdf_set_csl_sample_time(void) -{ - ftdf_time_t csl_period = ftdf_pib.csl_period * 10; - - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - ftdf_time_t delta = (cur_time - ftdf_start_csl_sample_time); - - /* A delta larger than 0x80000000 is assumed a negative delta, in this case the sample time - * does not need to be updated. */ - if (delta < 0x80000000) { - if (delta < csl_period) { - ftdf_start_csl_sample_time += csl_period; - - if (delta < 3) { - /* To avoid to set the CSL sample time to a time stamp in the past - * set it to a sample period later if the next sample would be - * within 3 symbols. */ - ftdf_start_csl_sample_time += csl_period; - } - - } else { - - ftdf_start_csl_sample_time = - ftdf_start_csl_sample_time + ((delta / csl_period) + 1) * csl_period; - } - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, ftdf_start_csl_sample_time); - } - - ftdf_exit_critical(); -} -#endif /* FTDF_NO_CSL */ -#endif /* !FTDF_LITE */ - -ftdf_time64_t ftdf_get_cur_time64(void) -{ - ftdf_time_t new_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - - if (new_time < ftdf_cur_time[0]) { - ftdf_cur_time[1]++; - } - - ftdf_cur_time[0] = new_time; - - return *(ftdf_time64_t*)ftdf_cur_time; -} - -void ftdf_init_cur_time64(void) -{ - ftdf_cur_time[0] = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - ftdf_cur_time[1] = 0; -} - -void ftdf_get_ext_address(void) -{ - uint32_t *ext_address = (uint32_t*)&ftdf_pib.ext_address; - - ext_address[0] = REG_GETF(FTDF, FTDF_GLOB_CONTROL_2_REG, AEXTENDEDADDRESS_L); - ext_address[1] = REG_GETF(FTDF, FTDF_GLOB_CONTROL_3_REG, AEXTENDEDADDRESS_H); -} - -void ftdf_set_ext_address(void) -{ - uint32_t *ext_address = (uint32_t*)&ftdf_pib.ext_address; - - REG_SETF(FTDF, FTDF_GLOB_CONTROL_2_REG, AEXTENDEDADDRESS_L, ext_address[0]); - REG_SETF(FTDF, FTDF_GLOB_CONTROL_3_REG, AEXTENDEDADDRESS_H, ext_address[1]); -} - -void ftdf_get_ack_wait_duration(void) -{ - ftdf_pib.ack_wait_duration = REG_GETF(FTDF, FTDF_MACACKWAITDURATION_REG, MACACKWAITDURATION); -} - -#ifndef FTDF_LITE -void ftdf_get_enh_ack_wait_duration(void) -{ - ftdf_pib.enh_ack_wait_duration = REG_GETF(FTDF, FTDF_MACENHACKWAITDURATION_REG, - MACENHACKWAITDURATION); -} - -void ftdf_set_enh_ack_wait_duration(void) -{ - REG_SETF(FTDF, FTDF_MACENHACKWAITDURATION_REG, MACENHACKWAITDURATION, - ftdf_pib.enh_ack_wait_duration); -} - -void ftdf_get_implicit_broadcast(void) -{ - ftdf_pib.implicit_broadcast = REG_GETF(FTDF, FTDF_RX_CONTROL_0_REG, MACIMPLICITBROADCAST); -} - -void ftdf_set_implicit_broadcast(void) -{ - REG_SETF(FTDF, FTDF_RX_CONTROL_0_REG, MACIMPLICITBROADCAST, ftdf_pib.implicit_broadcast); -} -#endif /* !FTDF_LITE */ - -void ftdf_set_short_address(void) -{ - REG_SETF(FTDF, FTDF_GLOB_CONTROL_1_REG, MACSHORTADDRESS, ftdf_pib.short_address); -} - -#ifndef FTDF_LITE -void ftdf_set_simple_address(void) -{ - REG_SETF(FTDF, FTDF_GLOB_CONTROL_0_REG, MACSIMPLEADDRESS, ftdf_pib.simple_address); -} -#endif /* !FTDF_LITE */ - -void ftdf_get_rx_on_when_idle(void) -{ - ftdf_pib.rx_on_when_idle = REG_GETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXALWAYSON); -} - -void ftdf_set_rx_on_when_idle(void) -{ -#if dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI - /* We do not force decision here. It will be automatically made when FTDF begins - * transaction. - */ - hw_coex_update_ftdf_pti((hw_coex_pti_t)ftdf_get_rx_pti(), NULL, false); -#endif /* dg_configCOEX_ENABLE_CONFIG && !FTDF_USE_AUTO_PTI */ - ftdf_set_link_quality_mode(); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 0); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, RXALWAYSON, ftdf_pib.rx_on_when_idle); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, RXENABLE, 1); - -} - -void ftdf_getpan_id(void) -{ - ftdf_pib.pan_id = REG_GETF(FTDF, FTDF_GLOB_CONTROL_1_REG, MACPANID); -} - -void ftdf_setpan_id(void) -{ - REG_SETF(FTDF, FTDF_GLOB_CONTROL_1_REG, MACPANID, ftdf_pib.pan_id); -} - -void ftdf_get_current_channel(void) -{ - ftdf_pib.current_channel = (REG_GETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN)) + 11; -} - -void ftdf_set_current_channel(void) -{ - uint32_t phy_ack_attr = 0; - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_CN, (ftdf_pib.current_channel - 11)); - - ftdf_set_link_quality_mode(); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_DEM_PTI, phy_ack_attr, 0x08); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_CN, phy_ack_attr, - (ftdf_pib.current_channel - 11)); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_RF_GPIO_PINS, phy_ack_attr, - (ftdf_pib.tx_power & 0x07)); - - FTDF->FTDF_LMAC_CONTROL_4_REG = phy_ack_attr; -} - -void ftdf_set_tx_power(void) -{ - /* Just like setCurrentChannel, this sets pyAckAttr */ - uint32_t phy_ack_attr = 0; - - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_DEM_PTI, phy_ack_attr, 0x08); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_CN, phy_ack_attr, - (ftdf_pib.current_channel - 11)); - REG_SET_FIELD(FTDF, FTDF_LMAC_CONTROL_4_REG, PHYACKATTR_RF_GPIO_PINS, phy_ack_attr, - (ftdf_pib.tx_power & 0x07)); - - FTDF->FTDF_LMAC_CONTROL_4_REG = phy_ack_attr; -} - -void ftdf_get_max_frame_total_wait_time(void) -{ - ftdf_pib.max_frame_total_wait_time = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, MACMAXFRAMETOTALWAITTIME); -} - -void ftdf_set_max_frame_total_wait_time(void) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, MACMAXFRAMETOTALWAITTIME, ftdf_pib.max_frame_total_wait_time); -} - -void ftdf_set_max_csma_backoffs(void) -{ -#ifndef FTDF_LITE - if ((ftdf_pib.le_enabled == FTDF_FALSE) && (ftdf_pib.tsch_enabled == FTDF_FALSE)) -#endif /* !FTDF_LITE */ - { - REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXCSMABACKOFFS, ftdf_pib.max_csma_backoffs); - } -} - -void ftdf_set_max_be(void) -{ - REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXBE, ftdf_pib.max_be); -} - -void ftdf_set_min_be(void) -{ -#ifndef FTDF_LITE - if ((ftdf_pib.le_enabled == FTDF_FALSE) && (ftdf_pib.tsch_enabled == FTDF_FALSE)) -#endif /* !FTDF_LITE */ - { - REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMINBE, ftdf_pib.min_be); - } -} - -#ifndef FTDF_LITE -#ifndef FTDF_NO_CSL -void ftdf_set_le_enabled(void) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACCSLSAMPLEPERIOD, 66); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_9_REG, MACCSLDATAPERIOD, 66); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_10_REG, MACCSLMARGINRZ, 1); - - if (ftdf_pib.le_enabled) { - REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXCSMABACKOFFS, 0); - REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMINBE, 0); - - if (ftdf_old_le_enabled == FTDF_FALSE) { - - if (ftdf_wake_up_enable_le == FTDF_FALSE) { - ftdf_start_csl_sample_time = - REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - ftdf_set_csl_sample_time(); - - } else { - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, - ftdf_start_csl_sample_time); - } - } - - } else { - - REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMAXCSMABACKOFFS, ftdf_pib.max_csma_backoffs); - REG_SETF(FTDF, FTDF_TX_CONTROL_0_REG, MACMINBE, ftdf_pib.min_be); - } - - REG_SETF(FTDF, FTDF_GLOB_CONTROL_0_REG, MACLEENABLED, ftdf_pib.le_enabled); - - ftdf_old_le_enabled = ftdf_pib.le_enabled; -} - -void ftdf_get_csl_frame_pending_wait(void) -{ - ftdf_pib.csl_frame_pending_wait = REG_GETF(FTDF, FTDF_LMAC_CONTROL_9_REG, MACCSLFRAMEPENDINGWAITT); -} - -void ftdf_set_csl_frame_pending_wait(void) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_9_REG, MACCSLFRAMEPENDINGWAITT, - ftdf_pib.csl_frame_pending_wait); -} -#endif /* FTDF_NO_CSL */ -#endif /* !FTDF_LITE */ - -void ftdf_get_lmac_pm_data(void) -{ - ftdf_pib.performance_metrics.fcs_error_count = - REG_GETF(FTDF, FTDF_MACFCSERRORCOUNT_REG, MACFCSERRORCOUNT) + - ftdf_lmac_counters.fcs_error_cnt; -} - -void ftdf_get_lmac_traffic_counters(void) -{ - ftdf_pib.traffic_counters.tx_std_ack_frm_cnt = - REG_GETF(FTDF, FTDF_MACTXSTDACKFRMCNT_REG, MACTXSTDACKFRMCNT) + - ftdf_lmac_counters.tx_std_ack_cnt; - - ftdf_pib.traffic_counters.rx_std_ack_frm_ok_cnt = - REG_GETF(FTDF, FTDF_MACRXSTDACKFRMOKCNT_REG, MACRXSTDACKFRMOKCNT) + - ftdf_lmac_counters.rx_std_ack_cnt; -} - -void ftdf_get_keep_phy_enabled(void) -{ - ftdf_pib.keep_phy_enabled = REG_GETF(FTDF, FTDF_LMAC_CONTROL_0_REG, KEEP_PHY_EN); -} - -void ftdf_set_keep_phy_enabled(void) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, KEEP_PHY_EN, ftdf_pib.keep_phy_enabled); -} - -void ftdf_set_bo_irq_threshold(void) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_BO_THRESHOLD, ftdf_pib.bo_irq_threshold); -} -void ftdf_get_bo_irq_threshold(void) -{ - ftdf_pib.bo_irq_threshold = REG_GETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_BO_THRESHOLD); -} -void ftdf_set_pti_config(void) -{ - REG_SETF(FTDF, FTDF_TX_PRIORITY_0_REG, PTI_TX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_TX]); - REG_SETF(FTDF, FTDF_TX_PRIORITY_1_REG, PTI_TX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_TX]); - REG_SETF(FTDF, FTDF_TX_PRIORITY_2_REG, PTI_TX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_RX]); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_0_REG, PTI_RX, ftdf_pib.pti_config.ptis[FTDF_PTI_CONFIG_RX]); -} - -#ifndef FTDF_LITE -#ifndef FTDF_NO_TSCH -void ftdf_set_timeslot_template(void) -{ - REG_SETF(FTDF, FTDF_TSCH_CONTROL_0_REG, MACTSTXACKDELAY, - ftdf_pib.timeslot_template.ts_tx_ack_delay); - REG_SETF(FTDF, FTDF_TSCH_CONTROL_0_REG, MACTSRXWAIT, ftdf_pib.timeslot_template.ts_rx_wait); - REG_SETF(FTDF, FTDF_TSCH_CONTROL_2_REG, MACTSRXACKDELAY, - ftdf_pib.timeslot_template.ts_rx_ack_delay); - REG_SETF(FTDF, FTDF_TSCH_CONTROL_2_REG, MACTSACKWAIT, - ftdf_pib.timeslot_template.ts_ack_wait); - REG_SETF(FTDF, FTDF_TSCH_CONTROL_1_REG, MACTSRXTX, (ftdf_pib.timeslot_template.ts_rx_tx - - FTDF_PHYTRXWAIT - FTDF_PHYTXSTARTUP - FTDF_PHYTXLATENCY)); -} -#endif /* FTDF_NO_TSCH */ -#endif /* !FTDF_LITE */ - -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO -/************************************ FPPR common functions ***************************************/ -#ifndef FTDF_LITE - -ftdf_boolean_t ftdf_fp_fsm_short_address_new(ftdf_pan_id_t panId, ftdf_short_address_t short_address) -{ - uint8_t entry; - uint8_t short_addr_idx; - - if (ftdf_fppr_get_free_short_address(&entry, &short_addr_idx) == FTDF_FALSE) { - return FTDF_FALSE; - } - - ftdf_fppr_set_short_address(entry, short_addr_idx, short_address); - ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_TRUE); - - return FTDF_TRUE; -} - -ftdf_boolean_t ftdf_fp_fsm_rxt_address_new(ftdf_pan_id_t panId, ftdf_ext_address_t ext_address) -{ - uint8_t entry; - - if (ftdf_fppr_get_free_ext_address(&entry) == FTDF_FALSE) { - return FTDF_FALSE; - } - - ftdf_fppr_set_ext_address(entry, ext_address); - ftdf_fppr_set_ext_address_valid(entry, FTDF_TRUE); - - return FTDF_TRUE; -} - -void ftdf_fp_fsm_short_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_short_address_t short_address) { -#if FTDF_FPPR_DEFER_INVALIDATION - ftdf_fppr_pending.addr_mode = FTDF_SHORT_ADDRESS; - ftdf_fppr_pending.pan_id = pan_id; - ftdf_fppr_pending.addr.short_address = short_address; -#else /* FTDF_FPPR_DEFER_INVALIDATION */ - uint8_t entry; - uint8_t short_addr_idx; - ftdf_boolean_t found = ftdf_fppr_lookup_short_address(short_address, &entry, &short_addr_idx); - ASSERT_WARNING(found); - ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_FALSE); -#endif /* FTDF_FPPR_DEFER_INVALIDATION */ -} - -void ftdf_fp_fsm_ext_address_last_frame_pending(ftdf_pan_id_t pan_id, ftdf_ext_address_t ext_address) { -#if FTDF_FPPR_DEFER_INVALIDATION - ftdf_fppr_pending.addr_mode = FTDF_EXTENDED_ADDRESS; - ftdf_fppr_pending.pan_id = pan_id; - ftdf_fppr_pending.addr.ext_address = ext_address; -#else /* FTDF_FPPR_DEFER_INVALIDATION */ - uint8_t entry; - ftdf_boolean_t found = ftdf_fppr_lookup_ext_address(ext_address, &entry); - ASSERT_WARNING(found); - ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); -#endif /* FTDF_FPPR_DEFER_INVALIDATION */ -} - -void ftdf_fp_fsm_clear_pending(void) -{ -#if FTDF_FPPR_DEFER_INVALIDATION - int n; - if (ftdf_fppr_pending.addr_mode == FTDF_NO_ADDRESS) { - return; - } - if (ftdf_fppr_pending.addr_mode == FTDF_SHORT_ADDRESS) { - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { - if (ftdf_tx_pending_list[n].addr_mode == FTDF_SHORT_ADDRESS) { - if ((ftdf_tx_pending_list[n].pan_id == ftdf_fppr_pending.pan_id) && - (ftdf_tx_pending_list[n].addr.short_address == - ftdf_fppr_pending.addr.short_address)) { - return; - } - } - } - // Address not found. - uint8_t entry; - uint8_t short_addr_idx; - ftdf_boolean_t found = ftdf_fppr_lookup_short_address( - ftdf_fppr_pending.addr.short_address, &entry, &short_addr_idx); - ASSERT_WARNING(found); - ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_FALSE); - } else if (ftdf_fppr_pending.addr_mode == FTDF_EXTENDED_ADDRESS) { - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { - if (ftdf_tx_pending_list[n].addr_mode == FTDF_EXTENDED_ADDRESS) { - if (ftdf_tx_pending_list[n].addr.ext_address == - ftdf_fppr_pending.addr.ext_address) { - return; - } - } - } - // Address not found. - uint8_t entry; - ftdf_boolean_t found = ftdf_fppr_lookup_ext_address(ftdf_fppr_pending.addr.ext_address, - &entry); - ASSERT_WARNING(found); - ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); - } else { - - } - ftdf_fppr_pending.addr_mode = FTDF_NO_ADDRESS; -#endif /* FTDF_FPPR_DEFER_INVALIDATION */ -} - -#endif /* #ifndef FTDF_LITE */ -/*********************************** FPPR low-level access ****************************************/ -void ftdf_fppr_reset(void) -{ - unsigned int i; - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { - *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i) = 0; - } -} - -ftdf_short_address_t ftdf_fppr_get_short_address(uint8_t entry, uint8_t short_addr_idx) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - switch (short_addr_idx) { - case 0: - return (ftdf_short_address_t) - *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry) & - 0x0000ffff; - case 1: - return (ftdf_short_address_t) - (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry) >> 16) & - 0x0000ffff; - case 2: - return (ftdf_short_address_t) - *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry) & - 0x0000ffff; - case 3: - return (ftdf_short_address_t) - (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry) >> 16) & - 0x0000ffff; - default: - ASSERT_WARNING(0); - } -} - -void ftdf_fppr_set_short_address(uint8_t entry, uint8_t short_addr_idx, - ftdf_short_address_t short_address) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - uint32_t val32; - volatile uint32_t *long_addr_reg; - switch (short_addr_idx) { - case 0: - long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry); - val32 = *long_addr_reg; - val32 &= 0xffff0000; - val32 |= (short_address & 0x0000ffff); - *long_addr_reg = val32; - break; - case 1: - long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry); - val32 = *long_addr_reg; - val32 &= 0x0000ffff; - val32 |= (short_address & 0x0000ffff) << 16; - *long_addr_reg = val32; - break; - case 2: - long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry); - val32 = *long_addr_reg; - val32 &= 0xffff0000; - val32 |= (short_address & 0x0000ffff); - *long_addr_reg = val32; - break; - case 3: - long_addr_reg = REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry); - val32 = *long_addr_reg; - val32 &= 0x0000ffff; - val32 |= (short_address & 0x0000ffff) << 16; - *long_addr_reg = val32; - break; - default: - ASSERT_WARNING(0); - } -} - -ftdf_boolean_t ftdf_fppr_get_short_address_valid(uint8_t entry, uint8_t short_addr_idx) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - ASSERT_WARNING(short_addr_idx < 4); - uint32_t val32 = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry); - return ((val32 & (REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT) | (1 << short_addr_idx))) == - (REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT) | (1 << short_addr_idx))) ? - FTDF_TRUE : FTDF_FALSE; -} - -void ftdf_fppr_set_short_address_valid(uint8_t entry, uint8_t short_addr_idx, - ftdf_boolean_t valid) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - ASSERT_WARNING(short_addr_idx < 4); - volatile uint32_t *reg_val = REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry); - if (valid) { - *reg_val |= REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT) | (1 << short_addr_idx); /* Also indicate short address. */ - } else { - *reg_val &= ~(1 << short_addr_idx); - } -} - -ftdf_ext_address_t ftdf_fppr_get_ext_address(uint8_t entry) -{ - ftdf_ext_address_t ext_address; - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - ext_address = (ftdf_ext_address_t) - (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry)) << 32; - ext_address |= (ftdf_ext_address_t) - (*REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry)); - - return ext_address; -} - -void ftdf_fppr_set_ext_address(uint8_t entry, ftdf_ext_address_t ext_address) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, 0x10, entry) = (uint32_t) ext_address; - *REG_GET_ADDR_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, 0x10, entry) = (uint32_t) (ext_address >> 32); -} - -ftdf_boolean_t ftdf_fppr_get_ext_address_valid(uint8_t entry) -{ - return (REG_GETF_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, VALID_SA, 0x10, entry) == 0x1) ? - FTDF_TRUE : FTDF_FALSE; -} - -void ftdf_fppr_set_ext_address_valid(uint8_t entry, ftdf_boolean_t valid) -{ - ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); - if (valid) { - /* Also indicate ext address. */ - *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry) = 0x1; - } else { - *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, entry) = 0x0; - } -} - -ftdf_boolean_t ftdf_fppr_get_free_short_address(uint8_t *entry, uint8_t *short_addr_idx) -{ - int i, j; - uint32_t size_and_val; - int empty_entry; - bool empty_found = false, non_empty_found = false; - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { - size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); - if (size_and_val == 0x1) { - /* Check if there is a valid extended address. */ - continue; - } else if ((size_and_val & REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT)) == 0) { - /* There is an invalid extended address, ignore SA valid bits */ - size_and_val = 0; - } else { - /* There is a SA. We are interested in bits V0 - V3. */ - size_and_val &= 0xf; - } - - /* Check if entire entry is free. */ - if (size_and_val == 0) { - /* We prefer to use partially full entries. Make note of this and - * continue. */ - if (!empty_found) { - empty_entry = i; - empty_found = true; - } - continue; - } - /* Check for free short address entries. */ - size_and_val = (~size_and_val) & 0xf; - j = 0; - while (size_and_val) { - if (size_and_val & 0x1) { - non_empty_found = true; - break; - } - size_and_val >>= 1; - j++; - } - if (non_empty_found) { - break; - } - } - if (non_empty_found) { - *entry = i; - *short_addr_idx = j; - } else if (empty_found) { - *entry = empty_entry; - *short_addr_idx = 0; - } else { - return FTDF_FALSE; - } - return FTDF_TRUE; -} - -ftdf_boolean_t ftdf_fppr_get_free_ext_address(uint8_t * entry) -{ - int i; - uint32_t size_and_val; - bool found = false; - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { - size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); - /* Check if there is no valid extended or short address. */ - if (!size_and_val || (size_and_val == REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT))) { - found = true; - break; - } - } - if (found) { - *entry = i; - } else { - return FTDF_FALSE; - } - return FTDF_TRUE; -} - -ftdf_boolean_t ftdf_fppr_lookup_short_address(ftdf_short_address_t short_addr, uint8_t *entry, - uint8_t *short_addr_idx) -{ - uint8_t i; - uint32_t size_and_val; - uint32_t saPart; - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { - size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); - /* Check if there is a valid short address. */ - if (!(size_and_val & REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, SHORT_LONGNOT)) || - !(size_and_val & REG_MSK(FTDF, FTDF_SIZE_AND_VAL_0_REG, VALID_SA))) { - continue; - } - saPart = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, EXP_SA_L, 0x10, i); - if (size_and_val & 0x1) { - if (short_addr == (ftdf_short_address_t) (saPart & 0x0000ffff)) { - *entry = i; - *short_addr_idx = 0; - return FTDF_TRUE; - } - } - if (size_and_val & 0x2) { - if (short_addr == (ftdf_short_address_t) ((saPart >> 16) & 0x0000ffff)) { - *entry = i; - *short_addr_idx = 1; - return FTDF_TRUE; - } - } - saPart = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, EXP_SA_H, 0x10, i); - if (size_and_val & 0x4) { - if (short_addr == (ftdf_short_address_t) (saPart & 0x0000ffff)) { - *entry = i; - *short_addr_idx = 2; - return FTDF_TRUE; - } - } - if (size_and_val & 0x8) { - if (short_addr == ((ftdf_short_address_t) (saPart >> 16) & 0x0000ffff)) { - *entry = i; - *short_addr_idx = 3; - return FTDF_TRUE; - } - } - } - return FTDF_FALSE; -} - -ftdf_boolean_t ftdf_fppr_lookup_ext_address(ftdf_ext_address_t ext_addr, uint8_t *entry) -{ - uint8_t i; - uint32_t size_and_val; - uint32_t ext_addr_hi, ext_addr_lo; - ext_addr_hi = (uint32_t) ((ext_addr >> 32) & 0xffffffff); - ext_addr_lo = (uint32_t) (ext_addr & 0xffffffff); - for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) { - size_and_val = *REG_GET_ADDR_INDEXED(FTDF, FTDF_SIZE_AND_VAL_0_REG, 0x10, i); - /* Check if there is a valid extended address. */ - if (size_and_val != 0x1) { - continue; - } - if ((ext_addr_lo == REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, EXP_SA_L, 0x10, i)) && - (ext_addr_hi == REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_1_0_REG, EXP_SA_H, 0x10, i))) { - *entry = i; - return FTDF_TRUE; - } - } - return FTDF_FALSE; -} - -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - -void ftdf_fppr_set_mode(ftdf_boolean_t match_fp, ftdf_boolean_t fp_override, ftdf_boolean_t fp_force) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, ADDR_TAB_MATCH_FP_VALUE, match_fp ? 1 : 0); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_OVERRIDE,fp_override ? 1 : 0); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_FORCE_VALUE, fp_force ? 1 : 0); -} - -#if FTDF_FP_BIT_TEST_MODE -void ftdf_fppr_get_mode(ftdf_boolean_t *match_fp, ftdf_boolean_t *fp_override, ftdf_boolean_t *fp_force) -{ - *match_fp = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, ADDR_TAB_MATCH_FP_VALUE) ? FTDF_TRUE : FTDF_FALSE; - *fp_override = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_OVERRIDE) ? FTDF_TRUE : FTDF_FALSE; - *fp_force = REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FP_FORCE_VALUE) ? FTDF_TRUE : FTDF_FALSE; -} -#endif // FTDF_FP_BIT_TEST_MODE - -void ftdf_lpdp_enable(ftdf_boolean_t enable) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FTDF_LPDP_ENABLE, enable ? 1 : 0); -} - -#if FTDF_FP_BIT_TEST_MODE -ftdf_boolean_t ftdf_lpdp_is_enabled(void) -{ - return REG_GETF(FTDF, FTDF_LMAC_CONTROL_3_REG, FTDF_LPDP_ENABLE) ? FTDF_TRUE : FTDF_FALSE; -} -#endif - -#if FTDF_USE_SLEEP_DURING_BACKOFF - -static inline void ftdf_sdb_save_state(void) -{ - volatile uint32_t *tx_fifo_ptr = &FTDF->FTDF_TX_FIFO_0_0_REG; - uint32_t * dstPtr = (uint32_t *) ftdf_sdb.buffer; - uint8_t word_length_rem; - - ftdf_sdb.nr_of_backoffs = REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, CSMA_CA_NB_STAT); - - /* Read first 4 bytes. */ - *dstPtr++ = *tx_fifo_ptr++; - - ASSERT_WARNING((ftdf_sdb.buffer[0] >= 3) && (ftdf_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); - /* The length is the buffer length excluding the length byte itself */ - word_length_rem = (ftdf_sdb.buffer[0] + 4) / 4 - 1; /* 1 word we already read */ - - while (word_length_rem--) { - *dstPtr++ = *tx_fifo_ptr++; - } - - ftdf_sdb.metadata_0 = FTDF->FTDF_TX_META_DATA_0_0_REG; - ftdf_sdb.metadata_1 = FTDF->FTDF_TX_META_DATA_1_0_REG; - - ftdf_sdb.phy_csma_ca_attr = FTDF->FTDF_LMAC_CONTROL_5_REG; -} - -static inline void ftdf_sdb_resume(void) -{ - volatile uint32_t *tx_fifo_ptr = &FTDF->FTDF_TX_FIFO_0_0_REG; - uint32_t * src_ptr = (uint32_t *) ftdf_sdb.buffer; - - uint8_t word_length_rem; - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_11_REG, CSMA_CA_NB_VAL, ftdf_sdb.nr_of_backoffs); - - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, CSMA_CA_RESUME_SET, 1); - - ASSERT_WARNING((ftdf_sdb.buffer[0] >= 3) && (ftdf_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); - - /* The length is the buffer length excluding the length byte itself */ - word_length_rem = (ftdf_sdb.buffer[0] + 4) / 4; - - while (word_length_rem--) { - *tx_fifo_ptr++ = *src_ptr++; - } - - REG_SET_MASKED(FTDF, FTDF_LMAC_CONTROL_5_REG, - (REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_DEM_PTI) | - REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CN) | - REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_CALCAP) | - REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_RF_GPIO_PINS) | - REG_MSK(FTDF, FTDF_LMAC_CONTROL_5_REG, PHYCSMACAATTR_HSI)), ftdf_sdb.phy_csma_ca_attr); - - FTDF->FTDF_TX_META_DATA_0_0_REG = ftdf_sdb.metadata_0; - - FTDF->FTDF_TX_META_DATA_1_0_REG = ftdf_sdb.metadata_1; - - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, - (REG_GETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET) | (1 << FTDF_TX_DATA_BUFFER))); -} - -static inline void ftdf_sdb_reset(void) -{ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, CSMA_CA_RESUME_CLEAR, 1); -} - -static inline void ftdf_sdb_set_cca_retry_time(void) -{ - ftdf_time_t timestamp = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - ftdf_time_t bo_stat = REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, CSMA_CA_BO_STAT) * - FTDF_UNIT_BACKOFF_PERIOD; - ftdf_sdb.cca_retry_time = timestamp + bo_stat; -} - -void ftdf_sdb_fsm_reset(void) { - ftdf_sdb_reset(); - ftdf_sdb.state = FTDF_SDB_STATE_INIT; -} - -void ftdf_sdb_fsm_backoff_irq(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - return; - } -#endif - switch (ftdf_sdb.state) { - case FTDF_SDB_STATE_RESUMING: - ftdf_sdb_reset(); - case FTDF_SDB_STATE_INIT: - case FTDF_SDB_STATE_BACKING_OFF: - ftdf_sdb_set_cca_retry_time(); - ftdf_sdb.state = FTDF_SDB_STATE_BACKING_OFF; - break; - default: - ASSERT_WARNING(0); - } -} - -void ftdf_sdb_fsm_sleep(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - return; - } -#endif - switch (ftdf_sdb.state) { - case FTDF_SDB_STATE_BACKING_OFF: - ftdf_sdb_save_state(); - ftdf_sdb.state = FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ; - break; - case FTDF_SDB_STATE_INIT: - break; - default: - ASSERT_WARNING(0); - } -} - -void ftdf_sdb_fsm_abort_sleep(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - return; - } -#endif - switch (ftdf_sdb.state) { - case FTDF_SDB_STATE_BACKING_OFF: - ftdf_sdb.state = FTDF_SDB_STATE_INIT; - break; - case FTDF_SDB_STATE_INIT: - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - case FTDF_SDB_STATE_RESUMING: - break; - default: - ASSERT_WARNING(0); - } -} - -void ftdf_sdb_fsm_wake_up_irq(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - return; - } -#endif - switch (ftdf_sdb.state) { - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - ftdf_sdb.state = FTDF_SDB_STATE_RESUMING; - break; - case FTDF_SDB_STATE_INIT: - break; - default: - ASSERT_WARNING(0); - } -} - -void ftdf_sdb_fsm_wake_up(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - return; - } -#endif - switch (ftdf_sdb.state) { - case FTDF_SDB_STATE_RESUMING: - ftdf_sdb_resume(); - break; - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - break; - case FTDF_SDB_STATE_INIT: - break; - default: - ASSERT_WARNING(0); - } -} - -void ftdf_sdb_fsm_tx_irq(void) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - return; - } -#endif - switch (ftdf_sdb.state) { - case FTDF_SDB_STATE_RESUMING: - ftdf_sdb_reset(); - ftdf_sdb.state = FTDF_SDB_STATE_INIT; - break; - case FTDF_SDB_STATE_BACKING_OFF: - ftdf_sdb.state = FTDF_SDB_STATE_INIT; - break; - case FTDF_SDB_STATE_INIT: - break; - default: - ASSERT_WARNING(0); - } -} - -ftdf_usec_t ftdf_sdb_get_sleep_time(void) -{ - ftdf_usec_t sleep_time = ~((ftdf_usec_t) 0); -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - return sleep_time; - } -#endif - switch (ftdf_sdb.state) { - case FTDF_SDB_STATE_INIT: - if ((REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) || ftdf_req_current) { - sleep_time = 0; - } else { - sleep_time = ~((ftdf_usec_t) 0); - } - break; - case FTDF_SDB_STATE_BACKING_OFF: - { - ftdf_time_t currentTime = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - if (currentTime <= ftdf_sdb.cca_retry_time) { - sleep_time = (ftdf_sdb.cca_retry_time - currentTime) * 16; - } else { - sleep_time = (1 << 31) - (currentTime + ftdf_sdb.cca_retry_time) * 16; - } - if (sleep_time > 256 * FTDF_UNIT_BACKOFF_PERIOD * 16) { - /* We have exceeded the CCA retry time. Abort sleep and wait for Tx IRQ. */ - sleep_time = 0; - } - break; - } - case FTDF_SDB_STATE_RESUMING: - sleep_time = 0; - break; - case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: - sleep_time = ~((ftdf_usec_t) 0); - break; - default: - ASSERT_WARNING(0); - } - return sleep_time; -} - -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - -#if dg_configUSE_FTDF_DDPHY == 1 -void ftdf_ddphy_set(uint16_t cca_reg) -{ - ftdf_critical_var(); - ftdf_enter_critical(); - /* We use the critical section here as protection for the global variable and the HW sleep - * state. */ - ftdf_ddphy_cca_reg = cca_reg; - /* Apply immediately if block is up. */ - if (REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0) { - FTDF_DPHY->DDPHY_CCA_REG = ftdf_ddphy_cca_reg; - } - ftdf_exit_critical(); -} - -void ftdf_ddphy_restore(void) -{ - if (ftdf_ddphy_cca_reg) { - /* Apply immediately if block is up. */ - ftdf_critical_var(); - ftdf_enter_critical(); - ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); - FTDF_DPHY->DDPHY_CCA_REG = ftdf_ddphy_cca_reg; - ftdf_exit_critical(); - } -} - -void ftdf_ddphy_save(void) -{ - /* Apply immediately if block is up. */ - ftdf_critical_var(); - ftdf_enter_critical(); - ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); - ftdf_ddphy_cca_reg = FTDF_DPHY->DDPHY_CCA_REG; - ftdf_exit_critical(); -} -#endif -#endif /* CONFIG_USE_FTDF */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c deleted file mode 100644 index f9444241d..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c +++ /dev/null @@ -1,621 +0,0 @@ -/** - **************************************************************************************** - * - * @file data.c - * - * @brief FTDF data send/receive functions - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#include - -#include -#include "internal.h" - -#ifdef CONFIG_USE_FTDF -#ifndef FTDF_LITE -void ftdf_process_data_request(ftdf_data_request_t *data_request) -{ -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled && ftdf_tsch_slot_link->request != data_request) { - ftdf_status_t status; - - if ((data_request->dst_addr_mode == FTDF_SHORT_ADDRESS) && !data_request->indirect_tx) { - status = ftdf_schedule_tsch((ftdf_msg_buffer_t*) data_request); - - if (status == FTDF_SUCCESS) { - return; - } - - } else { - status = FTDF_INVALID_PARAMETER; - } - - ftdf_send_data_confirm(data_request, status, 0, 0, 0, NULL); - - return; - } -#endif /* FTDF_NO_TSCH */ - - int queue; - ftdf_address_mode_t dst_addr_mode = data_request->dst_addr_mode; - ftdf_pan_id_t dst_pan_id = data_request->dst_pan_id; - ftdf_address_t dst_addr = data_request->dst_addr; - - /* Search for an existing indirect queue */ - for (queue = 0; queue < FTDF_NR_OF_REQ_BUFFERS; queue++) { - - if (dst_addr_mode == FTDF_SHORT_ADDRESS) { - - if ((ftdf_tx_pending_list[queue].addr_mode == dst_addr_mode) && - (ftdf_tx_pending_list[queue].addr.short_address == dst_addr.short_address)) { - break; - } - - } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { - - if ((ftdf_tx_pending_list[queue].addr_mode == dst_addr_mode) && - (ftdf_tx_pending_list[queue].addr.ext_address == dst_addr.ext_address)) { - break; - } - } - } - - if (data_request->indirect_tx) { - ftdf_status_t status = FTDF_SUCCESS; - - if (queue < FTDF_NR_OF_REQ_BUFFERS) { - /* Queue request in existing queue */ - status = ftdf_queue_req_head((ftdf_msg_buffer_t*) data_request, - &ftdf_tx_pending_list[queue].queue); - - if (status == FTDF_SUCCESS) { - ftdf_add_tx_pending_timer((ftdf_msg_buffer_t*) data_request, queue, - (ftdf_pib.transaction_persistence_time * - FTDF_BASE_SUPERFRAME_DURATION), - ftdf_send_transaction_expired); - return; - } - } - - if ((dst_addr_mode != FTDF_EXTENDED_ADDRESS) && (dst_addr_mode != FTDF_SHORT_ADDRESS)) { - status = FTDF_INVALID_PARAMETER; - } - - if (status != FTDF_SUCCESS) { - /* Queueing of indirect transfer was not successful */ - ftdf_send_data_confirm(data_request, status, 0, 0, 0, NULL); - - return; - } -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - uint8_t entry, short_addr_idx; - if (dst_addr_mode == FTDF_SHORT_ADDRESS) { - if (ftdf_fppr_get_free_short_address(&entry, &short_addr_idx) == FTDF_FALSE) { - goto transaction_overflow; - } - } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { - if (ftdf_fppr_get_free_ext_address(&entry) == FTDF_FALSE) { - goto transaction_overflow; - } - } else { - status = FTDF_INVALID_PARAMETER; - } -#endif - /* Search for an empty indirect queue */ - for (queue = 0; queue < FTDF_NR_OF_REQ_BUFFERS; queue++) { - if (ftdf_tx_pending_list[queue].addr_mode == FTDF_NO_ADDRESS) { - ftdf_tx_pending_list[queue].addr_mode = dst_addr_mode; - ftdf_tx_pending_list[queue].pan_id = dst_pan_id; - ftdf_tx_pending_list[queue].addr = dst_addr; - - status = ftdf_queue_req_head((ftdf_msg_buffer_t*) data_request, - &ftdf_tx_pending_list[queue].queue); - - if (status == FTDF_SUCCESS) { -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - if (dst_addr_mode == FTDF_SHORT_ADDRESS) { - ftdf_fppr_set_short_address(entry, short_addr_idx, dst_addr.short_address); - ftdf_fppr_set_short_address_valid(entry, short_addr_idx, FTDF_TRUE); - } else if (dst_addr_mode == FTDF_EXTENDED_ADDRESS) { - ftdf_fppr_set_ext_address(entry, dst_addr.short_address); - ftdf_fppr_set_ext_address_valid(entry, FTDF_TRUE); - } else { - ASSERT_WARNING(0); - } -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - ftdf_add_tx_pending_timer((ftdf_msg_buffer_t*) data_request, - queue, - (ftdf_pib.transaction_persistence_time * - FTDF_BASE_SUPERFRAME_DURATION), - ftdf_send_transaction_expired); - - return; - } else { - break; - } - } - } - - /* Did not find an existing or an empty queue */ -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - transaction_overflow: -#endif - ftdf_send_data_confirm(data_request, FTDF_TRANSACTION_OVERFLOW, 0, 0, 0, NULL); - - return; - } - - if (ftdf_req_current == NULL) { - ftdf_req_current = (ftdf_msg_buffer_t*) data_request; - } else { - if (ftdf_queue_req_head((ftdf_msg_buffer_t*) data_request, &ftdf_req_queue) == - FTDF_TRANSACTION_OVERFLOW) { - - ftdf_send_data_confirm(data_request, FTDF_TRANSACTION_OVERFLOW, 0, 0, 0, NULL); - } - - return; - } - - ftdf_frame_header_t *frame_header = &ftdf_fh; - ftdf_security_header *security_header = &ftdf_sh; - - frame_header->frame_type = data_request->send_multi_purpose ? FTDF_MULTIPURPOSE_FRAME : FTDF_DATA_FRAME; - - ftdf_boolean_t frame_pending; - - if (queue < FTDF_NR_OF_REQ_BUFFERS) { - frame_pending = FTDF_TRUE; - } else { - frame_pending = FTDF_FALSE; - } - - frame_header->options = - (data_request->security_level > 0 ? FTDF_OPT_SECURITY_ENABLED : 0) | - (data_request->ack_tx ? FTDF_OPT_ACK_REQUESTED : 0) | - (frame_pending ? FTDF_OPT_FRAME_PENDING : 0) | - ((data_request->frame_control_options & FTDF_PAN_ID_PRESENT) ? FTDF_OPT_PAN_ID_PRESENT : 0) | - ((data_request->frame_control_options & FTDF_IES_INCLUDED) ? FTDF_OPT_IES_PRESENT : 0) | - ((data_request->frame_control_options & FTDF_SEQ_NR_SUPPRESSED) ? FTDF_OPT_SEQ_NR_SUPPRESSED : 0); - - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - frame_header->options |= FTDF_OPT_ENHANCED; - } - - frame_header->src_addr_mode = data_request->src_addr_mode; - frame_header->src_pan_id = ftdf_pib.pan_id; - frame_header->dst_addr_mode = data_request->dst_addr_mode; - frame_header->dst_pan_id = data_request->dst_pan_id; - frame_header->dst_addr = data_request->dst_addr; - - security_header->security_level = data_request->security_level; - security_header->key_id_mode = data_request->key_id_mode; - security_header->key_index = data_request->key_index; - security_header->key_source = data_request->key_source; - security_header->frame_counter = ftdf_pib.frame_counter; - security_header->frame_counter_mode = ftdf_pib.frame_counter_mode; - -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { - frame_header->sn = ftdf_process_tsch_sn((ftdf_msg_buffer_t*)data_request, - ftdf_pib.dsn, - &data_request->requestSN); - } else -#endif /* FTDF_NO_TSCH */ - { - frame_header->sn = ftdf_pib.dsn; - } - - ftdf_octet_t *tx_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + - (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - - /* Skip PHY header (= MAC length) */ - tx_ptr++; - - ftdf_data_length_t msdu_length = data_request->msdu_length; - - tx_ptr = ftdf_add_frame_header(tx_ptr, frame_header, msdu_length); - - tx_ptr = ftdf_add_security_header(tx_ptr, security_header); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (data_request->frame_control_options & FTDF_IES_INCLUDED) { - tx_ptr = ftdf_add_ies(tx_ptr, - data_request->header_ie_list, - data_request->payload_ie_list, - data_request->msdu_length); - } -#endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - - ftdf_status_t status = ftdf_send_frame(ftdf_pib.current_channel, - frame_header, - security_header, - tx_ptr, - data_request->msdu_length, - data_request->msdu); - - if (status != FTDF_SUCCESS) { - ftdf_send_data_confirm(data_request, status, 0, 0, 0, NULL); - ftdf_req_current = NULL; - - return; - } - - ftdf_nr_of_retries = 0; - - if (frame_header->sn == ftdf_pib.dsn) { - ftdf_pib.dsn++; - } -} - -void ftdf_send_data_confirm(ftdf_data_request_t *data_request, - ftdf_status_t status, - ftdf_time_t timestamp, - ftdf_sn_t dsn, - ftdf_num_of_backoffs_t num_of_backoffs, - ftdf_ie_list_t *ack_payload) -{ - FTDF_REL_DATA_BUFFER(data_request->msdu); - - ftdf_data_confirm_t *data_confirm = - (ftdf_data_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_data_confirm_t)); - - data_confirm->msg_id = FTDF_DATA_CONFIRM; - data_confirm->msdu_handle = data_request->msdu_handle; - data_confirm->status = status; - data_confirm->timestamp = timestamp; - data_confirm->num_of_backoffs = num_of_backoffs; - data_confirm->dsn = dsn; - data_confirm->ack_payload = ack_payload; - - if (ftdf_req_current == (ftdf_msg_buffer_t*)data_request) { - ftdf_req_current = NULL; - } - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) data_request); - FTDF_RCV_MSG((ftdf_msg_buffer_t*) data_confirm); -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - ftdf_fp_fsm_clear_pending(); -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - ftdf_process_next_request(); -} - -void ftdf_send_data_indication(ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header, - ftdf_ie_list_t *payload_ie_list, - ftdf_data_length_t msdu_length, - ftdf_octet_t *msdu, - ftdf_link_quality_t mpdu_link_quality, - ftdf_time_t timestamp) -{ - ftdf_data_indication_t *data_indication = - (ftdf_data_indication_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_data_indication_t)); - - ftdf_octet_t *msdu_buf = FTDF_GET_DATA_BUFFER(msdu_length); - ftdf_octet_t *buf_ptr = msdu_buf; - - int n; - - for (n = 0; n < msdu_length; n++) { - *msdu_buf++ = *msdu++; - } - - data_indication->msg_id = FTDF_DATA_INDICATION; - data_indication->src_addr_mode = frame_header->src_addr_mode; - data_indication->src_pan_id = frame_header->src_pan_id; - data_indication->src_addr = frame_header->src_addr; - data_indication->dst_addr_mode = frame_header->dst_addr_mode; - data_indication->dst_pan_id = frame_header->dst_pan_id; - data_indication->dst_addr = frame_header->dst_addr; - data_indication->msdu_length = msdu_length; - data_indication->msdu = buf_ptr; - data_indication->mpdu_link_quality = mpdu_link_quality; - data_indication->dsn = frame_header->sn; - data_indication->timestamp = timestamp; - data_indication->security_level = security_header->security_level; - data_indication->key_id_mode = security_header->key_id_mode; - data_indication->key_index = security_header->key_index; - data_indication->payload_ie_list = payload_ie_list; - - if (data_indication->key_id_mode == 0x2) { - for (n = 0; n < 4; n++) { - data_indication->key_source[n] = security_header->key_source[n]; - } - } else if (data_indication->key_id_mode == 0x3) { - for (n = 0; n < 8; n++) { - data_indication->key_source[n] = security_header->key_source[n]; - } - } - - FTDF_RCV_MSG((ftdf_msg_buffer_t*) data_indication); -} - -void ftdf_process_poll_request(ftdf_poll_request_t *poll_request) -{ - if (ftdf_req_current == NULL) { - ftdf_req_current = (ftdf_msg_buffer_t*) poll_request; - } else { - if (ftdf_queue_req_head((ftdf_msg_buffer_t*) poll_request, &ftdf_req_queue) == - FTDF_TRANSACTION_OVERFLOW) { - ftdf_send_poll_confirm(poll_request, FTDF_TRANSACTION_OVERFLOW); - } - - return; - } - - ftdf_frame_header_t *frame_header = &ftdf_fh; - ftdf_security_header *security_header = &ftdf_sh; - - frame_header->frame_type = FTDF_MAC_COMMAND_FRAME; - frame_header->options = - (poll_request->security_level > 0 ? FTDF_OPT_SECURITY_ENABLED : 0) | FTDF_OPT_ACK_REQUESTED; - - if (ftdf_pib.short_address < 0xfffe) { - frame_header->src_addr_mode = FTDF_SHORT_ADDRESS; - frame_header->src_addr.short_address = ftdf_pib.short_address; - } else { - frame_header->src_addr_mode = FTDF_EXTENDED_ADDRESS; - frame_header->src_addr.ext_address = ftdf_pib.ext_address; - } - - frame_header->src_pan_id = ftdf_pib.pan_id; - frame_header->dst_addr_mode = poll_request->coord_addr_mode; - frame_header->dst_pan_id = poll_request->coord_pan_id; - frame_header->dst_addr = poll_request->coord_addr; - - security_header->security_level = poll_request->security_level; - security_header->key_id_mode = poll_request->key_id_mode; - security_header->key_index = poll_request->key_index; - security_header->key_source = poll_request->key_source; - security_header->frame_counter = ftdf_pib.frame_counter; - security_header->frame_counter_mode = ftdf_pib.frame_counter_mode; - - ftdf_octet_t *tx_ptr = (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - - /* Skip PHY header (= MAC length) */ - tx_ptr++; - - frame_header->sn = ftdf_pib.dsn; - - tx_ptr = ftdf_add_frame_header(tx_ptr, frame_header, 1); - - tx_ptr = ftdf_add_security_header(tx_ptr, security_header); - - *tx_ptr++ = FTDF_COMMAND_DATA_REQUEST; - - ftdf_status_t status = ftdf_send_frame(ftdf_pib.current_channel, - frame_header, - security_header, - tx_ptr, - 0, - NULL); - - if (status != FTDF_SUCCESS) { - ftdf_send_poll_confirm(poll_request, status); - return; - } - - ftdf_nr_of_retries = 0; - ftdf_pib.dsn++; -} - -void ftdf_send_poll_confirm(ftdf_poll_request_t *poll_request, ftdf_status_t status) -{ - ftdf_poll_confirm_t *poll_confirm = (ftdf_poll_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_poll_confirm_t)); - - poll_confirm->msg_id = FTDF_POLL_CONFIRM; - poll_confirm->status = status; - - if (ftdf_req_current == (ftdf_msg_buffer_t*)poll_request) { - ftdf_req_current = NULL; - } - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) poll_request); - FTDF_RCV_MSG((ftdf_msg_buffer_t*) poll_confirm); - - ftdf_process_next_request(); -} - -void ftdf_process_purge_request(ftdf_purge_request_t *purge_request) -{ - ftdf_handle_t msdu_handle = purge_request->msdu_handle; - ftdf_status_t status = FTDF_INVALID_HANDLE; - - int n; - - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { - ftdf_msg_buffer_t *request = - ftdf_dequeue_by_handle(msdu_handle, &ftdf_tx_pending_list[n].queue); - - if (request) { - ftdf_data_request_t *data_request = (ftdf_data_request_t*) request; - - if (data_request->indirect_tx == FTDF_TRUE) { - ftdf_remove_tx_pending_timer(request); -#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO - if (ftdf_tx_pending_list[n].addr_mode == FTDF_SHORT_ADDRESS) { - uint8_t entry, shortAddrIdx; - ftdf_boolean_t found = ftdf_fppr_lookup_short_address( - ftdf_tx_pending_list[n].addr.short_address, &entry, - &shortAddrIdx); - ASSERT_WARNING(found); - ftdf_fppr_set_short_address_valid(entry, shortAddrIdx, FTDF_FALSE); - } else if (ftdf_tx_pending_list[n].addr_mode == FTDF_EXTENDED_ADDRESS) { - uint8_t entry; - ftdf_boolean_t found = ftdf_fppr_lookup_ext_address( - ftdf_tx_pending_list[n].addr.ext_address, &entry); - ASSERT_WARNING(found); - ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE); - } else { - ASSERT_WARNING(0); - } -#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ - if (ftdf_is_queue_empty(&ftdf_tx_pending_list[n].queue)) { - ftdf_tx_pending_list[n].addr_mode = FTDF_NO_ADDRESS; - } - } - - FTDF_REL_DATA_BUFFER(data_request->msdu); - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) data_request); - - status = FTDF_SUCCESS; - - break; - } - } - - ftdf_purge_confirm_t *purge_confirm = - (ftdf_purge_confirm_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_purge_confirm_t)); - - purge_confirm->msg_id = FTDF_PURGE_CONFIRM; - purge_confirm->msdu_handle = msdu_handle; - purge_confirm->status = status; - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) purge_request); - FTDF_RCV_MSG((ftdf_msg_buffer_t*) purge_confirm); -} -#endif /* !FTDF_LITE */ - -#ifdef FTDF_PHY_API -ftdf_status_t ftdf_send_frame_simple(ftdf_data_length_t frame_length, - ftdf_octet_t *frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t csma_suppress) -{ - - ftdf_octet_t *fp = frame; - - if ((frame_length > 127) || (ftdf_transparent_mode != FTDF_TRUE)) { - return FTDF_INVALID_PARAMETER; - } - - ftdf_octet_t *tx_ptr = - (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - - /* This data copy could/should be optimized using DMA */ - *tx_ptr++ = frame_length; - - int n; - - for (n = 0; n < frame_length; n++) { - *tx_ptr++ = *fp++; - } - - ftdf_critical_var(); - ftdf_enter_critical(); - ftdf_nr_of_retries = 0; - ftdf_exit_critical(); - ftdf_send_transparent_frame(frame_length, - frame, - channel, - pti, - csma_suppress); - - return FTDF_SUCCESS; -} - - - -#else /* !FTDF_PHY_API */ -void ftdf_process_transparent_request(ftdf_transparent_request_t *transparent_request) -{ - ftdf_data_length_t frame_length = transparent_request->frame_length; - - if ((frame_length > 127) || (ftdf_transparent_mode != FTDF_TRUE)) { - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, - FTDF_INVALID_PARAMETER); - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) transparent_request); - - return; - } - - if (ftdf_req_current == NULL) { - ftdf_req_current = (ftdf_msg_buffer_t*) transparent_request; - } else { -#ifndef FTDF_LITE - if (ftdf_queue_req_head((ftdf_msg_buffer_t*) transparent_request, &ftdf_req_queue) == - FTDF_TRANSACTION_OVERFLOW) { -#endif /* !FTDF_LITE */ - FTDF_SEND_FRAME_TRANSPARENT_CONFIRM(transparent_request->handle, - FTDF_TRANSPARENT_OVERFLOW); - - FTDF_REL_MSG_BUFFER((ftdf_msg_buffer_t*) transparent_request); -#ifndef FTDF_LITE - } -#endif /* !FTDF_LITE */ - return; - } - - ftdf_octet_t *tx_ptr = - (ftdf_octet_t*) &FTDF->FTDF_TX_FIFO_0_0_REG + (FTDF_BUFFER_LENGTH * FTDF_TX_DATA_BUFFER); - - *tx_ptr++ = frame_length; - - ftdf_octet_t *frame = transparent_request->frame; - - int n; - - for (n = 0; n < frame_length; n++) { - *tx_ptr++ = *frame++; - } - - ftdf_send_transparent_frame(frame_length, - transparent_request->frame, - transparent_request->channel, - transparent_request->pti, - transparent_request->cmsa_suppress); - ftdf_nr_of_retries = 0; -} - -void ftdf_send_frame_transparent(ftdf_data_length_t frame_length, - ftdf_octet_t *frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t cmsa_suppress, - void *handle) -{ - ftdf_transparent_request_t *transparent_request = - (ftdf_transparent_request_t*) FTDF_GET_MSG_BUFFER(sizeof(ftdf_transparent_request_t)); - - transparent_request->msg_id = FTDF_TRANSPARENT_REQUEST; - transparent_request->frame_length = frame_length; - transparent_request->frame = frame; - transparent_request->channel = channel; - transparent_request->pti = pti; - transparent_request->cmsa_suppress = cmsa_suppress; - transparent_request->handle = handle; - - ftdf_process_transparent_request(transparent_request); -} - -#endif /* FTDF_PHY_API */ -#endif /* CONFIG_USE_FTDF */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h deleted file mode 100755 index cc4831aa4..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef FTDFINFO_H_ -#define FTDFINFO_H_ - -/* - * The FTDF release name (version) is listed below, and manually maintained. - * The build time is automatically generated. - */ -#define FTDF_ARCHITECTURE_VERSION 1 -#define FTDF_BRANCH_VERSION 0 -#define FTDF_LOAD_VERSION 32 - -const char *ftdf_get_umac_rel_name( void ); -const char *ftdf_get_umac_build_time( void ); - -#endif /* FTDFINFO_H_ */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h deleted file mode 100644 index 028637857..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h +++ /dev/null @@ -1,723 +0,0 @@ -/** - **************************************************************************************** - * - * @file internal.h - * - * @brief Internal header file - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#define FTDF_TBD 0 - -#define FTDF_FCS_LENGTH 2 -#define FTDF_BUFFER_LENGTH 128 -#ifndef FTDF_NR_OF_REQ_BUFFERS -#define FTDF_NR_OF_REQ_BUFFERS 96 -#endif -#define FTDF_NR_OF_RX_BUFFERS 8 -#define FTDF_NR_OF_CHANNELS 16 -#define FTDF_NR_OF_SCAN_RESULTS 16 -#define FTDF_NR_OF_CSL_PEERS 16 -#define FTDF_MAX_HEADER_IES 8 -#define FTDF_MAX_PAYLOAD_IES 4 -#define FTDF_MAX_SUB_IES 8 -#define FTDF_MAX_IE_CONTENT 128 -#define FTDF_NR_OF_RX_ADDRS 16 -#define FTDF_NR_OF_NEIGHBORS 16 - -#define FTDF_TX_DATA_BUFFER 0 -#define FTDF_TX_WAKEUP_BUFFER 1 -#define FTDF_TX_ACK_BUFFER 2 - -#define FTDF_OPT_SECURITY_ENABLED 0x01 -#define FTDF_OPT_FRAME_PENDING 0x02 -#define FTDF_OPT_SEQ_NR_SUPPRESSED 0x04 -#define FTDF_OPT_ACK_REQUESTED 0x08 -#define FTDF_OPT_IES_PRESENT 0x10 -#define FTDF_OPT_PAN_ID_PRESENT 0x20 -#define FTDF_OPT_ENHANCED 0x40 - -#define FTDF_MSK_RX_CE 0x00000002 -#define FTDF_MSK_SYMBOL_TMR_CE 0x00000008 -#define FTDF_MSK_TX_CE 0x00000010 - -#define FTDF_TX_FLAG_CLEAR_M_0_REG_INTV 0x20 -#define FTDF_TX_FLAG_CLEAR_E_0_REG_INTV 0x20 -#define FTDF_TX_PRIORITY_0_REG_INTV 0x20 -#define FTDF_RX_META_1_0_REG_INTV 0x10 -#define FTDF_TX_FLAG_S_0_REG_INTV 0x20 -#define FTDF_TX_RETURN_STATUS_1_0_REG_INTV 0x10 -#define FTDF_TX_META_DATA_0_0_REG_INTV 0x10 -#define FTDF_TX_RETURN_STATUS_1_0_REG_INTV 0x10 -#define FTDF_TX_META_DATA_1_0_REG_INTV 0x10 - -// The maximum time in symbols that is takes to process request. After succesful -// processing a request the TX buffer is fully initialized and ready to be sent. -#define FTDF_TSCH_MAX_PROCESS_REQUEST_TIME 35 - -// The maximum time in symbols needed to search for the next slot for which a -// TX or RX needs to be done -#define FTDF_TSCH_MAX_SCHEDULE_TIME 30 - -#define ftdf_process_request ftdf_snd_msg - -typedef struct { - ftdf_ext_address_t ext_address; - ftdf_period_t ack_wait_duration; -#ifndef FTDF_LITE - ftdf_boolean_t associated_pan_coord; - ftdf_boolean_t association_permit; - ftdf_boolean_t auto_request; - ftdf_boolean_t batt_life_ext; - ftdf_num_of_backoffs_t batt_life_ext_periods; - ftdf_octet_t beacon_payload[FTDF_MAX_BEACON_PAYLOAD_LENGTH]; - ftdf_size_t beacon_payload_length; - ftdf_order_t beacon_order; - ftdf_time_t beacon_tx_time; - ftdf_sn_t bsn; - ftdf_ext_address_t coord_ext_address; - ftdf_short_address_t coord_short_address; - ftdf_sn_t dsn; - ftdf_boolean_t gts_permit; -#endif /* !FTDF_LITE */ - ftdf_be_exponent_t max_be; - ftdf_size_t max_csma_backoffs; - ftdf_period_t max_frame_total_wait_time; - ftdf_size_t max_frame_retries; - ftdf_be_exponent_t min_be; -#ifndef FTDF_LITE - ftdf_period_t lifs_period; - ftdf_period_t sifs_period; -#endif /* !FTDF_LITE */ - ftdf_pan_id_t pan_id; -#ifndef FTDF_LITE - ftdf_boolean_t promiscuous_mode; /* Not supported. Use transparent mode instead */ - ftdf_size_t response_wait_time; -#endif /* !FTDF_LITE */ - ftdf_boolean_t rx_on_when_idle; -#ifndef FTDF_LITE - ftdf_boolean_t security_enabled; -#endif /* !FTDF_LITE */ - ftdf_short_address_t short_address; -#ifndef FTDF_LITE - ftdf_size_t superframe_order; - ftdf_period_t sync_symbol_offset; - ftdf_boolean_t timestamp_supported; - ftdf_period_t transaction_persistence_time; - ftdf_period_t enh_ack_wait_duration; - ftdf_boolean_t implicit_broadcast; - ftdf_simple_address_t simple_address; - ftdf_period_t disconnect_time; - ftdf_priority_t join_priority; - ftdf_asn_t asn; - ftdf_boolean_t no_hl_buffers; - ftdf_slotframe_table_t slotframe_table; - FTDF_LinkTable link_table; - ftdf_timeslot_template_t timeslot_template; - ftdf_hopping_sequence_id_t hopping_sequence_id; - ftdf_channel_page_t channel_page; - ftdf_channel_number_t number_of_channels; - ftdf_bitmap32_t phy_configuration; - ftdf_bitmap8_t extended_bitmap; - ftdf_length_t hopping_sequence_length; - ftdf_channel_number_t hopping_sequence_list[FTDF_MAX_HOPPING_SEQUENCE_LENGTH]; - ftdf_length_t current_hop; - ftdf_period_t dwell_time; - ftdf_period_t csl_period; - ftdf_period_t csl_max_period; - ftdf_bitmap32_t csl_channel_mask; - ftdf_period_t csl_frame_pending_wait; - ftdf_boolean_t low_energy_superframe_supported; - ftdf_boolean_t low_energy_superframe_sync_interval; -#endif /* !FTDF_LITE */ - ftdf_performance_metrics_t performance_metrics; -#ifndef FTDF_LITE - ftdf_boolean_t use_enhanced_becaon; - ftdf_ie_list_t eb_ie_list; - ftdf_boolean_t eb_filtering_enabled; - ftdf_sn_t eb_sn; - ftdf_auto_sa_t eb_auto_sa; - ftdf_ie_list_t e_ack_ie_list; - ftdf_boolean_t tsch_enabled; - ftdf_boolean_t le_enabled; -#endif /* !FTDF_LITE */ - ftdf_channel_number_t current_channel; - ftdf_tx_power_tolerance_t tx_power_tolerance; - ftdf_dbm tx_power; - ftdf_cca_mode_t cca_mode; -#ifndef FTDF_LITE - ftdf_channel_page_t current_page; - ftdf_period_t max_frame_duration; - ftdf_period_t shr_duration; - ftdf_key_table_t key_table; - ftdf_device_table_t device_table; - ftdf_security_level_table_t security_level_table; - ftdf_frame_counter_t frame_counter; - ftdf_security_level_t mt_data_security_level; - ftdf_key_id_mode_t mt_data_key_id_mode; - ftdf_octet_t mt_data_key_source[8]; - ftdf_key_index_t mt_data_key_index; - ftdf_octet_t default_key_source[8]; - ftdf_ext_address_t pan_coord_ext_address; - ftdf_short_address_t pan_coord_short_address; - ftdf_frame_counter_mode_t frame_counter_mode; - ftdf_period_t csl_sync_tx_margin; - ftdf_period_t csl_max_age_remote_info; -#endif /* !FTDF_LITE */ - ftdf_traffic_counters_t traffic_counters; -#ifndef FTDF_LITE - ftdf_boolean_t le_capable; - ftdf_boolean_t ll_capable; - ftdf_boolean_t dsme_capable; - ftdf_boolean_t rfid_capable; - ftdf_boolean_t amca_capable; -#endif /* !FTDF_LITE */ - ftdf_boolean_t metrics_capable; -#ifndef FTDF_LITE - ftdf_boolean_t ranging_supported; -#endif /* !FTDF_LITE */ - ftdf_boolean_t keep_phy_enabled; - ftdf_boolean_t metrics_enabled; -#ifndef FTDF_LITE - ftdf_boolean_t beacon_auto_respond; - ftdf_boolean_t tsch_capable; - ftdf_period_t ts_sync_correct_threshold; -#endif /* !FTDF_LITE */ - ftdf_nr_backoff_periods_t bo_irq_threshold; - ftdf_pti_config_t pti_config; - ftdf_link_quality_mode_t link_quality_mode; -} ftdf_pib_t; - -typedef uint8_t ftdf_frame_version_t; -#define FTDF_FRAME_VERSION_2003 0 -#define FTDF_FRAME_VERSION_2011 1 -#define FTDF_FRAME_VERSION_E 2 -#define FTDF_FRAME_VERSION_NOT_SUPPORTED 3 - -typedef struct { - ftdf_frame_type_t frame_type; - ftdf_frame_version_t frame_version; - ftdf_bitmap8_t options; - ftdf_sn_t sn; - ftdf_address_mode_t src_addr_mode; - ftdf_pan_id_t src_pan_id; - ftdf_address_t src_addr; - ftdf_address_mode_t dst_addr_mode; - ftdf_pan_id_t dst_pan_id; - ftdf_address_t dst_addr; - ftdf_command_frame_id_t command_frame_id; -} ftdf_frame_header_t; - -typedef struct { - ftdf_security_level_t security_level; - ftdf_key_id_mode_t key_id_mode; - ftdf_key_index_t key_index; - ftdf_frame_counter_mode_t frame_counter_mode; - ftdf_octet_t *key_source; - ftdf_frame_counter_t frame_counter; -} ftdf_security_header; - -typedef struct { - ftdf_boolean_t fast_a; - ftdf_boolean_t data_r; -} ftdf_assoc_admin_t; - -typedef uint8_t ftdf_sn_sel; -#define FTDF_SN_SEL_DSN 0 -#define FTDF_SN_SEL_BSN 1 -#define FTDF_SN_SEL_EBSN 2 - -typedef struct { - ftdf_address_mode_t addr_mode; - ftdf_address_t addr; - ftdf_time_t timestamp; - ftdf_boolean_t dsn_valid; - ftdf_sn_t dsn; - ftdf_boolean_t bsn_valid; - ftdf_sn_t bsn; - ftdf_boolean_t ebsn_valid; - ftdf_sn_t eb_sn; -} ftdf_rx_address_admin_t; - -struct ftdf_buffer_; - -typedef struct { - struct ftdf_buffer_ *next; - struct ftdf_buffer_ *prev; -} ftdf_buffer_header_t; - -typedef struct ftdf_buffer_ { - ftdf_buffer_header_t header; - ftdf_msg_buffer_t *request; -} ftdf_buffer_t; - -typedef struct { - ftdf_buffer_header_t head; - ftdf_buffer_header_t tail; -} ftdf_queue_t; - -typedef struct { - ftdf_address_t addr; - ftdf_address_mode_t addr_mode; - ftdf_pan_id_t pan_id; - ftdf_queue_t queue; -} ftdf_pending_t; - -typedef struct _ftdf_pending_tl_ { - struct _ftdf_pending_tl_ *next; - ftdf_boolean_t free; - ftdf_msg_buffer_t *request; - ftdf_time_t delta; - uint8_t pend_list_nr; - void (* func)(struct _ftdf_pending_tl_*); -} ftdf_pending_tl_t; - -typedef uint8_t ftdf_remote_id; -#define FTDF_REMOTE_DATA_REQUEST 0 -#define FTDF_REMOTE_PAN_ID_CONFLICT_NOTIFICATION 1 -#define FTDF_REMOTE_BEACON 2 -#define FTDF_REMOTE_KEEP_ALIVE 3 - -typedef struct { - ftdf_msg_id_t msg_id; - ftdf_remote_id remote_id; - ftdf_short_address_t dst_addr; -} ftdf_remote_request_t; - -#ifndef FTDF_NO_CSL -typedef struct { - ftdf_short_address_t addr; - ftdf_time_t time; - ftdf_period_t period; -} ftdf_peer_csl_timing_t; -#endif /* FTDF_NO_CSL */ - -typedef uint8_t FTDF_State; -#define FTDF_STATE_UNINITIALIZED 0 -#define FTDF_STATE_IDLE 1 -#define FTDF_STATE_DATA_REQUEST 2 -#define FTDF_STATE_POLL_REQUEST 3 -#define FTDF_STATE_SCANNING 4 - -#ifndef FTDF_NO_TSCH -typedef struct { - ftdf_short_address_t nodeAddr; - ftdf_size_t nr_of_retries; - ftdf_size_t nr_of_cca_retries; - ftdf_be_exponent_t BE; -} ftdf_tsch_retry_t; - -typedef struct { - ftdf_short_address_t dst_addr; - ftdf_keep_alive_period_t period; - ftdf_remote_request_t msg; -} FTDF_NeighborEntry; -#endif /* FTDF_NO_TSCH */ - -typedef struct { - ftdf_count_t fcs_error_cnt; - ftdf_count_t tx_std_ack_cnt; - ftdf_count_t rx_std_ack_cnt; -} ftdf_lmac_counters_t; - -extern ftdf_pib_t ftdf_pib; -extern FTDF_State *FTDF_state; -extern ftdf_boolean_t ftdf_transparent_mode; -extern ftdf_bitmap32_t ftdf_transparent_mode_options; -extern ftdf_queue_t ftdf_req_queue; -extern ftdf_queue_t ftdf_freeQueue; -extern ftdf_pending_t ftdf_tx_pending_list[FTDF_NR_OF_REQ_BUFFERS]; -extern ftdf_pending_tl_t ftdf_tx_pending_timer_list[FTDF_NR_OF_REQ_BUFFERS]; -extern ftdf_pending_tl_t *ftdf_tx_pending_timer_head; -extern ftdf_time_t ftdf_tx_pending_timer_lt; -extern ftdf_time_t ftdf_tx_pending_timer_time; -extern ftdf_msg_buffer_t *ftdf_req_current; -extern ftdf_size_t ftdf_nr_of_retries; -extern ftdf_boolean_t ftdf_is_pan_coordinator; -extern ftdf_slotframe_entry_t ftdf_slotframe_table[FTDF_MAX_SLOTFRAMES]; -extern ftdf_link_entry_t ftdf_link_table[FTDF_MAX_LINKS]; -#ifndef FTDF_NO_TSCH -extern ftdf_link_entry_t *ftdf_start_links[FTDF_MAX_SLOTFRAMES]; -extern ftdf_link_entry_t *ftdf_end_links[FTDF_MAX_SLOTFRAMES]; -extern FTDF_NeighborEntry ftdf_neighbor_table[FTDF_NR_OF_NEIGHBORS]; -extern ftdf_boolean_t ftdf_wake_up_enable_tsch; -#endif /* FTDF_NO_TSCH */ -#ifndef FTDF_NO_CSL -extern ftdf_boolean_t ftdf_wake_up_enable_le; -#endif /* FTDF_NO_CSL */ -extern ftdf_lmac_counters_t ftdf_lmac_counters; - -extern ftdf_frame_header_t ftdf_fh; -extern ftdf_security_header ftdf_sh; -extern ftdf_assoc_admin_t ftdf_aa; -extern ftdf_boolean_t ftdf_tx_in_progress; -#ifndef FTDF_NO_CSL -extern ftdf_time_t ftdf_rz_time; -extern ftdf_short_address_t ftdf_send_frame_pending; -#endif /* FTDF_NO_CSL */ -extern ftdf_time_t ftdf_start_csl_sample_time; - -#ifndef FTDF_NO_TSCH -extern ftdf_link_entry_t *ftdf_tsch_slot_link; -extern ftdf_time64_t ftdf_tsch_slot_time; -extern ftdf_asn_t ftdf_tsch_slot_asn; -#endif /* FTDF_NO_TSCH */ - -void ftdf_process_data_request(ftdf_data_request_t *req); -void ftdf_process_purge_request(ftdf_purge_request_t *req); -void ftdf_process_associate_request(ftdf_associate_request_t *req); -void ftdf_process_associate_response(ftdf_associate_response_t *req); -void ftdf_process_disassociate_request(ftdf_disassociate_request_t *req); -void ftdf_process_get_request(ftdf_get_request_t *req); -void ftdf_process_set_request(ftdf_set_request_t *req); -void ftdf_process_orphan_response(ftdf_orphan_response_t *req); -void ftdf_process_reset_request(ftdf_reset_request_t *req); -void ftdf_process_rx_enable_request(ftdf_rx_enable_request_t *req); -void ftdf_process_scan_request(ftdf_scan_request_t *req); -void ftdf_process_start_request(ftdf_start_request_t *req); -void ftdf_process_poll_request(ftdf_poll_request_t *req); -#ifndef FTDF_NO_TSCH -void ftdf_process_set_slotframe_request(ftdf_set_slotframe_request_t *req); -void ftdf_process_set_link_request(ftdf_set_link_request_t *req); -void ftdf_process_tsch_mode_request(ftdf_tsch_mode_request_t *req); -void ftdf_process_keep_alive_request(ftdf_keep_alive_request_t *req); -#endif /* FTDF_NO_TSCH */ -void ftdf_process_beacon_request(ftdf_beacon_request_t *req); -void ftdf_process_transparent_request(ftdf_transparent_request_t *req); -void ftdf_process_remote_request(ftdf_remote_request_t *req); - -void ftdf_process_next_request(void); -void ftdf_process_rx_event(void); -void ftdf_process_tx_event(void); -void ftdf_process_symbol_timer_event(void); - -void ftdf_send_data_confirm(ftdf_data_request_t *data_request, - ftdf_status_t status, - ftdf_time_t timestamp, - ftdf_sn_t dsn, - ftdf_num_of_backoffs_t num_of_backoffs, - ftdf_ie_list_t *ack_payload); - -void ftdf_send_data_indication(ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header, - ftdf_ie_list_t *payload_ie_list, - ftdf_data_length_t msdu_length, - ftdf_octet_t *msdu, - ftdf_link_quality_t mpdu_link_quality, - ftdf_time_t timestamp); - -void ftdf_send_poll_confirm(ftdf_poll_request_t *poll_request, ftdf_status_t status); - -void ftdf_send_scan_confirm(ftdf_scan_request_t *scan_request, ftdf_status_t status); - -void ftdf_send_beacon_notify_indication(ftdf_pan_descriptor_t *pan_descriptor); - -void ftdf_send_beacon_confirm(ftdf_beacon_request_t *beacon_request, ftdf_status_t status); - -void ftdf_send_associate_confirm(ftdf_associate_request_t *associate_request, - ftdf_status_t status, - ftdf_short_address_t assoc_short_addr); - -void ftdf_send_associate_data_request(void); - -void ftdf_send_disassociate_confirm(ftdf_disassociate_request_t *dis_req, ftdf_status_t status); - -void ftdf_send_sync_loss_indication(ftdf_loss_reason_t loss_reason, ftdf_security_header *security_header); - -void ftdf_sendpan_id_conflict_notification(ftdf_frame_header_t *frame_header, ftdf_security_header *security_header); - -void ftdf_send_comm_status_indication(ftdf_msg_buffer_t *request, - ftdf_status_t status, - ftdf_pan_id_t pan_Id, - ftdf_address_mode_t src_addr_mode, - ftdf_address_t src_addr, - ftdf_address_mode_t dst_addr_mode, - ftdf_address_t dst_addr, - ftdf_security_level_t security_level, - ftdf_key_id_mode_t key_id_mode, - ftdf_octet_t *key_source, - ftdf_key_index_t key_index); - -void ftdf_start_timer(ftdf_period_t period, void (* timer_func)(void *params), void *params); - -ftdf_octet_t *ftdf_get_tx_buf_ptr(ftdf_buffer_t *tx_buffer); - -void ftdf_set_tx_meta_data(ftdf_buffer_t *tx_buffer, - ftdf_data_length_t frame_length, - ftdf_channel_number_t channel, - ftdf_frame_type_t frame_type, - ftdf_boolean_t ack_tx, - ftdf_sn_t sn); - -ftdf_status_t ftdf_send_frame(ftdf_channel_number_t channel, - ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header, - ftdf_octet_t *tx_ptr, - ftdf_data_length_t payload_size, - ftdf_octet_t *payload); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -ftdf_status_t ftdf_send_ack_frame(ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header, - ftdf_octet_t *tx_ptr); -#endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - -void ftdf_send_transparent_frame(ftdf_data_length_t frame_length, - ftdf_octet_t *frame, - ftdf_channel_number_t channel, - ftdf_pti_t pti, - ftdf_boolean_t cmsa_suppress); - -ftdf_octet_t *ftdf_get_rx_buffer(void); - -void ftdf_process_rx_event(void); - -ftdf_octet_t *ftdf_add_frame_header(ftdf_octet_t *tx_ptr, - ftdf_frame_header_t *frame_header, - ftdf_data_length_t msdu_length); - -ftdf_octet_t *ftdf_get_frame_header(ftdf_octet_t *rx_ptr, ftdf_frame_header_t *frame_header); - -ftdf_data_length_t ftdf_get_mic_length(ftdf_security_level_t security_level); - -ftdf_octet_t *ftdf_get_security_header(ftdf_octet_t *rx_ptr, - uint8_t frame_version, - ftdf_security_header *security_header); - -ftdf_octet_t *ftdf_add_security_header(ftdf_octet_t *tx_ptr, - ftdf_security_header *security_header); - -ftdf_status_t ftdf_secure_frame(ftdf_octet_t *buf_ptr, - ftdf_octet_t *priv_ptr, - ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header); - -ftdf_status_t ftdf_unsecure_frame(ftdf_octet_t *buf_ptr, - ftdf_octet_t *priv_ptr, - ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header); - -ftdf_key_descriptor_t *ftdf_lookup_key(ftdf_address_mode_t dev_addr_mode, - ftdf_pan_id_t dev_pan_id, - ftdf_address_t dev_addr, - ftdf_frame_type_t frame_type, - ftdf_key_id_mode_t key_id_mode, - ftdf_key_index_t key_index, - ftdf_octet_t *key_source); - -ftdf_device_descriptor_t *ftdf_lookup_device(ftdf_size_t nr_of_device_descriptor_handles, - ftdf_device_descriptor_handle_t *device_descriptor_handles, - ftdf_address_mode_t dev_addr_mode, - ftdf_pan_id_t dev_pan_id, - ftdf_address_t dev_addr); - -ftdf_security_level_descriptor_t *ftdf_get_security_level_descr(ftdf_frame_type_t frame_type, - ftdf_command_frame_id_t command_frame_id); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -ftdf_octet_t *ftdf_add_ies(ftdf_octet_t *tx_ptr, - ftdf_ie_list_t *header_ie_list, - ftdf_ie_list_t *payload_ie_list, - ftdf_boolean_t with_termination_ie); - -ftdf_octet_t *ftdf_get_ies(ftdf_octet_t *rx_ptr, - ftdf_octet_t *frame_end_ptr, - ftdf_ie_list_t **header_ie_list, - ftdf_ie_list_t **payload_ie_list); -#endif /* !FTDF_NO_CSL || !FTDF_NO_TSCH */ - -#ifndef FTDF_NO_CSL -void ftdf_set_peer_csl_timing(ftdf_ie_list_t *header_ie_list, ftdf_time_t timeStamp); -void ftdf_set_csl_sample_time(void); -void ftdf_get_wakeup_params(ftdf_short_address_t dst_addr, - ftdf_time_t *wakeup_start_time, - ftdf_period_t *wakeup_period); -#endif /* FTDF_NO_CSL */ - -void ftdf_get_ext_address(void); -void ftdf_set_ext_address(void); -void ftdf_get_ack_wait_duration(void); -void ftdf_get_enh_ack_wait_duration(void); -void ftdf_set_enh_ack_wait_duration(void); -void ftdf_get_implicit_broadcast(void); -void ftdf_set_implicit_broadcast(void); -void ftdf_set_short_address(void); -void ftdf_set_simple_address(void); -void ftdf_get_rx_on_when_idle(void); -void ftdf_set_rx_on_when_idle(void); -void ftdf_getpan_id(void); -void ftdf_setpan_id(void); -void ftdf_get_current_channel(void); -void ftdf_set_current_channel(void); -void FTDF_setTXPower( void ); -void ftdf_get_max_frame_total_wait_time(void); -void ftdf_set_max_frame_total_wait_time(void); -#ifndef FTDF_NO_CSL -void ftdf_set_le_enabled(void); -void ftdf_get_csl_frame_pending_wait(void); -void ftdf_set_csl_frame_pending_wait(void); -#endif /* FTDF_NO_CSL */ -void ftdf_get_lmac_pm_data(void); -void ftdf_get_lmac_traffic_counters(void); -void ftdf_set_max_csma_backoffs(void); -void ftdf_set_max_be(void); -void ftdf_set_min_be(void); -void ftdf_get_keep_phy_enabled(void); -void ftdf_set_keep_phy_enabled(void); -void ftdf_set_bo_irq_threshold(void); -void ftdf_get_bo_irq_threshold(void); -void ftdf_set_pti_config(void); - -#ifndef FTDF_NO_TSCH -void ftdf_set_timeslot_template(void); -#endif /* FTDF_NO_TSCH */ - -void ftdf_init_lmac(void); -void ftdf_init_queues(void); -void ftdf_init_queue(ftdf_queue_t *queue); -void ftdf_queue_buffer_head(ftdf_buffer_t *buffer, ftdf_queue_t *queue); -ftdf_status_t ftdf_queue_req_head(ftdf_msg_buffer_t *request, ftdf_queue_t *queue); -ftdf_buffer_t *ftdf_dequeue_buffer_tail(ftdf_queue_t *queue); -ftdf_msg_buffer_t *ftdf_dequeue_req_tail(ftdf_queue_t *queue); -ftdf_msg_buffer_t *ftdf_dequeue_by_handle(ftdf_handle_t handle, ftdf_queue_t *queue); -ftdf_buffer_t *ftdf_dequeue_by_buffer(ftdf_buffer_t *buffer, ftdf_queue_t *queue); -ftdf_boolean_t ftdf_is_queue_empty(ftdf_queue_t *queue); - -void ftdf_add_tx_pending_timer(ftdf_msg_buffer_t *request, - uint8_t pend_list_nr, - ftdf_time_t delta, - void (* func)(ftdf_pending_tl_t*)); - -void ftdf_remove_tx_pending_timer(ftdf_msg_buffer_t *request); -void ftdf_restore_tx_pending_timer(void); -ftdf_boolean_t ftdf_get_tx_pending_timer_head(ftdf_time_t *time); -void ftdf_send_transaction_expired(ftdf_pending_tl_t *ptr); -#ifndef FTDF_NO_TSCH -void ftdf_process_keep_alive_timer_exp(ftdf_pending_tl_t *ptr); -void ftdf_reset_keep_alive_timer(ftdf_short_address_t dst_addr); -#endif /* FTDF_NO_TSCH */ - -void ftdf_process_tx_pending(ftdf_frame_header_t *frame_hader, ftdf_security_header *security_header); - -void ftdf_process_command_frame(ftdf_octet_t *rx_buffer, - ftdf_frame_header_t *frame_header, - ftdf_security_header *security_header, - ftdf_ie_list_t *payload_ie_list); - -void ftdf_scan_ready(ftdf_scan_request_t*); -void ftdf_add_pan_descriptor(ftdf_pan_descriptor_t*); -void ftdf_send_beacon_request(ftdf_channel_number_t channel); -void ftdf_send_beacon_request_indication(ftdf_frame_header_t *frame_header, ftdf_ie_list_t *payload_ie_list); -void ftdf_send_orphan_notification(ftdf_channel_number_t channel); - -#ifndef FTDF_NO_TSCH -void ftdf_set_tsch_enabled(void); -ftdf_status_t ftdf_schedule_tsch(ftdf_msg_buffer_t *request); -void ftdf_tsch_process_request(void); -ftdf_size_t ftdf_get_tsch_sync_sub_ie(void); -ftdf_octet_t *ftdf_add_tsch_sync_sub_ie(ftdf_octet_t *tx_ptr); -ftdf_short_address_t ftdf_get_request_address(ftdf_msg_buffer_t *request); -ftdf_msg_buffer_t *ftdf_tsch_get_pending(ftdf_msg_buffer_t *request); -ftdf_octet_t *ftdf_add_corr_time_ie(ftdf_octet_t *tx_ptr, ftdf_time_t rx_timestamp); -void ftdf_correct_slot_time(ftdf_time_t rx_timestamp); -void ftdf_correct_slot_time_from_ack(ftdf_ie_list_t *header_ie_list); -void ftdf_init_tsch_retries(void); -ftdf_tsch_retry_t *ftdf_get_tsch_retry(ftdf_short_address_t node_addr); -ftdf_num_of_backoffs_t ftdf_get_num_of_backoffs(ftdf_be_exponent_t be); -void ftdf_init_backoff(void); -ftdf_sn_t ftdf_process_tsch_sn(ftdf_msg_buffer_t *msg, ftdf_sn_t sn, uint8_t *priv); -#endif /* FTDF_NO_TSCH */ - -ftdf_time64_t ftdf_get_cur_time64(void); -void ftdf_init_cur_time64(void); - -#if FTDF_USE_SLEEP_DURING_BACKOFF -typedef enum -{ - FTDF_SDB_STATE_INIT = 0, - FTDF_SDB_STATE_BACKING_OFF, - FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ, - FTDF_SDB_STATE_RESUMING, -} ftdf_sdb_state_t; - -typedef struct -{ - ftdf_sdb_state_t state; - ftdf_size_t nr_of_backoffs; - ftdf_time_t cca_retry_time; - ftdf_octet_t buffer[FTDF_BUFFER_LENGTH]; - uint32_t metadata_0; - uint32_t metadata_1; - uint32_t phy_csma_ca_attr; -} ftdf_sdb_t; - -void ftdf_sdb_fsm_reset(void); - -void ftdf_sdb_fsm_backoff_irq(void); - -void ftdf_sdb_fsm_sleep(void); - -void ftdf_sdb_fsm_abort_sleep(void); - -void ftdf_sdb_fsm_wake_up_irq(void); - -void ftdf_sdb_fsm_wake_up(void); - -void ftdf_sdb_fsm_tx_irq(void); - -ftdf_usec_t ftdf_sdb_get_sleep_time(void); - -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - -static inline void ftdf_set_link_quality_mode(void) -{ -#ifdef FTDF_PIB_LINK_QUALITY_MODE - REG_SETF(FTDF, FTDF_LMAC_CONTROL_1_REG, PHYRXATTR_DEM_PTI, - (ftdf_pib.link_quality_mode == FTDF_LINK_QUALITY_MODE_RSSI) ? 0x8 : 0); - - REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_SCALE, 0); - - if (ftdf_pib.link_quality_mode == FTDF_LINK_QUALITY_MODE_RSSI) { - REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_PREAMBLE_EN, 0); - REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_CORRTH_EN, 1); - } else { - REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_PREAMBLE_EN, 1); - REG_SETF(DEM, RF_FTDF_CTRL4_REG, LQI_CORRTH_EN, 0); - } - -#endif -} - -#if dg_configUSE_FTDF_DDPHY == 1 - -void ftdf_ddphy_restore(void); - -void ftdf_ddphy_save(void); - -#endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c deleted file mode 100644 index 35a7f66a4..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c +++ /dev/null @@ -1,292 +0,0 @@ -/** - **************************************************************************************** - * - * @file main.c - * - * @brief Main FTDF functions - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - **************************************************************************************** - */ - -#include -#include - -#include "internal.h" -#include "ftdfInfo.h" - -void ftdf_get_release_info(char **lmac_rel_name, char **lmac_build_time, char **umac_rel_name, - char **umac_build_time) -{ - static char lrel_name[16]; - static char lbld_time[16]; - static char urel_name[16]; - static char ubld_time[16]; - uint8_t i; - - volatile uint32_t *ptr = &FTDF->FTDF_REL_NAME_0_REG; - uint32_t *chr_ptr = (uint32_t*)lrel_name; - - for (i = 0; i < 4; i++) { - *chr_ptr++ = *ptr++; - } - - ptr = &FTDF->FTDF_BUILDTIME_0_REG; - chr_ptr = (uint32_t*)lbld_time; - - for (i = 0; i < 4; i++) { - *chr_ptr++ = *ptr++; - } - - const char* umac_v_ptr = ftdf_get_umac_rel_name(); - - for (i = 0; i < 16; i++) { - urel_name[i] = umac_v_ptr[i]; - - if (umac_v_ptr[i] == '\0') { - break; - } - } - - umac_v_ptr = ftdf_get_umac_build_time(); - - for (i = 0; i < 16; i++) { - ubld_time[i] = umac_v_ptr[i]; - - if (umac_v_ptr[i] == '\0') { - break; - } - } - - lrel_name[15] = '\0'; - lbld_time[15] = '\0'; - urel_name[15] = '\0'; - ubld_time[15] = '\0'; - - *lmac_rel_name = lrel_name; - *lmac_build_time = lbld_time; - *umac_rel_name = urel_name; - *umac_build_time = ubld_time; -} - -void ftdf_confirm_lmac_interrupt(void) -{ - REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM, 0); -} - -void ftdf_event_handler(void) -{ - volatile uint32_t ftdf_ce = FTDF->FTDF_FTDF_CE_REG; - - if (ftdf_ce & FTDF_MSK_RX_CE) { - ftdf_process_rx_event(); - } - - if (ftdf_ce & FTDF_MSK_TX_CE) { - ftdf_process_tx_event(); - } - - if (ftdf_ce & FTDF_MSK_SYMBOL_TMR_CE) { - ftdf_process_symbol_timer_event(); - } - -#ifndef FTDF_LITE -#ifndef FTDF_NO_CSL - if (ftdf_pib.le_enabled) { - ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, - SYMBOLTIMESNAPSHOTVAL); - - ftdf_time_t delta = cur_time - ftdf_rz_time; - - if (delta < 0x80000000) { - /* RZ has passed check if a send frame is pending */ - if (ftdf_send_frame_pending != 0xfffe) { - ftdf_time_t wakeup_start_time; - ftdf_period_t wakeup_period; - - ftdf_critical_var(); - ftdf_enter_critical(); - - ftdf_get_wakeup_params(ftdf_send_frame_pending, &wakeup_start_time, - &wakeup_period); - - ftdf_tx_in_progress = FTDF_TRUE; - REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME, - wakeup_start_time); - REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACWUPERIOD, wakeup_period); - - REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET, - ((1 << FTDF_TX_DATA_BUFFER) | - (1 << FTDF_TX_WAKEUP_BUFFER))); - - ftdf_send_frame_pending = 0xfffe; - - ftdf_exit_critical(); - } - - if (ftdf_tx_in_progress == FTDF_FALSE) { - ftdf_set_csl_sample_time(); - } - } - } -#endif /* FTDF_NO_CSL */ -#endif /* !FTDF_LITE */ - REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM, - (FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE)); -} - -#ifndef FTDF_PHY_API -void ftdf_snd_msg(ftdf_msg_buffer_t* msg_buf) -{ - switch (msg_buf->msg_id) { -#ifndef FTDF_LITE - case FTDF_DATA_REQUEST: - ftdf_process_data_request((ftdf_data_request_t*)msg_buf); - break; - case FTDF_PURGE_REQUEST: - ftdf_process_purge_request((ftdf_purge_request_t*)msg_buf); - break; - case FTDF_ASSOCIATE_REQUEST: - ftdf_process_associate_request((ftdf_associate_request_t*)msg_buf); - break; - case FTDF_ASSOCIATE_RESPONSE: - ftdf_process_associate_response((ftdf_associate_response_t*)msg_buf); - break; - case FTDF_DISASSOCIATE_REQUEST: - ftdf_process_disassociate_request((ftdf_disassociate_request_t*)msg_buf); - break; -#endif /* !FTDF_LITE */ - case FTDF_GET_REQUEST: - ftdf_process_get_request((ftdf_get_request_t*)msg_buf); - break; - case FTDF_SET_REQUEST: - ftdf_process_set_request((ftdf_set_request_t*)msg_buf); - break; -#ifndef FTDF_LITE - case FTDF_ORPHAN_RESPONSE: - ftdf_process_orphan_response((ftdf_orphan_response_t*)msg_buf); - break; -#endif /* !FTDF_LITE */ - case FTDF_RESET_REQUEST: - ftdf_process_reset_request((ftdf_reset_request_t*)msg_buf); - break; - case FTDF_RX_ENABLE_REQUEST: - ftdf_process_rx_enable_request((ftdf_rx_enable_request_t*)msg_buf); - break; -#ifndef FTDF_LITE - case FTDF_SCAN_REQUEST: - ftdf_process_scan_request((ftdf_scan_request_t*)msg_buf); - break; - case FTDF_START_REQUEST: - ftdf_process_start_request((ftdf_start_request_t*)msg_buf); - break; - case FTDF_POLL_REQUEST: - ftdf_process_poll_request((ftdf_poll_request_t*)msg_buf); - break; -#ifndef FTDF_NO_TSCH - case FTDF_SET_SLOTFRAME_REQUEST: - ftdf_process_set_slotframe_request((ftdf_set_slotframe_request_t*)msg_buf); - break; - case FTDF_SET_LINK_REQUEST: - ftdf_process_set_link_request((ftdf_set_link_request_t*)msg_buf); - break; - case FTDF_TSCH_MODE_REQUEST: - ftdf_process_tsch_mode_request((ftdf_tsch_mode_request_t*)msg_buf); - break; - case FTDF_KEEP_ALIVE_REQUEST: - ftdf_process_keep_alive_request((ftdf_keep_alive_request_t*)msg_buf); - break; -#endif /* FTDF_NO_TSCH */ - case FTDF_BEACON_REQUEST: - ftdf_process_beacon_request((ftdf_beacon_request_t*)msg_buf); - break; -#endif /* !FTDF_LITE */ - case FTDF_TRANSPARENT_ENABLE_REQUEST: - ftdf_enable_transparent_mode(((ftdf_transparent_enable_request_t*)msg_buf)->enable, - ((ftdf_transparent_enable_request_t*)msg_buf)->options); - FTDF_REL_MSG_BUFFER(msg_buf); - break; - case FTDF_TRANSPARENT_REQUEST: - ftdf_process_transparent_request((ftdf_transparent_request_t*)msg_buf); - break; - case FTDF_SLEEP_REQUEST: - FTDF_SLEEP_CALLBACK(((ftdf_sleep_request_t*)msg_buf)->sleep_time); - FTDF_REL_MSG_BUFFER(msg_buf); - break; -#ifndef FTDF_LITE - case FTDF_REMOTE_REQUEST: - ftdf_process_remote_request((ftdf_remote_request_t*)msg_buf); - break; -#endif /* !FTDF_LITE */ -#if FTDF_DBG_BUS_ENABLE - case FTDF_DBG_MODE_SET_REQUEST: - ftdf_set_dbg_mode(((ftdf_dbg_mode_set_request_t *) msg_buf)->dbg_mode); - FTDF_REL_MSG_BUFFER(msg_buf); - break; -#endif /* FTDF_DBG_BUS_ENABLE */ - case FTDF_FPPR_MODE_SET_REQUEST: - ftdf_fppr_set_mode(((ftdf_fppr_mode_set_request_t *) msg_buf)->match_fp, - ((ftdf_fppr_mode_set_request_t *) msg_buf)->fp_override, - ((ftdf_fppr_mode_set_request_t *) msg_buf)->fp_force); - FTDF_REL_MSG_BUFFER(msg_buf); - break; - default: - // Silenty release the message buffer - FTDF_REL_MSG_BUFFER(msg_buf); - break; - } -} - -void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status) -{ - ftdf_transparent_confirm_t* confirm = - (ftdf_transparent_confirm_t*) FTDF_GET_MSG_BUFFER( - sizeof(ftdf_transparent_confirm_t)); - - confirm->msg_id = FTDF_TRANSPARENT_CONFIRM; - confirm->handle = handle; - confirm->status = status; - - FTDF_RCV_MSG((ftdf_msg_buffer_t*)confirm); -} - -void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length, ftdf_octet_t *frame, - ftdf_bitmap32_t status, ftdf_link_quality_t link_quality) -{ - ftdf_transparent_indication_t *indication = - (ftdf_transparent_indication_t*) FTDF_GET_MSG_BUFFER( - sizeof(ftdf_transparent_indication_t)); - - indication->msg_id = FTDF_TRANSPARENT_INDICATION; - indication->frame_length = frame_length; - indication->status = status; - indication->frame = FTDF_GET_DATA_BUFFER(frame_length); - memcpy(indication->frame, frame, frame_length); - - FTDF_RCV_MSG((ftdf_msg_buffer_t*)indication); -} -#endif /* !FTDF_PHY_API */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c deleted file mode 100644 index 4a70afdab..000000000 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c +++ /dev/null @@ -1,327 +0,0 @@ -/** - **************************************************************************************** - * - * @file power.c - * - * @brief FTDF power on/off functions - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************** - */ - -#include -#include -#include "internal.h" -#include "sdk_defs.h" - -#ifdef CONFIG_USE_FTDF -static ftdf_psec_t ftdf_low_power_clock_cycle __attribute__ ((section(".retention"))); -static ftdf_psec_t ftdf_wake_up_latency __attribute__ ((section(".retention"))); -/* Pre-calculated value for optimization. */ -static ftdf_usec_t ftdf_low_power_clock_cycle_u_sec __attribute__ ((section(".retention"))); -/* Pre-calculated value for optimization. */ -static ftdf_usec_t ftdf_wake_up_latency_u_sec __attribute__ ((section(".retention"))); -/* Pre-calculated value for optimization. */ -static ftdf_nr_low_power_clock_cycles_t ftdf_csmaca_wakeup_thr __attribute__ ((section(".retention"))); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) -static uint32_t ftdf_event_curr_val __attribute__ ((section(".retention"))); -static uint32_t ftdf_time_stamp_curr_val __attribute__ ((section(".retention"))); -static uint32_t ftdf_time_stamp_curr_phase_val __attribute__ ((section(".retention"))); -#endif -#ifndef FTDF_NO_CSL -ftdf_boolean_t ftdf_wake_up_enable_le __attribute__ ((section(".retention"))); -#endif /* FTDF_NO_CSL */ -#ifndef FTDF_NO_TSCH -ftdf_boolean_t ftdf_wake_up_enable_tsch; -#endif /* FTDF_NO_TSCH */ - -void ftdf_set_sleep_attributes(ftdf_psec_t low_power_clock_cycle, - ftdf_nr_low_power_clock_cycles_t wake_up_latency) -{ - ftdf_low_power_clock_cycle = low_power_clock_cycle; - ftdf_wake_up_latency = (ftdf_psec_t)wake_up_latency * low_power_clock_cycle; - ftdf_low_power_clock_cycle_u_sec = ftdf_low_power_clock_cycle / 1000000; - ftdf_wake_up_latency_u_sec = ftdf_wake_up_latency / 1000000; - ftdf_csmaca_wakeup_thr = (ftdf_nr_low_power_clock_cycles_t) - (((ftdf_psec_t) 0xffffffff * 1000000 - ftdf_wake_up_latency) / ftdf_low_power_clock_cycle); -} - -ftdf_usec_t ftdf_can_sleep(void) -{ -#ifdef FTDF_PHY_API - if (ftdf_tx_in_progress || ftdf_pib.keep_phy_enabled) { - return 0; - } -#else -#if FTDF_USE_SLEEP_DURING_BACKOFF - if (ftdf_pib.keep_phy_enabled) -#else - if (ftdf_req_current || ftdf_pib.keep_phy_enabled) -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - { - return 0; - } -#endif -#if FTDF_USE_SLEEP_DURING_BACKOFF - if (REG_GETF(FTDF, FTDF_SECURITY_STATUS_REG, SECBUSY) == 1) -#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ - if ((REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) || - (REG_GETF(FTDF, FTDF_SECURITY_STATUS_REG, SECBUSY) == 1)) -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - { - - return 0; - } - -#ifndef FTDF_NO_CSL - if (ftdf_pib.le_enabled) { -#if FTDF_USE_SLEEP_DURING_BACKOFF - /* Abort sleep when LMAC is busy. */ - if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) { - return 0; - } -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - if (ftdf_tx_in_progress == FTDF_FALSE) { - ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, - SYMBOLTIMESNAPSHOTVAL); - ftdf_time_t delta = cur_time - ftdf_start_csl_sample_time; - - /* A delta larger than 0x80000000 is assumed to be negative */ - /* Do not return a sleep value when CSL sample time is in the past */ - if (delta < 0x80000000) { - return 0; - } - - return (ftdf_start_csl_sample_time - cur_time) * 16; - } else { - return 0; - } - } -#endif /* FTDF_NO_CSL */ - -#ifndef FTDF_NO_TSCH - if (ftdf_pib.tsch_enabled) { -#if FTDF_USE_SLEEP_DURING_BACKOFF - /* Abort sleep when LMAC is busy. */ - if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) { - return 0; - } -#endif - ftdf_time64_t curTime64 = ftdf_get_cur_time64(); - ftdf_time64_t delta = curTime64 - ftdf_tsch_slot_time; - - /* A delta larger than 0x8000000000000000 is assumed to be negative */ - /* Do not return a sleep value when TSCH slot time is in the past */ - if (delta < 0x8000000000000000ULL) { - return 0; - } - - ftdf_usec_t sleep_time = (ftdf_usec_t)(ftdf_tsch_slot_time - curTime64); - - ftdf_time_t pend_list_time; - ftdf_time_t curTime = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL); - ftdf_boolean_t pending = ftdf_get_tx_pending_timer_head(&pend_list_time); - - if (pending) { - /* A delta larger than 0x80000000 is assumed to be negative */ - /* Do not return a sleep value when pending timer time is in the past */ - if (curTime - pend_list_time < 0x80000000) { - return 0; - } - - ftdf_usec_t tmp_sleep_time = (ftdf_usec_t)(pend_list_time - curTime); - - if (tmp_sleep_time < sleep_time) { - sleep_time = tmp_sleep_time; - } - } - - if (sleep_time < FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME) { - return 0; - } - - return (sleep_time - (FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME)) * 16; - } -#endif /* FTDF_NO_TSCH */ - -#ifndef FTDF_LITE - /* Normal mode */ - int n; - - for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) { - if (ftdf_tx_pending_list[n].addr_mode != FTDF_NO_ADDRESS) { - return 0; - } - } -#endif /* !FTDF_LITE */ -#if FTDF_USE_SLEEP_DURING_BACKOFF - return ftdf_sdb_get_sleep_time(); -#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ - return 0xffffffff; -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ -} - -ftdf_boolean_t ftdf_prepare_for_sleep(ftdf_usec_t sleep_time) -{ -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - if (sleep_time < (2 * ftdf_low_power_clock_cycle_u_sec)) { - return FTDF_FALSE; - } - - // Correct sleeptime with the inaccuracy of this function - sleep_time -= (2 * ftdf_low_power_clock_cycle_u_sec); - - if (sleep_time < (ftdf_wake_up_latency_u_sec + 500)) { - return FTDF_FALSE; - } - } - -#endif - - ftdf_critical_var(); - ftdf_enter_critical(); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - /* Capture the current value of both the event generator and the timestamp generator - and phase on the rising edge of LP_CLK */ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, GETGENERATORVAL, 1); - -#endif - /* Save current LMAC PM counters */ - ftdf_lmac_counters.fcs_error_cnt += REG_GETF(FTDF, FTDF_MACFCSERRORCOUNT_REG, MACFCSERRORCOUNT); - ftdf_lmac_counters.tx_std_ack_cnt += REG_GETF(FTDF, FTDF_MACTXSTDACKFRMCNT_REG, MACTXSTDACKFRMCNT); - ftdf_lmac_counters.rx_std_ack_cnt += REG_GETF(FTDF, FTDF_MACRXSTDACKFRMOKCNT_REG, MACRXSTDACKFRMOKCNT); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - - /* Wait until data is ready */ - while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E) == 0) {} - - ftdf_event_curr_val = REG_GETF(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL); - ftdf_time_stamp_curr_val = REG_GETF(FTDF, FTDF_TIMESTAMPCURRVAL_REG, TIMESTAMPCURRVAL); - ftdf_time_stamp_curr_phase_val = REG_GETF(FTDF, FTDF_TIMESTAMPCURRPHASEVAL_REG, TIMESTAMPCURRPHASEVAL); - -#ifdef SIMULATOR - REG_CLR_FIELD(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E, FTDF->FTDF_LMAC_CONTROL_DELTA_REG); -#else - FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E); -#endif - uint64_t next_wake_up_thr; -#if FTDF_USE_SLEEP_DURING_BACKOFF - uint64_t pico_sleep_time = (uint64_t)sleep_time * 1000000; - next_wake_up_thr = ( pico_sleep_time - ftdf_wake_up_latency ) / ftdf_low_power_clock_cycle; -#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ - if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) { - uint64_t picoSleepTime = (uint64_t)sleep_time * 1000000; - next_wake_up_thr = (picoSleepTime - ftdf_wake_up_latency) / ftdf_low_power_clock_cycle; - } else { - next_wake_up_thr = ftdf_csmaca_wakeup_thr; - } -#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ - - /* Set wake up threshold */ - uint32_t wake_up_int_thr = ftdf_event_curr_val + next_wake_up_thr; - /* Note that for IC revs other than A the size of WAKEUPINTTHR is 25 bits. */ - REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPINTTHR, wake_up_int_thr); - REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPENABLE, 1); -#endif - ftdf_exit_critical(); - - return FTDF_TRUE; -} - -void ftdf_wakeup(void) -{ -#ifndef FTDF_PHY_API - ftdf_critical_var(); - ftdf_enter_critical(); - - REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPENABLE, 0); - -#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) - /* Capture the current value of both the event generator and the timestamp generator - and phase on the rising edge of LP_CLK */ - REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, GETGENERATORVAL, 1); - - /* Wait until data is ready */ - while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E) == 0) {} - - uint32_t event_new_curr_val = REG_GETF(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL); - -#ifdef SIMULATOR - REG_CLR_FIELD(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E); -#else - FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E); -#endif - - /* Backward calculate the time slept */ - /* ftdf_psec_t sleep_time = ((uint64_t)(event_new_curr_val - ftdf_event_curr_val) * - ftdf_low_power_clock_cycle) + ftdf_wake_up_latency; */ - - ftdf_psec_t sleep_time; - if (event_new_curr_val >= ftdf_event_curr_val) { /* Check for wraps. */ - sleep_time = (event_new_curr_val - ftdf_event_curr_val) * ftdf_low_power_clock_cycle + - ftdf_wake_up_latency; - } else { - sleep_time = (event_new_curr_val + - (REG_MSK(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL) - ftdf_event_curr_val)) * - ftdf_low_power_clock_cycle + ftdf_wake_up_latency; - } - /* Calculate sync values */ - uint64_t new_sync_vals = ((uint64_t)ftdf_time_stamp_curr_val << 8) | - (ftdf_time_stamp_curr_phase_val & 0xff); - - new_sync_vals += (sleep_time / 62500) + 1; - - uint32_t sync_timestamp_thr = ftdf_event_curr_val + (sleep_time / ftdf_low_power_clock_cycle); - uint32_t sync_timestamp_val = (new_sync_vals & 0xffffffff00) >> 8; - uint32_t sync_timestamp_phase_val = (new_sync_vals & 0xff); - - /* Set values */ - REG_SETF(FTDF, FTDF_SYNCTIMESTAMPTHR_REG, SYNCTIMESTAMPTHR, sync_timestamp_thr); - REG_SETF(FTDF, FTDF_SYNCTIMESTAMPVAL_REG, SYNCTIMESTAMPVAL, sync_timestamp_val); - REG_SETF(FTDF, FTDF_SYNCTIMESTAMPPHASEVAL_REG, SYNCTIMESTAMPPHASEVAL, sync_timestamp_phase_val); - REG_SETF(FTDF, FTDF_TIMER_CONTROL_1_REG, SYNCTIMESTAMPENA, 1); -#endif - - ftdf_exit_critical(); - -#ifndef FTDF_NO_CSL - ftdf_wake_up_enable_le = ftdf_pib.le_enabled; - ftdf_pib.le_enabled = FTDF_FALSE; -#endif /* FTDF_NO_CSL */ - -#ifndef FTDF_NO_TSCH - ftdf_wake_up_enable_tsch = ftdf_pib.tsch_enabled; - ftdf_pib.tsch_enabled = FTDF_FALSE; -#endif /* FTDF_NO_TSCH */ -#endif /* ! FTDF_PHY_API */ - /* Init LMAC */ - ftdf_init_lmac(); -} -#endif /* CONFIG_USE_FTDF */ diff --git a/third_party/dialog/DialogTools/cli_programmer b/third_party/dialog/DialogTools/cli_programmer deleted file mode 100755 index 0db5c2e0c..000000000 Binary files a/third_party/dialog/DialogTools/cli_programmer and /dev/null differ diff --git a/third_party/dialog/DialogTools/imgprep.sh b/third_party/dialog/DialogTools/imgprep.sh deleted file mode 100755 index da2060355..000000000 --- a/third_party/dialog/DialogTools/imgprep.sh +++ /dev/null @@ -1,4 +0,0 @@ -arm-none-eabi-objcopy -O binary ../../../output/da15000/bin/ot-cli-ftd ../../../output/da15000/bin/ot-cli-ftd.bin - - - diff --git a/third_party/dialog/README.md b/third_party/dialog/README.md deleted file mode 100644 index 1fbfc6415..000000000 --- a/third_party/dialog/README.md +++ /dev/null @@ -1,17 +0,0 @@ -URL: http://www.dialog-semiconductor.com/openthread-sandbox-development-kit - -Version: TO BE UPDATED! - - -License: BSD3 - - -Description: - -DialogSDK - contain board support package and radio interface used for build - -DialogTools - contain flash tools - imgprep.sh - prepare image from generated binary using bin2image tool - cli_programmer and uartboot - utilities for loading image into the platform - -Look into examples/platform/da15000/README.am for DialogTools usage description.