espressif/openthread
1
0
Fork 0
mirror of https://github.com/espressif/openthread.git synced 2026-09-09 10:40:09 +00:00
Code Issues Packages Projects Releases Wiki Activity

Support AutoPend for CC2538 (#562)

Browse Source
This commit is contained in:
rongli
2016-09-23 11:12:53 -07:00
committed by Jonathan Hui
parent 4742419be6
commit add8639049
13 changed files with 853 additions and 127 deletions
Download Patch File Download Diff File Expand all files Collapse all files
examples/platforms/cc2538/cc2538-reg.h
+129 -112
View File
@@ -37,151 +37,168 @@
#include <stdint.h>
#define HWREG(x) (*((volatile uint32_t *)(x)))
#define HWREG(x) (*((volatile uint32_t *)(x)))
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
#define INT_UART0 21 // UART0 Rx and Tx
#define RFCORE_XREG_SRCMATCH_EN 0x00000001 // SRCMATCH.SRC_MATCH_EN(1)
#define RFCORE_XREG_SRCMATCH_AUTOPEND 0x00000002 // SRCMATCH.AUTOPEND(1)
#define RFCORE_XREG_SRCMATCH_PEND_DATAREQ_ONLY 0x00000004 // SRCMATCH.PEND_DATAREQ_ONLY(1)
#define IEEE_EUI64 0x00280028 // Address of IEEE EUI-64 address
#define RFCORE_XREG_SRCMATCH_ENABLE_STATUS_SIZE 3 // Num of register for source match enable status
#define RFCORE_XREG_SRCMATCH_SHORT_ENTRIES 24 // 24 short address entries in maximum
#define RFCORE_XREG_SRCMATCH_EXT_ENTRIES 12 // 12 extended address entries in maximum
#define RFCORE_XREG_SRCMATCH_SHORT_ENTRY_OFFSET 4 // address offset for one short address entry
#define RFCORE_XREG_SRCMATCH_EXT_ENTRY_OFFSET 8 // address offset for one extended address entry
#define RFCORE_FFSM_EXT_ADDR0 0x400885A8 // Local address information
#define RFCORE_FFSM_PAN_ID0 0x400885C8 // Local address information
#define RFCORE_FFSM_PAN_ID1 0x400885CC // Local address information
#define RFCORE_FFSM_SHORT_ADDR0 0x400885D0 // Local address information
#define RFCORE_FFSM_SHORT_ADDR1 0x400885D4 // Local address information
#define RFCORE_XREG_FRMFILT0 0x40088600 // The frame filtering function
#define RFCORE_XREG_SRCMATCH 0x40088608 // Source address matching and pending bits
#define RFCORE_XREG_FRMCTRL0 0x40088624 // Frame handling
#define RFCORE_XREG_FRMCTRL1 0x40088628 // Frame handling
#define RFCORE_XREG_RXENABLE 0x4008862C // RX enabling
#define RFCORE_XREG_FREQCTRL 0x4008863C // Controls the RF frequency
#define RFCORE_XREG_FSMSTAT1 0x4008864C // Radio status register
#define RFCORE_XREG_FIFOPCTRL 0x40088650 // FIFOP threshold
#define RFCORE_XREG_CCACTRL0 0x40088658 // CCA threshold
#define RFCORE_XREG_RSSISTAT 0x40088664 // RSSI valid status register
#define RFCORE_XREG_AGCCTRL1 0x400886C8 // AGC reference level
#define RFCORE_XREG_TXFILTCFG 0x400887E8 // TX filter configuration
#define RFCORE_XREG_RFRND 0x4008869C // Random data
#define RFCORE_SFR_RFDATA 0x40088828 // The TX FIFO and RX FIFO
#define RFCORE_SFR_RFERRF 0x4008882C // RF error interrupt flags
#define RFCORE_SFR_RFIRQF0 0x40088834 // RF interrupt flags
#define RFCORE_SFR_RFST 0x40088838 // RF CSMA-CA/strobe processor
#define INT_UART0 21 // UART0 Rx and Tx
#define RFCORE_XREG_FRMFILT0_FRAME_FILTER_EN 0x00000001 // Enables frame filtering
#define IEEE_EUI64 0x00280028 // Address of IEEE EUI-64 address
#define RFCORE_XREG_FRMCTRL0_AUTOACK 0x00000020
#define RFCORE_XREG_FRMCTRL0_AUTOCRC 0x00000040
#define RFCORE_XREG_FRMCTRL0_INFINITY_RX 0x00000008
#define RFCORE_FFSM_SRCADDRESS_TABLE 0x40088400 // Source Address Table
#define RFCORE_XREG_FRMCTRL1_PENDING_OR 0x00000004
#define RFCORE_FFSM_SRCEXTPENDEN0 0x4008858C // Enable/Disable automatic pending per extended address
#define RFCORE_FFSM_SRCSHORTPENDEN0 0x4008859C // Enable/Disable automatic pending per short address
#define RFCORE_FFSM_EXT_ADDR0 0x400885A8 // Local address information
#define RFCORE_FFSM_PAN_ID0 0x400885C8 // Local address information
#define RFCORE_FFSM_PAN_ID1 0x400885CC // Local address information
#define RFCORE_FFSM_SHORT_ADDR0 0x400885D0 // Local address information
#define RFCORE_FFSM_SHORT_ADDR1 0x400885D4 // Local address information
#define RFCORE_XREG_FRMFILT0 0x40088600 // The frame filtering function
#define RFCORE_XREG_SRCMATCH 0x40088608 // Source address matching and pending bits
#define RFCORE_XREG_SRCSHORTEN0 0x4008860C // Short address matching
#define RFCORE_XREG_SRCEXTEN0 0x40088618 // Extended address matching
#define RFCORE_XREG_RFRND_IRND 0x00000001
#define RFCORE_XREG_FRMCTRL0 0x40088624 // Frame handling
#define RFCORE_XREG_FRMCTRL1 0x40088628 // Frame handling
#define RFCORE_XREG_RXENABLE 0x4008862C // RX enabling
#define RFCORE_XREG_FREQCTRL 0x4008863C // Controls the RF frequency
#define RFCORE_XREG_FSMSTAT1 0x4008864C // Radio status register
#define RFCORE_XREG_FIFOPCTRL 0x40088650 // FIFOP threshold
#define RFCORE_XREG_CCACTRL0 0x40088658 // CCA threshold
#define RFCORE_XREG_RSSISTAT 0x40088664 // RSSI valid status register
#define RFCORE_XREG_AGCCTRL1 0x400886C8 // AGC reference level
#define RFCORE_XREG_TXFILTCFG 0x400887E8 // TX filter configuration
#define RFCORE_XREG_RFRND 0x4008869C // Random data
#define RFCORE_SFR_RFDATA 0x40088828 // The TX FIFO and RX FIFO
#define RFCORE_SFR_RFERRF 0x4008882C // RF error interrupt flags
#define RFCORE_SFR_RFIRQF0 0x40088834 // RF interrupt flags
#define RFCORE_SFR_RFST 0x40088838 // RF CSMA-CA/strobe processor
#define RFCORE_XREG_FSMSTAT1_TX_ACTIVE 0x00000002
#define RFCORE_XREG_FSMSTAT1_CCA 0x00000010 // Clear channel assessment
#define RFCORE_XREG_FSMSTAT1_SFD 0x00000020
#define RFCORE_XREG_FSMSTAT1_FIFOP 0x00000040
#define RFCORE_XREG_FSMSTAT1_FIFO 0x00000080
#define RFCORE_XREG_FRMFILT0_FRAME_FILTER_EN 0x00000001 // Enables frame filtering
#define RFCORE_XREG_RSSISTAT_RSSI_VALID 0x00000001 // RSSI value is valid.
#define RFCORE_XREG_FRMCTRL0_AUTOACK 0x00000020
#define RFCORE_XREG_FRMCTRL0_AUTOCRC 0x00000040
#define RFCORE_XREG_FRMCTRL0_INFINITY_RX 0x00000008
#define RFCORE_SFR_RFERRF_RXOVERF 0x00000004 // RX FIFO overflowed.
#define RFCORE_XREG_FRMCTRL1_PENDING_OR 0x00000004
#define RFCORE_SFR_RFST_INSTR_RXON 0xE3 // Instruction set RX on
#define RFCORE_SFR_RFST_INSTR_TXON 0xE9 // Instruction set TX on
#define RFCORE_SFR_RFST_INSTR_RFOFF 0xEF // Instruction set RF off
#define RFCORE_SFR_RFST_INSTR_FLUSHRX 0xED // Instruction set flush rx buffer
#define RFCORE_SFR_RFST_INSTR_FLUSHTX 0xEE // Instruction set flush tx buffer
#define RFCORE_XREG_RFRND_IRND 0x00000001
#define ANA_REGS_BASE 0x400D6000 // ANA_REGS
#define ANA_REGS_O_IVCTRL 0x00000004 // Analog control register
#define RFCORE_XREG_FSMSTAT1_TX_ACTIVE 0x00000002
#define RFCORE_XREG_FSMSTAT1_CCA 0x00000010 // Clear channel assessment
#define RFCORE_XREG_FSMSTAT1_SFD 0x00000020
#define RFCORE_XREG_FSMSTAT1_FIFOP 0x00000040
#define RFCORE_XREG_FSMSTAT1_FIFO 0x00000080
#define SYS_CTRL_CLOCK_CTRL 0x400D2000 // The clock control register
#define SYS_CTRL_SYSDIV_32MHZ 0x00000000 // Sys_div for sysclk 32MHz
#define SYS_CTRL_CLOCK_CTRL_AMP_DET 0x00200000
#define RFCORE_XREG_RSSISTAT_RSSI_VALID 0x00000001 // RSSI value is valid.
#define SYS_CTRL_PWRDBG 0x400D2074
#define SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008
#define RFCORE_SFR_RFERRF_RXOVERF 0x00000004 // RX FIFO overflowed.
#define SYS_CTRL_RCGCUART 0x400D2028
#define SYS_CTRL_SCGCUART 0x400D202C
#define SYS_CTRL_DCGCUART 0x400D2030
#define SYS_CTRL_I_MAP 0x400D2098
#define SYS_CTRL_RCGCRFC 0x400D20A8
#define SYS_CTRL_SCGCRFC 0x400D20AC
#define SYS_CTRL_DCGCRFC 0x400D20B0
#define SYS_CTRL_EMUOVR 0x400D20B4
#define RFCORE_SFR_RFST_INSTR_RXON 0xE3 // Instruction set RX on
#define RFCORE_SFR_RFST_INSTR_TXON 0xE9 // Instruction set TX on
#define RFCORE_SFR_RFST_INSTR_RFOFF 0xEF // Instruction set RF off
#define RFCORE_SFR_RFST_INSTR_FLUSHRX 0xED // Instruction set flush rx buffer
#define RFCORE_SFR_RFST_INSTR_FLUSHTX 0xEE // Instruction set flush tx buffer
#define SYS_CTRL_RCGCRFC_RFC0 0x00000001
#define SYS_CTRL_SCGCRFC_RFC0 0x00000001
#define SYS_CTRL_DCGCRFC_RFC0 0x00000001
#define ANA_REGS_BASE 0x400D6000 // ANA_REGS
#define ANA_REGS_O_IVCTRL 0x00000004 // Analog control register
#define SYS_CTRL_I_MAP_ALTMAP 0x00000001
#define SYS_CTRL_CLOCK_CTRL 0x400D2000 // The clock control register
#define SYS_CTRL_SYSDIV_32MHZ 0x00000000 // Sys_div for sysclk 32MHz
#define SYS_CTRL_CLOCK_CTRL_AMP_DET 0x00200000
#define SYS_CTRL_RCGCUART_UART0 0x00000001
#define SYS_CTRL_SCGCUART_UART0 0x00000001
#define SYS_CTRL_DCGCUART_UART0 0x00000001
#define SYS_CTRL_PWRDBG 0x400D2074
#define SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008
#define IOC_PA0_SEL 0x400D4000 // Peripheral select control
#define IOC_PA1_SEL 0x400D4004 // Peripheral select control
#define IOC_UARTRXD_UART0 0x400D4100
#define SYS_CTRL_RCGCUART 0x400D2028
#define SYS_CTRL_SCGCUART 0x400D202C
#define SYS_CTRL_DCGCUART 0x400D2030
#define SYS_CTRL_I_MAP 0x400D2098
#define SYS_CTRL_RCGCRFC 0x400D20A8
#define SYS_CTRL_SCGCRFC 0x400D20AC
#define SYS_CTRL_DCGCRFC 0x400D20B0
#define SYS_CTRL_EMUOVR 0x400D20B4
#define IOC_PA0_OVER 0x400D4080
#define IOC_PA1_OVER 0x400D4084
#define SYS_CTRL_RCGCRFC_RFC0 0x00000001
#define SYS_CTRL_SCGCRFC_RFC0 0x00000001
#define SYS_CTRL_DCGCRFC_RFC0 0x00000001
#define IOC_MUX_OUT_SEL_UART0_TXD 0x00000000
#define SYS_CTRL_I_MAP_ALTMAP 0x00000001
#define IOC_OVERRIDE_OE 0x00000008 // PAD Config Override Output Enable
#define IOC_OVERRIDE_DIS 0x00000000 // PAD Config Override Disabled
#define SYS_CTRL_RCGCUART_UART0 0x00000001
#define SYS_CTRL_SCGCUART_UART0 0x00000001
#define SYS_CTRL_DCGCUART_UART0 0x00000001
#define UART0_BASE 0x4000C000
#define GPIO_A_BASE 0x400D9000 // GPIO
#define IOC_PA0_SEL 0x400D4000 // Peripheral select control
#define IOC_PA1_SEL 0x400D4004 // Peripheral select control
#define IOC_UARTRXD_UART0 0x400D4100
#define GPIO_O_DIR 0x00000400
#define GPIO_O_AFSEL 0x00000420
#define IOC_PA0_OVER 0x400D4080
#define IOC_PA1_OVER 0x400D4084
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define IOC_MUX_OUT_SEL_UART0_TXD 0x00000000
#define UART_O_DR 0x00000000 // UART data
#define UART_O_FR 0x00000018 // UART flag
#define UART_O_IBRD 0x00000024
#define UART_O_FBRD 0x00000028
#define UART_O_LCRH 0x0000002C
#define UART_O_CTL 0x00000030 // UART control
#define UART_O_IM 0x00000038 // UART interrupt mask
#define UART_O_MIS 0x00000040 // UART masked interrupt status
#define UART_O_ICR 0x00000044 // UART interrupt clear
#define UART_O_CC 0x00000FC8 // UART clock configuration
#define IOC_OVERRIDE_OE 0x00000008 // PAD Config Override Output Enable
#define IOC_OVERRIDE_DIS 0x00000000 // PAD Config Override Disabled
#define UART_FR_RXFE 0x00000010 // UART receive FIFO empty
#define UART_FR_TXFF 0x00000020 // UART transmit FIFO full
#define UART_FR_RXFF 0x00000040 // UART receive FIFO full
#define UART0_BASE 0x4000C000
#define GPIO_A_BASE 0x400D9000 // GPIO
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define GPIO_O_DIR 0x00000400
#define GPIO_O_AFSEL 0x00000420
#define UART_CTL_UARTEN 0x00000001 // UART enable
#define UART_CTL_TXE 0x00000100 // UART transmit enable
#define UART_CTL_RXE 0x00000200 // UART receive enable
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define UART_IM_RXIM 0x00000010 // UART receive interrupt mask
#define UART_IM_RTIM 0x00000040 // UART receive time-out interrupt
#define UART_O_DR 0x00000000 // UART data
#define UART_O_FR 0x00000018 // UART flag
#define UART_O_IBRD 0x00000024
#define UART_O_FBRD 0x00000028
#define UART_O_LCRH 0x0000002C
#define UART_O_CTL 0x00000030 // UART control
#define UART_O_IM 0x00000038 // UART interrupt mask
#define UART_O_MIS 0x00000040 // UART masked interrupt status
#define UART_O_ICR 0x00000044 // UART interrupt clear
#define UART_O_CC 0x00000FC8 // UART clock configuration
#define SOC_ADC_ADCCON1 0x400D7000 // ADC Control
#define SOC_ADC_RNDL 0x400D7014 // RNG low data
#define SOC_ADC_RNDH 0x400D7018 // RNG high data
#define UART_FR_RXFE 0x00000010 // UART receive FIFO empty
#define UART_FR_TXFF 0x00000020 // UART transmit FIFO full
#define UART_FR_RXFF 0x00000040 // UART receive FIFO full
#define SOC_ADC_ADCCON1_RCTRL0 0x00000004 // ADCCON1 RCTRL bit 0
#define SOC_ADC_ADCCON1_RCTRL1 0x00000008 // ADCCON1 RCTRL bit 1
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CTL_UARTEN 0x00000001 // UART enable
#define UART_CTL_TXE 0x00000100 // UART transmit enable
#define UART_CTL_RXE 0x00000200 // UART receive enable
#define UART_IM_RXIM 0x00000010 // UART receive interrupt mask
#define UART_IM_RTIM 0x00000040 // UART receive time-out interrupt
#define SOC_ADC_ADCCON1 0x400D7000 // ADC Control
#define SOC_ADC_RNDL 0x400D7014 // RNG low data
#define SOC_ADC_RNDH 0x400D7018 // RNG high data
#define SOC_ADC_ADCCON1_RCTRL0 0x00000004 // ADCCON1 RCTRL bit 0
#define SOC_ADC_ADCCON1_RCTRL1 0x00000008 // ADCCON1 RCTRL bit 1
#endif
examples/platforms/cc2538/radio.c
+280 -3
View File
@@ -38,6 +38,7 @@
#include <common/code_utils.hpp>
#include <platform/platform.h>
#include <common/logging.hpp>
#include <platform/radio.h>
#include <platform/diag.h>
#include "platform-cc2538.h"
@@ -193,10 +194,9 @@ void cc2538RadioInit(void)
HWREG(RFCORE_XREG_FIFOPCTRL) = IEEE802154_MAX_LENGTH;
HWREG(RFCORE_XREG_FRMCTRL0) = RFCORE_XREG_FRMCTRL0_AUTOCRC | RFCORE_XREG_FRMCTRL0_AUTOACK;
HWREG(RFCORE_XREG_FRMCTRL1) |= RFCORE_XREG_FRMCTRL1_PENDING_OR;
// disable source address matching
HWREG(RFCORE_XREG_SRCMATCH) = 0;
// default: SRCMATCH.SRC_MATCH_EN(1), SRCMATCH.AUTOPEND(1),
// SRCMATCH.PEND_DATAREQ_ONLY(1), RFCORE_XREG_FRMCTRL1_PENDING_OR(0)
}
ThreadError otPlatRadioEnable(otInstance *aInstance)
@@ -460,3 +460,280 @@ void RFCoreErrIntHandler(void)
{
HWREG(RFCORE_SFR_RFERRF) = 0;
}
uint32_t getSrcMatchEntriesEnableStatus(bool aShort)
{
uint32_t status = 0;
uint32_t *addr = aShort ? (uint32_t *) RFCORE_XREG_SRCSHORTEN0 : (uint32_t *) RFCORE_XREG_SRCEXTEN0;
for (uint8_t i = 0; i < RFCORE_XREG_SRCMATCH_ENABLE_STATUS_SIZE; i++)
{
status |= HWREG(addr++) << (i * 8);
}
return status;
}
int8_t findSrcMatchShortEntry(const uint16_t aShortAddress)
{
int8_t entry = -1;
uint16_t shortAddr;
uint32_t bitMask;
uint32_t *addr = NULL;
uint32_t status = getSrcMatchEntriesEnableStatus(true);
for (uint8_t i = 0; i < RFCORE_XREG_SRCMATCH_SHORT_ENTRIES; i++)
{
bitMask = 0x00000001 << i;
if ((status & bitMask) == 0)
{
continue;
}
addr = (uint32_t *)RFCORE_FFSM_SRCADDRESS_TABLE + (i * RFCORE_XREG_SRCMATCH_SHORT_ENTRY_OFFSET);
shortAddr = HWREG(addr + 2);
shortAddr |= HWREG(addr + 3) << 8;
if ((shortAddr == aShortAddress))
{
ExitNow(entry = i);
}
}
exit:
return entry;
}
int8_t findSrcMatchExtEntry(const uint8_t *aExtAddress)
{
int8_t entry = -1;
uint32_t bitMask;
uint32_t *addr = NULL;
uint32_t status = getSrcMatchEntriesEnableStatus(false);
for (uint8_t i = 0; i < RFCORE_XREG_SRCMATCH_EXT_ENTRIES; i++)
{
uint8_t j = 0;
bitMask = 0x00000001 << 2 * i;
if ((status & bitMask) == 0)
{
continue;
}
addr = (uint32_t *)RFCORE_FFSM_SRCADDRESS_TABLE + (i * RFCORE_XREG_SRCMATCH_EXT_ENTRY_OFFSET);
for (j = 0; j < sizeof(otExtAddress); j++)
{
if (HWREG(addr + j) != aExtAddress[j])
{
break;
}
}
if (j == sizeof(otExtAddress))
{
ExitNow(entry = i);
}
}
exit:
return entry;
}
void setSrcMatchEntryEnableStatus(bool aShort, uint8_t aEntry, bool aEnable)
{
uint8_t entry = aShort ? aEntry : (2 * aEntry);
uint8_t index = entry / 8;
uint32_t *addrEn = aShort ? (uint32_t *)RFCORE_XREG_SRCSHORTEN0 : (uint32_t *)RFCORE_XREG_SRCEXTEN0;
uint32_t *addrAutoPendEn = aShort ? (uint32_t *)RFCORE_FFSM_SRCSHORTPENDEN0 : (uint32_t *)RFCORE_FFSM_SRCEXTPENDEN0;
uint32_t bitMask = 0x00000001;
if (aEnable)
{
HWREG(addrEn + index) |= (bitMask) << (entry % 8);
HWREG(addrAutoPendEn + index) |= (bitMask) << (entry % 8);
}
else
{
HWREG(addrEn + index) &= ~((bitMask) << (entry % 8));
HWREG(addrAutoPendEn + index) &= ~((bitMask) << (entry % 8));
}
}
int8_t findSrcMatchAvailEntry(bool aShort)
{
int8_t entry = -1;
uint32_t bitMask;
uint32_t shortEnableStatus = getSrcMatchEntriesEnableStatus(true);
uint32_t extEnableStatus = getSrcMatchEntriesEnableStatus(false);
otLogDebgMac("Short enable status: 0x%x\n", shortEnableStatus);
otLogDebgMac("Ext enable status: 0x%x\n", extEnableStatus);
if (aShort)
{
bitMask = 0x00000001;
for (uint8_t i = 0; i < RFCORE_XREG_SRCMATCH_SHORT_ENTRIES; i++)
{
if ((extEnableStatus & bitMask) == 0)
{
if ((shortEnableStatus & bitMask) == 0)
{
ExitNow(entry = i);
}
}
if (i % 2 == 1)
{
extEnableStatus = extEnableStatus >> 2;
}
shortEnableStatus = shortEnableStatus >> 1;
}
}
else
{
bitMask = 0x00000003;
for (uint8_t i = 0; i < RFCORE_XREG_SRCMATCH_EXT_ENTRIES; i++)
{
if (((extEnableStatus | shortEnableStatus) & bitMask) == 0)
{
ExitNow(entry = i);
}
extEnableStatus = extEnableStatus >> 2;
shortEnableStatus = shortEnableStatus >> 2;
}
}
exit:
return entry;
}
void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable)
{
(void)aInstance;
if (aEnable)
{
// only set FramePending when ack for data poll if there are queued messages
// for entries in the source match table.
HWREG(RFCORE_XREG_FRMCTRL1) &= ~RFCORE_XREG_FRMCTRL1_PENDING_OR;
}
else
{
// set FramePending for all ack.
HWREG(RFCORE_XREG_FRMCTRL1) |= RFCORE_XREG_FRMCTRL1_PENDING_OR;
}
}
ThreadError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
ThreadError error = kThreadError_None;
int8_t entry = findSrcMatchAvailEntry(true);
uint32_t *addr = (uint32_t *)RFCORE_FFSM_SRCADDRESS_TABLE;
(void)aInstance;
otLogDebgMac("Available short address entry: %d\n", entry);
VerifyOrExit(entry >= 0, error = kThreadError_NoBufs);
addr += (entry * RFCORE_XREG_SRCMATCH_SHORT_ENTRY_OFFSET);
HWREG(addr++) = HWREG(RFCORE_FFSM_PAN_ID0);
HWREG(addr++) = HWREG(RFCORE_FFSM_PAN_ID1);
HWREG(addr++) = aShortAddress & 0xFF;
HWREG(addr++) = aShortAddress >> 8;
setSrcMatchEntryEnableStatus(true, (uint8_t)(entry), true);
exit:
return error;
}
ThreadError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const uint8_t *aExtAddress)
{
ThreadError error = kThreadError_None;
int8_t entry = findSrcMatchAvailEntry(false);
uint32_t *addr = (uint32_t *)RFCORE_FFSM_SRCADDRESS_TABLE;
(void)aInstance;
otLogDebgMac("Available extended address entry: %d\n", entry);
VerifyOrExit(entry >= 0, error = kThreadError_NoBufs);
addr += (entry * RFCORE_XREG_SRCMATCH_EXT_ENTRY_OFFSET);
for (uint8_t i = 0; i < sizeof(otExtAddress); i++)
{
HWREG(addr++) = aExtAddress[i];
}
setSrcMatchEntryEnableStatus(false, (uint8_t)(entry), true);
exit:
return error;
}
ThreadError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
ThreadError error = kThreadError_None;
int8_t entry = findSrcMatchShortEntry(aShortAddress);
(void)aInstance;
otLogDebgMac("Found short address entry: %d\n", entry);
VerifyOrExit(entry >= 0, error = kThreadError_NoAddress);
setSrcMatchEntryEnableStatus(true, (uint8_t)(entry), false);
exit:
return error;
}
ThreadError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const uint8_t *aExtAddress)
{
ThreadError error = kThreadError_None;
int8_t entry = findSrcMatchExtEntry(aExtAddress);
(void)aInstance;
otLogDebgMac("Found ext address entry: %d\n", entry);
VerifyOrExit(entry >= 0, error = kThreadError_NoAddress);
setSrcMatchEntryEnableStatus(false, (uint8_t)(entry), false);
exit:
return error;
}
void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance)
{
uint32_t *addrEn = (uint32_t *)RFCORE_XREG_SRCSHORTEN0;
uint32_t *addrAutoPendEn = (uint32_t *)RFCORE_FFSM_SRCSHORTPENDEN0;
(void)aInstance;
for (uint8_t i = 0; i < RFCORE_XREG_SRCMATCH_ENABLE_STATUS_SIZE; i++)
{
HWREG(addrEn++) = 0;
HWREG(addrAutoPendEn++) = 0;
}
}
void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance)
{
uint32_t *addrEn = (uint32_t *)RFCORE_XREG_SRCEXTEN0;
uint32_t *addrAutoPendEn = (uint32_t *)RFCORE_FFSM_SRCEXTPENDEN0;
(void)aInstance;
for (uint8_t i = 0; i < RFCORE_XREG_SRCMATCH_ENABLE_STATUS_SIZE; i++)
{
HWREG(addrEn++) = 0;
HWREG(addrAutoPendEn++) = 0;
}
}
examples/platforms/posix/radio.c
+43
View File
@@ -682,3 +682,46 @@ exit:
}
}
void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable)
{
(void)aInstance;
(void)aEnable;
}
ThreadError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
(void)aInstance;
(void)aShortAddress;
return kThreadError_None;
}
ThreadError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const uint8_t *aExtAddress)
{
(void)aInstance;
(void)aExtAddress;
return kThreadError_None;
}
ThreadError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
(void)aInstance;
(void)aShortAddress;
return kThreadError_None;
}
ThreadError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const uint8_t *aExtAddress)
{
(void)aInstance;
(void)aExtAddress;
return kThreadError_None;
}
void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance)
{
(void)aInstance;
}
void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance)
{
(void)aInstance;
}